160 lines
3.1 KiB
C
160 lines
3.1 KiB
C
// insert cool lenghty disclaimer here
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// fpga.c: FPGA (re)programming
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// XXX TODO move SPI functions to fpga_spi.c!
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/*
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FPGA pin mapping
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================
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PROG_B PD3 OUT
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CCLK PD4 OUT
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INIT_B PD7 IN
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DIN PC7 OUT
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DONE PA3 IN
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*/
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#include <avr/pgmspace.h>
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#include <util/delay.h>
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#include "fpga.h"
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#include "config.h"
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#include "uart.h"
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#include "sdcard.h"
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#include "diskio.h"
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#include "integer.h"
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#include "ff.h"
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#include "fileops.h"
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#include "fpga_spi.h"
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#include "spi.h"
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#include "avrcompat.h"
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#include "led.h"
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/*DWORD get_fattime(void) {
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return 0L;
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}*/
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void set_prog_b(uint8_t val) {
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if(val) {
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PORTD |= _BV(PD3);
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} else {
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PORTD &= ~_BV(PD3);
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}
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}
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void set_cclk(uint8_t val) {
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if(val) {
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PORTD |= _BV(PD4);
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} else {
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PORTD &= ~_BV(PD4);
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}
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}
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void fpga_init() {
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DDRD &= ~_BV(PD7); // PD7 is input
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DDRC = _BV(PC7); // for FPGA config, PC7 is output
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DDRD |= _BV(PD3) | _BV(PD4); // PD3, PD4 are outputs
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DDRA = ~_BV(PA3); // PA3 is input <- DONE
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DDRB |= _BV(PB2); // DMA_CTRL preinit
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PORTB |= _BV(PB2);
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SPI_OFFLOAD=0;
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set_cclk(0); // initial clk=0
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}
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int fpga_get_done(void) {
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return PINA & _BV(PA3);
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}
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void fpga_postinit() {
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DDRA |= _BV(PA0) | _BV(PA1) | _BV(PA2) | _BV(PA4) | _BV(PA5) | _BV(PA6); // MAPPER+NEXTADDR output
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DDRB |= _BV(PB1) | _BV(PB0); // turn PB2 into output, enable AVR_BANK
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DDRD |= _BV(PD7); // turn PD7 into output
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}
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void fpga_pgm(uint8_t* filename) {
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int MAXRETRIES = 10;
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int retries = MAXRETRIES;
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int j=0;
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do {
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set_prog_b(0);
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uart_putc('P');
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set_prog_b(1);
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loop_until_bit_is_set(PIND, PD7);
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uart_putc('p');
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UINT bytes_read;
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// open configware file
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file_open(filename, FA_READ);
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if(file_res) {
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uart_putc('?');
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uart_putc(0x30+file_res);
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return;
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}
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for (;;) {
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if(!(j++ % 8)) {
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toggle_pwr_led();
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}
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bytes_read = file_read();
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if (file_res || bytes_read == 0) break; // error or eof
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for(int i=0; i<bytes_read; i++) {
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FPGA_SEND_BYTE_SERIAL(file_buf[i]);
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}
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}
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file_close();
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_delay_ms(100);
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} while (!fpga_get_done() && retries--);
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if(!fpga_get_done()) {
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dprintf("FPGA failed to configure after %d tries.\n", MAXRETRIES);
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_delay_ms(50);
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led_panic();
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}
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fpga_postinit();
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}
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void set_avr_ena(uint8_t val) {
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if(val) { // shared mode
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PORTD |= _BV(PD7);
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// Disable SPI double speed mode -> clock = f/4
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SPSR = 0;
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dprintf("SPI slow\n");
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} else { // avr only
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PORTD &= ~_BV(PD7);
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// Enable SPI double speed mode -> clock = f/2
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SPSR = _BV(SPI2X);
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dprintf("SPI fast\n");
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}
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}
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void set_avr_mapper(uint8_t val) {
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SPI_SS_HIGH();
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FPGA_SS_LOW();
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spiTransferByte(0x30 | (val & 0x0f));
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FPGA_SS_HIGH();
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SPI_SS_LOW();
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}
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void set_avr_bank(uint8_t val) {
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SPI_SS_HIGH();
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FPGA_SS_LOW();
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spiTransferByte(0x00); // SET ADDRESS
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spiTransferByte(val * 0x20); // select chip
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spiTransferByte(0x00); // select chip
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spiTransferByte(0x00); // select chip
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FPGA_SS_HIGH();
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SPI_SS_LOW();
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}
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uint8_t fpga_test() {
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spi_fpga();
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spiTransferByte(0xF0); // TEST
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spiTransferByte(0x00); // dummy
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uint8_t result = spiTransferByte(0x00);
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spi_none();
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return result;
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}
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