59 lines
1.6 KiB
Verilog
59 lines
1.6 KiB
Verilog
`timescale 1 ns / 1 ns
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//////////////////////////////////////////////////////////////////////////////////
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// Company: Rehkopf
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// Engineer: Rehkopf
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//
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// Create Date: 01:13:46 05/09/2009
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// Design Name:
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// Module Name: address
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// Project Name:
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// Target Devices:
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// Tool versions:
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// Description: Address logic w/ SaveRAM masking
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//
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// Dependencies:
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//
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// Revision:
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module address(
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input CLK,
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input [23:0] SNES_ADDR, // requested address from SNES
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input SNES_CS, // "CART" pin from SNES (active low)
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output [23:0] ROM_ADDR, // Address to request from SRAM0
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output IS_SAVERAM, // address/CS mapped as SRAM?
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output IS_ROM, // address mapped as ROM?
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input [23:0] SAVERAM_MASK,
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input [23:0] ROM_MASK
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);
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wire [23:0] SRAM_SNES_ADDR;
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/* static mapper:
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menu (ROM in upper SRAM)
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*/
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/* HiROM: SRAM @ Bank 0x30-0x3f, 0xb0-0xbf
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Offset 6000-7fff */
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assign IS_ROM = ((!SNES_ADDR[22] & SNES_ADDR[15])
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|(SNES_ADDR[22]));
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assign IS_SAVERAM = (!SNES_ADDR[22]
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& &SNES_ADDR[21:20]
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& &SNES_ADDR[14:13]
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& !SNES_ADDR[15]
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);
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assign SRAM_SNES_ADDR = (IS_SAVERAM
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? 24'hFF0000 + ((SNES_ADDR[14:0] - 15'h6000)
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& SAVERAM_MASK)
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: (({1'b0, SNES_ADDR[22:0]} & ROM_MASK)
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+ 24'hC00000)
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);
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assign ROM_ADDR = SRAM_SNES_ADDR;
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endmodule
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