Maximilian Rehkopf d1945d08a9 refactoring reminder

2009-09-11 11:10:48 +02:00

pcb

cleanup schematic, edge triggered cycle start detection, debug output cleanup

2009-09-11 11:03:00 +02:00

src

refactoring reminder

2009-09-11 11:10:48 +02:00

verilog/sd2snes

cleanup schematic, edge triggered cycle start detection, debug output cleanup

2009-09-11 11:03:00 +02:00

Description

No description provided

10 MiB

Languages

C 73.7%

Verilog 18.3%

Assembly 5.4%

Makefile 2.3%

Perl 0.1%

Other 0.1%