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sd2snes/verilog
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Maximilian Rehkopf effa2a6972 FPGA/SDDMA: fix clock glitch, adjust RAM write timings
2012-07-09 02:22:07 +02:00
..
sd2snes
FPGA/SDDMA: fix clock glitch, adjust RAM write timings
2012-07-09 02:22:07 +02:00
sd2snes_cx4
FPGA/SDDMA: fix clock glitch, adjust RAM write timings
2012-07-09 02:22:07 +02:00
sd2snes_test
FPGA: add SD clock pullup to test configuration
2012-05-02 10:46:27 +02:00
sd2sneslite
FPGA/SPI: detect end of byte via MSB toggle instead of constant compare of async input
2012-07-09 02:17:01 +02:00
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