146 lines
3.7 KiB
Verilog
146 lines
3.7 KiB
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 19:19:08 12/01/2010
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// Design Name:
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// Module Name: sd_dma
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// Project Name:
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// Target Devices:
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// Tool versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module sd_dma(
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input [3:0] SD_DAT,
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inout SD_CLK,
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input CLK,
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input SD_DMA_EN,
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output SD_DMA_STATUS,
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output SD_DMA_SRAM_WE,
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output SD_DMA_NEXTADDR,
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output [7:0] SD_DMA_SRAM_DATA,
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input SD_DMA_PARTIAL,
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input [10:0] SD_DMA_PARTIAL_START,
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input [10:0] SD_DMA_PARTIAL_END,
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input SD_DMA_START_MID_BLOCK,
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input SD_DMA_END_MID_BLOCK,
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output [10:0] DBG_cyclecnt,
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output [2:0] DBG_clkcnt
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);
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reg [10:0] SD_DMA_STARTr;
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reg [10:0] SD_DMA_ENDr;
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reg SD_DMA_PARTIALr;
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always @(posedge CLK) SD_DMA_PARTIALr <= SD_DMA_PARTIAL;
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reg SD_DMA_DONEr;
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reg[1:0] SD_DMA_DONEr2;
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initial begin
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SD_DMA_DONEr2 = 2'b00;
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SD_DMA_DONEr = 1'b0;
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end
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always @(posedge CLK) SD_DMA_DONEr2 <= {SD_DMA_DONEr2[0], SD_DMA_DONEr};
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wire SD_DMA_DONE_rising = (SD_DMA_DONEr2[1:0] == 2'b01);
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reg [1:0] SD_DMA_ENr;
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initial SD_DMA_ENr = 2'b00;
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always @(posedge CLK) SD_DMA_ENr <= {SD_DMA_ENr[0], SD_DMA_EN};
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wire SD_DMA_EN_rising = (SD_DMA_ENr [1:0] == 2'b01);
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reg SD_DMA_STATUSr;
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assign SD_DMA_STATUS = SD_DMA_STATUSr;
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// we need 1042 cycles (startbit + 1024 nibbles + 16 crc + stopbit)
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reg [10:0] cyclecnt;
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initial cyclecnt = 11'd0;
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reg SD_DMA_SRAM_WEr;
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initial SD_DMA_SRAM_WEr = 1'b1;
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assign SD_DMA_SRAM_WE = (cyclecnt < 1025 && SD_DMA_STATUSr) ? SD_DMA_SRAM_WEr : 1'b1;
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reg SD_DMA_NEXTADDRr;
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assign SD_DMA_NEXTADDR = (cyclecnt < 1025 && SD_DMA_STATUSr) ? SD_DMA_NEXTADDRr : 1'b0;
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reg[7:0] SD_DMA_SRAM_DATAr;
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assign SD_DMA_SRAM_DATA = SD_DMA_SRAM_DATAr;
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// we have 4 internal cycles per SD clock, 8 per RAM byte write
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reg [2:0] clkcnt;
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initial clkcnt = 3'b000;
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reg [1:0] SD_CLKr;
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initial SD_CLKr = 3'b111;
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always @(posedge CLK)
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if(SD_DMA_EN_rising) SD_CLKr <= 3'b111;
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else SD_CLKr <= {SD_CLKr[0], clkcnt[1]};
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assign SD_CLK = SD_DMA_STATUSr ? SD_CLKr[1] : 1'bZ;
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always @(posedge CLK) begin
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if(SD_DMA_EN_rising) begin
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SD_DMA_STATUSr <= 1'b1;
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SD_DMA_STARTr <= (SD_DMA_PARTIALr ? SD_DMA_PARTIAL_START : 11'h0);
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SD_DMA_ENDr <= (SD_DMA_PARTIALr ? SD_DMA_PARTIAL_END : 11'd1024);
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end
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else if (SD_DMA_DONE_rising) SD_DMA_STATUSr <= 1'b0;
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end
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always @(posedge CLK) begin
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if(cyclecnt == 1042
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|| ((SD_DMA_END_MID_BLOCK & SD_DMA_PARTIALr) && cyclecnt == SD_DMA_PARTIAL_END))
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SD_DMA_DONEr <= 1;
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else SD_DMA_DONEr <= 0;
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end
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always @(posedge CLK) begin
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if(SD_DMA_EN_rising || !SD_DMA_STATUSr) begin
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clkcnt <= 0;
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end else begin
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if(SD_DMA_STATUSr) begin
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clkcnt <= clkcnt + 1;
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end
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end
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end
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always @(posedge CLK) begin
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if(SD_DMA_EN_rising)
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cyclecnt <= (SD_DMA_PARTIALr && SD_DMA_START_MID_BLOCK) ? SD_DMA_PARTIAL_START : 0;
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else if(!SD_DMA_STATUSr) cyclecnt <= 0;
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else if(clkcnt[1:0] == 2'b10) cyclecnt <= cyclecnt + 1;
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end
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// we have 8 clk cycles to complete one RAM write
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// (4 clk cycles per SD_CLK; 2 SD_CLK cycles per byte)
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always @(posedge CLK) begin
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if(SD_DMA_STATUSr) begin
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case(clkcnt[2:0])
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3'h0: begin
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SD_DMA_SRAM_DATAr[7:4] <= SD_DAT;
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if(cyclecnt>SD_DMA_STARTr && cyclecnt <= SD_DMA_ENDr) SD_DMA_NEXTADDRr <= 1'b1;
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end
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3'h1: begin
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SD_DMA_NEXTADDRr <= 1'b0;
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end
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3'h2: if(cyclecnt>=SD_DMA_STARTr && cyclecnt < SD_DMA_ENDr) SD_DMA_SRAM_WEr <= 1'b0;
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// 3'h3:
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3'h4:
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SD_DMA_SRAM_DATAr[3:0] <= SD_DAT;
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// 3'h5:
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// 3'h6:
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3'h7:
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SD_DMA_SRAM_WEr <= 1'b1;
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endcase
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end
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end
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endmodule
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