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sd2snes/verilog/sd2snes_cx4
History
Maximilian Rehkopf f5caf21fac FPGA: slightly tighten timing constraints
2012-05-02 10:41:07 +02:00
..
ipcore_dir
FPGA: updated project files
2012-01-14 23:16:57 +01:00
address.v
FPGA/cx4: map ROM above bank 3F/BF
2012-02-27 22:14:19 +01:00
cx4.v
FPGA/Cx4: introduce wait states (fix MMX2 attract mode)
2012-05-02 10:30:22 +02:00
dac.v
FPGA/cx4: initial commit
2011-10-23 04:10:55 +02:00
dcm.v
FPGA/cx4: initial commit
2011-10-23 04:10:55 +02:00
main.ucf
FPGA: slightly tighten timing constraints
2012-05-02 10:41:07 +02:00
main.v
FPGA/Cx4: optimize non-sector-aligned SD DMA reads
2012-01-14 02:21:01 +01:00
msu.v
FPGA/cx4: initial commit
2011-10-23 04:10:55 +02:00
sd2snes_cx4.xise
FPGA: slightly tighten timing constraints
2012-05-02 10:41:07 +02:00
sd_dma.v
FPGA/Cx4: optimize non-sector-aligned SD DMA reads
2012-01-14 02:21:01 +01:00
spi.v
FPGA/cx4: clean up tab/whitespace mix
2011-11-01 21:09:31 +01:00
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