prelink: Add risc-v support

Signed-off-by: Khem Raj <raj.khem@gmail.com>

recipes-devtool/prelink/files/0001-prelink-Add-RISC-V-support.patch

@@ -0,0 +1,127 @@
+From e3bb636048916b092b36f81f787399f4a4c76e41 Mon Sep 17 00:00:00 2001
+From: Khem Raj <raj.khem@gmail.com>
+Date: Sat, 10 Mar 2018 13:39:34 -0800
+Subject: [PATCH] prelink: Add RISC-V support
+
+Signed-off-by: Khem Raj <raj.khem@gmail.com>
+---
+ ChangeLog         |  5 +++++
+ src/elf.h         | 25 ++++++++++++++++++++++++-
+ src/rtld/dl-tls.c |  5 +++++
+ src/rtld/rtld.c   | 14 ++++++++++++++
+ 4 files changed, 48 insertions(+), 1 deletion(-)
+
+diff --git a/ChangeLog b/ChangeLog
+index c72dca8..4487026 100644
+--- a/ChangeLog
++++ b/ChangeLog
+@@ -1,3 +1,8 @@
++2018-03-10   Khem Raj <raj.khem@gmail.com>
++	* src/elf.h: Add RISC-V defines
++	* src/rtld/dl-tls.c: Add RISC-V support
++	* src/rtld/rtld.c: Add RISC-V support
++
+ 2017-06-20   Mark Hatle <mark.hatle@windriver.com>
+ 	* doc/Makefile.am: Disable automatic generation of prelink.pdf
+ 
+diff --git a/src/elf.h b/src/elf.h
+index fbadda4..dbd6170 100644
+--- a/src/elf.h
++++ b/src/elf.h
+@@ -254,7 +254,8 @@ typedef struct
+ #define EM_TILEPRO	188		/* Tilera TILEPro */
+ #define EM_MICROBLAZE	189		/* Xilinx MicroBlaze */
+ #define EM_TILEGX	191		/* Tilera TILE-Gx */
+-#define EM_NUM		192
++#define EM_RISCV	243		/* RISC-V */
++#define EM_NUM		244
+ 
+ /* If it is necessary to assign new unofficial EM_* values, please
+    pick large random numbers (0x8523, 0xa7f2, etc.) to minimize the
+@@ -3556,6 +3557,28 @@ enum
+ 
+ #define R_TILEGX_NUM		130
+ 
++/* RISC-V ELF Flags */
++#define EF_RISCV_RVC			0x0001
++#define EF_RISCV_FLOAT_ABI		0x0006
++#define EF_RISCV_FLOAT_ABI_SOFT		0x0000
++#define EF_RISCV_FLOAT_ABI_SINGLE	0x0002
++#define EF_RISCV_FLOAT_ABI_DOUBLE	0x0004
++#define EF_RISCV_FLOAT_ABI_QUAD		0x0006
++
++/* RISC-V relocations.  */
++#define R_RISCV_NONE		0
++#define R_RISCV_32		1
++#define R_RISCV_64		2
++#define R_RISCV_RELATIVE	3
++#define R_RISCV_COPY		4
++#define R_RISCV_JUMP_SLOT	5
++#define R_RISCV_TLS_DTPMOD32	6
++#define R_RISCV_TLS_DTPMOD64	7
++#define R_RISCV_TLS_DTPREL32	8
++#define R_RISCV_TLS_DTPREL64	9
++#define R_RISCV_TLS_TPREL32	10
++#define R_RISCV_TLS_TPREL64	11
++#define R_RISCV_NUM		12
+ 
+ __END_DECLS
+ 
+diff --git a/src/rtld/dl-tls.c b/src/rtld/dl-tls.c
+index 2da6bc5..280cee4 100644
+--- a/src/rtld/dl-tls.c
++++ b/src/rtld/dl-tls.c
+@@ -138,6 +138,11 @@ rtld_determine_tlsoffsets (int e_machine, struct r_scope_elem *search_list)
+       tls_tcb_size = 8;
+       break;
+ 
++    case EM_RISCV:
++      tls_dtv_at_tp = 1;
++      tls_tcb_size = 0;
++      break;
++
+     default:
+       /* Hope there's no TLS!  */
+       for (i = 0; i < search_list->r_nlist; i++)
+diff --git a/src/rtld/rtld.c b/src/rtld/rtld.c
+index 3196981..2fc355b 100644
+--- a/src/rtld/rtld.c
++++ b/src/rtld/rtld.c
+@@ -224,6 +224,17 @@ parse_opt (int key, char *arg, struct argp_state *state)
+     * ELF_RTYPE_CLASS_PLT \
+    | ((type) == R_MICROBLAZE_COPY) * ELF_RTYPE_CLASS_COPY)
+ 
++/* From glibc-2.27: sysdeps/riscv/dl-machine.h */
++#define riscv_elf_machine_type_class(type)                      \
++  ((ELF_RTYPE_CLASS_PLT * ((type) == R_RISCV_JUMP_SLOT          \
++     || ((type) == R_RISCV_TLS_DTPREL32)    \
++     || ((type) == R_RISCV_TLS_DTPMOD32)    \
++     || ((type) == R_RISCV_TLS_TPREL32)     \
++     || ((type) == R_RISCV_TLS_DTPREL64)    \
++     || ((type) == R_RISCV_TLS_DTPMOD64)    \
++     || ((type) == R_RISCV_TLS_TPREL64)))   \
++   | (ELF_RTYPE_CLASS_COPY * ((type) == R_RISCV_COPY)))
++
+ int
+ elf_machine_type_class (int type, int machine)
+ {
+@@ -254,6 +265,8 @@ elf_machine_type_class (int type, int machine)
+ 	return nios2_elf_machine_type_class(type);
+     case EM_MICROBLAZE:
+ 	return microblaze_elf_machine_type_class(type);
++    case EM_RISCV:
++	return riscv_elf_machine_type_class(type);
+ 
+     default:
+       printf ("Unknown architecture!\n");
+@@ -296,6 +309,7 @@ machine_no_rela (int machine)
+     case EM_SPARCV9:
+     case EM_ALTERA_NIOS2:
+     case EM_MICROBLAZE:
++    case EM_RISCV:
+       return 0;
+     default:
+       return 1;
+-- 
+2.16.2
+

recipes-devtool/prelink/prelink_%.bbappend

@@ -0,0 +1,2 @@
+FILESEXTRAPATHS_prepend := "${THISDIR}/files:"
+SRC_URI_append = " file://0001-prelink-Add-RISC-V-support.patch"