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glibc: Add support for the RISC-V 32-bit fork

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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Alistair Francis
2018-11-26 11:32:31 -08:00
committed by Khem Raj
parent 1b9c91908b
commit 58ec67a3db
3 changed files with 62 additions and 0 deletions
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26
recipes-core/glibc/files/0001-riscv-Fix-dl-cache-array-bounds.patch Normal file
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@@ -0,0 +1,26 @@
From a23eb7becd5b6ecb09ed3f0f35a0441f43bd4aa1 Mon Sep 17 00:00:00 2001
From: Alistair Francis <alistair.francis@wdc.com>
Date: Wed, 28 Nov 2018 12:47:07 -0800
Subject: [PATCH] riscv: Fix dl-cache array bounds
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
sysdeps/unix/sysv/linux/riscv/dl-cache.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/sysdeps/unix/sysv/linux/riscv/dl-cache.h b/sysdeps/unix/sysv/linux/riscv/dl-cache.h
index f3a999ac86..e44d882e8c 100644
--- a/sysdeps/unix/sysv/linux/riscv/dl-cache.h
+++ b/sysdeps/unix/sysv/linux/riscv/dl-cache.h
@@ -51,7 +51,7 @@
do \
{ \
size_t len = strlen (dir); \
- char path[len + 9]; \
+ char path[len + 10]; \
memcpy (path, dir, len + 1); \
if (len >= 13 && ! memcmp(path + len - 13, "/lib32/ilp32d", 13)) \
{ \
--
2.19.1

18
recipes-core/glibc/glibc-initial_%.bbappend Normal file
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# Upstream Glibc does not yet have RISC-V 32-bit support.
# Force it to use the RISC-V fork
GLIBC_GIT_URI_qemuriscv32 = "git://github.com/riscv/riscv-glibc.git"
SRCBRANCH_qemuriscv32 = "32bit"
SRCREV_qemuriscv32 = "83d5eaa75361ba0cb7969669452c9ff233ac710b"
SRC_URI_remove_qemuriscv32 = " \
file://0031-sysdeps-ieee754-prevent-maybe-uninitialized-errors-w.patch \
file://0032-sysdeps-ieee754-soft-fp-ignore-maybe-uninitialized-w.patch \
file://0033-locale-prevent-maybe-uninitialized-errors-with-Os-BZ.patch \
"
FILESEXTRAPATHS_prepend := "${THISDIR}/files:"
SRC_URI_append_qemuriscv32 = "\
file://0001-riscv-Fix-dl-cache-array-bounds.patch \
"

18
recipes-core/glibc/glibc_%.bbappend Normal file
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@@ -0,0 +1,18 @@
# Upstream Glibc does not yet have RISC-V 32-bit support.
# Force it to use the RISC-V fork
GLIBC_GIT_URI_qemuriscv32 = "git://github.com/riscv/riscv-glibc.git"
SRCBRANCH_qemuriscv32 = "32bit"
SRCREV_qemuriscv32 = "83d5eaa75361ba0cb7969669452c9ff233ac710b"
SRC_URI_remove_qemuriscv32 = " \
file://0031-sysdeps-ieee754-prevent-maybe-uninitialized-errors-w.patch \
file://0032-sysdeps-ieee754-soft-fp-ignore-maybe-uninitialized-w.patch \
file://0033-locale-prevent-maybe-uninitialized-errors-with-Os-BZ.patch \
"
FILESEXTRAPATHS_prepend := "${THISDIR}/files:"
SRC_URI_append_qemuriscv32 = "\
file://0001-riscv-Fix-dl-cache-array-bounds.patch \
"