t-head/meta-riscv
1
0
Fork 0
mirror of https://github.com/thead-yocto-mirror/meta-riscv synced 2026-06-21 08:52:24 +02:00
Code Issues Packages Projects Releases Wiki Activity

nspr: Remove NSPR patch

Browse Source 
RISC-V support is now included in the OE-Core NSPR package, this patch
is no longer required so let's remove it.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Alistair Francis
2018-07-09 14:01:23 -07:00
committed by Khem Raj
parent 89c77d9ddb
commit ecd5f4ba89
2 changed files with 0 additions and 105 deletions
Download Patch File Download Diff File Expand all files Collapse all files

103
recipes-support/nspr/files/0001-Add-riscv-architecture-support.patch
View File

@@ -1,103 +0,0 @@
From ff3d77742bd3b0272c48ff7472a45e9c537709f2 Mon Sep 17 00:00:00 2001
From: Khem Raj <raj.khem@gmail.com>
Date: Wed, 4 Oct 2017 11:55:10 -0700
Subject: [PATCH] Add riscv architecture support
Signed-off-by: Khem Raj <raj.khem@gmail.com>
---
pr/include/md/_linux.cfg | 46 ++++++++++++++++++++++++++++++++++++++++++++++
pr/include/md/_linux.h | 14 ++++++++++++++
2 files changed, 60 insertions(+)
diff --git a/pr/include/md/_linux.cfg b/pr/include/md/_linux.cfg
index 31296a8..d0dde57 100644
--- a/pr/include/md/_linux.cfg
+++ b/pr/include/md/_linux.cfg
@@ -360,6 +360,52 @@
#define PR_BYTES_PER_WORD_LOG2 2
#define PR_BYTES_PER_DWORD_LOG2 3
+#elif defined(__riscv) && __riscv_xlen == 64
+
+#undef IS_BIG_ENDIAN
+#define IS_LITTLE_ENDIAN 1
+#define IS_64
+
+#define PR_BYTES_PER_BYTE 1
+#define PR_BYTES_PER_SHORT 2
+#define PR_BYTES_PER_INT 4
+#define PR_BYTES_PER_INT64 8
+#define PR_BYTES_PER_LONG 8
+#define PR_BYTES_PER_FLOAT 4
+#define PR_BYTES_PER_DOUBLE 8
+#define PR_BYTES_PER_WORD 8
+#define PR_BYTES_PER_DWORD 8
+
+#define PR_BITS_PER_BYTE 8
+#define PR_BITS_PER_SHORT 16
+#define PR_BITS_PER_INT 32
+#define PR_BITS_PER_INT64 64
+#define PR_BITS_PER_LONG 64
+#define PR_BITS_PER_FLOAT 32
+#define PR_BITS_PER_DOUBLE 64
+#define PR_BITS_PER_WORD 64
+
+#define PR_BITS_PER_BYTE_LOG2 3
+#define PR_BITS_PER_SHORT_LOG2 4
+#define PR_BITS_PER_INT_LOG2 5
+#define PR_BITS_PER_INT64_LOG2 6
+#define PR_BITS_PER_LONG_LOG2 6
+#define PR_BITS_PER_FLOAT_LOG2 5
+#define PR_BITS_PER_DOUBLE_LOG2 6
+#define PR_BITS_PER_WORD_LOG2 6
+
+#define PR_ALIGN_OF_SHORT 2
+#define PR_ALIGN_OF_INT 4
+#define PR_ALIGN_OF_INT64 8
+#define PR_ALIGN_OF_LONG 8
+#define PR_ALIGN_OF_FLOAT 4
+#define PR_ALIGN_OF_DOUBLE 8
+#define PR_ALIGN_OF_POINTER 8
+#define PR_ALIGN_OF_WORD 8
+
+#define PR_BYTES_PER_WORD_LOG2 3
+#define PR_BYTES_PER_DWORD_LOG2 3
+
#elif defined(__sparc__) && defined (__arch64__)
#undef IS_LITTLE_ENDIAN
diff --git a/pr/include/md/_linux.h b/pr/include/md/_linux.h
index 551918f..3a3cc2e 100644
--- a/pr/include/md/_linux.h
+++ b/pr/include/md/_linux.h
@@ -31,6 +31,8 @@
#define _PR_SI_ARCHITECTURE "x86-64"
#elif defined(__mc68000__)
#define _PR_SI_ARCHITECTURE "m68k"
+#elif defined(__riscv) && __riscv_xlen == 64
+#define _PR_SI_ARCHITECTURE "rv64"
#elif defined(__sparc__) && defined(__arch64__)
#define _PR_SI_ARCHITECTURE "sparc64"
#elif defined(__sparc__)
@@ -151,6 +153,18 @@ extern PRInt32 _PR_x86_64_AtomicSet(PRInt32 *val, PRInt32 newval);
#endif
#endif
+#if defined(__riscv)
+#if defined(__GNUC__)
+/* Use GCC built-in functions */
+#define _PR_HAVE_ATOMIC_OPS
+#define _MD_INIT_ATOMIC()
+#define _MD_ATOMIC_INCREMENT(ptr) __sync_add_and_fetch(ptr, 1)
+#define _MD_ATOMIC_DECREMENT(ptr) __sync_sub_and_fetch(ptr, 1)
+#define _MD_ATOMIC_ADD(ptr, i) __sync_add_and_fetch(ptr, i)
+#define _MD_ATOMIC_SET(ptr, nv) __sync_lock_test_and_set(ptr, nv)
+#endif
+#endif
+
#if defined(__powerpc__) && !defined(__powerpc64__)
#define _PR_HAVE_ATOMIC_OPS
#define _MD_INIT_ATOMIC()
--
2.14.2

2
recipes-support/nspr/nspr_%.bbappend
View File

@@ -1,2 +0,0 @@
FILESEXTRAPATHS_prepend := "${THISDIR}/files:"
SRC_URI += "file://0001-Add-riscv-architecture-support.patch"