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base: t-head:Linux_SDK_V0.9.5
Branches Tags
t-head:lpi4a t-head:huiwei t-head:thead-sdk t-head:fix-toolchains t-head:merged-ahead t-head:update/1.4.2/gpu/dvfs t-head:ahead-new t-head:ov5693 t-head:develop t-head:master
t-head:Linux_SDK_V1.4.2 t-head:Linux_SDK_V1.3.3 t-head:Linux_SDK_V1.2.1 t-head:Linux_SDK_V1.2.0 t-head:Linux_SDK_V1.1.2 t-head:Linux_SDK_V1.0.3 t-head:Linux_SDK_V1.0.2 t-head:Linux_SDK_V0.9.5
..
compare: t-head:master
Branches Tags
t-head:lpi4a t-head:huiwei t-head:thead-sdk t-head:fix-toolchains t-head:merged-ahead t-head:update/1.4.2/gpu/dvfs t-head:ahead-new t-head:ov5693 t-head:develop t-head:master
t-head:Linux_SDK_V1.4.2 t-head:Linux_SDK_V1.3.3 t-head:Linux_SDK_V1.2.1 t-head:Linux_SDK_V1.2.0 t-head:Linux_SDK_V1.1.2 t-head:Linux_SDK_V1.0.3 t-head:Linux_SDK_V1.0.2 t-head:Linux_SDK_V0.9.5

3 Commits
Linux_SDK_ ... master

Author SHA1 Message Date
thead_admin
ada47f394b Linux_SDK_V1.1.2 2023-03-05 22:36:24 +08:00
thead_admin
221913b496 Linux_SDK_V1.0.3 2023-01-04 13:12:21 +08:00
thead_admin
c20e64a982 Linux_SDK_V1.0.2 2022-11-22 15:53:40 +08:00
120 changed files with 16548 additions and 1763 deletions
Expand all files Collapse all files

8
arch/riscv/Kconfig
View File

@@ -26,13 +26,16 @@ config RISCV
select ARCH_HAS_SET_DIRECT_MAP
select ARCH_HAS_SET_MEMORY
select ARCH_HAS_STRICT_KERNEL_RWX if MMU
select ARCH_HAS_STRICT_MODULE_RWX if MMU
select ARCH_HAS_DMA_PREP_COHERENT
select ARCH_HAS_SYNC_DMA_FOR_CPU
select ARCH_HAS_SYNC_DMA_FOR_DEVICE
select ARCH_HAS_DMA_WRITE_COMBINE
select ARCH_HAS_DMA_MMAP_PGPROT
select ARCH_KEEP_MEMBLOCK
select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX
select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT
select ARCH_USE_QUEUED_RWLOCKS
select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU
select ARCH_WANT_FRAME_POINTERS
select ARCH_WANT_HUGE_PMD_SHARE if 64BIT
@@ -416,6 +419,11 @@ config VECTOR_0_7
endchoice
config VLEN_256
bool "VECTOR VLEN 256"
depends on VECTOR
default n
config VECTOR_EMU
bool "VECTOR e64 emulate for c906 v1"
depends on VECTOR

29
arch/riscv/boot/dts/thead/Makefile
View File

@@ -4,7 +4,7 @@ dtb-$(CONFIG_SOC_THEAD) += light-fm-emu.dtb light_mpw.dtb
dtb-$(CONFIG_SOC_THEAD) += light-fm-emu-npu-fce.dtb
dtb-$(CONFIG_SOC_THEAD) += light-fm-emu-gpu.dtb
dtb-$(CONFIG_SOC_THEAD) += light-fm-emu-dsp.dtb
dtb-$(CONFIG_SOC_THEAD) += light-fm-emu-audio.dtb
dtb-$(CONFIG_SOC_THEAD) += light-fm-emu-audio.dtb light-a-val-audio-hdmi.dtb
dtb-$(CONFIG_SOC_THEAD) += light-fm-emu-hdmi.dtb
dtb-$(CONFIG_SOC_THEAD) += light-fm-emu-dsi0-hdmi.dtb
dtb-$(CONFIG_SOC_THEAD) += light-a-val.dtb light-a-val-sv.dtb
@@ -24,23 +24,16 @@ dtb-$(CONFIG_SOC_THEAD) += light-b-product.dtb
dtb-$(CONFIG_SOC_THEAD) += light-b-product-ddr1G.dtb
dtb-$(CONFIG_SOC_THEAD) += light-b-product-miniapp-hdmi.dtb
dtb-$(CONFIG_SOC_THEAD) += light-a-val-full.dtb
dtb-$(CONFIG_SOC_THEAD) += light-ant-evt.dtb
dtb-$(CONFIG_SOC_THEAD) += light-ant-ref.dtb
dtb-$(CONFIG_SOC_THEAD) += light-ant-discrete.dtb
dtb-$(CONFIG_SOC_THEAD) += light-beagle.dtb
dtb-$(CONFIG_SOC_THEAD) += light-lpi4a.dtb light-lpi4a-ddr2G.dtb
dtb-$(CONFIG_SOC_THEAD) += light-a-ref.dtb light-a-ref-dsi0.dtb light-a-ref-dsi0-hdmi.dtb
dtb-$(CONFIG_SOC_THEAD) += light-b-ref.dtb
dtb-$(CONFIG_SOC_THEAD) += light-a-val-crash.dtb light-b-product-crash.dtb light-ant-ref-crash.dtb light-ant-discrete-crash.dtb
dtb-$(CONFIG_SOC_THEAD) += light-b-power.dtb
# // temporary dtb for power gate
dtb-$(CONFIG_SOC_THEAD) += light-a-val-powergate.dtb light-a-val-sv-powergate.dtb
dtb-$(CONFIG_SOC_THEAD) += light-a-val-ddr2G-powergate.dtb light-a-val-ddr1G-powergate.dtb
dtb-$(CONFIG_SOC_THEAD) += light-a-val-npu-fce-powergate.dtb
dtb-$(CONFIG_SOC_THEAD) += light-a-val-iso7816-powergate.dtb
dtb-$(CONFIG_SOC_THEAD) += light-a-val-nand-powergate.dtb
dtb-$(CONFIG_SOC_THEAD) += light-a-val-audio-powergate.dtb
dtb-$(CONFIG_SOC_THEAD) += light-a-val-dsi0-powergate.dtb light-a-val-dsi1-powergate.dtb light-a-val-hdmi-powergate.dtb light-a-val-dsi0-dsi1-powergate.dtb light-a-val-dsi0-hdmi-powergate.dtb light-a-val-dpi0-powergate.dtb light-a-val-dpi0-dpi1-powergate.dtb
dtb-$(CONFIG_SOC_THEAD) += light-a-val-wcn-powergate.dtb
dtb-$(CONFIG_SOC_THEAD) += light-a-val-khv-powergate.dtb
dtb-$(CONFIG_SOC_THEAD) += light-a-val-sec-powergate.dtb
dtb-$(CONFIG_SOC_THEAD) += light-a-val-miniapp-hdmi-powergate.dtb
dtb-$(CONFIG_SOC_THEAD) += light-a-product-powergate.dtb
dtb-$(CONFIG_SOC_THEAD) += light-b-product-powergate.dtb
dtb-$(CONFIG_SOC_THEAD) += light-b-product-ddr1G-powergate.dtb
dtb-$(CONFIG_SOC_THEAD) += light-a-val-full-powergate.dtb
dtb-$(CONFIG_SOC_THEAD) += light-a-val-android.dtb
dtb-$(CONFIG_SOC_THEAD) += fire-emu.dtb fire-emu-crash.dtb
dtb-$(CONFIG_SOC_THEAD) += fire-emu-soc-base.dtb fire-emu-soc-c910x4.dtb fire-emu-gpu-dpu-dsi0.dtb fire-emu-vi-dsp-vo.dtb fire-emu-vi-vp-vo.dtb

856
arch/riscv/boot/dts/thead/fire-crash.dts Normal file
View File

@@ -0,0 +1,856 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2021-2022 Alibaba Group Holding Limited.
*/
/dts-v1/;
#include "fire.dtsi"
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/gpio/gpio.h>
#include "light-vi-devices.dtsi"
/ {
model = "T-HEAD fire fpga board";
compatible = "thead,fire-emu", "thead,fire";
chosen {
bootargs = "console=ttyS0,115200 earlycon";
stdout-path = "serial0:115200n8";
};
leds {
compatible = "gpio-leds";
status = "disabled";
led0 {
label = "SYS_STATUS";
gpios = <&gpio1_porta 15 0>; /* GPIO_ACTIVE_HIGH: 0 */
default-state = "off";
};
};
display-subsystem {
status = "okay";
};
lcd0_backlight: pwm-backlight@0 {
status = "disabled";
compatible = "pwm-backlight";
pwms = <&pwm 0 5000000>;
brightness-levels = <0 4 8 16 32 64 128 255>;
default-brightness-level = <7>;
};
light_iopmp: iopmp {
status = "disabled";
compatible = "thead,light-iopmp";
/* config#1: multiple valid regions */
iopmp_emmc: IOPMP_EMMC {
regions = <0x000000 0x100000>,
<0x100000 0x200000>;
attr = <0xFFFFFFFF>;
dummy_slave= <0x800000>;
};
/* config#2: iopmp bypass */
iopmp_sdio0: IOPMP_SDIO0 {
bypass_en;
};
/* config#3: iopmp default region set */
iopmp_sdio1: IOPMP_SDIO1 {
attr = <0xFFFFFFFF>;
is_default_region;
};
iopmp_usb0: IOPMP_USB0 {
attr = <0xFFFFFFFF>;
is_default_region;
};
iopmp_ao: IOPMP_AO {
is_default_region;
};
iopmp_aud: IOPMP_AUD {
is_default_region;
};
iopmp_chip_dbg: IOPMP_CHIP_DBG {
is_default_region;
};
iopmp_eip120i: IOPMP_EIP120I {
is_default_region;
};
iopmp_eip120ii: IOPMP_EIP120II {
is_default_region;
};
iopmp_eip120iii: IOPMP_EIP120III {
is_default_region;
};
iopmp_isp0: IOPMP_ISP0 {
is_default_region;
};
iopmp_isp1: IOPMP_ISP1 {
is_default_region;
};
iopmp_dw200: IOPMP_DW200 {
is_default_region;
};
iopmp_vipre: IOPMP_VIPRE {
is_default_region;
};
iopmp_venc: IOPMP_VENC {
is_default_region;
};
iopmp_vdec: IOPMP_VDEC {
is_default_region;
};
iopmp_g2d: IOPMP_G2D {
is_default_region;
};
iopmp0_dpu: IOPMP0_DPU {
bypass_en;
};
iopmp1_dpu: IOPMP1_DPU {
bypass_en;
};
iopmp_gpu: IOPMP_GPU {
is_default_region;
};
iopmp_gmac1: IOPMP_GMAC1 {
is_default_region;
};
iopmp_gmac2: IOPMP_GMAC2 {
is_default_region;
};
iopmp_dmac: IOPMP_DMAC {
is_default_region;
};
iopmp_tee_dmac: IOPMP_TEE_DMAC {
is_default_region;
};
iopmp_dsp0: IOPMP_DSP0 {
is_default_region;
};
iopmp_dsp1: IOPMP_DSP1 {
is_default_region;
};
};
mbox_910t_client1: mbox_910t_client1 {
compatible = "thead,light-mbox-client";
mbox-names = "902";
mboxes = <&mbox_910t 1 0>;
status = "disabled";
};
mbox_910t_client2: mbox_910t_client2 {
compatible = "thead,light-mbox-client";
mbox-names = "906";
mboxes = <&mbox_910t 2 0>;
status = "disabled";
};
lightsound: lightsound@1 {
compatible = "simple-audio-card";
simple-audio-card,name = "Light-Sound-Card";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
dummy_codec: dummy_codec {
#sound-dai-cells = <1>;
compatible = "linux,bt-sco";
status = "okay";
};
wcn_wifi: wireless-wlan {
compatible = "wlan-platdata";
clock-names = "clk_wifi";
ref-clock-frequency = <24000000>;
keep_wifi_power_on;
pinctrl-names = "default";
wifi_chip_type = "rtl8723ds";
WIFI,poweren_gpio = <&gpio2_porta 26 0>;
WIFI,reset_n = <&gpio2_porta 28 0>;
status = "disabled";
};
wcn_bt: wireless-bluetooth {
compatible = "bluetooth-platdata";
pinctrl-names = "default", "rts_gpio";
BT,power_gpio = <&gpio2_porta 29 0>;
status = "disabled";
};
gpio_keys: gpio_keys{
compatible = "gpio-keys";
pinctrl-names = "default";
status = "disabled";
key-volumedown {
label = "Volume Down Key";
linux,code = <KEY_1>;
debounce-interval = <2>;
gpios = <&ao_gpio_porta 4 GPIO_ACTIVE_LOW>;
};
key-volumeup {
label = "Volume Up Key";
linux,code = <KEY_2>;
debounce-interval = <2>;
gpios = <&ao_gpio_porta 5 GPIO_ACTIVE_LOW>;
};
};
aon: light-aon {
compatible = "thead,light-aon";
mbox-names = "aon";
mboxes = <&mbox_910t 1 0>;
status = "disabled";
pd: light-aon-pd {
compatible = "thead,light-aon-pd";
#power-domain-cells = <1>;
status = "disabled";
};
aon_reg_dialog: light-dialog-reg {
compatible = "thead,light-dialog-pmic";
status = "disabled";
};
c910_cpufreq {
compatible = "thead,light-mpw-cpufreq";
status = "disabled";
};
test: light-aon-test {
compatible = "thead,light-aon-test";
status = "disabled";
};
};
};
&resmem {
#address-cells = <2>;
#size-cells = <2>;
ranges;
tee_mem: memory@1a000000 {
reg = <0x0 0x1a000000 0 0x4000000>;
no-map;
};
dsp0_mem: memory@20000000 { /**0x2000_0000~0x2040_0000 4M**/
reg = <0x0 0x20000000 0x0 0x00280000 /* DSP FW code&data section 2.5M*/
0x0 0x20280000 0x0 0x00001000 /* DSP communication area 4K*/
0x0 0x20281000 0x0 0x00007000 /* Panic/log page 28K */
0x0 0x20288000 0x0 0x00178000>; /* DSP shared memory 1.5M-32K*/
no-map;
};
dsp1_mem: memory@20400000 { /**0x2040_0000~0x2080_0000 4M**/
reg = <0x0 0x20400000 0x0 0x00280000 /* DSP FW code&data section */
0x0 0x20680000 0x0 0x00001000 /* DSP communication area */
0x0 0x20681000 0x0 0x00007000 /* Panic/log page*/
0x0 0x20688000 0x0 0x00178000>; /* DSP shared memory */
no-map;
};
vi_mem: framebuffer@0f800000 {
reg = <0x0 0x0F800000 0x0 0x05400000 /* vi_mem_pool_region[0] 84 MB (default) */
0x0 0x14C00000 0x0 0x01D00000 /* vi_mem_pool_region[1] 29 MB */
0x0 0x16900000 0x0 0x03200000>; /* vi_mem_pool_region[2] 50 MB */
no-map;
};
facelib_mem: memory@22000000 {
reg = <0x0 0x22000000 0x0 0x10000000>;
no-map;
};
};
&clk {
status = "disabled";
};
&i2c0 {
clock-frequency = <400000>;
status = "okay";
eeprom@50 {
compatible = "atmel,24c32";
reg = <0x50>;
pagesize = <32>;
};
codec: wm8960@1a {
#sound-dai-cells = <0>;
compatible = "wlf,wm8960";
reg = <0x1a>;
wlf,shared-lrclk;
wlf,hp-cfg = <3 2 3>;
wlf,gpio-cfg = <1 3>;
};
touch@5d {
#gpio-cells = <2>;
compatible = "goodix,gt911";
status = "disabled";
reg = <0x5d>;
interrupt-parent = <&gpio1_porta>;
interrupts = <8 0>;
irq-gpios = <&gpio1_porta 8 0>;
reset-gpios = <&gpio1_porta 7 0>;
touchscreen-size-x = <800>;
touchscreen-size-y = <1280>;
};
};
&audio_i2c0 {
clock-frequency = <100000>;
status = "disabled";
es8156_audio_codec: es8156@8 {
#sound-dai-cells = <0>;
compatible = "everest,es8156";
reg = <0x08>;
};
es7210_audio_codec: es7210@40 {
#sound-dai-cells = <0>;
compatible = "MicArray_0";
reg = <0x40>;
};
};
&i2c1 {
clock-frequency = <400000>;
status = "disabled";
touch1@5d {
#gpio-cells = <2>;
compatible = "goodix,gt911";
reg = <0x5d>;
interrupt-parent = <&gpio1_porta>;
interrupts = <12 0>;
irq-gpios = <&gpio1_porta 12 0>;
reset-gpios = <&gpio1_porta 11 0>;
touchscreen-size-x = <800>;
touchscreen-size-y = <1280>;
};
};
&spi0 {
num-cs = <1>;
cs-gpios = <&gpio2_porta 15 0>; // GPIO_ACTIVE_HIGH: 0
rx-sample-delay-ns = <10>;
status = "okay";
spi_norflash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "winbond,w25q64jwm", "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <50000000>;
w25q,fast-read;
status = "disabled";
};
spidev@1 {
compatible = "spidev";
#address-cells = <0x1>;
#size-cells = <0x1>;
reg = <0x1>;
spi-max-frequency = <50000000>;
};
};
&qspi0 {
num-cs = <1>;
cs-gpios = <&gpio2_porta 3 0>;
rx-sample-dly = <4>;
status = "disabled";
spi-flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spi-nand";
spi-max-frequency = <100000000>;
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
reg = <0>;
partition@0 {
label = "ubi1";
reg = <0x00000000 0x08000000>;
};
};
};
&qspi1 {
num-cs = <1>;
cs-gpios = <&gpio0_porta 1 0>;
status = "disabled";
spi-flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spi-nand";
spi-max-frequency = <66000000>;
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
reg = <0>;
partition@0 {
label = "ubi2";
reg = <0x00000000 0x08000000>;
};
};
};
&gmac0 {
phy-mode = "rgmii-id";
rx-clk-delay = <0x00>; /* for RGMII */
tx-clk-delay = <0x00>; /* for RGMII */
phy-handle = <&phy_88E1111_0>;
status = "okay";
mdio0 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,dwmac-mdio";
phy_88E1111_0: ethernet-phy@0 {
reg = <0x1>;
};
phy_88E1111_1: ethernet-phy@1 {
reg = <0x2>;
};
};
};
&emmc {
max-frequency = <198000000>;
non-removable;
mmc-hs400-1_8v;
io_fixed_1v8;
is_emmc;
no-sdio;
no-sd;
pull_up;
bus-width = <8>;
status = "okay";
};
&sdhci0 {
max-frequency = <198000000>;
bus-width = <4>;
pull_up;
wprtn_ignore;
status = "okay";
};
&sdhci1 {
max-frequency = <100000000>;
bus-width = <4>;
pull_up;
no-sd;
no-mmc;
non-removable;
io_fixed_1v8;
post-power-on-delay-ms = <50>;
wprtn_ignore;
cap-sd-highspeed;
keep-power-in-suspend;
wakeup-source;
status = "disabled";
};
&padctrl0_apsys { /* right-pinctrl */
light-evb-padctrl0 {
/*
* Pin Configuration Node:
* Format: <pin_id mux_node config>
*/
pinctrl_uart0: uart0grp {
thead,pins = <
FM_UART0_TXD 0x0 0x72
FM_UART0_RXD 0x0 0x72
>;
};
pinctrl_spi0: spi0grp {
thead,pins = <
FM_SPI_CSN 0x3 0x20a
FM_SPI_SCLK 0x0 0x20a
FM_SPI_MISO 0x0 0x23a
FM_SPI_MOSI 0x0 0x23a
>;
};
pinctrl_qspi0: qspi0grp {
thead,pins = <
FM_QSPI0_SCLK 0x0 0x20f
FM_QSPI0_CSN0 0x3 0x20f
FM_QSPI0_CSN1 0x0 0x20f
FM_QSPI0_D0_MOSI 0x0 0x23f
FM_QSPI0_D1_MISO 0x0 0x23f
FM_QSPI0_D2_WP 0x0 0x23f
FM_QSPI0_D3_HOLD 0x0 0x23f
>;
};
pinctrl_audio_i2s0: i2s0grp {
thead,pins = <
FM_QSPI0_SCLK 0x2 0x208
FM_QSPI0_CSN0 0x2 0x238
FM_QSPI0_CSN1 0x2 0x208
FM_QSPI0_D0_MOSI 0x2 0x238
FM_QSPI0_D1_MISO 0x2 0x238
FM_QSPI0_D2_WP 0x2 0x238
FM_QSPI0_D3_HOLD 0x2 0x238
>;
};
pinctrl_pwm: pwmgrp {
thead,pins = <
FM_GPIO3_2 0x1 0x208 /* pwm0 */
FM_GPIO3_3 0x1 0x208 /* pwm1 */
>;
};
};
};
&padctrl1_apsys { /* left-pinctrl */
light-evb-padctrl1 {
/*
* Pin Configuration Node:
* Format: <pin_id mux_node config>
*/
pinctrl_uart3: uart3grp {
thead,pins = <
FM_UART3_TXD 0x0 0x72
FM_UART3_RXD 0x0 0x72
>;
};
pinctrl_uart4: uart4grp {
thead,pins = <
FM_UART4_TXD 0x0 0x72
FM_UART4_RXD 0x0 0x72
FM_UART4_CTSN 0x0 0x72
FM_UART4_RTSN 0x0 0x72
>;
};
pinctrl_qspi1: qspi1grp {
thead,pins = <
FM_QSPI1_SCLK 0x0 0x20a
FM_QSPI1_CSN0 0x3 0x20a
FM_QSPI1_D0_MOSI 0x0 0x23a
FM_QSPI1_D1_MISO 0x0 0x23a
FM_QSPI1_D2_WP 0x0 0x23a
FM_QSPI1_D3_HOLD 0x0 0x23a
>;
};
pinctrl_iso7816: iso7816grp {
thead,pins = <
FM_QSPI1_SCLK 0x1 0x208
FM_QSPI1_D0_MOSI 0x1 0x238
FM_QSPI1_D1_MISO 0x1 0x238
FM_QSPI1_D2_WP 0x1 0x238
FM_QSPI1_D3_HOLD 0x1 0x238
>;
};
};
};
&i2c2 {
clock-frequency = <400000>;
status = "okay";
eeprom@50 {
compatible = "atmel,24c32";
reg = <0x50>;
pagesize = <32>;
};
};
&i2c3 {
clock-frequency = <400000>;
status = "okay";
eeprom@50 {
compatible = "atmel,24c32";
reg = <0x50>;
pagesize = <32>;
};
};
&i2c4 {
clock-frequency = <400000>;
status = "okay";
eeprom@50 {
compatible = "atmel,24c32";
reg = <0x50>;
pagesize = <32>;
};
pcal6408ahk_a: gpio@20 {
compatible = "nxp,pcal9554b";
reg = <0x20>;
gpio-controller;
#gpio-cells = <2>;
};
};
&isp0 {
status = "disabled";
};
&isp1 {
status = "disabled";
};
&isp_ry0 {
status = "disabled";
};
&dewarp {
status = "disabled";
};
&dec400_isp0 {
status = "disabled";
};
&dec400_isp1 {
status = "disabled";
};
&dec400_isp2 {
status = "disabled";
};
&bm_visys {
status = "disabled";
};
&bm_csi0 {
status = "disabled";
};
&bm_csi1 {
status = "disabled";
};
&bm_csi2 {
status = "disabled";
};
&vi_pre {
//vi_pre_irq_en = <1>;
status = "disabled";
};
&xtensa_dsp {
status = "disabled";
};
&xtensa_dsp0 {
status = "disabled";
memory-region = <&dsp0_mem>;
};
&xtensa_dsp1{
status = "disabled";
memory-region = <&dsp1_mem>;
};
&vvcam_flash_led0{
flash_led_name = "aw36413_aw36515";
floodlight_i2c_bus = /bits/ 8 <2>;
floodlight_en_pin = <&gpio1_porta 25 0>;
//projection_i2c_bus = /bits/ 8 <2>;
flash_led_touch_pin = <&gpio1_porta 27 0>; //flash led touch pin
status = "disabled";
};
&vvcam_sensor1 {
status = "disabled";
};
&vvcam_sensor2 {
status = "disabled";
};
&vvcam_sensor3 {
status = "disabled";
};
&vvcam_sensor4 {
status = "disabled";
};
&vvcam_sensor5 {
status = "disabled";
};
&video0{
status = "disabled";
};
&video1{
status = "disabled";
};
&video2{
status = "disabled";
};
&video3{
status = "disabled";
};
&video4{
status = "disabled";
};
&video5{
status = "disabled";
};
&video6{
status = "disabled";
};
&video7{
status = "disabled";
};
&video8{
status = "disabled";
};
&video9{
status = "disabled";
};
&video10{
status = "disabled";
};
&video11{
status = "disabled";
};
&video12{
status = "disabled";
};
&trng {
status = "disabled";
};
&eip_28 {
status = "disabled";
};
&vdec {
status = "disabled";
};
&venc {
status = "disabled";
};
&isp_venc_shake {
status = "disabled";
};
&vidmem {
status = "disabled";
};
&gpu {
status = "disabled";
};
&dpu_enc0 {
status = "disabled";
};
&dpu_enc1 {
status = "disabled";
};
&dpu {
status = "disabled";
};
&dsi0 {
status = "disabled";
};
&dhost_0 {
status = "disabled";
};
&disp1_out {
status = "disabled";
};
&hdmi_tx {
status = "disabled";
};
&lightsound {
status = "disabled";
};
&light_i2s {
status = "disabled";
};
&i2s0 {
status = "disabled";
};
&i2s1 {
status = "disabled";
};
&i2s3 {
status = "disabled";
};
&khvhost {
status = "disabled";
};

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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2021 Alibaba Group Holding Limited.
*/
#include "fire-crash.dts"
&aon {
aon_reg_dialog: light-dialog-reg {
compatible = "thead,light-dialog-pmic";
status = "disabled";
dvdd_cpu_reg: appcpu_dvdd {
regulator-name = "appcpu_dvdd";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <1500000>;
regulator-boot-on;
regulator-always-on;
};
dvddm_cpu_reg: appcpu_dvddm {
regulator-name = "appcpu_dvddm";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <1500000>;
regulator-boot-on;
regulator-always-on;
};
};
};
&cpus {
c910_0: cpu@0 {
operating-points = <
/* kHz uV */
300000 600000
800000 700000
1500000 800000
1848000 1000000
>;
light,dvddm-operating-points = <
/* kHz uV */
300000 800000
800000 800000
1500000 800000
1848000 1000000
>;
};
c910_1: cpu@1 {
operating-points = <
/* kHz uV */
300000 600000
800000 700000
1500000 800000
1848000 1000000
>;
light,dvddm-operating-points = <
/* kHz uV */
300000 800000
800000 800000
1500000 800000
1848000 1000000
>;
};
c910_2: cpu@2 {
operating-points = <
/* kHz uV */
300000 600000
800000 700000
1500000 800000
1848000 1000000
>;
light,dvddm-operating-points = <
/* kHz uV */
300000 800000
800000 800000
1500000 800000
1848000 1000000
>;
};
c910_3: cpu@3 {
operating-points = <
/* kHz uV */
300000 600000
800000 700000
1500000 800000
1848000 1000000
>;
light,dvddm-operating-points = <
/* kHz uV */
300000 800000
800000 800000
1500000 800000
1848000 1000000
>;
};
};

107
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2021-2022 Alibaba Group Holding Limited.
*/
/dts-v1/;
#include "fire-emu.dts"
&gpu {
status = "okay";
};
&vosys_reg {
status = "okay";
};
&display_subsystem {
status = "okay";
};
&dpu_enc0 {
status = "okay";
ports {
/* output */
port@1 {
reg = <1>;
enc0_out: endpoint {
remote-endpoint = <&dsi0_in>;
};
};
};
};
&dpu {
status = "okay";
};
&dsi0 {
status = "okay";
};
&dhost_0 {
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dsi0_in: endpoint {
remote-endpoint = <&enc0_out>;
};
};
port@1 {
reg = <1>;
dsi0_out: endpoint {
remote-endpoint = <&panel0_in>;
};
};
};
panel0@0 {
compatible = "hlt,hpk070h275";
reg = <0>;
port {
panel0_in: endpoint {
remote-endpoint = <&dsi0_out>;
};
};
};
};
&aon {
status = "okay";
};
&mbox_910t {
status = "okay";
};
&mbox_910t_client1 {
status = "okay";
};
&mbox_910t_client2 {
status = "okay";
};
&dmac1 {
status = "okay";
};
&lightsound {
status = "okay";
};
&dmac2 {
status = "disabled";
};

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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2021-2022 Alibaba Group Holding Limited.
*/
/dts-v1/;
#include "fire-emu.dts"
&sdhci0 {
status = "okay";
};
&usb3_drd {
status = "okay";
};
&usb {
status = "okay";
};
&spi0 {
num-cs = <1>;
cs-gpios = <&gpio2_porta 15 0>; // GPIO_ACTIVE_HIGH: 0
rx-sample-delay-ns = <10>;
status = "okay";
spi_norflash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "winbond,w25q64jwm", "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <50000000>;
w25q,fast-read;
status = "okay";
};
spidev@1 {
compatible = "spidev";
#address-cells = <0x1>;
#size-cells = <0x1>;
reg = <0x1>;
spi-max-frequency = <50000000>;
};
};
&qspi0 {
num-cs = <1>;
cs-gpios = <&gpio2_porta 3 0>;
rx-sample-dly = <4>;
status = "okay";
spi-flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spi-nand";
spi-max-frequency = <100000000>;
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
reg = <0>;
partition@0 {
label = "ubi1";
reg = <0x00000000 0x08000000>;
};
};
};
&qspi1 {
num-cs = <1>;
cs-gpios = <&gpio0_porta 1 0>;
status = "okay";
spi-flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spi-nand";
spi-max-frequency = <66000000>;
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
reg = <0>;
partition@0 {
label = "ubi2";
reg = <0x00000000 0x08000000>;
};
};
};

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arch/riscv/boot/dts/thead/fire-emu-soc-c910x4.dts Normal file
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2021-2022 Alibaba Group Holding Limited.
*/
#include "fire-emu.dts"
&c910_1 {
status = "okay";
};
&c910_2 {
status = "okay";
};
&c910_3 {
status = "okay";
};

57
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2021-2022 Alibaba Group Holding Limited.
*/
/dts-v1/;
#include "fire-emu.dts"
&c910_1 {
status = "okay";
};
&vi_pre {
status = "okay";
};
&dewarp {
status = "okay";
};
&xtensa_dsp {
status = "okay";
};
&xtensa_dsp0 {
status = "okay";
};
&xtensa_dsp1 {
status = "okay";
};
&vosys_reg {
status = "okay";
};
&display_subsystem {
status = "okay";
};
&dpu {
status = "okay";
};
&hdmi_tx {
status = "okay";
};
&dsi0 {
status = "okay";
};
&dpu_enc0 {
status = "okay";
};

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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2021-2022 Alibaba Group Holding Limited.
*/
/dts-v1/;
#include "fire-emu.dts"
&c910_1 {
status = "okay";
};
&vi_pre {
status = "okay";
};
&dewarp {
status = "okay";
};
&venc {
status = "okay";
};
&vdec {
status = "okay";
};
&g2d {
status = "okay";
};
&vosys_reg {
status = "okay";
};
&display_subsystem {
status = "okay";
};
&dpu_enc0 {
status = "okay";
ports {
/* output */
port@1 {
reg = <1>;
enc0_out: endpoint {
remote-endpoint = <&dsi0_in>;
};
};
};
};
&dsi0 {
status = "okay";
};
&dhost_0 {
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dsi0_in: endpoint {
remote-endpoint = <&enc0_out>;
};
};
port@1 {
reg = <1>;
dsi0_out: endpoint {
remote-endpoint = <&panel0_in>;
};
};
};
panel0@0 {
compatible = "hlt,hpk070h275";
reg = <0>;
port {
panel0_in: endpoint {
remote-endpoint = <&dsi0_out>;
};
};
};
};
&dpu_enc1 {
ports {
/delete-node/ port@0;
};
};
&disp1_out {
remote-endpoint = <&hdmi_tx_in>;
};
&dpu {
status = "okay";
};
&hdmi_tx {
status = "okay";
port@0 {
/* input */
hdmi_tx_in: endpoint {
remote-endpoint = <&disp1_out>;
};
};
};

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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2021-2022 Alibaba Group Holding Limited.
*/
/dts-v1/;
#include "fire.dtsi"
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/gpio/gpio.h>
#include "light-vi-devices.dtsi"
/ {
model = "T-HEAD fire fpga board";
compatible = "thead,fire-emu", "thead,fire";
chosen {
bootargs = "console=ttyS0,115200 crashkernel=256M-:128M earlycon clk_ignore_unused sram=0xffe0000000,0x180000";
stdout-path = "serial0:115200n8";
};
leds {
compatible = "gpio-leds";
led0 {
label = "SYS_STATUS";
gpios = <&gpio1_porta 15 0>; /* GPIO_ACTIVE_HIGH: 0 */
default-state = "off";
};
};
lcd0_backlight: pwm-backlight@0 {
compatible = "pwm-backlight";
pwms = <&pwm 0 5000000>;
brightness-levels = <0 4 8 16 32 64 128 255>;
default-brightness-level = <7>;
};
lcd1_backlight: pwm-backlight@1 {
compatible = "pwm-backlight";
pwms = <&pwm 1 5000000>;
brightness-levels = <0 4 8 16 32 64 128 255>;
default-brightness-level = <7>;
};
light_iopmp: iopmp {
compatible = "thead,light-iopmp";
/* config#1: multiple valid regions */
iopmp_emmc: IOPMP_EMMC {
regions = <0x000000 0x100000>,
<0x100000 0x200000>;
attr = <0xFFFFFFFF>;
dummy_slave= <0x800000>;
};
/* config#2: iopmp bypass */
iopmp_sdio0: IOPMP_SDIO0 {
bypass_en;
};
/* config#3: iopmp default region set */
iopmp_sdio1: IOPMP_SDIO1 {
attr = <0xFFFFFFFF>;
is_default_region;
};
iopmp_usb0: IOPMP_USB0 {
attr = <0xFFFFFFFF>;
is_default_region;
};
iopmp_ao: IOPMP_AO {
is_default_region;
};
iopmp_aud: IOPMP_AUD {
is_default_region;
};
iopmp_chip_dbg: IOPMP_CHIP_DBG {
is_default_region;
};
iopmp_eip120i: IOPMP_EIP120I {
is_default_region;
};
iopmp_eip120ii: IOPMP_EIP120II {
is_default_region;
};
iopmp_eip120iii: IOPMP_EIP120III {
is_default_region;
};
iopmp_isp0: IOPMP_ISP0 {
is_default_region;
};
iopmp_isp1: IOPMP_ISP1 {
is_default_region;
};
iopmp_dw200: IOPMP_DW200 {
is_default_region;
};
iopmp_vipre: IOPMP_VIPRE {
is_default_region;
};
iopmp_venc: IOPMP_VENC {
is_default_region;
};
iopmp_vdec: IOPMP_VDEC {
is_default_region;
};
iopmp_g2d: IOPMP_G2D {
is_default_region;
};
iopmp0_dpu: IOPMP0_DPU {
bypass_en;
};
iopmp1_dpu: IOPMP1_DPU {
bypass_en;
};
iopmp_gpu: IOPMP_GPU {
is_default_region;
};
iopmp_gmac1: IOPMP_GMAC1 {
is_default_region;
};
iopmp_gmac2: IOPMP_GMAC2 {
is_default_region;
};
iopmp_dmac: IOPMP_DMAC {
is_default_region;
};
iopmp_tee_dmac: IOPMP_TEE_DMAC {
is_default_region;
};
iopmp_dsp0: IOPMP_DSP0 {
is_default_region;
};
iopmp_dsp1: IOPMP_DSP1 {
is_default_region;
};
};
mbox_910t_client1: mbox_910t_client1 {
compatible = "thead,light-mbox-client";
mbox-names = "902";
mboxes = <&mbox_910t 1 0>;
status = "disabled";
};
mbox_910t_client2: mbox_910t_client2 {
compatible = "thead,light-mbox-client";
mbox-names = "906";
mboxes = <&mbox_910t 2 0>;
status = "disabled";
};
lightsound: lightsound@1 {
compatible = "simple-audio-card";
simple-audio-card,name = "Light-Sound-Card";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
dummy_codec: dummy_codec {
#sound-dai-cells = <1>;
compatible = "linux,bt-sco";
status = "okay";
};
wcn_wifi: wireless-wlan {
compatible = "wlan-platdata";
clock-names = "clk_wifi";
ref-clock-frequency = <24000000>;
keep_wifi_power_on;
pinctrl-names = "default";
wifi_chip_type = "rtl8723ds";
WIFI,poweren_gpio = <&gpio2_porta 26 0>;
WIFI,reset_n = <&gpio2_porta 28 0>;
status = "disabled";
};
wcn_bt: wireless-bluetooth {
compatible = "bluetooth-platdata";
pinctrl-names = "default", "rts_gpio";
BT,power_gpio = <&gpio2_porta 29 0>;
status = "disabled";
};
gpio_keys: gpio_keys{
compatible = "gpio-keys";
pinctrl-names = "default";
status = "disabled";
key-volumedown {
label = "Volume Down Key";
linux,code = <KEY_1>;
debounce-interval = <2>;
gpios = <&ao_gpio_porta 4 GPIO_ACTIVE_LOW>;
};
key-volumeup {
label = "Volume Up Key";
linux,code = <KEY_2>;
debounce-interval = <2>;
gpios = <&ao_gpio_porta 5 GPIO_ACTIVE_LOW>;
};
};
aon: light-aon {
compatible = "thead,light-aon";
mbox-names = "aon";
mboxes = <&mbox_910t 1 0>;
status = "disabled";
pd: light-aon-pd {
compatible = "thead,light-aon-pd";
#power-domain-cells = <1>;
status = "disabled";
};
aon_reg_dialog: light-dialog-reg {
compatible = "thead,light-dialog-pmic";
status = "disabled";
};
c910_cpufreq {
compatible = "thead,light-mpw-cpufreq";
status = "disabled";
};
test: light-aon-test {
compatible = "thead,light-aon-test";
status = "disabled";
};
};
};
&cmamem {
alloc-ranges = <0 0xe4000000 0 0x14000000>; // [0xE400_0000 ~ 0xF800_0000]
};
&resmem {
#address-cells = <2>;
#size-cells = <2>;
ranges;
tee_mem: memory@1a000000 {
reg = <0x0 0x1a000000 0 0x4000000>;
no-map;
};
dsp0_mem: memory@20000000 { /**0x2000_0000~0x2040_0000 4M**/
reg = <0x0 0x20000000 0x0 0x00280000 /* DSP FW code&data section 2.5M*/
0x0 0x20280000 0x0 0x00001000 /* DSP communication area 4K*/
0x0 0x20281000 0x0 0x00007000 /* Panic/log page 28K */
0x0 0x20288000 0x0 0x00178000>; /* DSP shared memory 1.5M-32K*/
no-map;
};
dsp1_mem: memory@20400000 { /**0x2040_0000~0x2080_0000 4M**/
reg = <0x0 0x20400000 0x0 0x00280000 /* DSP FW code&data section */
0x0 0x20680000 0x0 0x00001000 /* DSP communication area */
0x0 0x20681000 0x0 0x00007000 /* Panic/log page*/
0x0 0x20688000 0x0 0x00178000>; /* DSP shared memory */
no-map;
};
vi_mem: framebuffer@0f800000 {
reg = <0x0 0x0F800000 0x0 0x05400000 /* vi_mem_pool_region[0] 84 MB (default) */
0x0 0x14C00000 0x0 0x01D00000 /* vi_mem_pool_region[1] 29 MB */
0x0 0x16900000 0x0 0x03200000>; /* vi_mem_pool_region[2] 50 MB */
no-map;
};
facelib_mem: memory@22000000 {
reg = <0x0 0x22000000 0x0 0x10000000>;
no-map;
};
};
&clk {
status = "disabled";
};
&i2c0 {
clock-frequency = <400000>;
status = "okay";
eeprom@50 {
compatible = "atmel,24c32";
reg = <0x50>;
pagesize = <32>;
};
codec: wm8960@1a {
#sound-dai-cells = <0>;
compatible = "wlf,wm8960";
reg = <0x1a>;
wlf,shared-lrclk;
wlf,hp-cfg = <3 2 3>;
wlf,gpio-cfg = <1 3>;
};
touch@5d {
#gpio-cells = <2>;
compatible = "goodix,gt911";
status = "disabled";
reg = <0x5d>;
interrupt-parent = <&gpio1_porta>;
interrupts = <8 0>;
irq-gpios = <&gpio1_porta 8 0>;
reset-gpios = <&gpio1_porta 7 0>;
touchscreen-size-x = <800>;
touchscreen-size-y = <1280>;
};
};
&audio_i2c0 {
clock-frequency = <100000>;
status = "disabled";
es8156_audio_codec: es8156@8 {
#sound-dai-cells = <0>;
compatible = "everest,es8156";
reg = <0x08>;
};
es7210_audio_codec: es7210@40 {
#sound-dai-cells = <0>;
compatible = "MicArray_0";
reg = <0x40>;
};
};
&i2c1 {
clock-frequency = <400000>;
status = "disabled";
touch1@5d {
#gpio-cells = <2>;
compatible = "goodix,gt911";
reg = <0x5d>;
interrupt-parent = <&gpio1_porta>;
interrupts = <12 0>;
irq-gpios = <&gpio1_porta 12 0>;
reset-gpios = <&gpio1_porta 11 0>;
touchscreen-size-x = <800>;
touchscreen-size-y = <1280>;
};
};
&spi0 {
num-cs = <1>;
cs-gpios = <&gpio2_porta 15 0>; // GPIO_ACTIVE_HIGH: 0
rx-sample-delay-ns = <10>;
status = "okay";
spi_norflash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "winbond,w25q64jwm", "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <50000000>;
w25q,fast-read;
status = "disabled";
};
spidev@1 {
compatible = "spidev";
#address-cells = <0x1>;
#size-cells = <0x1>;
reg = <0x1>;
spi-max-frequency = <50000000>;
};
};
&qspi0 {
status = "disabled";
};
&qspi1 {
status = "disabled";
};
&gmac0 {
max-speed = <100>;
phy-mode = "mii";
phy-handle = <&phy_88E1111_0>;
status = "okay";
mdio0 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,dwmac-mdio";
phy_88E1111_0: ethernet-phy@0 {
reg = <0x0>;
};
};
};
&emmc {
max-frequency = <198000000>;
non-removable;
/*mmc-hs400-1_8v;*/
io_fixed_1v8;
is_emmc;
no-sdio;
no-sd;
pull_up;
bus-width = <8>;
status = "okay";
};
&sdhci0 {
max-frequency = <198000000>;
bus-width = <4>;
pull_up;
wprtn_ignore;
status = "disabled";
};
&sdhci1 {
max-frequency = <100000000>;
bus-width = <4>;
pull_up;
no-sd;
no-mmc;
non-removable;
io_fixed_1v8;
post-power-on-delay-ms = <50>;
wprtn_ignore;
cap-sd-highspeed;
keep-power-in-suspend;
wakeup-source;
status = "disabled";
};
&padctrl0_apsys { /* right-pinctrl */
light-evb-padctrl0 {
/*
* Pin Configuration Node:
* Format: <pin_id mux_node config>
*/
pinctrl_uart0: uart0grp {
thead,pins = <
FM_UART0_TXD 0x0 0x72
FM_UART0_RXD 0x0 0x72
>;
};
pinctrl_spi0: spi0grp {
thead,pins = <
FM_SPI_CSN 0x3 0x20a
FM_SPI_SCLK 0x0 0x20a
FM_SPI_MISO 0x0 0x23a
FM_SPI_MOSI 0x0 0x23a
>;
};
pinctrl_qspi0: qspi0grp {
thead,pins = <
FM_QSPI0_SCLK 0x0 0x20f
FM_QSPI0_CSN0 0x3 0x20f
FM_QSPI0_CSN1 0x0 0x20f
FM_QSPI0_D0_MOSI 0x0 0x23f
FM_QSPI0_D1_MISO 0x0 0x23f
FM_QSPI0_D2_WP 0x0 0x23f
FM_QSPI0_D3_HOLD 0x0 0x23f
>;
};
pinctrl_audio_i2s0: i2s0grp {
thead,pins = <
FM_QSPI0_SCLK 0x2 0x208
FM_QSPI0_CSN0 0x2 0x238
FM_QSPI0_CSN1 0x2 0x208
FM_QSPI0_D0_MOSI 0x2 0x238
FM_QSPI0_D1_MISO 0x2 0x238
FM_QSPI0_D2_WP 0x2 0x238
FM_QSPI0_D3_HOLD 0x2 0x238
>;
};
pinctrl_pwm: pwmgrp {
thead,pins = <
FM_GPIO3_2 0x1 0x208 /* pwm0 */
FM_GPIO3_3 0x1 0x208 /* pwm1 */
>;
};
};
};
&padctrl1_apsys { /* left-pinctrl */
light-evb-padctrl1 {
/*
* Pin Configuration Node:
* Format: <pin_id mux_node config>
*/
pinctrl_uart3: uart3grp {
thead,pins = <
FM_UART3_TXD 0x0 0x72
FM_UART3_RXD 0x0 0x72
>;
};
pinctrl_uart4: uart4grp {
thead,pins = <
FM_UART4_TXD 0x0 0x72
FM_UART4_RXD 0x0 0x72
FM_UART4_CTSN 0x0 0x72
FM_UART4_RTSN 0x0 0x72
>;
};
pinctrl_qspi1: qspi1grp {
thead,pins = <
FM_QSPI1_SCLK 0x0 0x20a
FM_QSPI1_CSN0 0x3 0x20a
FM_QSPI1_D0_MOSI 0x0 0x23a
FM_QSPI1_D1_MISO 0x0 0x23a
FM_QSPI1_D2_WP 0x0 0x23a
FM_QSPI1_D3_HOLD 0x0 0x23a
>;
};
pinctrl_iso7816: iso7816grp {
thead,pins = <
FM_QSPI1_SCLK 0x1 0x208
FM_QSPI1_D0_MOSI 0x1 0x238
FM_QSPI1_D1_MISO 0x1 0x238
FM_QSPI1_D2_WP 0x1 0x238
FM_QSPI1_D3_HOLD 0x1 0x238
>;
};
};
};
&i2c2 {
clock-frequency = <400000>;
status = "okay";
eeprom@50 {
compatible = "atmel,24c32";
reg = <0x50>;
pagesize = <32>;
};
};
&i2c3 {
clock-frequency = <400000>;
status = "okay";
eeprom@50 {
compatible = "atmel,24c32";
reg = <0x50>;
pagesize = <32>;
};
};
&i2c4 {
clock-frequency = <400000>;
status = "okay";
eeprom@50 {
compatible = "atmel,24c32";
reg = <0x50>;
pagesize = <32>;
};
pcal6408ahk_a: gpio@20 {
compatible = "nxp,pcal9554b";
reg = <0x20>;
gpio-controller;
#gpio-cells = <2>;
};
};
&isp0 {
status = "disabled";
};
&isp1 {
status = "disabled";
};
&isp_ry0 {
status = "disabled";
};
&dewarp {
status = "disabled";
};
&dec400_isp0 {
status = "disabled";
};
&dec400_isp1 {
status = "disabled";
};
&dec400_isp2 {
status = "disabled";
};
&bm_visys {
status = "disabled";
};
&bm_csi0 {
status = "disabled";
};
&bm_csi1 {
status = "disabled";
};
&bm_csi2 {
status = "disabled";
};
&vi_pre {
//vi_pre_irq_en = <1>;
status = "disabled";
};
&xtensa_dsp {
status = "disabled";
};
&xtensa_dsp0 {
status = "disabled";
memory-region = <&dsp0_mem>;
};
&xtensa_dsp1{
status = "disabled";
memory-region = <&dsp1_mem>;
};
&vvcam_flash_led0{
flash_led_name = "aw36413_aw36515";
floodlight_i2c_bus = /bits/ 8 <2>;
floodlight_en_pin = <&gpio1_porta 25 0>;
//projection_i2c_bus = /bits/ 8 <2>;
flash_led_touch_pin = <&gpio1_porta 27 0>; //flash led touch pin
status = "disabled";
};
&trng {
status = "disabled";
};
&eip_28 {
status = "okay";
};
&vdec {
status = "disabled";
};
&venc {
status = "disabled";
};
&isp_venc_shake {
status = "disabled";
};
&vidmem {
status = "okay";
memory-region = <&vi_mem>;
};
&gpu {
status = "disabled";
};
&cpus {
c910_0: cpu@0 {
operating-points = <
/* kHz uV */
300000 650000
800000 700000
1500000 800000
1848000 1000000
>;
light,dvddm-operating-points = <
/* kHz uV */
300000 800000
800000 800000
1500000 800000
1848000 1000000
>;
};
c910_1: cpu@1 {
status = "disabled";
operating-points = <
/* kHz uV */
300000 650000
800000 700000
1500000 800000
1848000 1000000
>;
light,dvddm-operating-points = <
/* kHz uV */
300000 800000
800000 800000
1500000 800000
1848000 1000000
>;
};
c910_2: cpu@2 {
status = "disabled";
operating-points = <
/* kHz uV */
300000 650000
800000 700000
1500000 800000
1848000 1000000
>;
light,dvddm-operating-points = <
/* kHz uV */
300000 800000
800000 800000
1500000 800000
1848000 1000000
>;
};
c910_3: cpu@3 {
status = "disabled";
operating-points = <
/* kHz uV */
300000 650000
800000 700000
1500000 800000
1848000 1000000
>;
light,dvddm-operating-points = <
/* kHz uV */
300000 800000
800000 800000
1500000 800000
1848000 1000000
>;
};
};
&thermal_zones {
cpu-thermal-zone {
status = "disabled";
};
};
&dummy_clock_apb {
clock-frequency = <50000000>;
};
&uart0 {
clocks = <&dummy_clock_apb>;
};
&uart1 {
clocks = <&dummy_clock_apb>;
};
&uart2 {
clocks = <&dummy_clock_apb>;
};
&uart3 {
clocks = <&dummy_clock_apb>;
};
&uart4 {
clocks = <&dummy_clock_apb>;
};
&uart5 {
clocks = <&dummy_clock_apb>;
};
&usb3_drd {
status = "disabled";
};
&usb {
status = "disabled";
};
&dspsys_reg {
status = "disabled";
};
&audio_ioctrl {
status = "disabled";
};
&audio_cpr {
status = "disabled";
};
&timer0 {
clock-frequency = <50000000>;
};
&timer1 {
clock-frequency = <50000000>;
};
&timer2 {
clock-frequency = <50000000>;
};
&timer3 {
clock-frequency = <50000000>;
};
&g2d {
status = "disabled";
};
&vosys_reg {
status = "disabled";
};
&dmac2 {
status = "disabled";
};
&sdhci1 {
status = "disabled";
};
&pvt {
status = "disabled";
};
&audio_i2c0 {
status = "disabled";
};
&csia_reg {
status = "disabled";
};
&visys_clk_gate { /* VI_SYSREG_R */
status = "disabled";
};
&vpsys_clk_gate { /* VP_SYSREG_R */
status = "disabled";
};
&vosys_clk_gate { /* VO_SYSREG_R */
status = "disabled";
};
&dspsys_clk_gate {
status = "disabled";
};
&watchdog0 {
status = "disabled";
};
&watchdog1 {
status = "disabled";
};

2094
arch/riscv/boot/dts/thead/fire.dtsi Normal file
View File

File diff suppressed because it is too large Load Diff

46
arch/riscv/boot/dts/thead/light-a-product.dts
View File

@@ -13,8 +13,6 @@
chosen {
bootargs = "console=ttyS0,115200 crashkernel=256M-:128M earlycon clk_ignore_unused sram=0xffe0000000,0x180000";
linux,initrd-start = <0x0 0x2000000>;
linux,initrd-end = <0x0 0x14600000>;
stdout-path = "serial0:115200n8";
};
@@ -465,6 +463,10 @@
};
};
&cmamem {
alloc-ranges = <0 0xe4000000 0 0x14000000>; // [0xE400_0000 ~ 0xF800_0000]
};
&resmem {
#address-cells = <2>;
#size-cells = <2>;
@@ -488,14 +490,16 @@
0x0 0x20688000 0x0 0x00178000>; /* DSP shared memory */
no-map;
};
facelib_mem: memory@d0000000 {
reg = <0x0 0xd0000000 0 0x10000000>;
vi_mem: framebuffer@0f800000 {
reg = <0x0 0x0F800000 0x0 0x05400000 /* vi_mem_pool_region[0] 84 MB (default) */
0x0 0x14C00000 0x0 0x01D00000 /* vi_mem_pool_region[1] 29 MB */
0x0 0x16900000 0x0 0x03200000>; /* vi_mem_pool_region[2] 50 MB */
no-map;
};
vi_mem: framebuffer@70000000 {
reg = <0x0 0x70000000 0 0xbc00000>;
facelib_mem: memory@22000000 {
reg = <0x0 0x22000000 0x0 0x10000000>;
no-map;
};
};
};
&adc {
@@ -504,7 +508,7 @@
};
&i2c0 {
clock-frequency = <100000>;
clock-frequency = <400000>;
status = "okay";
eeprom@50 {
@@ -531,13 +535,13 @@
irq-gpios = <&gpio1_porta 8 0>;
reset-gpios = <&gpio1_porta 7 0>;
AVDD28-supply = <&reg_tp_pwr_en>;
touchscreen-size-x = <720>;
touchscreen-size-x = <800>;
touchscreen-size-y = <1280>;
};
};
&i2c1 {
clock-frequency = <100000>;
clock-frequency = <400000>;
status = "okay";
touch1@5d {
#gpio-cells = <2>;
@@ -548,7 +552,7 @@
irq-gpios = <&gpio1_porta 12 0>;
reset-gpios = <&gpio1_porta 11 0>;
AVDD28-supply = <&reg_tp1_pwr_en>;
touchscreen-size-x = <720>;
touchscreen-size-x = <800>;
touchscreen-size-y = <1280>;
};
};
@@ -683,6 +687,7 @@
no-mmc;
non-removable;
io_fixed_1v8;
post-power-on-delay-ms = <50>;
wprtn_ignore;
cap-sd-highspeed;
keep-power-in-suspend;
@@ -815,6 +820,7 @@
};
&i2c2 {
clock-frequency = <400000>;
status = "okay";
eeprom@50 {
@@ -825,6 +831,7 @@
};
&i2c3 {
clock-frequency = <400000>;
status = "okay";
eeprom@50 {
@@ -835,6 +842,7 @@
};
&i2c4 {
clock-frequency = <400000>;
status = "okay";
eeprom@50 {
@@ -965,8 +973,8 @@
&video0{
status = "okay";
piplane0 {
pipline_id = <0>;
channel0 {
channel_id = <0>;
status = "okay";
sensor0 {
subdev_name = "vivcam";
@@ -990,8 +998,8 @@
&video1{
status = "okay";
piplane0 { // VSE0
pipline_id = <0>;
channel0 { // VSE0
channel_id = <0>;
status = "okay";
sensor0 {
subdev_name = "vivcam";
@@ -1015,8 +1023,8 @@
&video2{
status = "okay";
piplane0 {
pipline_id = <0>;
channel0 {
channel_id = <0>;
status = "okay";
sensor0 {
subdev_name = "vivcam";
@@ -1036,8 +1044,8 @@
path_type = "DSP_PATH_VIPRE_ODD";
};
};
piplane1 {
pipline_id = <1>;
channel1 {
channel_id = <1>;
status = "okay";
sensor0 {
subdev_name = "vivcam";

29
arch/riscv/boot/dts/thead/light-a-ref-dsi0-hdmi.dts Normal file
View File

@@ -0,0 +1,29 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2021 Alibaba Group Holding Limited.
*/
/dts-v1/;
#include "light-a-ref-dsi0.dts"
&dpu_enc1 {
ports {
/delete-node/ port@0;
};
};
&disp1_out {
remote-endpoint = <&hdmi_tx_in>;
};
&hdmi_tx {
status = "okay";
port@0 {
/* input */
hdmi_tx_in: endpoint {
remote-endpoint = <&disp1_out>;
};
};
};

75
arch/riscv/boot/dts/thead/light-a-ref-dsi0.dts Normal file
View File

@@ -0,0 +1,75 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2021 Alibaba Group Holding Limited.
*/
/dts-v1/;
#include "light-a-ref.dts"
/ {
display-subsystem {
status = "okay";
};
};
&dpu_enc0 {
status = "okay";
ports {
/* output */
port@1 {
reg = <1>;
enc0_out: endpoint {
remote-endpoint = <&dsi0_in>;
};
};
};
};
&dpu {
status = "okay";
};
&dsi0 {
status = "okay";
};
&dhost_0 {
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dsi0_in: endpoint {
remote-endpoint = <&enc0_out>;
};
};
port@1 {
reg = <1>;
dsi0_out: endpoint {
remote-endpoint = <&panel0_in>;
};
};
};
panel0@0 {
compatible = "txd,dy800qwxpab";
reg = <0>;
backlight = <&lcd0_backlight>;
reset-gpio = <&gpio1_porta 5 1>; /* active low */
vdd1v8-supply = <&lcd0_1v8>;
vspn5v7-supply = <&lcd0_5v7>;
port {
panel0_in: endpoint {
remote-endpoint = <&dsi0_out>;
};
};
};
};

5
arch/riscv/boot/dts/thead/light-a-ref.dts Normal file
View File

@@ -0,0 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2021 Alibaba Group Holding Limited.
*/
#include "light-a-val.dts"

89
arch/riscv/boot/dts/thead/light-a-val-audio-hdmi.dts Normal file
View File

@@ -0,0 +1,89 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2021 Alibaba Group Holding Limited.
*/
/dts-v1/;
#include "light-a-val.dts"
/ {
display-subsystem {
status = "okay";
};
};
&dpu_enc1 {
ports {
/delete-node/ port@0;
};
};
&disp1_out {
remote-endpoint = <&hdmi_tx_in>;
};
&dpu {
status = "okay";
};
&hdmi_tx {
status = "okay";
port@0 {
/* input */
hdmi_tx_in: endpoint {
remote-endpoint = <&disp1_out>;
};
};
};
&lightsound {
status = "okay";
simple-audio-card,dai-link@0 { /* I2S - AUDIO SYS CODEC 8156*/
reg = <0>;
format = "i2s";
cpu {
sound-dai = <&i2s0 0>;
};
codec {
sound-dai = <&es8156_audio_codec>;
};
};
simple-audio-card,dai-link@1 { /* I2S - AUDIO SYS CODEC 7210*/
reg = <1>;
format = "i2s";
cpu {
sound-dai = <&i2s3 0>;
};
codec {
sound-dai = <&es7210_audio_codec>;
};
};
simple-audio-card,dai-link@2 { /* I2S - HDMI */
reg = <2>;
format = "i2s";
cpu {
sound-dai = <&light_i2s 1>;
};
codec {
sound-dai = <&dummy_codec 2>;
};
};
};
&light_i2s {
status = "okay";
};
&i2s0 {
status = "okay";
};
&i2s3 {
status = "okay";
};

98
arch/riscv/boot/dts/thead/light-a-val-crash.dts Normal file
View File

@@ -0,0 +1,98 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2021 Alibaba Group Holding Limited.
*/
#include "light-crash.dts"
&aon {
aon_reg_dialog: light-dialog-reg {
compatible = "thead,light-dialog-pmic";
status = "okay";
dvdd_cpu_reg: appcpu_dvdd {
regulator-name = "appcpu_dvdd";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <1500000>;
regulator-boot-on;
regulator-always-on;
};
dvddm_cpu_reg: appcpu_dvddm {
regulator-name = "appcpu_dvddm";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <1500000>;
regulator-boot-on;
regulator-always-on;
};
};
};
&cpus {
c910_0: cpu@0 {
operating-points = <
/* kHz uV */
300000 600000
800000 700000
1500000 800000
1848000 1000000
>;
light,dvddm-operating-points = <
/* kHz uV */
300000 800000
800000 800000
1500000 800000
1848000 1000000
>;
};
c910_1: cpu@1 {
operating-points = <
/* kHz uV */
300000 600000
800000 700000
1500000 800000
1848000 1000000
>;
light,dvddm-operating-points = <
/* kHz uV */
300000 800000
800000 800000
1500000 800000
1848000 1000000
>;
};
c910_2: cpu@2 {
operating-points = <
/* kHz uV */
300000 600000
800000 700000
1500000 800000
1848000 1000000
>;
light,dvddm-operating-points = <
/* kHz uV */
300000 800000
800000 800000
1500000 800000
1848000 1000000
>;
};
c910_3: cpu@3 {
operating-points = <
/* kHz uV */
300000 600000
800000 700000
1500000 800000
1848000 1000000
>;
light,dvddm-operating-points = <
/* kHz uV */
300000 800000
800000 800000
1500000 800000
1848000 1000000
>;
};
};

4
arch/riscv/boot/dts/thead/light-a-val-ddr1G.dts
View File

@@ -16,6 +16,6 @@
};
&cmamem {
size = <0 0x8c00000>;
alloc-ranges = <0 0x35000000 0 0x3dc00000>;
size = <0 0x8c00000>; // 140MB by default
alloc-ranges = <0 0x02000000 0 0x0cc00000>; // [0x0600_0000 ~ 0x0EC0_0000]
};

6
arch/riscv/boot/dts/thead/light-a-val-ddr2G.dts
View File

@@ -15,7 +15,11 @@
};
};
&cmamem {
alloc-ranges = <0 0x64000000 0 0x14000000>; // [0x6400_0000 ~ 0x7800_0000]
};
&facelib_mem {
reg = <0x0 0x33000000 0 0x02000000>;
reg = <0x0 0x22000000 0 0x02000000>;
no-map;
};

431
arch/riscv/boot/dts/thead/light-a-val.dts
View File

@@ -16,8 +16,6 @@
chosen {
bootargs = "console=ttyS0,115200 crashkernel=256M-:128M earlycon clk_ignore_unused sram=0xffe0000000,0x180000";
linux,initrd-start = <0x0 0x2000000>;
linux,initrd-end = <0x0 0x14600000>;
stdout-path = "serial0:115200n8";
};
@@ -405,6 +403,8 @@
};
soc_dovdd18_scan_reg: soc_dovdd18_scan {
regulator-name = "soc_dovdd18_scan";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <3600000>;
};
soc_vext_2v8_reg: soc_vext_2v8 {
regulator-name = "soc_vext_2v8";
@@ -413,37 +413,51 @@
};
soc_dvdd12_scan_reg: soc_dvdd12_scan {
regulator-name = "soc_dvdd12_scan";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <3600000>;
};
soc_avdd28_scan_en_reg: soc_avdd28_scan_en {
regulator-name = "soc_avdd28_scan_en";
};
soc_avdd28_rgb_reg: soc_avdd28_rgb {
regulator-name = "soc_avdd28_rgb";
regulator-min-microvolt = <2200000>;
regulator-max-microvolt = <3475000>;
regulator-boot-on;
regulator-always-on;
};
soc_dovdd18_rgb_reg: soc_dovdd18_rgb {
regulator-name = "soc_dovdd18_rgb";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3600000>;
regulator-boot-on;
regulator-always-on;
};
soc_dvdd12_rgb_reg: soc_dvdd12_rgb {
regulator-name = "soc_dvdd12_rgb";
regulator-min-microvolt = <400000>;
regulator-max-microvolt = <1675000>;
regulator-boot-on;
regulator-always-on;
};
soc_avdd25_ir_reg: soc_avdd25_ir {
regulator-name = "soc_avdd25_ir";
regulator-min-microvolt = <2200000>;
regulator-max-microvolt = <3475000>;
regulator-boot-on;
regulator-always-on;
};
soc_dovdd18_ir_reg: soc_dovdd18_ir {
regulator-name = "soc_dovdd18_ir";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3600000>;
regulator-boot-on;
regulator-always-on;
};
soc_dvdd12_ir_reg: soc_dvdd12_ir {
regulator-name = "soc_dvdd12_ir";
regulator-min-microvolt = <400000>;
regulator-max-microvolt = <1675000>;
regulator-boot-on;
regulator-always-on;
};
@@ -461,6 +475,10 @@
};
};
&cmamem {
alloc-ranges = <0 0xe4000000 0 0x14000000>; // [0xE400_0000 ~ 0xF800_0000]
};
&resmem {
#address-cells = <2>;
#size-cells = <2>;
@@ -484,17 +502,17 @@
0x0 0x20688000 0x0 0x00178000>; /* DSP shared memory */
no-map;
};
facelib_mem: memory@d0000000 {
reg = <0x0 0xd0000000 0x0 0x10000000>;
vi_mem: framebuffer@0f800000 {
reg = <0x0 0x0F800000 0x0 0x05400000 /* vi_mem_pool_region[0] 84 MB (default) */
0x0 0x14C00000 0x0 0x01D00000 /* vi_mem_pool_region[1] 29 MB */
0x0 0x16900000 0x0 0x03200000>; /* vi_mem_pool_region[2] 50 MB */
no-map;
};
facelib_mem: memory@22000000 {
reg = <0x0 0x22000000 0x0 0x10000000>;
no-map;
};
vi_mem: framebuffer@70000000 {
reg = <0x0 0x70000000 0x0 0x05400000 /* vi_mem_pool_region[0] 84 MB (default) */
0x0 0x75400000 0x0 0x01D00000 /* vi_mem_pool_region[1] 29 MB */
0x0 0x77100000 0x0 0x03200000>; /* vi_mem_pool_region[2] 50 MB */
no-map;
};
};
&adc {
@@ -503,7 +521,7 @@
};
&i2c0 {
clock-frequency = <100000>;
clock-frequency = <400000>;
status = "okay";
eeprom@50 {
@@ -530,7 +548,7 @@
irq-gpios = <&gpio1_porta 8 0>;
reset-gpios = <&gpio1_porta 7 0>;
AVDD28-supply = <&reg_tp_pwr_en>;
touchscreen-size-x = <720>;
touchscreen-size-x = <800>;
touchscreen-size-y = <1280>;
};
};
@@ -553,7 +571,7 @@
};
&i2c1 {
clock-frequency = <100000>;
clock-frequency = <400000>;
status = "okay";
touch1@5d {
#gpio-cells = <2>;
@@ -564,7 +582,7 @@
irq-gpios = <&gpio1_porta 12 0>;
reset-gpios = <&gpio1_porta 11 0>;
AVDD28-supply = <&reg_tp1_pwr_en>;
touchscreen-size-x = <720>;
touchscreen-size-x = <800>;
touchscreen-size-y = <1280>;
};
};
@@ -699,6 +717,7 @@
no-mmc;
non-removable;
io_fixed_1v8;
post-power-on-delay-ms = <50>;
wprtn_ignore;
cap-sd-highspeed;
keep-power-in-suspend;
@@ -837,8 +856,8 @@
};
&i2c2 {
clock-frequency = <400000>;
status = "okay";
eeprom@50 {
compatible = "atmel,24c32";
reg = <0x50>;
@@ -847,8 +866,8 @@
};
&i2c3 {
clock-frequency = <400000>;
status = "okay";
eeprom@50 {
compatible = "atmel,24c32";
reg = <0x50>;
@@ -857,8 +876,8 @@
};
&i2c4 {
clock-frequency = <400000>;
status = "okay";
eeprom@50 {
compatible = "atmel,24c32";
reg = <0x50>;
@@ -948,9 +967,10 @@
&vvcam_sensor0 {
sensor_name = "SC2310";
sensor_regulators = "DOVDD18_RGB", "DVDD12_RGB", "AVDD28_RGB";
sensor_regulator_voltage_uV = <1800000 1200000 2800000>;
sensor_regulator_timing_us = <70 50 20>;
sensor_rst = <&gpio1_porta 16 0>;
sensor_pdn_delay_us = <1000>; //powerdown pin / shutdown pin actived till I2C ready
sensor_pdn_delay_us = <4000>; //powerdown pin / shutdown pin actived till I2C ready
DOVDD18_RGB-supply = <&soc_dovdd18_rgb_reg>;
DVDD12_RGB-supply = <&soc_dvdd12_rgb_reg>;
AVDD28_RGB-supply = <&soc_avdd28_rgb_reg>;
@@ -990,22 +1010,26 @@
sensor_name = "SC2310";
sensor_regulators = "DOVDD18_SCAN", "DVDD12_SCAN", "AVDD28_SCAN";
sensor_regulator_timing_us = <70 50 20>;
//sensor_pdn = <&gpio1_porta 30 0>; //powerdown pin / shutdown pin
//sensor_rst = <&gpio1_porta 29 0>;
sensor_pdn = <&gpio1_porta 30 0>; //powerdown pin / shutdown pin
sensor_rst = <&gpio1_porta 29 0>;
sensor_pdn_delay_us = <4000>; //powerdown pin / shutdown pin actived till I2C ready
DOVDD18_SCAN-supply = <&soc_dovdd18_scan_reg>;
DVDD12_SCAN-supply = <&soc_dvdd12_scan_reg>;
AVDD28_SCAN-supply = <&soc_avdd28_scan_en_reg>;
i2c_bus = /bits/ 8 <4>;
i2c_reg_width = /bits/ 8 <2>;
i2c_data_width = /bits/ 8 <1>;
i2c_addr = /bits/ 8 <0x30>;
status = "okay";
};
&vvcam_sensor4 {
sensor_name = "SC132GS";
sensor_regulators = "DOVDD18_IR", "DVDD12_IR", "AVDD25_IR";
sensor_regulator_timing_us = <70 50 20>;
sensor_regulator_timing_us = <70 1000 2000>;
i2c_addr = /bits/ 8 <0x31>;
sensor_rst = <&gpio1_porta 24 0>;
sensor_pdn_delay_us = <1000>; //powerdown pin / shutdown pin actived till I2C ready
sensor_pdn_delay_us = <2000>; //powerdown pin / shutdown pin actived till I2C ready
DOVDD18_IR-supply = <&soc_dovdd18_ir_reg>;
DVDD12_IR-supply = <&soc_dvdd12_ir_reg>;
AVDD25_IR-supply = <&soc_avdd25_ir_reg>;
@@ -1018,8 +1042,9 @@
&vvcam_sensor5 {
sensor_name = "OV12870";
sensor_regulators = "DOVDD18_RGB", "DVDD12_RGB", "AVDD28_RGB";
sensor_regulator_voltage_uV = <1800000 1200000 2800000>;
sensor_regulator_timing_us = <100 50 0>;
//sensor_rst = <&gpio1_porta 16 0>;
sensor_rst = <&gpio1_porta 16 0>;
sensor_pdn_delay_us = <60>; //powerdown pin / shutdown pin actived till I2C ready
DOVDD18_RGB-supply = <&soc_dovdd18_rgb_reg>;
DVDD12_RGB-supply = <&soc_dvdd12_rgb_reg>;
@@ -1031,20 +1056,39 @@
status = "okay";
};
&vvcam_sensor6 {
sensor_name = "GC02M1B";
sensor_regulators = "DOVDD18_RGB", "DVDD12_RGB", "AVDD28_RGB";
sensor_regulator_voltage_uV = <1800000 1675000 2800000>;
sensor_regulator_timing_us = <70 50 20>;
sensor_rst = <&gpio1_porta 16 0>;
sensor_pdn_delay_us = <1000>; //powerdown pin / shutdown pin actived till I2C ready
DOVDD18_RGB-supply = <&soc_dovdd18_rgb_reg>;
DVDD12_RGB-supply = <&soc_dvdd12_rgb_reg>;
AVDD28_RGB-supply = <&soc_avdd28_rgb_reg>;
i2c_reg_width = /bits/ 8 <1>;
i2c_data_width = /bits/ 8 <1>;
i2c_addr = /bits/ 8 <0x37>;
i2c_bus = /bits/ 8 <3>;
status = "okay";
};
&video0{
vi_mem_pool_region = <2>; // vi_mem: framebuffer, region[2]
pipline0 {
channel0 {
sensor0 {
subdev_name = "vivcam";
idx = <2>; //<2>=vivcam2 : gc5035
csi_idx = <1>; //<1>=CSI2X2_B
path_type = "SENSOR_1080P_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER//
mode_idx = <3>;
path_type = "SENSOR_1296x972_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER//
};
sensor1 {
subdev_name = "vivcam";
idx = <3>; //<3>=vivcam3 : sc2310
csi_idx = <1>; //<1>=CSI2X2_B
path_type = "SENSOR_1080P_RAW12_LINER";
mode_idx = <1>;
path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER";
};
isp {
subdev_name = "isp";
@@ -1058,18 +1102,20 @@
};
};
};
pipline1 {
channel1 {
sensor0 {
subdev_name = "vivcam";
idx = <2>; //<2>=vivcam2 : gc5035
csi_idx = <1>; //<1>=CSI2X2_B
path_type = "SENSOR_1080P_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER//
mode_idx = <3>;
path_type = "SENSOR_1296x972_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER//
};
sensor1 {
subdev_name = "vivcam";
idx = <3>; //<3>=vivcam3 : sc2310
csi_idx = <1>; //<1>=CSI2X2_B
path_type = "SENSOR_1080P_RAW12_LINER";
mode_idx = <1>;
path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER";
};
isp {
subdev_name = "isp";
@@ -1083,18 +1129,20 @@
};
};
};
pipline2 {
channel2 {
sensor0 {
subdev_name = "vivcam";
idx = <2>; //<2>=vivcam2 : gc5035
csi_idx = <1>; //<1>=CSI2X2_B
path_type = "SENSOR_1080P_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER//
mode_idx = <3>;
path_type = "SENSOR_1296x972_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER//
};
sensor1 {
subdev_name = "vivcam";
idx = <3>; //<3>=vivcam3 : sc2310
csi_idx = <1>; //<1>=CSI2X2_B
path_type = "SENSOR_1080P_RAW12_LINER";
mode_idx = <1>;
path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER";
};
isp {
subdev_name = "isp";
@@ -1113,18 +1161,20 @@
&video1{
vi_mem_pool_region = <2>; // vi_mem: framebuffer, region[2]
pipline0 {
channel0 {
sensor0 {
subdev_name = "vivcam";
idx = <2>; //<2>=vivcam2 : gc5035
csi_idx = <1>; //<1>=CSI2X2_B
path_type = "SENSOR_1080P_RAW10_LINER";
mode_idx = <3>;
path_type = "SENSOR_1296x972_RAW10_LINER";
};
sensor1 {
subdev_name = "vivcam";
idx = <3>; //<3>=vivcam3 : sc2310
csi_idx = <1>; //<1>=CSI2X2_B
path_type = "SENSOR_1080P_RAW12_LINER";
mode_idx = <1>;
path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER";
};
isp {
subdev_name = "isp";
@@ -1144,18 +1194,20 @@
dw_dst_depth = <2>;
};
};
pipline1 {
channel1 {
sensor0 {
subdev_name = "vivcam";
idx = <2>; //<2>=vivcam2 : gc5035
csi_idx = <1>; //<1>=CSI2X2_B
path_type = "SENSOR_1080P_RAW10_LINER";
mode_idx = <3>;
path_type = "SENSOR_1296x972_RAW10_LINER";
};
sensor1 {
subdev_name = "vivcam";
idx = <3>; //<3>=vivcam3 : sc2310
csi_idx = <1>; //<1>=CSI2X2_B
path_type = "SENSOR_1080P_RAW12_LINER";
mode_idx = <1>;
path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER";
};
isp {
subdev_name = "isp";
@@ -1175,18 +1227,20 @@
dw_dst_depth = <2>;
};
};
pipline2 {
channel2 {
sensor0 {
subdev_name = "vivcam";
idx = <2>; //<2>=vivcam2 : gc5035
csi_idx = <1>; //<1>=CSI2X2_B
path_type = "SENSOR_1080P_RAW10_LINER";
mode_idx = <3>;
path_type = "SENSOR_1296x972_RAW10_LINER";
};
sensor1 {
subdev_name = "vivcam";
idx = <3>; //<3>=vivcam3 : sc2310
csi_idx = <1>; //<1>=CSI2X2_B
path_type = "SENSOR_1080P_RAW12_LINER";
mode_idx = <1>;
path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER";
};
isp {
subdev_name = "isp";
@@ -1210,12 +1264,20 @@
&video2{
vi_mem_pool_region = <0>; // vi_mem: framebuffer, region[0]
pipline0 {
channel0 {
sensor0 {
subdev_name = "vivcam";
idx = <0>; //sc2310
csi_idx = <0>; //<0>=CSI2
path_type = "SENSOR_1080P_RAW12_LINER";
mode_idx = <1>;
path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER";
};
sensor1 {
subdev_name = "vivcam";
idx = <6>; //gc02m1b
csi_idx = <0>; //<0>=CSI2
mode_idx = <0>;
path_type = "SENSOR_1600x1200_RAW10_LINER";
};
isp {
subdev_name = "isp";
@@ -1224,17 +1286,25 @@
output {
max_width = <1920>;
max_height = <1088>;
bit_per_pixel = <12>;
bit_per_pixel = <16>;
frame_count = <3>;
};
};
};
pipline1 {
channel1 {
sensor0 {
subdev_name = "vivcam";
idx = <0>; //sc2310
csi_idx = <0>; //<0>=CSI2
path_type = "SENSOR_1080P_RAW12_LINER";
mode_idx = <1>;
path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER";
};
sensor1 {
subdev_name = "vivcam";
idx = <6>; //gc02m1b
csi_idx = <0>; //<0>=CSI2
mode_idx = <0>;
path_type = "SENSOR_1600x1200_RAW10_LINER";
};
isp {
subdev_name = "isp";
@@ -1243,17 +1313,25 @@
output {
max_width = <1920>;
max_height = <1088>;
bit_per_pixel = <12>;
bit_per_pixel = <16>;
frame_count = <3>;
};
};
};
pipline2 {
channel2 {
sensor0 {
subdev_name = "vivcam";
idx = <0>; //sc2310
csi_idx = <0>; //<0>=CSI2
path_type = "SENSOR_1080P_RAW12_LINER";
mode_idx = <1>;
path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER";
};
sensor1 {
subdev_name = "vivcam";
idx = <6>; //gc02m1b
csi_idx = <0>; //<0>=CSI2
mode_idx = <0>;
path_type = "SENSOR_1600x1200_RAW10_LINER";
};
isp {
subdev_name = "isp";
@@ -1262,7 +1340,7 @@
output {
max_width = <1920>;
max_height = <1088>;
bit_per_pixel = <12>;
bit_per_pixel = <16>;
frame_count = <3>;
};
};
@@ -1271,12 +1349,20 @@
&video3{
vi_mem_pool_region = <0>; // vi_mem: framebuffer, region[0]
pipline0 {
channel0 {
sensor0 {
subdev_name = "vivcam";
idx = <0>; //sc2310
csi_idx = <0>; //<0>=CSI2
path_type = "SENSOR_1080P_RAW12_LINER";
mode_idx = <1>;
path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER";
};
sensor1 {
subdev_name = "vivcam";
idx = <6>; //gc02m1b
csi_idx = <0>; //<0>=CSI2
mode_idx = <0>;
path_type = "SENSOR_1600x1200_RAW10_LINER";
};
isp {
subdev_name = "isp";
@@ -1296,12 +1382,20 @@
dw_dst_depth = <2>;
};
};
pipline1 {
channel1 {
sensor0 {
subdev_name = "vivcam";
idx = <0>; //sc2310
csi_idx = <0>; //<0>=CSI2
path_type = "SENSOR_1080P_RAW12_LINER";
mode_idx = <1>;
path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER";
};
sensor1 {
subdev_name = "vivcam";
idx = <6>; //gc02m1b
csi_idx = <0>; //<0>=CSI2
mode_idx = <0>;
path_type = "SENSOR_1600x1200_RAW10_LINER";
};
isp {
subdev_name = "isp";
@@ -1321,12 +1415,20 @@
dw_dst_depth = <2>;
};
};
pipline2 {
channel2 {
sensor0 {
subdev_name = "vivcam";
idx = <0>; //sc2310
csi_idx = <0>; //<0>=CSI2
path_type = "SENSOR_1080P_RAW12_LINER";
mode_idx = <1>;
path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER";
};
sensor1 {
subdev_name = "vivcam";
idx = <6>; //gc02m1b
csi_idx = <0>; //<0>=CSI2
mode_idx = <0>;
path_type = "SENSOR_1600x1200_RAW10_LINER";
};
isp {
subdev_name = "isp";
@@ -1350,12 +1452,20 @@
&video4{
vi_mem_pool_region = <0>; // vi_mem: framebuffer, region[0]
pipline0 {
channel0 {
sensor0 {
subdev_name = "vivcam";
idx = <0>; //sc2310
csi_idx = <0>; //<0>=CSI2
path_type = "SENSOR_1080P_RAW12_LINER";
mode_idx = <1>;
path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER";
};
sensor1 {
subdev_name = "vivcam";
idx = <6>; //gc02m1b
csi_idx = <0>; //<0>=CSI2
mode_idx = <0>;
path_type = "SENSOR_1600x1200_RAW10_LINER";
};
isp {
subdev_name = "isp";
@@ -1391,12 +1501,20 @@
};
};
};
pipline1 {
channel1 {
sensor0 {
subdev_name = "vivcam";
idx = <0>; //sc2310
csi_idx = <0>; //<0>=CSI2
path_type = "SENSOR_1080P_RAW12_LINER";
mode_idx = <1>;
path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER";
};
sensor1 {
subdev_name = "vivcam";
idx = <6>; //gc02m1b
csi_idx = <0>; //<0>=CSI2
mode_idx = <0>;
path_type = "SENSOR_1600x1200_RAW10_LINER";
};
isp {
subdev_name = "isp";
@@ -1432,12 +1550,20 @@
};
};
};
pipline2 {
channel2 {
sensor0 {
subdev_name = "vivcam";
idx = <0>; //sc2310
csi_idx = <0>; //<0>=CSI2
path_type = "SENSOR_1080P_RAW12_LINER";
mode_idx = <1>;
path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER";
};
sensor1 {
subdev_name = "vivcam";
idx = <6>; //gc02m1b
csi_idx = <0>; //<0>=CSI2
mode_idx = <0>;
path_type = "SENSOR_1600x1200_RAW10_LINER";
};
isp {
subdev_name = "isp";
@@ -1477,12 +1603,20 @@
&video5{
vi_mem_pool_region = <0>; // vi_mem: framebuffer, region[0]
pipline0 {
channel0 {
sensor0 {
subdev_name = "vivcam";
idx = <0>; //sc2310
csi_idx = <0>; //<0>=CSI2
path_type = "SENSOR_1080P_RAW12_LINER";
mode_idx = <1>;
path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER";
};
sensor1 {
subdev_name = "vivcam";
idx = <6>; //gc02m1b
csi_idx = <0>; //<0>=CSI2
mode_idx = <0>;
path_type = "SENSOR_1600x1200_RAW10_LINER";
};
isp {
subdev_name = "isp";
@@ -1524,12 +1658,20 @@
dw_dst_depth = <2>;
};
};
pipline1 {
channel1 {
sensor0 {
subdev_name = "vivcam";
idx = <0>; //sc2310
csi_idx = <0>; //<0>=CSI2
path_type = "SENSOR_1080P_RAW12_LINER";
mode_idx = <1>;
path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER";
};
sensor1 {
subdev_name = "vivcam";
idx = <6>; //gc02m1b
csi_idx = <0>; //<0>=CSI2
mode_idx = <0>;
path_type = "SENSOR_1600x1200_RAW10_LINER";
};
isp {
subdev_name = "isp";
@@ -1571,12 +1713,20 @@
dw_dst_depth = <2>;
};
};
pipline2 {
channel2 {
sensor0 {
subdev_name = "vivcam";
idx = <0>; //sc2310
csi_idx = <0>; //<0>=CSI2
path_type = "SENSOR_1080P_RAW12_LINER";
mode_idx = <1>;
path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER";
};
sensor1 {
subdev_name = "vivcam";
idx = <6>; //gc02m1b
csi_idx = <0>; //<0>=CSI2
mode_idx = <0>;
path_type = "SENSOR_1600x1200_RAW10_LINER";
};
isp {
subdev_name = "isp";
@@ -1622,13 +1772,14 @@
&video6{
vi_mem_pool_region = <1>; // vi_mem: framebuffer, region[1]
pipline0 {
channel0 {
sensor0 {
subdev_name = "vivcam";
idx = <4>; //sc132gs
csi_idx = <2>; //<2>=CSI2X2_A
flash_led_idx = <0>;
path_type = "SENSOR_1080P_RAW10_LINER";
mode_idx = <0>;
path_type = "SENSOR_1080X1280_30FPS_RAW10_LINER";
};
dsp{
output {
@@ -1639,13 +1790,14 @@
};
};
};
pipline1 {
channel1 {
sensor0 {
subdev_name = "vivcam";
idx = <4>; //sc132gs
csi_idx = <2>; //<2>=CSI2X2_A
flash_led_idx = <0>;
path_type = "SENSOR_1080P_RAW10_LINER";
mode_idx = <0>;
path_type = "SENSOR_1080X1280_30FPS_RAW10_LINER";
};
dsp{
output {
@@ -1659,18 +1811,20 @@
};
&video7{
pipline0 {
channel0 {
sensor0 {
subdev_name = "vivcam";
idx = <2>; //<2>=vivcam2 : gc5035
csi_idx = <1>; //<1>=CSI2X2_B
path_type = "SENSOR_1080P_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER//
mode_idx = <3>;
path_type = "SENSOR_1296x972_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER//
};
sensor1 {
subdev_name = "vivcam";
idx = <3>; //<3>=vivcam3 : sc2310
csi_idx = <1>; //<1>=CSI2X2_B
path_type = "SENSOR_1080P_RAW12_LINER";
mode_idx = <1>;
path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER";
};
isp {
subdev_name = "isp";
@@ -1712,18 +1866,20 @@
dw_dst_depth = <2>;
};
};
pipline1 {
channel1 {
sensor0 {
subdev_name = "vivcam";
idx = <2>; //<2>=vivcam2 : gc5035
csi_idx = <1>; //<1>=CSI2X2_B
path_type = "SENSOR_1080P_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER//
mode_idx = <3>;
path_type = "SENSOR_1296x972_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER//
};
sensor1 {
subdev_name = "vivcam";
idx = <3>; //<3>=vivcam3 : sc2310
csi_idx = <1>; //<1>=CSI2X2_B
path_type = "SENSOR_1080P_RAW12_LINER";
mode_idx = <1>;
path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER";
};
isp {
subdev_name = "isp";
@@ -1765,18 +1921,20 @@
dw_dst_depth = <2>;
};
};
pipline2 {
channel2 {
sensor0 {
subdev_name = "vivcam";
idx = <2>; //<2>=vivcam2 : gc5035
csi_idx = <1>; //<1>=CSI2X2_B
path_type = "SENSOR_1080P_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER//
mode_idx = <3>;
path_type = "SENSOR_1296x972_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER//
};
sensor1 {
subdev_name = "vivcam";
idx = <3>; //<3>=vivcam3 : sc2310
csi_idx = <1>; //<1>=CSI2X2_B
path_type = "SENSOR_1080P_RAW12_LINER";
mode_idx = <1>;
path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER";
};
isp {
subdev_name = "isp";
@@ -1823,18 +1981,20 @@
&video8{
vi_mem_pool_region = <1>; // vi_mem: framebuffer, region[1]
pipline0 {
channel0 {
sensor0 {
subdev_name = "vivcam";
idx = <2>; //<2>=vivcam2 : gc5035
csi_idx = <1>; //<1>=CSI2X2_B
path_type = "SENSOR_1080P_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER//
mode_idx = <3>;
path_type = "SENSOR_1296x972_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER//
};
sensor1 {
subdev_name = "vivcam";
idx = <3>; //<3>=vivcam3 : sc2310
csi_idx = <1>; //<1>=CSI2X2_B
path_type = "SENSOR_1080P_RAW12_LINER";
mode_idx = <1>;
path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER";
};
dsp {
subdev_name = "dsp";
@@ -1851,12 +2011,13 @@
};
&video9{
pipline0 {
channel0 {
sensor0 {
subdev_name = "vivcam";
idx = <4>; //sc132gs
csi_idx = <2>; //<2>=CSI2X2_A
path_type = "SENSOR_1080P_RAW10_LINER";
mode_idx = <0>;
path_type = "SENSOR_1080X1280_30FPS_RAW10_LINER";
};
dsp{
output {
@@ -1871,32 +2032,37 @@
&video10{
pipline0 {
channel0 {
sensor0 {
subdev_name = "vivcam";
idx = <2>; //<2>=vivcam2 : gc5035
csi_idx = <1>; //<1>=CSI2X2_B
mode_idx = <1>;
path_type = "SENSOR_1080P_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER//
skip_init = <1>;
};
sensor1 {
subdev_name = "vivcam";
idx = <3>; //<3>=vivcam3 : sc2310
csi_idx = <1>; //<1>=CSI2X2_B
path_type = "SENSOR_1080P_RAW12_LINER";
mode_idx = <1>;
path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER";
skip_init = <1>;
};
};
};
&video11{
pipline0 {
pipline_id = <0>;
channel0 {
channel_id = <0>;
status = "okay";
sensor0 {
subdev_name = "vivcam";
idx = <4>; //sc132gs
csi_idx = <2>; //<2>=CSI2X2_A
flash_led_idx = <0>;
path_type = "SENSOR_1080P_RAW10_LINER";
mode_idx = <0>;
path_type = "SENSOR_1080X1280_30FPS_RAW10_LINER";
};
isp {
subdev_name = "isp";
@@ -1912,13 +2078,22 @@
};
};
&video12{
pipline0 { // CSI2
&video12{ // TUNINGTOOL
channel0 { // CSI2
sensor0 {
subdev_name = "vivcam";
idx = <0>; //sc2310
csi_idx = <0>; //<0>=CSI2
path_type = "SENSOR_1080P_RAW12_LINER";
mode_idx = <1>;
path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER";
skip_init = <1>;
};
sensor1 {
subdev_name = "vivcam";
idx = <6>; //gc02m1b
csi_idx = <0>; //<0>=CSI2
mode_idx = <0>;
path_type = "SENSOR_1600x1200_RAW10_LINER";
skip_init = <1>;
};
};
@@ -1963,3 +2138,71 @@
status = "okay";
};
&cpus {
c910_0: cpu@0 {
operating-points = <
/* kHz uV */
300000 650000
800000 700000
1500000 800000
1848000 1000000
>;
light,dvddm-operating-points = <
/* kHz uV */
300000 800000
800000 800000
1500000 800000
1848000 1000000
>;
};
c910_1: cpu@1 {
operating-points = <
/* kHz uV */
300000 650000
800000 700000
1500000 800000
1848000 1000000
>;
light,dvddm-operating-points = <
/* kHz uV */
300000 800000
800000 800000
1500000 800000
1848000 1000000
>;
};
c910_2: cpu@2 {
operating-points = <
/* kHz uV */
300000 650000
800000 700000
1500000 800000
1848000 1000000
>;
light,dvddm-operating-points = <
/* kHz uV */
300000 800000
800000 800000
1500000 800000
1848000 1000000
>;
};
c910_3: cpu@3 {
operating-points = <
/* kHz uV */
300000 650000
800000 700000
1500000 800000
1848000 1000000
>;
light,dvddm-operating-points = <
/* kHz uV */
300000 800000
800000 800000
1500000 800000
1848000 1000000
>;
};
};

88
arch/riscv/boot/dts/thead/light-ant-discrete-crash.dts Normal file
View File

@@ -0,0 +1,88 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2022 Alibaba Group Holding Limited.
*/
#include "light-crash.dts"
&aon {
aon_reg_dialog: light-dialog-reg {
compatible = "thead,light-dialog-pmic-ant";
status = "okay";
dvdd_cpu_reg: appcpu_dvdd {
regulator-name = "appcpu_dvdd";
regulator-min-microvolt = <300000>;
regulator-max-microvolt = <1570000>;
regulator-boot-on;
regulator-always-on;
};
dvddm_cpu_reg: appcpu_dvddm {
regulator-name = "appcpu_dvddm";
regulator-min-microvolt = <300000>;
regulator-max-microvolt = <1570000>;
regulator-boot-on;
regulator-always-on;
};
};
};
&cpus {
c910_0: cpu@0 {
operating-points = <
/* kHz uV */
300000 720000
800000 720000
1500000 820000
>;
light,dvddm-operating-points = <
/* kHz uV */
300000 770000
800000 820000
1500000 820000
>;
};
c910_1: cpu@1 {
operating-points = <
/* kHz uV */
300000 720000
800000 720000
1500000 820000
>;
light,dvddm-operating-points = <
/* kHz uV */
300000 770000
800000 820000
1500000 820000
>;
};
c910_2: cpu@2 {
operating-points = <
/* kHz uV */
300000 720000
800000 720000
1500000 820000
>;
light,dvddm-operating-points = <
/* kHz uV */
300000 770000
800000 820000
1500000 820000
>;
};
c910_3: cpu@3 {
operating-points = <
/* kHz uV */
300000 720000
800000 720000
1500000 820000
>;
light,dvddm-operating-points = <
/* kHz uV */
300000 770000
800000 820000
1500000 820000
>;
};
};

1567
arch/riscv/boot/dts/thead/light-ant-discrete.dts
View File

File diff suppressed because it is too large Load Diff

90
arch/riscv/boot/dts/thead/light-ant-ref-crash.dts Normal file
View File

@@ -0,0 +1,90 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2022 Alibaba Group Holding Limited.
*/
#include "light-crash.dts"
&aon {
aon_reg_dialog: light-dialog-reg {
compatible = "thead,light-dialog-pmic-ant";
status = "okay";
dvdd_cpu_reg: appcpu_dvdd {
regulator-name = "appcpu_dvdd";
regulator-min-microvolt = <300000>;
regulator-max-microvolt = <1570000>;
regulator-boot-on;
regulator-always-on;
};
dvddm_cpu_reg: appcpu_dvddm {
regulator-name = "appcpu_dvddm";
regulator-min-microvolt = <300000>;
regulator-max-microvolt = <1570000>;
regulator-boot-on;
regulator-always-on;
};
};
};
&cpus {
c910_0: cpu@0 {
operating-points = <
/* kHz uV */
300000 650000
800000 700000
1500000 800000
>;
light,dvddm-operating-points = <
/* kHz uV */
300000 800000
800000 800000
1500000 800000
>;
};
c910_1: cpu@1 {
operating-points = <
/* kHz uV */
300000 650000
800000 700000
1500000 800000
>;
light,dvddm-operating-points = <
/* kHz uV */
300000 800000
800000 800000
1500000 800000
>;
};
c910_2: cpu@2 {
operating-points = <
/* kHz uV */
300000 650000
800000 700000
1500000 800000
>;
light,dvddm-operating-points = <
/* kHz uV */
300000 800000
800000 800000
1500000 800000
>;
};
c910_3: cpu@3 {
operating-points = <
/* kHz uV */
300000 650000
800000 700000
1500000 800000
>;
light,dvddm-operating-points = <
/* kHz uV */
300000 800000
800000 800000
1500000 800000
>;
};
};

2
arch/riscv/boot/dts/thead/light-ant-evt-sec.dts → arch/riscv/boot/dts/thead/light-ant-ref-sec.dts
View File

@@ -5,7 +5,7 @@
/dts-v1/;
#include "light-ant-evt.dts"
#include "light-ant-ref.dts"

498
arch/riscv/boot/dts/thead/light-ant-evt.dts → arch/riscv/boot/dts/thead/light-ant-ref.dts
View File

@@ -20,8 +20,6 @@
chosen {
bootargs = "console=ttyS0,115200 crashkernel=256M-:128M earlycon clk_ignore_unused sram=0xffe0000000,0x180000";
linux,initrd-start = <0x0 0x2000000>;
linux,initrd-end = <0x0 0x14600000>;
stdout-path = "serial0:115200n8";
};
@@ -256,7 +254,7 @@
};
};
aon {
aon: aon {
compatible = "thead,light-aon";
mbox-names = "aon";
mboxes = <&mbox_910t 1 0>;
@@ -494,14 +492,20 @@
soc_dovdd18_scan_reg: soc_dovdd18_scan {
regulator-name = "soc_dovdd18_scan";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <3600000>;
};
soc_dvdd12_scan_reg: soc_dvdd12_scan {
regulator-name = "soc_dvdd12_scan";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <3600000>;
};
soc_avdd28_scan_en_reg: soc_avdd28_scan_en {
regulator-name = "soc_avdd28_scan_en";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <3600000>;
};
};
@@ -542,16 +546,17 @@
0x0 0x20688000 0x0 0x00178000>; /* DSP shared memory */
no-map;
};
facelib_mem: memory@33000000 {
reg = <0x0 0x33000000 0 0x02000000>;
vi_mem: framebuffer@10000000 {
reg = <0x0 0x10000000 0x0 0x02C00000 /* vi_mem_pool_region[0] 44 MB (default) */
0x0 0x12C00000 0x0 0x01D00000 /* vi_mem_pool_region[1] 29 MB */
0x0 0x14900000 0x0 0x01E00000>; /* vi_mem_pool_region[2] 30 MB */
no-map;
};
vi_mem: framebuffer@70000000 {
reg = <0x0 0x70000000 0x0 0x02C00000 /* vi_mem_pool_region[0] 44 MB (default) */
0x0 0x72C00000 0x0 0x01D00000 /* vi_mem_pool_region[1] 29 MB */
0x0 0x74900000 0x0 0x01E00000>; /* vi_mem_pool_region[2] 30 MB */
facelib_mem: memory@17000000 {
reg = <0x0 0x17000000 0 0x02000000>;
no-map;
};
};
&adc {
@@ -573,7 +578,7 @@
irq-gpios = <&gpio1_porta 8 0>;
reset-gpios = <&gpio1_porta 7 0>;
AVDD28-supply = <&reg_tp_pwr_en>;
touchscreen-size-x = <720>;
touchscreen-size-x = <800>;
touchscreen-size-y = <1280>;
};
@@ -733,6 +738,7 @@
no-mmc;
non-removable;
io_fixed_1v8;
post-power-on-delay-ms = <50>;
wprtn_ignore;
cap-sd-highspeed;
keep-power-in-suspend;
@@ -867,22 +873,27 @@
};
&i2c0 {
clock-frequency = <400000>;
status = "okay";
};
&i2c1 {
clock-frequency = <400000>;
status = "okay";
};
&i2c2 {
clock-frequency = <400000>;
status = "okay";
};
&i2c3 {
clock-frequency = <400000>;
status = "okay";
};
&i2c4 {
clock-frequency = <400000>;
status = "okay";
};
@@ -951,7 +962,7 @@
&vvcam_flash_led0{
flash_led_name = "aw36413_aw36515";
floodlight_i2c_bus = /bits/ 8 <0>;
floodlight_i2c_bus = /bits/ 8 <2>;
floodlight_en_pin = <&gpio1_porta 26 0>;
projection_i2c_bus = /bits/ 8 <1>;
flash_led_touch_pin = <&gpio1_porta 27 0>; //flash led touch pin
@@ -966,7 +977,7 @@
sensor_regulator_timing_us = <70 50 20>;
sensor_pdn = <&gpio1_porta 21 0>; //powerdown pin / shutdown pin
sensor_rst = <&gpio1_porta 16 0>;
sensor_pdn_delay_us = <1000>; //powerdown pin / shutdown pin actived till I2C ready
sensor_pdn_delay_us = <4000>; //powerdown pin / shutdown pin actived till I2C ready
DOVDD18_RGB-supply = <&soc_dovdd18_rgb_reg>;
DVDD12_RGB-supply = <&soc_dvdd12_rgb_reg>;
AVDD28_RGB-supply = <&soc_avdd28_rgb_reg>;
@@ -980,11 +991,11 @@
&vvcam_sensor1 {
sensor_name = "SC132GS";
sensor_regulators = "DOVDD18_IR", "DVDD12_IR", "AVDD25_IR";
sensor_regulator_timing_us = <70 50 20>;
sensor_regulator_timing_us = <70 1000 2000>;
i2c_addr = /bits/ 8 <0x31>;
sensor_pdn = <&gpio1_porta 28 0>; //powerdown pin / shutdown pin
sensor_rst = <&gpio1_porta 24 0>;
sensor_pdn_delay_us = <1000>; //powerdown pin / shutdown pin actived till I2C ready
sensor_pdn_delay_us = <2000>; //powerdown pin / shutdown pin actived till I2C ready
DOVDD18_IR-supply = <&soc_dovdd18_ir_reg>;
DVDD12_IR-supply = <&soc_dvdd12_ir_reg>;
AVDD25_IR-supply = <&soc_avdd25_ir_reg>;
@@ -997,6 +1008,25 @@
&vvcam_sensor2 {
sensor_name = "GC5035";
sensor_regulators = "DOVDD18_SCAN", "DVDD12_SCAN", "AVDD28_SCAN";
sensor_regulator_voltage_uV = <1800000 1200000 2800000>;
sensor_regulator_timing_us = <100 50 0>;
sensor_pdn = <&gpio1_porta 30 0>; //powerdown pin / shutdown pin
sensor_rst = <&gpio1_porta 29 0>;
sensor_pdn_delay_us = <1000>; //powerdown pin / shutdown pin actived till I2C ready
DOVDD18_SCAN-supply = <&soc_dovdd18_scan_reg>;
DVDD12_SCAN-supply = <&soc_dvdd12_scan_reg>;
AVDD28_SCAN-supply = <&soc_avdd28_scan_en_reg>;
i2c_addr = /bits/ 8 <0x37>;
i2c_bus = /bits/ 8 <4>;
i2c_reg_width = /bits/ 8 <1>;
i2c_data_width = /bits/ 8 <1>;
status = "okay";
};
&vvcam_sensor3 {
sensor_name = "GC02M1B";
sensor_regulators = "DOVDD18_SCAN", "DVDD12_SCAN", "AVDD28_SCAN";
sensor_regulator_voltage_uV = <1800000 1800000 2800000>;
sensor_regulator_timing_us = <100 50 0>;
sensor_pdn = <&gpio1_porta 30 0>; //powerdown pin / shutdown pin
sensor_rst = <&gpio1_porta 29 0>;
@@ -1012,13 +1042,24 @@
};
&video0{
vi_mem_pool_region = <2>; // vi_mem: framebuffer, region[2]
pipline0 {
vi_mem_pool_region = <2>; // vi_mem: framebuffer, region[2]
channel0 {
sensor0 {
subdev_name = "vivcam";
idx = <2>; //<2>=vivcam2 : gc5035
csi_idx = <1>; //<1>=CSI2X2_B
path_type = "SENSOR_1080P_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER//
csi_idx = <0>; //<0>=CSI2
mode_idx = <3>;
path_type = "SENSOR_1296x972_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER//
};
sensor1 {
subdev_name = "vivcam";
idx = <3>; //<3>=vivcam3 : gc02m1b
csi_idx = <0>; //<0>=CSI2
mode_idx = <0>;
path_type = "SENSOR_1600x1200_RAW10_LINER";
};
dma {
path_type = "VIPRE_CSI0_ISP0";
};
isp {
subdev_name = "isp";
@@ -1032,12 +1073,23 @@
};
};
};
pipline1 {
channel1 {
sensor0 {
subdev_name = "vivcam";
idx = <2>; //<2>=vivcam2 : gc5035
csi_idx = <1>; //<1>=CSI2X2_B
path_type = "SENSOR_1080P_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER//
csi_idx = <0>; //<0>=CSI2
mode_idx = <3>;
path_type = "SENSOR_1296x972_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER//
};
sensor1 {
subdev_name = "vivcam";
idx = <3>; //<3>=vivcam3 : gc02m1b
csi_idx = <0>; //<0>=CSI2
mode_idx = <0>;
path_type = "SENSOR_1600x1200_RAW10_LINER";
};
dma {
path_type = "VIPRE_CSI0_ISP0";
};
isp {
subdev_name = "isp";
@@ -1051,12 +1103,23 @@
};
};
};
pipline2 {
channel2 {
sensor0 {
subdev_name = "vivcam";
idx = <2>; //<2>=vivcam2 : gc5035
csi_idx = <1>; //<1>=CSI2X2_B
path_type = "SENSOR_1080P_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER//
csi_idx = <0>; //<0>=CSI2
mode_idx = <3>;
path_type = "SENSOR_1296x972_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER//
};
sensor1 {
subdev_name = "vivcam";
idx = <3>; //<3>=vivcam3 : gc02m1b
csi_idx = <0>; //<0>=CSI2
mode_idx = <0>;
path_type = "SENSOR_1600x1200_RAW10_LINER";
};
dma {
path_type = "VIPRE_CSI0_ISP0";
};
isp {
subdev_name = "isp";
@@ -1075,13 +1138,25 @@
&video1{
vi_mem_pool_region = <2>; // vi_mem: framebuffer, region[2]
pipline0 {
channel0 {
sensor0 {
subdev_name = "vivcam";
idx = <2>; //<2>=vivcam2 : gc5035
csi_idx = <1>; //<1>=CSI2X2_B
path_type = "SENSOR_1080P_RAW10_LINER";
csi_idx = <0>; //<0>=CSI2
mode_idx = <3>;
path_type = "SENSOR_1296x972_RAW10_LINER";
};
sensor1 {
subdev_name = "vivcam";
idx = <3>; //<3>=vivcam3 : gc02m1b
csi_idx = <0>; //<0>=CSI2
mode_idx = <0>;
path_type = "SENSOR_1600x1200_RAW10_LINER";
};
dma {
path_type = "VIPRE_CSI0_ISP0";
};
isp {
subdev_name = "isp";
idx = <0>;
@@ -1100,13 +1175,25 @@
dw_dst_depth = <2>;
};
};
pipline1 {
channel1 {
sensor0 {
subdev_name = "vivcam";
idx = <2>; //<2>=vivcam2 : gc5035
csi_idx = <1>; //<1>=CSI2X2_B
path_type = "SENSOR_1080P_RAW10_LINER";
csi_idx = <0>; //<0>=CSI2
mode_idx = <3>;
path_type = "SENSOR_1296x972_RAW10_LINER";
};
sensor1 {
subdev_name = "vivcam";
idx = <3>; //<3>=vivcam3 : gc02m1b
csi_idx = <0>; //<0>=CSI2
mode_idx = <0>;
path_type = "SENSOR_1600x1200_RAW10_LINER";
};
dma {
path_type = "VIPRE_CSI0_ISP0";
};
isp {
subdev_name = "isp";
idx = <0>;
@@ -1125,13 +1212,25 @@
dw_dst_depth = <2>;
};
};
pipline2 {
channel2 {
sensor0 {
subdev_name = "vivcam";
idx = <2>; //<2>=vivcam2 : gc5035
csi_idx = <1>; //<1>=CSI2X2_B
path_type = "SENSOR_1080P_RAW10_LINER";
csi_idx = <0>; //<0>=CSI2
mode_idx = <3>;
path_type = "SENSOR_1296x972_RAW10_LINER";
};
sensor1 {
subdev_name = "vivcam";
idx = <3>; //<3>=vivcam3 : gc02m1b
csi_idx = <0>; //<0>=CSI2
mode_idx = <0>;
path_type = "SENSOR_1600x1200_RAW10_LINER";
};
dma {
path_type = "VIPRE_CSI0_ISP0";
};
isp {
subdev_name = "isp";
idx = <0>;
@@ -1154,12 +1253,16 @@
&video2{
vi_mem_pool_region = <0>; // vi_mem: framebuffer, region[0]
pipline0 {
channel0 {
sensor0 {
subdev_name = "vivcam";
idx = <0>; //vivcam0 sc2310
csi_idx = <0>; //<0>=CSI2
path_type = "SENSOR_1080P_RAW12_LINER";
csi_idx = <1>; //<1>=CSI2_B
mode_idx = <1>;
path_type = "SENSOR_1920X1088_30FPS_RAW12_LINER";
};
dma {
path_type = "VIPRE_CSI1_ISP1";
};
isp {
subdev_name = "isp";
@@ -1173,12 +1276,16 @@
};
};
};
pipline1 {
channel1 {
sensor0 {
subdev_name = "vivcam";
idx = <0>; //vivcam0 sc2310
csi_idx = <0>; //<0>=CSI2
path_type = "SENSOR_1080P_RAW12_LINER";
csi_idx = <1>; //<1>=CSI2_B
mode_idx = <1>;
path_type = "SENSOR_1920X1088_30FPS_RAW12_LINER";
};
dma {
path_type = "VIPRE_CSI1_ISP1";
};
isp {
subdev_name = "isp";
@@ -1192,12 +1299,16 @@
};
};
};
pipline2 {
channel2 {
sensor0 {
subdev_name = "vivcam";
idx = <0>; //vivcam0 sc2310
csi_idx = <0>; //<0>=CSI2
path_type = "SENSOR_1080P_RAW12_LINER";
csi_idx = <1>; //<1>=CSI2_B
mode_idx = <1>;
path_type = "SENSOR_1920X1088_30FPS_RAW12_LINER";
};
dma {
path_type = "VIPRE_CSI1_ISP1";
};
isp {
subdev_name = "isp";
@@ -1215,12 +1326,16 @@
&video3{
vi_mem_pool_region = <0>; // vi_mem: framebuffer, region[0]
pipline0 {
channel0 {
sensor0 {
subdev_name = "vivcam";
idx = <0>; //vivcam0 sc2310
csi_idx = <0>; //<0>=CSI2
path_type = "SENSOR_1080P_RAW12_LINER";
csi_idx = <1>; //<1>=CSI2B
mode_idx = <1>;
path_type = "SENSOR_1920X1088_30FPS_RAW12_LINER";
};
dma {
path_type = "VIPRE_CSI1_ISP1";
};
isp {
subdev_name = "isp";
@@ -1240,12 +1355,16 @@
dw_dst_depth = <2>;
};
};
pipline1 {
channel1 {
sensor0 {
subdev_name = "vivcam";
idx = <0>; //vivcam0 sc2310
csi_idx = <0>; //<0>=CSI2
path_type = "SENSOR_1080P_RAW12_LINER";
csi_idx = <1>; //<1>=CSI2B
mode_idx = <1>;
path_type = "SENSOR_1920X1088_30FPS_RAW12_LINER";
};
dma {
path_type = "VIPRE_CSI1_ISP1";
};
isp {
subdev_name = "isp";
@@ -1265,12 +1384,16 @@
dw_dst_depth = <2>;
};
};
pipline2 {
channel2 {
sensor0 {
subdev_name = "vivcam";
idx = <0>; //vivcam0 sc2310
csi_idx = <0>; //<0>=CSI2
path_type = "SENSOR_1080P_RAW12_LINER";
csi_idx = <1>; //<1>=CSI2_B
mode_idx = <1>;
path_type = "SENSOR_1920X1088_30FPS_RAW12_LINER";
};
dma {
path_type = "VIPRE_CSI1_ISP1";
};
isp {
subdev_name = "isp";
@@ -1294,12 +1417,16 @@
&video4{
vi_mem_pool_region = <0>; // vi_mem: framebuffer, region[0]
pipline0 {
channel0 {
sensor0 {
subdev_name = "vivcam";
idx = <0>; //vivcam0 sc2310
csi_idx = <0>; //<0>=CSI2
path_type = "SENSOR_1080P_RAW12_LINER";
csi_idx = <1>; //<1>=CSI2_B
mode_idx = <1>;
path_type = "SENSOR_1920X1088_30FPS_RAW12_LINER";
};
dma {
path_type = "VIPRE_CSI1_ISP1";
};
isp {
subdev_name = "isp";
@@ -1335,12 +1462,16 @@
};
};
};
pipline1 {
channel1 {
sensor0 {
subdev_name = "vivcam";
idx = <0>; //vivcam0 sc2310
csi_idx = <0>; //<0>=CSI2
path_type = "SENSOR_1080P_RAW12_LINER";
csi_idx = <1>; //<1>=CSI2_B
mode_idx = <1>;
path_type = "SENSOR_1920X1088_30FPS_RAW12_LINER";
};
dma {
path_type = "VIPRE_CSI1_ISP1";
};
isp {
subdev_name = "isp";
@@ -1376,12 +1507,16 @@
};
};
};
pipline2 {
channel2 {
sensor0 {
subdev_name = "vivcam";
idx = <0>; //vivcam0 sc2310
csi_idx = <0>; //<0>=CSI2
path_type = "SENSOR_1080P_RAW12_LINER";
csi_idx = <1>; //<1>=CSI2_B
mode_idx = <1>;
path_type = "SENSOR_1920X1088_30FPS_RAW12_LINER";
};
dma {
path_type = "VIPRE_CSI1_ISP1";
};
isp {
subdev_name = "isp";
@@ -1421,12 +1556,16 @@
&video5{
vi_mem_pool_region = <0>; // vi_mem: framebuffer, region[0]
pipline0 {
channel0 {
sensor0 {
subdev_name = "vivcam";
idx = <0>; //vivcam0 sc2310
csi_idx = <0>; //<0>=CSI2
path_type = "SENSOR_1080P_RAW12_LINER";
csi_idx = <1>; //<1>=CSI2_B
mode_idx = <1>;
path_type = "SENSOR_1920X1088_30FPS_RAW12_LINER";
};
dma {
path_type = "VIPRE_CSI1_ISP1";
};
isp {
subdev_name = "isp";
@@ -1468,12 +1607,16 @@
dw_dst_depth = <2>;
};
};
pipline1 {
channel1 {
sensor0 {
subdev_name = "vivcam";
idx = <0>; //vivcam0 sc2310
csi_idx = <0>; //<0>=CSI2
path_type = "SENSOR_1080P_RAW12_LINER";
csi_idx = <1>; //<1>=CSI2_B
mode_idx = <1>;
path_type = "SENSOR_1920X1088_30FPS_RAW12_LINER";
};
dma {
path_type = "VIPRE_CSI1_ISP1";
};
isp {
subdev_name = "isp";
@@ -1515,12 +1658,16 @@
dw_dst_depth = <2>;
};
};
pipline2 {
channel2 {
sensor0 {
subdev_name = "vivcam";
idx = <0>; //vivcam0 sc2310
csi_idx = <0>; //<0>=CSI2
path_type = "SENSOR_1080P_RAW12_LINER";
csi_idx = <1>; //<1>=CSI2_B
mode_idx = <1>;
path_type = "SENSOR_1920X1088_30FPS_RAW12_LINER";
};
dma {
path_type = "VIPRE_CSI1_ISP1";
};
isp {
subdev_name = "isp";
@@ -1566,13 +1713,14 @@
&video6{
vi_mem_pool_region = <1>; // vi_mem: framebuffer, region[1]
pipline0 {
channel0 {
sensor0 {
subdev_name = "vivcam";
idx = <1>; // vivcam1 sc132gs
csi_idx = <2>; //<2>=CSI2X2_A
flash_led_idx = <0>;
path_type = "SENSOR_1080P_RAW10_LINER";
mode_idx = <0>;
path_type = "SENSOR_1080X1280_30FPS_RAW10_LINER";
};
dsp{
output {
@@ -1583,13 +1731,14 @@
};
};
};
pipline1 {
channel1 {
sensor0 {
subdev_name = "vivcam";
idx = <1>; //vivcam1 sc132gs
csi_idx = <2>; //<2>=CSI2X2_A
flash_led_idx = <0>;
path_type = "SENSOR_1080P_RAW10_LINER";
mode_idx = <0>;
path_type = "SENSOR_1080X1280_30FPS_RAW10_LINER";
};
dsp{
output {
@@ -1604,13 +1753,25 @@
};
&video7{
pipline0 {
channel0 {
sensor0 {
subdev_name = "vivcam";
idx = <2>; //<2>=vivcam2 : gc5035
csi_idx = <1>; //<1>=CSI2X2_B
path_type = "SENSOR_1080P_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER//
csi_idx = <0>; //<0>=CSI2
mode_idx = <3>;
path_type = "SENSOR_1296x972_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER//
};
sensor1 {
subdev_name = "vivcam";
idx = <3>; //<3>=vivcam3 : gc02m1b
csi_idx = <0>; //<0>=CSI2
mode_idx = <0>;
path_type = "SENSOR_1600x1200_RAW10_LINER";
};
dma {
path_type = "VIPRE_CSI0_ISP0";
};
isp {
subdev_name = "isp";
idx = <0>;
@@ -1651,13 +1812,25 @@
dw_dst_depth = <2>;
};
};
pipline1 {
channel1 {
sensor0 {
subdev_name = "vivcam";
idx = <2>; //<2>=vivcam2 : gc5035
csi_idx = <1>; //<1>=CSI2X2_B
path_type = "SENSOR_1080P_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER//
csi_idx = <0>; //<0>=CSI2
mode_idx = <3>;
path_type = "SENSOR_1296x972_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER//
};
sensor1 {
subdev_name = "vivcam";
idx = <3>; //<3>=vivcam3 : gc02m1b
csi_idx = <0>; //<0>=CSI2
mode_idx = <0>;
path_type = "SENSOR_1600x1200_RAW10_LINER";
};
dma {
path_type = "VIPRE_CSI0_ISP0";
};
isp {
subdev_name = "isp";
idx = <0>;
@@ -1698,13 +1871,25 @@
dw_dst_depth = <2>;
};
};
pipline2 {
channel2 {
sensor0 {
subdev_name = "vivcam";
idx = <2>; //<2>=vivcam2 : gc5035
csi_idx = <1>; //<1>=CSI2X2_B
path_type = "SENSOR_1080P_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER//
csi_idx = <0>; //<0>=CSI2
mode_idx = <3>;
path_type = "SENSOR_1296x972_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER//
};
sensor1 {
subdev_name = "vivcam";
idx = <3>; //<3>=vivcam3 : gc02m1b
csi_idx = <0>; //<0>=CSI2
mode_idx = <0>;
path_type = "SENSOR_1600x1200_RAW10_LINER";
};
dma {
path_type = "VIPRE_CSI0_ISP0";
};
isp {
subdev_name = "isp";
idx = <0>;
@@ -1750,12 +1935,23 @@
&video8{
vi_mem_pool_region = <1>; // vi_mem: framebuffer, region[1]
pipline0 {
channel0 {
sensor0 {
subdev_name = "vivcam";
idx = <2>; //<2>=vivcam2 : gc5035
csi_idx = <1>; //<1>=CSI2X2_B
path_type = "SENSOR_1080P_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER//
csi_idx = <0>; //<0>=CSI2
mode_idx = <3>;
path_type = "SENSOR_1296x972_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER//
};
sensor1 {
subdev_name = "vivcam";
idx = <3>; //<3>=vivcam3 : gc02m1b
csi_idx = <0>; //<0>=CSI2
mode_idx = <0>;
path_type = "SENSOR_1600x1200_RAW10_LINER";
};
dma {
path_type = "VIPRE_CSI0_DSP";
};
dsp {
subdev_name = "dsp";
@@ -1772,12 +1968,13 @@
};
&video9{
pipline0 {
channel0 {
sensor0 {
subdev_name = "vivcam";
idx = <1>; //vivcam1 sc132gs
csi_idx = <2>; //<2>=CSI2X2_A
path_type = "SENSOR_1080P_RAW10_LINER";
mode_idx = <0>;
path_type = "SENSOR_1080X1280_30FPS_RAW10_LINER";
};
dsp{
output {
@@ -1791,27 +1988,41 @@
};
&video10{
pipline0 {
&video10{ // TUNINGTOOL
channel0 {
sensor0 {
subdev_name = "vivcam";
idx = <2>; //<2>=vivcam2 : gc5035
csi_idx = <1>; //<1>=CSI2X2_B
csi_idx = <0>; //<0>=CSI2
mode_idx = <1>;
path_type = "SENSOR_1080P_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER//
skip_init = <1>;
};
sensor1 {
subdev_name = "vivcam";
idx = <3>; //<3>=vivcam3 : gc02m1b
csi_idx = <0>; //<0>=CSI2
mode_idx = <0>;
path_type = "SENSOR_1600x1200_RAW10_LINER";
skip_init = <1>;
};
dma {
path_type = "VIPRE_CSI0_ISP0";
};
};
};
&video11{
pipline0 {
pipline_id = <0>;
channel0 {
channel_id = <0>;
status = "okay";
sensor0 {
subdev_name = "vivcam";
idx = <4>; //sc132gs
idx = <1>; //sc132gs
csi_idx = <2>; //<2>=CSI2X2_A
flash_led_idx = <0>;
path_type = "SENSOR_1080P_RAW10_LINER";
mode_idx = <0>;
path_type = "SENSOR_1080X1280_30FPS_RAW10_LINER";
};
isp {
subdev_name = "isp";
@@ -1827,18 +2038,109 @@
};
};
&video12{
pipline0 { // CSI2
&video12{ // TUNINGTOOL
channel0 { // CSI2
sensor0 {
subdev_name = "vivcam";
idx = <0>; //sc2310
csi_idx = <0>; //<0>=CSI2
path_type = "SENSOR_1080P_RAW12_LINER";
csi_idx = <1>; //<1>=CSI2_B
mode_idx = <1>;
path_type = "SENSOR_1920X1088_30FPS_RAW12_LINER";
skip_init = <1>;
};
dma {
path_type = "VIPRE_CSI1_ISP0";
};
};
};
&video13{
status = "okay";
//vi_mem_pool_region = <0>;
channel0 {
channel_id = <0>;
status = "okay";
sensor0 {
subdev_name = "vivcam";
idx = <0>; //sc2310
csi_idx = <1>; //<1>=CSI2_B
mode_idx = <1>;
path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER";
};
dma {
subdev_name = "vipre";
idx = <0>;
path_type = "VIPRE_CSI0_ISP0";
};
isp {
subdev_name = "isp";
idx = <0>;
path_type = "ISP_MI_MCM_WR0";
output {
max_width = <1920>;
max_height = <1088>;
bit_per_pixel = <16>;
frame_count = <3>;
};
};
};
};
&video14{
vi_mem_pool_region = <2>; // vi_mem: framebuffer, region[0]
status = "okay";
channel0 {
channel_id = <0>;
status = "okay";
sensor0 {
subdev_name = "vivcam";
idx = <1>; //sc132gs
csi_idx = <2>; //<2>=CSI2X2_A
flash_led_idx = <0>;
mode_idx = <0>;
path_type = "SENSOR_1080X1280_30FPS_RAW10_LINER";
};
dma {
subdev_name = "vipre";
idx = <0>;
path_type = "VIPRE_CSI2_ISP1";
};
isp {
subdev_name = "isp";
idx = <1>;
path_type = "ISP_MI_MCM_WR0";
output {
max_width = <1080>;
max_height = <1280>;
bit_per_pixel = <16>;
frame_count = <3>;
};
};
};
};
&video15{
status = "okay";
//vi_mem_pool_region = <0>;
channel0 {
channel_id = <0>;
status = "okay";
sensor0 {
subdev_name = "vivcam";
idx = <0>; //<0>=vivcam0 :2310
csi_idx = <1>; //<1>=CSI2_B
flash_led_idx = <0>;
mode_idx = <1>;
path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER";
};
dma {
subdev_name = "vipre";
idx = <0>;
path_type = "VIPRE_CSI0_DDR";
};
};
};
&trng {
status = "disabled";

134
arch/riscv/boot/dts/thead/light-b-power.dts Normal file
View File

@@ -0,0 +1,134 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2021 Alibaba Group Holding Limited.
*/
/dts-v1/;
#include "light-b-product.dts"
&aon {
/delete-node/light-ricoh-reg;
soc_vdd18_lcd0_bk_en_reg: soc_vdd18_lcd0_bk_en {
compatible = "regulator-fixed";
regulator-name = "soc_vdd18_lcd0_bk_en";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
gpio = <&gpio1_porta 9 1>;
enable-active-high;
};
aon_reg_dialog: light-dialog-reg {
compatible = "thead,light-dialog-pmic-ant";
status = "okay";
dvdd_cpu_reg: appcpu_dvdd {
regulator-name = "appcpu_dvdd";
regulator-min-microvolt = <300000>;
regulator-max-microvolt = <1570000>;
regulator-boot-on;
regulator-always-on;
};
dvddm_cpu_reg: appcpu_dvddm {
regulator-name = "appcpu_dvddm";
regulator-min-microvolt = <300000>;
regulator-max-microvolt = <1570000>;
regulator-boot-on;
regulator-always-on;
};
soc_dvdd18_aon_reg: soc_dvdd18_aon {
regulator-name = "soc_dvdd18_aon";
regulator-boot-on;
regulator-always-on;
};
soc_avdd33_usb3_reg: soc_avdd33_usb3 {
regulator-name = "soc_avdd33_usb3";
regulator-boot-on;
regulator-always-on;
};
soc_dvdd08_aon_reg: soc_dvdd08_aon {
regulator-name = "soc_dvdd08_aon";
regulator-boot-on;
regulator-always-on;
};
soc_dvdd08_ddr_reg: soc_dvdd08_ddr {
regulator-name = "soc_dvdd08_ddr";
regulator-boot-on;
regulator-always-on;
};
soc_vdd_ddr_1v8_reg: soc_vdd_ddr_1v8 {
regulator-name = "soc_vdd_ddr_1v8";
regulator-boot-on;
regulator-always-on;
};
soc_vdd_ddr_1v1_reg: soc_vdd_ddr_1v1 {
regulator-name = "soc_vdd_ddr_1v1";
regulator-boot-on;
regulator-always-on;
};
soc_vdd_ddr_0v6_reg: soc_vdd_ddr_0v6 {
regulator-name = "soc_vdd_ddr_0v6";
regulator-boot-on;
regulator-always-on;
};
soc_dvdd18_ap_reg: soc_dvdd18_ap {
regulator-name = "soc_dvdd18_ap";
regulator-boot-on;
regulator-always-on;
};
soc_avdd08_mipi_hdmi_reg: soc_avdd08_mipi_hdmi {
regulator-name = "soc_avdd08_mipi_hdmi";
regulator-boot-on;
regulator-always-on;
};
soc_avdd18_mipi_hdmi_reg: soc_avdd18_mipi_hdmi {
regulator-name = "soc_avdd18_mipi_hdmi";
regulator-boot-on;
regulator-always-on;
};
soc_vdd33_emmc_reg: soc_vdd33_emmc {
regulator-name = "soc_vdd33_emmc";
regulator-boot-on;
regulator-always-on;
};
soc_vdd18_emmc_reg: soc_vdd18_emmc {
regulator-name = "soc_vdd18_emmc";
regulator-boot-on;
regulator-always-on;
};
#if 0
soc_dovdd18_scan_reg: soc_dovdd18_scan {
regulator-name = "soc_dovdd18_scan";
};
soc_dvdd12_scan_reg: soc_dvdd12_scan {
regulator-name = "soc_dvdd12_scan";
};
soc_avdd28_scan_en_reg: soc_avdd28_scan_en {
regulator-name = "soc_avdd28_scan_en";
};
#endif
};
};
&panel0 {
vdd1v8-supply = <&soc_vdd18_lcd0_bk_en_reg>;
};

90
arch/riscv/boot/dts/thead/light-b-product-crash.dts Normal file
View File

@@ -0,0 +1,90 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2021 Alibaba Group Holding Limited.
*/
#include "light-crash.dts"
&aon {
aon_reg_ricoh: light-ricoh-reg {
compatible = "thead,light-ricoh-pmic";
status = "okay";
dvdd_cpu_reg: appcpu_dvdd {
regulator-name = "appcpu_dvdd";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <1500000>;
regulator-boot-on;
regulator-always-on;
};
dvddm_cpu_reg: appcpu_dvddm {
regulator-name = "appcpu_dvddm";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <1500000>;
regulator-boot-on;
regulator-always-on;
};
};
};
&cpus {
c910_0: cpu@0 {
operating-points = <
/* kHz uV */
300000 600000
800000 700000
1500000 800000
>;
light,dvddm-operating-points = <
/* kHz uV */
300000 800000
800000 800000
1500000 800000
>;
};
c910_1: cpu@1 {
operating-points = <
/* kHz uV */
300000 600000
800000 700000
1500000 800000
>;
light,dvddm-operating-points = <
/* kHz uV */
300000 800000
800000 800000
1500000 800000
>;
};
c910_2: cpu@2 {
operating-points = <
/* kHz uV */
300000 600000
800000 700000
1500000 800000
>;
light,dvddm-operating-points = <
/* kHz uV */
300000 800000
800000 800000
1500000 800000
>;
};
c910_3: cpu@3 {
operating-points = <
/* kHz uV */
300000 600000
800000 700000
1500000 800000
>;
light,dvddm-operating-points = <
/* kHz uV */
300000 800000
800000 800000
1500000 800000
>;
};
};

4
arch/riscv/boot/dts/thead/light-b-product-ddr1G.dts
View File

@@ -16,6 +16,6 @@
};
&cmamem {
size = <0 0x8c00000>;
alloc-ranges = <0 0x35000000 0 0x3dc00000>;
size = <0 0x8c00000>; // 140MB by default
alloc-ranges = <0 0x02000000 0 0x0cc000000>; // [0x0600_0000 ~ 0x0EC0_0000]
};

401
arch/riscv/boot/dts/thead/light-b-product.dts
View File

@@ -20,8 +20,6 @@
chosen {
bootargs = "console=ttyS0,115200 crashkernel=256M-:128M earlycon clk_ignore_unused sram=0xffe0000000,0x180000";
linux,initrd-start = <0x0 0x2000000>;
linux,initrd-end = <0x0 0x14600000>;
stdout-path = "serial0:115200n8";
};
@@ -227,14 +225,14 @@
pinctrl-names = "default";
wifi_chip_type = "rtl8723ds";
WIFI,poweren_gpio = <&gpio2_porta 29 0>;
WIFI,reset_n = <&gpio2_porta 22 0>;
WIFI,reset_n = <&gpio2_porta 24 0>;
status = "okay";
};
wcn_bt: wireless-bluetooth {
compatible = "bluetooth-platdata";
pinctrl-names = "default", "rts_gpio";
BT,power_gpio = <&gpio2_porta 29 0>;
BT,power_gpio = <&gpio2_porta 25 0>;
status = "okay";
};
@@ -256,7 +254,7 @@
};
};
aon {
aon: aon@0 {
compatible = "thead,light-aon";
mbox-names = "aon";
mboxes = <&mbox_910t 1 0>;
@@ -560,16 +558,19 @@
0x0 0x20688000 0x0 0x00178000>; /* DSP shared memory */
no-map;
};
facelib_mem: memory@33000000 {
reg = <0x0 0x33000000 0 0x02000000>;
vi_mem: framebuffer@10000000 {
reg = <0x0 0x10000000 0x0 0x02C00000 /* vi_mem_pool_region[0] 44 MB (default) */
0x0 0x12C00000 0x0 0x01D00000 /* vi_mem_pool_region[1] 29 MB */
0x0 0x14900000 0x0 0x01E00000>; /* vi_mem_pool_region[2] 30 MB */
no-map;
};
vi_mem: framebuffer@70000000 {
reg = <0x0 0x70000000 0x0 0x02C00000 /* vi_mem_pool_region[0] 44 MB (default) */
0x0 0x72C00000 0x0 0x01D00000 /* vi_mem_pool_region[1] 29 MB */
0x0 0x74900000 0x0 0x01E00000>; /* vi_mem_pool_region[2] 30 MB */
facelib_mem: memory@17000000 {
reg = <0x0 0x17000000 0 0x02000000>;
no-map;
};
};
&adc {
@@ -590,7 +591,7 @@
irq-gpios = <&gpio1_porta 8 0>;
reset-gpios = <&gpio1_porta 7 0>;
AVDD28-supply = <&reg_tp_pwr_en>;
touchscreen-size-x = <720>;
touchscreen-size-x = <800>;
touchscreen-size-y = <1280>;
};
@@ -749,6 +750,7 @@
no-mmc;
non-removable;
io_fixed_1v8;
post-power-on-delay-ms = <50>;
wprtn_ignore;
cap-sd-highspeed;
keep-power-in-suspend;
@@ -886,22 +888,27 @@
};
&i2c0 {
clock-frequency = <400000>;
status = "okay";
};
&i2c1 {
clock-frequency = <400000>;
status = "okay";
};
&i2c2 {
clock-frequency = <400000>;
status = "okay";
};
&i2c3 {
clock-frequency = <400000>;
status = "okay";
};
&i2c4 {
clock-frequency = <400000>;
status = "okay";
};
@@ -950,7 +957,7 @@
};
&vi_pre {
//vi_pre_irq_en = <1>;
vi_pre_irq_en = <1>;
status = "okay";
};
@@ -977,13 +984,12 @@
status = "okay";
};
&vvcam_sensor0 {
sensor_name = "SC2310";
sensor_regulators = "DOVDD18_RGB", "DVDD12_RGB", "AVDD28_RGB";
sensor_regulator_timing_us = <70 50 20>;
sensor_rst = <&gpio1_porta 16 0>;
sensor_pdn_delay_us = <1000>; //powerdown pin / shutdown pin actived till I2C ready
sensor_pdn_delay_us = <4000>; //powerdown pin / shutdown pin actived till I2C ready
DOVDD18_RGB-supply = <&soc_dovdd18_rgb_reg>;
DVDD12_RGB-supply = <&soc_dvdd12_rgb_reg>;
AVDD28_RGB-supply = <&soc_avdd28_rgb_reg>;
@@ -1012,7 +1018,6 @@
};
*/
&vvcam_sensor1 {
sensor_name = "OV5693";
i2c_bus = /bits/ 8 <3>;
@@ -1042,22 +1047,26 @@
sensor_name = "SC2310";
sensor_regulators = "DOVDD18_SCAN", "DVDD12_SCAN", "AVDD28_SCAN";
sensor_regulator_timing_us = <70 50 20>;
//sensor_pdn = <&gpio1_porta 30 0>; //powerdown pin / shutdown pin
//sensor_rst = <&gpio1_porta 29 0>;
sensor_pdn = <&gpio1_porta 30 0>; //powerdown pin / shutdown pin
sensor_rst = <&gpio1_porta 29 0>;
sensor_pdn_delay_us = <4000>; //powerdown pin / shutdown pin actived till I2C ready
DOVDD18_SCAN-supply = <&soc_dovdd18_scan_reg>;
DVDD12_SCAN-supply = <&soc_dvdd12_scan_reg>;
AVDD28_SCAN-supply = <&soc_avdd28_scan_en_reg>;
i2c_bus = /bits/ 8 <4>;
i2c_reg_width = /bits/ 8 <2>;
i2c_data_width = /bits/ 8 <1>;
i2c_addr = /bits/ 8 <0x30>;
status = "okay";
};
&vvcam_sensor4 {
sensor_name = "SC132GS";
sensor_regulators = "DOVDD18_IR", "DVDD12_IR", "AVDD25_IR";
sensor_regulator_timing_us = <70 50 20>;
sensor_regulator_timing_us = <70 1000 2000>;
i2c_addr = /bits/ 8 <0x31>;
sensor_rst = <&gpio1_porta 24 0>;
sensor_pdn_delay_us = <1000>; //powerdown pin / shutdown pin actived till I2C ready
sensor_pdn_delay_us = <2000>; //powerdown pin / shutdown pin actived till I2C ready
DOVDD18_IR-supply = <&soc_dovdd18_ir_reg>;
DVDD12_IR-supply = <&soc_dvdd12_ir_reg>;
AVDD25_IR-supply = <&soc_avdd25_ir_reg>;
@@ -1071,7 +1080,7 @@
sensor_name = "OV12870";
sensor_regulators = "DOVDD18_RGB", "DVDD12_RGB", "AVDD28_RGB";
sensor_regulator_timing_us = <100 50 0>;
//sensor_rst = <&gpio1_porta 16 0>;
sensor_rst = <&gpio1_porta 16 0>;
sensor_pdn_delay_us = <60>; //powerdown pin / shutdown pin actived till I2C ready
DOVDD18_RGB-supply = <&soc_dovdd18_rgb_reg>;
DVDD12_RGB-supply = <&soc_dvdd12_rgb_reg>;
@@ -1083,20 +1092,38 @@
status = "okay";
};
&vvcam_sensor6 {
sensor_name = "GC02M1B";
sensor_regulators = "DOVDD18_RGB", "DVDD12_RGB", "AVDD28_RGB";
sensor_regulator_timing_us = <70 50 20>;
sensor_rst = <&gpio1_porta 16 0>;
sensor_pdn_delay_us = <1000>; //powerdown pin / shutdown pin actived till I2C ready
DOVDD18_RGB-supply = <&soc_dovdd18_rgb_reg>;
DVDD12_RGB-supply = <&soc_dvdd12_rgb_reg>;
AVDD28_RGB-supply = <&soc_avdd28_rgb_reg>;
i2c_reg_width = /bits/ 8 <1>;
i2c_data_width = /bits/ 8 <1>;
i2c_addr = /bits/ 8 <0x37>;
i2c_bus = /bits/ 8 <3>;
status = "okay";
};
&video0{
vi_mem_pool_region = <2>; // vi_mem: framebuffer, region[2]
pipline0 {
channel0 {
sensor0 {
subdev_name = "vivcam";
idx = <2>; //<2>=vivcam2 : gc5035
csi_idx = <1>; //<1>=CSI2X2_B
path_type = "SENSOR_1080P_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER//
mode_idx = <3>;
path_type = "SENSOR_1296x972_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER//
};
sensor1 {
subdev_name = "vivcam";
idx = <3>; //<3>=vivcam3 : sc2310
csi_idx = <1>; //<1>=CSI2X2_B
path_type = "SENSOR_1080P_RAW12_LINER";
mode_idx = <1>;
path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER";
};
isp {
subdev_name = "isp";
@@ -1110,18 +1137,20 @@
};
};
};
pipline1 {
channel1 {
sensor0 {
subdev_name = "vivcam";
idx = <2>; //<2>=vivcam2 : gc5035
csi_idx = <1>; //<1>=CSI2X2_B
path_type = "SENSOR_1080P_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER//
mode_idx = <3>;
path_type = "SENSOR_1296x972_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER//
};
sensor1 {
subdev_name = "vivcam";
idx = <3>; //<3>=vivcam3 : sc2310
csi_idx = <1>; //<1>=CSI2X2_B
path_type = "SENSOR_1080P_RAW12_LINER";
mode_idx = <1>;
path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER";
};
isp {
subdev_name = "isp";
@@ -1135,18 +1164,20 @@
};
};
};
pipline2 {
channel2 {
sensor0 {
subdev_name = "vivcam";
idx = <2>; //<2>=vivcam2 : gc5035
csi_idx = <1>; //<1>=CSI2X2_B
path_type = "SENSOR_1080P_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER//
mode_idx = <3>;
path_type = "SENSOR_1296x972_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER//
};
sensor1 {
subdev_name = "vivcam";
idx = <3>; //<3>=vivcam3 : sc2310
csi_idx = <1>; //<1>=CSI2X2_B
path_type = "SENSOR_1080P_RAW12_LINER";
mode_idx = <1>;
path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER";
};
isp {
subdev_name = "isp";
@@ -1165,18 +1196,20 @@
&video1{
vi_mem_pool_region = <2>; // vi_mem: framebuffer, region[2]
pipline0 {
channel0 {
sensor0 {
subdev_name = "vivcam";
idx = <2>; //<2>=vivcam2 : gc5035
csi_idx = <1>; //<1>=CSI2X2_B
path_type = "SENSOR_1080P_RAW10_LINER";
mode_idx = <3>;
path_type = "SENSOR_1296x972_RAW10_LINER";
};
sensor1 {
subdev_name = "vivcam";
idx = <3>; //<3>=vivcam3 : sc2310
csi_idx = <1>; //<1>=CSI2X2_B
path_type = "SENSOR_1080P_RAW12_LINER";
mode_idx = <1>;
path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER";
};
isp {
subdev_name = "isp";
@@ -1196,18 +1229,20 @@
dw_dst_depth = <2>;
};
};
pipline1 {
channel1 {
sensor0 {
subdev_name = "vivcam";
idx = <2>; //<2>=vivcam2 : gc5035
csi_idx = <1>; //<1>=CSI2X2_B
path_type = "SENSOR_1080P_RAW10_LINER";
mode_idx = <3>;
path_type = "SENSOR_1296x972_RAW10_LINER";
};
sensor1 {
subdev_name = "vivcam";
idx = <3>; //<3>=vivcam3 : sc2310
csi_idx = <1>; //<1>=CSI2X2_B
path_type = "SENSOR_1080P_RAW12_LINER";
mode_idx = <1>;
path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER";
};
isp {
subdev_name = "isp";
@@ -1227,18 +1262,20 @@
dw_dst_depth = <2>;
};
};
pipline2 {
channel2 {
sensor0 {
subdev_name = "vivcam";
idx = <2>; //<2>=vivcam2 : gc5035
csi_idx = <1>; //<1>=CSI2X2_B
path_type = "SENSOR_1080P_RAW10_LINER";
mode_idx = <3>;
path_type = "SENSOR_1296x972_RAW10_LINER";
};
sensor1 {
subdev_name = "vivcam";
idx = <3>; //<3>=vivcam3 : sc2310
csi_idx = <1>; //<1>=CSI2X2_B
path_type = "SENSOR_1080P_RAW12_LINER";
mode_idx = <1>;
path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER";
};
isp {
subdev_name = "isp";
@@ -1262,12 +1299,20 @@
&video2{
vi_mem_pool_region = <0>; // vi_mem: framebuffer, region[0]
pipline0 {
channel0 {
sensor0 {
subdev_name = "vivcam";
idx = <0>; //sc2310
csi_idx = <0>; //<0>=CSI2
path_type = "SENSOR_1080P_RAW12_LINER";
mode_idx = <1>;
path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER";
};
sensor1 {
subdev_name = "vivcam";
idx = <6>; //gc02m1b
csi_idx = <0>; //<0>=CSI2
mode_idx = <0>;
path_type = "SENSOR_1600x1200_RAW10_LINER";
};
isp {
subdev_name = "isp";
@@ -1276,17 +1321,25 @@
output {
max_width = <1920>;
max_height = <1088>;
bit_per_pixel = <12>;
bit_per_pixel = <16>;
frame_count = <3>;
};
};
};
pipline1 {
channel1 {
sensor0 {
subdev_name = "vivcam";
idx = <0>; //sc2310
csi_idx = <0>; //<0>=CSI2
path_type = "SENSOR_1080P_RAW12_LINER";
mode_idx = <1>;
path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER";
};
sensor1 {
subdev_name = "vivcam";
idx = <6>; //gc02m1b
csi_idx = <0>; //<0>=CSI2
mode_idx = <0>;
path_type = "SENSOR_1600x1200_RAW10_LINER";
};
isp {
subdev_name = "isp";
@@ -1295,17 +1348,25 @@
output {
max_width = <1920>;
max_height = <1088>;
bit_per_pixel = <12>;
bit_per_pixel = <16>;
frame_count = <3>;
};
};
};
pipline2 {
channel2 {
sensor0 {
subdev_name = "vivcam";
idx = <0>; //sc2310
csi_idx = <0>; //<0>=CSI2
path_type = "SENSOR_1080P_RAW12_LINER";
mode_idx = <1>;
path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER";
};
sensor1 {
subdev_name = "vivcam";
idx = <6>; //gc02m1b
csi_idx = <0>; //<0>=CSI2
mode_idx = <0>;
path_type = "SENSOR_1600x1200_RAW10_LINER";
};
isp {
subdev_name = "isp";
@@ -1314,7 +1375,7 @@
output {
max_width = <1920>;
max_height = <1088>;
bit_per_pixel = <12>;
bit_per_pixel = <16>;
frame_count = <3>;
};
};
@@ -1323,12 +1384,20 @@
&video3{
vi_mem_pool_region = <0>; // vi_mem: framebuffer, region[0]
pipline0 {
channel0 {
sensor0 {
subdev_name = "vivcam";
idx = <0>; //sc2310
csi_idx = <0>; //<0>=CSI2
path_type = "SENSOR_1080P_RAW12_LINER";
mode_idx = <1>;
path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER";
};
sensor1 {
subdev_name = "vivcam";
idx = <6>; //gc02m1b
csi_idx = <0>; //<0>=CSI2
mode_idx = <0>;
path_type = "SENSOR_1600x1200_RAW10_LINER";
};
isp {
subdev_name = "isp";
@@ -1348,12 +1417,20 @@
dw_dst_depth = <2>;
};
};
pipline1 {
channel1 {
sensor0 {
subdev_name = "vivcam";
idx = <0>; //sc2310
csi_idx = <0>; //<0>=CSI2
path_type = "SENSOR_1080P_RAW12_LINER";
mode_idx = <1>;
path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER";
};
sensor1 {
subdev_name = "vivcam";
idx = <6>; //gc02m1b
csi_idx = <0>; //<0>=CSI2
mode_idx = <0>;
path_type = "SENSOR_1600x1200_RAW10_LINER";
};
isp {
subdev_name = "isp";
@@ -1373,12 +1450,20 @@
dw_dst_depth = <2>;
};
};
pipline2 {
channel2 {
sensor0 {
subdev_name = "vivcam";
idx = <0>; //sc2310
csi_idx = <0>; //<0>=CSI2
path_type = "SENSOR_1080P_RAW12_LINER";
mode_idx = <1>;
path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER";
};
sensor1 {
subdev_name = "vivcam";
idx = <6>; //gc02m1b
csi_idx = <0>; //<0>=CSI2
mode_idx = <0>;
path_type = "SENSOR_1600x1200_RAW10_LINER";
};
isp {
subdev_name = "isp";
@@ -1402,12 +1487,20 @@
&video4{
vi_mem_pool_region = <0>; // vi_mem: framebuffer, region[0]
pipline0 {
channel0 {
sensor0 {
subdev_name = "vivcam";
idx = <0>; //sc2310
csi_idx = <0>; //<0>=CSI2
path_type = "SENSOR_1080P_RAW12_LINER";
mode_idx = <1>;
path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER";
};
sensor1 {
subdev_name = "vivcam";
idx = <6>; //gc02m1b
csi_idx = <0>; //<0>=CSI2
mode_idx = <0>;
path_type = "SENSOR_1600x1200_RAW10_LINER";
};
isp {
subdev_name = "isp";
@@ -1443,12 +1536,20 @@
};
};
};
pipline1 {
channel1 {
sensor0 {
subdev_name = "vivcam";
idx = <0>; //sc2310
csi_idx = <0>; //<0>=CSI2
path_type = "SENSOR_1080P_RAW12_LINER";
mode_idx = <1>;
path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER";
};
sensor1 {
subdev_name = "vivcam";
idx = <6>; //gc02m1b
csi_idx = <0>; //<0>=CSI2
mode_idx = <0>;
path_type = "SENSOR_1600x1200_RAW10_LINER";
};
isp {
subdev_name = "isp";
@@ -1484,12 +1585,20 @@
};
};
};
pipline2 {
channel2 {
sensor0 {
subdev_name = "vivcam";
idx = <0>; //sc2310
csi_idx = <0>; //<0>=CSI2
path_type = "SENSOR_1080P_RAW12_LINER";
mode_idx = <1>;
path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER";
};
sensor1 {
subdev_name = "vivcam";
idx = <6>; //gc02m1b
csi_idx = <0>; //<0>=CSI2
mode_idx = <0>;
path_type = "SENSOR_1600x1200_RAW10_LINER";
};
isp {
subdev_name = "isp";
@@ -1529,12 +1638,20 @@
&video5{
vi_mem_pool_region = <0>; // vi_mem: framebuffer, region[0]
pipline0 {
channel0 {
sensor0 {
subdev_name = "vivcam";
idx = <0>; //sc2310
csi_idx = <0>; //<0>=CSI2
path_type = "SENSOR_1080P_RAW12_LINER";
mode_idx = <1>;
path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER";
};
sensor1 {
subdev_name = "vivcam";
idx = <6>; //gc02m1b
csi_idx = <0>; //<0>=CSI2
mode_idx = <0>;
path_type = "SENSOR_1600x1200_RAW10_LINER";
};
isp {
subdev_name = "isp";
@@ -1576,12 +1693,20 @@
dw_dst_depth = <2>;
};
};
pipline1 {
channel1 {
sensor0 {
subdev_name = "vivcam";
idx = <0>; //sc2310
csi_idx = <0>; //<0>=CSI2
path_type = "SENSOR_1080P_RAW12_LINER";
mode_idx = <1>;
path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER";
};
sensor1 {
subdev_name = "vivcam";
idx = <6>; //gc02m1b
csi_idx = <0>; //<0>=CSI2
mode_idx = <0>;
path_type = "SENSOR_1600x1200_RAW10_LINER";
};
isp {
subdev_name = "isp";
@@ -1623,12 +1748,20 @@
dw_dst_depth = <2>;
};
};
pipline2 {
channel2 {
sensor0 {
subdev_name = "vivcam";
idx = <0>; //sc2310
csi_idx = <0>; //<0>=CSI2
path_type = "SENSOR_1080P_RAW12_LINER";
mode_idx = <1>;
path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER";
};
sensor1 {
subdev_name = "vivcam";
idx = <6>; //gc02m1b
csi_idx = <0>; //<0>=CSI2
mode_idx = <0>;
path_type = "SENSOR_1600x1200_RAW10_LINER";
};
isp {
subdev_name = "isp";
@@ -1674,13 +1807,14 @@
&video6{
vi_mem_pool_region = <1>; // vi_mem: framebuffer, region[1]
pipline0 {
channel0 {
sensor0 {
subdev_name = "vivcam";
idx = <4>; //sc132gs
csi_idx = <2>; //<2>=CSI2X2_A
flash_led_idx = <0>;
path_type = "SENSOR_1080P_RAW10_LINER";
mode_idx = <0>;
path_type = "SENSOR_1080X1280_30FPS_RAW10_LINER";
};
dsp{
output {
@@ -1691,13 +1825,14 @@
};
};
};
pipline1 {
channel1 {
sensor0 {
subdev_name = "vivcam";
idx = <4>; //sc132gs
csi_idx = <2>; //<2>=CSI2X2_A
flash_led_idx = <0>;
path_type = "SENSOR_1080P_RAW10_LINER";
mode_idx = <0>;
path_type = "SENSOR_1080X1280_30FPS_RAW10_LINER";
};
dsp{
output {
@@ -1712,18 +1847,20 @@
};
&video7{
pipline0 {
channel0 {
sensor0 {
subdev_name = "vivcam";
idx = <2>; //<2>=vivcam2 : gc5035
csi_idx = <1>; //<1>=CSI2X2_B
path_type = "SENSOR_1080P_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER//
mode_idx = <1>;
path_type = "SENSOR_1080P_RAW10_LINER";
};
sensor1 {
subdev_name = "vivcam";
idx = <3>; //<3>=vivcam3 : sc2310
csi_idx = <1>; //<1>=CSI2X2_B
path_type = "SENSOR_1080P_RAW12_LINER";
mode_idx = <1>;
path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER";
};
isp {
subdev_name = "isp";
@@ -1765,18 +1902,20 @@
dw_dst_depth = <2>;
};
};
pipline1 {
channel1 {
sensor0 {
subdev_name = "vivcam";
idx = <2>; //<2>=vivcam2 : gc5035
csi_idx = <1>; //<1>=CSI2X2_B
path_type = "SENSOR_1080P_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER//
mode_idx = <3>;
path_type = "SENSOR_1296x972_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER//
};
sensor1 {
subdev_name = "vivcam";
idx = <3>; //<3>=vivcam3 : sc2310
csi_idx = <1>; //<1>=CSI2X2_B
path_type = "SENSOR_1080P_RAW12_LINER";
mode_idx = <1>;
path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER";
};
isp {
subdev_name = "isp";
@@ -1818,18 +1957,20 @@
dw_dst_depth = <2>;
};
};
pipline2 {
channel2 {
sensor0 {
subdev_name = "vivcam";
idx = <2>; //<2>=vivcam2 : gc5035
csi_idx = <1>; //<1>=CSI2X2_B
path_type = "SENSOR_1080P_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER//
mode_idx = <3>;
path_type = "SENSOR_1296x972_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER//
};
sensor1 {
subdev_name = "vivcam";
idx = <3>; //<3>=vivcam3 : sc2310
csi_idx = <1>; //<1>=CSI2X2_B
path_type = "SENSOR_1080P_RAW12_LINER";
mode_idx = <1>;
path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER";
};
isp {
subdev_name = "isp";
@@ -1876,18 +2017,20 @@
&video8{
vi_mem_pool_region = <1>; // vi_mem: framebuffer, region[1]
pipline0 {
channel0 {
sensor0 {
subdev_name = "vivcam";
idx = <2>; //<2>=vivcam2 : gc5035
csi_idx = <1>; //<1>=CSI2X2_B
path_type = "SENSOR_1080P_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER//
mode_idx = <3>;
path_type = "SENSOR_1296x972_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER//
};
sensor1 {
subdev_name = "vivcam";
idx = <3>; //<3>=vivcam3 : sc2310
csi_idx = <1>; //<1>=CSI2X2_B
path_type = "SENSOR_1080P_RAW12_LINER";
mode_idx = <1>;
path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER";
};
dsp {
subdev_name = "dsp";
@@ -1904,12 +2047,13 @@
};
&video9{
pipline0 {
channel0 {
sensor0 {
subdev_name = "vivcam";
idx = <4>; //sc132gs
csi_idx = <2>; //<2>=CSI2X2_A
path_type = "SENSOR_1080P_RAW10_LINER";
mode_idx = <0>;
path_type = "SENSOR_1080X1280_30FPS_RAW10_LINER";
};
dsp{
output {
@@ -1923,33 +2067,38 @@
};
&video10{
pipline0 {
&video10{ // TUNINGTOOL
channel0 {
sensor0 {
subdev_name = "vivcam";
idx = <2>; //<2>=vivcam2 : gc5035
csi_idx = <1>; //<1>=CSI2X2_B
mode_idx = <1>;
path_type = "SENSOR_1080P_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER//
skip_init = <1>;
};
sensor1 {
subdev_name = "vivcam";
idx = <3>; //<3>=vivcam3 : sc2310
csi_idx = <1>; //<1>=CSI2X2_B
path_type = "SENSOR_1080P_RAW12_LINER";
mode_idx = <1>;
path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER";
skip_init = <1>;
};
};
};
&video11{
pipline0 {
pipline_id = <0>;
channel0 {
channel_id = <0>;
status = "okay";
sensor0 {
subdev_name = "vivcam";
idx = <4>; //sc132gs
csi_idx = <2>; //<2>=CSI2X2_A
flash_led_idx = <0>;
path_type = "SENSOR_1080P_RAW10_LINER";
mode_idx = <0>;
path_type = "SENSOR_1080X1280_30FPS_RAW10_LINER";
};
isp {
subdev_name = "isp";
@@ -1965,15 +2114,79 @@
};
};
&video12{
pipline0 { // CSI2
&video12{ // TUNINGTOOL
channel0 { // CSI2
sensor0 {
subdev_name = "vivcam";
idx = <0>; //sc2310
csi_idx = <0>; //<0>=CSI2
path_type = "SENSOR_1080P_RAW12_LINER";
mode_idx = <1>;
path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER";
skip_init = <1>;
};
sensor1 {
subdev_name = "vivcam";
idx = <6>; //gc02m1b
csi_idx = <0>; //<0>=CSI2
mode_idx = <0>;
path_type = "SENSOR_1600x1200_RAW10_LINER";
skip_init = <1>;
};
};
};
&video14{
vi_mem_pool_region = <2>; // vi_mem: framebuffer, region[0]
status = "okay";
channel0 {
channel_id = <0>;
status = "okay";
sensor0 {
subdev_name = "vivcam";
idx = <4>; //sc132gs
csi_idx = <2>; //<2>=CSI2X2_A
flash_led_idx = <0>;
mode_idx = <0>;
path_type = "SENSOR_1080X1280_30FPS_RAW10_LINER";
};
dma {
subdev_name = "vipre";
idx = <0>;
path_type = "VIPRE_CSI2_ISP1";
};
isp {
subdev_name = "isp";
idx = <1>;
path_type = "ISP_MI_MCM_WR0";
output {
max_width = <1080>;
max_height = <1280>;
bit_per_pixel = <16>;
frame_count = <3>;
};
};
};
};
&video15{
status = "okay";
//vi_mem_pool_region = <0>;
channel0 {
channel_id = <0>;
status = "okay";
sensor0 {
subdev_name = "vivcam";
idx = <0>; //<0>=vivcam0 :2310
csi_idx = <0>; //<0>=CSI2
flash_led_idx = <0>;
mode_idx = <1>;
path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER";
};
dma {
subdev_name = "vipre";
idx = <0>;
path_type = "VIPRE_CSI0_DDR";
};
};
};
@@ -2067,7 +2280,7 @@
};
};
panel0@0 {
panel0: panel0@0 {
compatible = "txd,dy800qwxpab";
reg = <0>;
backlight = <&lcd0_backlight>;

134
arch/riscv/boot/dts/thead/light-b-ref.dts Normal file
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@@ -0,0 +1,134 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2021 Alibaba Group Holding Limited.
*/
/dts-v1/;
#include "light-b-product.dts"
&aon {
/delete-node/light-ricoh-reg;
soc_vdd18_lcd0_bk_en_reg: soc_vdd18_lcd0_bk_en {
compatible = "regulator-fixed";
regulator-name = "soc_vdd18_lcd0_bk_en";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
gpio = <&gpio1_porta 9 1>;
enable-active-high;
};
aon_reg_dialog: light-dialog-reg {
compatible = "thead,light-dialog-pmic-ant";
status = "okay";
dvdd_cpu_reg: appcpu_dvdd {
regulator-name = "appcpu_dvdd";
regulator-min-microvolt = <300000>;
regulator-max-microvolt = <1570000>;
regulator-boot-on;
regulator-always-on;
};
dvddm_cpu_reg: appcpu_dvddm {
regulator-name = "appcpu_dvddm";
regulator-min-microvolt = <300000>;
regulator-max-microvolt = <1570000>;
regulator-boot-on;
regulator-always-on;
};
soc_dvdd18_aon_reg: soc_dvdd18_aon {
regulator-name = "soc_dvdd18_aon";
regulator-boot-on;
regulator-always-on;
};
soc_avdd33_usb3_reg: soc_avdd33_usb3 {
regulator-name = "soc_avdd33_usb3";
regulator-boot-on;
regulator-always-on;
};
soc_dvdd08_aon_reg: soc_dvdd08_aon {
regulator-name = "soc_dvdd08_aon";
regulator-boot-on;
regulator-always-on;
};
soc_dvdd08_ddr_reg: soc_dvdd08_ddr {
regulator-name = "soc_dvdd08_ddr";
regulator-boot-on;
regulator-always-on;
};
soc_vdd_ddr_1v8_reg: soc_vdd_ddr_1v8 {
regulator-name = "soc_vdd_ddr_1v8";
regulator-boot-on;
regulator-always-on;
};
soc_vdd_ddr_1v1_reg: soc_vdd_ddr_1v1 {
regulator-name = "soc_vdd_ddr_1v1";
regulator-boot-on;
regulator-always-on;
};
soc_vdd_ddr_0v6_reg: soc_vdd_ddr_0v6 {
regulator-name = "soc_vdd_ddr_0v6";
regulator-boot-on;
regulator-always-on;
};
soc_dvdd18_ap_reg: soc_dvdd18_ap {
regulator-name = "soc_dvdd18_ap";
regulator-boot-on;
regulator-always-on;
};
soc_avdd08_mipi_hdmi_reg: soc_avdd08_mipi_hdmi {
regulator-name = "soc_avdd08_mipi_hdmi";
regulator-boot-on;
regulator-always-on;
};
soc_avdd18_mipi_hdmi_reg: soc_avdd18_mipi_hdmi {
regulator-name = "soc_avdd18_mipi_hdmi";
regulator-boot-on;
regulator-always-on;
};
soc_vdd33_emmc_reg: soc_vdd33_emmc {
regulator-name = "soc_vdd33_emmc";
regulator-boot-on;
regulator-always-on;
};
soc_vdd18_emmc_reg: soc_vdd18_emmc {
regulator-name = "soc_vdd18_emmc";
regulator-boot-on;
regulator-always-on;
};
#if 0
soc_dovdd18_scan_reg: soc_dovdd18_scan {
regulator-name = "soc_dovdd18_scan";
};
soc_dvdd12_scan_reg: soc_dvdd12_scan {
regulator-name = "soc_dvdd12_scan";
};
soc_avdd28_scan_en_reg: soc_avdd28_scan_en {
regulator-name = "soc_avdd28_scan_en";
};
#endif
};
};
&panel0 {
vdd1v8-supply = <&soc_vdd18_lcd0_bk_en_reg>;
};

2359
arch/riscv/boot/dts/thead/light-beagle-ref.dts Normal file
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705
arch/riscv/boot/dts/thead/light-beagle.dts Normal file
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@@ -0,0 +1,705 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2021 Alibaba Group Holding Limited.
*/
/dts-v1/;
#include "light-beagle-ref.dts"
&vvcam_sensor4 { // beagle board J5 CSI0 connector
sensor_name = "IMX219";
sensor_pdn = <&gpio2_porta 23 0>; //powerdown pin / shutdown pin
sensor_pdn_delay_us = <2000>; //powerdown pin / shutdown pin actived till I2C ready
i2c_addr = /bits/ 8 <0x10>;
i2c_bus = /bits/ 8 <1>;
i2c_reg_width = /bits/ 8 <2>;
i2c_data_width = /bits/ 8 <1>;
status = "okay";
};
&vvcam_sensor5 { // beagle board J4 CSI1 connector
sensor_name = "IMX219";
sensor_pdn = <&gpio2_porta 24 0>; //powerdown pin / shutdown pin
sensor_pdn_delay_us = <2000>; //powerdown pin / shutdown pin actived till I2C ready
i2c_addr = /bits/ 8 <0x10>;
i2c_bus = /bits/ 8 <3>;
i2c_reg_width = /bits/ 8 <2>;
i2c_data_width = /bits/ 8 <1>;
status = "okay";
};
/*
sensor imx219 mounted on beagle board J4 CSI1 (=light CSI2X2_A+CSI2X2_B / CSI2X2_A only)
video0: sensor-vipre-isp0
video1: sensor-vipre-isp0-dw
video7: sensor-vipre-isp0-dsp1-ry-dw
video10: tuningtool
sensor imx219 mounted on beagle board J5 CSI0 (=light CSI2)
video2: sensor-vipre-isp1
video3: sensor-vipre-isp1-dw
video4: sensor-vipre-isp1-dsp0-ry
video5: sensor-vipre-isp1-dsp0-ry-dw
video12: tuningtool
*/
&video0{
vi_mem_pool_region = <0xFFFFFFFF>; // vi_mem: framebuffer, region[2]
channel0 {
sensor0 {
subdev_name = "vivcam";
idx = <5>; // imx219
csi_idx = <2>; //<2>=CSI2X2_A
mode_idx = <0>;
path_type = "SENSOR_1080P_RAW10_LINER";
};
sensor1 {
subdev_name = "vivcam";
idx = <0xff>; // invalid
csi_idx = <0xff>;
path_type = "SENSOR_VGA_RAW10_LINER";
};
dma {
subdev_name = "vipre";
idx = <0>;
path_type = "VIPRE_CSI2_ISP0";
};
isp {
subdev_name = "isp";
idx = <0>;
path_type = "ISP_MI_PATH_MP";
output {
max_width = <1920>;
max_height = <1088>;
bit_per_pixel = <16>;
frame_count = <3>;
};
};
};
channel1 {
sensor0 {
subdev_name = "vivcam";
idx = <5>; // imx219
csi_idx = <2>; //<2>=CSI2X2_A
mode_idx = <0>;
path_type = "SENSOR_1080P_RAW10_LINER";
};
sensor1 {
subdev_name = "vivcam";
idx = <0xff>; // invalid
csi_idx = <0xff>;
path_type = "SENSOR_VGA_RAW10_LINER";
};
dma {
subdev_name = "vipre";
idx = <0>;
path_type = "VIPRE_CSI2_ISP0";
};
isp {
subdev_name = "isp";
idx = <0>;
path_type = "ISP_MI_PATH_SP";
output {
max_width = <1920>;
max_height = <1088>;
bit_per_pixel = <16>;
frame_count = <3>;
};
};
};
channel2 {
sensor0 {
subdev_name = "vivcam";
idx = <5>; // imx219
csi_idx = <2>; //<2>=CSI2X2_A
mode_idx = <0>;
path_type = "SENSOR_1080P_RAW10_LINER";
};
sensor1 {
subdev_name = "vivcam";
idx = <0xff>; // invalid
csi_idx = <0xff>;
path_type = "SENSOR_VGA_RAW10_LINER";
};
dma {
subdev_name = "vipre";
idx = <0>;
path_type = "VIPRE_CSI2_ISP0";
};
isp {
subdev_name = "isp";
idx = <0>;
path_type = "ISP_MI_PATH_SP2_BP";
output {
max_width = <1920>;
max_height = <1088>;
bit_per_pixel = <16>;
frame_count = <3>;
};
};
};
};
&video2 {
vi_mem_pool_region = <0>; // vi_mem: framebuffer, region[0]
status = "okay";
channel0 {
channel_id = <0>;
status = "okay";
sensor0 {
subdev_name = "vivcam";
idx = <4>; // imx219
csi_idx = <0>; //<0>=CSI2
mode_idx = <0>;
path_type = "SENSOR_1080P_RAW10_LINER";
};
sensor1 {
subdev_name = "vivcam";
idx = <0xff>; // invalid
csi_idx = <0xff>;
path_type = "SENSOR_VGA_RAW10_LINER";
};
dma {
subdev_name = "vipre";
idx = <0>;
path_type = "VIPRE_CSI0_ISP1";
};
isp {
subdev_name = "isp";
idx = <1>;
path_type = "ISP_MI_PATH_MP";
output {
max_width = <1920>;
max_height = <1088>;
bit_per_pixel = <16>;
frame_count = <3>;
};
};
};
channel1 {
channel_id = <1>;
status = "okay";
sensor0 {
subdev_name = "vivcam";
idx = <4>; // imx219
csi_idx = <0>; //<0>=CSI2
mode_idx = <0>;
path_type = "SENSOR_1080P_RAW10_LINER";
};
sensor1 {
subdev_name = "vivcam";
idx = <0xff>; // invalid
csi_idx = <0xff>;
path_type = "SENSOR_VGA_RAW10_LINER";
};
dma {
subdev_name = "vipre";
idx = <0>;
path_type = "VIPRE_CSI0_ISP1";
};
isp {
subdev_name = "isp";
idx = <1>;
path_type = "ISP_MI_PATH_SP";
output {
max_width = <1920>;
max_height = <1088>;
bit_per_pixel = <16>;
frame_count = <3>;
};
};
};
channel2 {
channel_id = <2>;
status = "okay";
sensor0 {
subdev_name = "vivcam";
idx = <4>; // imx219
csi_idx = <0>; //<0>=CSI2
mode_idx = <0>;
path_type = "SENSOR_1080P_RAW10_LINER";
};
sensor1 {
subdev_name = "vivcam";
idx = <0xff>; // invalid
csi_idx = <0xff>;
path_type = "SENSOR_VGA_RAW10_LINER";
};
dma {
subdev_name = "vipre";
idx = <0>;
path_type = "VIPRE_CSI0_ISP1";
};
isp {
subdev_name = "isp";
idx = <1>;
path_type = "ISP_MI_PATH_SP2_BP";
output {
max_width = <1920>;
max_height = <1088>;
bit_per_pixel = <16>;
frame_count = <3>;
};
};
};
};
&video3{
vi_mem_pool_region = <0>; // vi_mem: framebuffer, region[0]
channel0 {
sensor0 {
subdev_name = "vivcam";
idx = <4>; // imx219
csi_idx = <0>; //<0>=CSI2
mode_idx = <0>;
path_type = "SENSOR_1080P_RAW10_LINER";
};
sensor1 {
subdev_name = "vivcam";
idx = <0xff>; // invalid
csi_idx = <0xff>;
path_type = "SENSOR_VGA_RAW10_LINER";
};
dma {
subdev_name = "vipre";
idx = <0>;
path_type = "VIPRE_CSI0_ISP1";
};
isp {
subdev_name = "isp";
idx = <1>;
path_type = "ISP_MI_PATH_MP";
output {
max_width = <1920>;
max_height = <1088>;
bit_per_pixel = <12>;
frame_count = <3>;
};
};
dw {
subdev_name = "dw";
idx = <0>;
path_type = "DW_DWE_VSE0";
dw_dst_depth = <2>;
};
};
channel1 {
sensor0 {
subdev_name = "vivcam";
idx = <4>; // imx219
csi_idx = <0>; //<0>=CSI2
mode_idx = <0>;
path_type = "SENSOR_1080P_RAW10_LINER";
};
sensor1 {
subdev_name = "vivcam";
idx = <0xff>; // invalid
csi_idx = <0xff>;
path_type = "SENSOR_VGA_RAW10_LINER";
};
dma {
subdev_name = "vipre";
idx = <0>;
path_type = "VIPRE_CSI0_ISP1";
};
isp {
subdev_name = "isp";
idx = <1>;
path_type = "ISP_MI_PATH_MP";
output {
max_width = <1920>;
max_height = <1088>;
bit_per_pixel = <12>;
frame_count = <3>;
};
};
dw {
subdev_name = "dw";
idx = <0>;
path_type = "DW_DWE_VSE1";
dw_dst_depth = <2>;
};
};
channel2 {
sensor0 {
subdev_name = "vivcam";
idx = <4>; // imx219
csi_idx = <0>; //<0>=CSI2
mode_idx = <0>;
path_type = "SENSOR_1080P_RAW10_LINER";
};
sensor1 {
subdev_name = "vivcam";
idx = <0xff>; // invalid
csi_idx = <0xff>;
path_type = "SENSOR_VGA_RAW10_LINER";
};
dma {
subdev_name = "vipre";
idx = <0>;
path_type = "VIPRE_CSI0_ISP1";
};
isp {
subdev_name = "isp";
idx = <1>;
path_type = "ISP_MI_PATH_MP";
output {
max_width = <1920>;
max_height = <1088>;
bit_per_pixel = <12>;
frame_count = <3>;
};
};
dw {
subdev_name = "dw";
idx = <0>;
path_type = "DW_DWE_VSE2";
dw_dst_depth = <2>;
};
};
};
&video4{
vi_mem_pool_region = <0>; // vi_mem: framebuffer, region[0]
channel0 {
sensor0 {
subdev_name = "vivcam";
idx = <4>; // imx219
csi_idx = <0>; //<0>=CSI2
mode_idx = <0>;
path_type = "SENSOR_1080P_RAW10_LINER";
};
sensor1 {
subdev_name = "vivcam";
idx = <0xff>; // invalid
csi_idx = <0xff>;
path_type = "SENSOR_VGA_RAW10_LINER";
};
dma {
subdev_name = "vipre";
idx = <0>;
path_type = "VIPRE_CSI0_ISP1";
};
isp {
subdev_name = "isp";
idx = <1>;
path_type = "ISP_MI_PATH_PP";
output {
max_width = <1920>;
max_height = <1088>;
bit_per_pixel = <12>;
frame_count = <3>;
};
};
dsp {
subdev_name = "dsp";
idx = <0>;
path_type = "DSP_PATH_ISP_RY";
output {
max_width = <1920>;
max_height = <1088>;
bit_per_pixel = <12>;
frame_count = <3>;
};
};
ry {
subdev_name = "ry";
idx = <0>;
path_type = "ISP_RY_MI_PATH_MP";
output {
max_width = <1920>;
max_height = <1088>;
bit_per_pixel = <12>;
frame_count = <3>;
};
};
};
channel1 {
sensor0 {
subdev_name = "vivcam";
idx = <4>; // imx219
csi_idx = <0>; //<0>=CSI2
mode_idx = <0>;
path_type = "SENSOR_1080P_RAW10_LINER";
};
sensor1 {
subdev_name = "vivcam";
idx = <0xff>; // invalid
csi_idx = <0xff>;
path_type = "SENSOR_VGA_RAW10_LINER";
};
dma {
subdev_name = "vipre";
idx = <0>;
path_type = "VIPRE_CSI0_ISP1";
};
isp {
subdev_name = "isp";
idx = <1>;
path_type = "ISP_MI_PATH_PP";
output {
max_width = <1920>;
max_height = <1088>;
bit_per_pixel = <12>;
frame_count = <3>;
};
};
dsp {
subdev_name = "dsp";
idx = <0>;
path_type = "DSP_PATH_ISP_RY";
output {
max_width = <1920>;
max_height = <1088>;
bit_per_pixel = <12>;
frame_count = <3>;
};
};
ry {
subdev_name = "ry";
idx = <0>;
path_type = "ISP_RY_MI_PATH_SP";
output {
max_width = <1920>;
max_height = <1088>;
bit_per_pixel = <12>;
frame_count = <3>;
};
};
};
channel2 {
sensor0 {
subdev_name = "vivcam";
idx = <4>; // imx219
csi_idx = <0>; //<0>=CSI2
mode_idx = <0>;
path_type = "SENSOR_1080P_RAW10_LINER";
};
sensor1 {
subdev_name = "vivcam";
idx = <0xff>; // invalid
csi_idx = <0xff>;
path_type = "SENSOR_VGA_RAW10_LINER";
};
dma {
subdev_name = "vipre";
idx = <0>;
path_type = "VIPRE_CSI0_ISP1";
};
isp {
subdev_name = "isp";
idx = <1>;
path_type = "ISP_MI_PATH_PP";
output {
max_width = <1920>;
max_height = <1088>;
bit_per_pixel = <12>;
frame_count = <3>;
};
};
dsp {
subdev_name = "dsp";
idx = <0>;
path_type = "DSP_PATH_ISP_RY";
output {
max_width = <1920>;
max_height = <1088>;
bit_per_pixel = <12>;
frame_count = <3>;
};
};
ry {
subdev_name = "ry";
idx = <0>;
path_type = "ISP_RY_MI_PATH_SP2_BP";
output {
max_width = <1920>;
max_height = <1088>;
bit_per_pixel = <12>;
frame_count = <3>;
};
};
};
};
&video5{
vi_mem_pool_region = <0>; // vi_mem: framebuffer, region[0]
channel0 {
sensor0 {
subdev_name = "vivcam";
idx = <4>; // imx219
csi_idx = <0>; //<0>=CSI2
mode_idx = <0>;
path_type = "SENSOR_1080P_RAW10_LINER";
};
sensor1 {
subdev_name = "vivcam";
idx = <0xff>; // invalid
csi_idx = <0xff>;
path_type = "SENSOR_VGA_RAW10_LINER";
};
dma {
subdev_name = "vipre";
idx = <0>;
path_type = "VIPRE_CSI0_ISP1";
};
isp {
subdev_name = "isp";
idx = <1>;
path_type = "ISP_MI_PATH_PP";
output {
max_width = <1920>;
max_height = <1088>;
bit_per_pixel = <12>;
frame_count = <3>;
};
};
dsp {
subdev_name = "dsp";
idx = <0>;
path_type = "DSP_PATH_ISP_RY";
output {
max_width = <1920>;
max_height = <1088>;
bit_per_pixel = <12>;
frame_count = <3>;
};
};
ry {
subdev_name = "ry";
idx = <0>;
path_type = "ISP_RY_MI_PATH_MP";
output {
max_width = <1920>;
max_height = <1088>;
bit_per_pixel = <12>;
frame_count = <3>;
};
};
dw {
subdev_name = "dw";
idx = <0>;
path_type = "DW_DWE_VSE0";
dw_dst_depth = <2>;
};
};
channel1 {
sensor0 {
subdev_name = "vivcam";
idx = <4>; // imx219
csi_idx = <0>; //<0>=CSI2
mode_idx = <0>;
path_type = "SENSOR_1080P_RAW10_LINER";
};
sensor1 {
subdev_name = "vivcam";
idx = <0xff>; // invalid
csi_idx = <0xff>;
path_type = "SENSOR_VGA_RAW10_LINER";
};
dma {
subdev_name = "vipre";
idx = <0>;
path_type = "VIPRE_CSI0_ISP1";
};
isp {
subdev_name = "isp";
idx = <1>;
path_type = "ISP_MI_PATH_PP";
output {
max_width = <1920>;
max_height = <1088>;
bit_per_pixel = <12>;
frame_count = <3>;
};
};
dsp {
subdev_name = "dsp";
idx = <0>;
path_type = "DSP_PATH_ISP_RY";
output {
max_width = <1920>;
max_height = <1088>;
bit_per_pixel = <12>;
frame_count = <3>;
};
};
ry {
subdev_name = "ry";
idx = <0>;
path_type = "ISP_RY_MI_PATH_MP";
output {
max_width = <1920>;
max_height = <1088>;
bit_per_pixel = <12>;
frame_count = <3>;
};
};
dw {
subdev_name = "dw";
idx = <0>;
path_type = "DW_DWE_VSE1";
dw_dst_depth = <2>;
};
};
channel2 {
sensor0 {
subdev_name = "vivcam";
idx = <4>; // imx219
csi_idx = <0>; //<0>=CSI2
mode_idx = <0>;
path_type = "SENSOR_1080P_RAW10_LINER";
};
sensor1 {
subdev_name = "vivcam";
idx = <0xff>; // invalid
csi_idx = <0xff>;
path_type = "SENSOR_VGA_RAW10_LINER";
};
dma {
subdev_name = "vipre";
idx = <0>;
path_type = "VIPRE_CSI0_ISP1";
};
isp {
subdev_name = "isp";
idx = <1>;
path_type = "ISP_MI_PATH_PP";
output {
max_width = <1920>;
max_height = <1088>;
bit_per_pixel = <12>;
frame_count = <3>;
};
};
dsp {
subdev_name = "dsp";
idx = <0>;
path_type = "DSP_PATH_ISP_RY";
output {
max_width = <1920>;
max_height = <1088>;
bit_per_pixel = <12>;
frame_count = <3>;
};
};
ry {
subdev_name = "ry";
idx = <0>;
path_type = "ISP_RY_MI_PATH_MP";
output {
max_width = <1920>;
max_height = <1088>;
bit_per_pixel = <12>;
frame_count = <3>;
};
};
dw {
subdev_name = "dw";
idx = <0>;
path_type = "DW_DWE_VSE2";
dw_dst_depth = <2>;
};
};
};

883
arch/riscv/boot/dts/thead/light-crash.dts Normal file
View File

@@ -0,0 +1,883 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2021 Alibaba Group Holding Limited.
*/
/dts-v1/;
#include "light.dtsi"
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/gpio/gpio.h>
#include "light-vi-devices.dtsi"
/ {
model = "T-HEAD Light val board";
compatible = "thead,light-val", "thead,light";
chosen {
bootargs = "console=ttyS0,115200 earlycon";
stdout-path = "serial0:115200n8";
};
leds {
compatible = "gpio-leds";
status = "disabled";
led0 {
label = "SYS_STATUS";
gpios = <&gpio1_porta 15 0>; /* GPIO_ACTIVE_HIGH: 0 */
default-state = "off";
};
};
display-subsystem {
status = "okay";
};
lcd0_backlight: pwm-backlight@0 {
status = "disabled";
compatible = "pwm-backlight";
pwms = <&pwm 0 5000000>;
brightness-levels = <0 4 8 16 32 64 128 255>;
default-brightness-level = <7>;
};
light_iopmp: iopmp {
status = "disabled";
compatible = "thead,light-iopmp";
/* config#1: multiple valid regions */
iopmp_emmc: IOPMP_EMMC {
regions = <0x000000 0x100000>,
<0x100000 0x200000>;
attr = <0xFFFFFFFF>;
dummy_slave= <0x800000>;
};
/* config#2: iopmp bypass */
iopmp_sdio0: IOPMP_SDIO0 {
bypass_en;
};
/* config#3: iopmp default region set */
iopmp_sdio1: IOPMP_SDIO1 {
attr = <0xFFFFFFFF>;
is_default_region;
};
iopmp_usb0: IOPMP_USB0 {
attr = <0xFFFFFFFF>;
is_default_region;
};
iopmp_ao: IOPMP_AO {
is_default_region;
};
iopmp_aud: IOPMP_AUD {
is_default_region;
};
iopmp_chip_dbg: IOPMP_CHIP_DBG {
is_default_region;
};
iopmp_eip120i: IOPMP_EIP120I {
is_default_region;
};
iopmp_eip120ii: IOPMP_EIP120II {
is_default_region;
};
iopmp_eip120iii: IOPMP_EIP120III {
is_default_region;
};
iopmp_isp0: IOPMP_ISP0 {
is_default_region;
};
iopmp_isp1: IOPMP_ISP1 {
is_default_region;
};
iopmp_dw200: IOPMP_DW200 {
is_default_region;
};
iopmp_vipre: IOPMP_VIPRE {
is_default_region;
};
iopmp_venc: IOPMP_VENC {
is_default_region;
};
iopmp_vdec: IOPMP_VDEC {
is_default_region;
};
iopmp_g2d: IOPMP_G2D {
is_default_region;
};
iopmp_fce: IOPMP_FCE {
is_default_region;
};
iopmp_npu: IOPMP_NPU {
is_default_region;
};
iopmp0_dpu: IOPMP0_DPU {
bypass_en;
};
iopmp1_dpu: IOPMP1_DPU {
bypass_en;
};
iopmp_gpu: IOPMP_GPU {
is_default_region;
};
iopmp_gmac1: IOPMP_GMAC1 {
is_default_region;
};
iopmp_gmac2: IOPMP_GMAC2 {
is_default_region;
};
iopmp_dmac: IOPMP_DMAC {
is_default_region;
};
iopmp_tee_dmac: IOPMP_TEE_DMAC {
is_default_region;
};
iopmp_dsp0: IOPMP_DSP0 {
is_default_region;
};
iopmp_dsp1: IOPMP_DSP1 {
is_default_region;
};
};
mbox_910t_client1: mbox_910t_client1 {
compatible = "thead,light-mbox-client";
mbox-names = "902";
mboxes = <&mbox_910t 1 0>;
status = "disabled";
};
mbox_910t_client2: mbox_910t_client2 {
compatible = "thead,light-mbox-client";
mbox-names = "906";
mboxes = <&mbox_910t 2 0>;
status = "disabled";
};
lightsound: lightsound@1 {
compatible = "simple-audio-card";
simple-audio-card,name = "Light-Sound-Card";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
dummy_codec: dummy_codec {
#sound-dai-cells = <1>;
compatible = "linux,bt-sco";
status = "okay";
};
reg_vref_1v8: regulator-adc-verf {
compatible = "regulator-fixed";
regulator-name = "vref-1v8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
status = "okay";
};
reg_tp_pwr_en: regulator-pwr-en {
compatible = "regulator-fixed";
regulator-name = "PWR_EN";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
gpio = <&gpio1_porta 12 1>;
enable-active-high;
regulator-always-on;
};
wcn_wifi: wireless-wlan {
compatible = "wlan-platdata";
clock-names = "clk_wifi";
ref-clock-frequency = <24000000>;
keep_wifi_power_on;
pinctrl-names = "default";
wifi_chip_type = "rtl8723ds";
WIFI,poweren_gpio = <&gpio2_porta 29 0>;
WIFI,reset_n = <&gpio2_porta 24 0>;
status = "okay";
};
wcn_bt: wireless-bluetooth {
compatible = "bluetooth-platdata";
pinctrl-names = "default", "rts_gpio";
BT,power_gpio = <&gpio2_porta 25 0>;
status = "okay";
};
gpio-keys {
compatible = "gpio-keys";
pinctrl-0 = <&pinctrl_volume>;
pinctrl-names = "default";
key-volumedown {
label = "Volume Down Key";
linux,code = <KEY_VOLUMEDOWN>;
debounce-interval = <1>;
gpios = <&ao_gpio_porta 11 0x1>;
};
key-volumeup {
label = "Volume Up Key";
linux,code = <KEY_VOLUMEUP>;
debounce-interval = <1>;
gpios = <&ao_gpio_porta 10 0x1>;
};
};
aon: light-aon {
compatible = "thead,light-aon";
mbox-names = "aon";
mboxes = <&mbox_910t 1 0>;
status = "okay";
pd: light-aon-pd {
compatible = "thead,light-aon-pd";
#power-domain-cells = <1>;
};
c910_cpufreq {
compatible = "thead,light-mpw-cpufreq";
status = "okay";
};
test: light-aon-test {
compatible = "thead,light-aon-test";
};
};
};
&resmem {
#address-cells = <2>;
#size-cells = <2>;
ranges;
tee_mem: memory@1a000000 {
reg = <0x0 0x1a000000 0 0x4000000>;
no-map;
};
dsp0_mem: memory@20000000 { /**0x2000_0000~0x2040_0000 4M**/
reg = <0x0 0x20000000 0x0 0x00280000 /* DSP FW code&data section 2.5M*/
0x0 0x20280000 0x0 0x00001000 /* DSP communication area 4K*/
0x0 0x20281000 0x0 0x00007000 /* Panic/log page 28K */
0x0 0x20288000 0x0 0x00178000>; /* DSP shared memory 1.5M-32K*/
no-map;
};
dsp1_mem: memory@20400000 { /**0x2040_0000~0x2080_0000 4M**/
reg = <0x0 0x20400000 0x0 0x00280000 /* DSP FW code&data section */
0x0 0x20680000 0x0 0x00001000 /* DSP communication area */
0x0 0x20681000 0x0 0x00007000 /* Panic/log page*/
0x0 0x20688000 0x0 0x00178000>; /* DSP shared memory */
no-map;
};
vi_mem: framebuffer@10000000 {
reg = <0x0 0x10000000 0x0 0x02C00000 /* vi_mem_pool_region[0] 44 MB (default) */
0x0 0x12C00000 0x0 0x01D00000 /* vi_mem_pool_region[1] 29 MB */
0x0 0x14900000 0x0 0x01E00000>; /* vi_mem_pool_region[2] 30 MB */
no-map;
};
facelib_mem: memory@17000000 {
reg = <0x0 0x17000000 0 0x02000000>;
no-map;
};
};
&adc {
vref-supply = <&reg_vref_1v8>;
status = "okay";
};
&i2c0 {
clock-frequency = <100000>;
status = "okay";
touch@5d {
#gpio-cells = <2>;
compatible = "goodix,gt911";
reg = <0x5d>;
interrupt-parent = <&gpio1_porta>;
interrupts = <8 0>;
irq-gpios = <&gpio1_porta 8 0>;
reset-gpios = <&gpio1_porta 7 0>;
AVDD28-supply = <&reg_tp_pwr_en>;
touchscreen-size-x = <800>;
touchscreen-size-y = <1280>;
};
};
&audio_i2c0 {
clock-frequency = <100000>;
status = "okay";
es8156_audio_codec: es8156@8 {
#sound-dai-cells = <0>;
compatible = "everest,es8156";
reg = <0x08>;
};
es7210_audio_codec: es7210@40 {
#sound-dai-cells = <0>;
compatible = "MicArray_0";
reg = <0x40>;
};
audio_aw87519_pa@58 {
compatible = "awinic,aw87519_pa";
reg = <0x58>;
reset-gpio = <&ao_gpio4_porta 9 0x1>;
status = "okay";
};
};
&i2c1 {
clock-frequency = <100000>;
status = "okay";
};
&spi0 {
num-cs = <1>;
cs-gpios = <&gpio2_porta 15 0>; // GPIO_ACTIVE_HIGH: 0
rx-sample-delay-ns = <10>;
status = "disabled";
spi_norflash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "winbond,w25q64jwm", "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <50000000>;
w25q,fast-read;
};
spidev@1 {
compatible = "spidev";
#address-cells = <0x1>;
#size-cells = <0x1>;
reg = <0x1>;
spi-max-frequency = <50000000>;
};
};
&uart0 {
clocks = <&dummy_clock_uart_sclk>;
clock-names = "baudclk";
clock-frequency = <100000000>;
};
&qspi0 {
num-cs = <1>;
cs-gpios = <&gpio2_porta 3 0>;
rx-sample-dly = <4>;
status = "disabled";
spi-flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spi-nand";
spi-max-frequency = <100000000>;
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
reg = <0>;
partition@0 {
label = "ubi1";
reg = <0x00000000 0x08000000>;
};
};
};
&qspi1 {
compatible = "snps,dw-apb-ssi";
num-cs = <1>;
cs-gpios = <&gpio0_porta 1 0>;
status = "disabled";
spidev@0 {
compatible = "spidev";
#address-cells = <0x1>;
#size-cells = <0x1>;
reg = <0x0>;
spi-max-frequency = <50000000>;
};
};
&gmac0 {
phy-mode = "rgmii-id";
rx-clk-delay = <0x00>; /* for RGMII */
tx-clk-delay = <0x00>; /* for RGMII */
phy-handle = <&phy_88E1111_0>;
status = "okay";
mdio0 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,dwmac-mdio";
phy_88E1111_0: ethernet-phy@0 {
reg = <0x1>;
};
phy_88E1111_1: ethernet-phy@1 {
reg = <0x2>;
};
};
};
&gmac1 {
phy-mode = "rgmii-id";
rx-clk-delay = <0x00>; /* for RGMII */
tx-clk-delay = <0x00>; /* for RGMII */
phy-handle = <&phy_88E1111_1>;
status = "okay";
};
&emmc {
max-frequency = <198000000>;
non-removable;
mmc-hs400-1_8v;
io_fixed_1v8;
is_emmc;
no-sdio;
no-sd;
pull_up;
bus-width = <8>;
status = "okay";
};
&sdhci0 {
max-frequency = <198000000>;
bus-width = <4>;
pull_up;
wprtn_ignore;
status = "okay";
};
&sdhci1 {
max-frequency = <100000000>;
bus-width = <4>;
pull_up;
no-sd;
no-mmc;
non-removable;
io_fixed_1v8;
post-power-on-delay-ms = <50>;
wprtn_ignore;
cap-sd-highspeed;
keep-power-in-suspend;
wakeup-source;
status = "okay";
};
&padctrl0_apsys { /* right-pinctrl */
light-evb-padctrl0 {
/*
* Pin Configuration Node:
* Format: <pin_id mux_node config>
*/
pinctrl_uart0: uart0grp {
thead,pins = <
FM_UART0_TXD 0x0 0x72
FM_UART0_RXD 0x0 0x72
>;
};
pinctrl_spi0: spi0grp {
thead,pins = <
FM_SPI_CSN 0x3 0x20a
FM_SPI_SCLK 0x0 0x20a
FM_SPI_MISO 0x0 0x23a
FM_SPI_MOSI 0x0 0x23a
>;
};
pinctrl_qspi0: qspi0grp {
thead,pins = <
FM_QSPI0_SCLK 0x0 0x20f
FM_QSPI0_CSN0 0x3 0x20f
FM_QSPI0_CSN1 0x0 0x20f
FM_QSPI0_D0_MOSI 0x0 0x23f
FM_QSPI0_D1_MISO 0x0 0x23f
FM_QSPI0_D2_WP 0x0 0x23f
FM_QSPI0_D3_HOLD 0x0 0x23f
>;
};
pinctrl_audio_i2s0: i2s0grp {
thead,pins = <
FM_QSPI0_SCLK 0x2 0x208
FM_QSPI0_CSN0 0x2 0x238
FM_QSPI0_CSN1 0x2 0x208
FM_QSPI0_D0_MOSI 0x2 0x238
FM_QSPI0_D1_MISO 0x2 0x238
FM_QSPI0_D2_WP 0x2 0x238
FM_QSPI0_D3_HOLD 0x2 0x238
>;
};
pinctrl_pwm: pwmgrp {
thead,pins = <
FM_GPIO3_2 0x1 0x208 /* pwm0 */
>;
};
};
};
&padctrl1_apsys { /* left-pinctrl */
light-evb-padctrl1 {
/*
* Pin Configuration Node:
* Format: <pin_id mux_node config>
*/
pinctrl_uart3: uart3grp {
thead,pins = <
FM_UART3_TXD 0x0 0x72
FM_UART3_RXD 0x0 0x72
>;
};
pinctrl_uart4: uart4grp {
thead,pins = <
FM_UART4_TXD 0x0 0x72
FM_UART4_RXD 0x0 0x72
FM_UART4_CTSN 0x0 0x72
FM_UART4_RTSN 0x0 0x72
>;
};
pinctrl_qspi1: qspi1grp {
thead,pins = <
FM_QSPI1_SCLK 0x0 0x20a
FM_QSPI1_CSN0 0x3 0x20a
FM_QSPI1_D0_MOSI 0x0 0x23a
FM_QSPI1_D1_MISO 0x0 0x23a
FM_QSPI1_D2_WP 0x0 0x23a
FM_QSPI1_D3_HOLD 0x0 0x23a
>;
};
pinctrl_iso7816: iso7816grp {
thead,pins = <
FM_QSPI1_SCLK 0x1 0x208
FM_QSPI1_D0_MOSI 0x1 0x238
FM_QSPI1_D1_MISO 0x1 0x238
FM_QSPI1_D2_WP 0x1 0x238
FM_QSPI1_D3_HOLD 0x1 0x238
>;
};
};
};
&padctrl_aosys {
light-aon-padctrl {
/*
* Pin Configuration Node:
* Format: <pin_id mux_node config>
*/
pinctrl_audiopa1: audiopa1_grp {
thead,pins = <
FM_AUDIO_PA1 0x3 0x72
>;
};
pinctrl_audiopa2: audiopa2_grp {
thead,pins = <
FM_AUDIO_PA2 0x0 0x72
>;
};
pinctrl_volume: volume_grp {
thead,pins = <
FM_AOGPIO_11 0x0 0x208
FM_AOGPIO_10 0x3 0x208
>;
};
};
};
&i2c0 {
clock-frequency = <400000>;
status = "okay";
};
&i2c1 {
clock-frequency = <400000>;
status = "okay";
};
&i2c2 {
clock-frequency = <400000>;
status = "okay";
};
&i2c3 {
clock-frequency = <400000>;
status = "okay";
};
&i2c4 {
clock-frequency = <400000>;
status = "okay";
};
&isp0 {
status = "disabled";
};
&isp1 {
status = "disabled";
};
&isp_ry0 {
status = "disabled";
};
&dewarp {
status = "disabled";
};
&dec400_isp0 {
status = "disabled";
};
&dec400_isp1 {
status = "disabled";
};
&dec400_isp2 {
status = "disabled";
};
&bm_visys {
status = "disabled";
};
&bm_csi0 {
status = "disabled";
};
&bm_csi1 {
status = "disabled";
};
&bm_csi2 {
status = "disabled";
};
&vi_pre {
status = "disabled";
};
&xtensa_dsp {
status = "disabled";
};
&xtensa_dsp0 {
status = "disabled";
};
&xtensa_dsp1 {
status = "disabled";
};
&vvcam_flash_led0{
status = "disabled";
};
&vvcam_sensor0 {
status = "disabled";
};
&vvcam_sensor1 {
status = "disabled";
};
&vvcam_sensor2 {
status = "disabled";
};
&vvcam_sensor3 {
status = "disabled";
};
&vvcam_sensor4 {
status = "disabled";
};
&vvcam_sensor5 {
status = "disabled";
};
&video0{
status = "disabled";
};
&video1{
status = "disabled";
};
&video2{
status = "disabled";
};
&video3{
status = "disabled";
};
&video4{
status = "disabled";
};
&video5{
status = "disabled";
};
&video6{
status = "disabled";
};
&video7{
status = "disabled";
};
&video8{
status = "disabled";
};
&video9{
status = "disabled";
};
&video10{
status = "disabled";
};
&video11{
status = "disabled";
};
&video12{
status = "disabled";
};
&trng {
status = "disabled";
};
&eip_28 {
status = "disabled";
};
&vdec {
status = "disabled";
};
&venc {
status = "disabled";
};
&isp_venc_shake {
status = "disabled";
};
&vidmem {
status = "disabled";
};
&gpu {
status = "disabled";
};
&npu {
status = "disabled";
};
&fce {
status = "disabled";
};
&dpu_enc0 {
status = "disabled";
};
&dpu_enc1 {
status = "disabled";
};
&dpu {
status = "disabled";
};
&dsi0 {
status = "disabled";
};
&dhost_0 {
status = "disabled";
};
&disp1_out {
status = "disabled";
};
&hdmi_tx {
status = "disabled";
};
&lightsound {
status = "disabled";
};
&light_i2s {
status = "okay";
};
&i2s0 {
status = "okay";
};
&i2s1 {
status = "okay";
};
&i2s3 {
status = "okay";
};
&khvhost {
status = "disabled";
};

6
arch/riscv/boot/dts/thead/light-evb.dtsi
View File

@@ -42,6 +42,7 @@
vivcam3= &vvcam_sensor3;
vivcam4= &vvcam_sensor4;
vivcam5= &vvcam_sensor5;
vivcam6= &vvcam_sensor6;
};
memory@0 {
@@ -1574,6 +1575,11 @@
compatible = "thead,light-vvcam-sensor";
status = "disabled";
};
vvcam_sensor6: vvcam_sensor@6 {
compatible = "thead,light-vvcam-sensor";
status = "disabled";
};
xtensa_dsp: dsp@01{
compatible = "thead,dsp-hw-common";

4
arch/riscv/boot/dts/thead/light-fm-emu.dts
View File

@@ -451,8 +451,8 @@
&video{
status = "okay";
piplane0 {
pipline_id = <0>;
channel0 {
channel_id = <0>;
status = "okay";
sensor0 {
subdev_name = "vivcam";

20
arch/riscv/boot/dts/thead/light-lpi4a-ddr2G.dts Normal file
View File

@@ -0,0 +1,20 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2022 Alibaba Group Holding Limited.
*/
#include "light-lpi4a.dts"
/ {
model = "T-HEAD Light Lichee Pi 4A configuration for 2GB DDR board";
compatible = "thead,light-val", "thead,light-lpi4a-ddr2G", "thead,light";
memory@0 {
device_type = "memory";
reg = <0x0 0x00000000 0x0 0x80000000>;
};
};
&cmamem {
alloc-ranges = <0 0x64000000 0 0x14000000>; // [0x6400_0000 ~ 0x7800_0000]
};

1516
arch/riscv/boot/dts/thead/light-lpi4a-ref.dts Normal file
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File diff suppressed because it is too large Load Diff

27
arch/riscv/boot/dts/thead/light-lpi4a.dts Normal file
View File

@@ -0,0 +1,27 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2022 Alibaba Group Holding Limited.
*/
#include "light-lpi4a-ref.dts"
/ {
model = "T-HEAD Light Lichee Pi 4A configuration for 4GB DDR board";
compatible = "thead,light-val", "thead,light-lpi4a", "thead,light";
memory@0 {
device_type = "memory";
reg = <0x0 0x00000000 0x1 0x00000000>;
};
};
&cmamem {
alloc-ranges = <0 0xe4000000 0 0x14000000>; // [0xE400_0000 ~ 0xF800_0000]
};
&usb_1 {
hubswitch-gpio = <&ao_gpio_porta 4 0>;
vbus-supply = <&soc_vbus_en_reg>;
hub1v2-supply = <&reg_usb_hub_vdd1v2>;
hub5v-supply = <&reg_usb_hub_vcc5v>;
};

116
arch/riscv/boot/dts/thead/light-vi-devices.dtsi
View File

@@ -5,8 +5,8 @@
&video0{
status = "okay";
pipline0 {
pipline_id = <0>;
channel0 {
channel_id = <0>;
status = "okay";
sensor0 {
subdev_name = "vivcam";
@@ -31,8 +31,8 @@
path_type = "ISP_MI_PATH_MP";
};
};
pipline1 {
pipline_id = <1>;
channel1 {
channel_id = <1>;
status = "okay";
sensor0 {
subdev_name = "vivcam";
@@ -57,8 +57,8 @@
path_type = "ISP_MI_PATH_SP";
};
};
pipline2 {
pipline_id = <2>;
channel2 {
channel_id = <2>;
status = "okay";
sensor0 {
subdev_name = "vivcam";
@@ -87,8 +87,8 @@
&video1{
status = "okay";
pipline0 { // VSE0
pipline_id = <0>;
channel0 { // VSE0
channel_id = <0>;
status = "okay";
sensor0 {
subdev_name = "vivcam";
@@ -118,8 +118,8 @@
path_type = "DW_DWE_VSE0";
};
};
pipline1 { // VSE1
pipline_id = <1>;
channel1 { // VSE1
channel_id = <1>;
status = "okay";
sensor0 {
subdev_name = "vivcam";
@@ -149,8 +149,8 @@
path_type = "DW_DWE_VSE1";
};
};
pipline2 { // VSE2
pipline_id = <2>;
channel2 { // VSE2
channel_id = <2>;
status = "okay";
sensor0 {
subdev_name = "vivcam";
@@ -184,8 +184,8 @@
&video2 {
status = "okay";
pipline0 {
pipline_id = <0>;
channel0 {
channel_id = <0>;
status = "okay";
sensor0 {
subdev_name = "vivcam";
@@ -210,8 +210,8 @@
path_type = "ISP_MI_PATH_MP";
};
};
pipline1 {
pipline_id = <1>;
channel1 {
channel_id = <1>;
status = "okay";
sensor0 {
subdev_name = "vivcam";
@@ -236,8 +236,8 @@
path_type = "ISP_MI_PATH_SP";
};
};
pipline2 {
pipline_id = <2>;
channel2 {
channel_id = <2>;
status = "okay";
sensor0 {
subdev_name = "vivcam";
@@ -267,8 +267,8 @@
&video3 {
status = "okay";
pipline0 {
pipline_id = <0>;
channel0 {
channel_id = <0>;
status = "okay";
sensor0 {
subdev_name = "vivcam";
@@ -298,8 +298,8 @@
path_type = "DW_DWE_VSE0";
};
};
pipline1 {
pipline_id = <1>;
channel1 {
channel_id = <1>;
status = "okay";
sensor0 {
subdev_name = "vivcam";
@@ -330,8 +330,8 @@
path_type = "DW_DWE_VSE1";
};
};
pipline2 {
pipline_id = <2>;
channel2 {
channel_id = <2>;
status = "okay";
sensor0 {
subdev_name = "vivcam";
@@ -365,8 +365,8 @@
&video4 {
status = "okay";
pipline0 {
pipline_id = <0>;
channel0 {
channel_id = <0>;
status = "okay";
sensor0 {
subdev_name = "vivcam";
@@ -402,8 +402,8 @@
path_type = "ISP_RY_MI_PATH_MP";
};
};
pipline1 {
pipline_id = <1>;
channel1 {
channel_id = <1>;
status = "okay";
sensor0 {
subdev_name = "vivcam";
@@ -438,8 +438,8 @@
path_type = "ISP_RY_MI_PATH_SP";
};
};
pipline2 {
pipline_id = <2>;
channel2 {
channel_id = <2>;
status = "okay";
sensor0 {
subdev_name = "vivcam";
@@ -478,8 +478,8 @@
&video5 {
status = "okay";
pipline0 {
pipline_id = <0>;
channel0 {
channel_id = <0>;
status = "okay";
sensor0 {
subdev_name = "vivcam";
@@ -520,8 +520,8 @@
path_type = "DW_DWE_VSE0";
};
};
pipline1 {
pipline_id = <1>;
channel1 {
channel_id = <1>;
status = "okay";
sensor0 {
subdev_name = "vivcam";
@@ -561,8 +561,8 @@
path_type = "DW_DWE_VSE1";
};
};
pipline2 {
pipline_id = <2>;
channel2 {
channel_id = <2>;
status = "okay";
sensor0 {
subdev_name = "vivcam";
@@ -607,8 +607,8 @@
&video6 {
status = "okay";
pipline0 {
pipline_id = <0>;
channel0 {
channel_id = <0>;
status = "okay";
sensor0 {
subdev_name = "vivcam";
@@ -625,7 +625,7 @@
dma {
subdev_name = "vipre";
idx = <0>;
path_type = "VIPRE_CSI2_DDR";
path_type = "VIPRE_CSI2_DSP";
};
dsp {
subdev_name = "dsp";
@@ -633,8 +633,8 @@
path_type = "DSP_PATH_VIPRE_ODD";
};
};
pipline1 {
pipline_id = <1>;
channel1 {
channel_id = <1>;
status = "okay";
sensor0 {
subdev_name = "vivcam";
@@ -651,7 +651,7 @@
dma {
subdev_name = "vipre";
idx = <0>;
path_type = "VIPRE_CSI2_DDR";
path_type = "VIPRE_CSI2_DSP";
};
dsp {
subdev_name = "dsp";
@@ -664,8 +664,8 @@
&video7{
status = "okay";
pipline0 {
pipline_id = <0>;
channel0 {
channel_id = <0>;
status = "okay";
sensor0 {
subdev_name = "vivcam";
@@ -706,8 +706,8 @@
};
};
pipline1 {
pipline_id = <1>;
channel1 {
channel_id = <1>;
status = "okay";
sensor0 {
subdev_name = "vivcam";
@@ -747,8 +747,8 @@
path_type = "DW_DWE_VSE1";
};
};
pipline2 {
pipline_id = <2>;
channel2 {
channel_id = <2>;
status = "okay";
sensor0 {
subdev_name = "vivcam";
@@ -793,8 +793,8 @@
&video8{
status = "okay";
pipline0 {
pipline_id = <0>;
channel0 {
channel_id = <0>;
status = "okay";
sensor0 {
subdev_name = "vivcam";
@@ -811,7 +811,7 @@
dma {
subdev_name = "vipre";
idx = <0>;
path_type = "VIPRE_CSI1_DDR";
path_type = "VIPRE_CSI1_DSP";
};
dsp {
subdev_name = "dsp";
@@ -824,8 +824,8 @@
&video9 { //IR debug
status = "okay";
pipline0 {
pipline_id = <0>;
channel0 {
channel_id = <0>;
status = "okay";
sensor0 {
subdev_name = "vivcam";
@@ -844,7 +844,7 @@
dma {
subdev_name = "vipre";
idx = <0>;
path_type = "VIPRE_CSI2_DDR";
path_type = "VIPRE_CSI2_DSP";
};
dsp {
subdev_name = "dsp";
@@ -857,7 +857,7 @@
&video10{ // TUNING TOOL
status = "okay";
pipline0 { // CSI2X2_B
channel0 { // CSI2X2_B
status = "okay";
sensor0 {
subdev_name = "vivcam";
@@ -884,8 +884,8 @@
&video11{
status = "okay";
pipline0 {
pipline_id = <0>;
channel0 {
channel_id = <0>;
status = "okay";
sensor0 {
subdev_name = "vivcam";
@@ -915,7 +915,7 @@
&video12{ // TUNING TOOL
status = "okay";
pipline0 { // CSI2
channel0 { // CSI2
status = "okay";
sensor0 {
subdev_name = "vivcam";

218
arch/riscv/boot/dts/thead/light.dtsi
View File

@@ -14,6 +14,7 @@
#include <dt-bindings/firmware/thead/rsrc.h>
#include <dt-bindings/soc/thead,light-iopmp.h>
#include <dt-bindings/thermal/thermal.h>
#include <dt-bindings/reset/light-reset.h>
/ {
compatible = "thead,light";
@@ -33,6 +34,7 @@
i2c3 = &i2c3;
i2c4 = &i2c4;
audio_i2c0 = &audio_i2c0;
audio_i2c1 = &audio_i2c1;
mmc0 = &emmc;
mmc1 = &sdhci0;
serial0 = &uart0;
@@ -74,7 +76,7 @@
memory@0 {
device_type = "memory";
reg = <0x0 0x00000000 0x1 0x00000000>;
reg = <0x0 0x200000 0x0 0xffe00000>;
};
resmem: reserved-memory {
@@ -86,8 +88,8 @@
cmamem: linux,cma {
compatible = "shared-dma-pool";
reusable;
size = <0 0x14000000>;
alloc-ranges = <0 0x20000000 0 0x40000000>;
size = <0 0x14000000>; // 320MB by default
alloc-ranges = <0 0x64000000 0 0x14000000>; // [0x6400_0000 ~ 0x7800_0000]
linux,cma-default;
};
};
@@ -975,9 +977,9 @@
status = "disabled";
};
adc: adc@ffec020000 {
adc: adc@0xfffff51000 {
compatible = "thead,light-adc";
reg = <0xff 0xfff51000 0x0 0x2000>;
reg = <0xff 0xfff51000 0x0 0x1000>;
interrupt-parent = <&intc>;
interrupts = <61>;
clocks = <&dummy_clock_aonsys_clk>;
@@ -1171,8 +1173,9 @@
reg = <0xff 0xefc30000 0x0 0x1000>;
interrupt-parent = <&intc>;
interrupts = <24>;
clocks = <&dummy_clock_apb>;
clock-names = "baudclk";
clocks = <&clk CLKGEN_WDT0_PCLK>;
clock-names = "tclk";
resets = <&rst LIGHT_RESET_WDT0>;
status = "okay";
};
@@ -1181,8 +1184,9 @@
reg = <0xff 0xefc31000 0x0 0x1000>;
interrupt-parent = <&intc>;
interrupts = <25>;
clocks = <&dummy_clock_apb>;
clock-names = "baudclk";
clocks = <&clk CLKGEN_WDT1_PCLK>;
clock-names = "tclk";
resets = <&rst LIGHT_RESET_WDT1>;
status = "okay";
};
@@ -1237,6 +1241,13 @@
status = "okay";
};
rst: reset-controller@ffef014000 {
compatible = "thead,light-reset-src","syscon";
reg = <0xff 0xef014000 0x0 0x1000>;
#reset-cells = <1>;
status = "okay";
};
sys_reg: sys_reg@ffef010100 {
compatible = "thead,light_sys_reg";
reg = <0xff 0xef010100 0x0 0x100>;
@@ -1386,6 +1397,7 @@
interrupt-parent = <&intc>;
interrupts = <113>;
interrupt-names = "npuirq";
power-domains = <&pd LIGHT_AON_NPU_PD>;
clocks = <&clk CLKGEN_TOP_APB_SX_PCLK>,
<&clk CLKGEN_TOP_AXI4S_ACLK>;
clock-names = "pclk", "aclk";
@@ -1401,6 +1413,8 @@
interrupt-parent = <&intc>;
interrupts = <102>;
interrupt-names = "gpuirq";
vosys-regmap = <&vosys_reg>;
power-domains = <&pd LIGHT_AON_GPU_PD>;
clocks = <&vosys_clk_gate LIGHT_CLKGEN_GPU_CORE_CLK>,
<&vosys_clk_gate LIGHT_CLKGEN_GPU_CFG_ACLK>;
clock-names = "cclk", "aclk";
@@ -1427,6 +1441,7 @@
reg = <0xff 0xecc00000 0x0 0x8000>;
interrupt-parent = <&intc>;
interrupts = <131>;
power-domains = <&pd LIGHT_AON_VDEC_PD>;
clocks = <&vpsys_clk_gate LIGHT_VPSYS_VDEC_ACLK>,
<&vpsys_clk_gate LIGHT_VPSYS_VDEC_CCLK>,
<&vpsys_clk_gate LIGHT_VPSYS_VDEC_PCLK>;
@@ -1439,6 +1454,7 @@
reg = <0xff 0xecc10000 0x0 0x8000>;
interrupt-parent = <&intc>;
interrupts = <133>;
power-domains = <&pd LIGHT_AON_VENC_PD>;
clocks = <&vpsys_clk_gate LIGHT_VPSYS_VENC_ACLK>,
<&vpsys_clk_gate LIGHT_VPSYS_VENC_CCLK>,
<&vpsys_clk_gate LIGHT_VPSYS_VENC_PCLK>;
@@ -1519,6 +1535,26 @@
status = "disabled";
};
i2s2: audio_i2s2@0xffcb016000 {
#sound-dai-cells = <1>;
compatible = "light,light-i2s";
reg = <0xff 0xcb016000 0x0 0x1000>;
audio-pin-regmap = <&audio_ioctrl>;
audio-cpr-regmap = <&audio_cpr>;
pinctrl-names = "default";
light,mode = "i2s-master";
light,sel = "i2s2";
interrupt-parent = <&intc>;
interrupts = <176>;
dmas = <&dmac2 13>, <&dmac2 12>;
dma-names = "tx", "rx";
light,dma_maxburst = <4>;
#dma-cells = <1>;
clocks = <&dummy_clock_apb>;
clock-names = "pclk";
status = "disabled";
};
i2s3: audio_i2s3@0xffcb017000 {
#sound-dai-cells = <1>;
compatible = "light,light-i2s";
@@ -1562,8 +1598,8 @@
fs_lcnt = /bits/ 16 <0x42>;
fp_hcnt = /bits/ 16 <0x14>;
fp_lcnt = /bits/ 16 <0x1a>;
hs_hcnt = /bits/ 16 <0x5>;
hs_lcnt = /bits/ 16 <0x15>;
hs_hcnt = /bits/ 16 <0x9>;
hs_lcnt = /bits/ 16 <0x11>;
#address-cells = <1>;
#size-cells = <0>;
};
@@ -1581,8 +1617,8 @@
fs_lcnt = /bits/ 16 <0x42>;
fp_hcnt = /bits/ 16 <0x14>;
fp_lcnt = /bits/ 16 <0x1a>;
hs_hcnt = /bits/ 16 <0x5>;
hs_lcnt = /bits/ 16 <0x15>;
hs_hcnt = /bits/ 16 <0x9>;
hs_lcnt = /bits/ 16 <0x11>;
#address-cells = <1>;
#size-cells = <0>;
};
@@ -1600,8 +1636,8 @@
fs_lcnt = /bits/ 16 <0x42>;
fp_hcnt = /bits/ 16 <0x14>;
fp_lcnt = /bits/ 16 <0x1a>;
hs_hcnt = /bits/ 16 <0x5>;
hs_lcnt = /bits/ 16 <0x15>;
hs_hcnt = /bits/ 16 <0x9>;
hs_lcnt = /bits/ 16 <0x11>;
status = "disabled";
#address-cells = <1>;
@@ -1621,8 +1657,8 @@
fs_lcnt = /bits/ 16 <0x42>;
fp_hcnt = /bits/ 16 <0x14>;
fp_lcnt = /bits/ 16 <0x1a>;
hs_hcnt = /bits/ 16 <0x5>;
hs_lcnt = /bits/ 16 <0x15>;
hs_hcnt = /bits/ 16 <0x9>;
hs_lcnt = /bits/ 16 <0x11>;
status = "disabled";
#address-cells = <1>;
@@ -1642,8 +1678,8 @@
fs_lcnt = /bits/ 16 <0x42>;
fp_hcnt = /bits/ 16 <0x14>;
fp_lcnt = /bits/ 16 <0x1a>;
hs_hcnt = /bits/ 16 <0x5>;
hs_lcnt = /bits/ 16 <0x15>;
hs_hcnt = /bits/ 16 <0x9>;
hs_lcnt = /bits/ 16 <0x11>;
status = "disabled";
#address-cells = <1>;
@@ -1669,15 +1705,36 @@
#size-cells = <0>;
};
audio_i2c1: i2c@0xffcb01b000 {
compatible = "snps,designware-i2c";
reg = <0xff 0xcb01b000 0x0 0x1000>;
interrupt-parent = <&intc>;
interrupts = <183>;
clocks = <&dummy_clock_apb>;
clock-frequency = <100000>;
ss_hcnt = /bits/ 16 <0x82>;
ss_lcnt = /bits/ 16 <0x78>;
fs_hcnt = /bits/ 16 <0x37>;
fs_lcnt = /bits/ 16 <0x42>;
fp_hcnt = /bits/ 16 <0x14>;
fp_lcnt = /bits/ 16 <0x1a>;
hs_hcnt = /bits/ 16 <0x5>;
hs_lcnt = /bits/ 16 <0x15>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
isp0: isp@ffe4100000 {
compatible = "thead,light-isp";
reg = <0xff 0xe4100000 0x0 0x10000>;
interrupt-parent = <&intc>;
interrupts = <117>,<118>;
clocks = <&dummy_clock_visys>,
<&dummy_clock_visys>,
<&dummy_clock_visys>,
<&dummy_clock_visys>;
clocks = <&visys_clk_gate LIGHT_CLKGEN_ISP0_ACLK>,
<&visys_clk_gate LIGHT_CLKGEN_ISP0_HCLK>,
<&visys_clk_gate LIGHT_CLKGEN_ISP0_PIXELCLK>,
<&visys_clk_gate LIGHT_CLKGEN_ISP0_CLK>;
clock-names = "aclk", "hclk", "isp0_pclk", "cclk";
status = "disabled";
};
@@ -1687,11 +1744,11 @@
reg = <0xff 0xe4110000 0x0 0x10000>;
interrupt-parent = <&intc>;
interrupts = <120>,<121>;
clocks = <&dummy_clock_visys>,
<&dummy_clock_visys>,
<&dummy_clock_visys>,
<&dummy_clock_visys>,
<&dummy_clock_visys>;
clocks = <&visys_clk_gate LIGHT_CLKGEN_ISP0_ACLK>,
<&visys_clk_gate LIGHT_CLKGEN_ISP0_HCLK>,
<&visys_clk_gate LIGHT_CLKGEN_ISP0_PIXELCLK>,
<&visys_clk_gate LIGHT_CLKGEN_ISP1_CLK>,
<&visys_clk_gate LIGHT_CLKGEN_ISP1_PIXELCLK>;
clock-names = "aclk", "hclk", "isp0_pclk", "cclk", "isp1_pclk";
status = "disabled";
};
@@ -1701,9 +1758,9 @@
reg = <0xff 0xe4120000 0x0 0x10000>;
interrupt-parent = <&intc>;
interrupts = <123>,<124>;
clocks = <&dummy_clock_visys>,
<&dummy_clock_visys>,
<&dummy_clock_visys>;
clocks = <&visys_clk_gate LIGHT_CLKGEN_ISP_RY_ACLK>,
<&visys_clk_gate LIGHT_CLKGEN_ISP_RY_HCLK>,
<&visys_clk_gate LIGHT_CLKGEN_ISP_RY_CCLK>;
clock-names = "aclk", "hclk", "cclk";
status = "disabled";
};
@@ -1713,10 +1770,10 @@
reg = <0xff 0xe4130000 0x0 0x10000>;
interrupt-parent = <&intc>;
interrupts = <98>,<99>;
clocks = <&dummy_clock_visys>,
<&dummy_clock_visys>,
<&dummy_clock_visys>,
<&dummy_clock_visys>;
clocks = <&visys_clk_gate LIGHT_CLKGEN_DW200_ACLK>,
<&visys_clk_gate LIGHT_CLKGEN_DW200_HCLK>,
<&visys_clk_gate LIGHT_CLKGEN_DW200_CLK_VSE>,
<&visys_clk_gate LIGHT_CLKGEN_DW200_CLK_DWE>;
clock-names = "aclk", "hclk", "vseclk", "dweclk";
status = "disabled";
};
@@ -1746,51 +1803,58 @@
};
bm_csi0: csi@ffe4000000{ //CSI2
compatible = "thead,light-bm-csi";
reg = < 0xff 0xe4000000 0x0 0x10000>;
interrupt-parent = <&intc>;
interrupts = <128>;
dphyglueiftester = <0x180>;
sysreg_mipi_csi_ctrl = <0x140>;
clocks = <&dummy_clock_visys>,
<&dummy_clock_visys>,
<&dummy_clock_visys>;
clock-names = "pclk", "pixclk", "cfg_clk";
compatible = "thead,light-bm-csi";
reg = < 0xff 0xe4000000 0x0 0x10000>;
interrupt-parent = <&intc>;
interrupts = <128>;
dphyglueiftester = <0x180>;
sysreg_mipi_csi_ctrl = <0x140>;
clocks = <&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI0_PCLK>,
<&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI0_PIXCLK>,
<&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI0_CFG_CLK>;
clock-names = "pclk", "pixclk", "cfg_clk";
phy_name = "CSI_4LANE";
status = "disabled";
};
status = "disabled";
csia_reg: visys-reg@ffe4020000 {
compatible = "thead,light-visys-reg", "syscon";
reg = < 0xff 0xe4020000 0x0 0x10000>;
status = "okay";
};
bm_csi1: csi@ffe4010000{ //CSI2X2_B
compatible = "thead,light-bm-csi";
reg = < 0xff 0xe4010000 0x0 0x10000>;
interrupt-parent = <&intc>;
interrupts = <126>; // 110 + 16 int_mipi_csi2x2_int0
dphyglueiftester = <0x182>; // for FPGA PHY only. ASIC not needed.
sysreg_mipi_csi_ctrl = <0x148>;
clocks = <&dummy_clock_visys>,
<&dummy_clock_visys>,
<&dummy_clock_visys>;
clock-names = "pclk", "pixclk", "cfg_clk";
status = "disabled";
compatible = "thead,light-bm-csi";
reg = < 0xff 0xe4010000 0x0 0x10000>;
interrupt-parent = <&intc>;
interrupts = <126>; // 110 + 16 int_mipi_csi2x2_int0
dphyglueiftester = <0x182>; // for FPGA PHY only. ASIC not needed.
sysreg_mipi_csi_ctrl = <0x148>;
visys-regmap = <&visys_reg>;
csia-regmap = <&csia_reg>;
clocks = <&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI1_PCLK>,
<&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI1_PIXCLK>,
<&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI1_CFG_CLK>;
clock-names = "pclk", "pixclk", "cfg_clk";
phy_name = "CSI_B";
status = "disabled";
};
bm_csi2: csi@ffe4020000{ //CSI2X2_A
compatible = "thead,light-bm-csi";
reg = < 0xff 0xe4020000 0x0 0x10000>;
interrupt-parent = <&intc>;
interrupts = <127>;
dphyglueiftester = <0x184>;
sysreg_mipi_csi_ctrl = <0x144>;
clocks = <&dummy_clock_visys>,
<&dummy_clock_visys>,
<&dummy_clock_visys>;
clock-names = "pclk", "pixclk", "cfg_clk";
status = "disabled";
compatible = "thead,light-bm-csi";
reg = < 0xff 0xe4020000 0x0 0x10000>;
interrupt-parent = <&intc>;
interrupts = <127>;
dphyglueiftester = <0x184>;
sysreg_mipi_csi_ctrl = <0x144>;
clocks = <&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI2_PCLK>,
<&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI2_PIXCLK>,
<&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI2_CFG_CLK>;
clock-names = "pclk", "pixclk", "cfg_clk";
phy_name = "CSI_A";
status = "disabled";
};
bm_isp0: bm_isp@ffe4100000 {
compatible = "thead,light-bm-isp";
reg = <0xff 0xe4100000 0x0 0x10000>;
@@ -1815,6 +1879,10 @@
reg = <0xff 0xe4030000 0x0 0x1000>;
interrupt-parent = <&intc>;
interrupts = <134>;
clocks = <&visys_clk_gate LIGHT_CLKGEN_VIPRE_ACLK>,
<&visys_clk_gate LIGHT_CLKGEN_VIPRE_PCLK>,
<&visys_clk_gate LIGHT_CLKGEN_VIPRE_PIXELCLK>;
clock-names ="aclk", "pclk", "pixclk";
status = "disabled";
};
@@ -1960,8 +2028,8 @@
interrupt-parent = <&intc>;
interrupts = <156>;
firmware-name = "xrp0.elf";
clocks = <&dummy_clock_visys>,
<&dummy_clock_visys>;
clocks = <&dummy_clock_visys>,
<&dummy_clock_visys>;
clock-names = "pclk", "cclk";
status = "disabled";
@@ -1998,8 +2066,8 @@
interrupt-parent = <&intc>;
interrupts = <157>;
firmware-name = "xrp1.elf";
clocks = <&dummy_clock_visys>,
<&dummy_clock_visys>;
clocks = <&dummy_clock_visys>,
<&dummy_clock_visys>;
clock-names = "pclk", "cclk";
status = "disabled";

1
arch/riscv/configs/defconfig
View File

@@ -183,6 +183,5 @@ CONFIG_DEBUG_INFO=y
CONFIG_MAGIC_SYSRQ=y
CONFIG_DEBUG_FS=y
CONFIG_DETECT_HUNG_TASK=y
CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=60
CONFIG_DEBUG_ATOMIC_SLEEP=y
# CONFIG_RCU_TRACE is not set

310
arch/riscv/configs/fire_defconfig Normal file
View File

@@ -0,0 +1,310 @@
CONFIG_SYSVIPC=y
CONFIG_POSIX_MQUEUE=y
CONFIG_NO_HZ_IDLE=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_PREEMPT=y
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_CGROUPS=y
CONFIG_NAMESPACES=y
CONFIG_USER_NS=y
CONFIG_CHECKPOINT_RESTORE=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_EXPERT=y
# CONFIG_BUG is not set
CONFIG_BPF_SYSCALL=y
CONFIG_PERF_EVENTS=y
CONFIG_FORCE_MAX_ZONEORDER=15
CONFIG_SOC_SIFIVE=y
CONFIG_SOC_THEAD=y
CONFIG_SMP=y
CONFIG_VECTOR=y
CONFIG_VECTOR_0_7=y
CONFIG_KEXEC=y
CONFIG_CRASH_DUMP=y
CONFIG_VIRTUALIZATION=y
CONFIG_KVM=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
CONFIG_CMA=y
CONFIG_CMA_DEBUGFS=y
CONFIG_CMA_AREAS=16
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_INET=y
CONFIG_IP_MULTICAST=y
CONFIG_IP_ADVANCED_ROUTER=y
CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y
CONFIG_IP_PNP_BOOTP=y
CONFIG_IP_PNP_RARP=y
CONFIG_BRIDGE=y
CONFIG_VSOCKETS=y
# CONFIG_VSOCKETS_LOOPBACK is not set
CONFIG_VIRTIO_VSOCKETS=y
CONFIG_NETLINK_DIAG=y
CONFIG_BT=y
CONFIG_BT_RFCOMM=y
CONFIG_BT_RFCOMM_TTY=y
CONFIG_BT_BNEP=y
CONFIG_BT_HIDP=y
CONFIG_BT_HCIUART=y
CONFIG_BT_HCIUART_H4=y
CONFIG_BT_HCIUART_RTL3WIRE=y
CONFIG_CFG80211=y
CONFIG_RFKILL=y
CONFIG_NET_9P=y
CONFIG_NET_9P_VIRTIO=y
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
CONFIG_MTD=y
CONFIG_MTD_TESTS=m
CONFIG_MTD_BLOCK=y
CONFIG_MTD_SLRAM=m
CONFIG_MTD_PHRAM=m
CONFIG_MTD_SPI_NAND=y
CONFIG_MTD_SPI_NOR=y
CONFIG_MTD_UBI=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_VIRTIO_BLK=y
CONFIG_LIGHT_DSMART_CARD=y
CONFIG_EEPROM_AT24=y
CONFIG_SCSI=y
CONFIG_BLK_DEV_SD=y
CONFIG_NETDEVICES=y
CONFIG_TUN=y
CONFIG_VIRTIO_NET=y
CONFIG_MACB=y
CONFIG_STMMAC_ETH=y
CONFIG_DWMAC_LIGHT=y
CONFIG_MICROSEMI_PHY=y
CONFIG_REALTEK_PHY=y
CONFIG_MARVELL_PHY=y
CONFIG_USB_USBNET=m
# CONFIG_USB_NET_AX8817X is not set
# CONFIG_USB_NET_AX88179_178A is not set
# CONFIG_USB_NET_NET1080 is not set
CONFIG_RTL8723DS=y
CONFIG_INPUT_MOUSEDEV=y
CONFIG_INPUT_EVDEV=y
CONFIG_KEYBOARD_GPIO=y
# CONFIG_INPUT_MOUSE is not set
CONFIG_INPUT_TOUCHSCREEN=y
CONFIG_TOUCHSCREEN_GOODIX=y
CONFIG_INPUT_MISC=y
CONFIG_INPUT_UINPUT=y
CONFIG_SERIAL_8250=y
# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_8250_NR_UARTS=6
CONFIG_SERIAL_8250_RUNTIME_UARTS=6
CONFIG_SERIAL_8250_DW=y
CONFIG_SERIAL_OF_PLATFORM=y
CONFIG_SERIAL_EARLYCON_RISCV_SBI=y
CONFIG_VIRTIO_CONSOLE=y
CONFIG_HW_RANDOM=y
CONFIG_HW_RANDOM_VIRTIO=y
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_DESIGNWARE_PLATFORM=y
CONFIG_SPI=y
CONFIG_SPI_DW_QUAD=y
CONFIG_SPI_DESIGNWARE=y
CONFIG_SPI_DW_MMIO=y
CONFIG_SPI_SPIDEV=y
# CONFIG_PTP_1588_CLOCK is not set
CONFIG_PINCTRL=y
CONFIG_GPIOLIB=y
CONFIG_GPIO_SYSFS=y
CONFIG_GPIO_DWAPB=y
CONFIG_GPIO_PCA953X=y
CONFIG_GPIO_PCA953X_IRQ=y
CONFIG_POWER_SUPPLY=y
CONFIG_SENSORS_MR75203=y
CONFIG_THERMAL=y
CONFIG_CPU_THERMAL=y
CONFIG_THERMAL_EMULATION=y
CONFIG_WATCHDOG=y
CONFIG_DW_WATCHDOG=y
CONFIG_LIGHT_PMIC_WATCHDOG=y
CONFIG_WATCHDOG_PRETIMEOUT_GOV=y
CONFIG_WATCHDOG_PRETIMEOUT_GOV_SEL=m
CONFIG_WATCHDOG_PRETIMEOUT_GOV_PANIC=y
#CONFIG_WATCHDOG_PRETIMEOUT_DEFAULT_GOV_PANIC=y
CONFIG_WATCHDOG_PRETIMEOUT_DEFAULT_GOV_NOOP=y
CONFIG_WATCHDOG_OPEN_TIMEOUT=32
CONFIG_ABX500_CORE=y
CONFIG_REGULATOR=y
CONFIG_REGULATOR_FIXED_VOLTAGE=y
CONFIG_MEDIA_SUPPORT=y
# CONFIG_MEDIA_ANALOG_TV_SUPPORT is not set
# CONFIG_MEDIA_DIGITAL_TV_SUPPORT is not set
CONFIG_MEDIA_USB_SUPPORT=y
CONFIG_USB_VIDEO_CLASS=m
CONFIG_V4L_PLATFORM_DRIVERS=y
CONFIG_VIDEO_ASPEED=y
CONFIG_V4L_MEM2MEM_DRIVERS=y
# CONFIG_MEDIA_TUNER_SIMPLE is not set
# CONFIG_MEDIA_TUNER_TDA18250 is not set
# CONFIG_MEDIA_TUNER_TDA8290 is not set
# CONFIG_MEDIA_TUNER_TDA827X is not set
# CONFIG_MEDIA_TUNER_TDA18271 is not set
# CONFIG_MEDIA_TUNER_TDA9887 is not set
# CONFIG_MEDIA_TUNER_TEA5761 is not set
# CONFIG_MEDIA_TUNER_TEA5767 is not set
# CONFIG_MEDIA_TUNER_MSI001 is not set
# CONFIG_MEDIA_TUNER_MT20XX is not set
# CONFIG_MEDIA_TUNER_MT2060 is not set
# CONFIG_MEDIA_TUNER_MT2063 is not set
# CONFIG_MEDIA_TUNER_MT2266 is not set
# CONFIG_MEDIA_TUNER_MT2131 is not set
# CONFIG_MEDIA_TUNER_QT1010 is not set
# CONFIG_MEDIA_TUNER_XC2028 is not set
# CONFIG_MEDIA_TUNER_XC5000 is not set
# CONFIG_MEDIA_TUNER_XC4000 is not set
# CONFIG_MEDIA_TUNER_MXL5005S is not set
# CONFIG_MEDIA_TUNER_MXL5007T is not set
# CONFIG_MEDIA_TUNER_MC44S803 is not set
# CONFIG_MEDIA_TUNER_MAX2165 is not set
# CONFIG_MEDIA_TUNER_TDA18218 is not set
# CONFIG_MEDIA_TUNER_FC0011 is not set
# CONFIG_MEDIA_TUNER_FC0012 is not set
# CONFIG_MEDIA_TUNER_FC0013 is not set
# CONFIG_MEDIA_TUNER_TDA18212 is not set
# CONFIG_MEDIA_TUNER_E4000 is not set
# CONFIG_MEDIA_TUNER_FC2580 is not set
# CONFIG_MEDIA_TUNER_M88RS6000T is not set
# CONFIG_MEDIA_TUNER_TUA9001 is not set
# CONFIG_MEDIA_TUNER_SI2157 is not set
# CONFIG_MEDIA_TUNER_IT913X is not set
# CONFIG_MEDIA_TUNER_R820T is not set
# CONFIG_MEDIA_TUNER_MXL301RF is not set
# CONFIG_MEDIA_TUNER_QM1D1C0042 is not set
# CONFIG_MEDIA_TUNER_QM1D1B0004 is not set
CONFIG_DRM=y
CONFIG_DRM_PANEL_SIMPLE=y
CONFIG_DRM_PANEL_ILITEK_ILI9881C=y
CONFIG_DRM_PANEL_ILI9881D=y
CONFIG_DRM_VERISILICON=y
CONFIG_BACKLIGHT_CLASS_DEVICE=y
CONFIG_BACKLIGHT_PWM=y
CONFIG_FRAMEBUFFER_CONSOLE=y
CONFIG_LOGO=y
CONFIG_SOUND=y
CONFIG_SND=y
CONFIG_SND_USB_AUDIO=m
CONFIG_SND_SOC=y
CONFIG_SND_SOC_THEAD_LIGHT=y
CONFIG_SND_SOC_AW87519=y
CONFIG_SND_SOC_BT_SCO=y
CONFIG_SND_SOC_ES7210=y
CONFIG_SND_SOC_ES8156=y
CONFIG_SND_SOC_WM8960=y
CONFIG_SND_SIMPLE_CARD=y
CONFIG_SND_AUDIO_GRAPH_CARD=y
CONFIG_UHID=y
CONFIG_HID_PID=y
CONFIG_USB_HIDDEV=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_PLATFORM=y
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_USB_STORAGE_SDDR09=y
CONFIG_USB_STORAGE_SDDR55=y
CONFIG_USB_DWC3=m
# CONFIG_USB_DWC3_OF_SIMPLE is not set
CONFIG_USB_GADGET=y
CONFIG_USB_CONFIGFS=y
CONFIG_USB_CONFIGFS_F_FS=y
CONFIG_USB_CONFIGFS_F_ACC=y
CONFIG_USB_ZERO=m
CONFIG_USB_ETH=m
CONFIG_USB_ETH_EEM=y
CONFIG_USB_G_NCM=m
CONFIG_USB_MASS_STORAGE=m
CONFIG_USB_G_SERIAL=m
CONFIG_USB_G_MULTI=m
CONFIG_USB_G_MULTI_CDC=y
CONFIG_USB_ROLE_SWITCH=m
CONFIG_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_PLTFM=y
CONFIG_MMC_SDHCI_OF_DWCMSHC=y
CONFIG_NEW_LEDS=y
CONFIG_LEDS_CLASS=y
CONFIG_LEDS_GPIO=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_DRV_XGENE=y
CONFIG_DMADEVICES=y
CONFIG_DW_AXI_DMAC=y
CONFIG_DMATEST=y
CONFIG_SW_SYNC=y
CONFIG_UDMABUF=y
CONFIG_DMABUF_SELFTESTS=m
CONFIG_VIRTIO_MMIO=y
CONFIG_VIRTIO_KHV_MMIO=y
CONFIG_VHOST_NET=y
CONFIG_VHOST_VSOCK=y
CONFIG_CLK_LIGHT_FM=y
CONFIG_HWSPINLOCK=y
CONFIG_HWSPINLOCK_LIGHT=y
CONFIG_HWSPINLOCK_LIGHT_TEST=m
CONFIG_MAILBOX=y
CONFIG_IIO=y
CONFIG_IIO_SW_DEVICE=y
CONFIG_PWM=y
CONFIG_PWM_LIGHT=y
CONFIG_NVMEM_THEAD_LIGHT_EFUSE=y
CONFIG_TEE=y
CONFIG_OPTEE=y
CONFIG_OPTEE_BENCHMARK=y
CONFIG_LIGHT_GPU_VIV=m
# CONFIG_LIGHT_NET is not set
CONFIG_EXT4_FS=y
CONFIG_EXT4_FS_POSIX_ACL=y
CONFIG_AUTOFS4_FS=y
CONFIG_FUSE_FS=y
CONFIG_MSDOS_FS=y
CONFIG_VFAT_FS=y
CONFIG_TMPFS=y
CONFIG_TMPFS_POSIX_ACL=y
CONFIG_HUGETLBFS=y
CONFIG_JFFS2_FS=y
CONFIG_UBIFS_FS=y
CONFIG_NFS_FS=y
CONFIG_NFS_V4=y
CONFIG_NFS_V4_1=y
CONFIG_NFS_V4_2=y
CONFIG_ROOT_NFS=y
CONFIG_9P_FS=y
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_ISO8859_1=y
CONFIG_CRYPTO_AUTHENC=y
CONFIG_CRYPTO_DH=y
CONFIG_CRYPTO_CURVE25519=y
CONFIG_CRYPTO_CHACHA20POLY1305=y
CONFIG_CRYPTO_OFB=y
CONFIG_CRYPTO_MD5=y
CONFIG_CRYPTO_SHA512=y
CONFIG_CRYPTO_SHA3=y
CONFIG_CRYPTO_SM3=y
CONFIG_CRYPTO_DES=y
CONFIG_CRYPTO_USER_API_HASH=y
CONFIG_DMA_CMA=y
CONFIG_DMA_PERNUMA_CMA=y
CONFIG_CMA_SIZE_MBYTES=32
CONFIG_PRINTK_TIME=y
CONFIG_DYNAMIC_DEBUG=y
CONFIG_DEBUG_INFO=y
CONFIG_MAGIC_SYSRQ=y
CONFIG_DEBUG_FS=y
CONFIG_DETECT_HUNG_TASK=y
CONFIG_DEBUG_ATOMIC_SLEEP=y
# CONFIG_RCU_TRACE is not set
CONFIG_OVERLAY_FS=y
CONFIG_LOCKUP_DETECTOR=y
CONFIG_SOFTLOCKUP_DETECTOR=y
CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
# CONFIG_SUSPEND is not set
# CONFIG_PM_SLEEP is not set

311
arch/riscv/configs/fire_emu_defconfig Normal file
View File

@@ -0,0 +1,311 @@
CONFIG_SYSVIPC=y
CONFIG_POSIX_MQUEUE=y
CONFIG_NO_HZ_IDLE=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_PREEMPT=y
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_CGROUPS=y
CONFIG_NAMESPACES=y
CONFIG_USER_NS=y
CONFIG_CHECKPOINT_RESTORE=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_EXPERT=y
# CONFIG_BUG is not set
CONFIG_BPF_SYSCALL=y
CONFIG_PERF_EVENTS=y
CONFIG_FORCE_MAX_ZONEORDER=15
CONFIG_SOC_SIFIVE=y
CONFIG_SOC_THEAD=y
CONFIG_SOC_THEAD_LIGHT_EMU=y
CONFIG_SMP=y
CONFIG_VECTOR=y
CONFIG_VECTOR_0_7=y
CONFIG_KEXEC=y
CONFIG_CRASH_DUMP=y
CONFIG_VIRTUALIZATION=y
CONFIG_KVM=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
CONFIG_CMA=y
CONFIG_CMA_DEBUGFS=y
CONFIG_CMA_AREAS=16
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_INET=y
CONFIG_IP_MULTICAST=y
CONFIG_IP_ADVANCED_ROUTER=y
CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y
CONFIG_IP_PNP_BOOTP=y
CONFIG_IP_PNP_RARP=y
CONFIG_BRIDGE=y
CONFIG_VSOCKETS=y
# CONFIG_VSOCKETS_LOOPBACK is not set
CONFIG_VIRTIO_VSOCKETS=y
CONFIG_NETLINK_DIAG=y
CONFIG_BT=y
CONFIG_BT_RFCOMM=y
CONFIG_BT_RFCOMM_TTY=y
CONFIG_BT_BNEP=y
CONFIG_BT_HIDP=y
CONFIG_BT_HCIUART=y
CONFIG_BT_HCIUART_H4=y
CONFIG_BT_HCIUART_RTL3WIRE=y
CONFIG_CFG80211=y
CONFIG_RFKILL=y
CONFIG_NET_9P=y
CONFIG_NET_9P_VIRTIO=y
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
CONFIG_MTD=y
CONFIG_MTD_TESTS=m
CONFIG_MTD_BLOCK=y
CONFIG_MTD_SLRAM=m
CONFIG_MTD_PHRAM=m
CONFIG_MTD_SPI_NAND=y
CONFIG_MTD_SPI_NOR=y
CONFIG_MTD_UBI=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_VIRTIO_BLK=y
CONFIG_LIGHT_DSMART_CARD=y
CONFIG_EEPROM_AT24=y
CONFIG_SCSI=y
CONFIG_BLK_DEV_SD=y
CONFIG_NETDEVICES=y
CONFIG_TUN=y
CONFIG_VIRTIO_NET=y
CONFIG_MACB=y
CONFIG_STMMAC_ETH=y
CONFIG_DWMAC_LIGHT=y
CONFIG_MICROSEMI_PHY=y
CONFIG_REALTEK_PHY=y
CONFIG_MARVELL_PHY=y
CONFIG_USB_USBNET=m
# CONFIG_USB_NET_AX8817X is not set
# CONFIG_USB_NET_AX88179_178A is not set
# CONFIG_USB_NET_NET1080 is not set
CONFIG_RTL8723DS=y
CONFIG_INPUT_MOUSEDEV=y
CONFIG_INPUT_EVDEV=y
CONFIG_KEYBOARD_GPIO=y
# CONFIG_INPUT_MOUSE is not set
CONFIG_INPUT_TOUCHSCREEN=y
CONFIG_TOUCHSCREEN_GOODIX=y
CONFIG_INPUT_MISC=y
CONFIG_INPUT_UINPUT=y
CONFIG_SERIAL_8250=y
# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_8250_NR_UARTS=6
CONFIG_SERIAL_8250_RUNTIME_UARTS=6
CONFIG_SERIAL_8250_DW=y
CONFIG_SERIAL_OF_PLATFORM=y
CONFIG_SERIAL_EARLYCON_RISCV_SBI=y
CONFIG_VIRTIO_CONSOLE=y
CONFIG_HW_RANDOM=y
CONFIG_HW_RANDOM_VIRTIO=y
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_DESIGNWARE_PLATFORM=y
CONFIG_SPI=y
CONFIG_SPI_DW_QUAD=y
CONFIG_SPI_DESIGNWARE=y
CONFIG_SPI_DW_MMIO=y
CONFIG_SPI_SPIDEV=y
# CONFIG_PTP_1588_CLOCK is not set
CONFIG_PINCTRL=y
CONFIG_GPIOLIB=y
CONFIG_GPIO_SYSFS=y
CONFIG_GPIO_DWAPB=y
CONFIG_GPIO_PCA953X=y
CONFIG_GPIO_PCA953X_IRQ=y
CONFIG_POWER_SUPPLY=y
CONFIG_SENSORS_MR75203=y
CONFIG_THERMAL=y
CONFIG_CPU_THERMAL=y
CONFIG_THERMAL_EMULATION=y
CONFIG_WATCHDOG=y
CONFIG_DW_WATCHDOG=y
CONFIG_LIGHT_PMIC_WATCHDOG=y
CONFIG_WATCHDOG_PRETIMEOUT_GOV=y
CONFIG_WATCHDOG_PRETIMEOUT_GOV_SEL=m
CONFIG_WATCHDOG_PRETIMEOUT_GOV_PANIC=y
#CONFIG_WATCHDOG_PRETIMEOUT_DEFAULT_GOV_PANIC=y
CONFIG_WATCHDOG_PRETIMEOUT_DEFAULT_GOV_NOOP=y
CONFIG_WATCHDOG_OPEN_TIMEOUT=32
CONFIG_ABX500_CORE=y
CONFIG_REGULATOR=y
CONFIG_REGULATOR_FIXED_VOLTAGE=y
CONFIG_MEDIA_SUPPORT=y
# CONFIG_MEDIA_ANALOG_TV_SUPPORT is not set
# CONFIG_MEDIA_DIGITAL_TV_SUPPORT is not set
CONFIG_MEDIA_USB_SUPPORT=y
CONFIG_USB_VIDEO_CLASS=m
CONFIG_V4L_PLATFORM_DRIVERS=y
CONFIG_VIDEO_ASPEED=y
CONFIG_V4L_MEM2MEM_DRIVERS=y
# CONFIG_MEDIA_TUNER_SIMPLE is not set
# CONFIG_MEDIA_TUNER_TDA18250 is not set
# CONFIG_MEDIA_TUNER_TDA8290 is not set
# CONFIG_MEDIA_TUNER_TDA827X is not set
# CONFIG_MEDIA_TUNER_TDA18271 is not set
# CONFIG_MEDIA_TUNER_TDA9887 is not set
# CONFIG_MEDIA_TUNER_TEA5761 is not set
# CONFIG_MEDIA_TUNER_TEA5767 is not set
# CONFIG_MEDIA_TUNER_MSI001 is not set
# CONFIG_MEDIA_TUNER_MT20XX is not set
# CONFIG_MEDIA_TUNER_MT2060 is not set
# CONFIG_MEDIA_TUNER_MT2063 is not set
# CONFIG_MEDIA_TUNER_MT2266 is not set
# CONFIG_MEDIA_TUNER_MT2131 is not set
# CONFIG_MEDIA_TUNER_QT1010 is not set
# CONFIG_MEDIA_TUNER_XC2028 is not set
# CONFIG_MEDIA_TUNER_XC5000 is not set
# CONFIG_MEDIA_TUNER_XC4000 is not set
# CONFIG_MEDIA_TUNER_MXL5005S is not set
# CONFIG_MEDIA_TUNER_MXL5007T is not set
# CONFIG_MEDIA_TUNER_MC44S803 is not set
# CONFIG_MEDIA_TUNER_MAX2165 is not set
# CONFIG_MEDIA_TUNER_TDA18218 is not set
# CONFIG_MEDIA_TUNER_FC0011 is not set
# CONFIG_MEDIA_TUNER_FC0012 is not set
# CONFIG_MEDIA_TUNER_FC0013 is not set
# CONFIG_MEDIA_TUNER_TDA18212 is not set
# CONFIG_MEDIA_TUNER_E4000 is not set
# CONFIG_MEDIA_TUNER_FC2580 is not set
# CONFIG_MEDIA_TUNER_M88RS6000T is not set
# CONFIG_MEDIA_TUNER_TUA9001 is not set
# CONFIG_MEDIA_TUNER_SI2157 is not set
# CONFIG_MEDIA_TUNER_IT913X is not set
# CONFIG_MEDIA_TUNER_R820T is not set
# CONFIG_MEDIA_TUNER_MXL301RF is not set
# CONFIG_MEDIA_TUNER_QM1D1C0042 is not set
# CONFIG_MEDIA_TUNER_QM1D1B0004 is not set
CONFIG_DRM=y
CONFIG_DRM_PANEL_SIMPLE=y
CONFIG_DRM_PANEL_ILITEK_ILI9881C=y
CONFIG_DRM_PANEL_ILI9881D=y
CONFIG_DRM_VERISILICON=y
CONFIG_BACKLIGHT_CLASS_DEVICE=y
CONFIG_BACKLIGHT_PWM=y
CONFIG_FRAMEBUFFER_CONSOLE=y
CONFIG_LOGO=y
CONFIG_SOUND=y
CONFIG_SND=y
CONFIG_SND_USB_AUDIO=m
CONFIG_SND_SOC=y
CONFIG_SND_SOC_THEAD_LIGHT=y
CONFIG_SND_SOC_AW87519=y
CONFIG_SND_SOC_BT_SCO=y
CONFIG_SND_SOC_ES7210=y
CONFIG_SND_SOC_ES8156=y
CONFIG_SND_SOC_WM8960=y
CONFIG_SND_SIMPLE_CARD=y
CONFIG_SND_AUDIO_GRAPH_CARD=y
CONFIG_UHID=y
CONFIG_HID_PID=y
CONFIG_USB_HIDDEV=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_PLATFORM=y
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_USB_STORAGE_SDDR09=y
CONFIG_USB_STORAGE_SDDR55=y
CONFIG_USB_DWC3=m
# CONFIG_USB_DWC3_OF_SIMPLE is not set
CONFIG_USB_GADGET=y
CONFIG_USB_CONFIGFS=y
CONFIG_USB_CONFIGFS_F_FS=y
CONFIG_USB_CONFIGFS_F_ACC=y
CONFIG_USB_ZERO=m
CONFIG_USB_ETH=m
CONFIG_USB_ETH_EEM=y
CONFIG_USB_G_NCM=m
CONFIG_USB_MASS_STORAGE=m
CONFIG_USB_G_SERIAL=m
CONFIG_USB_G_MULTI=m
CONFIG_USB_G_MULTI_CDC=y
CONFIG_USB_ROLE_SWITCH=m
CONFIG_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_PLTFM=y
CONFIG_MMC_SDHCI_OF_DWCMSHC=y
CONFIG_NEW_LEDS=y
CONFIG_LEDS_CLASS=y
CONFIG_LEDS_GPIO=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_DRV_XGENE=y
CONFIG_DMADEVICES=y
CONFIG_DW_AXI_DMAC=y
CONFIG_DMATEST=y
CONFIG_SW_SYNC=y
CONFIG_UDMABUF=y
CONFIG_DMABUF_SELFTESTS=m
CONFIG_VIRTIO_MMIO=y
CONFIG_VIRTIO_KHV_MMIO=y
CONFIG_VHOST_NET=y
CONFIG_VHOST_VSOCK=y
CONFIG_CLK_LIGHT_FM=y
CONFIG_HWSPINLOCK=y
CONFIG_HWSPINLOCK_LIGHT=y
CONFIG_HWSPINLOCK_LIGHT_TEST=m
CONFIG_MAILBOX=y
CONFIG_IIO=y
CONFIG_IIO_SW_DEVICE=y
CONFIG_PWM=y
CONFIG_PWM_LIGHT=y
CONFIG_NVMEM_THEAD_LIGHT_EFUSE=y
CONFIG_TEE=y
CONFIG_OPTEE=y
CONFIG_OPTEE_BENCHMARK=y
CONFIG_LIGHT_GPU_VIV=m
# CONFIG_LIGHT_NET is not set
CONFIG_EXT4_FS=y
CONFIG_EXT4_FS_POSIX_ACL=y
CONFIG_AUTOFS4_FS=y
CONFIG_FUSE_FS=y
CONFIG_MSDOS_FS=y
CONFIG_VFAT_FS=y
CONFIG_TMPFS=y
CONFIG_TMPFS_POSIX_ACL=y
CONFIG_HUGETLBFS=y
CONFIG_JFFS2_FS=y
CONFIG_UBIFS_FS=y
CONFIG_NFS_FS=y
CONFIG_NFS_V4=y
CONFIG_NFS_V4_1=y
CONFIG_NFS_V4_2=y
CONFIG_ROOT_NFS=y
CONFIG_9P_FS=y
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_ISO8859_1=y
CONFIG_CRYPTO_AUTHENC=y
CONFIG_CRYPTO_DH=y
CONFIG_CRYPTO_CURVE25519=y
CONFIG_CRYPTO_CHACHA20POLY1305=y
CONFIG_CRYPTO_OFB=y
CONFIG_CRYPTO_MD5=y
CONFIG_CRYPTO_SHA512=y
CONFIG_CRYPTO_SHA3=y
CONFIG_CRYPTO_SM3=y
CONFIG_CRYPTO_DES=y
CONFIG_CRYPTO_USER_API_HASH=y
CONFIG_DMA_CMA=y
CONFIG_DMA_PERNUMA_CMA=y
CONFIG_CMA_SIZE_MBYTES=32
CONFIG_PRINTK_TIME=y
CONFIG_DYNAMIC_DEBUG=y
CONFIG_DEBUG_INFO=y
CONFIG_MAGIC_SYSRQ=y
CONFIG_DEBUG_FS=y
CONFIG_DETECT_HUNG_TASK=y
CONFIG_DEBUG_ATOMIC_SLEEP=y
# CONFIG_RCU_TRACE is not set
CONFIG_OVERLAY_FS=y
CONFIG_LOCKUP_DETECTOR=y
CONFIG_SOFTLOCKUP_DETECTOR=y
CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
# CONFIG_SUSPEND is not set
# CONFIG_PM_SLEEP is not set

1
arch/riscv/configs/ice_defconfig
View File

@@ -180,6 +180,5 @@ CONFIG_DEBUG_INFO=y
CONFIG_MAGIC_SYSRQ=y
CONFIG_DEBUG_FS=y
CONFIG_DETECT_HUNG_TASK=y
CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=60
CONFIG_DEBUG_ATOMIC_SLEEP=y
# CONFIG_RCU_TRACE is not set

449
arch/riscv/configs/light-android_defconfig
View File

@@ -1,34 +1,273 @@
CONFIG_COMPILE_TEST=y
CONFIG_SYSVIPC=y
CONFIG_POSIX_MQUEUE=y
# see kernel/configs/android-5.10/android-base.config
# KEEP ALPHABETICALLY SORTED
# CONFIG_ANDROID_LOW_MEMORY_KILLER is not set
# CONFIG_ANDROID_PARANOID_NETWORK is not set
# CONFIG_BPFILTER is not set
# CONFIG_CRYPTO_MD4 is not set
# CONFIG_DEVMEM is not set
# CONFIG_FHANDLE is not set
# CONFIG_FW_CACHE is not set
# CONFIG_IP6_NF_NAT is not set
# CONFIG_MODULE_FORCE_UNLOAD is not set
# CONFIG_NFSD is not set
# CONFIG_NFS_FS is not set
# CONFIG_PM_AUTOSLEEP is not set
# CONFIG_RT_GROUP_SCHED is not set
# CONFIG_SYSVIPC is not set
# CONFIG_USELIB is not set
CONFIG_ADVISE_SYSCALLS=y
CONFIG_AIO=y
CONFIG_ANDROID=y
CONFIG_ANDROID_BINDER_DEVICES="binder,hwbinder,vndbinder"
CONFIG_ANDROID_BINDER_IPC=y
CONFIG_ANDROID_BINDERFS=y
CONFIG_ASHMEM=y
CONFIG_AUDIT=y
CONFIG_NO_HZ=y
CONFIG_BINFMT_ELF=y
CONFIG_BINFMT_SCRIPT=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLOCK=y
CONFIG_BPF_JIT=y
CONFIG_BPF_SYSCALL=y
CONFIG_CGROUPS=y
CONFIG_CGROUP_BPF=y
CONFIG_CGROUP_CPUACCT=y
CONFIG_CGROUP_FREEZER=y
CONFIG_CGROUP_SCHED=y
CONFIG_CROSS_MEMORY_ATTACH=y
CONFIG_CRYPTO_AES=y
CONFIG_CRYPTO_CBC=y
CONFIG_CRYPTO_CHACHA20POLY1305=y
CONFIG_CRYPTO_CMAC=y
CONFIG_CRYPTO_CTR=y
CONFIG_CRYPTO_ECB=y
CONFIG_CRYPTO_GCM=y
CONFIG_CRYPTO_HMAC=y
CONFIG_CRYPTO_MD5=y
CONFIG_CRYPTO_NULL=y
CONFIG_CRYPTO_SHA1=y
CONFIG_CRYPTO_SHA256=y
CONFIG_CRYPTO_SHA512=y
CONFIG_CRYPTO_XCBC=y
CONFIG_DEBUG_LIST=y
CONFIG_DEFAULT_SECURITY_SELINUX=y
CONFIG_DM_SNAPSHOT=y
CONFIG_DM_VERITY=y
CONFIG_DUMMY=y
CONFIG_EMBEDDED=y
CONFIG_EPOLL=y
CONFIG_EVENTFD=y
CONFIG_FILE_LOCKING=y
CONFIG_FS_ENCRYPTION=y
CONFIG_FS_VERITY=y
CONFIG_FS_VERITY_BUILTIN_SIGNATURES=y
CONFIG_FUSE_FS=y
CONFIG_FUTEX=y
CONFIG_HARDENED_USERCOPY=y
CONFIG_HID_GENERIC=y
CONFIG_HID_PLAYSTATION=y
CONFIG_PLAYSTATION_FF=y
CONFIG_HID_SONY=y
CONFIG_SONY_FF=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_PREEMPT=y
CONFIG_TASKSTATS=y
CONFIG_TASK_DELAY_ACCT=y
CONFIG_TASK_XACCT=y
CONFIG_TASK_IO_ACCOUNTING=y
CONFIG_PSI=y
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_UCLAMP_TASK=y
CONFIG_CGROUPS=y
CONFIG_CGROUP_SCHED=y
CONFIG_UCLAMP_TASK_GROUP=y
CONFIG_CGROUP_FREEZER=y
CONFIG_CGROUP_CPUACCT=y
CONFIG_CGROUP_BPF=y
CONFIG_INET6_ESP=y
CONFIG_INET6_IPCOMP=y
CONFIG_INET=y
CONFIG_INET_DIAG_DESTROY=y
CONFIG_INET_ESP=y
CONFIG_INET_UDP_DIAG=y
CONFIG_INOTIFY_USER=y
CONFIG_INPUT=y
CONFIG_INPUT_EVDEV=y
CONFIG_INPUT_JOYSTICK=y
CONFIG_IP6_NF_FILTER=y
CONFIG_IP6_NF_IPTABLES=y
CONFIG_IP6_NF_MANGLE=y
CONFIG_IP6_NF_MATCH_RPFILTER=y
CONFIG_IP6_NF_RAW=y
CONFIG_IP6_NF_TARGET_REJECT=y
CONFIG_IPV6=y
CONFIG_IPV6_MIP6=y
CONFIG_IPV6_MULTIPLE_TABLES=y
CONFIG_IPV6_OPTIMISTIC_DAD=y
CONFIG_IPV6_ROUTER_PREF=y
CONFIG_IPV6_ROUTE_INFO=y
CONFIG_IPV6_VTI=y
CONFIG_IP_ADVANCED_ROUTER=y
CONFIG_IP_MULTICAST=y
CONFIG_IP_MULTIPLE_TABLES=y
CONFIG_IP_NF_ARPFILTER=y
CONFIG_IP_NF_ARPTABLES=y
CONFIG_IP_NF_ARP_MANGLE=y
CONFIG_IP_NF_FILTER=y
CONFIG_IP_NF_IPTABLES=y
CONFIG_IP_NF_MANGLE=y
CONFIG_IP_NF_MATCH_ECN=y
CONFIG_IP_NF_MATCH_TTL=y
CONFIG_IP_NF_NAT=y
CONFIG_IP_NF_RAW=y
CONFIG_IP_NF_SECURITY=y
CONFIG_IP_NF_TARGET_MASQUERADE=y
CONFIG_IP_NF_TARGET_NETMAP=y
CONFIG_IP_NF_TARGET_REDIRECT=y
CONFIG_IP_NF_TARGET_REJECT=y
CONFIG_JOYSTICK_XPAD=y
CONFIG_L2TP=y
CONFIG_MAGIC_SYSRQ=y
CONFIG_MD=y
CONFIG_MEMBARRIER=y
CONFIG_MMU=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
CONFIG_MODVERSIONS=y
CONFIG_MULTIUSER=y
CONFIG_NAMESPACES=y
CONFIG_NET=y
CONFIG_NETDEVICES=y
CONFIG_NETFILTER=y
CONFIG_NETFILTER_XT_MATCH_BPF=y
CONFIG_NETFILTER_XT_MATCH_COMMENT=y
CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y
CONFIG_NETFILTER_XT_MATCH_CONNMARK=y
CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y
CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=y
CONFIG_NETFILTER_XT_MATCH_HELPER=y
CONFIG_NETFILTER_XT_MATCH_IPRANGE=y
CONFIG_NETFILTER_XT_MATCH_LENGTH=y
CONFIG_NETFILTER_XT_MATCH_LIMIT=y
CONFIG_NETFILTER_XT_MATCH_MAC=y
CONFIG_NETFILTER_XT_MATCH_MARK=y
CONFIG_NETFILTER_XT_MATCH_OWNER=y
CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y
CONFIG_NETFILTER_XT_MATCH_POLICY=y
CONFIG_NETFILTER_XT_MATCH_QUOTA2=y
CONFIG_NETFILTER_XT_MATCH_QUOTA2_LOG=y
CONFIG_NETFILTER_XT_MATCH_QUOTA=y
CONFIG_NETFILTER_XT_MATCH_SOCKET=y
CONFIG_NETFILTER_XT_MATCH_STATE=y
CONFIG_NETFILTER_XT_MATCH_STATISTIC=y
CONFIG_NETFILTER_XT_MATCH_STRING=y
CONFIG_NETFILTER_XT_MATCH_TIME=y
CONFIG_NETFILTER_XT_MATCH_U32=y
CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y
CONFIG_NETFILTER_XT_TARGET_CONNMARK=y
CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=y
CONFIG_NETFILTER_XT_TARGET_CT=y
CONFIG_NETFILTER_XT_TARGET_IDLETIMER=y
CONFIG_NETFILTER_XT_TARGET_MARK=y
CONFIG_NETFILTER_XT_TARGET_NFLOG=y
CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y
CONFIG_NETFILTER_XT_TARGET_SECMARK=y
CONFIG_NETFILTER_XT_TARGET_TCPMSS=y
CONFIG_NETFILTER_XT_TARGET_TPROXY=y
CONFIG_NETFILTER_XT_TARGET_TRACE=y
CONFIG_NET_CLS_ACT=y
CONFIG_NET_CLS_BPF=y
CONFIG_NET_CLS_U32=y
CONFIG_NET_EMATCH=y
CONFIG_NET_EMATCH_U32=y
CONFIG_NET_IPGRE_DEMUX=y
CONFIG_NET_IPVTI=y
CONFIG_NET_KEY=y
CONFIG_NET_NS=y
CONFIG_NET_SCHED=y
CONFIG_NET_SCH_HTB=y
CONFIG_NET_SCH_INGRESS=y
CONFIG_NF_CONNTRACK=y
CONFIG_NF_CONNTRACK_AMANDA=y
CONFIG_NF_CONNTRACK_EVENTS=y
CONFIG_NF_CONNTRACK_FTP=y
CONFIG_NF_CONNTRACK_H323=y
CONFIG_NF_CONNTRACK_IRC=y
CONFIG_NF_CONNTRACK_NETBIOS_NS=y
CONFIG_NF_CONNTRACK_PPTP=y
CONFIG_NF_CONNTRACK_SANE=y
CONFIG_NF_CONNTRACK_SECMARK=y
CONFIG_NF_CONNTRACK_TFTP=y
CONFIG_NF_CT_NETLINK=y
CONFIG_NF_CT_PROTO_DCCP=y
CONFIG_NF_CT_PROTO_SCTP=y
CONFIG_NF_CT_PROTO_UDPLITE=y
CONFIG_NF_NAT=y
CONFIG_NF_SOCKET_IPV4=y
CONFIG_NF_SOCKET_IPV6=y
CONFIG_NO_HZ=y
CONFIG_PACKET=y
CONFIG_PM_WAKELOCKS=y
CONFIG_POSIX_TIMERS=y
CONFIG_PPP=y
CONFIG_PPPOL2TP=y
CONFIG_PPP_BSDCOMP=y
CONFIG_PPP_DEFLATE=y
CONFIG_PPP_MPPE=y
CONFIG_PPTP=y
CONFIG_PREEMPT=y
CONFIG_PROC_FS=y
CONFIG_PROFILING=y
CONFIG_PSI=y
CONFIG_QFMT_V2=y
CONFIG_QUOTA=y
CONFIG_QUOTACTL=y
CONFIG_RD_LZ4=y
CONFIG_RTC_CLASS=y
CONFIG_SCHED_DEBUG=y
CONFIG_SECCOMP=y
CONFIG_SECCOMP_FILTER=y
CONFIG_SECURITY=y
CONFIG_SECURITY_NETWORK=y
CONFIG_SECURITY_SELINUX=y
CONFIG_SHMEM=y
CONFIG_SIGNALFD=y
CONFIG_SND=y
CONFIG_SOUND=y
CONFIG_STACKPROTECTOR=y
CONFIG_STACKPROTECTOR_STRONG=y
CONFIG_STAGING=y
CONFIG_STATIC_USERMODEHELPER=y
CONFIG_STRICT_KERNEL_RWX=y
CONFIG_STRICT_MODULE_RWX=y
CONFIG_SUSPEND=y
CONFIG_SYNC_FILE=y
CONFIG_SYSFS=y
CONFIG_TASKSTATS=y
CONFIG_TASK_IO_ACCOUNTING=y
CONFIG_TASK_XACCT=y
CONFIG_TIMERFD=y
CONFIG_TRACE_GPU_MEM=y
CONFIG_TTY=y
CONFIG_TUN=y
CONFIG_UHID=y
CONFIG_UID_SYS_STATS=y
CONFIG_UNIX=y
CONFIG_USB=y
CONFIG_USB_CONFIGFS=y
CONFIG_USB_CONFIGFS_F_ACC=y
CONFIG_USB_CONFIGFS_F_AUDIO_SRC=y
CONFIG_USB_CONFIGFS_F_FS=y
CONFIG_USB_CONFIGFS_F_MIDI=y
CONFIG_USB_CONFIGFS_UEVENT=y
CONFIG_USB_GADGET=y
CONFIG_USB_SUPPORT=y
CONFIG_UTS_NS=y
CONFIG_VETH=y
CONFIG_XFRM_INTERFACE=y
CONFIG_XFRM_MIGRATE=y
CONFIG_XFRM_STATISTICS=y
CONFIG_XFRM_USER=y
# kernel/configs/android-5.10/android-base.config
CONFIG_COMPILE_TEST=y
CONFIG_POSIX_MQUEUE=y
CONFIG_TASK_DELAY_ACCT=y
CONFIG_UCLAMP_TASK=y
CONFIG_UCLAMP_TASK_GROUP=y
CONFIG_USER_NS=y
CONFIG_CHECKPOINT_RESTORE=y
CONFIG_BLK_DEV_INITRD=y
# CONFIG_FHANDLE is not set
# CONFIG_BUG is not set
CONFIG_KALLSYMS_ALL=y
CONFIG_BPF_SYSCALL=y
CONFIG_EMBEDDED=y
CONFIG_PROFILING=y
CONFIG_SOC_SIFIVE=y
CONFIG_SOC_THEAD=y
CONFIG_SMP=y
@@ -45,133 +284,26 @@ CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
CONFIG_CPUFREQ_DT=y
CONFIG_RISV_THEAD_LIGHT_CPUFREQ=y
CONFIG_PM_WAKELOCKS=y
CONFIG_PM_WAKELOCKS_LIMIT=0
# CONFIG_PM_WAKELOCKS_GC is not set
CONFIG_ENERGY_MODEL=y
CONFIG_VIRTUALIZATION=y
CONFIG_KVM=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
CONFIG_MODVERSIONS=y
CONFIG_BLK_INLINE_ENCRYPTION=y
# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
CONFIG_CMA=y
CONFIG_CMA_DEBUGFS=y
CONFIG_CMA_AREAS=16
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_XFRM_USER=y
CONFIG_XFRM_INTERFACE=y
CONFIG_XFRM_MIGRATE=y
CONFIG_XFRM_STATISTICS=y
CONFIG_NET_KEY=y
CONFIG_INET=y
CONFIG_IP_MULTICAST=y
CONFIG_IP_ADVANCED_ROUTER=y
CONFIG_IP_MULTIPLE_TABLES=y
CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y
CONFIG_IP_PNP_BOOTP=y
CONFIG_IP_PNP_RARP=y
CONFIG_NET_IPGRE_DEMUX=y
CONFIG_NET_IPVTI=y
CONFIG_INET_ESP=y
CONFIG_INET_UDP_DIAG=y
CONFIG_INET_DIAG_DESTROY=y
CONFIG_IPV6_ROUTER_PREF=y
CONFIG_IPV6_ROUTE_INFO=y
CONFIG_IPV6_OPTIMISTIC_DAD=y
CONFIG_INET6_ESP=y
CONFIG_INET6_IPCOMP=y
CONFIG_IPV6_MIP6=y
CONFIG_IPV6_VTI=y
CONFIG_IPV6_MULTIPLE_TABLES=y
CONFIG_NETFILTER=y
CONFIG_NF_CONNTRACK=y
CONFIG_NF_CONNTRACK_SECMARK=y
CONFIG_NF_CONNTRACK_EVENTS=y
CONFIG_NF_CONNTRACK_AMANDA=y
CONFIG_NF_CONNTRACK_FTP=y
CONFIG_NF_CONNTRACK_H323=y
CONFIG_NF_CONNTRACK_IRC=y
CONFIG_NF_CONNTRACK_NETBIOS_NS=y
CONFIG_NF_CONNTRACK_PPTP=y
CONFIG_NF_CONNTRACK_SANE=y
CONFIG_NF_CONNTRACK_TFTP=y
CONFIG_NF_CT_NETLINK=y
CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y
CONFIG_NETFILTER_XT_TARGET_CONNMARK=y
CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=y
CONFIG_NETFILTER_XT_TARGET_CT=y
CONFIG_NETFILTER_XT_TARGET_IDLETIMER=y
CONFIG_NETFILTER_XT_TARGET_MARK=y
CONFIG_NETFILTER_XT_TARGET_NFLOG=y
CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y
CONFIG_NETFILTER_XT_TARGET_TPROXY=y
CONFIG_NETFILTER_XT_TARGET_TRACE=y
CONFIG_NETFILTER_XT_TARGET_SECMARK=y
CONFIG_NETFILTER_XT_TARGET_TCPMSS=y
CONFIG_NETFILTER_XT_MATCH_BPF=y
CONFIG_NETFILTER_XT_MATCH_COMMENT=y
CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y
CONFIG_NETFILTER_XT_MATCH_CONNMARK=y
CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y
CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=y
CONFIG_NETFILTER_XT_MATCH_HELPER=y
CONFIG_NETFILTER_XT_MATCH_IPRANGE=y
CONFIG_NETFILTER_XT_MATCH_LENGTH=y
CONFIG_NETFILTER_XT_MATCH_LIMIT=y
CONFIG_NETFILTER_XT_MATCH_MAC=y
CONFIG_NETFILTER_XT_MATCH_MARK=y
CONFIG_NETFILTER_XT_MATCH_OWNER=y
CONFIG_NETFILTER_XT_MATCH_POLICY=y
CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y
CONFIG_NETFILTER_XT_MATCH_QUOTA=y
CONFIG_NETFILTER_XT_MATCH_QUOTA2=y
CONFIG_NETFILTER_XT_MATCH_QUOTA2_LOG=y
CONFIG_NETFILTER_XT_MATCH_SOCKET=y
CONFIG_NETFILTER_XT_MATCH_STATE=y
CONFIG_NETFILTER_XT_MATCH_STATISTIC=y
CONFIG_NETFILTER_XT_MATCH_STRING=y
CONFIG_NETFILTER_XT_MATCH_TIME=y
CONFIG_NETFILTER_XT_MATCH_U32=y
CONFIG_IP_NF_IPTABLES=y
CONFIG_IP_NF_MATCH_ECN=y
CONFIG_IP_NF_MATCH_TTL=y
CONFIG_IP_NF_FILTER=y
CONFIG_IP_NF_TARGET_REJECT=y
CONFIG_IP_NF_NAT=y
CONFIG_IP_NF_TARGET_MASQUERADE=y
CONFIG_IP_NF_TARGET_NETMAP=y
CONFIG_IP_NF_TARGET_REDIRECT=y
CONFIG_IP_NF_MANGLE=y
CONFIG_IP_NF_RAW=y
CONFIG_IP_NF_SECURITY=y
CONFIG_IP_NF_ARPTABLES=y
CONFIG_IP_NF_ARPFILTER=y
CONFIG_IP_NF_ARP_MANGLE=y
CONFIG_IP6_NF_IPTABLES=y
CONFIG_IP6_NF_MATCH_RPFILTER=y
CONFIG_IP6_NF_FILTER=y
CONFIG_IP6_NF_TARGET_REJECT=y
CONFIG_IP6_NF_MANGLE=y
CONFIG_IP6_NF_RAW=y
CONFIG_L2TP=y
CONFIG_BRIDGE=y
CONFIG_NET_SCHED=y
CONFIG_NET_SCH_HTB=y
CONFIG_NET_SCH_NETEM=y
CONFIG_NET_SCH_INGRESS=y
CONFIG_NET_CLS_U32=y
CONFIG_NET_CLS_BPF=y
CONFIG_NET_EMATCH=y
CONFIG_NET_EMATCH_U32=y
CONFIG_NET_CLS_ACT=y
CONFIG_VSOCKETS=y
# CONFIG_VSOCKETS_LOOPBACK is not set
CONFIG_VIRTIO_VSOCKETS=y
CONFIG_NETLINK_DIAG=y
CONFIG_BPF_JIT=y
CONFIG_BT=y
CONFIG_BT_RFCOMM=y
CONFIG_BT_RFCOMM_TTY=y
@@ -194,48 +326,30 @@ CONFIG_MTD_PHRAM=m
CONFIG_MTD_SPI_NAND=y
CONFIG_MTD_SPI_NOR=y
CONFIG_MTD_UBI=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_SIZE=8192
CONFIG_VIRTIO_BLK=y
CONFIG_UID_SYS_STATS=y
CONFIG_LIGHT_DSMART_CARD=y
CONFIG_EEPROM_AT24=y
CONFIG_SCSI=y
CONFIG_BLK_DEV_SD=y
CONFIG_MD=y
CONFIG_BLK_DEV_DM=y
CONFIG_DM_CRYPT=y
CONFIG_DM_DEFAULT_KEY=y
CONFIG_DM_SNAPSHOT=y
CONFIG_DM_UEVENT=y
CONFIG_DM_VERITY=y
CONFIG_DM_VERITY_FEC=y
CONFIG_DM_BOW=y
CONFIG_NETDEVICES=y
CONFIG_DUMMY=y
CONFIG_TUN=y
CONFIG_VETH=y
CONFIG_VIRTIO_NET=y
CONFIG_MACB=y
CONFIG_STMMAC_ETH=y
CONFIG_DWMAC_LIGHT=y
CONFIG_MICROSEMI_PHY=y
CONFIG_REALTEK_PHY=y
CONFIG_PPP=y
CONFIG_PPP_BSDCOMP=y
CONFIG_PPP_DEFLATE=y
CONFIG_PPP_MPPE=y
CONFIG_PPTP=y
CONFIG_PPPOL2TP=y
CONFIG_USB_RTL8152=y
CONFIG_USB_USBNET=m
CONFIG_RTL8723DS=y
CONFIG_INPUT_MOUSEDEV=m
CONFIG_INPUT_EVDEV=y
CONFIG_KEYBOARD_GPIO=y
CONFIG_INPUT_JOYSTICK=y
CONFIG_JOYSTICK_XPAD=y
CONFIG_JOYSTICK_XPAD_FF=y
CONFIG_JOYSTICK_XPAD_LEDS=y
CONFIG_INPUT_TABLET=y
@@ -291,8 +405,6 @@ CONFIG_DRM_VERISILICON=y
CONFIG_BACKLIGHT_CLASS_DEVICE=y
CONFIG_BACKLIGHT_PWM=y
CONFIG_LOGO=y
CONFIG_SOUND=y
CONFIG_SND=y
CONFIG_SND_USB_AUDIO=m
CONFIG_SND_SOC=y
CONFIG_SND_SOC_THEAD_LIGHT=y
@@ -301,7 +413,6 @@ CONFIG_SND_SOC_WM8960=y
CONFIG_SND_SIMPLE_CARD=y
CONFIG_SND_AUDIO_GRAPH_CARD=y
CONFIG_HIDRAW=y
CONFIG_UHID=y
CONFIG_HID_A4TECH=y
CONFIG_HID_ACRUX=y
CONFIG_HID_ACRUX_FF=y
@@ -340,14 +451,10 @@ CONFIG_HID_PANTHERLORD=y
CONFIG_PANTHERLORD_FF=y
CONFIG_HID_PETALYNX=y
CONFIG_HID_PICOLCD=y
CONFIG_HID_PLAYSTATION=y
CONFIG_PLAYSTATION_FF=y
CONFIG_HID_PRIMAX=y
CONFIG_HID_ROCCAT=y
CONFIG_HID_SAITEK=y
CONFIG_HID_SAMSUNG=y
CONFIG_HID_SONY=y
CONFIG_SONY_FF=y
CONFIG_HID_SPEEDLINK=y
CONFIG_HID_STEAM=y
CONFIG_HID_SUNPLUS=y
@@ -374,13 +481,6 @@ CONFIG_USB_STORAGE_SDDR09=y
CONFIG_USB_STORAGE_SDDR55=y
CONFIG_USB_DWC3=m
# CONFIG_USB_DWC3_OF_SIMPLE is not set
CONFIG_USB_GADGET=y
CONFIG_USB_CONFIGFS=y
CONFIG_USB_CONFIGFS_UEVENT=y
CONFIG_USB_CONFIGFS_F_FS=y
CONFIG_USB_CONFIGFS_F_ACC=y
CONFIG_USB_CONFIGFS_F_AUDIO_SRC=y
CONFIG_USB_CONFIGFS_F_MIDI=y
CONFIG_USB_ZERO=m
CONFIG_USB_ETH=m
CONFIG_USB_ETH_EEM=y
@@ -394,7 +494,6 @@ CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_PLTFM=y
CONFIG_MMC_SDHCI_OF_DWCMSHC=y
CONFIG_LEDS_GPIO=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_DRV_XGENE=y
CONFIG_DMADEVICES=y
CONFIG_DW_AXI_DMAC=y
@@ -410,8 +509,6 @@ CONFIG_DMABUF_HEAPS_SYSTEM=y
# CONFIG_VIRTIO_MENU is not set
CONFIG_VHOST_NET=y
CONFIG_VHOST_VSOCK=y
CONFIG_STAGING=y
CONFIG_ASHMEM=y
CONFIG_ION=y
CONFIG_ION_SYSTEM_HEAP=y
CONFIG_ION_CMA_HEAP=y
@@ -424,8 +521,6 @@ CONFIG_IIO=y
CONFIG_IIO_SW_DEVICE=y
CONFIG_PWM=y
CONFIG_PWM_LIGHT=y
CONFIG_ANDROID=y
CONFIG_ANDROID_BINDER_IPC=y
CONFIG_NVMEM_THEAD_LIGHT_EFUSE=y
CONFIG_LIGHT_GPU_VIV=m
# CONFIG_LIGHT_NET is not set
@@ -434,14 +529,8 @@ CONFIG_EXT4_FS_POSIX_ACL=y
CONFIG_EXT4_FS_SECURITY=y
CONFIG_F2FS_FS=y
CONFIG_F2FS_FS_SECURITY=y
CONFIG_FS_ENCRYPTION=y
CONFIG_FS_ENCRYPTION_INLINE_CRYPT=y
CONFIG_FS_VERITY=y
CONFIG_FS_VERITY_BUILTIN_SIGNATURES=y
CONFIG_QUOTA=y
CONFIG_QFMT_V2=y
CONFIG_AUTOFS4_FS=y
CONFIG_FUSE_FS=y
CONFIG_OVERLAY_FS=y
CONFIG_MSDOS_FS=y
CONFIG_VFAT_FS=y
@@ -457,17 +546,9 @@ CONFIG_PSTORE_RAM=y
CONFIG_9P_FS=y
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_ISO8859_1=y
CONFIG_SECURITY=y
CONFIG_SECURITY_NETWORK=y
CONFIG_HARDENED_USERCOPY=y
CONFIG_STATIC_USERMODEHELPER=y
CONFIG_SECURITY_SELINUX=y
CONFIG_CRYPTO_DH=y
CONFIG_CRYPTO_CURVE25519=y
CONFIG_CRYPTO_CHACHA20POLY1305=y
CONFIG_CRYPTO_OFB=y
CONFIG_CRYPTO_XCBC=y
CONFIG_CRYPTO_MD5=y
CONFIG_CRYPTO_SHA3=y
CONFIG_CRYPTO_SM3=y
CONFIG_CRYPTO_DES=y
@@ -477,14 +558,12 @@ CONFIG_DMA_PERNUMA_CMA=y
CONFIG_CMA_SIZE_MBYTES=32
CONFIG_PRINTK_TIME=y
CONFIG_DYNAMIC_DEBUG=y
CONFIG_MAGIC_SYSRQ=y
CONFIG_DEBUG_FS=y
CONFIG_PANIC_TIMEOUT=5
CONFIG_DETECT_HUNG_TASK=y
CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=60
CONFIG_SCHEDSTATS=y
CONFIG_DEBUG_ATOMIC_SLEEP=y
CONFIG_DEBUG_LIST=y
# CONFIG_GCC_PLUGINS is not set
# CONFIG_RCU_TRACE is not set
CONFIG_ENABLE_DEFAULT_TRACERS=y
CONFIG_GKI_HACKS_TO_FIX=y

12
arch/riscv/configs/light_defconfig
View File

@@ -143,7 +143,8 @@ CONFIG_LIGHT_PMIC_WATCHDOG=y
CONFIG_WATCHDOG_PRETIMEOUT_GOV=y
CONFIG_WATCHDOG_PRETIMEOUT_GOV_SEL=m
CONFIG_WATCHDOG_PRETIMEOUT_GOV_PANIC=y
CONFIG_WATCHDOG_PRETIMEOUT_DEFAULT_GOV_PANIC=y
#CONFIG_WATCHDOG_PRETIMEOUT_DEFAULT_GOV_PANIC=y
CONFIG_WATCHDOG_PRETIMEOUT_DEFAULT_GOV_NOOP=y
CONFIG_WATCHDOG_OPEN_TIMEOUT=32
CONFIG_ABX500_CORE=y
CONFIG_REGULATOR=y
@@ -196,6 +197,8 @@ CONFIG_V4L_MEM2MEM_DRIVERS=y
CONFIG_DRM=y
CONFIG_DRM_PANEL_SIMPLE=y
CONFIG_DRM_PANEL_ILITEK_ILI9881C=y
CONFIG_DRM_PANEL_ILI9881D=y
CONFIG_DRM_PANEL_HX8394=y
CONFIG_DRM_VERISILICON=y
CONFIG_BACKLIGHT_CLASS_DEVICE=y
CONFIG_BACKLIGHT_PWM=y
@@ -311,7 +314,12 @@ CONFIG_DEBUG_INFO=y
CONFIG_MAGIC_SYSRQ=y
CONFIG_DEBUG_FS=y
CONFIG_DETECT_HUNG_TASK=y
CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=60
CONFIG_DEBUG_ATOMIC_SLEEP=y
# CONFIG_RCU_TRACE is not set
CONFIG_OVERLAY_FS=y
CONFIG_LOCKUP_DETECTOR=y
CONFIG_SOFTLOCKUP_DETECTOR=y
CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
CONFIG_PM=y
# CONFIG_SUSPEND is not set
# CONFIG_PM_SLEEP is not set

1
arch/riscv/configs/light_emu_defconfig
View File

@@ -189,7 +189,6 @@ CONFIG_DYNAMIC_DEBUG=y
CONFIG_DEBUG_INFO=y
CONFIG_DEBUG_FS=y
CONFIG_DETECT_HUNG_TASK=y
CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=60
CONFIG_DEBUG_ATOMIC_SLEEP=y
# CONFIG_RCU_TRACE is not set
CONFIG_FORCE_MAX_ZONEORDER=15

1
arch/riscv/configs/vector_0_7_defconfig
View File

@@ -184,6 +184,5 @@ CONFIG_DEBUG_INFO=y
CONFIG_MAGIC_SYSRQ=y
CONFIG_DEBUG_FS=y
CONFIG_DETECT_HUNG_TASK=y
CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=60
CONFIG_DEBUG_ATOMIC_SLEEP=y
# CONFIG_RCU_TRACE is not set

2
arch/riscv/include/asm/Kbuild
View File

@@ -3,5 +3,7 @@ generic-y += early_ioremap.h
generic-y += extable.h
generic-y += flat.h
generic-y += kvm_para.h
generic-y += qrwlock.h
generic-y += qrwlock_types.h
generic-y += user.h
generic-y += vmlinux.lds.h

14
arch/riscv/include/asm/atomic.h
View File

@@ -55,13 +55,11 @@ static __always_inline void atomic64_set(atomic64_t *v, s64 i)
static __always_inline \
void atomic##prefix##_##op(c_type i, atomic##prefix##_t *v) \
{ \
smp_mb(); \
__asm__ __volatile__ ( \
" amo" #asm_op "." #asm_type " zero, %1, %0" \
: "+A" (v->counter) \
: "r" (I) \
: "memory"); \
smp_mb(); \
} \
#ifdef CONFIG_GENERIC_ATOMIC64
@@ -93,26 +91,22 @@ c_type atomic##prefix##_fetch_##op##_relaxed(c_type i, \
atomic##prefix##_t *v) \
{ \
register c_type ret; \
smp_mb(); \
__asm__ __volatile__ ( \
" amo" #asm_op "." #asm_type " %1, %2, %0" \
: "+A" (v->counter), "=r" (ret) \
: "r" (I) \
: "memory"); \
smp_mb(); \
return ret; \
} \
static __always_inline \
c_type atomic##prefix##_fetch_##op(c_type i, atomic##prefix##_t *v) \
{ \
register c_type ret; \
smp_mb(); \
__asm__ __volatile__ ( \
" amo" #asm_op "." #asm_type ".aqrl %1, %2, %0" \
: "+A" (v->counter), "=r" (ret) \
: "r" (I) \
: "memory"); \
smp_mb(); \
return ret; \
}
@@ -207,7 +201,6 @@ static __always_inline int atomic_fetch_add_unless(atomic_t *v, int a, int u)
{
int prev, rc;
smp_mb();
__asm__ __volatile__ (
"0: lr.w %[p], %[c]\n"
" beq %[p], %[u], 1f\n"
@@ -219,7 +212,6 @@ static __always_inline int atomic_fetch_add_unless(atomic_t *v, int a, int u)
: [p]"=&r" (prev), [rc]"=&r" (rc), [c]"+A" (v->counter)
: [a]"r" (a), [u]"r" (u)
: "memory");
smp_mb();
return prev;
}
#define atomic_fetch_add_unless atomic_fetch_add_unless
@@ -230,7 +222,6 @@ static __always_inline s64 atomic64_fetch_add_unless(atomic64_t *v, s64 a, s64 u
s64 prev;
long rc;
smp_mb();
__asm__ __volatile__ (
"0: lr.d %[p], %[c]\n"
" beq %[p], %[u], 1f\n"
@@ -242,7 +233,6 @@ static __always_inline s64 atomic64_fetch_add_unless(atomic64_t *v, s64 a, s64 u
: [p]"=&r" (prev), [rc]"=&r" (rc), [c]"+A" (v->counter)
: [a]"r" (a), [u]"r" (u)
: "memory");
smp_mb();
return prev;
}
#define atomic64_fetch_add_unless atomic64_fetch_add_unless
@@ -324,7 +314,6 @@ static __always_inline int atomic_sub_if_positive(atomic_t *v, int offset)
{
int prev, rc;
smp_mb();
__asm__ __volatile__ (
"0: lr.w %[p], %[c]\n"
" sub %[rc], %[p], %[o]\n"
@@ -336,7 +325,6 @@ static __always_inline int atomic_sub_if_positive(atomic_t *v, int offset)
: [p]"=&r" (prev), [rc]"=&r" (rc), [c]"+A" (v->counter)
: [o]"r" (offset)
: "memory");
smp_mb();
return prev - offset;
}
@@ -348,7 +336,6 @@ static __always_inline s64 atomic64_sub_if_positive(atomic64_t *v, s64 offset)
s64 prev;
long rc;
smp_mb();
__asm__ __volatile__ (
"0: lr.d %[p], %[c]\n"
" sub %[rc], %[p], %[o]\n"
@@ -360,7 +347,6 @@ static __always_inline s64 atomic64_sub_if_positive(atomic64_t *v, s64 offset)
: [p]"=&r" (prev), [rc]"=&r" (rc), [c]"+A" (v->counter)
: [o]"r" (offset)
: "memory");
smp_mb();
return prev - offset;
}

16
arch/riscv/include/asm/cmpxchg.h
View File

@@ -16,7 +16,6 @@
__typeof__(ptr) __ptr = (ptr); \
__typeof__(new) __new = (new); \
__typeof__(*(ptr)) __ret; \
smp_mb(); \
switch (size) { \
case 4: \
__asm__ __volatile__ ( \
@@ -35,7 +34,6 @@
default: \
BUILD_BUG(); \
} \
smp_mb(); \
__ret; \
})
@@ -51,7 +49,6 @@
__typeof__(ptr) __ptr = (ptr); \
__typeof__(new) __new = (new); \
__typeof__(*(ptr)) __ret; \
smp_mb(); \
switch (size) { \
case 4: \
__asm__ __volatile__ ( \
@@ -72,7 +69,6 @@
default: \
BUILD_BUG(); \
} \
smp_mb(); \
__ret; \
})
@@ -88,7 +84,6 @@
__typeof__(ptr) __ptr = (ptr); \
__typeof__(new) __new = (new); \
__typeof__(*(ptr)) __ret; \
smp_mb(); \
switch (size) { \
case 4: \
__asm__ __volatile__ ( \
@@ -109,7 +104,6 @@
default: \
BUILD_BUG(); \
} \
smp_mb(); \
__ret; \
})
@@ -125,7 +119,6 @@
__typeof__(ptr) __ptr = (ptr); \
__typeof__(new) __new = (new); \
__typeof__(*(ptr)) __ret; \
smp_mb(); \
switch (size) { \
case 4: \
__asm__ __volatile__ ( \
@@ -144,7 +137,6 @@
default: \
BUILD_BUG(); \
} \
smp_mb(); \
__ret; \
})
@@ -178,7 +170,6 @@
__typeof__(*(ptr)) __new = (new); \
__typeof__(*(ptr)) __ret; \
register unsigned int __rc; \
smp_mb(); \
switch (size) { \
case 4: \
__asm__ __volatile__ ( \
@@ -205,7 +196,6 @@
default: \
BUILD_BUG(); \
} \
smp_mb(); \
__ret; \
})
@@ -224,7 +214,6 @@
__typeof__(*(ptr)) __new = (new); \
__typeof__(*(ptr)) __ret; \
register unsigned int __rc; \
smp_mb(); \
switch (size) { \
case 4: \
__asm__ __volatile__ ( \
@@ -253,7 +242,6 @@
default: \
BUILD_BUG(); \
} \
smp_mb(); \
__ret; \
})
@@ -272,7 +260,6 @@
__typeof__(*(ptr)) __new = (new); \
__typeof__(*(ptr)) __ret; \
register unsigned int __rc; \
smp_mb(); \
switch (size) { \
case 4: \
__asm__ __volatile__ ( \
@@ -301,7 +288,6 @@
default: \
BUILD_BUG(); \
} \
smp_mb(); \
__ret; \
})
@@ -320,7 +306,6 @@
__typeof__(*(ptr)) __new = (new); \
__typeof__(*(ptr)) __ret; \
register unsigned int __rc; \
smp_mb(); \
switch (size) { \
case 4: \
__asm__ __volatile__ ( \
@@ -349,7 +334,6 @@
default: \
BUILD_BUG(); \
} \
smp_mb(); \
__ret; \
})

5
arch/riscv/include/asm/csr.h
View File

@@ -143,11 +143,6 @@
#define CSR_VTYPE 0xc21
#define CSR_VLENB 0xc22
#define CSR_SMIR 0x9c0
#define CSR_SMEL 0x9c1
#define CSR_SMEH 0x9c2
#define CSR_SMCIR 0x9c3
#ifdef CONFIG_RISCV_M_MODE
# define CSR_STATUS CSR_MSTATUS
# define CSR_IE CSR_MIE

3
arch/riscv/include/asm/smp.h
View File

@@ -51,6 +51,9 @@ void riscv_set_ipi_ops(struct riscv_ipi_ops *ops);
/* Clear IPI for current CPU */
void riscv_clear_ipi(void);
void crash_smp_send_stop(void);
bool smp_crash_stop_failed(void);
/* Secondary hart entry */
asmlinkage void smp_callin(void);

167
arch/riscv/include/asm/spinlock.h
View File

@@ -1,135 +1,92 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (C) 2015 Regents of the University of California
* Copyright (C) 2017 SiFive
*/
#ifndef _ASM_RISCV_SPINLOCK_H
#define _ASM_RISCV_SPINLOCK_H
#include <linux/kernel.h>
#include <asm/current.h>
#include <asm/fence.h>
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Simple spin lock operations. These provide no fairness guarantees.
* 'Generic' ticket-lock implementation.
*
* It relies on atomic_fetch_add() having well defined forward progress
* guarantees under contention. If your architecture cannot provide this, stick
* to a test-and-set lock.
*
* It also relies on atomic_fetch_add() being safe vs smp_store_release() on a
* sub-word of the value. This is generally true for anything LL/SC although
* you'd be hard pressed to find anything useful in architecture specifications
* about this. If your architecture cannot do this you might be better off with
* a test-and-set.
*
* It further assumes atomic_*_release() + atomic_*_acquire() is RCpc and hence
* uses atomic_fetch_add() which is RCsc to create an RCsc hot path, along with
* a full fence after the spin to upgrade the otherwise-RCpc
* atomic_cond_read_acquire().
*
* The implementation uses smp_cond_load_acquire() to spin, so if the
* architecture has WFE like instructions to sleep instead of poll for word
* modifications be sure to implement that (see ARM64 for example).
*
*/
/* FIXME: Replace this with a ticket lock, like MIPS. */
#ifndef __ASM_GENERIC_SPINLOCK_H
#define __ASM_GENERIC_SPINLOCK_H
#define arch_spin_is_locked(x) (READ_ONCE((x)->lock) != 0)
#include <linux/atomic.h>
#include <asm/spinlock_types.h>
static inline void arch_spin_unlock(arch_spinlock_t *lock)
static __always_inline void arch_spin_lock(arch_spinlock_t *lock)
{
smp_store_release(&lock->lock, 0);
u32 val = atomic_fetch_add(1<<16, lock);
u16 ticket = val >> 16;
if (ticket == (u16)val)
return;
/*
* atomic_cond_read_acquire() is RCpc, but rather than defining a
* custom cond_read_rcsc() here we just emit a full fence. We only
* need the prior reads before subsequent writes ordering from
* smb_mb(), but as atomic_cond_read_acquire() just emits reads and we
* have no outstanding writes due to the atomic_fetch_add() the extra
* orderings are free.
*/
atomic_cond_read_acquire(lock, ticket == (u16)VAL);
smp_mb();
}
static inline int arch_spin_trylock(arch_spinlock_t *lock)
static __always_inline bool arch_spin_trylock(arch_spinlock_t *lock)
{
int tmp = 1, busy;
u32 old = atomic_read(lock);
__asm__ __volatile__ (
" amoswap.w %0, %2, %1\n"
RISCV_ACQUIRE_BARRIER
: "=r" (busy), "+A" (lock->lock)
: "r" (tmp)
: "memory");
if ((old >> 16) != (old & 0xffff))
return false;
return !busy;
return atomic_try_cmpxchg(lock, &old, old + (1<<16)); /* SC, for RCsc */
}
static inline void arch_spin_lock(arch_spinlock_t *lock)
static __always_inline void arch_spin_unlock(arch_spinlock_t *lock)
{
while (1) {
if (arch_spin_is_locked(lock))
continue;
u16 *ptr = (u16 *)lock + IS_ENABLED(CONFIG_CPU_BIG_ENDIAN);
u32 val = atomic_read(lock);
if (arch_spin_trylock(lock))
break;
}
smp_store_release(ptr, (u16)val + 1);
}
/***********************************************************/
static inline void arch_read_lock(arch_rwlock_t *lock)
static __always_inline int arch_spin_is_locked(arch_spinlock_t *lock)
{
int tmp;
u32 val = atomic_read(lock);
__asm__ __volatile__(
"1: lr.w %1, %0\n"
" bltz %1, 1b\n"
" addi %1, %1, 1\n"
" sc.w %1, %1, %0\n"
" bnez %1, 1b\n"
RISCV_ACQUIRE_BARRIER
: "+A" (lock->lock), "=&r" (tmp)
:: "memory");
return ((val >> 16) != (val & 0xffff));
}
static inline void arch_write_lock(arch_rwlock_t *lock)
static __always_inline int arch_spin_is_contended(arch_spinlock_t *lock)
{
int tmp;
u32 val = atomic_read(lock);
__asm__ __volatile__(
"1: lr.w %1, %0\n"
" bnez %1, 1b\n"
" li %1, -1\n"
" sc.w %1, %1, %0\n"
" bnez %1, 1b\n"
RISCV_ACQUIRE_BARRIER
: "+A" (lock->lock), "=&r" (tmp)
:: "memory");
return (s16)((val >> 16) - (val & 0xffff)) > 1;
}
static inline int arch_read_trylock(arch_rwlock_t *lock)
static __always_inline int arch_spin_value_unlocked(arch_spinlock_t lock)
{
int busy;
__asm__ __volatile__(
"1: lr.w %1, %0\n"
" bltz %1, 1f\n"
" addi %1, %1, 1\n"
" sc.w %1, %1, %0\n"
" bnez %1, 1b\n"
RISCV_ACQUIRE_BARRIER
"1:\n"
: "+A" (lock->lock), "=&r" (busy)
:: "memory");
return !busy;
return !arch_spin_is_locked(&lock);
}
static inline int arch_write_trylock(arch_rwlock_t *lock)
{
int busy;
#include <asm/qrwlock.h>
__asm__ __volatile__(
"1: lr.w %1, %0\n"
" bnez %1, 1f\n"
" li %1, -1\n"
" sc.w %1, %1, %0\n"
" bnez %1, 1b\n"
RISCV_ACQUIRE_BARRIER
"1:\n"
: "+A" (lock->lock), "=&r" (busy)
:: "memory");
return !busy;
}
static inline void arch_read_unlock(arch_rwlock_t *lock)
{
__asm__ __volatile__(
RISCV_RELEASE_BARRIER
" amoadd.w x0, %1, %0\n"
: "+A" (lock->lock)
: "r" (-1)
: "memory");
}
static inline void arch_write_unlock(arch_rwlock_t *lock)
{
smp_store_release(&lock->lock, 0);
}
#endif /* _ASM_RISCV_SPINLOCK_H */
#endif /* __ASM_GENERIC_SPINLOCK_H */

34
arch/riscv/include/asm/spinlock_types.h
View File

@@ -1,25 +1,17 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __ASM_GENERIC_SPINLOCK_TYPES_H
#define __ASM_GENERIC_SPINLOCK_TYPES_H
#include <linux/types.h>
typedef atomic_t arch_spinlock_t;
/*
* Copyright (C) 2015 Regents of the University of California
* qrwlock_types depends on arch_spinlock_t, so we must typedef that before the
* include.
*/
#include <asm/qrwlock_types.h>
#ifndef _ASM_RISCV_SPINLOCK_TYPES_H
#define _ASM_RISCV_SPINLOCK_TYPES_H
#define __ARCH_SPIN_LOCK_UNLOCKED ATOMIC_INIT(0)
#ifndef __LINUX_SPINLOCK_TYPES_H
# error "please don't include this file directly"
#endif
typedef struct {
volatile unsigned int lock;
} arch_spinlock_t;
#define __ARCH_SPIN_LOCK_UNLOCKED { 0 }
typedef struct {
volatile unsigned int lock;
} arch_rwlock_t;
#define __ARCH_RW_LOCK_UNLOCKED { 0 }
#endif /* _ASM_RISCV_SPINLOCK_TYPES_H */
#endif /* __ASM_GENERIC_SPINLOCK_TYPES_H */

17
arch/riscv/include/asm/tlbflush.h
View File

@@ -14,7 +14,7 @@
static inline void local_flush_tlb_all(void)
{
#ifdef CONFIG_NO_SFENCE_VMA
csr_write(CSR_SMCIR, 1 << 26);
csr_write(0x9c3, 1 << 26);
#else
__asm__ __volatile__ ("sfence.vma" : : : "memory");
#endif
@@ -24,7 +24,7 @@ static inline void local_flush_tlb_all(void)
static inline void local_flush_tlb_page(unsigned long addr)
{
#ifdef CONFIG_NO_SFENCE_VMA
csr_write(CSR_SMCIR, 1 << 26);
csr_write(0x9c3, 1 << 26);
#else
__asm__ __volatile__ ("sfence.vma %0" : : "r" (addr) : "memory");
#endif
@@ -58,18 +58,7 @@ static inline void flush_tlb_range(struct vm_area_struct *vma,
static inline void flush_tlb_kernel_range(unsigned long start,
unsigned long end)
{
#ifdef CONFIG_NO_SFENCE_VMA
csr_write(CSR_SMCIR, 1 << 26);
#else
start &= PAGE_MASK;
end += PAGE_SIZE - 1;
end &= PAGE_MASK;
while (start < end) {
__asm__ __volatile__ ("sfence.vma %0" : : "r" (start) : "memory");
start += PAGE_SIZE;
}
#endif
flush_tlb_all();
}
#endif /* _ASM_RISCV_TLBFLUSH_H */

10
arch/riscv/include/uapi/asm/ptrace.h
View File

@@ -77,8 +77,18 @@ union __riscv_fp_state {
struct __riscv_q_ext_state q;
};
#ifdef CONFIG_VLEN_256
struct __riscv_vblen {
__uint128_t v[2];
};
#endif
struct __riscv_v_state {
#ifdef CONFIG_VLEN_256
struct __riscv_vblen v[32];
#else
__uint128_t v[32];
#endif
unsigned long vstart;
unsigned long vxsat;
unsigned long vxrm;

4
arch/riscv/kernel/asm-offsets.c
View File

@@ -104,7 +104,11 @@ void asm_offsets(void)
OFFSET(TASK_THREAD_VXRM, task_struct, thread.vstate.vxrm);
OFFSET(TASK_THREAD_VL, task_struct, thread.vstate.vl);
OFFSET(TASK_THREAD_VTYPE, task_struct, thread.vstate.vtype);
#ifdef CONFIG_VLEN_256
DEFINE(RISCV_VECTOR_VLENB, sizeof(struct __riscv_vblen));
#else
DEFINE(RISCV_VECTOR_VLENB, sizeof(__uint128_t));
#endif
DEFINE(PT_SIZE, sizeof(struct pt_regs));
OFFSET(PT_EPC, pt_regs, epc);

2
arch/riscv/kernel/entry.S
View File

@@ -251,7 +251,7 @@ ret_from_syscall_rejected:
andi t0, t0, _TIF_SYSCALL_WORK
bnez t0, handle_syscall_trace_exit
ret_from_exception:
ENTRY(ret_from_exception)
REG_L s0, PT_STATUS(sp)
csrc CSR_STATUS, SR_IE
#ifdef CONFIG_TRACE_IRQFLAGS

55
arch/riscv/kernel/machine_kexec.c
View File

@@ -14,6 +14,8 @@
#include <asm/set_memory.h> /* For set_memory_x() */
#include <linux/compiler.h> /* For unreachable() */
#include <linux/cpu.h> /* For cpu_down() */
#include <linux/interrupt.h>
#include <linux/irq.h>
/**
* kexec_image_info - Print received image details
@@ -135,19 +137,55 @@ void machine_shutdown(void)
#endif
}
/**
static void machine_kexec_mask_interrupts(void)
{
unsigned int i;
struct irq_desc *desc;
for_each_irq_desc(i, desc) {
struct irq_chip *chip;
int ret;
chip = irq_desc_get_chip(desc);
if (!chip)
continue;
/*
* First try to remove the active state. If this
* fails, try to EOI the interrupt.
*/
ret = irq_set_irqchip_state(i, IRQCHIP_STATE_ACTIVE, false);
if (ret && irqd_irq_inprogress(&desc->irq_data) &&
chip->irq_eoi)
chip->irq_eoi(&desc->irq_data);
if (chip->irq_mask)
chip->irq_mask(&desc->irq_data);
if (chip->irq_disable && !irqd_irq_disabled(&desc->irq_data))
chip->irq_disable(&desc->irq_data);
}
}
/*
* machine_crash_shutdown - Prepare to kexec after a kernel crash
*
* This function is called by crash_kexec just before machine_kexec
* below and its goal is similar to machine_shutdown, but in case of
* a kernel crash. Since we don't handle such cases yet, this function
* is empty.
* and its goal is to shutdown non-crashing cpus and save registers.
*/
void
machine_crash_shutdown(struct pt_regs *regs)
{
local_irq_disable();
#ifdef CONFIG_SMP
/* shutdown non-crashing cpus */
crash_smp_send_stop();
#endif
crash_save_cpu(regs, smp_processor_id());
machine_shutdown();
machine_kexec_mask_interrupts();
pr_info("Starting crashdump kernel...\n");
}
@@ -168,12 +206,17 @@ machine_kexec(struct kimage *image)
struct kimage_arch *internal = &image->arch;
unsigned long jump_addr = (unsigned long) image->start;
unsigned long first_ind_entry = (unsigned long) &image->head;
unsigned long this_cpu_id = smp_processor_id();
unsigned long this_cpu_id = __smp_processor_id();
unsigned long this_hart_id = cpuid_to_hartid_map(this_cpu_id);
unsigned long fdt_addr = internal->fdt_addr;
void *control_code_buffer = page_address(image->control_code_page);
riscv_kexec_method kexec_method = NULL;
#ifdef CONFIG_SMP
WARN(smp_crash_stop_failed(),
"Some CPUs may be stale, kdump will be unreliable.\n");
#endif
if (image->type != KEXEC_TYPE_CRASH)
kexec_method = control_code_buffer;
else

4
arch/riscv/kernel/perf_callchain.c
View File

@@ -75,13 +75,13 @@ void perf_callchain_user(struct perf_callchain_entry_ctx *entry,
fp = user_backtrace(entry, fp, 0);
}
bool fill_callchain(unsigned long pc, void *entry)
bool fill_callchain(unsigned long pc, unsigned long regs, void *entry)
{
return perf_callchain_store(entry, pc) == 0;
}
void notrace walk_stackframe(struct task_struct *task,
struct pt_regs *regs, bool (*fn)(unsigned long, void *), void *arg);
struct pt_regs *regs, bool (*fn)(unsigned long, unsigned long, void *), void *arg);
void perf_callchain_kernel(struct perf_callchain_entry_ctx *entry,
struct pt_regs *regs)
{

18
arch/riscv/kernel/probes/kprobes.c
View File

@@ -46,6 +46,21 @@ static void __kprobes arch_simulate_insn(struct kprobe *p, struct pt_regs *regs)
post_kprobe_handler(kcb, regs);
}
static bool __kprobes arch_check_kprobe(struct kprobe *p)
{
unsigned long tmp = (unsigned long)p->addr - p->offset;
unsigned long addr = (unsigned long)p->addr;
while (tmp <= addr) {
if (tmp == addr)
return true;
tmp += GET_INSN_LENGTH(*(u16 *)tmp);
}
return false;
}
int __kprobes arch_prepare_kprobe(struct kprobe *p)
{
unsigned long probe_addr = (unsigned long)p->addr;
@@ -56,6 +71,9 @@ int __kprobes arch_prepare_kprobe(struct kprobe *p)
return -EINVAL;
}
if (!arch_check_kprobe(p))
return -EILSEQ;
/* copy instruction */
p->opcode = le32_to_cpu(*p->addr);

85
arch/riscv/kernel/smp.c
View File

@@ -11,6 +11,7 @@
#include <linux/cpu.h>
#include <linux/interrupt.h>
#include <linux/module.h>
#include <linux/kexec.h>
#include <linux/profile.h>
#include <linux/smp.h>
#include <linux/sched.h>
@@ -26,6 +27,7 @@ enum ipi_message_type {
IPI_RESCHEDULE,
IPI_CALL_FUNC,
IPI_CPU_STOP,
IPI_CPU_CRASH_STOP,
IPI_IRQ_WORK,
IPI_MAX
};
@@ -85,6 +87,22 @@ static void ipi_stop(void)
wait_for_interrupt();
}
#ifdef CONFIG_KEXEC_CORE
static atomic_t waiting_for_crash_ipi = ATOMIC_INIT(0);
static void ipi_cpu_crash_stop(unsigned int cpu, struct pt_regs *regs)
{
crash_save_cpu(regs, cpu);
atomic_dec(&waiting_for_crash_ipi);
local_irq_disable();
while(1)
wait_for_interrupt();
}
#endif
static struct riscv_ipi_ops *ipi_ops;
void riscv_set_ipi_ops(struct riscv_ipi_ops *ops)
@@ -138,6 +156,7 @@ void arch_irq_work_raise(void)
void handle_IPI(struct pt_regs *regs)
{
unsigned int cpu = smp_processor_id();
struct pt_regs *old_regs = set_irq_regs(regs);
unsigned long *pending_ipis = &ipi_data[smp_processor_id()].bits;
unsigned long *stats = ipi_data[smp_processor_id()].stats;
@@ -171,6 +190,13 @@ void handle_IPI(struct pt_regs *regs)
ipi_stop();
}
if (ops & (1 << IPI_CPU_CRASH_STOP)) {
#ifdef CONFIG_KEXEC_CORE
ipi_cpu_crash_stop(cpu, get_irq_regs());
#endif
unreachable();
}
if (ops & (1 << IPI_IRQ_WORK)) {
stats[IPI_IRQ_WORK]++;
irq_work_run();
@@ -191,6 +217,7 @@ static const char * const ipi_names[] = {
[IPI_RESCHEDULE] = "Rescheduling interrupts",
[IPI_CALL_FUNC] = "Function call interrupts",
[IPI_CPU_STOP] = "CPU stop interrupts",
[IPI_CPU_CRASH_STOP] = "CPU stop (for crash dump) interrupts",
[IPI_IRQ_WORK] = "IRQ work interrupts",
};
@@ -242,6 +269,64 @@ void smp_send_stop(void)
cpumask_pr_args(cpu_online_mask));
}
#ifdef CONFIG_KEXEC_CORE
/*
* The number of CPUs online, not counting this CPU (which may not be
* fully online and so not counted in num_online_cpus()).
*/
static inline unsigned int num_other_online_cpus(void)
{
unsigned int this_cpu_online = cpu_online(smp_processor_id());
return num_online_cpus() - this_cpu_online;
}
void crash_smp_send_stop(void)
{
static int cpus_stopped;
cpumask_t mask;
unsigned long timeout;
/*
* This function can be called twice in panic path, but obviously
* we execute this only once.
*/
if (cpus_stopped)
return;
cpus_stopped = 1;
/*
* If this cpu is the only one alive at this point in time, online or
* not, there are no stop messages to be sent around, so just back out.
*/
if (num_other_online_cpus() == 0)
return;
cpumask_copy(&mask, cpu_online_mask);
cpumask_clear_cpu(smp_processor_id(), &mask);
atomic_set(&waiting_for_crash_ipi, num_other_online_cpus());
pr_crit("SMP: stopping secondary CPUs\n");
send_ipi_mask(&mask, IPI_CPU_CRASH_STOP);
/* Wait up to ten seconds for other CPUs to stop */
timeout = USEC_PER_SEC * 10;
while ((atomic_read(&waiting_for_crash_ipi) > 0) && timeout--)
udelay(1);
if (atomic_read(&waiting_for_crash_ipi) > 0)
pr_warn("SMP: failed to stop secondary CPUs %*pbl\n",
cpumask_pr_args(&mask));
}
bool smp_crash_stop_failed(void)
{
return (atomic_read(&waiting_for_crash_ipi) > 0);
}
#endif
void smp_send_reschedule(int cpu)
{
send_ipi_single(cpu, IPI_RESCHEDULE);

40
arch/riscv/kernel/stacktrace.c
View File

@@ -21,8 +21,10 @@ struct stackframe {
unsigned long ra;
};
extern asmlinkage void ret_from_exception(void);
void notrace walk_stackframe(struct task_struct *task, struct pt_regs *regs,
bool (*fn)(unsigned long, void *), void *arg)
bool (*fn)(unsigned long, unsigned long, void *), void *arg)
{
unsigned long fp, sp, pc;
@@ -46,7 +48,7 @@ void notrace walk_stackframe(struct task_struct *task, struct pt_regs *regs,
unsigned long low, high;
struct stackframe *frame;
if (unlikely(!__kernel_text_address(pc) || fn(pc, arg)))
if (unlikely(!__kernel_text_address(pc) || fn(pc, 0, arg)))
break;
/* Validate frame pointer */
@@ -57,16 +59,29 @@ void notrace walk_stackframe(struct task_struct *task, struct pt_regs *regs,
/* Unwind stack frame */
frame = (struct stackframe *)fp - 1;
sp = fp;
fp = frame->fp;
pc = ftrace_graph_ret_addr(current, NULL, frame->ra,
(unsigned long *)(fp - 8));
if (regs && (regs->epc == pc) && (frame->fp & 0x7)) {
fp = frame->ra;
pc = regs->ra;
} else {
fp = frame->fp;
pc = ftrace_graph_ret_addr(current, NULL, frame->ra,
&frame->ra);
if (pc == (unsigned long)ret_from_exception) {
if (unlikely(!__kernel_text_address(pc) || fn(pc, sp, arg)))
break;
pc = ((struct pt_regs *)sp)->epc;
fp = ((struct pt_regs *)sp)->s0;
}
}
}
}
#else /* !CONFIG_FRAME_POINTER */
void notrace walk_stackframe(struct task_struct *task,
struct pt_regs *regs, bool (*fn)(unsigned long, void *), void *arg)
struct pt_regs *regs, bool (*fn)(unsigned long, unsigned long, void *), void *arg)
{
unsigned long sp, pc;
unsigned long *ksp;
@@ -88,7 +103,7 @@ void notrace walk_stackframe(struct task_struct *task,
ksp = (unsigned long *)sp;
while (!kstack_end(ksp)) {
if (__kernel_text_address(pc) && unlikely(fn(pc, arg)))
if (__kernel_text_address(pc) && unlikely(fn(pc, 0, arg)))
break;
pc = (*ksp++) - 0x4;
}
@@ -97,11 +112,15 @@ void notrace walk_stackframe(struct task_struct *task,
#endif /* CONFIG_FRAME_POINTER */
static bool print_trace_address(unsigned long pc, void *arg)
static bool print_trace_address(unsigned long pc, unsigned long regs, void *arg)
{
const char *loglvl = arg;
print_ip_sym(loglvl, pc);
if (regs)
show_regs((struct pt_regs *)regs);
return false;
}
@@ -109,9 +128,10 @@ void show_stack(struct task_struct *task, unsigned long *sp, const char *loglvl)
{
pr_cont("Call Trace:\n");
walk_stackframe(task, NULL, print_trace_address, (void *)loglvl);
pr_cont("End Trace.\n");
}
static bool save_wchan(unsigned long pc, void *arg)
static bool save_wchan(unsigned long pc, unsigned long regs, void *arg)
{
if (!in_sched_functions(pc)) {
unsigned long *p = arg;
@@ -148,7 +168,7 @@ static bool __save_trace(unsigned long pc, void *arg, bool nosched)
return (trace->nr_entries >= trace->max_entries);
}
static bool save_trace(unsigned long pc, void *arg)
static bool save_trace(unsigned long pc, unsigned long regs, void *arg)
{
return __save_trace(pc, arg, false);
}

134
arch/riscv/kernel/vector.S
View File

@@ -46,6 +46,72 @@ ENTRY(__vstate_save)
csrr t0, CSR_VTYPE
sd t0, TASK_THREAD_VTYPE_V0(a0)
#ifdef CONFIG_VLEN_256
vsetvli t0, x0, e8,m1
V_ST v0, (a0)
addi a0, a0, RISCV_VECTOR_VLENB
V_ST v1, (a0)
addi a0, a0, RISCV_VECTOR_VLENB
V_ST v2, (a0)
addi a0, a0, RISCV_VECTOR_VLENB
V_ST v3, (a0)
addi a0, a0, RISCV_VECTOR_VLENB
V_ST v4, (a0)
addi a0, a0, RISCV_VECTOR_VLENB
V_ST v5, (a0)
addi a0, a0, RISCV_VECTOR_VLENB
V_ST v6, (a0)
addi a0, a0, RISCV_VECTOR_VLENB
V_ST v7, (a0)
addi a0, a0, RISCV_VECTOR_VLENB
V_ST v8, (a0)
addi a0, a0, RISCV_VECTOR_VLENB
V_ST v9, (a0)
addi a0, a0, RISCV_VECTOR_VLENB
V_ST v10, (a0)
addi a0, a0, RISCV_VECTOR_VLENB
V_ST v11, (a0)
addi a0, a0, RISCV_VECTOR_VLENB
V_ST v12, (a0)
addi a0, a0, RISCV_VECTOR_VLENB
V_ST v13, (a0)
addi a0, a0, RISCV_VECTOR_VLENB
V_ST v14, (a0)
addi a0, a0, RISCV_VECTOR_VLENB
V_ST v15, (a0)
addi a0, a0, RISCV_VECTOR_VLENB
V_ST v16, (a0)
addi a0, a0, RISCV_VECTOR_VLENB
V_ST v17, (a0)
addi a0, a0, RISCV_VECTOR_VLENB
V_ST v18, (a0)
addi a0, a0, RISCV_VECTOR_VLENB
V_ST v19, (a0)
addi a0, a0, RISCV_VECTOR_VLENB
V_ST v20, (a0)
addi a0, a0, RISCV_VECTOR_VLENB
V_ST v21, (a0)
addi a0, a0, RISCV_VECTOR_VLENB
V_ST v22, (a0)
addi a0, a0, RISCV_VECTOR_VLENB
V_ST v23, (a0)
addi a0, a0, RISCV_VECTOR_VLENB
V_ST v24, (a0)
addi a0, a0, RISCV_VECTOR_VLENB
V_ST v25, (a0)
addi a0, a0, RISCV_VECTOR_VLENB
V_ST v26, (a0)
addi a0, a0, RISCV_VECTOR_VLENB
V_ST v27, (a0)
addi a0, a0, RISCV_VECTOR_VLENB
V_ST v28, (a0)
addi a0, a0, RISCV_VECTOR_VLENB
V_ST v29, (a0)
addi a0, a0, RISCV_VECTOR_VLENB
V_ST v30, (a0)
addi a0, a0, RISCV_VECTOR_VLENB
V_ST v31, (a0)
#else
vsetvli t0, x0, e8,m8
V_ST v0, (a0)
addi a0, a0, RISCV_VECTOR_VLENB*8
@@ -54,6 +120,7 @@ ENTRY(__vstate_save)
V_ST v16, (a0)
addi a0, a0, RISCV_VECTOR_VLENB*8
V_ST v24, (a0)
#endif
csrc sstatus, t1
ret
@@ -67,6 +134,72 @@ ENTRY(__vstate_restore)
li t1, (SR_VS | SR_FS)
csrs sstatus, t1
#ifdef CONFIG_VLEN_256
vsetvli t0, x0, e8,m1
V_LD v0, (a0)
addi a0, a0, RISCV_VECTOR_VLENB
V_LD v1, (a0)
addi a0, a0, RISCV_VECTOR_VLENB
V_LD v2, (a0)
addi a0, a0, RISCV_VECTOR_VLENB
V_LD v3, (a0)
addi a0, a0, RISCV_VECTOR_VLENB
V_LD v4, (a0)
addi a0, a0, RISCV_VECTOR_VLENB
V_LD v5, (a0)
addi a0, a0, RISCV_VECTOR_VLENB
V_LD v6, (a0)
addi a0, a0, RISCV_VECTOR_VLENB
V_LD v7, (a0)
addi a0, a0, RISCV_VECTOR_VLENB
V_LD v8, (a0)
addi a0, a0, RISCV_VECTOR_VLENB
V_LD v9, (a0)
addi a0, a0, RISCV_VECTOR_VLENB
V_LD v10, (a0)
addi a0, a0, RISCV_VECTOR_VLENB
V_LD v11, (a0)
addi a0, a0, RISCV_VECTOR_VLENB
V_LD v12, (a0)
addi a0, a0, RISCV_VECTOR_VLENB
V_LD v13, (a0)
addi a0, a0, RISCV_VECTOR_VLENB
V_LD v14, (a0)
addi a0, a0, RISCV_VECTOR_VLENB
V_LD v15, (a0)
addi a0, a0, RISCV_VECTOR_VLENB
V_LD v16, (a0)
addi a0, a0, RISCV_VECTOR_VLENB
V_LD v17, (a0)
addi a0, a0, RISCV_VECTOR_VLENB
V_LD v18, (a0)
addi a0, a0, RISCV_VECTOR_VLENB
V_LD v19, (a0)
addi a0, a0, RISCV_VECTOR_VLENB
V_LD v20, (a0)
addi a0, a0, RISCV_VECTOR_VLENB
V_LD v21, (a0)
addi a0, a0, RISCV_VECTOR_VLENB
V_LD v22, (a0)
addi a0, a0, RISCV_VECTOR_VLENB
V_LD v23, (a0)
addi a0, a0, RISCV_VECTOR_VLENB
V_LD v24, (a0)
addi a0, a0, RISCV_VECTOR_VLENB
V_LD v25, (a0)
addi a0, a0, RISCV_VECTOR_VLENB
V_LD v26, (a0)
addi a0, a0, RISCV_VECTOR_VLENB
V_LD v27, (a0)
addi a0, a0, RISCV_VECTOR_VLENB
V_LD v28, (a0)
addi a0, a0, RISCV_VECTOR_VLENB
V_LD v29, (a0)
addi a0, a0, RISCV_VECTOR_VLENB
V_LD v30, (a0)
addi a0, a0, RISCV_VECTOR_VLENB
V_LD v31, (a0)
#else
vsetvli t0, x0, e8,m8
V_LD v0, (a0)
addi a0, a0, RISCV_VECTOR_VLENB*8
@@ -75,6 +208,7 @@ ENTRY(__vstate_restore)
V_LD v16, (a0)
addi a0, a0, RISCV_VECTOR_VLENB*8
V_LD v24, (a0)
#endif
mv a0, t2
ld t0, TASK_THREAD_VSTART_V0(a0)

6
arch/riscv/mm/cacheflush.c
View File

@@ -84,14 +84,16 @@ void flush_icache_pte(pte_t pte)
{
struct page *page = pte_page(pte);
if (!test_and_set_bit(PG_dcache_clean, &page->flags))
if (!test_bit(PG_dcache_clean, &page->flags)) {
flush_icache_all();
set_bit(PG_dcache_clean, &page->flags);
}
}
#endif /* CONFIG_MMU */
static bool thead_dma_init_flag = false;
#define sync_is() asm volatile (".long 0x01b0000b")
#define sync_is() asm volatile (".long 0x01a0000b")
void dma_wbinv_range(unsigned long start, unsigned long end)
{
register unsigned long i asm("a0") = start & ~(L1_CACHE_BYTES - 1);

36
arch/riscv/mm/context.c
View File

@@ -56,14 +56,48 @@ void switch_mm(struct mm_struct *prev, struct mm_struct *next,
*/
cpu = smp_processor_id();
cpumask_clear_cpu(cpu, mm_cpumask(prev));
cpumask_set_cpu(cpu, mm_cpumask(next));
#ifdef CONFIG_MMU
__asm__ __volatile__(
"jal t0,1f\n\t"
"1: \n\t"
"jal t0,2f\n\t"
"2: \n\t"
"jal t0,3f\n\t"
"3: \n\t"
"jal t0,4f\n\t"
"4: \n\t"
"jal t0,5f\n\t"
"5: \n\t"
"jal t0,6f\n\t"
"6: \n\t"
"jal t0,7f\n\t"
"7: \n\t"
"jal t0,8f\n\t"
"8: \n\t"
"jal t0,9f\n\t"
"9: \n\t"
"jal t0,10f\n\t"
"10: \n\t"
"jal t0,11f\n\t"
"11: \n\t"
"jal t0,12f\n\t"
"12: \n\t"
::: "memory", "t0");
check_and_switch_context(next, cpu);
asid = (next->context.asid.counter & SATP_ASID_MASK)
<< SATP_ASID_SHIFT;
local_flush_tlb_page(0);
/* flush utlb before setting satp */
__asm__ __volatile__(
"li t0, 0\n\t"
"sfence.vma t0, t0\n\t"
::: "memory", "t0");
csr_write(sptbr, virt_to_pfn(next->pgd) | SATP_MODE | asid);
#endif

68
arch/riscv/mm/tlbflush.c
View File

@@ -3,73 +3,6 @@
#include <linux/mm.h>
#include <linux/smp.h>
#include <linux/sched.h>
#define XUANTIE
#ifdef XUANTIE
#include <asm/mmu_context.h>
void flush_tlb_all(void)
{
#ifdef CONFIG_NO_SFENCE_VMA
csr_write(CSR_SMCIR, 1 << 26);
#else
__asm__ __volatile__ ("sfence.vma" : : : "memory");
#endif
}
void flush_tlb_mm(struct mm_struct *mm)
{
int newpid = cpu_asid(mm);
#ifdef CONFIG_NO_SFENCE_VMA
csr_write(CSR_SMCIR, (1 << 27) | newpid);
#else
__asm__ __volatile__ ("sfence.vma zero, %0"
:
: "r"(newpid)
: "memory");
#endif
}
void flush_tlb_page(struct vm_area_struct *vma, unsigned long addr)
{
int newpid = cpu_asid(vma->vm_mm);
#ifdef CONFIG_NO_SFENCE_VMA
csr_write(CSR_SMCIR, (1 << 27) | newpid);
#else
addr &= PAGE_MASK;
__asm__ __volatile__ ("sfence.vma %0, %1"
:
: "r"(addr), "r"(newpid)
: "memory");
#endif
}
void flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
unsigned long end)
{
unsigned long newpid = cpu_asid(vma->vm_mm);
#ifdef CONFIG_NO_SFENCE_VMA
csr_write(CSR_SMCIR, (1 << 27) | newpid);
#else
start &= PAGE_MASK;
end += PAGE_SIZE - 1;
end &= PAGE_MASK;
while (start < end) {
__asm__ __volatile__ ("sfence.vma %0, %1"
:
: "r"(start), "r"(newpid)
: "memory");
start += PAGE_SIZE;
}
#endif
}
#else
#include <asm/sbi.h>
void flush_tlb_all(void)
@@ -121,4 +54,3 @@ void flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
{
__sbi_tlb_flush_range(mm_cpumask(vma->vm_mm), start, end - start);
}
#endif

3
drivers/clk/thead/clk-light-fm.c
View File

@@ -5,6 +5,7 @@
#include <dt-bindings/clock/light-fm-ap-clock.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/init.h>
#include <linux/io.h>
@@ -640,6 +641,6 @@ static struct platform_driver light_clk_driver = {
};
module_platform_driver(light_clk_driver);
MODULE_AUTHOR("wei.liu <lw312886@alibaba-inc.com>");
MODULE_AUTHOR("wei.liu <lw312886@linux.alibaba.com>");
MODULE_DESCRIPTION("Thead Light Fullmask clock driver");
MODULE_LICENSE("GPL v2");

2
drivers/clk/thead/clk-light-mpw.c
View File

@@ -487,6 +487,6 @@ static struct platform_driver light_clk_driver = {
};
module_platform_driver(light_clk_driver);
MODULE_AUTHOR("fugang.duan <duanfugang.dfg@alibaba-inc.com>");
MODULE_AUTHOR("fugang.duan <duanfugang.dfg@linux.alibaba.com>");
MODULE_DESCRIPTION("Thead Light MPW clock driver");
MODULE_LICENSE("GPL v2");

2
drivers/clk/thead/gate/dspsys-gate.c
View File

@@ -104,6 +104,6 @@ static struct platform_driver light_dspsys_clk_driver = {
};
module_platform_driver(light_dspsys_clk_driver);
MODULE_AUTHOR("wei.liu <lw312886@alibaba-inc.com>");
MODULE_AUTHOR("wei.liu <lw312886@linux.alibaba.com>");
MODULE_DESCRIPTION("Thead Light Fullmask dspsys clock gate provider");
MODULE_LICENSE("GPL v2");

6
drivers/clk/thead/gate/visys-gate.c
View File

@@ -80,9 +80,9 @@ static int light_visys_clk_probe(struct platform_device *pdev)
gates[LIGHT_CLKGEN_MIPI_CSI0_CFG_CLK] = thead_gate_clk_register("clkgen_mipi_csi0_cfg_clk", NULL,
visys_regmap, 0xa0, 8, GATE_NOT_SHARED, NULL, dev);
gates[LIGHT_CLKGEN_MIPI_CSI1_CFG_CLK] = thead_gate_clk_register("clkgen_mipi_csi1_cfg_clk", NULL,
visys_regmap, 0xa0, 7, GATE_NOT_SHARED, NULL, dev);
gates[LIGHT_CLKGEN_MIPI_CSI2_CFG_CLK] = thead_gate_clk_register("clkgen_mipi_csi2_cfg_clk", NULL,
visys_regmap, 0xa0, 6, GATE_NOT_SHARED, NULL, dev);
gates[LIGHT_CLKGEN_MIPI_CSI2_CFG_CLK] = thead_gate_clk_register("clkgen_mipi_csi2_cfg_clk", NULL,
visys_regmap, 0xa0, 7, GATE_NOT_SHARED, NULL, dev);
gates[LIGHT_CLKGEN_DW200_CLK_VSE] = thead_gate_clk_register("clkgen_dw200_clk_vse", NULL,
visys_regmap, 0xa0, 5, GATE_NOT_SHARED, NULL, dev);
gates[LIGHT_CLKGEN_DW200_CLK_DWE] = thead_gate_clk_register("clkgen_dw200_clk_dwe", NULL,
@@ -139,6 +139,6 @@ static struct platform_driver light_visys_clk_driver = {
};
module_platform_driver(light_visys_clk_driver);
MODULE_AUTHOR("wei.liu <lw312886@alibaba-inc.com>");
MODULE_AUTHOR("wei.liu <lw312886@linux.alibaba.com>");
MODULE_DESCRIPTION("Thead Light Fullmask visys clock gate provider");
MODULE_LICENSE("GPL v2");

2
drivers/clk/thead/gate/vosys-gate.c
View File

@@ -106,6 +106,6 @@ static struct platform_driver light_vosys_clk_driver = {
};
module_platform_driver(light_vosys_clk_driver);
MODULE_AUTHOR("wei.liu <lw312886@alibaba-inc.com>");
MODULE_AUTHOR("wei.liu <lw312886@linux.alibaba.com>");
MODULE_DESCRIPTION("Thead Light Fullmask vosys clock gate provider");
MODULE_LICENSE("GPL v2");

2
drivers/clk/thead/gate/vpsys-gate.c
View File

@@ -89,6 +89,6 @@ static struct platform_driver light_vpsys_clk_driver = {
};
module_platform_driver(light_vpsys_clk_driver);
MODULE_AUTHOR("wei.liu <lw312886@alibaba-inc.com>");
MODULE_AUTHOR("wei.liu <lw312886@linux.alibaba.com>");
MODULE_DESCRIPTION("Thead Light Fullmask vpsys clock gate provider");
MODULE_LICENSE("GPL v2");

92
drivers/cpufreq/light-mpw-cpufreq.c
View File

@@ -13,9 +13,15 @@
#include <linux/of_address.h>
#include <linux/pm_opp.h>
#include <linux/platform_device.h>
#include <linux/reboot.h>
#include <linux/regulator/consumer.h>
#include <linux/suspend.h>
#include <linux/clk-provider.h>
#include <linux/smp.h>
static DEFINE_MUTEX(cpufreq_lock);
bool cpufreq_denied = false;
struct regulator *dvdd_cpu_reg;
struct regulator *dvddm_cpu_reg;
@@ -62,6 +68,13 @@ static int light_set_target(struct cpufreq_policy *policy, unsigned int index)
u32 val;
u32 re_modify_bus_freq = 0;
mutex_lock(&cpufreq_lock);
if (cpufreq_denied) {
dev_emerg(cpu_dev, "Denied to set cpu frequency temporarily on reboot\n");
mutex_unlock(&cpufreq_lock);
return 0;
}
new_freq = freq_table[index].frequency;
freq_hz = new_freq * 1000;
old_freq = policy->cur;
@@ -69,6 +82,7 @@ static int light_set_target(struct cpufreq_policy *policy, unsigned int index)
opp = dev_pm_opp_find_freq_ceil(cpu_dev, &freq_hz);
if (IS_ERR(opp)) {
dev_err(cpu_dev, "failed to find OPP for %ld\n", freq_hz);
mutex_unlock(&cpufreq_lock);
return PTR_ERR(opp);
}
@@ -78,6 +92,7 @@ static int light_set_target(struct cpufreq_policy *policy, unsigned int index)
volt_old = regulator_get_voltage(dvdd_cpu_reg);
if (volt_old < 0) {
dev_err(cpu_dev, "failed to get cpu voltage\n");
mutex_unlock(&cpufreq_lock);
return volt_old;
}
@@ -113,12 +128,14 @@ static int light_set_target(struct cpufreq_policy *policy, unsigned int index)
ret = regulator_set_voltage_tol(dvddm_cpu_reg, light_dvddm_volt[index], 0);
if (ret) {
dev_err(cpu_dev, "failed to scale vddsoc up: %d\n", ret);
mutex_unlock(&cpufreq_lock);
return ret;
}
ret = regulator_set_voltage_tol(dvdd_cpu_reg, volt, 0);
if (ret) {
dev_err(cpu_dev,
"failed to scale vddarm up: %d\n", ret);
mutex_unlock(&cpufreq_lock);
return ret;
}
}
@@ -150,6 +167,7 @@ static int light_set_target(struct cpufreq_policy *policy, unsigned int index)
ret1 = regulator_set_voltage_tol(dvdd_cpu_reg, volt_old, 0);
if (ret1)
dev_err(cpu_dev, "failed to restore dvdd_cpu voltage: %d\n", ret1);
mutex_unlock(&cpufreq_lock);
return ret;
}
@@ -177,6 +195,8 @@ static int light_set_target(struct cpufreq_policy *policy, unsigned int index)
udelay(1);
}
mutex_unlock(&cpufreq_lock);
return 0;
}
@@ -191,6 +211,20 @@ static int light_cpufreq_init(struct cpufreq_policy *policy)
return 0;
}
static int light_cpufreq_reboot_notifier(struct notifier_block *this,
unsigned long event, void *ptr)
{
mutex_lock(&cpufreq_lock);
cpufreq_denied = true;
mutex_unlock(&cpufreq_lock);
return NOTIFY_DONE;
}
static struct notifier_block cpufreq_reboot_notifier = {
.notifier_call = light_cpufreq_reboot_notifier,
};
static struct cpufreq_driver light_cpufreq_driver = {
.flags = CPUFREQ_NEED_INITIAL_FREQ_CHECK |
CPUFREQ_IS_COOLING_DEV,
@@ -224,6 +258,53 @@ static struct notifier_block light_cpufreq_pm_notifier = {
.notifier_call = light_cpufreq_pm_notify,
};
/*
* Set CPU PLL1's frequency as minimum on panic
*/
static int panic_cpufreq_notifier_call(struct notifier_block *nb,
unsigned long action, void *data)
{
int cpu = smp_processor_id();
struct cpufreq_policy *policy = cpufreq_cpu_get(cpu);
u32 val = readl(ap_sys_reg);
pr_info("enter panic_cpufreq_notifier_call\n");
/*
* set CPU PLL1's frequency as minimum to compatible voltage
* becarefull if the PLL1 is serving the cpu core, swith to PLL0 first
*/
if (strcmp(__clk_get_name(clk_get_parent(clks[LIGHT_C910_CCLK].clk)),
__clk_get_name(clks[LIGHT_C910_CCLK_I0].clk))) {
pr_debug("[%s,%d]\n", __func__, __LINE__);
clk_prepare_enable(clks[LIGHT_CPU_PLL0_FOUTPOSTDIV].clk);
clk_set_rate(clks[LIGHT_CPU_PLL0_FOUTPOSTDIV].clk, policy->min * 1000);
udelay(1);
clk_set_parent(clks[LIGHT_C910_CCLK].clk, clks[LIGHT_C910_CCLK_I0].clk);
pr_debug("[%s,%d]\n", __func__, __LINE__);
}
pr_debug("[%s,%d]\n", __func__, __LINE__);
/*
* since the clk driver will use PLL1 as the default clock source,
* in order to compatible voltage which is unpredictable we should
* set the CPU PLL1's frequency as minimum in advance, otherwise the
* system may crash in crash kernel stage.
*/
clk_prepare_enable(clks[LIGHT_CPU_PLL1_FOUTPOSTDIV].clk);
clk_set_rate(clks[LIGHT_CPU_PLL1_FOUTPOSTDIV].clk, policy->min * 1000);
udelay(1);
pr_info("finish to execute cpufreq notifier callback on panic\n");
return 0;
}
static struct notifier_block panic_cpufreq_notifier = {
.notifier_call = panic_cpufreq_notifier_call,
};
static int light_cpufreq_probe(struct platform_device *pdev)
{
struct device_node *np;
@@ -341,6 +422,15 @@ soc_opp_out:
of_node_put(np);
ret = atomic_notifier_chain_register(&panic_notifier_list,
&panic_cpufreq_notifier);
if (ret) {
pr_err("unable to register notifier(%d)\n", ret);
goto free_freq_table;
}
register_reboot_notifier(&cpufreq_reboot_notifier);
dev_info(cpu_dev, "finish to register cpufreq driver\n");
return 0;
@@ -391,6 +481,6 @@ static struct platform_driver light_cpufreq_platdrv = {
module_platform_driver(light_cpufreq_platdrv);
MODULE_ALIAS("platform:light-cpufreq");
MODULE_AUTHOR("fugang.duan <duanfugang.dfg@alibaba-inc.com>");
MODULE_AUTHOR("fugang.duan <duanfugang.dfg@linux.alibaba.com>");
MODULE_DESCRIPTION("Thead Light cpufreq driver");
MODULE_LICENSE("GPL v2");

13
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
View File

@@ -82,37 +82,49 @@ axi_chan_iowrite64(struct axi_dma_chan *chan, u32 reg, u64 val)
static inline void axi_dma_disable(struct axi_dma_chip *chip)
{
u32 val;
unsigned long flags;
spin_lock_irqsave(&chip->lock, flags);
val = axi_dma_ioread32(chip, DMAC_CFG);
val &= ~DMAC_EN_MASK;
axi_dma_iowrite32(chip, DMAC_CFG, val);
spin_unlock_irqrestore(&chip->lock, flags);
}
static inline void axi_dma_enable(struct axi_dma_chip *chip)
{
u32 val;
unsigned long flags;
spin_lock_irqsave(&chip->lock, flags);
val = axi_dma_ioread32(chip, DMAC_CFG);
val |= DMAC_EN_MASK;
axi_dma_iowrite32(chip, DMAC_CFG, val);
spin_unlock_irqrestore(&chip->lock, flags);
}
static inline void axi_dma_irq_disable(struct axi_dma_chip *chip)
{
u32 val;
unsigned long flags;
spin_lock_irqsave(&chip->lock, flags);
val = axi_dma_ioread32(chip, DMAC_CFG);
val &= ~INT_EN_MASK;
axi_dma_iowrite32(chip, DMAC_CFG, val);
spin_unlock_irqrestore(&chip->lock, flags);
}
static inline void axi_dma_irq_enable(struct axi_dma_chip *chip)
{
u32 val;
unsigned long flags;
spin_lock_irqsave(&chip->lock, flags);
val = axi_dma_ioread32(chip, DMAC_CFG);
val |= INT_EN_MASK;
axi_dma_iowrite32(chip, DMAC_CFG, val);
spin_unlock_irqrestore(&chip->lock, flags);
}
static inline void axi_chan_irq_disable(struct axi_dma_chan *chan, u32 irq_mask)
@@ -1348,6 +1360,7 @@ static int dw_probe(struct platform_device *pdev)
chip->dev = &pdev->dev;
chip->dw->hdata = hdata;
spin_lock_init(&chip->lock);
chip->irq = platform_get_irq(pdev, 0);
if (chip->irq < 0)
return chip->irq;

1
drivers/dma/dw-axi-dmac/dw-axi-dmac.h
View File

@@ -70,6 +70,7 @@ struct axi_dma_chip {
struct clk *core_clk;
struct clk *cfgr_clk;
struct dw_axi_dma *dw;
spinlock_t lock;
};
/* LLI == Linked List Item */

2
drivers/firmware/thead/light_aon.c
View File

@@ -239,6 +239,6 @@ static struct platform_driver light_aon_driver = {
};
builtin_platform_driver(light_aon_driver);
MODULE_AUTHOR("fugang.duan <duanfugang.dfg@alibaba-inc.com>");
MODULE_AUTHOR("fugang.duan <duanfugang.dfg@linux.alibaba.com>");
MODULE_DESCRIPTION("Thead Light firmware protocol driver");
MODULE_LICENSE("GPL v2");

2
drivers/firmware/thead/light_aon_pd.c
View File

@@ -412,6 +412,6 @@ static struct platform_driver light_aon_pd_driver = {
};
builtin_platform_driver(light_aon_pd_driver);
MODULE_AUTHOR("fugang.duan <duanfugang.dfg@alibaba-inc.com>");
MODULE_AUTHOR("fugang.duan <duanfugang.dfg@linux.alibaba.com>");
MODULE_DESCRIPTION("Thead Light firmware protocol driver");
MODULE_LICENSE("GPL v2");

2
drivers/firmware/thead/light_aon_test.c
View File

@@ -158,6 +158,6 @@ static struct platform_driver light_aon_driver = {
};
module_platform_driver(light_aon_driver);
MODULE_AUTHOR("fugang.duan <duanfugang.dfg@alibaba-inc.com>");
MODULE_AUTHOR("fugang.duan <duanfugang.dfg@linux.alibaba.com>");
MODULE_DESCRIPTION("Thead Light firmware protocol test driver");
MODULE_LICENSE("GPL v2");

73
drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
View File

@@ -49,6 +49,10 @@
#define HDMI14_MAX_TMDSCLK 340000000
#define HDMI_DDC_CHECK_MAX_RETRIES 100
#define HDMI_DDC_CHECK_NORMAL 2
#define HDMI_SCRAMBLING_RETRIES 20
enum hdmi_datamap {
RGB444_8B = 0x01,
RGB444_10B = 0x03,
@@ -1865,6 +1869,45 @@ static void hdmi_config_drm_infoframe(struct dw_hdmi *hdmi,
HDMI_FC_PACKET_TX_EN_DRM_MASK, HDMI_FC_PACKET_TX_EN);
}
static bool dw_hdmi_ddc_debounce(struct dw_hdmi *hdmi)
{
u8 config, val, orig;
int ret, count = 0, check = 0;
drm_scdc_readb(hdmi->ddc, SCDC_TMDS_CONFIG, &orig);
do {
drm_scdc_readb(hdmi->ddc, SCDC_TMDS_CONFIG, &config);
if (count & 0x1)
config |= SCDC_SCRAMBLING_ENABLE;
else
config &= ~SCDC_SCRAMBLING_ENABLE;
drm_scdc_writeb(hdmi->ddc, SCDC_TMDS_CONFIG, config);
drm_scdc_readb(hdmi->ddc, SCDC_TMDS_CONFIG, &val);
if (val != config)
check = 0;
else
check++;
if (check >= HDMI_DDC_CHECK_NORMAL) {
ret = true;
goto out;
}
if (count++ >= HDMI_DDC_CHECK_MAX_RETRIES) {
dev_err(hdmi->dev, "exceed max retries:%d\n", HDMI_DDC_CHECK_MAX_RETRIES);
ret = false;
goto out;
}
usleep_range(10000, 15000);
} while (1);
out:
drm_scdc_writeb(hdmi->ddc, SCDC_TMDS_CONFIG, orig);
return ret;
}
static void hdmi_av_composer(struct dw_hdmi *hdmi,
const struct drm_display_info *display,
const struct drm_display_mode *mode)
@@ -1983,7 +2026,8 @@ static void hdmi_av_composer(struct dw_hdmi *hdmi,
* Source Devices compliant shall set the
* Source Version = 1.
*/
mdelay(60);
dw_hdmi_ddc_debounce(hdmi);
drm_scdc_readb(hdmi->ddc, SCDC_SINK_VERSION,
&bytes);
drm_scdc_writeb(hdmi->ddc, SCDC_SOURCE_VERSION,
@@ -2137,6 +2181,28 @@ static void hdmi_disable_overflow_interrupts(struct dw_hdmi *hdmi)
HDMI_IH_MUTE_FC_STAT2);
}
static void hdmi_check_scrambling_status(struct dw_hdmi *hdmi,
const struct drm_display_info *display)
{
int count = 0;
if (!dw_hdmi_support_scdc(hdmi, display))
return;
do {
if (drm_scdc_get_scrambling_status(hdmi->ddc))
break;
/* polling scrambling_status up to a maximum of 200ms */
if (count++ >= HDMI_SCRAMBLING_RETRIES) {
dev_err(hdmi->dev,
"TMDS link of scrambling_status is not ready\n");
break;
}
usleep_range(10000, 11000);
} while (1);
}
static int dw_hdmi_setup(struct dw_hdmi *hdmi,
const struct drm_connector *connector,
const struct drm_display_mode *mode)
@@ -2223,6 +2289,7 @@ static int dw_hdmi_setup(struct dw_hdmi *hdmi,
hdmi_video_csc(hdmi);
hdmi_video_sample(hdmi);
hdmi_tx_hdcp_config(hdmi);
hdmi_check_scrambling_status(hdmi, &connector->display_info);
dw_hdmi_clear_overflow(hdmi);
@@ -2960,6 +3027,8 @@ static irqreturn_t dw_hdmi_hardirq(int irq, void *dev_id)
intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0);
if (intr_stat) {
hdmi_writeb(hdmi, intr_stat, HDMI_IH_PHY_STAT0);
hdmi_writeb(hdmi, 0xff, HDMI_PHY_MASK0);
hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0);
return IRQ_WAKE_THREAD;
}
@@ -3000,6 +3069,7 @@ static irqreturn_t dw_hdmi_irq(int irq, void *dev_id)
struct dw_hdmi *hdmi = dev_id;
u8 intr_stat, phy_int_pol, phy_pol_mask, phy_stat;
msleep(50);
intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0);
phy_int_pol = hdmi_readb(hdmi, HDMI_PHY_POL0);
phy_stat = hdmi_readb(hdmi, HDMI_PHY_STAT0);
@@ -3057,6 +3127,7 @@ static irqreturn_t dw_hdmi_irq(int irq, void *dev_id)
hdmi_writeb(hdmi, intr_stat, HDMI_IH_PHY_STAT0);
hdmi_writeb(hdmi, ~(HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE),
HDMI_IH_MUTE_PHY_STAT0);
hdmi_writeb(hdmi, (u8)~(HDMI_PHY_HPD | HDMI_PHY_RX_SENSE), HDMI_PHY_MASK0);
return IRQ_HANDLED;
}

19
drivers/gpu/drm/panel/Kconfig
View File

@@ -500,4 +500,23 @@ config DRM_PANEL_XINPENG_XPP055C272
Say Y here if you want to enable support for the Xinpeng
XPP055C272 controller for 720x1280 LCD panels with MIPI/RGB/SPI
system interfaces.
config DRM_PANEL_ILI9881D
tristate "ILI9881D-based panels"
depends on OF
depends on DRM_MIPI_DSI
depends on BACKLIGHT_CLASS_DEVICE
help
Say Y if you want to enable support for panels based on the
ILI9881d controller.
config DRM_PANEL_HX8394
tristate "HX8394-based panels"
depends on OF
depends on DRM_MIPI_DSI
depends on BACKLIGHT_CLASS_DEVICE
help
Say Y if you want to enable support for panels based on the
HX8394 controller.
endmenu

2
drivers/gpu/drm/panel/Makefile
View File

@@ -53,3 +53,5 @@ obj-$(CONFIG_DRM_PANEL_TPO_TPG110) += panel-tpo-tpg110.o
obj-$(CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA) += panel-truly-nt35597.o
obj-$(CONFIG_DRM_PANEL_VISIONOX_RM69299) += panel-visionox-rm69299.o
obj-$(CONFIG_DRM_PANEL_XINPENG_XPP055C272) += panel-xinpeng-xpp055c272.o
obj-$(CONFIG_DRM_PANEL_ILI9881D) += panel-ili9881d.o
obj-$(CONFIG_DRM_PANEL_HX8394) += panel-himax8394.o

429
drivers/gpu/drm/panel/panel-himax8394.c Normal file
View File

@@ -0,0 +1,429 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Diiver for panels based on Himax HX8394 controller
* Copyright (c) 2023, Alibaba-inc Co., Ltd
*
*/
#include <linux/delay.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/gpio/consumer.h>
#include <linux/regulator/consumer.h>
#include <drm/drm_device.h>
#include <drm/drm_mipi_dsi.h>
#include <drm/drm_modes.h>
#include <drm/drm_panel.h>
#include <video/mipi_display.h>
struct hx8394_panel_cmd {
char cmdlen;
char cmddata[0x40];
};
struct hx8394_panel_desc {
const struct drm_display_mode *display_mode;
unsigned long mode_flags;
enum mipi_dsi_pixel_format format;
unsigned int lanes;
const struct hx8394_panel_cmd *on_cmds;
unsigned int on_cmds_num;
};
struct panel_info {
struct drm_panel base;
struct mipi_dsi_device *link;
const struct hx8394_panel_desc *desc;
struct gpio_desc *reset;
struct regulator *hsvcc;
struct regulator *vspn3v3;
bool prepared;
bool enabled;
};
static inline struct panel_info *to_panel_info(struct drm_panel *panel)
{
return container_of(panel, struct panel_info, base);
}
static int hx8394_send_mipi_cmds(struct drm_panel *panel, const struct hx8394_panel_cmd *cmds)
{
struct panel_info *pinfo = to_panel_info(panel);
unsigned int i = 0;
int err;
for (i = 0; i < pinfo->desc->on_cmds_num; i++) {
err = mipi_dsi_dcs_write_buffer(pinfo->link, &(cmds[i].cmddata[0]), cmds[i].cmdlen);
if (err < 0)
return err;
}
return 0;
}
static int hx8394_panel_disable(struct drm_panel *panel)
{
struct panel_info *pinfo = to_panel_info(panel);
int err;
if (!pinfo->enabled)
return 0;
err = mipi_dsi_dcs_set_display_off(pinfo->link);
if (err < 0) {
dev_err(panel->dev, "failed to set display off: %d\n", err);
return err;
}
pinfo->enabled = false;
return 0;
}
static int hx8394_panel_unprepare(struct drm_panel *panel)
{
struct panel_info *pinfo = to_panel_info(panel);
int err;
if (!pinfo->prepared)
return 0;
err = mipi_dsi_dcs_set_display_off(pinfo->link);
if (err < 0)
dev_err(panel->dev, "failed to set display off: %d\n", err);
err = mipi_dsi_dcs_enter_sleep_mode(pinfo->link);
if (err < 0)
dev_err(panel->dev, "failed to enter sleep mode: %d\n", err);
/* sleep_mode_delay: 1ms - 2ms */
usleep_range(1000, 2000);
gpiod_set_value(pinfo->reset, 1);
regulator_disable(pinfo->hsvcc);
regulator_disable(pinfo->vspn3v3);
pinfo->prepared = false;
return 0;
}
static int hx8394_panel_prepare(struct drm_panel *panel)
{
struct panel_info *pinfo = to_panel_info(panel);
int ret;
if (pinfo->prepared)
return 0;
gpiod_set_value(pinfo->reset, 1);
/* Power the panel */
ret = regulator_enable(pinfo->hsvcc);
if (ret) {
dev_err(pinfo->base.dev, "Failed to enable hsvcc supply: %d\n", ret);
return ret;
}
usleep_range(1000, 2000);
ret = regulator_enable(pinfo->vspn3v3);
if (ret) {
dev_err(pinfo->base.dev, "Failed to enable vspn3v3 supply: %d\n", ret);
goto fail;
}
usleep_range(5000, 6000);
gpiod_set_value(pinfo->reset, 0);
msleep(180);
pinfo->prepared = true;
return 0;
fail:
gpiod_set_value(pinfo->reset, 1);
regulator_disable(pinfo->hsvcc);
return ret;
}
static int hx8394_read_id(struct mipi_dsi_device *dsi, u8 *id1)
{
int ret;
ret = mipi_dsi_dcs_read(dsi, 0xDA, id1, 1);
if (ret < 0) {
dev_err(&dsi->dev, "could not read ID1\n");
return ret;
}
dev_info(&dsi->dev, "ID1 : 0x%02x\n", *id1);
return 0;
}
static int hx8394_panel_enable(struct drm_panel *panel)
{
struct panel_info *pinfo = to_panel_info(panel);
int ret;
u8 id1;
if (pinfo->enabled)
return 0;
ret = hx8394_read_id(pinfo->link, &id1);
if (ret < 0)
dev_info(panel->dev, "No LCD connected,pls check your hardware! ret:%d\n", ret);
/* send init code */
ret = hx8394_send_mipi_cmds(panel, pinfo->desc->on_cmds);
if (ret < 0) {
dev_err(panel->dev, "failed to send DCS Init Code: %d\n", ret);
return ret;
}
ret = mipi_dsi_dcs_exit_sleep_mode(pinfo->link);
if (ret < 0) {
dev_err(panel->dev, "failed to exit sleep mode: %d\n", ret);
return ret;
}
msleep(120);
ret = mipi_dsi_dcs_set_display_on(pinfo->link);
if (ret < 0) {
dev_err(panel->dev, "failed to set display on: %d\n", ret);
return ret;
}
pinfo->enabled = true;
return 0;
}
static int hx8394_panel_get_modes(struct drm_panel *panel,
struct drm_connector *connector)
{
struct panel_info *pinfo = to_panel_info(panel);
const struct drm_display_mode *m = pinfo->desc->display_mode;
struct drm_display_mode *mode;
mode = drm_mode_duplicate(connector->dev, m);
if (!mode) {
dev_err(pinfo->base.dev, "failed to add mode %ux%u@%u\n",
m->hdisplay, m->vdisplay, drm_mode_vrefresh(m));
return -ENOMEM;
}
drm_mode_set_name(mode);
mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
drm_mode_probed_add(connector, mode);
connector->display_info.width_mm = mode->width_mm;
connector->display_info.height_mm = mode->height_mm;
return 1;
}
static const struct drm_panel_funcs panel_funcs = {
.disable = hx8394_panel_disable,
.unprepare = hx8394_panel_unprepare,
.prepare = hx8394_panel_prepare,
.enable = hx8394_panel_enable,
.get_modes = hx8394_panel_get_modes,
};
static const struct drm_display_mode hx8394_default_mode = {
.clock = 76000,
.hdisplay = 720,
.hsync_start = 720 + 45,
.hsync_end = 720 + 45 + 8,
.htotal = 720 + 45 + 8 + 45,
.vdisplay = 1280,
.vsync_start = 1280 + 16,
.vsync_end = 1280 + 16 + 8,
.vtotal = 1280 + 16 + 8 + 16,
.width_mm = 62,
.height_mm = 110,
.flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
};
static const struct hx8394_panel_cmd hx8394_on_cmds[] = {
{ .cmdlen = 4, .cmddata = {0xB9, 0xFF, 0x83, 0x94} },
{ .cmdlen = 11, .cmddata = {0xB1, 0x48, 0x0A, 0x6A, 0x09, 0x33, 0x54,
0x71, 0x71, 0x2E, 0x45} },
{ .cmdlen = 7, .cmddata = {0xBA, 0x63, 0x03, 0x68, 0x6B, 0xB2, 0xC0} },
{ .cmdlen = 7, .cmddata = {0xB2, 0x00, 0x80, 0x64, 0x0C, 0x06, 0x2F} },
{ .cmdlen = 22, .cmddata = {0xB4, 0x1C, 0x78, 0x1C, 0x78, 0x1C, 0x78, 0x01,
0x0C, 0x86, 0x75, 0x00, 0x3F, 0x1C, 0x78, 0x1C,
0x78, 0x1C, 0x78, 0x01, 0x0C, 0x86} },
{ .cmdlen = 34, .cmddata = {0xD3, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08,
0x08, 0x32, 0x10, 0x05, 0x00, 0x05, 0x32, 0x13,
0xC1, 0x00, 0x01, 0x32, 0x10, 0x08, 0x00, 0x00,
0x37, 0x03, 0x07, 0x07, 0x37, 0x05, 0x05, 0x37,
0x0C, 0x40} },
{ .cmdlen = 45, .cmddata = {0xD5, 0x18, 0x18, 0x18, 0x18, 0x22, 0x23, 0x20,
0x21, 0x04, 0x05, 0x06, 0x07, 0x00, 0x01, 0x02,
0x03, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
0x18, 0x19, 0x19, 0x19, 0x19} },
{ .cmdlen = 45, .cmddata = {0xD6, 0x18, 0x18, 0x19, 0x19, 0x21, 0x20, 0x23,
0x22, 0x03, 0x02, 0x01, 0x00, 0x07, 0x06, 0x05,
0x04, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
0x18, 0x19, 0x19, 0x18, 0x18} },
{ .cmdlen = 59, .cmddata = {0xE0, 0x07, 0x08, 0x09, 0x0D, 0x10, 0x14, 0x16,
0x13, 0x24, 0x36, 0x48, 0x4A, 0x58, 0x6F, 0x76,
0x80, 0x97, 0xA5, 0xA8, 0xB5, 0xC6, 0x62, 0x63,
0x68, 0x6F, 0x72, 0x78, 0x7F, 0x7F, 0x00, 0x02,
0x08, 0x0D, 0x0C, 0x0E, 0x0F, 0x10, 0x24, 0x36,
0x48, 0x4A, 0x58, 0x6F, 0x78, 0x82, 0x99, 0xA4,
0xA0, 0xB1, 0xC0, 0x5E, 0x5E, 0x64, 0x6B, 0x6C,
0x73, 0x7F, 0x7F} },
{ .cmdlen = 2, .cmddata = {0xCC, 0x03} },
{ .cmdlen = 3, .cmddata = {0xC0, 0x1F, 0x73} },
{ .cmdlen = 3, .cmddata = {0xB6, 0x90, 0x90} },
{ .cmdlen = 2, .cmddata = {0xD4, 0x02} },
{ .cmdlen = 2, .cmddata = {0xBD, 0x01} },
{ .cmdlen = 2, .cmddata = {0xB1, 0x00} },
{ .cmdlen = 2, .cmddata = {0xBD, 0x00} },
{ .cmdlen = 8, .cmddata = {0xBF, 0x40, 0x81, 0x50, 0x00, 0x1A, 0xFC, 0x01} },
{ .cmdlen = 2, .cmddata = {0x36, 0x02} },
};
static const struct hx8394_panel_desc hx8394_desc = {
.display_mode = &hx8394_default_mode,
.mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_VIDEO_BURST,
.format = MIPI_DSI_FMT_RGB888,
.lanes = 4,
.on_cmds = hx8394_on_cmds,
.on_cmds_num = ARRAY_SIZE(hx8394_on_cmds),
};
static const struct of_device_id panel_of_match[] = {
{
.compatible = "himax,hx8394",
.data = &hx8394_desc,
},
{
/* sentinel */
}
};
MODULE_DEVICE_TABLE(of, panel_of_match);
static int hx8394_panel_add(struct panel_info *pinfo)
{
struct device *dev = &pinfo->link->dev;
int ret;
pinfo->reset = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
if (IS_ERR(pinfo->reset))
return dev_err_probe(dev, PTR_ERR(pinfo->reset),
"Couldn't get our reset GPIO\n");
pinfo->hsvcc = devm_regulator_get(dev, "hsvcc");
if (IS_ERR(pinfo->hsvcc))
return dev_err_probe(dev, PTR_ERR(pinfo->hsvcc),
"Failed to request hsvcc regulator\n");
pinfo->vspn3v3 = devm_regulator_get(dev, "vspn3v3");
if (IS_ERR(pinfo->vspn3v3))
return dev_err_probe(dev, PTR_ERR(pinfo->vspn3v3),
"Failed to request vspn3v3 regulator\n");
drm_panel_init(&pinfo->base, dev, &panel_funcs,
DRM_MODE_CONNECTOR_DSI);
ret = drm_panel_of_backlight(&pinfo->base);
if (ret)
return ret;
drm_panel_add(&pinfo->base);
return 0;
}
static int hx8394_panel_probe(struct mipi_dsi_device *dsi)
{
struct panel_info *pinfo;
const struct hx8394_panel_desc *desc;
int err;
pinfo = devm_kzalloc(&dsi->dev, sizeof(*pinfo), GFP_KERNEL);
if (!pinfo)
return -ENOMEM;
desc = of_device_get_match_data(&dsi->dev);
dsi->mode_flags = desc->mode_flags;
dsi->format = desc->format;
dsi->lanes = desc->lanes;
pinfo->desc = desc;
pinfo->link = dsi;
mipi_dsi_set_drvdata(dsi, pinfo);
err = hx8394_panel_add(pinfo);
if (err < 0)
return err;
err = mipi_dsi_attach(dsi);
if (err < 0)
drm_panel_remove(&pinfo->base);
return err;
}
static int hx8394_panel_remove(struct mipi_dsi_device *dsi)
{
struct panel_info *pinfo = mipi_dsi_get_drvdata(dsi);
int err;
err = hx8394_panel_disable(&pinfo->base);
if (err < 0)
dev_err(&dsi->dev, "failed to disable panel: %d\n", err);
err = hx8394_panel_unprepare(&pinfo->base);
if (err < 0)
dev_err(&dsi->dev, "failed to unprepare panel: %d\n", err);
err = mipi_dsi_detach(dsi);
if (err < 0)
dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err);
drm_panel_remove(&pinfo->base);
return 0;
}
static void hx8394_panel_shutdown(struct mipi_dsi_device *dsi)
{
struct panel_info *pinfo = mipi_dsi_get_drvdata(dsi);
hx8394_panel_disable(&pinfo->base);
hx8394_panel_unprepare(&pinfo->base);
}
static struct mipi_dsi_driver panel_driver = {
.driver = {
.name = "panel-himax8394",
.of_match_table = panel_of_match,
},
.probe = hx8394_panel_probe,
.remove = hx8394_panel_remove,
.shutdown = hx8394_panel_shutdown,
};
module_mipi_dsi_driver(panel_driver);
MODULE_DESCRIPTION("Himax8394 driver");
MODULE_LICENSE("GPL v2");

909
drivers/gpu/drm/panel/panel-ili9881d.c Normal file
View File

@@ -0,0 +1,909 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* ILI9881D panel driver
*
* Copyright (c) 2020 Seeed Studio
*/
#include "panel-ili9881d.h"
#include <linux/version.h>
#define ILI9881_PAGE(_page) DSI_DCS_WRITE(dsi, 0xff, 0x98, 0x81, _page)
#define IILI9881_COMMAND(_cmd, _data...) DSI_DCS_WRITE(dsi, _cmd, _data)
#define DCS_CMD_READ_ID1 0xDA
#define ILI_9881D_I2C_ADAPTER 1
#define ILI_9881D_I2C_ADDR 0x45
#define GOODIX_STATUS_SIZE 2
#define GOODIX_CONTACT_SIZE 8
#define GOODIX_BUFFER_STATUS_READY (((uint32_t)0x01) << 7)//BIT(7)
#define GOODIX_HAVE_KEY (((uint32_t)0x01) << 4)//BIT(4)
#define TP_DEFAULT_WIDTH 1280
#define TP_DEFAULT_HEIGHT 720
#define TP_MAX_POINTS 5
#define TP_POLL_INTERVAL 15
static struct i2c_mipi_dsi *ili9881d_mipi_dsi;
static int goodix_ts_read_input_report(struct i2c_mipi_dsi *md, u8 *data)
{
int header = GOODIX_STATUS_SIZE + GOODIX_CONTACT_SIZE;
int i, ret, touch_num;
for (i = 0; i < 2; i++) {
ret = i2c_md_read(md, REG_TP_STATUS, data, header);
if (ret < 0)
return -EIO;
if (data[0] & GOODIX_BUFFER_STATUS_READY) {
touch_num = data[0] & 0x0f;
if (touch_num > TP_MAX_POINTS)
return -EPROTO;
if (touch_num > 1) {
ret = i2c_md_read(md, REG_TP_POINT, data+header, (touch_num-1)*GOODIX_CONTACT_SIZE);
if (ret < 0)
return -EIO;
}
return touch_num;
}
usleep_range(3000, 5000); /* Poll every 3 - 5 ms */
}
/*
* The Goodix panel will send spurious interrupts after a
* 'finger up' event, which will always cause a timeout.
*/
return -ENOMSG;
}
//TODO
//need more work for it's compatibility
static void x_y_rotate(int *x, int *y)
{
int temp_x, temp_y;
int temp;
if (*x < 0 || *y < 0) {
pr_err("%s<%d> parameter error\n", __func__, __LINE__);
return;
}
//1 move rectangle center to (0,0)
temp_x = *x - TP_DEFAULT_WIDTH/2;
temp_y = *y - TP_DEFAULT_HEIGHT/2;
//2 rotate the point anti-clockwise for 90 degree
temp = temp_x;
temp_x = temp_y;
temp_y = temp;
temp_x *= (-1);
temp_y *= 1;
//3 zoom
temp_x = temp_x * TP_DEFAULT_WIDTH / TP_DEFAULT_HEIGHT;
temp_y = temp_y * TP_DEFAULT_HEIGHT / TP_DEFAULT_WIDTH;
//4 move rectangle center back to (TP_DEFAULT_WIDTH/2, TP_DEFAULT_HEIGHT/2)
temp_x += TP_DEFAULT_WIDTH/2;
temp_y += TP_DEFAULT_HEIGHT/2;
*x = temp_x;
*y = temp_y;
}
static void goodix_ts_report_touch_8b(struct i2c_mipi_dsi *md, u8 *coor_data)
{
struct input_dev *input_dev = md->input;
int id = coor_data[7];
int input_x = 0;
int input_y = 0;
int input_w = coor_data[4];
input_x = coor_data[1];
input_x <<= 8;
input_x += coor_data[0];
input_y = coor_data[3];
input_y <<= 8;
input_y += coor_data[2];
if (md->tp_point_rotate)
x_y_rotate(&input_x, &input_y);
input_mt_slot(input_dev, id);
input_mt_report_slot_state(input_dev, MT_TOOL_FINGER, true);
touchscreen_report_pos(input_dev, &md->prop, input_x, input_y, true);
input_report_abs(input_dev, ABS_MT_TOUCH_MAJOR, input_w);
input_report_abs(input_dev, ABS_MT_WIDTH_MAJOR, input_w);
}
static void tp_poll_func(struct input_dev *input)
{
struct i2c_mipi_dsi *md = (struct i2c_mipi_dsi *)input_get_drvdata(input);
u8 point_data[GOODIX_STATUS_SIZE + TP_MAX_POINTS * GOODIX_CONTACT_SIZE] = { 0 };
int touch_num;
int i;
touch_num = goodix_ts_read_input_report(md, point_data);
if (touch_num < 0)
return;
for (i = 0; i < touch_num; i++)
goodix_ts_report_touch_8b(md, &point_data[GOODIX_STATUS_SIZE + i*GOODIX_CONTACT_SIZE]);
input_mt_sync_frame(input);
input_sync(input);
}
int tp_init(struct i2c_mipi_dsi *md)
{
struct i2c_client *i2c = md->i2c;
struct device *dev = &i2c->dev;
struct input_dev *input;
int ret;
input = devm_input_allocate_device(dev);
if (!input) {
dev_err(dev, "Failed to allocate input device\n");
return -ENOMEM;
}
md->input = input;
input_set_drvdata(input, md);
input->dev.parent = dev;
input->name = "seeed-tp";
input->id.bustype = BUS_I2C;
input->id.vendor = 0x1234;
input->id.product = 0x1001;
input->id.version = 0x0100;
input_set_abs_params(input, ABS_MT_WIDTH_MAJOR, 0, 255, 0, 0);
input_set_abs_params(input, ABS_MT_TOUCH_MAJOR, 0, 255, 0, 0);
input_set_abs_params(input, ABS_MT_POSITION_X, 0, TP_DEFAULT_WIDTH, 0, 0);
input_set_abs_params(input, ABS_MT_POSITION_Y, 0, TP_DEFAULT_HEIGHT, 0, 0);
ret = input_mt_init_slots(input, TP_MAX_POINTS, INPUT_MT_DIRECT | INPUT_MT_DROP_UNUSED);
if (ret) {
dev_err(dev, "could not init mt slots, %d\n", ret);
return ret;
}
ret = input_setup_polling(input, tp_poll_func);
if (ret) {
dev_err(dev, "could not set up polling mode, %d\n", ret);
return ret;
}
input_set_poll_interval(input, TP_POLL_INTERVAL);
ret = input_register_device(input);
if (ret) {
dev_err(dev, "could not register input device, %d\n", ret);
return ret;
}
return 0;
}
int tp_deinit(struct i2c_mipi_dsi *md)
{
input_unregister_device(md->input);
return 0;
}
static const struct drm_display_mode ili9881d_modes = {
.clock = 76000,
.hdisplay = 800,
.hsync_start = 800 + 60,
.hsync_end = 800 + 60 + 40,
.htotal = 800 + 60 + 40 + 60,
.vdisplay = 1280,
.vsync_start = 1280 + 16,
.vsync_end = 1280 + 16 + 8,
.vtotal = 1280 + 16 + 8 + 16,
.width_mm = 62,
.height_mm = 110,
.flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
};
static int ili9881d_get_modes(struct drm_panel *panel, struct drm_connector *connector)
{
struct drm_display_mode *mode;
mode = drm_mode_duplicate(connector->dev, &ili9881d_modes);
if (!mode) {
dev_err(panel->dev, "failed to add mode %ux%u@%u\n",
mode->hdisplay, mode->vdisplay,
drm_mode_vrefresh(mode));
return -ENOMEM;
}
mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
drm_mode_set_name(mode);
connector->display_info.width_mm = mode->width_mm;
connector->display_info.height_mm = mode->height_mm;
drm_mode_probed_add(connector, mode);
return 1;
}
static int ili9881d_read_id(struct mipi_dsi_device *dsi, u8 *id1)
{
int ret;
ret = mipi_dsi_dcs_read(dsi, DCS_CMD_READ_ID1, id1, 1);
if (ret < 0) {
dev_err(&dsi->dev, "could not read ID1\n");
return ret;
}
dev_info(&dsi->dev, "ID1 : %02x\n", *id1);
return 0;
}
static int ili9881d_enable(struct drm_panel *panel)
{
struct mipi_dsi_device *dsi = ili9881d_mipi_dsi->dsi;
int ret = 0;
u8 id1;
DBG_FUNC();
if (!dsi)
return -1;
dsi->mode_flags |= MIPI_DSI_MODE_LPM;
ILI9881_PAGE(0x00);
mipi_dsi_set_maximum_return_packet_size(dsi, 1);
ret = ili9881d_read_id(dsi, &id1);
if (ret < 0) {
dev_info(&dsi->dev, "No LCD connected,pls check your hardware! ret:%d\n", ret);
return -ENODEV;
}
ILI9881_PAGE(0x01);
IILI9881_COMMAND(0x91,0x00);
IILI9881_COMMAND(0x92,0x00);
IILI9881_COMMAND(0x93,0x72);
IILI9881_COMMAND(0x94,0x00);
IILI9881_COMMAND(0x95,0x00);
IILI9881_COMMAND(0x96,0x09);
IILI9881_COMMAND(0x97,0x00);
IILI9881_COMMAND(0x98,0x00);
IILI9881_COMMAND(0x09,0x01);
IILI9881_COMMAND(0x0a,0x00);
IILI9881_COMMAND(0x0b,0x00);
IILI9881_COMMAND(0x0c,0x01);
IILI9881_COMMAND(0x0d,0x00);
IILI9881_COMMAND(0x0e,0x00);
IILI9881_COMMAND(0x0f,0x1D);
IILI9881_COMMAND(0x10,0x1D);
IILI9881_COMMAND(0x11,0x00);
IILI9881_COMMAND(0x12,0x00);
IILI9881_COMMAND(0x13,0x00);
IILI9881_COMMAND(0x14,0x00);
IILI9881_COMMAND(0x15,0x00);
IILI9881_COMMAND(0x16,0x00);
IILI9881_COMMAND(0x17,0x00);
IILI9881_COMMAND(0x18,0x00);
IILI9881_COMMAND(0x19,0x00);
IILI9881_COMMAND(0x1a,0x00);
IILI9881_COMMAND(0x1b,0x00);
IILI9881_COMMAND(0x1c,0x00);
IILI9881_COMMAND(0x1d,0x00);
IILI9881_COMMAND(0x1e,0xc0);
IILI9881_COMMAND(0x1f,0x00);
IILI9881_COMMAND(0x20,0x06);
IILI9881_COMMAND(0x21,0x02);
IILI9881_COMMAND(0x22,0x00);
IILI9881_COMMAND(0x23,0x00);
IILI9881_COMMAND(0x24,0x00);
IILI9881_COMMAND(0x25,0x00);
IILI9881_COMMAND(0x26,0x00);
IILI9881_COMMAND(0x27,0x00);
IILI9881_COMMAND(0x28,0x33);
IILI9881_COMMAND(0x29,0x03);
IILI9881_COMMAND(0x2a,0x00);
IILI9881_COMMAND(0x2b,0x00);
IILI9881_COMMAND(0x2c,0x00);
IILI9881_COMMAND(0x2d,0x00);
IILI9881_COMMAND(0x2e,0x00);
IILI9881_COMMAND(0x2f,0x00);
IILI9881_COMMAND(0x30,0x00);
IILI9881_COMMAND(0x31,0x00);
IILI9881_COMMAND(0x32,0x00);
IILI9881_COMMAND(0x33,0x00);
IILI9881_COMMAND(0x34,0x04);
IILI9881_COMMAND(0x35,0x00);
IILI9881_COMMAND(0x36,0x00);
IILI9881_COMMAND(0x37,0x00);
IILI9881_COMMAND(0x38,0x3C);
IILI9881_COMMAND(0x39,0x07);
IILI9881_COMMAND(0x3a,0x00);
IILI9881_COMMAND(0x3b,0x00);
IILI9881_COMMAND(0x3c,0x00);
IILI9881_COMMAND(0x40,0x03);
IILI9881_COMMAND(0x41,0x20);
IILI9881_COMMAND(0x42,0x00);
IILI9881_COMMAND(0x43,0x00);
IILI9881_COMMAND(0x44,0x03);
IILI9881_COMMAND(0x45,0x00);
IILI9881_COMMAND(0x46,0x01);
IILI9881_COMMAND(0x47,0x08);
IILI9881_COMMAND(0x48,0x00);
IILI9881_COMMAND(0x49,0x00);
IILI9881_COMMAND(0x4a,0x00);
IILI9881_COMMAND(0x4b,0x00);
// ==== GL[3OUT=
IILI9881_COMMAND(0x4c,0x01);
IILI9881_COMMAND(0x4d,0x54);
IILI9881_COMMAND(0x4e,0x57);
IILI9881_COMMAND(0x4f,0x9b);
IILI9881_COMMAND(0x50,0xf9);
IILI9881_COMMAND(0x51,0x27);
IILI9881_COMMAND(0x52,0x2f);
IILI9881_COMMAND(0x53,0xf2);
IILI9881_COMMAND(0x54,0xff);
IILI9881_COMMAND(0x55,0xff);
IILI9881_COMMAND(0x56,0xff);
// ==== GR[3OUT==
IILI9881_COMMAND(0x57,0x01);
IILI9881_COMMAND(0x58,0x54);
IILI9881_COMMAND(0x59,0x46);
IILI9881_COMMAND(0x5a,0x8a);
IILI9881_COMMAND(0x5b,0xf8);
IILI9881_COMMAND(0x5c,0x26);
IILI9881_COMMAND(0x5d,0x2f);
IILI9881_COMMAND(0x5e,0xf2);
IILI9881_COMMAND(0x5f,0xff);
IILI9881_COMMAND(0x60,0xff);
IILI9881_COMMAND(0x61,0xff);
IILI9881_COMMAND(0x62,0x06);
// == GOUT:4]_BWUTL[5:0]==
IILI9881_COMMAND(0x63,0x01);
IILI9881_COMMAND(0x64,0x00);
IILI9881_COMMAND(0x65,0xa4);
IILI9881_COMMAND(0x66,0xa5);
IILI9881_COMMAND(0x67,0x58);
IILI9881_COMMAND(0x68,0x5a);
IILI9881_COMMAND(0x69,0x54);
IILI9881_COMMAND(0x6a,0x56);
IILI9881_COMMAND(0x6b,0x06);
IILI9881_COMMAND(0x6c,0xff);
IILI9881_COMMAND(0x6d,0x08);
IILI9881_COMMAND(0x6e,0x02);
IILI9881_COMMAND(0x6f,0xff);
IILI9881_COMMAND(0x70,0x02);
IILI9881_COMMAND(0x71,0x02);
IILI9881_COMMAND(0x72,0xff);
IILI9881_COMMAND(0x73,0xff);
IILI9881_COMMAND(0x74,0xff);
IILI9881_COMMAND(0x75,0xff);
IILI9881_COMMAND(0x76,0xff);
IILI9881_COMMAND(0x77,0xff);
IILI9881_COMMAND(0x78,0xff);
// == GOUT:4]_BWUTR[5:0]==
IILI9881_COMMAND(0x79,0x01);
IILI9881_COMMAND(0x7a,0x00);
IILI9881_COMMAND(0x7b,0xa4);
IILI9881_COMMAND(0x7c,0xa5);
IILI9881_COMMAND(0x7d,0x59);
IILI9881_COMMAND(0x7e,0x5b);
IILI9881_COMMAND(0x7f,0x55);
IILI9881_COMMAND(0x80,0x57);
IILI9881_COMMAND(0x81,0x07);
IILI9881_COMMAND(0x82,0xff);
IILI9881_COMMAND(0x83,0x09);
IILI9881_COMMAND(0x84,0x02);
IILI9881_COMMAND(0x85,0xff);
IILI9881_COMMAND(0x86,0x02);
IILI9881_COMMAND(0x87,0x02);
IILI9881_COMMAND(0x88,0xff);
IILI9881_COMMAND(0x89,0xff);
IILI9881_COMMAND(0x8a,0xff);
IILI9881_COMMAND(0x8b,0xff);
IILI9881_COMMAND(0x8c,0xff);
IILI9881_COMMAND(0x8d,0xff);
IILI9881_COMMAND(0x8e,0xff);
IILI9881_COMMAND(0x8f,0x00);
IILI9881_COMMAND(0x90,0x00);
IILI9881_COMMAND(0x9d,0x00);
IILI9881_COMMAND(0x9e,0x00);
IILI9881_COMMAND(0xa0,0x35);
IILI9881_COMMAND(0xa1,0x00);
IILI9881_COMMAND(0xa2,0x00);
IILI9881_COMMAND(0xa3,0x00);
IILI9881_COMMAND(0xa4,0x00);
IILI9881_COMMAND(0xa5,0x00);
IILI9881_COMMAND(0xa6,0x08);
IILI9881_COMMAND(0xa7,0x00);
IILI9881_COMMAND(0xa8,0x00);
IILI9881_COMMAND(0xa9,0x00);
IILI9881_COMMAND(0xaa,0x00);
IILI9881_COMMAND(0xab,0x00);
IILI9881_COMMAND(0xac,0x00);
IILI9881_COMMAND(0xad,0x00);
IILI9881_COMMAND(0xae,0xff);
IILI9881_COMMAND(0xaf,0x00);
IILI9881_COMMAND(0xb0,0x00);
ILI9881_PAGE(0x02);
IILI9881_COMMAND(0x08,0x11);
IILI9881_COMMAND(0x0a,0x0c);
IILI9881_COMMAND(0x0f,0x06);
IILI9881_COMMAND(0xA0,0x00,0x26,0x35,0x16,0x19,0x2C,0x1F,0x1F,0x96,0x1C,0x28,0x80,0x1A,0x18,0x4C,0x21,0x27,0x55,0x65,0x39);
IILI9881_COMMAND(0xC0,0x00,0x26,0x35,0x16,0x19,0x2C,0x1F,0x1F,0x96,0x1C,0x28,0x80,0x1A,0x18,0x4C,0x21,0x27,0x55,0x65,0x39);
//===== GIP code finish =====//
IILI9881_COMMAND(0x4C,0xA4); // PS_EN on ,0x default :A4
IILI9881_COMMAND(0x18,0xF4); // SH on ,0x default E4
//=========================//
ILI9881_PAGE(0x04);
IILI9881_COMMAND(0x5D,0xAF); // VREG1 5.5V
IILI9881_COMMAND(0x5E,0xAF); // VREG2 5.5V
IILI9881_COMMAND(0x60,0x9B); // VCM1
IILI9881_COMMAND(0x62,0x9B); // VCM2
IILI9881_COMMAND(0x82,0x38); // VREF_VGH_MOD_CLPSEL 16V
IILI9881_COMMAND(0x84,0x38); // VREF_VGH_DC 16V
IILI9881_COMMAND(0x86,0x18); // VREF_VGL_CLPSEL -10V
IILI9881_COMMAND(0x66,0xC4); // VGH_AC x4 ,0xdefault :04
IILI9881_COMMAND(0xC1,0xF0); // VGH_DC x4 ,0xdefault :70
IILI9881_COMMAND(0x70,0x60);
IILI9881_COMMAND(0x71,0x00);
//=========================//
IILI9881_COMMAND(0x5B,0x33); // vcore_sel Voltage
IILI9881_COMMAND(0x6C,0x10); // vcore bias L
IILI9881_COMMAND(0x77,0x03); // vcore_sel Voltage
IILI9881_COMMAND(0x7B,0x02); // vcore bias R
//=========================//
ILI9881_PAGE(0x01);
IILI9881_COMMAND(0xF0,0x00); // 1280 Gate NL
IILI9881_COMMAND(0xF1,0xC8); // 1280 Gate NL
ILI9881_PAGE(0x05);
IILI9881_COMMAND(0x22,0x3A); // RGB to BGR
ILI9881_PAGE(0x00);
IILI9881_COMMAND(0x35,0x00);
IILI9881_COMMAND(0x11);
msleep(120);
IILI9881_COMMAND(0x29);
return 0;
}
static const struct drm_panel_funcs ili9881d_funcs = {
.get_modes = ili9881d_get_modes,
.enable = ili9881d_enable,
};
static void ili9881d_set_dsi(struct mipi_dsi_device *dsi)
{
dsi->mode_flags = (MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_LPM);
dsi->format = MIPI_DSI_FMT_RGB888;
dsi->lanes = 4;
}
const struct panel_data ili9881d_data = {
.set_dsi = ili9881d_set_dsi,
.funcs = &ili9881d_funcs,
};
static int i2c_md_read(struct i2c_mipi_dsi *md, u8 reg, u8 *buf, int len)
{
struct i2c_client *client = md->i2c;
struct i2c_msg msgs[1];
u8 addr_buf[1] = { reg };
u8 data_buf[1] = { 0, };
int ret;
mutex_lock(&md->mutex);
/* Write register address */
msgs[0].addr = client->addr;
msgs[0].flags = 0;
msgs[0].len = ARRAY_SIZE(addr_buf);
msgs[0].buf = addr_buf;
ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
if (ret != ARRAY_SIZE(msgs)) {
mutex_unlock(&md->mutex);
return -EIO;
}
usleep_range(1000, 1500);
/* Read data from register */
msgs[0].addr = client->addr;
msgs[0].flags = I2C_M_RD;
if (buf == NULL) {
msgs[0].len = 1;
msgs[0].buf = data_buf;
} else {
msgs[0].len = len;
msgs[0].buf = buf;
}
ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
if (ret != ARRAY_SIZE(msgs)) {
mutex_unlock(&md->mutex);
return -EIO;
}
mutex_unlock(&md->mutex);
if (buf == NULL)
return data_buf[0];
else
return ret;
}
static void i2c_md_write(struct i2c_mipi_dsi *md, u8 reg, u8 val)
{
struct i2c_client *client = md->i2c;
int ret;
mutex_lock(&md->mutex);
ret = i2c_smbus_write_byte_data(client, reg, val);
if (ret)
dev_err(&client->dev, "I2C write failed: %d\n", ret);
usleep_range(1000, 1500);
mutex_unlock(&md->mutex);
}
/* panel_funcs */
static int panel_prepare(struct drm_panel *panel)
{
int ret = 0;
struct i2c_mipi_dsi *md = panel_to_md(panel);
const struct drm_panel_funcs *funcs = md->panel_data->funcs;
DBG_FUNC("");
/* i2c */
/* reset pin */
i2c_md_write(md, REG_LCD_RST, 0);
msleep(20);
i2c_md_write(md, REG_LCD_RST, 1);
msleep(20);
/* panel */
if (funcs && funcs->prepare) {
ret = funcs->prepare(panel);
if (ret < 0) {
i2c_md_write(md, REG_POWERON, 0);
i2c_md_write(md, REG_LCD_RST, 0);
i2c_md_write(md, REG_PWM, 0);
return ret;
}
}
return ret;
}
static int panel_unprepare(struct drm_panel *panel)
{
int ret = 0;
struct i2c_mipi_dsi *md = panel_to_md(panel);
const struct drm_panel_funcs *funcs = md->panel_data->funcs;
DBG_FUNC("");
if (funcs && funcs->unprepare) {
ret = funcs->unprepare(panel);
if (ret < 0)
return ret;
}
return ret;
}
static int panel_enable(struct drm_panel *panel)
{
int ret = 0;
struct i2c_mipi_dsi *md = panel_to_md(panel);
const struct drm_panel_funcs *funcs = md->panel_data->funcs;
DBG_FUNC("");
/* panel */
if (funcs && funcs->enable) {
ret = funcs->enable(panel);
if (ret < 0)
return ret;
}
/* i2c */
i2c_md_write(md, REG_PWM, md->brightness);
return ret;
}
static int panel_disable(struct drm_panel *panel)
{
int ret = 0;
struct i2c_mipi_dsi *md = panel_to_md(panel);
const struct drm_panel_funcs *funcs = md->panel_data->funcs;
DBG_FUNC("");
/* i2c */
i2c_md_write(md, REG_PWM, 0);
i2c_md_write(md, REG_LCD_RST, 0);
/* panel */
if (funcs && funcs->disable) {
ret = funcs->disable(panel);
if (ret < 0)
return ret;
}
return ret;
}
static int panel_get_modes(struct drm_panel *panel, struct drm_connector *connector)
{
int ret = 0;
struct i2c_mipi_dsi *md = panel_to_md(panel);
const struct drm_panel_funcs *funcs = md->panel_data->funcs;
if (funcs && funcs->get_modes) {
ret = funcs->get_modes(panel, connector);
if (ret < 0)
return ret;
}
return ret;
}
static const struct drm_panel_funcs panel_funcs = {
.prepare = panel_prepare,
.unprepare = panel_unprepare,
.enable = panel_enable,
.disable = panel_disable,
.get_modes = panel_get_modes,
};
/* backlight */
static int backlight_update(struct backlight_device *bd)
{
struct i2c_mipi_dsi *md = bl_get_data(bd);
int brightness = bd->props.brightness;
if (bd->props.power != FB_BLANK_UNBLANK ||
bd->props.fb_blank != FB_BLANK_UNBLANK ||
(bd->props.state & (BL_CORE_SUSPENDED | BL_CORE_FBBLANK))) {
brightness = 0;
}
md->brightness = brightness;
i2c_md_write(md, REG_PWM, brightness);
return 0;
}
static const struct backlight_ops backlight_ops = {
.options = BL_CORE_SUSPENDRESUME,
.update_status = backlight_update,
};
static int backlight_init(struct i2c_mipi_dsi *md)
{
struct device *dev = &md->i2c->dev;
struct backlight_properties props;
struct backlight_device *bd;
memset(&props, 0, sizeof(props));
props.type = BACKLIGHT_RAW;
props.max_brightness = 255;
bd = devm_backlight_device_register(dev, dev_name(dev),
dev, md, &backlight_ops,
&props);
if (IS_ERR(bd)) {
dev_err(dev, "failed to register backlight\n");
return PTR_ERR(bd);
}
bd->props.brightness = 255;
backlight_update_status(bd);
return 0;
}
static int i2c_md_probe(struct i2c_client *i2c, const struct i2c_device_id *id)
{
struct device *dev = &i2c->dev;
struct i2c_mipi_dsi *md = ili9881d_mipi_dsi;
int ret = 0;
DBG_FUNC("start");
i2c_set_clientdata(i2c, md);
mutex_init(&md->mutex);
md->i2c = i2c;
md->panel_data = &ili9881d_data;
if (!md->panel_data) {
dev_err(dev, "No valid panel data.\n");
return -ENODEV;
}
ret = i2c_md_read(md, REG_ID, NULL, 0);
if (ret != 0xC3) {
dev_err(dev, "Unknown chip id: 0x%02x\n", ret);
return -ENODEV;
}
dev_info(dev, "I2C Address:0x%x read id: 0x%x\n", i2c->addr, ret);
/* Turn on */
i2c_md_write(md, REG_POWERON, 1);
DBG_FUNC("finished.");
return 0;
}
static int i2c_md_remove(struct i2c_client *i2c)
{
struct i2c_mipi_dsi *md = i2c_get_clientdata(i2c);
DBG_FUNC();
tp_deinit(md);
/* Turn off power */
i2c_md_write(md, REG_POWERON, 0);
i2c_md_write(md, REG_LCD_RST, 0);
i2c_md_write(md, REG_PWM, 0);
mipi_dsi_detach(md->dsi);
drm_panel_remove(&md->panel);
return 0;
}
static void i2c_md_shutdown(struct i2c_client *i2c)
{
struct i2c_mipi_dsi *md = i2c_get_clientdata(i2c);
DBG_FUNC();
tp_deinit(md);
/* Turn off power */
i2c_md_write(md, REG_POWERON, 0);
i2c_md_write(md, REG_LCD_RST, 0);
i2c_md_write(md, REG_PWM, 0);
mipi_dsi_detach(md->dsi);
drm_panel_remove(&md->panel);
}
static const struct of_device_id i2c_md_of_ids[] = {
{
.compatible = "ili9881d",
},
{ }
};
MODULE_DEVICE_TABLE(of, i2c_md_of_ids);
static struct i2c_driver i2c_md_driver = {
.driver = {
.name = "i2c_mipi_dsi",
.of_match_table = i2c_md_of_ids,
},
.probe = i2c_md_probe,
.remove = i2c_md_remove,
.shutdown = i2c_md_shutdown,
};
static int ili9881d_hack_create_device(void)
{
struct i2c_adapter *adapter;
struct i2c_client *client;
struct i2c_board_info info = {
.type = "ili9881d",
.addr = ILI_9881D_I2C_ADDR,
};
adapter = i2c_get_adapter(ILI_9881D_I2C_ADAPTER);
if (!adapter) {
pr_err("%s: i2c_get_adapter(%d) failed\n", __func__,
ILI_9881D_I2C_ADAPTER);
return -EINVAL;
}
client = i2c_new_client_device(adapter, &info);
if (IS_ERR(client)) {
pr_err("%s: creating I2C device failed\n", __func__);
i2c_put_adapter(adapter);
return PTR_ERR(client);
}
return 0;
}
static int ili9881d_dsi_probe(struct mipi_dsi_device *dsi)
{
int ret;
struct i2c_mipi_dsi *ctx;
ctx = devm_kzalloc(&dsi->dev, sizeof(*ctx), GFP_KERNEL);
if (!ctx)
return -ENOMEM;
ili9881d_mipi_dsi = ctx;
ili9881d_hack_create_device();
ret = i2c_add_driver(&i2c_md_driver);
if (ret < 0) {
dev_err(&dsi->dev, "i2c_add_driver ret:%d\n", ret);
return ret;
}
mipi_dsi_set_drvdata(dsi, ctx);
ctx->dsi = dsi;
ctx->panel_data->set_dsi(ctx->dsi);
drm_panel_init(&ctx->panel, &dsi->dev, &panel_funcs, DRM_MODE_CONNECTOR_DSI);
drm_panel_add(&ctx->panel);
tp_init(ctx);
backlight_init(ctx);
ret = device_property_read_u32(&dsi->dev, "mcu_auto_reset_enable", &ctx->mcu_auto_reset);
if (ret < 0)
dev_err(&dsi->dev, "Can't get the data of mcu_auto_reset!\n");
i2c_md_write(ctx, REG_MCU_AUTO_RESET, (ctx->mcu_auto_reset&0xff));
ret = device_property_read_u32(&dsi->dev, "tp_point_rotate", &ctx->tp_point_rotate);
if (ret < 0)
dev_err(&dsi->dev, "Can't get the data of tp_point_rotate!\n");
return mipi_dsi_attach(dsi);
}
static int ili9881d_dsi_remove(struct mipi_dsi_device *dsi)
{
struct i2c_mipi_dsi *ctx = mipi_dsi_get_drvdata(dsi);
mipi_dsi_detach(dsi);
drm_panel_remove(&ctx->panel);
return 0;
}
static const struct of_device_id ili9881d_of_match[] = {
{ .compatible = "i2c_dsi,ili9881d", },
{ }
};
MODULE_DEVICE_TABLE(of, ili9881d_of_match);
static struct mipi_dsi_driver ili9881d_dsi_driver = {
.probe = ili9881d_dsi_probe,
.remove = ili9881d_dsi_remove,
.driver = {
.name = "ili9881d-dsi",
.of_match_table = ili9881d_of_match,
},
};
module_mipi_dsi_driver(ili9881d_dsi_driver);
MODULE_DESCRIPTION("Ilitek ILI9881D Controller Driver");
MODULE_LICENSE("GPL v2");

128
drivers/gpu/drm/panel/panel-ili9881d.h Normal file
View File

@@ -0,0 +1,128 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* mipi_dsi.h - MIPI dsi module
*
* Copyright (c) 2020 Seeed Studio
*
* I2C slave address: 0x45
*/
#ifndef __MIPI_DSI_H__
#define __MIPI_DSI_H__
#include <linux/interrupt.h>
#include <linux/bitops.h>
#include <linux/slab.h>
#include <linux/string.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/fb.h>
#include <linux/gpio.h>
#include <linux/gpio/consumer.h>
#include <linux/i2c.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/of_graph.h>
#include <linux/pm.h>
#include <drm/drm_crtc.h>
#include <drm/drm_device.h>
#include <drm/drm_mipi_dsi.h>
#include <drm/drm_panel.h>
#include <drm/drm_modes.h>
#include <video/mipi_display.h>
#include <linux/input.h>
#include <linux/input/mt.h>
#include <linux/input/touchscreen.h>
#ifdef I2C_DSI_DBG
#define DBG_FUNC(format, x...) printk(KERN_INFO "[DSI]%s:" format"\n", __func__, ##x)
#define DBG_PRINT(format, x...) printk(KERN_INFO "[DSI]" format"\n", ##x)
#else
#define DBG_FUNC(format, x...)
#define DBG_PRINT(format, x...)
#endif
#define DSI_DRIVER_NAME "i2c_mipi_dsi"
/* i2c: commands */
enum REG_ADDR {
REG_ID = 0x80,
REG_PORTA, /* BIT(2) for horizontal flip, BIT(3) for vertical flip */
REG_PORTB, // --
REG_PORTC,
REG_PORTD,
REG_POWERON,// --
REG_PWM, // --
REG_DDRA,
REG_DDRB,
REG_DDRC,
REG_DDRD,
REG_TEST,
REG_WR_ADDRL,
REG_WR_ADDRH,
REG_READH,
REG_READL,
REG_WRITEH,
REG_WRITEL,
REG_ID2,
REG_LCD_RST,
REG_TP_RST,
REG_TP_STATUS,
REG_TP_POINT,
REG_TP_VERSION,
REG_ADC1,
REG_ADC2,
REG_MCU_AUTO_RESET,
REG_MAX
};
#define DSI_DCS_WRITE(dsi, seq...) \
{ \
int ret = 0; \
const u8 d[] = { seq }; \
ret = mipi_dsi_dcs_write_buffer(dsi, d, ARRAY_SIZE(d)); \
if (ret < 0) \
return ret; \
}
struct panel_data {
void (*set_dsi)(struct mipi_dsi_device *dsi);
const struct drm_panel_funcs *funcs;
};
struct i2c_mipi_dsi {
struct i2c_client *i2c;
struct mutex mutex;
// panel
struct drm_panel panel;
struct panel_data *panel_data;
// dsi
struct mipi_dsi_device *dsi;
// tp
struct input_dev *input;
struct touchscreen_properties prop;
uint32_t tp_point_rotate;
// backlight
int brightness;
// mcu auto reset enable when the tp driver is not working
uint32_t mcu_auto_reset;
};
#define panel_to_md(_p) container_of(_p, struct i2c_mipi_dsi, panel)
static int i2c_md_read(struct i2c_mipi_dsi *md, u8 reg, u8 *buf, int len);
#endif /*End of header guard macro */

5
drivers/gpu/drm/panel/panel-ilitek-ili9881c.c
View File

@@ -690,11 +690,6 @@ static const struct ili9881c_instr txd_dy800qwxpab_init[] = {
};
static const struct ili9881c_instr gx_kd080d74_d028_init[] = {
ILI9881C_SWITCH_PAGE_INSTR(0),
ILI9881C_COMMAND_INSTR(0x35, 0x0),
ILI9881C_COMMAND_INSTR(0x11, 0x0),
ILI9881C_COMMAND_INSTR(0x29, 0x0),
ILI9881C_SWITCH_PAGE_INSTR(0x3),
ILI9881C_COMMAND_INSTR(0x01, 0x00),
ILI9881C_COMMAND_INSTR(0x02, 0x00),

2
drivers/gpu/drm/verisilicon/dw_hdmi-light.c
View File

@@ -163,7 +163,7 @@ struct platform_driver dw_hdmi_light_platform_driver = {
},
};
MODULE_AUTHOR("You Xiao <youxiao.fc@alibaba-inc.com>");
MODULE_AUTHOR("You Xiao <youxiao.fc@linux.alibaba.com>");
MODULE_DESCRIPTION("Light Platforms Specific DW-HDMI Driver Extention");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:dwhdmi-light");

3
drivers/gpu/drm/verisilicon/vs_dc_hw.c
View File

@@ -1390,6 +1390,9 @@ int dc_hw_init(struct dc_hw *hw)
dc_write(hw, DC_OVERLAY_WATER_MARK + 0xc, 0x3000);
dc_write(hw, DC_QOS_CONFIG, 0xc0);
dc_write(hw, DC_CLK_GATTING, 0x0);
dc_write(hw, DC_CLK_GATTING + 0x4, 0x0);
return 0;
}

7
drivers/gpu/drm/verisilicon/vs_gem.c
View File

@@ -227,10 +227,13 @@ static void vs_gem_free_object(struct drm_gem_object *obj)
{
struct vs_gem_object *vs_obj = to_vs_gem_object(obj);
if (obj->import_attach)
if (obj->import_attach) {
drm_prime_gem_destroy(obj, vs_obj->sgt);
else
kvfree(vs_obj->pages);
}
else {
vs_gem_free_buf(vs_obj);
}
drm_gem_object_release(obj);

1
drivers/i2c/busses/i2c-designware-core.h
View File

@@ -107,6 +107,7 @@
#define DW_IC_STATUS_ACTIVITY 0x1
#define DW_IC_STATUS_TFE BIT(2)
#define DW_IC_STATUS_RFNE BIT(3)
#define DW_IC_STATUS_MASTER_ACTIVITY BIT(5)
#define DW_IC_STATUS_SLAVE_ACTIVITY BIT(6)

8
drivers/i2c/busses/i2c-designware-master.c
View File

@@ -613,7 +613,7 @@ static u32 i2c_dw_read_clear_intrbits(struct dw_i2c_dev *dev)
*/
static int i2c_dw_irq_handler_master(struct dw_i2c_dev *dev)
{
u32 stat;
u32 stat, status;
stat = i2c_dw_read_clear_intrbits(dev);
if (stat & DW_IC_INTR_TX_ABRT) {
@@ -641,7 +641,11 @@ static int i2c_dw_irq_handler_master(struct dw_i2c_dev *dev)
*/
tx_aborted:
if ((stat & (DW_IC_INTR_TX_ABRT | DW_IC_INTR_STOP_DET)) || dev->msg_err)
regmap_read(dev->map, DW_IC_STATUS, &status);
if ((stat & DW_IC_INTR_TX_ABRT) || dev->msg_err ||
((status & DW_IC_STATUS_TFE) &&
(!(status & DW_IC_STATUS_RFNE)) &&
(!(status & DW_IC_STATUS_MASTER_ACTIVITY))))
complete(&dev->cmd_complete);
else if (unlikely(dev->flags & ACCESS_INTR_MASK)) {
/* Workaround to trigger pending interrupt */

2
drivers/iio/adc/light_adc.c
View File

@@ -722,6 +722,6 @@ static struct platform_driver light_adc_driver = {
module_platform_driver(light_adc_driver);
MODULE_AUTHOR("fugang.duan <duanfugang.dfg@alibaba-inc.com>");
MODULE_AUTHOR("fugang.duan <duanfugang.dfg@linux.alibaba.com>");
MODULE_DESCRIPTION("Thead Light ADC driver");
MODULE_LICENSE("GPL v2");

26
drivers/irqchip/irq-riscv-intc.c
View File

@@ -22,7 +22,33 @@ static struct irq_domain *intc_domain;
static asmlinkage void riscv_intc_irq(struct pt_regs *regs)
{
unsigned long cause = regs->cause & ~CAUSE_IRQ_FLAG;
unsigned long epc = instruction_pointer(regs);
u32 insn;
#define MATCH_LR_W 0x1000202f
#define MASK_LR_W 0xf9f0707f
#define MATCH_DCACHE_CVAL1 0x0240000b
#define MASK_DCACHE_CVAL1 0xfff07fff
pagefault_disable();
if ((epc & 0x7f) != 4)
goto out;
if (__get_user(insn, (u32 *)epc))
goto out;
if ((insn & MASK_LR_W) != MATCH_LR_W)
goto out;
if (__get_user(insn, (u32 *)(epc - 4)))
goto out;
if ((insn & MASK_DCACHE_CVAL1) != MATCH_DCACHE_CVAL1)
goto out;
instruction_pointer_set(regs, epc - 4);
out:
pagefault_enable();
if (unlikely(cause >= BITS_PER_LONG))
panic("unexpected interrupt cause");

6
drivers/mailbox/light-mailbox.c
View File

@@ -254,10 +254,8 @@ static irqreturn_t light_mbox_isr(int irq, void *p)
mbox_chan_txdone(chan, 0);
}
if (!info0_data && !info7_data) {
dev_warn_ratelimited(priv->dev, "not expected chan[%d] interrupt\n", cp->idx);
if (!info0_data && !info7_data)
return IRQ_NONE;
}
return IRQ_HANDLED;
}
@@ -504,6 +502,6 @@ static struct platform_driver light_mbox_driver = {
};
module_platform_driver(light_mbox_driver);
MODULE_AUTHOR("fugang.duan <duanfugang.dfg@alibaba-inc.com>");
MODULE_AUTHOR("fugang.duan <duanfugang.dfg@linux.alibaba.com>");
MODULE_DESCRIPTION("Thead Light mailbox IPC driver");
MODULE_LICENSE("GPL v2");

2
drivers/misc/dsmart_card.c
View File

@@ -1246,6 +1246,6 @@ static struct platform_driver dsmart_card_driver = {
};
module_platform_driver(dsmart_card_driver);
MODULE_AUTHOR("wei.liu <lw32886@alibaba-inc.com>");
MODULE_AUTHOR("wei.liu <lw32886@linux.alibaba.com>");
MODULE_DESCRIPTION("iso7816 smart card platform driver");
MODULE_LICENSE("GPL v2");

202
drivers/mmc/host/sdhci-of-dwcmshc.c
View File

@@ -33,6 +33,7 @@ struct dwcmshc_priv {
bool pull_up_en;
bool io_fixed_1v8;
bool wprtn_ignore;
long reset_cnt;
};
#define HS400_DELAY_LINE 24
@@ -255,12 +256,35 @@ static int snps_execute_tuning(struct sdhci_host *host, u32 opcode)
return 0;
}
static void snps_sdhci_reset(struct sdhci_host *host, u8 mask)
static void snps_sdhci_set_phy(struct sdhci_host *host)
{
struct sdhci_pltfm_host *pltfm_host;
struct dwcmshc_priv *priv;
u8 emmc_ctl;
//u32 soc_reg;
pltfm_host = sdhci_priv(host);
priv = sdhci_pltfm_priv(pltfm_host);
/*Before power on,set PHY configs*/
emmc_ctl = sdhci_readw(host, EMMC_CTRL_R);
if (priv->is_emmc_card) {
snps_phy_1_8v_init(host);
emmc_ctl |= (1 << CARD_IS_EMMC);
} else {
snps_phy_3_3v_init(host);
emmc_ctl &=~(1 << CARD_IS_EMMC);
}
sdhci_writeb(host, emmc_ctl, EMMC_CTRL_R);
sdhci_writeb(host, 0x25, PHY_DLL_CNFG1_R);
}
static void snps_sdhci_reset(struct sdhci_host *host, u8 mask)
{
struct sdhci_pltfm_host *pltfm_host;
struct dwcmshc_priv *priv;
u16 ctrl_2;
pltfm_host = sdhci_priv(host);
priv = sdhci_pltfm_priv(pltfm_host);
@@ -274,19 +298,21 @@ static void snps_sdhci_reset(struct sdhci_host *host, u8 mask)
/*host reset*/
sdhci_reset(host, mask);
/*fix host reset error*/
mdelay(100);
/* Before phy reset,set io voltage to fixed to 1v8.
* For mask is SDHCI_RESET_ALL,regs will reset to default val.
*/
if(priv->io_fixed_1v8){
ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
if(! (ctrl_2 & SDHCI_CTRL_VDD_180)){
ctrl_2 |= SDHCI_CTRL_VDD_180;
sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
}
}
++(priv->reset_cnt);
pr_debug("%s: sdhci reset cnt %ld\n",host->hw_name,priv->reset_cnt);
emmc_ctl = sdhci_readw(host, EMMC_CTRL_R);
if (priv->is_emmc_card) {
snps_phy_1_8v_init(host);
emmc_ctl |= (1 << CARD_IS_EMMC);
} else {
snps_phy_3_3v_init(host);
emmc_ctl &=~(1 << CARD_IS_EMMC);
}
sdhci_writeb(host, emmc_ctl, EMMC_CTRL_R);
sdhci_writeb(host, 0x25, PHY_DLL_CNFG1_R);
}
/*
* If DMA addr spans 128MB boundary, we split the DMA transfer into two
@@ -362,7 +388,7 @@ static void dwcmshc_set_uhs_signaling(struct sdhci_host *host,
if (priv->io_fixed_1v8)
ctrl_2 |= SDHCI_CTRL_VDD_180;
sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
if (timing == MMC_TIMING_MMC_HS400) {
@@ -381,6 +407,7 @@ static void dwcmshc_set_uhs_signaling(struct sdhci_host *host,
sdhci_writel(host, reg, AT_CTRL_R);
delay_line = HS400_DELAY_LINE;
snps_sdhci_set_phy(host); /* update tx delay*/
} else {
sdhci_writeb(host, 0, PHY_DLLDL_CNFG_R);
}
@@ -400,8 +427,141 @@ static unsigned int dwcmshc_pltfm_get_ro(struct sdhci_host *host)
return is_readonly;
}
/* Complete selection of HS400 ,software reset DAT & cmd line
* resolve for first time data access error(time out) when
* first swith to hs400 mode.
*
* From : SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS
* Some (ENE) controllers go apeshit on some ios operation,
* signalling timeout and CRC errors even on CMD0. Resetting
* it on each ios seems to solve the problem.
*
*/
static void dwcmshc_hs400_complete(struct mmc_host *mmc)
{
struct sdhci_host *host = mmc_priv(mmc);
u8 mask = SDHCI_RESET_CMD | SDHCI_RESET_DATA;
if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
if (!mmc->ops->get_cd(mmc))
return;
}
snps_sdhci_reset(host,mask);
//host->ops->reset(host, mask);
}
static void sdhci_set_power_reg(struct sdhci_host *host, unsigned char mode,
unsigned short vdd)
{
struct mmc_host *mmc = host->mmc;
mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
if (mode != MMC_POWER_OFF)
sdhci_writeb(host, SDHCI_POWER_ON, SDHCI_POWER_CONTROL);
else
sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
}
/* Add snps_sdhci_set_phy before POWER ON for this controller.
* Similar to public sdhci.c sdhci_set_power_noreg().
*/
static void dwcmshc_set_power_noreg(struct sdhci_host *host, unsigned char mode,
unsigned short vdd)
{
u8 pwr = 0;
if (mode != MMC_POWER_OFF) {
switch (1 << vdd) {
case MMC_VDD_165_195:
/*
* Without a regulator, SDHCI does not support 2.0v
* so we only get here if the driver deliberately
* added the 2.0v range to ocr_avail. Map it to 1.8v
* for the purpose of turning on the power.
*/
case MMC_VDD_20_21:
pwr = SDHCI_POWER_180;
break;
case MMC_VDD_29_30:
case MMC_VDD_30_31:
pwr = SDHCI_POWER_300;
break;
case MMC_VDD_32_33:
case MMC_VDD_33_34:
/*
* 3.4 ~ 3.6V are valid only for those platforms where it's
* known that the voltage range is supported by hardware.
*/
case MMC_VDD_34_35:
case MMC_VDD_35_36:
pwr = SDHCI_POWER_330;
break;
default:
WARN(1, "%s: Invalid vdd %#x\n",
mmc_hostname(host->mmc), vdd);
break;
}
}
if (host->pwr == pwr)
return;
host->pwr = pwr;
snps_sdhci_set_phy(host);
if (pwr == 0) {
sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
/*
if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
sdhci_runtime_pm_bus_off(host);
*/
} else {
/*
* Spec says that we should clear the power reg before setting
* a new value. Some controllers don't seem to like this though.
*/
if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
/*
* At least the Marvell CaFe chip gets confused if we set the
* voltage and set turn on power at the same time, so set the
* voltage first.
*/
if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
pwr |= SDHCI_POWER_ON;
sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
/*
if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
sdhci_runtime_pm_bus_on(host);
*/
/*
* Some controllers need an extra 10ms delay of 10ms before
* they can apply clock after applying power
*/
if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
mdelay(10);
}
}
static void dwcmshc_set_power(struct sdhci_host *host, unsigned char mode,
unsigned short vdd)
{
if (IS_ERR(host->mmc->supply.vmmc))
dwcmshc_set_power_noreg(host, mode, vdd);
else
sdhci_set_power_reg(host, mode, vdd);
}
static const struct sdhci_ops sdhci_dwcmshc_ops = {
.set_clock = sdhci_set_clock,
.set_power = dwcmshc_set_power,
.set_bus_width = sdhci_set_bus_width,
.set_uhs_signaling = dwcmshc_set_uhs_signaling,
.get_max_clock = sdhci_pltfm_clk_get_max_clock,
@@ -415,7 +575,7 @@ static const struct sdhci_ops sdhci_dwcmshc_ops = {
static const struct sdhci_pltfm_data sdhci_dwcmshc_pdata = {
.ops = &sdhci_dwcmshc_ops,
.quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
.quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN | SDHCI_QUIRK_SINGLE_POWER_WRITE,
.quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
};
@@ -463,6 +623,15 @@ static int dwcmshc_probe(struct platform_device *pdev)
priv->io_fixed_1v8 = true;
else
priv->io_fixed_1v8 = false;
/* start_signal_voltage_switch will try 3V3 first, when io fixed 1V8,
* use SDHCI_SIGNALING_180 ranther than SDHCI_SIGNALING_330 to avoid set to 3V3
* in sdhci_start_signal_voltage_switch.
*/
if(priv->io_fixed_1v8){
host->flags &=~SDHCI_SIGNALING_330;
host->flags |= SDHCI_SIGNALING_180;
}
if (device_property_present(&pdev->dev, "wprtn_ignore"))
priv->wprtn_ignore = true;
@@ -490,6 +659,7 @@ static int dwcmshc_probe(struct platform_device *pdev)
sdhci_get_of_property(pdev);
host->mmc_host_ops.request = dwcmshc_request;
host->mmc_host_ops.hs400_complete = dwcmshc_hs400_complete;
err = sdhci_add_host(host);
if (err)

1
drivers/net/phy/realtek.c
View File

@@ -635,6 +635,7 @@ static struct phy_driver realtek_drvs[] = {
.name = "RTL8211F Gigabit Ethernet",
.config_init = &rtl8211f_config_init,
.ack_interrupt = &rtl8211f_ack_interrupt,
.read_status = rtlgen_read_status,
.config_intr = &rtl8211f_config_intr,
.suspend = genphy_suspend,
.resume = rtl821x_resume,

128
drivers/nvmem/light-efuse.c
View File

@@ -37,6 +37,7 @@
#define SHADOW_RDATA6 0xd8
#define SHADOW_RDATA7 0xdc
#define TEE_SYS_EFUSE_LC_PRELD_OFF 0x64
#define TEE_SYS_EFUSE_DBG_KEY1_OFF 0x70
#define ENABLE_DFT_FUNC_MASK GENMASK(3, 0)
#define ENABLE_DFT_FUNC 0x5
@@ -837,14 +838,139 @@ exit:
return ret < 0 ? ret : count;
}
static ssize_t lc_preld_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct light_efuse_priv *priv = dev_get_drvdata(dev);
int ret;
u32 data;
ret = regmap_read(priv->teesys_regs, TEE_SYS_EFUSE_LC_PRELD_OFF, &data);
if (ret) {
dev_err(dev, "failed to read data from LC_PRELD area\n");
return ret;
}
return sprintf(buf, "0x%08x\n", data);
}
static ssize_t update_lc_store(struct device *dev,
struct device_attribute *attr,
const char *buf, size_t count)
{
struct light_efuse_priv *priv = dev_get_drvdata(dev);
int ret;
u32 value, data;
const char *p, *life_cycle = buf;
int len;
p = memchr(buf, '\n', count);
len = p ? p - buf : count;
dev_dbg(dev, "life_cycle: %s, buf: %s, len: %d\n", life_cycle, buf, len);
if (!strncmp(life_cycle, "LC_RMA", len)) {
/* If target life cycle is RMA, open permission in teesystem regs */
ret = regmap_read(priv->teesys_regs,
TEE_SYS_EFUSE_DBG_KEY1_OFF,
&data); /* Register from tee system */
if (ret) {
dev_err(dev, "failed to read data from DBG_KEY1 area\n");
return ret;
}
data &= ~0xf;
data |= 0x5;
ret = regmap_write(priv->teesys_regs,
TEE_SYS_EFUSE_DBG_KEY1_OFF,
data);
if (ret) {
dev_err(dev, "failed to write data to DBG_KEY1 area\n");
return ret;
}
value = 0x1A946F9B;
} else if (!strncmp(life_cycle, "LC_OEM", len))
value = 0x64EA9B8E;
else if (!strncmp(life_cycle, "LC_PRO", len))
value = 0xB0E047A8;
else if (!strncmp(life_cycle, "LC_DEV", len))
value = 0x59DD3BDF;
else if (!strncmp(life_cycle, "LC_RIP", len))
value = 0xEE45E8A7;
else if (!strncmp(life_cycle, "LC_KILL_KEY1", len))
value = 0x7D8E9CA1;
else if (!strncmp(life_cycle, "LC_KILL_KEY0", len))
value = 0xC29F604B;
else {
dev_err(dev, "invalid life cycle type!\n");
return -EINVAL;
}
/*
* Check permission:
* Check it every time to avoid wp0~3 are changed somewhere
*/
efuse_permission_magic_config(priv->base, cmd_perm_magic_num, CMD_UPDATE_LC);
/* Config life cycle */
efuse_life_cycle_para_config(priv->base, value);
/* set command */
ret = efuse_cmd_start(priv->base, CON_CMD_UP_LC);
if (ret)
goto exit;
/* Wait controller completed */
ret = efuse_idle_check(priv->base);
exit:
/* Check status, if there has error, reort and clear status */
ret |= efuse_status_check(priv->base);
if (ret)
dev_err(dev, "error occurs while starting write\n");
efuse_data_clear(priv->base);
if (strncmp(life_cycle, "LC_RMA", len))
goto out;
dev_info(dev, "set LC_RMA life cycle\n");
/* If target life cycle is RMA, close permission in teesystem regs */
ret = regmap_read(priv->teesys_regs,
TEE_SYS_EFUSE_DBG_KEY1_OFF,
&data); /* Register from tee system */
if (ret) {
dev_err(dev, "failed to read data from DBG_KEY1 area\n");
return ret;
}
data &= ~0xf;
data |= 0xa;
ret = regmap_write(priv->teesys_regs,
TEE_SYS_EFUSE_DBG_KEY1_OFF,
data);
if (ret) {
dev_err(dev, "failed to write data to DBG_KEY1 area\n");
return ret;
}
out:
return ret < 0 ? ret : count;
}
static DEVICE_ATTR_WO(rma_lc);
static DEVICE_ATTR_WO(rip_lc);
static DEVICE_ATTR_RW(efuse_nvmem);
static DEVICE_ATTR_RO(lc_preld);
static DEVICE_ATTR_WO(update_lc);
static struct attribute *light_efuse_sysfs_entries[] = {
&dev_attr_efuse_nvmem.attr,
&dev_attr_rip_lc.attr,
&dev_attr_rma_lc.attr,
&dev_attr_lc_preld.attr,
&dev_attr_update_lc.attr,
NULL
};
@@ -965,6 +1091,6 @@ static struct platform_driver light_efuse_driver = {
};
module_platform_driver(light_efuse_driver);
MODULE_AUTHOR("wei.liu <lw312886@alibaba-inc.com>");
MODULE_AUTHOR("wei.liu <lw312886@linux.alibaba.com>");
MODULE_DESCRIPTION("Thead light nvmem driver");
MODULE_LICENSE("GPL v2");

4
drivers/phy/synopsys/phy-dw-mipi-dphy.c
View File

@@ -473,7 +473,7 @@ static int dw_dphy_get_pll_cfg(struct dw_dphy *dphy,
vco_div = 1 << (range->vco_range >> 4);
fout = fout * vco_div;
pr_info("%s: vco_div = %u\n", __func__, vco_div);
pr_debug("%s: vco_div = %u\n", __func__, vco_div);
n_min = DIV_ROUND_UP_ULL(fin, FIN_DIV_N_FREQ_MAX * 1000);
n_max = DIV_ROUND_UP_ULL(fin, FIN_DIV_N_FREQ_MIN * 1000);
@@ -767,6 +767,6 @@ static struct platform_driver dw_dphy_driver = {
};
module_platform_driver(dw_dphy_driver);
MODULE_AUTHOR("You Xiao <youxiao.fc@alibaba-inc.com>");
MODULE_AUTHOR("You Xiao <youxiao.fc@linux.alibaba.com>");
MODULE_DESCRIPTION("Synopsys DesignWare MIPI DPHY driver");
MODULE_LICENSE("GPL");

Some files were not shown because too many files have changed in this diff Show More