10 Commits

Author SHA1 Message Date
thead_admin
6059b374a0 Linux_SDK_V1.5.4
Signed-off-by: thead_admin <occ_thead@service.alibaba.com>
2024-05-07 09:58:02 +00:00
thead_admin
a9b3178041 Linux_SDK_V1.4.2
Signed-off-by: thead_admin <occ_thead@service.alibaba.com>
2023-12-24 19:36:49 +08:00
thead_admin
c20ad6292d Linux_SDK_V1.3.3
Signed-off-by: thead_admin <occ_thead@service.alibaba.com>
2023-12-24 19:36:38 +08:00
thead_admin
f4327ba402 Linux_SDK_V1.2.1
Signed-off-by: thead_admin <occ_thead@service.alibaba.com>
2023-08-19 00:37:34 +08:00
jianghai
599b048690 eth: gmac: adapt to support DMA 32-bit in skb 2023-07-30 04:42:32 +08:00
thead_admin
b269dc8fa7 apply lpi4a patches 2023-07-30 04:42:27 +08:00
Han Gao
87e5c31f94 Linux_SDK_V1.2.0 2023-07-30 04:39:12 +08:00
thead_admin
ada47f394b Linux_SDK_V1.1.2 2023-03-05 22:36:24 +08:00
thead_admin
221913b496 Linux_SDK_V1.0.3 2023-01-04 13:12:21 +08:00
thead_admin
c20e64a982 Linux_SDK_V1.0.2 2022-11-22 15:53:40 +08:00
363 changed files with 25486 additions and 16895 deletions

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@@ -81,4 +81,4 @@ Example:
}; };
}; };
[1]. Documentation/devicetree/bindings/arm/idle-states.yaml [1]. Documentation/devicetree/bindings/cpu/idle-states.yaml

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@@ -101,7 +101,7 @@ properties:
bindings in [1]) must specify this property. bindings in [1]) must specify this property.
[1] Kernel documentation - ARM idle states bindings [1] Kernel documentation - ARM idle states bindings
Documentation/devicetree/bindings/arm/idle-states.yaml Documentation/devicetree/bindings/cpu/idle-states.yaml
patternProperties: patternProperties:
"^power-domain-": "^power-domain-":

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@@ -1,25 +1,30 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2 %YAML 1.2
--- ---
$id: http://devicetree.org/schemas/arm/idle-states.yaml# $id: http://devicetree.org/schemas/cpu/idle-states.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml#
title: ARM idle states binding description title: Idle states binding description
maintainers: maintainers:
- Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
- Anup Patel <anup@brainfault.org>
description: |+ description: |+
========================================== ==========================================
1 - Introduction 1 - Introduction
========================================== ==========================================
ARM systems contain HW capable of managing power consumption dynamically, ARM and RISC-V systems contain HW capable of managing power consumption
where cores can be put in different low-power states (ranging from simple wfi dynamically, where cores can be put in different low-power states (ranging
to power gating) according to OS PM policies. The CPU states representing the from simple wfi to power gating) according to OS PM policies. The CPU states
range of dynamic idle states that a processor can enter at run-time, can be representing the range of dynamic idle states that a processor can enter at
specified through device tree bindings representing the parameters required to run-time, can be specified through device tree bindings representing the
enter/exit specific idle states on a given processor. parameters required to enter/exit specific idle states on a given processor.
==========================================
2 - ARM idle states
==========================================
According to the Server Base System Architecture document (SBSA, [3]), the According to the Server Base System Architecture document (SBSA, [3]), the
power states an ARM CPU can be put into are identified by the following list: power states an ARM CPU can be put into are identified by the following list:
@@ -43,8 +48,23 @@ description: |+
The device tree binding definition for ARM idle states is the subject of this The device tree binding definition for ARM idle states is the subject of this
document. document.
==========================================
3 - RISC-V idle states
==========================================
On RISC-V systems, the HARTs (or CPUs) [6] can be put in platform specific
suspend (or idle) states (ranging from simple WFI, power gating, etc). The
RISC-V SBI v0.3 (or higher) [7] hart state management extension provides a
standard mechanism for OS to request HART state transitions.
The platform specific suspend (or idle) states of a hart can be either
retentive or non-rententive in nature. A retentive suspend state will
preserve HART registers and CSR values for all privilege modes whereas
a non-retentive suspend state will not preserve HART registers and CSR
values.
=========================================== ===========================================
2 - idle-states definitions 4 - idle-states definitions
=========================================== ===========================================
Idle states are characterized for a specific system through a set of Idle states are characterized for a specific system through a set of
@@ -211,10 +231,10 @@ description: |+
properties specification that is the subject of the following sections. properties specification that is the subject of the following sections.
=========================================== ===========================================
3 - idle-states node 5 - idle-states node
=========================================== ===========================================
ARM processor idle states are defined within the idle-states node, which is The processor idle states are defined within the idle-states node, which is
a direct child of the cpus node [1] and provides a container where the a direct child of the cpus node [1] and provides a container where the
processor idle states, defined as device tree nodes, are listed. processor idle states, defined as device tree nodes, are listed.
@@ -223,7 +243,7 @@ description: |+
just supports idle_standby, an idle-states node is not required. just supports idle_standby, an idle-states node is not required.
=========================================== ===========================================
4 - References 6 - References
=========================================== ===========================================
[1] ARM Linux Kernel documentation - CPUs bindings [1] ARM Linux Kernel documentation - CPUs bindings
@@ -238,9 +258,15 @@ description: |+
[4] ARM Architecture Reference Manuals [4] ARM Architecture Reference Manuals
http://infocenter.arm.com/help/index.jsp http://infocenter.arm.com/help/index.jsp
[6] ARM Linux Kernel documentation - Booting AArch64 Linux [5] ARM Linux Kernel documentation - Booting AArch64 Linux
Documentation/arm64/booting.rst Documentation/arm64/booting.rst
[6] RISC-V Linux Kernel documentation - CPUs bindings
Documentation/devicetree/bindings/riscv/cpus.yaml
[7] RISC-V Supervisor Binary Interface (SBI)
http://github.com/riscv/riscv-sbi-doc/riscv-sbi.adoc
properties: properties:
$nodename: $nodename:
const: idle-states const: idle-states
@@ -253,7 +279,7 @@ properties:
On ARM 32-bit systems this property is optional On ARM 32-bit systems this property is optional
This assumes that the "enable-method" property is set to "psci" in the cpu This assumes that the "enable-method" property is set to "psci" in the cpu
node[6] that is responsible for setting up CPU idle management in the OS node[5] that is responsible for setting up CPU idle management in the OS
implementation. implementation.
const: psci const: psci
@@ -265,8 +291,8 @@ patternProperties:
as follows. as follows.
The idle state entered by executing the wfi instruction (idle_standby The idle state entered by executing the wfi instruction (idle_standby
SBSA,[3][4]) is considered standard on all ARM platforms and therefore SBSA,[3][4]) is considered standard on all ARM and RISC-V platforms and
must not be listed. therefore must not be listed.
In addition to the properties listed above, a state node may require In addition to the properties listed above, a state node may require
additional properties specific to the entry-method defined in the additional properties specific to the entry-method defined in the
@@ -275,7 +301,27 @@ patternProperties:
properties: properties:
compatible: compatible:
const: arm,idle-state enum:
- arm,idle-state
- riscv,idle-state
arm,psci-suspend-param:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
power_state parameter to pass to the ARM PSCI suspend call.
Device tree nodes that require usage of PSCI CPU_SUSPEND function
(i.e. idle states node with entry-method property is set to "psci")
must specify this property.
riscv,sbi-suspend-param:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
suspend_type parameter to pass to the RISC-V SBI HSM suspend call.
This property is required in idle state nodes of device tree meant
for RISC-V systems. For more details on the suspend_type parameter
refer the SBI specifiation v0.3 (or higher) [7].
local-timer-stop: local-timer-stop:
description: description:
@@ -317,6 +363,8 @@ patternProperties:
description: description:
A string used as a descriptive name for the idle state. A string used as a descriptive name for the idle state.
additionalProperties: false
required: required:
- compatible - compatible
- entry-latency-us - entry-latency-us
@@ -658,4 +706,150 @@ examples:
}; };
}; };
- |
// Example 3 (RISC-V 64-bit, 4-cpu systems, two clusters):
cpus {
#size-cells = <0>;
#address-cells = <1>;
cpu@0 {
device_type = "cpu";
compatible = "riscv";
reg = <0x0>;
riscv,isa = "rv64imafdc";
mmu-type = "riscv,sv48";
cpu-idle-states = <&CPU_RET_0_0 &CPU_NONRET_0_0
&CLUSTER_RET_0 &CLUSTER_NONRET_0>;
cpu_intc0: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
interrupt-controller;
};
};
cpu@1 {
device_type = "cpu";
compatible = "riscv";
reg = <0x1>;
riscv,isa = "rv64imafdc";
mmu-type = "riscv,sv48";
cpu-idle-states = <&CPU_RET_0_0 &CPU_NONRET_0_0
&CLUSTER_RET_0 &CLUSTER_NONRET_0>;
cpu_intc1: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
interrupt-controller;
};
};
cpu@10 {
device_type = "cpu";
compatible = "riscv";
reg = <0x10>;
riscv,isa = "rv64imafdc";
mmu-type = "riscv,sv48";
cpu-idle-states = <&CPU_RET_1_0 &CPU_NONRET_1_0
&CLUSTER_RET_1 &CLUSTER_NONRET_1>;
cpu_intc10: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
interrupt-controller;
};
};
cpu@11 {
device_type = "cpu";
compatible = "riscv";
reg = <0x11>;
riscv,isa = "rv64imafdc";
mmu-type = "riscv,sv48";
cpu-idle-states = <&CPU_RET_1_0 &CPU_NONRET_1_0
&CLUSTER_RET_1 &CLUSTER_NONRET_1>;
cpu_intc11: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
interrupt-controller;
};
};
idle-states {
CPU_RET_0_0: cpu-retentive-0-0 {
compatible = "riscv,idle-state";
riscv,sbi-suspend-param = <0x10000000>;
entry-latency-us = <20>;
exit-latency-us = <40>;
min-residency-us = <80>;
};
CPU_NONRET_0_0: cpu-nonretentive-0-0 {
compatible = "riscv,idle-state";
riscv,sbi-suspend-param = <0x90000000>;
entry-latency-us = <250>;
exit-latency-us = <500>;
min-residency-us = <950>;
};
CLUSTER_RET_0: cluster-retentive-0 {
compatible = "riscv,idle-state";
riscv,sbi-suspend-param = <0x11000000>;
local-timer-stop;
entry-latency-us = <50>;
exit-latency-us = <100>;
min-residency-us = <250>;
wakeup-latency-us = <130>;
};
CLUSTER_NONRET_0: cluster-nonretentive-0 {
compatible = "riscv,idle-state";
riscv,sbi-suspend-param = <0x91000000>;
local-timer-stop;
entry-latency-us = <600>;
exit-latency-us = <1100>;
min-residency-us = <2700>;
wakeup-latency-us = <1500>;
};
CPU_RET_1_0: cpu-retentive-1-0 {
compatible = "riscv,idle-state";
riscv,sbi-suspend-param = <0x10000010>;
entry-latency-us = <20>;
exit-latency-us = <40>;
min-residency-us = <80>;
};
CPU_NONRET_1_0: cpu-nonretentive-1-0 {
compatible = "riscv,idle-state";
riscv,sbi-suspend-param = <0x90000010>;
entry-latency-us = <250>;
exit-latency-us = <500>;
min-residency-us = <950>;
};
CLUSTER_RET_1: cluster-retentive-1 {
compatible = "riscv,idle-state";
riscv,sbi-suspend-param = <0x11000010>;
local-timer-stop;
entry-latency-us = <50>;
exit-latency-us = <100>;
min-residency-us = <250>;
wakeup-latency-us = <130>;
};
CLUSTER_NONRET_1: cluster-nonretentive-1 {
compatible = "riscv,idle-state";
riscv,sbi-suspend-param = <0x91000010>;
local-timer-stop;
entry-latency-us = <600>;
exit-latency-us = <1100>;
min-residency-us = <2700>;
wakeup-latency-us = <1500>;
};
};
};
... ...

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@@ -87,6 +87,12 @@ properties:
- compatible - compatible
- interrupt-controller - interrupt-controller
cpu-idle-states:
$ref: '/schemas/types.yaml#/definitions/phandle-array'
description: |
List of phandles to idle state nodes supported
by this hart (see ./idle-states.yaml).
required: required:
- riscv,isa - riscv,isa
- interrupt-controller - interrupt-controller

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@@ -4614,6 +4614,20 @@ S: Supported
F: drivers/cpuidle/cpuidle-psci.h F: drivers/cpuidle/cpuidle-psci.h
F: drivers/cpuidle/cpuidle-psci-domain.c F: drivers/cpuidle/cpuidle-psci-domain.c
CPUIDLE DRIVER - DT IDLE PM DOMAIN
M: Ulf Hansson <ulf.hansson@linaro.org>
L: linux-pm@vger.kernel.org
S: Supported
F: drivers/cpuidle/dt_idle_genpd.c
F: drivers/cpuidle/dt_idle_genpd.h
CPUIDLE DRIVER - RISC-V SBI
M: Anup Patel <anup@brainfault.org>
L: linux-pm@vger.kernel.org
L: linux-riscv@lists.infradead.org
S: Maintained
F: drivers/cpuidle/cpuidle-riscv-sbi.c
CRAMFS FILESYSTEM CRAMFS FILESYSTEM
M: Nicolas Pitre <nico@fluxnic.net> M: Nicolas Pitre <nico@fluxnic.net>
S: Maintained S: Maintained

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@@ -21,25 +21,28 @@ config RISCV
select ARCH_HAS_GCOV_PROFILE_ALL select ARCH_HAS_GCOV_PROFILE_ALL
select ARCH_HAS_GIGANTIC_PAGE select ARCH_HAS_GIGANTIC_PAGE
select ARCH_HAS_KCOV select ARCH_HAS_KCOV
select ARCH_HAS_MMIOWB
select ARCH_HAS_PTE_SPECIAL select ARCH_HAS_PTE_SPECIAL
select ARCH_HAS_SET_DIRECT_MAP select ARCH_HAS_SET_DIRECT_MAP
select ARCH_HAS_SET_MEMORY select ARCH_HAS_SET_MEMORY
select ARCH_HAS_STRICT_KERNEL_RWX if MMU select ARCH_HAS_STRICT_KERNEL_RWX if MMU
select ARCH_HAS_STRICT_MODULE_RWX if MMU
select ARCH_HAS_DMA_PREP_COHERENT select ARCH_HAS_DMA_PREP_COHERENT
select ARCH_HAS_SYNC_DMA_FOR_CPU select ARCH_HAS_SYNC_DMA_FOR_CPU
select ARCH_HAS_SYNC_DMA_FOR_DEVICE select ARCH_HAS_SYNC_DMA_FOR_DEVICE
select ARCH_HAS_DMA_WRITE_COMBINE select ARCH_HAS_DMA_WRITE_COMBINE
select ARCH_HAS_DMA_MMAP_PGPROT select ARCH_HAS_DMA_MMAP_PGPROT
select ARCH_KEEP_MEMBLOCK
select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX
select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT
select ARCH_USE_QUEUED_SPINLOCKS
select ARCH_USE_QUEUED_RWLOCKS
select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU
select ARCH_WANT_FRAME_POINTERS select ARCH_WANT_FRAME_POINTERS
select ARCH_WANT_HUGE_PMD_SHARE if 64BIT select ARCH_WANT_HUGE_PMD_SHARE if 64BIT
select CLONE_BACKWARDS select CLONE_BACKWARDS
select CLINT_TIMER if !MMU select CLINT_TIMER if !MMU
select COMMON_CLK select COMMON_CLK
select CPU_PM if (SUSPEND || CPU_IDLE) select CPU_PM if CPU_IDLE || HIBERNATION
select COMPAT_BINFMT_ELF if BINFMT_ELF && COMPAT select COMPAT_BINFMT_ELF if BINFMT_ELF && COMPAT
select EDAC_SUPPORT select EDAC_SUPPORT
select DMA_DIRECT_REMAP select DMA_DIRECT_REMAP
@@ -416,6 +419,11 @@ config VECTOR_0_7
endchoice endchoice
config VLEN_256
bool "VECTOR VLEN 256"
depends on VECTOR
default n
config VECTOR_EMU config VECTOR_EMU
bool "VECTOR e64 emulate for c906 v1" bool "VECTOR e64 emulate for c906 v1"
depends on VECTOR depends on VECTOR
@@ -565,6 +573,18 @@ source "kernel/power/Kconfig"
config ARCH_SUSPEND_POSSIBLE config ARCH_SUSPEND_POSSIBLE
def_bool y def_bool y
config ARCH_HIBERNATION_POSSIBLE
def_bool y
config ARCH_HIBERNATION_HEADER
def_bool HIBERNATION
endmenu
menu "CPU Power Management"
source "drivers/cpuidle/Kconfig"
endmenu endmenu
source "arch/riscv/kvm/Kconfig" source "arch/riscv/kvm/Kconfig"

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@@ -19,6 +19,9 @@ config SOC_VIRT
select GOLDFISH select GOLDFISH
select RTC_DRV_GOLDFISH if RTC_CLASS select RTC_DRV_GOLDFISH if RTC_CLASS
select SIFIVE_PLIC select SIFIVE_PLIC
select PM_GENERIC_DOMAINS if PM
select PM_GENERIC_DOMAINS_OF if PM && OF
select RISCV_SBI_CPUIDLE if CPU_IDLE
help help
This enables support for QEMU Virt Machine. This enables support for QEMU Virt Machine.

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@@ -1,46 +1,50 @@
# SPDX-License-Identifier: GPL-2.0 # SPDX-License-Identifier: GPL-2.0
dtb-$(CONFIG_SOC_THEAD) += ice.dtb dtb-$(CONFIG_SOC_THEAD_ICE) += ice.dtb
dtb-$(CONFIG_SOC_THEAD) += light-fm-emu.dtb light_mpw.dtb dtb-$(CONFIG_SOC_THEAD_TH1520_MPW) += th1520_mpw.dtb
dtb-$(CONFIG_SOC_THEAD) += light-fm-emu-npu-fce.dtb dtb-$(CONFIG_SOC_THEAD_TH1520_EMU) += th1520-fm-emu.dtb
dtb-$(CONFIG_SOC_THEAD) += light-fm-emu-gpu.dtb dtb-$(CONFIG_SOC_THEAD_TH1520_EMU) += th1520-fm-emu-npu-fce.dtb
dtb-$(CONFIG_SOC_THEAD) += light-fm-emu-dsp.dtb dtb-$(CONFIG_SOC_THEAD_TH1520_EMU) += th1520-fm-emu-gpu.dtb
dtb-$(CONFIG_SOC_THEAD) += light-fm-emu-audio.dtb dtb-$(CONFIG_SOC_THEAD_TH1520_EMU) += th1520-fm-emu-dsp.dtb
dtb-$(CONFIG_SOC_THEAD) += light-fm-emu-hdmi.dtb dtb-$(CONFIG_SOC_THEAD_TH1520_EMU) += th1520-fm-emu-audio.dtb
dtb-$(CONFIG_SOC_THEAD) += light-fm-emu-dsi0-hdmi.dtb dtb-$(CONFIG_SOC_THEAD_TH1520_EMU) += th1520-fm-emu-hdmi.dtb
dtb-$(CONFIG_SOC_THEAD) += light-a-val.dtb light-a-val-sv.dtb dtb-$(CONFIG_SOC_THEAD_TH1520_EMU) += th1520-fm-emu-dsi0-hdmi.dtb
dtb-$(CONFIG_SOC_THEAD) += light-a-val-ddr2G.dtb light-a-val-ddr1G.dtb dtb-$(CONFIG_SOC_THEAD) += th1520-a-val.dtb th1520-a-val-sec.dtb
dtb-$(CONFIG_SOC_THEAD) += light-a-val-npu-fce.dtb dtb-$(CONFIG_SOC_THEAD) += th1520-a-val-crash.dtb
dtb-$(CONFIG_SOC_THEAD) += light-a-val-iso7816.dtb dtb-$(CONFIG_SOC_THEAD) += th1520-a-val-audio-i2s-8ch.dtb
dtb-$(CONFIG_SOC_THEAD) += light-a-val-nand.dtb dtb-$(CONFIG_SOC_THEAD) += th1520-a-val-audio-tdm.dtb
dtb-$(CONFIG_SOC_THEAD) += light-a-val-audio.dtb dtb-$(CONFIG_SOC_THEAD) += th1520-a-val-audio-spdif.dtb
dtb-$(CONFIG_SOC_THEAD) += light-a-val-dsi0.dtb light-a-val-dsi1.dtb light-a-val-hdmi.dtb light-a-val-dsi0-dsi1.dtb light-a-val-dsi0-hdmi.dtb light-a-val-dpi0.dtb light-a-val-dpi0-dpi1.dtb dtb-$(CONFIG_SOC_THEAD) += th1520-a-val-dsi0-hdmi.dtb
dtb-$(CONFIG_SOC_THEAD) += light-a-val-wcn.dtb dtb-$(CONFIG_SOC_THEAD) += th1520-a-val-dsi0-dsi1.dtb
dtb-$(CONFIG_SOC_THEAD) += light-a-val-gpio-keys.dtb dtb-$(CONFIG_SOC_THEAD_TH1520_DEV) += th1520-a-val-audio.dtb
dtb-$(CONFIG_SOC_THEAD) += light-a-val-khv.dtb dtb-$(CONFIG_SOC_THEAD_TH1520_DEV) += th1520-a-val-sv.dtb
dtb-$(CONFIG_SOC_THEAD) += light-a-val-sec.dtb dtb-$(CONFIG_SOC_THEAD_TH1520_DEV) += th1520-a-val-ddr2G.dtb th1520-a-val-ddr1G.dtb
dtb-$(CONFIG_SOC_THEAD) += light-a-val-miniapp-hdmi.dtb dtb-$(CONFIG_SOC_THEAD_TH1520_DEV) += th1520-a-val-npu-fce.dtb
dtb-$(CONFIG_SOC_THEAD) += light-a-product.dtb dtb-$(CONFIG_SOC_THEAD_TH1520_DEV) += th1520-a-val-iso7816.dtb
dtb-$(CONFIG_SOC_THEAD) += light-b-product.dtb dtb-$(CONFIG_SOC_THEAD_TH1520_DEV) += th1520-a-val-dsi0.dtb th1520-a-val-dsi1.dtb th1520-a-val-hdmi.dtb th1520-a-val-dsi0-hdmi-audio.dtb th1520-a-val-dpi0.dtb th1520-a-val-dpi0-dpi1.dtb
dtb-$(CONFIG_SOC_THEAD) += light-b-product-ddr1G.dtb dtb-$(CONFIG_SOC_THEAD_TH1520_DEV) += th1520-a-val-wcn.dtb
dtb-$(CONFIG_SOC_THEAD) += light-b-product-miniapp-hdmi.dtb dtb-$(CONFIG_SOC_THEAD_TH1520_DEV) += th1520-a-val-khv.dtb
dtb-$(CONFIG_SOC_THEAD) += light-a-val-full.dtb dtb-$(CONFIG_SOC_THEAD_TH1520_DEV) += th1520-a-val-miniapp-hdmi.dtb
dtb-$(CONFIG_SOC_THEAD) += light-ant-evt.dtb dtb-$(CONFIG_SOC_THEAD_TH1520_PRD) += th1520-a-product.dtb
dtb-$(CONFIG_SOC_THEAD) += light-ant-discrete.dtb dtb-$(CONFIG_SOC_THEAD_TH1520_DEV) += th1520-a-val-full.dtb
dtb-$(CONFIG_SOC_THEAD_TH1520_DEV) += th1520-a-ref.dtb th1520-a-ref-dsi0.dtb th1520-a-ref-dsi0-hdmi.dtb
# // temporary dtb for power gate dtb-$(CONFIG_SOC_THEAD) += th1520-b-product.dtb th1520-b-product-sec.dtb
dtb-$(CONFIG_SOC_THEAD) += light-a-val-powergate.dtb light-a-val-sv-powergate.dtb dtb-$(CONFIG_SOC_THEAD) += th1520-b-dsi.dtb
dtb-$(CONFIG_SOC_THEAD) += light-a-val-ddr2G-powergate.dtb light-a-val-ddr1G-powergate.dtb dtb-$(CONFIG_SOC_THEAD) += th1520-b-product-crash.dtb
dtb-$(CONFIG_SOC_THEAD) += light-a-val-npu-fce-powergate.dtb dtb-$(CONFIG_SOC_THEAD_TH1520_DEV) += th1520-b-product-ddr1G.dtb
dtb-$(CONFIG_SOC_THEAD) += light-a-val-iso7816-powergate.dtb dtb-$(CONFIG_SOC_THEAD_TH1520_DEV) += th1520-b-product-miniapp-hdmi.dtb
dtb-$(CONFIG_SOC_THEAD) += light-a-val-nand-powergate.dtb dtb-$(CONFIG_SOC_THEAD_TH1520_DEV) += th1520-b-ref.dtb
dtb-$(CONFIG_SOC_THEAD) += light-a-val-audio-powergate.dtb dtb-$(CONFIG_SOC_THEAD_TH1520_DEV) += th1520-b-power.dtb
dtb-$(CONFIG_SOC_THEAD) += light-a-val-dsi0-powergate.dtb light-a-val-dsi1-powergate.dtb light-a-val-hdmi-powergate.dtb light-a-val-dsi0-dsi1-powergate.dtb light-a-val-dsi0-hdmi-powergate.dtb light-a-val-dpi0-powergate.dtb light-a-val-dpi0-dpi1-powergate.dtb dtb-$(CONFIG_SOC_THEAD_TH1520_ANT) += th1520-ant-ref.dtb
dtb-$(CONFIG_SOC_THEAD) += light-a-val-wcn-powergate.dtb dtb-$(CONFIG_SOC_THEAD_TH1520_ANT) += th1520-ant-ref-crash.dtb th1520-ant-discrete-crash.dtb
dtb-$(CONFIG_SOC_THEAD) += light-a-val-khv-powergate.dtb dtb-$(CONFIG_SOC_THEAD_TH1520_DEV) += th1520-ant-discrete.dtb
dtb-$(CONFIG_SOC_THEAD) += light-a-val-sec-powergate.dtb dtb-$(CONFIG_SOC_THEAD_TH1520_DEV) += th1520-beagle.dtb
dtb-$(CONFIG_SOC_THEAD) += light-a-val-miniapp-hdmi-powergate.dtb dtb-$(CONFIG_SOC_THEAD) += th1520-lpi4a-product.dtb th1520-lpi4a-product-sec.dtb
dtb-$(CONFIG_SOC_THEAD) += light-a-product-powergate.dtb dtb-$(CONFIG_SOC_THEAD) += th1520-lpi4a-product-crash.dtb
dtb-$(CONFIG_SOC_THEAD) += light-b-product-powergate.dtb dtb-$(CONFIG_SOC_THEAD) += th1520-lpi4a-camera-tuning.dtb
dtb-$(CONFIG_SOC_THEAD) += light-b-product-ddr1G-powergate.dtb dtb-$(CONFIG_SOC_THEAD) += th1520-lpi4a-hx8279.dtb
dtb-$(CONFIG_SOC_THEAD) += light-a-val-full-powergate.dtb dtb-$(CONFIG_SOC_THEAD) += th1520-lpi4a-dsi0.dtb
dtb-$(CONFIG_SOC_THEAD) += light-a-val-android.dtb dtb-$(CONFIG_SOC_THEAD_TH1520_DEV) += th1520-lpi4a-ddr2G.dtb
dtb-$(CONFIG_SOC_THEAD_TH1520_ANDROID) += th1520-a-val-android.dtb
dtb-$(CONFIG_SOC_THEAD_FIRE) += fire-emu.dtb fire-emu-crash.dtb
dtb-$(CONFIG_SOC_THEAD_FIRE) += fire-emu-soc-base.dtb fire-emu-soc-c910x4.dtb fire-emu-gpu-dpu-dsi0.dtb fire-emu-vi-dsp-vo.dtb fire-emu-vi-vp-vo.dtb
dtb-$(CONFIG_SOC_THEAD_FIRE) += fire-emu-soc-base-sec.dtb

View File

@@ -1,399 +0,0 @@
/dts-v1/;
/ {
model = "T-HEAD c910 ice";
compatible = "thead,c910_ice";
#address-cells = <2>;
#size-cells = <2>;
memory@0 {
device_type = "memory";
/*
* Total memory size: 4GB (0x00000000 0x100000000)
* 0x00200000 - 0x0e0000000: 3407MB for Linux system
* 0xe0000000 - 0x100000000: 512MB for GPU
*/
reg = <0x0 0x200000 0x0 0xdfe00000>;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
timebase-frequency = <3000000>;
cpu@0 {
device_type = "cpu";
reg = <0>;
status = "okay";
compatible = "riscv";
riscv,isa = "rv64imafdcsu";
mmu-type = "riscv,sv39";
cpu-freq = "1.2Ghz";
cpu-icache = "64KB";
cpu-dcache = "64KB";
cpu-l2cache = "2MB";
cpu-tlb = "1024 4-ways";
cpu-cacheline = "64Bytes";
cpu-vector = "0.7.1";
cpu0_intc: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
interrupt-controller;
};
};
cpu@1 {
device_type = "cpu";
reg = <1>;
status = "okay";
compatible = "riscv";
riscv,isa = "rv64imafdcsu";
mmu-type = "riscv,sv39";
cpu-freq = "1.2Ghz";
cpu-icache = "64KB";
cpu-dcache = "64KB";
cpu-l2cache = "2MB";
cpu-tlb = "1024 4-ways";
cpu-cacheline = "64Bytes";
cpu-vector = "0.7.1";
cpu1_intc: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
interrupt-controller;
};
};
};
soc {
#address-cells = <2>;
#size-cells = <2>;
compatible = "simple-bus";
ranges;
reset: reset-sample {
compatible = "thead,reset-sample";
plic-delegate = <0x3 0xf01ffffc>;
using-csr-reset;
csr-copy = <
0x7c0 0x7c1 0x7c2 0x7c3 0x7c5 0x7cc
0x3b0 0x3b1 0x3b2 0x3b3
0x3b4 0x3b5 0x3b6 0x3b7
0x3a0
>;
};
clint0: clint@3f4000000 {
compatible = "riscv,clint0";
interrupts-extended = <
&cpu0_intc 3 &cpu0_intc 7
&cpu1_intc 3 &cpu1_intc 7
>;
reg = <0x3 0xf4000000 0x0 0x04000000>;
clint,has-no-64bit-mmio;
};
intc: interrupt-controller@3f0000000 {
#interrupt-cells = <1>;
compatible = "riscv,plic0";
interrupt-controller;
interrupts-extended = <
&cpu0_intc 0xffffffff &cpu0_intc 9
&cpu1_intc 0xffffffff &cpu1_intc 9
>;
reg = <0x3 0xf0000000 0x0 0x04000000>;
reg-names = "control";
riscv,max-priority = <7>;
riscv,ndev = <80>;
};
dummy_apb: apb-clock {
compatible = "fixed-clock";
clock-frequency = <62500000>;
clock-output-names = "dummy_apb";
#clock-cells = <0>;
};
dummy_ahb: ahb-clock {
compatible = "fixed-clock";
clock-frequency = <250000000>;
clock-output-names = "dummy_ahb";
#clock-cells = <0>;
};
dummy_axi: axi-clock {
compatible = "fixed-clock";
clock-frequency = <500000000>;
clock-output-names = "dummy_axi";
#clock-cells = <0>;
};
dummy_gmac: gmac-clock {
compatible = "fixed-clock";
clock-frequency = <1000000000>;
clock-output-names = "dummy_gmac";
#clock-cells = <0>;
};
dummy_clk_sdio: dummy-clk-sdio {
compatible = "fixed-clock";
clock-frequency = <150000000>;
clock-output-names = "dummy_clk_sdio";
#clock-cells = <0>;
};
usb: dwc3@3fff10000 {
compatible = "snps,dwc3";
reg = <0x3 0xfff10000 0x0 0x10000>;
interrupt-parent = <&intc>;
interrupts = <44>;
clocks = <&dummy_ahb>, <&dummy_ahb>, <&dummy_ahb>;
clock-names = "ref", "bus_early", "suspend";
maximum-speed = "super-speed";
dr_mode = "peripheral";
snps,usb3_lpm_capable;
snps,dis_u3_susphy_quirk;
};
gpio0: gpio@3fff71000 {
compatible = "snps,dw-apb-gpio";
reg = <0x3 0xfff71000 0x0 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
/* GPIO0[0-31] */
gpio0_porta: gpio0-controller@0 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
snps,nr-gpios = <32>;
reg = <0>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&intc>;
interrupts = <27>;
};
/* GPIO0[32-63] */
gpio0_portb: gpio0-controller@1 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
snps,nr-gpios = <32>;
reg = <1>;
};
};
gpio1: gpio@3fff72000 {
compatible = "snps,dw-apb-gpio";
reg = <0x3 0xfff72000 0x0 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
/* GPIO1[0-31] */
gpio1_porta: gpio1-controller@0 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
snps,nr-gpios = <32>;
reg = <0>;
};
/* GPIO1[32-63] */
gpio1_portb: gpio1-controller@1 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
snps,nr-gpios = <32>;
reg = <1>;
};
/* GPIO1[64-95] */
gpio1_portc: gpio1-controller@2 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
snps,nr-gpios = <32>;
reg = <2>;
};
};
gpio-leds {
compatible = "gpio-leds";
led0 { /* GPIO0[11] - UART2_TXD */
label = "led0";
gpios = <&gpio0_porta 11 1>;
default-state = "off";
};
};
gpio-keys {
compatible = "gpio-keys";
/* autorepeat; */
key_0 { /* GPIO0[10] - UART2_RXD */
gpios = <&gpio0_porta 10 1>;
linux,code = <59>;
label = "key_0";
};
};
i2c@3fff74000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,designware-i2c-ice";
reg = <0x3 0xfff74000 0x0 0x1000>;
interrupts = <21>;
interrupt-parent = <&intc>;
clocks = <&dummy_apb>;
clock-frequency = <400000>;
eeprom@50 {
compatible = "atmel,24c64";
reg = <0x50>;
pagesize = <32>;
};
goodix_ts@14 {
#gpio-cells = <2>;
compatible = "goodix,gt917s";
reg = <0x14>;
interrupt-parent = <&gpio0_porta>;
interrupts = <31 0>;
irq-gpios = <&gpio0_porta 31 0>;
reset-gpios = <&gpio0_porta 30 0>;
touchscreen-size-x = <720>;
touchscreen-size-y = <1280>;
};
};
serial@3fff73000 {
compatible = "snps,dw-apb-uart";
reg = <0x3 0xfff73000 0x0 0x400>;
interrupt-parent = <&intc>;
interrupts = <23>;
clocks = <&dummy_apb>;
clock-names = "baudclk";
reg-shift = <2>;
reg-io-width = <4>;
};
pmu: pmu {
interrupt-parent = <&cpu0_intc>;
interrupts = <17>;
compatible = "riscv,c910_pmu";
};
dmac0: dmac@3fffd0000 {
compatible = "snps,axi-dma-1.01a";
reg = <0x3 0xfffd0000 0x0 0x1000>;
interrupt-parent = <&intc>;
interrupts = <65>;
clocks = <&dummy_axi>, <&dummy_ahb>;
clock-names = "core-clk", "cfgr-clk";
dma-channels = <8>;
snps,block-size = <65536 65536 65536 65536 65536 65536 65536 65536>;
snps,priority = <0 1 2 3 4 5 6 7>;
snps,dma-masters = <1>;
snps,data-width = <4>;
snps,axi-max-burst-len = <16>;
status = "disabled";
};
sdhc0: sdhc0@3fffb0000 {
compatible = "snps,dw-mshc";
reg = <0x3 0xfffb0000 0x0 0x1000>;
interrupt-parent = <&intc>;
interrupts = <37>;
clocks = <&dummy_clk_sdio>, <&dummy_clk_sdio>;
clock-names = "ciu", "biu";
num-slots = <1>;
card-detect-delay = <200>;
cap-mmc-highspeed;
cap-cmd23;
non-removable;
bus-width = <8>;
};
sdhc1: sdhc1@3fffa0000 {
compatible = "snps,dw-mshc";
reg = <0x3 0xfffa0000 0x0 0x1000>;
interrupt-parent = <&intc>;
interrupts = <38>;
clocks = <&dummy_clk_sdio>, <&dummy_clk_sdio>;
clock-names = "ciu", "biu";
num-slots = <1>;
card-detect-delay = <200>;
cap-sd-highspeed;
bus-width = <4>;
};
stmmac_axi_setup: stmmac-axi-config {
snps,wr_osr_lmt = <3>;
snps,rd_osr_lmt = <3>;
snps,blen = <16 8 4 0 0 0 0>;
};
gmac: ethernet@3fffc0000 {
compatible = "thead,dwmac";
reg = < 0x3 0xfffc0000 0x0 0x2000
0x3 0xfe83025c 0x0 0x4
0x3 0xfe83031c 0x0 0x4
0x3 0xfff770c0 0x0 0x1c>;
reg-names = "gmac", "phy_if_reg", "txclk_dir_reg", "clk_mgr_reg";
interrupt-parent = <&intc>;
interrupts = <40>;
interrupt-names = "macirq";
clocks = <&dummy_ahb>, <&dummy_gmac>;
clock-names = "stmmaceth", "gmac_pll_clk";
snps,pbl = <32>;
snps,fixed-burst;
snps,axi-config = <&stmmac_axi_setup>;
phy-mode = "rgmii-id";
rx-clk-delay = <0x1f>; /* for RGMII */
tx-clk-delay = <0x1f>; /* for RGMII */
phy-handle = <&eth_phy_0>;
mdio0 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,dwmac-mdio";
eth_phy_0: ethernet-phy@0 {
reg = <0>;
};
};
};
gpu: gpu@3fff27000 {
compatible = "verisilicon,gc8000ul";
reg = <0x3 0xfff27000 0x0 0x1000>;
interrupt-parent = <&intc>;
interrupts = <63>;
contiguous-base = <0x0 0xe0000000>;
contiguous-size = <0x0 0x20000000>;
};
watchdog: watchdog@3fffe3000 {
compatible = "ice,ice-wdt";
reg = <0x3 0xfffe3000 0x0 0x1000>;
interrupts = <20>;
};
dpu: dpu@3fff28000 {
compatible = "verisilicon,dc8000-fb";
reg = <0x3 0xfff28000 0x0 0x8000>;
interrupt-parent = <&intc>;
interrupts = <64>;
};
};
chosen {
/* bootargs = "console=ttyS0,115200 crashkernel=256M-:128M c910_mmu_v1"; */
/* linux,initrd-start = <0x2000000>; */
/* linux,initrd-end = <0x17000000>; */
bootargs = "console=ttyS0,115200 rdinit=/sbin/init root=/dev/mmcblk0p4 rw rootfstype=ext4 blkdevparts=mmcblk0:2M(table),2M(dtb),60M(kernel),-(rootfs) clk_ignore_unused loglevel=7 rootwait crashkernel=256M-:128M c910_mmu_v1";
stdout-path = "serial0@3fff73000:115200";
};
};

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@@ -1,8 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2021 Alibaba Group Holding Limited.
*/
#include "light-a-product.dts"
#include "light-powergate.dts"

File diff suppressed because it is too large Load Diff

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@@ -1,111 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2021 Alibaba Group Holding Limited.
*/
/dts-v1/;
#include "light-a-val-dsi0.dts"
&dpu_enc1 {
ports {
/delete-node/ port@0;
};
};
&disp1_out {
remote-endpoint = <&hdmi_tx_in>;
};
&sdhci1 {
status = "okay";
};
&wcn_bt {
status = "okay";
};
&wcn_wifi {
status = "okay";
};
&lightsound {
status = "okay";
simple-audio-card,widgets =
"Microphone", "Mic Jack",
"Speaker", "Speaker",
"Headphone", "Headphone Jack";
simple-audio-card,routing =
"Headphone Jack", "HP_L",
"Headphone Jack", "HP_R",
"Speaker", "SPK_LP",
"Speaker", "SPK_LN",
"Speaker", "SPK_RP",
"Speaker", "SPK_RN",
"Mic Jack","MICB",
"LINPUT1", "Mic Jack",
"LINPUT3", "Mic Jack";
simple-audio-card,dai-link@0 { /* I2S - CODEC */
reg = <0>;
format = "i2s";
cpu {
sound-dai = <&light_i2s 0>;
};
codec {
sound-dai = <&codec>;
};
};
simple-audio-card,dai-link@1 { /* I2S - HDMI */
reg = <1>;
format = "i2s";
cpu {
sound-dai = <&light_i2s 1>;
};
codec {
sound-dai = <&dummy_codec 2>;
};
};
};
&light_i2s {
status = "okay";
};
&hdmi_tx {
status = "okay";
port@0 {
/* input */
hdmi_tx_in: endpoint {
remote-endpoint = <&disp1_out>;
};
};
};
/ {
firmware {
android {
compatible = "android,firmware";
boot_devices = "soc/ffe7080000.sdhci";
fstab {
compatible = "android,fstab";
system {
compatible = "android,system";
dev = "/dev/block/platform/soc/ffe7080000.sdhci/by-name/system";
type = "ext4";
mnt_flags = "ro,barrier=1";
fsmgr_flags = "wait";
};
vendor {
compatible = "android,vendor";
dev = "/dev/block/platform/soc/ffe7080000.sdhci/by-name/vendor";
type = "ext4";
mnt_flags = "ro,barrier=1";
fsmgr_flags = "wait";
};
};
};
};
};

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@@ -1,8 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2021 Alibaba Group Holding Limited.
*/
#include "light-a-val-audio.dts"
#include "light-powergate.dts"

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@@ -1,8 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2021 Alibaba Group Holding Limited.
*/
#include "light-a-val-ddr1G.dts"
#include "light-powergate.dts"

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@@ -1,21 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2022 Alibaba Group Holding Limited.
*/
#include "light-a-val-ddr2G.dts"
/ {
model = "T-HEAD Light VAL configuration for 1GB DDR board";
compatible = "thead,light-val", "thead,light-val-ddr1G", "thead,light";
memory@0 {
device_type = "memory";
reg = <0x0 0x00000000 0x0 0x40000000>;
};
};
&cmamem {
size = <0 0x8c00000>;
alloc-ranges = <0 0x35000000 0 0x3dc00000>;
};

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@@ -1,8 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2021 Alibaba Group Holding Limited.
*/
#include "light-a-val-ddr2G.dts"
#include "light-powergate.dts"

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@@ -1,21 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2022 Alibaba Group Holding Limited.
*/
#include "light-a-val.dts"
/ {
model = "T-HEAD Light VAL configuration for 2GB DDR board";
compatible = "thead,light-val", "thead,light-val-ddr2G", "thead,light";
memory@0 {
device_type = "memory";
reg = <0x0 0x00000000 0x0 0x80000000>;
};
};
&facelib_mem {
reg = <0x0 0x33000000 0 0x02000000>;
no-map;
};

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@@ -1,8 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2021 Alibaba Group Holding Limited.
*/
#include "light-a-val-dpi0-dpi1.dts"
#include "light-powergate.dts"

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@@ -1,40 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2022 Alibaba Group Holding Limited.
*/
/dts-v1/;
#include "light-a-val-dpi0.dts"
/ {
dpi_panel1: dpi-panel@1 {
compatible = "light,dummy-panel";
port {
dpi1_in: endpoint {
remote-endpoint = <&enc1_out>;
};
};
};
};
&dpu_enc1 {
compatible = "verisilicon,dpi-encoder";
status = "okay";
ports {
/* output */
port@1 {
reg = <1>;
enc1_out: endpoint {
remote-endpoint = <&dpi1_in>;
};
};
};
};
&dpu {
status = "okay";
};

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@@ -1,8 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2021 Alibaba Group Holding Limited.
*/
#include "light-a-val-dpi0.dts"
#include "light-powergate.dts"

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@@ -1,44 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2022 Alibaba Group Holding Limited.
*/
/dts-v1/;
#include "light-a-val.dts"
/ {
display-subsystem {
status = "okay";
};
dpi_panel0: dpi-panel@0 {
compatible = "light,dummy-panel";
port {
dpi0_in: endpoint {
remote-endpoint = <&enc0_out>;
};
};
};
};
&dpu_enc0 {
compatible = "verisilicon,dpi-encoder";
status = "okay";
ports {
/* output */
port@1 {
reg = <1>;
enc0_out: endpoint {
remote-endpoint = <&dpi0_in>;
};
};
};
};
&dpu {
status = "okay";
};

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@@ -1,8 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2021 Alibaba Group Holding Limited.
*/
#include "light-a-val-dsi0-dsi1.dts"
#include "light-powergate.dts"

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@@ -1,64 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2021 Alibaba Group Holding Limited.
*/
/dts-v1/;
#include "light-a-val-dsi0.dts"
&dpu_enc1 {
status = "okay";
ports {
/* output */
port@1 {
reg = <1>;
enc1_out: endpoint {
remote-endpoint = <&dsi1_in>;
};
};
};
};
&dsi1 {
status = "okay";
};
&dhost_1 {
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dsi1_in: endpoint {
remote-endpoint = <&enc1_out>;
};
};
port@1 {
reg = <1>;
dsi1_out: endpoint {
remote-endpoint = <&panel1_in>;
};
};
};
panel1@0 {
compatible = "txd,dy800qwxpab";
reg = <0>;
reset-gpio = <&gpio1_porta 9 1>; /* active low */
vdd1v8-supply = <&lcd1_1v8>;
vspn5v7-supply = <&lcd1_5v7>;
port {
panel1_in: endpoint {
remote-endpoint = <&dsi1_out>;
};
};
};
};

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@@ -1,8 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2021 Alibaba Group Holding Limited.
*/
#include "light-a-val-dsi0-hdmi.dts"
#include "light-powergate.dts"

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@@ -1,29 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2021 Alibaba Group Holding Limited.
*/
/dts-v1/;
#include "light-a-val-dsi0.dts"
&dpu_enc1 {
ports {
/delete-node/ port@0;
};
};
&disp1_out {
remote-endpoint = <&hdmi_tx_in>;
};
&hdmi_tx {
status = "okay";
port@0 {
/* input */
hdmi_tx_in: endpoint {
remote-endpoint = <&disp1_out>;
};
};
};

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@@ -1,8 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2021 Alibaba Group Holding Limited.
*/
#include "light-a-val-dsi0.dts"
#include "light-powergate.dts"

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@@ -1,75 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2021 Alibaba Group Holding Limited.
*/
/dts-v1/;
#include "light-a-val.dts"
/ {
display-subsystem {
status = "okay";
};
};
&dpu_enc0 {
status = "okay";
ports {
/* output */
port@1 {
reg = <1>;
enc0_out: endpoint {
remote-endpoint = <&dsi0_in>;
};
};
};
};
&dpu {
status = "okay";
};
&dsi0 {
status = "okay";
};
&dhost_0 {
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dsi0_in: endpoint {
remote-endpoint = <&enc0_out>;
};
};
port@1 {
reg = <1>;
dsi0_out: endpoint {
remote-endpoint = <&panel0_in>;
};
};
};
panel0@0 {
compatible = "txd,dy800qwxpab";
reg = <0>;
backlight = <&lcd0_backlight>;
reset-gpio = <&gpio1_porta 5 1>; /* active low */
vdd1v8-supply = <&lcd0_1v8>;
vspn5v7-supply = <&lcd0_5v7>;
port {
panel0_in: endpoint {
remote-endpoint = <&dsi0_out>;
};
};
};
};

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@@ -1,8 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2021 Alibaba Group Holding Limited.
*/
#include "light-a-val-dsi1.dts"
#include "light-powergate.dts"

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@@ -1,75 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2021 Alibaba Group Holding Limited.
*/
/dts-v1/;
#include "light-a-val.dts"
/ {
display-subsystem {
status = "okay";
};
};
&dpu_enc1 {
status = "okay";
ports {
/* output */
port@1 {
reg = <1>;
enc1_out: endpoint {
remote-endpoint = <&dsi1_in>;
};
};
};
};
&dpu {
status = "okay";
};
&dsi1 {
status = "okay";
};
&dhost_1 {
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dsi1_in: endpoint {
remote-endpoint = <&enc1_out>;
};
};
port@1 {
reg = <1>;
dsi1_out: endpoint {
remote-endpoint = <&panel1_in>;
};
};
};
panel1@0 {
compatible = "txd,dy800qwxpab";
reg = <0>;
backlight = <&lcd1_backlight>;
reset-gpio = <&gpio1_porta 9 1>; /* active low */
vdd1v8-supply = <&lcd1_1v8>;
vspn5v7-supply = <&lcd1_5v7>;
port {
panel1_in: endpoint {
remote-endpoint = <&dsi1_out>;
};
};
};
};

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@@ -1,8 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2021 Alibaba Group Holding Limited.
*/
#include "light-a-val-dsp0-dsp1.dts"
#include "light-powergate.dts"

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@@ -1,13 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2021 Alibaba Group Holding Limited.
*/
/dts-v1/;
#include "light-a-val.dts"
&xtensa_dsp1 {
status = "okay";
};

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@@ -1,8 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2021 Alibaba Group Holding Limited.
*/
#include "light-a-val-full.dts"
#include "light-powergate.dts"

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@@ -1,161 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2022 Alibaba Group Holding Limited.
*/
#include "light-a-val.dts"
/ {
display-subsystem {
status = "okay";
};
};
&dpu_enc0 {
status = "okay";
ports {
/* output */
port@1 {
reg = <1>;
enc0_out: endpoint {
remote-endpoint = <&dsi0_in>;
};
};
};
};
&dpu_enc1 {
ports {
/delete-node/ port@0;
};
};
&dpu {
status = "okay";
};
&dsi0 {
status = "okay";
};
&dhost_0 {
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dsi0_in: endpoint {
remote-endpoint = <&enc0_out>;
};
};
port@1 {
reg = <1>;
dsi0_out: endpoint {
remote-endpoint = <&panel0_in>;
};
};
};
panel0@0 {
compatible = "txd,dy800qwxpab";
reg = <0>;
backlight = <&lcd0_backlight>;
reset-gpio = <&gpio1_porta 5 1>; /* active low */
vdd1v8-supply = <&lcd0_1v8>;
vspn5v7-supply = <&lcd0_5v7>;
port {
panel0_in: endpoint {
remote-endpoint = <&dsi0_out>;
};
};
};
};
&disp1_out {
remote-endpoint = <&hdmi_tx_in>;
};
&hdmi_tx {
status = "okay";
port@0 {
/* input */
hdmi_tx_in: endpoint {
remote-endpoint = <&disp1_out>;
};
};
};
&lightsound {
status = "okay";
simple-audio-card,dai-link@0 { /* I2S - AUDIO SYS CODEC 8156*/
reg = <0>;
format = "i2s";
cpu {
sound-dai = <&i2s0 0>;
};
codec {
sound-dai = <&es8156_audio_codec>;
};
};
simple-audio-card,dai-link@1 { /* I2S - AUDIO SYS CODEC 7210*/
reg = <1>;
format = "i2s";
cpu {
sound-dai = <&i2s3 0>;
};
codec {
sound-dai = <&es7210_audio_codec>;
};
};
};
&light_i2s {
status = "okay";
};
&i2s0 {
status = "okay";
};
&i2s3 {
status = "okay";
};
&qspi0 {
status = "okay";
};
&qspi1 {
status = "okay";
};
&uart2 {
status = "okay";
};
&uart3 {
status = "okay";
};
&sdhci1 {
status = "okay";
};
&wcn_bt {
status = "okay";
};
&wcn_wifi {
status = "okay";
};

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@@ -1,15 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2021 Alibaba Group Holding Limited.
*/
#include "light-a-val.dts"
/ {
model = "T-HEAD Light FM GPIO-KEYS VAL board";
compatible = "thead,light-val-gpio-keys", "thead,light";
};
&gpio_keys {
status = "okay";
};

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@@ -1,8 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2021 Alibaba Group Holding Limited.
*/
#include "light-a-val-hdmi.dts"
#include "light-powergate.dts"

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@@ -1,8 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2021 Alibaba Group Holding Limited.
*/
#include "light-a-val-iso7816.dts"
#include "light-powergate.dts"

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@@ -1,10 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2021 Alibaba Group Holding Limited.
*/
#include "light-a-val.dts"
&iso7816 {
status = "okay";
};

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@@ -1,8 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2021 Alibaba Group Holding Limited.
*/
#include "light-a-val-khv.dts"
#include "light-powergate.dts"

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@@ -1,21 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2021 Alibaba Group Holding Limited.
*/
#include "light-a-val.dts"
&resmem {
#address-cells = <2>;
#size-cells = <2>;
ranges;
/* 512M for guest memory */
guestmem: memory@50000000 {
reg = <0x0 0x50000000 0x0 0x20000000>;
};
};
&khvhost {
memory-region = <&guestmem>;
};

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@@ -1,126 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2021 Alibaba Group Holding Limited.
*/
/dts-v1/;
#include "light-a-val.dts"
/ {
display-subsystem {
status = "okay";
};
};
&dpu_enc0 {
status = "okay";
ports {
/* output */
port@1 {
reg = <1>;
enc0_out: endpoint {
remote-endpoint = <&dsi0_in>;
};
};
};
};
&dpu {
status = "okay";
};
&dsi0 {
status = "okay";
};
&dhost_0 {
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dsi0_in: endpoint {
remote-endpoint = <&enc0_out>;
};
};
port@1 {
reg = <1>;
dsi0_out: endpoint {
remote-endpoint = <&panel0_in>;
};
};
};
panel0@0 {
compatible = "txd,dy800qwxpab";
reg = <0>;
backlight = <&lcd0_backlight>;
reset-gpio = <&gpio1_porta 5 1>; /* active low */
vdd1v8-supply = <&lcd0_1v8>;
vspn5v7-supply = <&lcd0_5v7>;
port {
panel0_in: endpoint {
remote-endpoint = <&dsi0_out>;
};
};
};
};
&lightsound {
status = "okay";
simple-audio-card,dai-link@0 { /* I2S - AUDIO SYS CODEC 8156*/
reg = <0>;
format = "i2s";
cpu {
sound-dai = <&i2s0 0>;
};
codec {
sound-dai = <&es8156_audio_codec>;
};
};
simple-audio-card,dai-link@1 { /* I2S - AUDIO SYS CODEC 7210*/
reg = <1>;
format = "i2s";
cpu {
sound-dai = <&i2s3 0>;
};
codec {
sound-dai = <&es7210_audio_codec>;
};
};
};
&light_i2s {
status = "okay";
};
&i2s0 {
status = "okay";
};
&i2s3 {
status = "okay";
};
&sdhci1 {
status = "okay";
};
&wcn_bt {
status = "okay";
};
&wcn_wifi {
status = "okay";
};

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@@ -1,8 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2021 Alibaba Group Holding Limited.
*/
#include "light-a-val-miniapp-hdmi.dts"
#include "light-powergate.dts"

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@@ -1,90 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2021 Alibaba Group Holding Limited.
*/
/dts-v1/;
#include "light-a-val.dts"
/ {
display-subsystem {
status = "okay";
};
};
&dpu_enc1 {
ports {
/delete-node/ port@0;
};
};
&disp1_out {
remote-endpoint = <&hdmi_tx_in>;
};
&dpu {
status = "okay";
};
&hdmi_tx {
status = "okay";
port@0 {
/* input */
hdmi_tx_in: endpoint {
remote-endpoint = <&disp1_out>;
};
};
};
&lightsound {
status = "okay";
simple-audio-card,dai-link@0 { /* I2S - AUDIO SYS CODEC 8156*/
reg = <0>;
format = "i2s";
cpu {
sound-dai = <&i2s0 0>;
};
codec {
sound-dai = <&es8156_audio_codec>;
};
};
simple-audio-card,dai-link@1 { /* I2S - AUDIO SYS CODEC 7210*/
reg = <1>;
format = "i2s";
cpu {
sound-dai = <&i2s3 0>;
};
codec {
sound-dai = <&es7210_audio_codec>;
};
};
};
&light_i2s {
status = "okay";
};
&i2s0 {
status = "okay";
};
&i2s3 {
status = "okay";
};
&sdhci1 {
status = "okay";
};
&wcn_bt {
status = "okay";
};
&wcn_wifi {
status = "okay";
};

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@@ -1,8 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2021 Alibaba Group Holding Limited.
*/
#include "light-a-val-nand.dts"
#include "light-powergate.dts"

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@@ -1,14 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2021 Alibaba Group Holding Limited.
*/
#include "light-a-val.dts"
&qspi0 {
status = "okay";
};
&qspi1 {
status = "okay";
};

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@@ -1,12 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2021 Alibaba Group Holding Limited.
*/
#include "light-a-val-npu-fce.dts"
#include "light-powergate.dts"
&npu {
power-domains = <&pd LIGHT_AON_NPU_PD>;
};

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@@ -1,28 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2021 Alibaba Group Holding Limited.
*/
#include "light-a-val.dts"
/ {
model = "T-HEAD Light FM NPU&FCE on VAL board";
compatible = "thead,light-val-npu-fce", "thead,light";
};
&facelib_mem {
reg = <0x0 0xd0000000 0 0x20000000>;
no-map;
};
&npu {
vha_clk_rate = <1000000000>;
status = "okay";
};
&fce {
memory-region = <&facelib_mem>;
status = "okay";
};

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@@ -1,8 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2021 Alibaba Group Holding Limited.
*/
#include "light-a-val.dts"
#include "light-powergate.dts"

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@@ -1,8 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2021 Alibaba Group Holding Limited.
*/
#include "light-a-val-sec.dts"
#include "light-powergate.dts"

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@@ -1,8 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2021 Alibaba Group Holding Limited.
*/
#include "light-a-val-sv.dts"
#include "light-powergate.dts"

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@@ -1,8 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2021 Alibaba Group Holding Limited.
*/
#include "light-a-val-wcn.dts"
#include "light-powergate.dts"

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@@ -1,20 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2021 Alibaba Group Holding Limited.
*/
/dts-v1/;
#include "light-a-val.dts"
&sdhci1 {
status = "okay";
};
&wcn_bt {
status = "okay";
};
&wcn_wifi {
status = "okay";
};

File diff suppressed because it is too large Load Diff

File diff suppressed because it is too large Load Diff

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@@ -1,14 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2021 Alibaba Group Holding Limited.
*/
#include "light-b-product-ddr1G.dts"
#include "light-powergate.dts"
&soc_vdd18_lcd0_en_reg {
/delete-property/regulator-always-on;
};
&soc_lcd0_bias_en_reg {
/delete-property/regulator-always-on;
};

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@@ -1,21 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2022 Alibaba Group Holding Limited.
*/
#include "light-b-product.dts"
/ {
model = "T-HEAD Light-B VAL configuration for 1GB DDR board";
compatible = "thead,light-val", "thead,light-val-ddr1G", "thead,light";
memory@0 {
device_type = "memory";
reg = <0x0 0x00000000 0x0 0x40000000>;
};
};
&cmamem {
size = <0 0x8c00000>;
alloc-ranges = <0 0x35000000 0 0x3dc00000>;
};

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@@ -1,28 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2021 Alibaba Group Holding Limited.
*/
/dts-v1/;
#include "light-b-product.dts"
&dpu_enc0 {
status = "disabled";
};
&dsi0 {
status = "disabled";
};
&dhost_0 {
status = "disabled";
};
&wcn_bt {
status = "okay";
};
&wcn_wifi {
status = "okay";
};

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@@ -1,16 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2021 Alibaba Group Holding Limited.
*/
#include "light-b-product.dts"
#include "light-powergate.dts"
&soc_vdd18_lcd0_en_reg {
/delete-property/regulator-always-on;
};
&soc_lcd0_bias_en_reg {
/delete-property/regulator-always-on;
};

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@@ -1,8 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2021 Alibaba Group Holding Limited.
*/
#include "light-b-product-sec.dts"
#include "light-powergate.dts"

File diff suppressed because it is too large Load Diff

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@@ -1,19 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2021 Alibaba Group Holding Limited.
*/
#include "light-fm-emu.dts"
/ {
model = "T-HEAD Light FM EMP Audio FPGA board";
compatible = "thead,light-fm-emu-audio", "thead,light";
};
&lightsound {
status = "okay";
};
&light_i2s {
status = "okay";
};

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@@ -1,16 +0,0 @@
#include "light-fm-emu-dsi0.dts"
&disp1_out {
remote-endpoint = <&hdmi_tx_in>;
};
&hdmi_tx {
status = "okay";
port@0 {
/* input */
hdmi_tx_in: endpoint {
remote-endpoint = <&disp1_out>;
};
};
};

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@@ -1,64 +0,0 @@
#include "light-fm-emu.dts"
/ {
display-subsystem {
status = "okay";
};
};
&dpu_enc0 {
status = "okay";
ports {
/* output */
port@1 {
reg = <1>;
enc0_out: endpoint {
remote-endpoint = <&dsi0_in>;
};
};
};
};
&dpu {
status = "okay";
};
&dsi0 {
status = "okay";
};
&dhost_0 {
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dsi0_in: endpoint {
remote-endpoint = <&enc0_out>;
};
};
port@1 {
reg = <1>;
dsi0_out: endpoint {
remote-endpoint = <&panel_in>;
};
};
};
panel@0 {
compatible = "hlt,hpk070h275";
reg = <0>;
port {
panel_in: endpoint {
remote-endpoint = <&dsi0_out>;
};
};
};
};

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@@ -1,34 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2021 Alibaba Group Holding Limited.
*/
#include "light-fm-emu.dts"
/ {
model = "T-HEAD Light FM EMU DSP FPGA board";
compatible = "thead,light-fm-emu-dsp", "thead,light";
chosen {
linux,initrd-end = <0x0 0x1B000000>;
};
};
&resmem {
dsp_mem: memory@70000000 {
reg = <0x0 0x70000000 0 0x40000000>;
no-map;
};
};
&xtensa_dsp {
status = "okay";
};
&xtensa_dsp0 {
status = "okay";
};
&xtensa_dsp1 {
status = "disabled";
};

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@@ -1,20 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2021 Alibaba Group Holding Limited.
*/
#include "light-fm-emu.dts"
/ {
model = "T-HEAD Light FM EMU GPU FPGA board";
compatible = "thead,light-fm-emu-gpu", "thead,light";
chosen {
linux,initrd-end = <0x0 0x18000000>;
};
};
&gpu {
status = "okay";
};

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@@ -1,26 +0,0 @@
#include "light-fm-emu.dts"
/ {
display-subsystem {
status = "okay";
};
};
&disp1_out {
remote-endpoint = <&hdmi_tx_in>;
};
&dpu {
status = "okay";
};
&hdmi_tx {
status = "okay";
port@0 {
/* input */
hdmi_tx_in: endpoint {
remote-endpoint = <&disp1_out>;
};
};
};

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@@ -1,37 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2021 Alibaba Group Holding Limited.
*/
#include "light-fm-emu.dts"
/ {
model = "T-HEAD Light FM EMU NPU&FCE FPGA board";
compatible = "thead,light-fm-emu-npu-fce", "thead,light";
chosen {
linux,initrd-end = <0x0 0x1B000000>;
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
facelib_mem: memory@e0000000 {
reg = <0x1 0xe0000000 0 0x20000000>;
no-map;
};
};
};
&npu {
vha_clk_rate = <13000000>;
status = "okay";
};
&fce {
memory-region = <&facelib_mem>;
status = "okay";
};

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@@ -1,511 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2021 Alibaba Group Holding Limited.
*/
/dts-v1/;
#include "light-emu.dtsi"
/ {
model = "T-HEAD Light FM EMU FPGA board";
compatible = "thead,light-fm-emu", "thead,light";
chosen {
bootargs = "console=ttyS0,115200 crashkernel=256M-:128M earlycon sram=0xffe0000000,0x180000";
linux,initrd-start = <0x0 0x2000000>;
linux,initrd-end = <0x0 0x4600000>;
stdout-path = "serial0:115200n8";
};
keys {
compatible = "gpio-keys";
key0 {
label = "key0";
gpios = <&gpio1_porta 7 1>; /* GPIO_ACTIVE_LOW: 1 */
linux,code = <59>; /* KEY_F1: 59 */
status = "okay";
};
};
leds {
compatible = "gpio-leds";
led0 {
label = "led0";
gpios = <&gpio1_porta 8 0>; /* GPIO_ACTIVE_HIGH: 0 */
default-state = "off";
};
};
iopmp {
compatible = "thead,light-iopmp";
/* config#1: multiple valid regions */
iopmp_emmc: IOPMP_EMMC {
regions = <0x000000 0x100000>,
<0x100000 0x200000>;
attr = <0xFFFFFFFF>;
dummy_slave= <0x800000>;
};
/* config#2: iopmp bypass */
iopmp_sdio0: IOPMP_SDIO0 {
bypass_en;
};
/* config#3: iopmp default region set */
iopmp_sdio1: IOPMP_SDIO1 {
attr = <0xFFFFFFFF>;
is_default_region;
};
iopmp_usb0: IOPMP_USB0 {
attr = <0xFFFFFFFF>;
is_default_region;
};
iopmp_ao: IOPMP_AO {
is_default_region;
};
iopmp_aud: IOPMP_AUD {
is_default_region;
};
iopmp_chip_dbg: IOPMP_CHIP_DBG {
is_default_region;
};
iopmp_eip120i: IOPMP_EIP120I {
is_default_region;
};
iopmp_eip120ii: IOPMP_EIP120II {
is_default_region;
};
iopmp_eip120iii: IOPMP_EIP120III {
is_default_region;
};
iopmp_isp0: IOPMP_ISP0 {
is_default_region;
};
iopmp_isp1: IOPMP_ISP1 {
is_default_region;
};
iopmp_dsp: IOPMP_DSP {
is_default_region;
};
iopmp_dw200: IOPMP_DW200 {
is_default_region;
};
iopmp_venc: IOPMP_VENC {
is_default_region;
};
iopmp_vdec: IOPMP_VDEC {
is_default_region;
};
iopmp_g2d: IOPMP_G2D {
is_default_region;
};
iopmp_fce: IOPMP_FCE {
is_default_region;
};
iopmp_npu: IOPMP_NPU {
is_default_region;
};
iopmp0_dpu: IOPMP0_DPU {
bypass_en;
};
iopmp1_dpu: IOPMP1_DPU {
bypass_en;
};
iopmp_gpu: IOPMP_GPU {
is_default_region;
};
iopmp_gmac1: IOPMP_GMAC1 {
is_default_region;
};
iopmp_gmac2: IOPMP_GMAC2 {
is_default_region;
};
iopmp_dmac: IOPMP_DMAC {
is_default_region;
};
iopmp_tee_dmac: IOPMP_TEE_DMAC {
is_default_region;
};
};
mbox_910t_client1: mbox_910t_client1 {
compatible = "thead,light-mbox-client";
mbox-names = "902";
mboxes = <&mbox_910t 1 0>;
status = "disabled";
};
mbox_910t_client2: mbox_910t_client2 {
compatible = "thead,light-mbox-client";
mbox-names = "906";
mboxes = <&mbox_910t 2 0>;
status = "disabled";
};
lightsound: lightsound@1 {
compatible = "simple-audio-card";
simple-audio-card,name = "Light-Sound-Card";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
simple-audio-card,dai-link@0 { /* I2S - CODEC */
reg = <0>;
format = "i2s";
cpu {
sound-dai = <&light_i2s 0>;
};
codec {
sound-dai = <&dummy_codec 2>;
};
};
simple-audio-card,dai-link@1 { /* I2S - HDMI */
reg = <1>;
format = "i2s";
cpu {
sound-dai = <&light_i2s 1>;
};
codec {
sound-dai = <&dummy_codec 2>;
};
};
};
dummy_codec: dummy_codec {
#sound-dai-cells = <1>;
compatible = "linux,bt-sco";
status = "okay";
};
};
&i2c0 {
clock-frequency = <100000>;
status = "okay";
eeprom@50 {
compatible = "atmel,24c32";
reg = <0x50>;
pagesize = <32>;
};
};
&spi0 {
num-cs = <2>;
cs-gpios = <&gpio2_porta 15 0>, // GPIO_ACTIVE_HIGH: 0
<&gpio2_porta 23 0>; // GPIO_ACTIVE_LOW: 1
status = "okay";
spi_norflash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "winbond,w25q64", "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <8000000>;
w25q,fast-read;
};
spidev@1 {
compatible = "spidev";
#address-cells = <1>;
#size-cells = <1>;
reg = <1>;
spi-max-frequency = <12500000>;
};
};
&uart0 {
clock-frequency = <50000000>;
};
&qspi0 {
num-cs = <2>;
cs-gpios = <&gpio2_porta 3 0>, // GPIO_ACTIVE_HIGH: 0
<&gpio2_porta 26 0>;
status = "okay";
spi-flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spi-nand";
spi-max-frequency = <10000000>;
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
reg = <0>;
partition@0 {
label = "ubi1";
reg = <0x00000000 0x08000000>;
};
};
spidev@1 {
compatible = "spidev";
#address-cells = <1>;
#size-cells = <1>;
reg = <1>;
spi-max-frequency = <6250000>;
};
};
&gmac0 {
max-speed = <100>;
phy-mode = "mii";
phy-handle = <&phy_88E1111_0>;
status = "okay";
mdio0 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,dwmac-mdio";
phy_88E1111_0: ethernet-phy@0 {
reg = <0x0 0x0>;
};
};
};
&gmac1 {
max-speed = <100>;
phy-mode = "mii";
phy-handle = <&phy_88E1111_1>;
status = "disabled";
mdio0 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,dwmac-mdio";
phy_88E1111_1: ethernet-phy@0 {
reg = <0x0 0x0>;
};
};
};
&emmc {
max-frequency = <50000000>;
non-removable;
no-sdio;
no-sd;
bus-width = <8>;
status = "okay";
};
&sdhci0 {
max-frequency = <50000000>;
no-1-8-v;
bus-width = <4>;
status = "okay";
};
&padctrl0_apsys {
light-fm-evb {
/*
* Pin Configuration Node:
* Format: <pin_id mux_node config>
*/
pinctrl_uart0: uart0grp {
thead,pins = <
FM_UART0_TXD 0x0 0x72
FM_UART0_RXD 0x0 0x72
>;
};
pinctrl_spi0: spi0grp {
thead,pins = <
FM_SPI_CSN 0x0 0x72
>;
};
pinctrl_qspi0: qspi0grp {
thead,pins = <
FM_QSPI0_CSN0 0x0 0x72
>;
};
};
};
&padctrl1_apsys {
light-fm-evb {
/*
* Pin Configuration Node:
* Format: <pin_id mux_node config>
*/
pinctrl_uart3: uart3grp {
thead,pins = <
FM_UART3_TXD 0x0 0x72
FM_UART3_RXD 0x0 0x72
>;
};
pinctrl_uart4: uart4grp {
thead,pins = <
FM_UART4_TXD 0x0 0x72
FM_UART4_RXD 0x0 0x72
FM_UART4_CTSN 0x0 0x72
FM_UART4_RTSN 0x0 0x72
>;
};
};
};
&padctrl_aosys {
light-fm-evb {
/*
* Pin Configuration Node:
* Format: <pin_id mux_node config>
*/
pinctrl_audiopa1: audiopa1_grp {
thead,pins = <
FM_AUDIO_PA1 0x3 0x72
>;
};
pinctrl_audiopa2: audiopa2_grp {
thead,pins = <
FM_AUDIO_PA2 0x0 0x72
>;
};
};
};
&i2c2 {
status = "okay";
};
&isp0 {
status = "okay";
};
&isp1 {
status = "okay";
};
&isp_ry0 {
status = "okay";
};
&dewarp {
status = "okay";
};
&dec400_isp0 {
status = "okay";
};
&dec400_isp1 {
status = "okay";
};
&dec400_isp2 {
status = "okay";
};
&bm_visys {
status = "okay";
};
&bm_csi0 {
status = "okay";
};
&vi_pre {
status = "okay";
};
&vvcam_sensor0 {
sensor_name = "OV5693";
status = "okay";
};
&video{
status = "okay";
piplane0 {
pipline_id = <0>;
status = "okay";
sensor0 {
subdev_name = "vivcam";
idx = <0>;
csi_idx = <0>;
path_type = "SENSOR_VGA_RAW10_LINER";
};
/*
csi0 {
subdev_name = "bm_csi";
idx = <0>;
};
*/
dma {
subdev_name = "vipre";
idx = <0>;
path_type = "VIPRE_CSI0_ISP0";
};
isp {
subdev_name = "isp";
idx = <0>;
path_type = "ISP_MI_PATH_PP";
};
dsp {
subdev_name = "dsp";
idx = <0>;
path_type = "DSP_PATH_ISP_RY";
};
ry {
subdev_name = "ry";
idx = <0>;
path_type = "ISP_RY_MI_PATH_MP";
};
dw {
subdev_name = "dw";
idx = <0>;
path_type = "DW_PATH_MEM_DW_SC_MEM";
};
};
};
&vdec {
status = "okay";
};
&venc {
status = "okay";
};
&isp_venc_shake {
status = "okay";
};
&vidmem {
status = "okay";
};

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@@ -1,99 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2021 Alibaba Group Holding Limited.
*/
&npu {
power-domains = <&pd LIGHT_AON_NPU_PD>;
};
&gpu {
power-domains = <&pd LIGHT_AON_GPU_PD>;
};
&vdec {
power-domains = <&pd LIGHT_AON_VDEC_PD>;
};
&venc {
power-domains = <&pd LIGHT_AON_VENC_PD>;
};
&xtensa_dsp0 {
power-domains = <&pd LIGHT_AON_DSP0_PD>;
clocks = <&dspsys_clk_gate CLKGEN_DSP0_PCLK>, <&dspsys_clk_gate CLKGEN_DSP0_CCLK>;
clock-names = "pclk", "cclk";
};
&xtensa_dsp1 {
power-domains = <&pd LIGHT_AON_DSP1_PD>;
clocks = <&dspsys_clk_gate CLKGEN_DSP1_PCLK>, <&dspsys_clk_gate CLKGEN_DSP1_CCLK>;
clock-names = "pclk", "cclk";
};
&isp0 {
clocks = <&visys_clk_gate LIGHT_CLKGEN_ISP0_ACLK>,
<&visys_clk_gate LIGHT_CLKGEN_ISP0_HCLK>,
<&visys_clk_gate LIGHT_CLKGEN_ISP0_PIXELCLK>,
<&visys_clk_gate LIGHT_CLKGEN_ISP0_CLK>;
clock-names = "aclk", "hclk", "isp0_pclk", "cclk";
};
&isp1 {
clocks = <&visys_clk_gate LIGHT_CLKGEN_ISP0_ACLK>,
<&visys_clk_gate LIGHT_CLKGEN_ISP0_HCLK>,
<&visys_clk_gate LIGHT_CLKGEN_ISP0_PIXELCLK>,
<&visys_clk_gate LIGHT_CLKGEN_ISP1_CLK>,
<&visys_clk_gate LIGHT_CLKGEN_ISP1_PIXELCLK>;
clock-names = "aclk", "hclk", "isp0_pclk", "cclk", "isp1_pclk";
};
&isp_ry0 {
clocks = <&visys_clk_gate LIGHT_CLKGEN_ISP_RY_ACLK>,
<&visys_clk_gate LIGHT_CLKGEN_ISP_RY_HCLK>,
<&visys_clk_gate LIGHT_CLKGEN_ISP_RY_CCLK>;
clock-names = "aclk", "hclk", "cclk";
};
&dewarp {
clocks = <&visys_clk_gate LIGHT_CLKGEN_DW200_ACLK>,
<&visys_clk_gate LIGHT_CLKGEN_DW200_HCLK>,
<&visys_clk_gate LIGHT_CLKGEN_DW200_CLK_VSE>,
<&visys_clk_gate LIGHT_CLKGEN_DW200_CLK_DWE>;
clock-names = "aclk", "hclk", "vseclk", "dweclk";
};
&bm_csi0 { //CSI2
clocks = <&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI0_PCLK>,
<&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI0_PIXCLK>,
<&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI0_CFG_CLK>,
<&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI1_CFG_CLK>,
<&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI2_CFG_CLK>;
clock-names = "pclk", "pixclk", "cfg_clk0", "cfg_clk1", "cfg_clk2";
};
&bm_csi1 { //CSI2X2_B
clocks = <&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI1_PCLK>,
<&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI1_PIXCLK>,
<&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI0_CFG_CLK>,
<&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI1_CFG_CLK>,
<&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI2_CFG_CLK>;
clock-names = "pclk", "pixclk", "cfg_clk0", "cfg_clk1", "cfg_clk2";
};
&bm_csi2 { //CSI2X2_A
clocks = <&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI2_PCLK>,
<&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI2_PIXCLK>,
<&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI0_CFG_CLK>,
<&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI1_CFG_CLK>,
<&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI2_CFG_CLK>;
clock-names = "pclk", "pixclk", "cfg_clk0", "cfg_clk1", "cfg_clk2";
};
&vi_pre {
clocks = <&visys_clk_gate LIGHT_CLKGEN_VIPRE_ACLK>,
<&visys_clk_gate LIGHT_CLKGEN_VIPRE_PCLK>,
<&visys_clk_gate LIGHT_CLKGEN_VIPRE_PIXELCLK>;
clock-names ="aclk", "pclk", "pixclk";
};

View File

@@ -1,259 +0,0 @@
/dts-v1/;
/ {
model = "T-HEAD c910 light mpw";
compatible = "thead,c910_light_mpw";
#address-cells = <2>;
#size-cells = <2>;
memory@0 {
device_type = "memory";
reg = <0x0 0x00200000 0x0 0xf0000000>;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
timebase-frequency = <0x2dc6c0>;
cpu@0 {
device_type = "cpu";
reg = <0>;
status = "okay";
compatible = "riscv";
riscv,isa = "rv64imafdcvsu";
mmu-type = "riscv,sv39";
cpu-freq = "1.5Ghz";
cpu-icache = "64KB";
cpu-dcache = "64KB";
cpu-l2cache = "2MB";
cpu-tlb = "1024 4-ways";
cpu-cacheline = "64Bytes";
cpu-vector = "0.7.1";
cpu0_intc: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
interrupt-controller;
};
};
cpu@1 {
device_type = "cpu";
reg = <1>;
status = "okay";
compatible = "riscv";
riscv,isa = "rv64imafdcvsu";
mmu-type = "riscv,sv39";
cpu-freq = "1.5Ghz";
cpu-icache = "64KB";
cpu-dcache = "64KB";
cpu-l2cache = "2MB";
cpu-tlb = "1024 4-ways";
cpu-cacheline = "64Bytes";
cpu-vector = "0.7.1";
cpu1_intc: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
interrupt-controller;
};
};
cpu@2 {
device_type = "cpu";
reg = <2>;
status = "okay";
compatible = "riscv";
riscv,isa = "rv64imafdcvsu";
mmu-type = "riscv,sv39";
cpu-freq = "1.5Ghz";
cpu-icache = "64KB";
cpu-dcache = "64KB";
cpu-l2cache = "2MB";
cpu-tlb = "1024 4-ways";
cpu-cacheline = "64Bytes";
cpu-vector = "0.7.1";
cpu2_intc: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
interrupt-controller;
};
};
cpu@3 {
device_type = "cpu";
reg = <3>;
status = "okay";
compatible = "riscv";
riscv,isa = "rv64imafdcvsu";
mmu-type = "riscv,sv39";
cpu-freq = "1.5Ghz";
cpu-icache = "64KB";
cpu-dcache = "64KB";
cpu-l2cache = "2MB";
cpu-tlb = "1024 4-ways";
cpu-cacheline = "64Bytes";
cpu-vector = "0.7.1";
cpu3_intc: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
interrupt-controller;
};
};
};
soc {
#address-cells = <2>;
#size-cells = <2>;
compatible = "simple-bus";
ranges;
reset: reset-sample {
compatible = "thead,reset-sample";
plic-delegate = <0xff 0xd81ffffc>;
using-csr-reset;
csr-copy = <
0x7c0 0x7c1 0x7c2 0x7c3 0x7c5 0x7cc
0x3b0 0x3b1 0x3b2 0x3b3
0x3b4 0x3b5 0x3b6 0x3b7
0x3a0
>;
};
clint0: clint@ffdc000000 {
compatible = "riscv,clint0";
interrupts-extended = <
&cpu0_intc 3 &cpu0_intc 7
&cpu1_intc 3 &cpu1_intc 7
&cpu2_intc 3 &cpu2_intc 7
&cpu3_intc 3 &cpu3_intc 7
>;
reg = <0xff 0xdc000000 0x0 0x04000000>;
clint,has-no-64bit-mmio;
};
intc: interrupt-controller@ffd8000000 {
#interrupt-cells = <1>;
compatible = "riscv,plic0";
interrupt-controller;
interrupts-extended = <
&cpu0_intc 0xffffffff &cpu0_intc 9
&cpu1_intc 0xffffffff &cpu1_intc 9
&cpu2_intc 0xffffffff &cpu2_intc 9
&cpu3_intc 0xffffffff &cpu3_intc 9
>;
reg = <0xff 0xd8000000 0x0 0x08000000>;
reg-names = "control";
riscv,max-priority = <7>;
riscv,ndev = <80>;
};
clocks {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
dummy_apb: apb-clock {
compatible = "fixed-clock";
clock-frequency = <62500000>;
clock-output-names = "dummy_apb";
#clock-cells = <0>;
};
dummy_clock_sdhci: sdhci-clock {
compatible = "fixed-clock";
reg = <4>; /* Not address, just for index */
clock-frequency = <198000000>;
clock-output-names = "dummy_clock_sdhci";
#clock-cells = <0>;
};
dummy_clock_gmac: gmac-clock {
compatible = "fixed-clock";
clock-frequency = <1000000000>;
clock-output-names = "dummy_clock_gmac";
#clock-cells = <0>;
};
};
serial@ffe7014000 {
compatible = "snps,dw-apb-uart";
reg = <0xff 0xe7014000 0x0 0x4000>;
interrupt-parent = <&intc>;
interrupts = <36>;
clocks = <&dummy_apb>;
clock-names = "baudclk";
reg-shift = <2>;
reg-io-width = <4>;
};
stmmac_axi_setup: stmmac-axi-config {
snps,wr_osr_lmt = <3>;
snps,rd_osr_lmt = <3>;
snps,blen = <16 8 4 0 0 0 0>;
};
gmac: ethernet@ffe7070000 {
compatible = "snps,dwmac";
reg = <0xff 0xe7070000 0x0 0x2000>;
interrupt-parent = <&intc>;
interrupts = <66>;
interrupt-names = "macirq";
clocks = <&dummy_clock_gmac>;
clock-names = "stmmaceth";
snps,pbl = <32>;
snps,fixed-burst;
snps,axi-config = <&stmmac_axi_setup>;
phy-mode = "rgmii-txid";
phy-handle = <&phy_88E1111>;
mdio0 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,dwmac-mdio";
phy_88E1111: ethernet-phy@0 {
reg = <0x1>;
};
};
};
emmc: sdhci@ffe7080000 {
compatible = "snps,dwcmshc-sdhci-light-mpw";
reg = <0xff 0xe7080000 0x0 0x10000
0xff 0xEF014060 0x0 0x4>;
interrupt-parent = <&intc>;
interrupts = <62>;
interrupt-names = "sdhciirq";
clocks = <&dummy_clock_sdhci>;
clock-names = "core";
max-frequency = <198000000>;
non-removable;
is_emmc;
no-sdio;
no-sd;
no-1-8-v;
bus-width = <8>;
status = "okay";
};
sdcard: sd@ffe7090000 {
compatible = "snps,dwcmshc-sdhci-light-mpw";
reg = <0xff 0xe7090000 0x0 0x10000
0xff 0xEF014064 0x0 0x4>;
interrupt-parent = <&intc>;
interrupts = <64>;
interrupt-names = "sdhci0irq";
clocks = <&dummy_clock_sdhci>;
clock-names = "core";
max-frequency = <198000000>;
bus-width = <4>;
status = "okay";
};
pmu: pmu {
interrupt-parent = <&cpu0_intc>;
interrupts = <17>;
compatible = "riscv,c910_pmu";
};
};
chosen {
bootargs = "console=ttyS0,115200 root=PARTUUID=80a5a8e9-c744-491a-93c1-4f4194fd690b rootfstype=ext4 rdinit=/sbin/init rootwait rw earlyprintk clk_ignore_unused loglevel=7 eth=00:a0:a0:a0:a0:a1";
stdout-path = "/soc/serial@ffe7014000:115200";
};
};

View File

@@ -0,0 +1,53 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2021 Alibaba Group Holding Limited.
*/
#include "th1520-a-val.dtsi"
/ {
model = "T-HEAD Light FM Audio VAL board";
compatible = "thead,light-val-audio-i2s-8ch", "thead,light";
};
&lightsound_i2s_8ch {
status = "okay";
};
&i2s0 {
status = "okay";
};
&i2s_8ch_sd0 {
status = "okay";
};
&i2s_8ch_sd1 {
status = "okay";
};
&i2s_8ch_sd2 {
status = "okay";
};
&i2s_8ch_sd3 {
status = "okay";
};
&es8156_audio_codec {
status = "okay";
};
&es7210_audio_codec_adc0 {
status = "okay";
channels-max = <8>;
};
&es7210_audio_codec_adc1 {
status = "okay";
channels-max = <8>;
};
&audio_aw87519_pa {
status = "okay";
};

View File

@@ -0,0 +1,18 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2021 Alibaba Group Holding Limited.
*/
#include "th1520-a-val.dtsi"
&spdif0 {
status = "okay";
};
&spdif1 {
status = "okay";
};
&lightsound_spdif {
status = "okay";
};

View File

@@ -0,0 +1,62 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2021 Alibaba Group Holding Limited.
*/
#include "th1520-a-val.dtsi"
&tdm_slot1 {
status = "okay";
};
&tdm_slot2 {
status = "okay";
};
&tdm_slot3 {
status = "okay";
};
&tdm_slot4 {
status = "okay";
};
&tdm_slot5 {
status = "okay";
};
&tdm_slot6 {
status = "okay";
};
&tdm_slot7 {
status = "okay";
};
&tdm_slot8 {
status = "okay";
};
&es8156_audio_codec {
status = "okay";
};
&es7210_adc2 {
status = "okay";
};
&es7210_adc3 {
status = "okay";
};
&lightsound_tdm {
status = "okay";
};
&i2s0 {
status = "okay";
};
&audio_aw87519_pa {
status = "okay";
};

View File

@@ -0,0 +1,334 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2021-2022 Alibaba Group Holding Limited.
*/
/ {
lightsound: lightsound@1 {
compatible = "simple-audio-card";
simple-audio-card,name = "Light-Sound-Card";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
simple-audio-card,widgets = "Speaker", "Speaker";
simple-audio-card,routing =
"Speaker", "AW87519 VO",
"AW87519 IN", "ES8156 ROUT";
simple-audio-card,aux-devs = <&audio_aw87519_pa>;
simple-audio-card,dai-link@0 { /* I2S - AUDIO SYS CODEC 8156*/
reg = <0>;
format = "i2s";
cpu {
sound-dai = <&i2s0 0>;
};
codec {
sound-dai = <&es8156_audio_codec>;
};
};
simple-audio-card,dai-link@1 { /* I2S - AUDIO SYS CODEC 7210*/
reg = <1>;
format = "i2s";
cpu {
sound-dai = <&i2s_8ch_sd2 2>;
};
codec {
sound-dai = <&es7210_audio_codec_adc0>;
};
};
};
lightsound_spdif: lightsound@2 {
compatible = "simple-audio-card";
simple-audio-card,name = "Light-Sound-Card";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
simple-audio-card,dai-link@0 { /* SPDIF0 */
reg = <1>;
format = "i2s";
cpu {
sound-dai = <&spdif0>;
};
codec {
sound-dai = <&dummy_codec>;
};
};
simple-audio-card,dai-link@1 { /* SPDIF1 */
reg = <1>;
format = "i2s";
cpu {
sound-dai = <&spdif1>;
};
codec {
sound-dai = <&dummy_codec>;
};
};
};
lightsound_tdm: lightsound@3 {
compatible = "simple-audio-card";
simple-audio-card,name = "Light-Sound-Card";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
simple-audio-card,widgets = "Speaker", "Speaker";
simple-audio-card,routing =
"Speaker", "AW87519 VO",
"AW87519 IN", "ES8156 ROUT";
simple-audio-card,aux-devs = <&audio_aw87519_pa>;
simple-audio-card,dai-link@0 { /* I2S - AUDIO SYS CODEC 8156*/
reg = <0>;
format = "i2s";
cpu {
sound-dai = <&i2s0 0>;
};
codec {
sound-dai = <&es8156_audio_codec>;
};
};
simple-audio-card,dai-link@1 { /* TDM - AUDIO SYS CODEC 7210*/
reg = <1>;
format = "dsp_b";
cpu {
sound-dai = <&tdm_slot1>;
};
codec {
sound-dai = <&es7210_adc2>;
};
};
simple-audio-card,dai-link@2 {
reg = <1>;
format = "dsp_b";
cpu {
sound-dai = <&tdm_slot2>;
};
codec {
sound-dai = <&es7210_adc2>;
};
};
simple-audio-card,dai-link@3 {
reg = <1>;
format = "dsp_b";
cpu {
sound-dai = <&tdm_slot3>;
};
codec {
sound-dai = <&es7210_adc2>;
};
};
simple-audio-card,dai-link@4 {
reg = <1>;
format = "dsp_b";
cpu {
sound-dai = <&tdm_slot4>;
};
codec {
sound-dai = <&es7210_adc2>;
};
};
simple-audio-card,dai-link@5 {
reg = <1>;
format = "dsp_b";
cpu {
sound-dai = <&tdm_slot5>;
};
codec {
sound-dai = <&es7210_adc2>;
};
};
simple-audio-card,dai-link@6 {
reg = <1>;
format = "dsp_b";
cpu {
sound-dai = <&tdm_slot6>;
};
codec {
sound-dai = <&es7210_adc2>;
};
};
simple-audio-card,dai-link@7 {
reg = <1>;
format = "dsp_b";
cpu {
sound-dai = <&tdm_slot7>;
};
codec {
sound-dai = <&es7210_adc2>;
};
};
simple-audio-card,dai-link@8 {
reg = <1>;
format = "dsp_b";
cpu {
sound-dai = <&tdm_slot8>;
};
codec {
sound-dai = <&es7210_adc2>;
};
};
};
lightsound_i2s_8ch: lightsound@4 {
compatible = "simple-audio-card";
simple-audio-card,name = "Light-Sound-Card";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
simple-audio-card,widgets = "Speaker", "Speaker";
simple-audio-card,routing =
"Speaker", "AW87519 VO",
"AW87519 IN", "ES8156 ROUT";
simple-audio-card,aux-devs = <&audio_aw87519_pa>;
simple-audio-card,dai-link@0 { /* I2S - AUDIO SYS CODEC 8156*/
reg = <0>;
format = "i2s";
cpu {
sound-dai = <&i2s0 0>;
};
codec {
sound-dai = <&es8156_audio_codec>;
};
};
simple-audio-card,dai-link@1 { /* I2S - AUDIO SYS CODEC 7210*/
reg = <1>;
format = "i2s";
cpu {
sound-dai = <&i2s_8ch_sd2>;
};
codec {
mclk-fs = <512>;
sound-dai = <&es7210_audio_codec_adc0>;
};
};
simple-audio-card,dai-link@2 { /* I2S - AUDIO SYS CODEC 7210*/
reg = <2>;
format = "i2s";
cpu {
sound-dai = <&i2s_8ch_sd3>;
};
codec {
mclk-fs = <512>;
sound-dai = <&es7210_audio_codec_adc0>;
};
};
simple-audio-card,dai-link@3 { /* I2S - AUDIO SYS CODEC 7210_1*/
reg = <3>;
format = "i2s";
cpu {
sound-dai = <&i2s_8ch_sd0>;
};
codec {
mclk-fs = <512>;
sound-dai = <&es7210_audio_codec_adc1>;
};
};
simple-audio-card,dai-link@4 { /* I2S - AUDIO SYS CODEC 7210_1*/
reg = <4>;
format = "i2s";
cpu {
sound-dai = <&i2s_8ch_sd1>;
};
codec {
mclk-fs = <512>;
sound-dai = <&es7210_audio_codec_adc1>;
};
};
};
};
&audio_i2c0 {
es8156_audio_codec: es8156@8 {
#sound-dai-cells = <0>;
compatible = "everest,es8156";
reg = <0x08>;
sound-name-prefix = "ES8156";
AVDD-supply = <&soc_aud_dac_3v3_en_reg>;
DVDD-supply = <&soc_dvdd18_aon_reg>;
PVDD-supply = <&soc_dvdd18_aon_reg>;
mclk-sclk-ratio = <4>;
status = "disabled";
};
es7210_audio_codec_adc0: es7210@40 {
#sound-dai-cells = <0>;
compatible = "MicArray_0";
reg = <0x40>;
work-mode = "ES7210_NORMAL_I2S";
channels-max = <2>;
mclk-sclk-ratio = <4>;
sound-name-prefix = "ES7210_ADC0";
MVDD-supply = <&soc_aud_adc_3v3_en_reg>;
AVDD-supply = <&soc_aud_adc_3v3_en_reg>;
DVDD-supply = <&soc_dvdd18_aon_reg>;
PVDD-supply = <&soc_dvdd18_aon_reg>;
status = "disabled";
};
es7210_audio_codec_adc1: es7210@41 {
#sound-dai-cells = <0>;
compatible = "MicArray_1";
reg = <0x41>;
work-mode = "ES7210_NORMAL_I2S";
channels-max = <2>;
mclk-sclk-ratio = <4>;
sound-name-prefix = "ES7210_ADC1";
MVDD-supply = <&soc_aud_adc_3v3_en_reg>;
AVDD-supply = <&soc_aud_adc_3v3_en_reg>;
DVDD-supply = <&soc_dvdd18_aon_reg>;
PVDD-supply = <&soc_dvdd18_aon_reg>;
status = "disabled";
};
es7210_adc2: es7210@42 {
#sound-dai-cells = <0>;
compatible = "MicArray_0";
reg = <0x42>;
work-mode = "ES7210_TDM_1LRCK_DSPB";
channels-max = <8>;
sound-name-prefix = "ES7210_ADC2";
MVDD-supply = <&soc_aud_adc_3v3_en_reg>;
AVDD-supply = <&soc_aud_adc_3v3_en_reg>;
DVDD-supply = <&soc_dvdd18_aon_reg>;
PVDD-supply = <&soc_dvdd18_aon_reg>;
status = "disabled";
};
es7210_adc3: es7210@43 {
#sound-dai-cells = <0>;
compatible = "MicArray_1";
reg = <0x43>;
work-mode = "ES7210_TDM_1LRCK_DSPB";
channels-max = <8>;
sound-name-prefix = "ES7210_ADC3";
MVDD-supply = <&soc_aud_adc_3v3_en_reg>;
AVDD-supply = <&soc_aud_adc_3v3_en_reg>;
DVDD-supply = <&soc_dvdd18_aon_reg>;
PVDD-supply = <&soc_dvdd18_aon_reg>;
status = "disabled";
};
audio_aw87519_pa: amp@58 {
compatible = "awinic,aw87519_pa";
reg = <0x58>;
reset-gpio = <&pcal6408ahk_b 3 0x1>;
sound-name-prefix = "AW87519";
status = "disabled";
};
};

View File

@@ -0,0 +1,108 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2021 Alibaba Group Holding Limited.
*/
#include "th1520-crash.dtsi"
/ {
model = "T-HEAD Light val board";
compatible = "thead,light-val", "thead,light";
memory@0 {
device_type = "memory";
reg = <0x0 0x200000 0x0 0xffe00000>;
};
};
&aon {
aon_reg_dialog: light-dialog-reg {
compatible = "thead,light-dialog-pmic";
status = "okay";
dvdd_cpu_reg: appcpu_dvdd {
regulator-name = "appcpu_dvdd";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <1500000>;
regulator-boot-on;
regulator-always-on;
};
dvddm_cpu_reg: appcpu_dvddm {
regulator-name = "appcpu_dvddm";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <1500000>;
regulator-boot-on;
regulator-always-on;
};
};
};
&cpus {
c910_0: cpu@0 {
operating-points = <
/* kHz uV */
300000 600000
800000 700000
1500000 800000
1848000 1000000
>;
light,dvddm-operating-points = <
/* kHz uV */
300000 800000
800000 800000
1500000 800000
1848000 1000000
>;
};
c910_1: cpu@1 {
operating-points = <
/* kHz uV */
300000 600000
800000 700000
1500000 800000
1848000 1000000
>;
light,dvddm-operating-points = <
/* kHz uV */
300000 800000
800000 800000
1500000 800000
1848000 1000000
>;
};
c910_2: cpu@2 {
operating-points = <
/* kHz uV */
300000 600000
800000 700000
1500000 800000
1848000 1000000
>;
light,dvddm-operating-points = <
/* kHz uV */
300000 800000
800000 800000
1500000 800000
1848000 1000000
>;
};
c910_3: cpu@3 {
operating-points = <
/* kHz uV */
300000 600000
800000 700000
1500000 800000
1848000 1000000
>;
light,dvddm-operating-points = <
/* kHz uV */
300000 800000
800000 800000
1500000 800000
1848000 1000000
>;
};
};

View File

@@ -0,0 +1,58 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2021 Alibaba Group Holding Limited.
*/
/dts-v1/;
#include "th1520-a-val.dtsi"
&i2c0 {
touch@5d {
compatible = "goodix,gt911";
touchscreen-size-x = <800>;
touchscreen-size-y = <1280>;
status = "okay";
};
};
&i2c1 {
touch1@5d {
compatible = "goodix,gt911";
touchscreen-size-x = <800>;
touchscreen-size-y = <1280>;
status = "okay";
};
};
&dpu_enc0 {
status = "okay";
};
&dpu_enc1 {
status = "okay";
};
&dsi0 {
status = "okay";
};
&dsi1 {
status = "okay";
};
&dhost_0 {
status = "okay";
panel0@0 {
compatible = "txd,dy800qwxpab";
};
};
&dhost_1 {
status = "okay";
panel1@0 {
compatible = "txd,dy800qwxpab";
};
};

View File

@@ -0,0 +1,47 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2021 Alibaba Group Holding Limited.
*/
/dts-v1/;
#include "th1520-a-val.dtsi"
&i2c0 {
touch@5d {
compatible = "goodix,gt911";
touchscreen-size-x = <800>;
touchscreen-size-y = <1280>;
status = "okay";
};
};
&dpu_enc0 {
status = "okay";
};
&dpu_enc1 {
ports {
/delete-node/ port@0;
};
};
&disp1_out {
remote-endpoint = <&hdmi_tx_in>;
};
&hdmi_tx {
status = "okay";
};
&dsi0 {
status = "okay";
};
&dhost_0 {
status = "okay";
panel0@0 {
compatible = "txd,dy800qwxpab";
};
};

View File

@@ -5,14 +5,13 @@
/dts-v1/; /dts-v1/;
#include "light-b-product.dts" #include "th1520-a-val.dts"
&light_iopmp { &light_iopmp {
status = "disabled"; status = "disabled";
}; };
&qspi1 { &eip_28 {
status = "disabled"; status = "disabled";
}; };

View File

@@ -5,13 +5,7 @@
/dts-v1/; /dts-v1/;
#include "light-a-val.dts" #include "th1520-a-val.dtsi"
/ {
display-subsystem {
status = "okay";
};
};
&dpu_enc1 { &dpu_enc1 {
ports { ports {
@@ -23,32 +17,21 @@
remote-endpoint = <&hdmi_tx_in>; remote-endpoint = <&hdmi_tx_in>;
}; };
&dpu {
status = "okay";
};
&hdmi_tx { &hdmi_tx {
status = "okay"; status = "okay";
port@0 {
/* input */
hdmi_tx_in: endpoint {
remote-endpoint = <&disp1_out>;
};
};
}; };
&lightsound { &lightsound {
status = "okay"; status = "okay";
simple-audio-card,dai-link@1 { /* I2S - HDMI */ simple-audio-card,dai-link@2 { /* I2S - HDMI */
reg = <1>; reg = <2>;
format = "i2s"; format = "i2s";
cpu { cpu {
sound-dai = <&light_i2s 1>; sound-dai = <&light_i2s 1>;
}; };
codec { codec {
sound-dai = <&dummy_codec 2>; sound-dai = <&dummy_codec>;
}; };
}; };
}; };
@@ -56,3 +39,23 @@
&light_i2s { &light_i2s {
status = "okay"; status = "okay";
}; };
&i2s0 {
status = "okay";
};
&i2s_8ch_sd2 {
status = "okay";
};
&es8156_audio_codec {
status = "okay";
};
&es7210_audio_codec_adc0 {
status = "okay";
};
&audio_aw87519_pa {
status = "okay";
};

View File

@@ -0,0 +1,100 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2021 Alibaba Group Holding Limited.
*/
#include "th1520-crash.dtsi"
/ {
model = "T-HEAD Light product board";
compatible = "thead,light-val", "thead,light";
memory@0 {
device_type = "memory";
reg = <0x0 0x200000 0x0 0x7fe00000>;
};
};
&aon {
aon_reg_ricoh: light-ricoh-reg {
compatible = "thead,light-ricoh-pmic";
status = "okay";
dvdd_cpu_reg: appcpu_dvdd {
regulator-name = "appcpu_dvdd";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <1500000>;
regulator-boot-on;
regulator-always-on;
};
dvddm_cpu_reg: appcpu_dvddm {
regulator-name = "appcpu_dvddm";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <1500000>;
regulator-boot-on;
regulator-always-on;
};
};
};
&cpus {
c910_0: cpu@0 {
operating-points = <
/* kHz uV */
300000 600000
800000 700000
1500000 800000
>;
light,dvddm-operating-points = <
/* kHz uV */
300000 800000
800000 800000
1500000 800000
>;
};
c910_1: cpu@1 {
operating-points = <
/* kHz uV */
300000 600000
800000 700000
1500000 800000
>;
light,dvddm-operating-points = <
/* kHz uV */
300000 800000
800000 800000
1500000 800000
>;
};
c910_2: cpu@2 {
operating-points = <
/* kHz uV */
300000 600000
800000 700000
1500000 800000
>;
light,dvddm-operating-points = <
/* kHz uV */
300000 800000
800000 800000
1500000 800000
>;
};
c910_3: cpu@3 {
operating-points = <
/* kHz uV */
300000 600000
800000 700000
1500000 800000
>;
light,dvddm-operating-points = <
/* kHz uV */
300000 800000
800000 800000
1500000 800000
>;
};
};

View File

@@ -5,7 +5,7 @@
/dts-v1/; /dts-v1/;
#include "light-ant-evt.dts" #include "th1520-b-product.dts"
@@ -13,8 +13,6 @@
status = "disabled"; status = "disabled";
}; };
&qspi1 { &eip_28 {
status = "disabled"; status = "disabled";
}; };

View File

@@ -0,0 +1,884 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2021 Alibaba Group Holding Limited.
*/
/dts-v1/;
#include "th1520.dtsi"
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/gpio/gpio.h>
#include "th1520-vi-devices.dtsi"
/ {
model = "T-HEAD Light val board";
compatible = "thead,light-val", "thead,light";
chosen {
bootargs = "console=ttyS0,115200 earlycon";
stdout-path = "serial0:115200n8";
};
leds {
compatible = "gpio-leds";
status = "disabled";
led0 {
label = "SYS_STATUS";
gpios = <&gpio1_porta 15 0>; /* GPIO_ACTIVE_HIGH: 0 */
default-state = "off";
};
};
display-subsystem {
status = "okay";
};
lcd0_backlight: pwm-backlight@0 {
status = "disabled";
compatible = "pwm-backlight";
pwms = <&pwm 0 5000000>;
brightness-levels = <0 4 8 16 32 64 128 255>;
default-brightness-level = <7>;
};
light_iopmp: iopmp {
status = "disabled";
compatible = "thead,light-iopmp";
/* config#1: multiple valid regions */
iopmp_emmc: IOPMP_EMMC {
attr = <0xFFFFFFFF>;
is_default_region;
};
/* config#2: iopmp bypass */
iopmp_sdio0: IOPMP_SDIO0 {
bypass_en;
};
/* config#3: iopmp default region set */
iopmp_sdio1: IOPMP_SDIO1 {
attr = <0xFFFFFFFF>;
is_default_region;
};
iopmp_usb0: IOPMP_USB0 {
attr = <0xFFFFFFFF>;
is_default_region;
};
iopmp_ao: IOPMP_AO {
is_default_region;
};
iopmp_aud: IOPMP_AUD {
is_default_region;
};
iopmp_chip_dbg: IOPMP_CHIP_DBG {
is_default_region;
};
iopmp_eip120i: IOPMP_EIP120I {
is_default_region;
};
iopmp_eip120ii: IOPMP_EIP120II {
is_default_region;
};
iopmp_eip120iii: IOPMP_EIP120III {
is_default_region;
};
iopmp_isp0: IOPMP_ISP0 {
is_default_region;
};
iopmp_isp1: IOPMP_ISP1 {
is_default_region;
};
iopmp_dw200: IOPMP_DW200 {
is_default_region;
};
iopmp_vipre: IOPMP_VIPRE {
is_default_region;
};
iopmp_venc: IOPMP_VENC {
is_default_region;
};
iopmp_vdec: IOPMP_VDEC {
is_default_region;
};
iopmp_g2d: IOPMP_G2D {
is_default_region;
};
iopmp_fce: IOPMP_FCE {
is_default_region;
};
iopmp_npu: IOPMP_NPU {
is_default_region;
};
iopmp0_dpu: IOPMP0_DPU {
bypass_en;
};
iopmp1_dpu: IOPMP1_DPU {
bypass_en;
};
iopmp_gpu: IOPMP_GPU {
is_default_region;
};
iopmp_gmac1: IOPMP_GMAC1 {
is_default_region;
};
iopmp_gmac2: IOPMP_GMAC2 {
is_default_region;
};
iopmp_dmac: IOPMP_DMAC {
is_default_region;
};
iopmp_tee_dmac: IOPMP_TEE_DMAC {
is_default_region;
};
iopmp_dsp0: IOPMP_DSP0 {
is_default_region;
};
iopmp_dsp1: IOPMP_DSP1 {
is_default_region;
};
iopmp_audio0: IOPMP_AUDIO0 {
is_default_region;
};
iopmp_audio1: IOPMP_AUDIO1 {
is_default_region;
};
};
mbox_910t_client1: mbox_910t_client1 {
compatible = "thead,light-mbox-client";
mbox-names = "902";
mboxes = <&mbox_910t 1 0>;
status = "disabled";
};
mbox_910t_client2: mbox_910t_client2 {
compatible = "thead,light-mbox-client";
mbox-names = "906";
mboxes = <&mbox_910t 2 0>;
status = "disabled";
};
lightsound: lightsound@1 {
compatible = "simple-audio-card";
simple-audio-card,name = "Light-Sound-Card";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
dummy_codec: dummy_codec {
#sound-dai-cells = <0>;
compatible = "thead,light-dummy-pcm";
sound-name-prefix = "DUMMY";
status = "okay";
};
reg_vref_1v8: regulator-adc-verf {
compatible = "regulator-fixed";
regulator-name = "vref-1v8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
status = "okay";
};
reg_tp_pwr_en: regulator-pwr-en {
compatible = "regulator-fixed";
regulator-name = "PWR_EN";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
gpio = <&gpio1_porta 12 1>;
enable-active-high;
regulator-always-on;
};
wcn_wifi: wireless-wlan {
compatible = "wlan-platdata";
clock-names = "clk_wifi";
ref-clock-frequency = <24000000>;
keep_wifi_power_on;
pinctrl-names = "default";
wifi_chip_type = "rtl8723ds";
WIFI,poweren_gpio = <&gpio2_porta 29 0>;
WIFI,reset_n = <&gpio2_porta 24 0>;
status = "okay";
};
wcn_bt: wireless-bluetooth {
compatible = "bluetooth-platdata";
pinctrl-names = "default", "rts_gpio";
BT,power_gpio = <&gpio2_porta 25 0>;
status = "okay";
};
gpio-keys {
compatible = "gpio-keys";
pinctrl-0 = <&pinctrl_volume>;
pinctrl-names = "default";
key-volumedown {
label = "Volume Down Key";
linux,code = <KEY_VOLUMEDOWN>;
debounce-interval = <1>;
gpios = <&ao_gpio_porta 11 0x1>;
};
key-volumeup {
label = "Volume Up Key";
linux,code = <KEY_VOLUMEUP>;
debounce-interval = <1>;
gpios = <&ao_gpio_porta 10 0x1>;
};
};
aon: light-aon {
compatible = "thead,light-aon";
mbox-names = "aon";
mboxes = <&mbox_910t 1 0>;
log-memory-region = <&aon_log_mem>;
status = "okay";
pd: light-aon-pd {
compatible = "thead,light-aon-pd";
#power-domain-cells = <1>;
};
c910_cpufreq {
compatible = "thead,light-mpw-cpufreq";
status = "okay";
};
test: light-aon-test {
compatible = "thead,light-aon-test";
};
};
};
&resmem {
#address-cells = <2>;
#size-cells = <2>;
ranges;
tee_mem: memory@1a000000 {
reg = <0x0 0x1a000000 0 0x4000000>;
no-map;
};
dsp0_mem: memory@20000000 { /**0x2000_0000~0x2040_0000 4M**/
reg = <0x0 0x20000000 0x0 0x00280000 /* DSP FW code&data section 2.5M*/
0x0 0x20280000 0x0 0x00001000 /* DSP communication area 4K*/
0x0 0x20281000 0x0 0x00007000 /* Panic/log page 28K */
0x0 0x20288000 0x0 0x00178000>; /* DSP shared memory 1.5M-32K*/
//no-map;
};
dsp1_mem: memory@20400000 { /**0x2040_0000~0x2080_0000 4M**/
reg = <0x0 0x20400000 0x0 0x00280000 /* DSP FW code&data section */
0x0 0x20680000 0x0 0x00001000 /* DSP communication area */
0x0 0x20681000 0x0 0x00007000 /* Panic/log page*/
0x0 0x20688000 0x0 0x00178000>; /* DSP shared memory */
//no-map;
};
vi_mem: framebuffer@10000000 {
reg = <0x0 0x10000000 0x0 0x02C00000 /* vi_mem_pool_region[0] 44 MB (default) */
0x0 0x12C00000 0x0 0x01D00000 /* vi_mem_pool_region[1] 29 MB */
0x0 0x14900000 0x0 0x01E00000>; /* vi_mem_pool_region[2] 30 MB */
no-map;
};
facelib_mem: memory@17000000 {
reg = <0x0 0x17000000 0 0x02000000>;
//no-map;
};
aon_log_mem: memory@33600000 {
reg = <0x0 0x33600000 0x0 0x200000>;
};
};
&adc {
vref-supply = <&reg_vref_1v8>;
status = "okay";
};
&i2c0 {
clock-frequency = <100000>;
status = "okay";
touch@5d {
#gpio-cells = <2>;
compatible = "goodix,gt911";
reg = <0x5d>;
interrupt-parent = <&gpio1_porta>;
interrupts = <8 0>;
irq-gpios = <&gpio1_porta 8 0>;
reset-gpios = <&gpio1_porta 7 0>;
AVDD28-supply = <&reg_tp_pwr_en>;
touchscreen-size-x = <800>;
touchscreen-size-y = <1280>;
};
};
&audio_i2c0 {
clock-frequency = <100000>;
status = "okay";
es8156_audio_codec: es8156@8 {
#sound-dai-cells = <0>;
compatible = "everest,es8156";
reg = <0x08>;
sound-name-prefix = "ES8156";
status = "disabled";
};
es7210_audio_codec: es7210@40 {
#sound-dai-cells = <0>;
compatible = "MicArray_0";
reg = <0x40>;
sound-name-prefix = "ES7210";
status = "disabled";
};
audio_aw87519_pa: amp@58 {
compatible = "awinic,aw87519_pa";
reg = <0x58>;
reset-gpio = <&ao_gpio4_porta 9 0x1>;
sound-name-prefix = "AW87519";
status = "okay";
};
};
&i2c1 {
clock-frequency = <100000>;
status = "okay";
};
&spi0 {
num-cs = <1>;
cs-gpios = <&gpio2_porta 15 0>; // GPIO_ACTIVE_HIGH: 0
rx-sample-delay-ns = <10>;
status = "disabled";
spi_norflash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "winbond,w25q64jwm", "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <50000000>;
w25q,fast-read;
};
spidev@1 {
compatible = "spidev";
#address-cells = <0x1>;
#size-cells = <0x1>;
reg = <0x1>;
spi-max-frequency = <50000000>;
};
};
&uart0 {
clocks = <&dummy_clock_uart_sclk>;
clock-names = "baudclk";
clock-frequency = <100000000>;
};
&qspi0 {
num-cs = <1>;
cs-gpios = <&gpio2_porta 3 0>;
rx-sample-dly = <4>;
status = "disabled";
spi-flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spi-nand";
spi-max-frequency = <100000000>;
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
reg = <0>;
partition@0 {
label = "ubi1";
reg = <0x00000000 0x08000000>;
};
};
};
&qspi1 {
compatible = "snps,dw-apb-ssi";
num-cs = <1>;
cs-gpios = <&gpio0_porta 1 0>;
status = "disabled";
spidev@0 {
compatible = "spidev";
#address-cells = <0x1>;
#size-cells = <0x1>;
reg = <0x0>;
spi-max-frequency = <50000000>;
};
};
&gmac0 {
phy-mode = "rgmii-id";
rx-clk-delay = <0x00>; /* for RGMII */
tx-clk-delay = <0x00>; /* for RGMII */
phy-handle = <&phy_88E1111_0>;
status = "okay";
mdio0 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,dwmac-mdio";
phy_88E1111_0: ethernet-phy@0 {
reg = <0x1>;
};
phy_88E1111_1: ethernet-phy@1 {
reg = <0x2>;
};
};
};
&gmac1 {
phy-mode = "rgmii-id";
rx-clk-delay = <0x00>; /* for RGMII */
tx-clk-delay = <0x00>; /* for RGMII */
phy-handle = <&phy_88E1111_1>;
status = "okay";
};
&emmc {
max-frequency = <198000000>;
non-removable;
mmc-hs400-1_8v;
io_fixed_1v8;
is_emmc;
no-sdio;
no-sd;
pull_up;
bus-width = <8>;
status = "okay";
};
&sdhci0 {
max-frequency = <198000000>;
bus-width = <4>;
pull_up;
wprtn_ignore;
status = "okay";
};
&sdhci1 {
max-frequency = <100000000>;
bus-width = <4>;
pull_up;
no-sd;
no-mmc;
non-removable;
io_fixed_1v8;
rxclk-sample-delay = <80>;
post-power-on-delay-ms = <50>;
wprtn_ignore;
cap-sd-highspeed;
keep-power-in-suspend;
wakeup-source;
status = "okay";
};
&padctrl0_apsys { /* right-pinctrl */
light-evb-padctrl0 {
/*
* Pin Configuration Node:
* Format: <pin_id mux_node config>
*/
pinctrl_uart0: uart0grp {
thead,pins = <
FM_UART0_TXD 0x0 0x72
FM_UART0_RXD 0x0 0x72
>;
};
pinctrl_spi0: spi0grp {
thead,pins = <
FM_SPI_CSN 0x3 0x20a
FM_SPI_SCLK 0x0 0x20a
FM_SPI_MISO 0x0 0x23a
FM_SPI_MOSI 0x0 0x23a
>;
};
pinctrl_qspi0: qspi0grp {
thead,pins = <
FM_QSPI0_SCLK 0x0 0x20f
FM_QSPI0_CSN0 0x3 0x20f
FM_QSPI0_CSN1 0x0 0x20f
FM_QSPI0_D0_MOSI 0x0 0x23f
FM_QSPI0_D1_MISO 0x0 0x23f
FM_QSPI0_D2_WP 0x0 0x23f
FM_QSPI0_D3_HOLD 0x0 0x23f
>;
};
pinctrl_light_i2s0: i2s0grp {
thead,pins = <
FM_QSPI0_SCLK 0x2 0x208
FM_QSPI0_CSN0 0x2 0x238
FM_QSPI0_CSN1 0x2 0x208
FM_QSPI0_D0_MOSI 0x2 0x238
FM_QSPI0_D1_MISO 0x2 0x238
FM_QSPI0_D2_WP 0x2 0x238
FM_QSPI0_D3_HOLD 0x2 0x238
>;
};
pinctrl_pwm: pwmgrp {
thead,pins = <
FM_GPIO3_2 0x1 0x208 /* pwm0 */
>;
};
};
};
&padctrl1_apsys { /* left-pinctrl */
light-evb-padctrl1 {
/*
* Pin Configuration Node:
* Format: <pin_id mux_node config>
*/
pinctrl_uart3: uart3grp {
thead,pins = <
FM_UART3_TXD 0x0 0x72
FM_UART3_RXD 0x0 0x72
>;
};
pinctrl_uart4: uart4grp {
thead,pins = <
FM_UART4_TXD 0x0 0x72
FM_UART4_RXD 0x0 0x72
FM_UART4_CTSN 0x0 0x72
FM_UART4_RTSN 0x0 0x72
>;
};
pinctrl_qspi1: qspi1grp {
thead,pins = <
FM_QSPI1_SCLK 0x0 0x20a
FM_QSPI1_CSN0 0x3 0x20a
FM_QSPI1_D0_MOSI 0x0 0x23a
FM_QSPI1_D1_MISO 0x0 0x23a
FM_QSPI1_D2_WP 0x0 0x23a
FM_QSPI1_D3_HOLD 0x0 0x23a
>;
};
pinctrl_iso7816: iso7816grp {
thead,pins = <
FM_QSPI1_SCLK 0x1 0x208
FM_QSPI1_D0_MOSI 0x1 0x238
FM_QSPI1_D1_MISO 0x1 0x238
FM_QSPI1_D2_WP 0x1 0x238
FM_QSPI1_D3_HOLD 0x1 0x238
>;
};
};
};
&padctrl_aosys {
light-aon-padctrl {
/*
* Pin Configuration Node:
* Format: <pin_id mux_node config>
*/
pinctrl_audiopa1: audiopa1_grp {
thead,pins = <
FM_AUDIO_PA1 0x3 0x72
>;
};
pinctrl_audiopa2: audiopa2_grp {
thead,pins = <
FM_AUDIO_PA2 0x0 0x72
>;
};
pinctrl_volume: volume_grp {
thead,pins = <
FM_AOGPIO_11 0x0 0x208
FM_AOGPIO_10 0x3 0x208
>;
};
};
};
&i2c0 {
clock-frequency = <400000>;
status = "okay";
};
&i2c1 {
clock-frequency = <400000>;
status = "okay";
};
&i2c2 {
clock-frequency = <400000>;
status = "okay";
};
&i2c3 {
clock-frequency = <400000>;
status = "okay";
};
&i2c4 {
clock-frequency = <400000>;
status = "okay";
};
&isp0 {
status = "disabled";
};
&isp1 {
status = "disabled";
};
&isp_ry0 {
status = "disabled";
};
&dewarp {
status = "disabled";
};
&dec400_isp0 {
status = "disabled";
};
&dec400_isp1 {
status = "disabled";
};
&dec400_isp2 {
status = "disabled";
};
&bm_visys {
status = "disabled";
};
&bm_csi0 {
status = "disabled";
};
&bm_csi1 {
status = "disabled";
};
&bm_csi2 {
status = "disabled";
};
&vi_pre {
status = "disabled";
};
&xtensa_dsp {
status = "disabled";
};
&xtensa_dsp0 {
status = "disabled";
};
&xtensa_dsp1 {
status = "disabled";
};
&vvcam_flash_led0{
status = "disabled";
};
&vvcam_sensor0 {
status = "disabled";
};
&vvcam_sensor1 {
status = "disabled";
};
&vvcam_sensor2 {
status = "disabled";
};
&vvcam_sensor3 {
status = "disabled";
};
&vvcam_sensor4 {
status = "disabled";
};
&vvcam_sensor5 {
status = "disabled";
};
&video0{
status = "disabled";
};
&video1{
status = "disabled";
};
&video2{
status = "disabled";
};
&video3{
status = "disabled";
};
&video4{
status = "disabled";
};
&video5{
status = "disabled";
};
&video6{
status = "disabled";
};
&video7{
status = "disabled";
};
&video8{
status = "disabled";
};
&video9{
status = "disabled";
};
&video10{
status = "disabled";
};
&video11{
status = "disabled";
};
&video12{
status = "disabled";
};
&trng {
status = "disabled";
};
&eip_28 {
status = "disabled";
};
&vdec {
status = "disabled";
};
&venc {
status = "disabled";
};
&isp_venc_shake {
status = "disabled";
};
&vidmem {
status = "disabled";
};
&gpu {
status = "disabled";
};
&npu {
status = "disabled";
};
&fce {
status = "disabled";
};
&dpu_enc0 {
status = "disabled";
};
&dpu_enc1 {
status = "disabled";
};
&dpu {
status = "disabled";
};
&dsi0 {
status = "disabled";
};
&dhost_0 {
status = "disabled";
};
&disp1_out {
status = "disabled";
};
&hdmi_tx {
status = "disabled";
};
&lightsound {
status = "disabled";
};
&khvhost {
status = "disabled";
};

View File

@@ -0,0 +1,72 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2021 Alibaba Group Holding Limited.
*/
/dts-v1/;
#include "th1520-lpi4a.dtsi"
&i2c3 {
touch@14 {
touchscreen-size-x = <800>;
touchscreen-size-y = <1200>;
};
};
&dsi0 {
status = "okay";
};
&dpu_enc0 {
status = "okay";
};
&dhost_0 {
panel0@0 {
compatible = "chongzhou,cz101b4001", "jadard,jd9365da-h3";
};
};
&video10{ // TUNINGTOOL
status = "okay";
channel0 {
sensor1 {
subdev_name = "vivcam";
idx = <3>;
csi_idx = <0>;
mode_idx = <1>; // 0=640 480 1=2592x1944
path_type = "SENSOR_2592x1944_LINER";
};
dma {
path_type = "VIPRE_CSI0_ISP0";
};
};
};
&video15{
status = "okay";
vi_mem_pool_region = <0>; // vi_mem: framebuffer, region[0]
channel0 {
status = "okay";
sensor0 {
subdev_name = "vivcam";
idx = <0>;
csi_idx = <0>;
mode_idx = <0>;
path_type = "SENSOR_VGA_RAW12_LINER";
};
sensor1 {
subdev_name = "vivcam";
idx = <3>;
csi_idx = <0>;
mode_idx = <1>;
path_type = "SENSOR_2592x1944_LINER";
};
dma {
subdev_name = "vipre";
idx = <0>;
path_type = "VIPRE_CSI0_DDR";
};
};
};

View File

@@ -0,0 +1,33 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2022-2023 Alibaba Group Holding Limited.
*/
#include "th1520-lpi4a.dtsi"
/ {
model = "T-HEAD Light Lichee Pi 4A configuration for 8GB DDR board";
compatible = "thead,light-val", "thead,light-lpi4a", "thead,light";
};
&i2c3 {
touch@14 {
touchscreen-size-x = <800>;
touchscreen-size-y = <1200>;
status = "okay";
};
};
&dsi0 {
status = "okay";
};
&dpu_enc0 {
status = "okay";
};
&dhost_0 {
panel0@0 {
compatible = "chongzhou,cz101b4001", "jadard,jd9365da-h3";
};
};

View File

@@ -0,0 +1,33 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2022-2023 Alibaba Group Holding Limited.
*/
#include "th1520-lpi4a.dtsi"
/ {
model = "T-HEAD Light Lichee Pi 4A configuration for 8GB DDR board";
compatible = "thead,light-val", "thead,light-lpi4a", "thead,light";
};
&i2c3 {
touch@14 {
touchscreen-size-x = <1200>;
touchscreen-size-y = <1920>;
status = "okay";
};
};
&dsi0 {
status = "okay";
};
&dpu_enc0 {
status = "okay";
};
&dhost_0 {
panel0@0 {
compatible = "himax,hx8279";
};
};

View File

@@ -0,0 +1,108 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2023 Alibaba Group Holding Limited.
*/
#include "th1520-crash.dtsi"
/ {
model = "T-HEAD Light Lichee Pi 4A board";
compatible = "thead,light-val", "thead,light-lpi4a", "thead,light";
memory@0 {
device_type = "memory";
reg = <0x0 0x200000 0x1 0xffe00000>;
};
};
&aon {
aon_reg_dialog: light-dialog-reg {
compatible = "thead,light-dialog-pmic-ant";
status = "okay";
dvdd_cpu_reg: appcpu_dvdd {
regulator-name = "appcpu_dvdd";
regulator-min-microvolt = <300000>;
regulator-max-microvolt = <1570000>;
regulator-boot-on;
regulator-always-on;
};
dvddm_cpu_reg: appcpu_dvddm {
regulator-name = "appcpu_dvddm";
regulator-min-microvolt = <300000>;
regulator-max-microvolt = <1570000>;
regulator-boot-on;
regulator-always-on;
};
};
};
&cpus {
c910_0: cpu@0 {
operating-points = <
/* kHz uV */
300000 600000
800000 700000
1500000 800000
1848000 1000000
>;
light,dvddm-operating-points = <
/* kHz uV */
300000 800000
800000 800000
1500000 800000
1848000 1000000
>;
};
c910_1: cpu@1 {
operating-points = <
/* kHz uV */
300000 600000
800000 700000
1500000 800000
1848000 1000000
>;
light,dvddm-operating-points = <
/* kHz uV */
300000 800000
800000 800000
1500000 800000
1848000 1000000
>;
};
c910_2: cpu@2 {
operating-points = <
/* kHz uV */
300000 600000
800000 700000
1500000 800000
1848000 1000000
>;
light,dvddm-operating-points = <
/* kHz uV */
300000 800000
800000 800000
1500000 800000
1848000 1000000
>;
};
c910_3: cpu@3 {
operating-points = <
/* kHz uV */
300000 600000
800000 700000
1500000 800000
1848000 1000000
>;
light,dvddm-operating-points = <
/* kHz uV */
300000 800000
800000 800000
1500000 800000
1848000 1000000
>;
};
};

View File

@@ -5,9 +5,13 @@
/dts-v1/; /dts-v1/;
#include "light-a-val-dsi0-hdmi.dts" #include "th1520-lpi4a-product.dts"
&light_iopmp { &light_iopmp {
status = "disabled"; status = "disabled";
}; };
&eip_28 {
status = "disabled";
};

View File

@@ -3,47 +3,40 @@
* Copyright (C) 2021 Alibaba Group Holding Limited. * Copyright (C) 2021 Alibaba Group Holding Limited.
*/ */
#include "light-a-val.dts" /dts-v1/;
/ { #include "th1520-lpi4a.dtsi"
model = "T-HEAD Light FM Audio VAL board";
compatible = "thead,light-val-audio", "thead,light";
};
&lightsound { &lightsound {
status = "okay"; status = "okay";
simple-audio-card,dai-link@0 { /* I2S - HDMI*/
simple-audio-card,dai-link@0 { /* I2S - AUDIO SYS CODEC 8156*/
reg = <0>; reg = <0>;
format = "i2s"; format = "i2s";
cpu { cpu {
sound-dai = <&i2s0 0>; sound-dai = <&light_i2s 1>;
}; };
codec { codec {
sound-dai = <&es8156_audio_codec>; sound-dai = <&dummy_codec>;
}; };
}; };
simple-audio-card,dai-link@1 { /* I2S - AUDIO SYS CODEC 7210*/ simple-audio-card,dai-link@1 { /* I2S - AUDIO SYS CODEC 7210*/
reg = <1>; reg = <1>;
format = "i2s"; format = "i2s";
cpu { cpu {
sound-dai = <&i2s3 0>; sound-dai = <&i2s1 0>;
}; };
codec { codec {
sound-dai = <&es7210_audio_codec>; sound-dai = <&es7210_audio_codec>;
}; };
}; };
simple-audio-card,dai-link@2 { /* I2S - AUDIO SYS CODEC 8156*/
reg = <2>;
format = "i2s";
cpu {
sound-dai = <&i2s1 0>;
}; };
codec {
&light_i2s { sound-dai = <&es8156_audio_codec>;
status = "okay";
}; };
&i2s0 {
status = "okay";
}; };
&i2s3 {
status = "okay";
}; };

File diff suppressed because it is too large Load Diff

View File

@@ -4,9 +4,9 @@
*/ */
&video0{ &video0{
status = "okay"; status = "disabled";
pipline0 { channel0 {
pipline_id = <0>; channel_id = <0>;
status = "okay"; status = "okay";
sensor0 { sensor0 {
subdev_name = "vivcam"; subdev_name = "vivcam";
@@ -31,8 +31,8 @@
path_type = "ISP_MI_PATH_MP"; path_type = "ISP_MI_PATH_MP";
}; };
}; };
pipline1 { channel1 {
pipline_id = <1>; channel_id = <1>;
status = "okay"; status = "okay";
sensor0 { sensor0 {
subdev_name = "vivcam"; subdev_name = "vivcam";
@@ -57,8 +57,8 @@
path_type = "ISP_MI_PATH_SP"; path_type = "ISP_MI_PATH_SP";
}; };
}; };
pipline2 { channel2 {
pipline_id = <2>; channel_id = <2>;
status = "okay"; status = "okay";
sensor0 { sensor0 {
subdev_name = "vivcam"; subdev_name = "vivcam";
@@ -86,9 +86,9 @@
}; };
&video1{ &video1{
status = "okay"; status = "disabled";
pipline0 { // VSE0 channel0 { // VSE0
pipline_id = <0>; channel_id = <0>;
status = "okay"; status = "okay";
sensor0 { sensor0 {
subdev_name = "vivcam"; subdev_name = "vivcam";
@@ -118,8 +118,8 @@
path_type = "DW_DWE_VSE0"; path_type = "DW_DWE_VSE0";
}; };
}; };
pipline1 { // VSE1 channel1 { // VSE1
pipline_id = <1>; channel_id = <1>;
status = "okay"; status = "okay";
sensor0 { sensor0 {
subdev_name = "vivcam"; subdev_name = "vivcam";
@@ -149,8 +149,8 @@
path_type = "DW_DWE_VSE1"; path_type = "DW_DWE_VSE1";
}; };
}; };
pipline2 { // VSE2 channel2 { // VSE2
pipline_id = <2>; channel_id = <2>;
status = "okay"; status = "okay";
sensor0 { sensor0 {
subdev_name = "vivcam"; subdev_name = "vivcam";
@@ -183,9 +183,9 @@
}; };
&video2 { &video2 {
status = "okay"; status = "disabled";
pipline0 { channel0 {
pipline_id = <0>; channel_id = <0>;
status = "okay"; status = "okay";
sensor0 { sensor0 {
subdev_name = "vivcam"; subdev_name = "vivcam";
@@ -199,6 +199,12 @@
csi_idx = <0xff>; csi_idx = <0xff>;
path_type = "SENSOR_VGA_RAW10_LINER"; path_type = "SENSOR_VGA_RAW10_LINER";
}; };
sensor2 {
subdev_name = "vivcam";
idx = <0xff>; // invalid
csi_idx = <0xff>;
path_type = "SENSOR_VGA_RAW10_LINER";
};
dma { dma {
subdev_name = "vipre"; subdev_name = "vipre";
idx = <0>; idx = <0>;
@@ -210,8 +216,8 @@
path_type = "ISP_MI_PATH_MP"; path_type = "ISP_MI_PATH_MP";
}; };
}; };
pipline1 { channel1 {
pipline_id = <1>; channel_id = <1>;
status = "okay"; status = "okay";
sensor0 { sensor0 {
subdev_name = "vivcam"; subdev_name = "vivcam";
@@ -236,8 +242,8 @@
path_type = "ISP_MI_PATH_SP"; path_type = "ISP_MI_PATH_SP";
}; };
}; };
pipline2 { channel2 {
pipline_id = <2>; channel_id = <2>;
status = "okay"; status = "okay";
sensor0 { sensor0 {
subdev_name = "vivcam"; subdev_name = "vivcam";
@@ -266,9 +272,9 @@
}; };
&video3 { &video3 {
status = "okay"; status = "disabled";
pipline0 { channel0 {
pipline_id = <0>; channel_id = <0>;
status = "okay"; status = "okay";
sensor0 { sensor0 {
subdev_name = "vivcam"; subdev_name = "vivcam";
@@ -298,8 +304,8 @@
path_type = "DW_DWE_VSE0"; path_type = "DW_DWE_VSE0";
}; };
}; };
pipline1 { channel1 {
pipline_id = <1>; channel_id = <1>;
status = "okay"; status = "okay";
sensor0 { sensor0 {
subdev_name = "vivcam"; subdev_name = "vivcam";
@@ -330,8 +336,8 @@
path_type = "DW_DWE_VSE1"; path_type = "DW_DWE_VSE1";
}; };
}; };
pipline2 { channel2 {
pipline_id = <2>; channel_id = <2>;
status = "okay"; status = "okay";
sensor0 { sensor0 {
subdev_name = "vivcam"; subdev_name = "vivcam";
@@ -364,9 +370,9 @@
}; };
&video4 { &video4 {
status = "okay"; status = "disabled";
pipline0 { channel0 {
pipline_id = <0>; channel_id = <0>;
status = "okay"; status = "okay";
sensor0 { sensor0 {
subdev_name = "vivcam"; subdev_name = "vivcam";
@@ -402,8 +408,8 @@
path_type = "ISP_RY_MI_PATH_MP"; path_type = "ISP_RY_MI_PATH_MP";
}; };
}; };
pipline1 { channel1 {
pipline_id = <1>; channel_id = <1>;
status = "okay"; status = "okay";
sensor0 { sensor0 {
subdev_name = "vivcam"; subdev_name = "vivcam";
@@ -438,8 +444,8 @@
path_type = "ISP_RY_MI_PATH_SP"; path_type = "ISP_RY_MI_PATH_SP";
}; };
}; };
pipline2 { channel2 {
pipline_id = <2>; channel_id = <2>;
status = "okay"; status = "okay";
sensor0 { sensor0 {
subdev_name = "vivcam"; subdev_name = "vivcam";
@@ -477,9 +483,9 @@
}; };
&video5 { &video5 {
status = "okay"; status = "disabled";
pipline0 { channel0 {
pipline_id = <0>; channel_id = <0>;
status = "okay"; status = "okay";
sensor0 { sensor0 {
subdev_name = "vivcam"; subdev_name = "vivcam";
@@ -520,8 +526,8 @@
path_type = "DW_DWE_VSE0"; path_type = "DW_DWE_VSE0";
}; };
}; };
pipline1 { channel1 {
pipline_id = <1>; channel_id = <1>;
status = "okay"; status = "okay";
sensor0 { sensor0 {
subdev_name = "vivcam"; subdev_name = "vivcam";
@@ -561,8 +567,8 @@
path_type = "DW_DWE_VSE1"; path_type = "DW_DWE_VSE1";
}; };
}; };
pipline2 { channel2 {
pipline_id = <2>; channel_id = <2>;
status = "okay"; status = "okay";
sensor0 { sensor0 {
subdev_name = "vivcam"; subdev_name = "vivcam";
@@ -606,9 +612,9 @@
&video6 { &video6 {
status = "okay"; status = "disabled";
pipline0 { channel0 {
pipline_id = <0>; channel_id = <0>;
status = "okay"; status = "okay";
sensor0 { sensor0 {
subdev_name = "vivcam"; subdev_name = "vivcam";
@@ -625,7 +631,7 @@
dma { dma {
subdev_name = "vipre"; subdev_name = "vipre";
idx = <0>; idx = <0>;
path_type = "VIPRE_CSI2_DDR"; path_type = "VIPRE_CSI2_DSP";
}; };
dsp { dsp {
subdev_name = "dsp"; subdev_name = "dsp";
@@ -633,8 +639,8 @@
path_type = "DSP_PATH_VIPRE_ODD"; path_type = "DSP_PATH_VIPRE_ODD";
}; };
}; };
pipline1 { channel1 {
pipline_id = <1>; channel_id = <1>;
status = "okay"; status = "okay";
sensor0 { sensor0 {
subdev_name = "vivcam"; subdev_name = "vivcam";
@@ -651,7 +657,7 @@
dma { dma {
subdev_name = "vipre"; subdev_name = "vipre";
idx = <0>; idx = <0>;
path_type = "VIPRE_CSI2_DDR"; path_type = "VIPRE_CSI2_DSP";
}; };
dsp { dsp {
subdev_name = "dsp"; subdev_name = "dsp";
@@ -663,9 +669,9 @@
&video7{ &video7{
status = "okay"; status = "disabled";
pipline0 { channel0 {
pipline_id = <0>; channel_id = <0>;
status = "okay"; status = "okay";
sensor0 { sensor0 {
subdev_name = "vivcam"; subdev_name = "vivcam";
@@ -706,8 +712,8 @@
}; };
}; };
pipline1 { channel1 {
pipline_id = <1>; channel_id = <1>;
status = "okay"; status = "okay";
sensor0 { sensor0 {
subdev_name = "vivcam"; subdev_name = "vivcam";
@@ -747,8 +753,8 @@
path_type = "DW_DWE_VSE1"; path_type = "DW_DWE_VSE1";
}; };
}; };
pipline2 { channel2 {
pipline_id = <2>; channel_id = <2>;
status = "okay"; status = "okay";
sensor0 { sensor0 {
subdev_name = "vivcam"; subdev_name = "vivcam";
@@ -792,9 +798,9 @@
&video8{ &video8{
status = "okay"; status = "disabled";
pipline0 { channel0 {
pipline_id = <0>; channel_id = <0>;
status = "okay"; status = "okay";
sensor0 { sensor0 {
subdev_name = "vivcam"; subdev_name = "vivcam";
@@ -811,7 +817,7 @@
dma { dma {
subdev_name = "vipre"; subdev_name = "vipre";
idx = <0>; idx = <0>;
path_type = "VIPRE_CSI1_DDR"; path_type = "VIPRE_CSI1_DSP";
}; };
dsp { dsp {
subdev_name = "dsp"; subdev_name = "dsp";
@@ -823,9 +829,9 @@
&video9 { //IR debug &video9 { //IR debug
status = "okay"; status = "disabled";
pipline0 { channel0 {
pipline_id = <0>; channel_id = <0>;
status = "okay"; status = "okay";
sensor0 { sensor0 {
subdev_name = "vivcam"; subdev_name = "vivcam";
@@ -844,7 +850,7 @@
dma { dma {
subdev_name = "vipre"; subdev_name = "vipre";
idx = <0>; idx = <0>;
path_type = "VIPRE_CSI2_DDR"; path_type = "VIPRE_CSI2_DSP";
}; };
dsp { dsp {
subdev_name = "dsp"; subdev_name = "dsp";
@@ -856,8 +862,8 @@
&video10{ // TUNING TOOL &video10{ // TUNING TOOL
status = "okay"; status = "disabled";
pipline0 { // CSI2X2_B channel0 { // CSI2X2_B
status = "okay"; status = "okay";
sensor0 { sensor0 {
subdev_name = "vivcam"; subdev_name = "vivcam";
@@ -883,9 +889,9 @@
&video11{ &video11{
status = "okay"; status = "disabled";
pipline0 { channel0 {
pipline_id = <0>; channel_id = <0>;
status = "okay"; status = "okay";
sensor0 { sensor0 {
subdev_name = "vivcam"; subdev_name = "vivcam";
@@ -914,8 +920,8 @@
&video12{ // TUNING TOOL &video12{ // TUNING TOOL
status = "okay"; status = "disabled";
pipline0 { // CSI2 channel0 { // CSI2
status = "okay"; status = "okay";
sensor0 { sensor0 {
subdev_name = "vivcam"; subdev_name = "vivcam";

View File

@@ -17,6 +17,12 @@ CONFIG_PERF_EVENTS=y
CONFIG_SOC_THEAD=y CONFIG_SOC_THEAD=y
CONFIG_SMP=y CONFIG_SMP=y
CONFIG_VECTOR=y CONFIG_VECTOR=y
CONFIG_HOTPLUG_CPU=y
CONFIG_PM=y
CONFIG_CPU_IDLE=y
CONFIG_VIRTUALIZATION=y
CONFIG_KVM=m
CONFIG_JUMP_LABEL=y
CONFIG_MODULES=y CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y CONFIG_MODULE_UNLOAD=y
CONFIG_PARTITION_ADVANCED=y CONFIG_PARTITION_ADVANCED=y
@@ -183,6 +189,5 @@ CONFIG_DEBUG_INFO=y
CONFIG_MAGIC_SYSRQ=y CONFIG_MAGIC_SYSRQ=y
CONFIG_DEBUG_FS=y CONFIG_DEBUG_FS=y
CONFIG_DETECT_HUNG_TASK=y CONFIG_DETECT_HUNG_TASK=y
CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=60
CONFIG_DEBUG_ATOMIC_SLEEP=y CONFIG_DEBUG_ATOMIC_SLEEP=y
# CONFIG_RCU_TRACE is not set # CONFIG_RCU_TRACE is not set

View File

@@ -0,0 +1,311 @@
CONFIG_SYSVIPC=y
CONFIG_POSIX_MQUEUE=y
CONFIG_NO_HZ_IDLE=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_PREEMPT=y
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_CGROUPS=y
CONFIG_NAMESPACES=y
CONFIG_USER_NS=y
CONFIG_CHECKPOINT_RESTORE=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_EXPERT=y
# CONFIG_BUG is not set
CONFIG_BPF_SYSCALL=y
CONFIG_PERF_EVENTS=y
CONFIG_FORCE_MAX_ZONEORDER=15
CONFIG_SOC_SIFIVE=y
CONFIG_SOC_THEAD=y
CONFIG_SMP=y
CONFIG_VECTOR=y
CONFIG_VECTOR_0_7=y
CONFIG_KEXEC=y
CONFIG_CRASH_DUMP=y
CONFIG_VIRTUALIZATION=y
CONFIG_KVM=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
CONFIG_CMA=y
CONFIG_CMA_DEBUGFS=y
CONFIG_CMA_AREAS=16
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_INET=y
CONFIG_IP_MULTICAST=y
CONFIG_IP_ADVANCED_ROUTER=y
CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y
CONFIG_IP_PNP_BOOTP=y
CONFIG_IP_PNP_RARP=y
CONFIG_BRIDGE=y
CONFIG_VSOCKETS=y
# CONFIG_VSOCKETS_LOOPBACK is not set
CONFIG_VIRTIO_VSOCKETS=y
CONFIG_NETLINK_DIAG=y
CONFIG_BT=y
CONFIG_BT_RFCOMM=y
CONFIG_BT_RFCOMM_TTY=y
CONFIG_BT_BNEP=y
CONFIG_BT_HIDP=y
CONFIG_BT_HCIUART=y
CONFIG_BT_HCIUART_H4=y
CONFIG_BT_HCIUART_RTL3WIRE=y
CONFIG_CFG80211=y
CONFIG_RFKILL=y
CONFIG_NET_9P=y
CONFIG_NET_9P_VIRTIO=y
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
CONFIG_MTD=y
CONFIG_MTD_TESTS=m
CONFIG_MTD_BLOCK=y
CONFIG_MTD_SLRAM=m
CONFIG_MTD_PHRAM=m
CONFIG_MTD_SPI_NAND=y
CONFIG_MTD_SPI_NOR=y
CONFIG_MTD_UBI=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_VIRTIO_BLK=y
CONFIG_LIGHT_DSMART_CARD=y
CONFIG_EEPROM_AT24=y
CONFIG_SCSI=y
CONFIG_BLK_DEV_SD=y
CONFIG_NETDEVICES=y
CONFIG_TUN=y
CONFIG_VIRTIO_NET=y
CONFIG_MACB=y
CONFIG_STMMAC_ETH=y
CONFIG_DWMAC_LIGHT=y
CONFIG_MICROSEMI_PHY=y
CONFIG_REALTEK_PHY=y
CONFIG_MARVELL_PHY=y
CONFIG_USB_USBNET=m
# CONFIG_USB_NET_AX8817X is not set
# CONFIG_USB_NET_AX88179_178A is not set
# CONFIG_USB_NET_NET1080 is not set
CONFIG_RTL8723DS=y
CONFIG_INPUT_MOUSEDEV=y
CONFIG_INPUT_EVDEV=y
CONFIG_KEYBOARD_GPIO=y
# CONFIG_INPUT_MOUSE is not set
CONFIG_INPUT_TOUCHSCREEN=y
CONFIG_TOUCHSCREEN_GOODIX=y
CONFIG_INPUT_MISC=y
CONFIG_INPUT_UINPUT=y
CONFIG_SERIAL_8250=y
# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_8250_NR_UARTS=6
CONFIG_SERIAL_8250_RUNTIME_UARTS=6
CONFIG_SERIAL_8250_DW=y
CONFIG_SERIAL_OF_PLATFORM=y
CONFIG_SERIAL_EARLYCON_RISCV_SBI=y
CONFIG_VIRTIO_CONSOLE=y
CONFIG_HW_RANDOM=y
CONFIG_HW_RANDOM_VIRTIO=y
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_DESIGNWARE_PLATFORM=y
CONFIG_SPI=y
CONFIG_SPI_DW_QUAD=y
CONFIG_SPI_DESIGNWARE=y
CONFIG_SPI_DW_MMIO=y
CONFIG_SPI_SPIDEV=y
# CONFIG_PTP_1588_CLOCK is not set
CONFIG_PINCTRL=y
CONFIG_GPIOLIB=y
CONFIG_GPIO_SYSFS=y
CONFIG_GPIO_DWAPB=y
CONFIG_GPIO_PCA953X=y
CONFIG_GPIO_PCA953X_IRQ=y
CONFIG_POWER_SUPPLY=y
CONFIG_SENSORS_MR75203=y
CONFIG_THERMAL=y
CONFIG_CPU_THERMAL=y
CONFIG_THERMAL_EMULATION=y
CONFIG_WATCHDOG=y
CONFIG_DW_WATCHDOG=y
CONFIG_LIGHT_PMIC_WATCHDOG=y
CONFIG_WATCHDOG_PRETIMEOUT_GOV=y
CONFIG_WATCHDOG_PRETIMEOUT_GOV_SEL=m
CONFIG_WATCHDOG_PRETIMEOUT_GOV_PANIC=y
#CONFIG_WATCHDOG_PRETIMEOUT_DEFAULT_GOV_PANIC=y
CONFIG_WATCHDOG_PRETIMEOUT_DEFAULT_GOV_NOOP=y
CONFIG_WATCHDOG_OPEN_TIMEOUT=32
CONFIG_ABX500_CORE=y
CONFIG_REGULATOR=y
CONFIG_REGULATOR_FIXED_VOLTAGE=y
CONFIG_MEDIA_SUPPORT=y
# CONFIG_MEDIA_ANALOG_TV_SUPPORT is not set
# CONFIG_MEDIA_DIGITAL_TV_SUPPORT is not set
CONFIG_MEDIA_USB_SUPPORT=y
CONFIG_USB_VIDEO_CLASS=m
CONFIG_V4L_PLATFORM_DRIVERS=y
CONFIG_VIDEO_ASPEED=y
CONFIG_V4L_MEM2MEM_DRIVERS=y
# CONFIG_MEDIA_TUNER_SIMPLE is not set
# CONFIG_MEDIA_TUNER_TDA18250 is not set
# CONFIG_MEDIA_TUNER_TDA8290 is not set
# CONFIG_MEDIA_TUNER_TDA827X is not set
# CONFIG_MEDIA_TUNER_TDA18271 is not set
# CONFIG_MEDIA_TUNER_TDA9887 is not set
# CONFIG_MEDIA_TUNER_TEA5761 is not set
# CONFIG_MEDIA_TUNER_TEA5767 is not set
# CONFIG_MEDIA_TUNER_MSI001 is not set
# CONFIG_MEDIA_TUNER_MT20XX is not set
# CONFIG_MEDIA_TUNER_MT2060 is not set
# CONFIG_MEDIA_TUNER_MT2063 is not set
# CONFIG_MEDIA_TUNER_MT2266 is not set
# CONFIG_MEDIA_TUNER_MT2131 is not set
# CONFIG_MEDIA_TUNER_QT1010 is not set
# CONFIG_MEDIA_TUNER_XC2028 is not set
# CONFIG_MEDIA_TUNER_XC5000 is not set
# CONFIG_MEDIA_TUNER_XC4000 is not set
# CONFIG_MEDIA_TUNER_MXL5005S is not set
# CONFIG_MEDIA_TUNER_MXL5007T is not set
# CONFIG_MEDIA_TUNER_MC44S803 is not set
# CONFIG_MEDIA_TUNER_MAX2165 is not set
# CONFIG_MEDIA_TUNER_TDA18218 is not set
# CONFIG_MEDIA_TUNER_FC0011 is not set
# CONFIG_MEDIA_TUNER_FC0012 is not set
# CONFIG_MEDIA_TUNER_FC0013 is not set
# CONFIG_MEDIA_TUNER_TDA18212 is not set
# CONFIG_MEDIA_TUNER_E4000 is not set
# CONFIG_MEDIA_TUNER_FC2580 is not set
# CONFIG_MEDIA_TUNER_M88RS6000T is not set
# CONFIG_MEDIA_TUNER_TUA9001 is not set
# CONFIG_MEDIA_TUNER_SI2157 is not set
# CONFIG_MEDIA_TUNER_IT913X is not set
# CONFIG_MEDIA_TUNER_R820T is not set
# CONFIG_MEDIA_TUNER_MXL301RF is not set
# CONFIG_MEDIA_TUNER_QM1D1C0042 is not set
# CONFIG_MEDIA_TUNER_QM1D1B0004 is not set
CONFIG_DRM=y
CONFIG_DRM_PANEL_SIMPLE=y
CONFIG_DRM_PANEL_ILITEK_ILI9881C=y
CONFIG_DRM_PANEL_ILI9881D=y
CONFIG_DRM_VERISILICON=y
CONFIG_BACKLIGHT_CLASS_DEVICE=y
CONFIG_BACKLIGHT_PWM=y
CONFIG_FRAMEBUFFER_CONSOLE=y
CONFIG_LOGO=y
CONFIG_SOUND=y
CONFIG_SND=y
CONFIG_SND_USB_AUDIO=m
CONFIG_SND_SOC=y
CONFIG_SND_SOC_THEAD_LIGHT=y
CONFIG_SND_SOC_AW87519=y
CONFIG_SND_SOC_BT_SCO=y
CONFIG_SND_SOC_ES7210=y
CONFIG_SND_SOC_ES8156=y
CONFIG_SND_SOC_WM8960=y
CONFIG_SND_SIMPLE_CARD=y
CONFIG_SND_AUDIO_GRAPH_CARD=y
CONFIG_UHID=y
CONFIG_HID_PID=y
CONFIG_USB_HIDDEV=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_PLATFORM=y
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_USB_STORAGE_SDDR09=y
CONFIG_USB_STORAGE_SDDR55=y
CONFIG_USB_DWC3=m
# CONFIG_USB_DWC3_OF_SIMPLE is not set
CONFIG_USB_GADGET=y
CONFIG_USB_CONFIGFS=y
CONFIG_USB_CONFIGFS_F_FS=y
CONFIG_USB_CONFIGFS_F_ACC=y
CONFIG_USB_ZERO=m
CONFIG_USB_ETH=m
CONFIG_USB_ETH_EEM=y
CONFIG_USB_G_NCM=m
CONFIG_USB_MASS_STORAGE=m
CONFIG_USB_G_SERIAL=m
CONFIG_USB_G_MULTI=m
CONFIG_USB_G_MULTI_CDC=y
CONFIG_USB_ROLE_SWITCH=m
CONFIG_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_PLTFM=y
CONFIG_MMC_SDHCI_OF_DWCMSHC=y
CONFIG_NEW_LEDS=y
CONFIG_LEDS_CLASS=y
CONFIG_LEDS_GPIO=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_DRV_XGENE=y
CONFIG_DMADEVICES=y
CONFIG_DW_AXI_DMAC=y
CONFIG_DMATEST=y
CONFIG_SW_SYNC=y
CONFIG_UDMABUF=y
CONFIG_DMABUF_SELFTESTS=m
CONFIG_VIRTIO_MMIO=y
CONFIG_VIRTIO_KHV_MMIO=y
CONFIG_VHOST_NET=y
CONFIG_VHOST_VSOCK=y
CONFIG_CLK_LIGHT_FM=y
CONFIG_HWSPINLOCK=y
CONFIG_HWSPINLOCK_LIGHT=y
CONFIG_HWSPINLOCK_LIGHT_TEST=m
CONFIG_MAILBOX=y
CONFIG_EXTCON=y
CONFIG_IIO=y
CONFIG_IIO_SW_DEVICE=y
CONFIG_PWM=y
CONFIG_PWM_LIGHT=y
CONFIG_NVMEM_THEAD_LIGHT_EFUSE=y
CONFIG_TEE=y
CONFIG_OPTEE=y
CONFIG_OPTEE_BENCHMARK=y
CONFIG_LIGHT_GPU_VIV=m
# CONFIG_LIGHT_NET is not set
CONFIG_EXT4_FS=y
CONFIG_EXT4_FS_POSIX_ACL=y
CONFIG_AUTOFS4_FS=y
CONFIG_FUSE_FS=y
CONFIG_MSDOS_FS=y
CONFIG_VFAT_FS=y
CONFIG_TMPFS=y
CONFIG_TMPFS_POSIX_ACL=y
CONFIG_HUGETLBFS=y
CONFIG_JFFS2_FS=y
CONFIG_UBIFS_FS=y
CONFIG_NFS_FS=y
CONFIG_NFS_V4=y
CONFIG_NFS_V4_1=y
CONFIG_NFS_V4_2=y
CONFIG_ROOT_NFS=y
CONFIG_9P_FS=y
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_ISO8859_1=y
CONFIG_CRYPTO_AUTHENC=y
CONFIG_CRYPTO_DH=y
CONFIG_CRYPTO_CURVE25519=y
CONFIG_CRYPTO_CHACHA20POLY1305=y
CONFIG_CRYPTO_OFB=y
CONFIG_CRYPTO_MD5=y
CONFIG_CRYPTO_SHA512=y
CONFIG_CRYPTO_SHA3=y
CONFIG_CRYPTO_SM3=y
CONFIG_CRYPTO_DES=y
CONFIG_CRYPTO_USER_API_HASH=y
CONFIG_DMA_CMA=y
CONFIG_DMA_PERNUMA_CMA=y
CONFIG_CMA_SIZE_MBYTES=32
CONFIG_PRINTK_TIME=y
CONFIG_DYNAMIC_DEBUG=y
CONFIG_DEBUG_INFO=y
CONFIG_MAGIC_SYSRQ=y
CONFIG_DEBUG_FS=y
CONFIG_DETECT_HUNG_TASK=y
CONFIG_DEBUG_ATOMIC_SLEEP=y
# CONFIG_RCU_TRACE is not set
CONFIG_OVERLAY_FS=y
CONFIG_LOCKUP_DETECTOR=y
CONFIG_SOFTLOCKUP_DETECTOR=y
CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
# CONFIG_SUSPEND is not set
# CONFIG_PM_SLEEP is not set

View File

@@ -0,0 +1,312 @@
CONFIG_SYSVIPC=y
CONFIG_POSIX_MQUEUE=y
CONFIG_NO_HZ_IDLE=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_PREEMPT=y
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_CGROUPS=y
CONFIG_NAMESPACES=y
CONFIG_USER_NS=y
CONFIG_CHECKPOINT_RESTORE=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_EXPERT=y
# CONFIG_BUG is not set
CONFIG_BPF_SYSCALL=y
CONFIG_PERF_EVENTS=y
CONFIG_FORCE_MAX_ZONEORDER=15
CONFIG_SOC_SIFIVE=y
CONFIG_SOC_THEAD=y
CONFIG_SOC_THEAD_LIGHT_EMU=y
CONFIG_SMP=y
CONFIG_VECTOR=y
CONFIG_VECTOR_0_7=y
CONFIG_KEXEC=y
CONFIG_CRASH_DUMP=y
CONFIG_VIRTUALIZATION=y
CONFIG_KVM=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
CONFIG_CMA=y
CONFIG_CMA_DEBUGFS=y
CONFIG_CMA_AREAS=16
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_INET=y
CONFIG_IP_MULTICAST=y
CONFIG_IP_ADVANCED_ROUTER=y
CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y
CONFIG_IP_PNP_BOOTP=y
CONFIG_IP_PNP_RARP=y
CONFIG_BRIDGE=y
CONFIG_VSOCKETS=y
# CONFIG_VSOCKETS_LOOPBACK is not set
CONFIG_VIRTIO_VSOCKETS=y
CONFIG_NETLINK_DIAG=y
CONFIG_BT=y
CONFIG_BT_RFCOMM=y
CONFIG_BT_RFCOMM_TTY=y
CONFIG_BT_BNEP=y
CONFIG_BT_HIDP=y
CONFIG_BT_HCIUART=y
CONFIG_BT_HCIUART_H4=y
CONFIG_BT_HCIUART_RTL3WIRE=y
CONFIG_CFG80211=y
CONFIG_RFKILL=y
CONFIG_NET_9P=y
CONFIG_NET_9P_VIRTIO=y
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
CONFIG_MTD=y
CONFIG_MTD_TESTS=m
CONFIG_MTD_BLOCK=y
CONFIG_MTD_SLRAM=m
CONFIG_MTD_PHRAM=m
CONFIG_MTD_SPI_NAND=y
CONFIG_MTD_SPI_NOR=y
CONFIG_MTD_UBI=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_VIRTIO_BLK=y
CONFIG_LIGHT_DSMART_CARD=y
CONFIG_EEPROM_AT24=y
CONFIG_SCSI=y
CONFIG_BLK_DEV_SD=y
CONFIG_NETDEVICES=y
CONFIG_TUN=y
CONFIG_VIRTIO_NET=y
CONFIG_MACB=y
CONFIG_STMMAC_ETH=y
CONFIG_DWMAC_LIGHT=y
CONFIG_MICROSEMI_PHY=y
CONFIG_REALTEK_PHY=y
CONFIG_MARVELL_PHY=y
CONFIG_USB_USBNET=m
# CONFIG_USB_NET_AX8817X is not set
# CONFIG_USB_NET_AX88179_178A is not set
# CONFIG_USB_NET_NET1080 is not set
CONFIG_RTL8723DS=y
CONFIG_INPUT_MOUSEDEV=y
CONFIG_INPUT_EVDEV=y
CONFIG_KEYBOARD_GPIO=y
# CONFIG_INPUT_MOUSE is not set
CONFIG_INPUT_TOUCHSCREEN=y
CONFIG_TOUCHSCREEN_GOODIX=y
CONFIG_INPUT_MISC=y
CONFIG_INPUT_UINPUT=y
CONFIG_SERIAL_8250=y
# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_8250_NR_UARTS=6
CONFIG_SERIAL_8250_RUNTIME_UARTS=6
CONFIG_SERIAL_8250_DW=y
CONFIG_SERIAL_OF_PLATFORM=y
CONFIG_SERIAL_EARLYCON_RISCV_SBI=y
CONFIG_VIRTIO_CONSOLE=y
CONFIG_HW_RANDOM=y
CONFIG_HW_RANDOM_VIRTIO=y
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_DESIGNWARE_PLATFORM=y
CONFIG_SPI=y
CONFIG_SPI_DW_QUAD=y
CONFIG_SPI_DESIGNWARE=y
CONFIG_SPI_DW_MMIO=y
CONFIG_SPI_SPIDEV=y
# CONFIG_PTP_1588_CLOCK is not set
CONFIG_PINCTRL=y
CONFIG_GPIOLIB=y
CONFIG_GPIO_SYSFS=y
CONFIG_GPIO_DWAPB=y
CONFIG_GPIO_PCA953X=y
CONFIG_GPIO_PCA953X_IRQ=y
CONFIG_POWER_SUPPLY=y
CONFIG_SENSORS_MR75203=y
CONFIG_THERMAL=y
CONFIG_CPU_THERMAL=y
CONFIG_THERMAL_EMULATION=y
CONFIG_WATCHDOG=y
CONFIG_DW_WATCHDOG=y
CONFIG_LIGHT_PMIC_WATCHDOG=y
CONFIG_WATCHDOG_PRETIMEOUT_GOV=y
CONFIG_WATCHDOG_PRETIMEOUT_GOV_SEL=m
CONFIG_WATCHDOG_PRETIMEOUT_GOV_PANIC=y
#CONFIG_WATCHDOG_PRETIMEOUT_DEFAULT_GOV_PANIC=y
CONFIG_WATCHDOG_PRETIMEOUT_DEFAULT_GOV_NOOP=y
CONFIG_WATCHDOG_OPEN_TIMEOUT=32
CONFIG_ABX500_CORE=y
CONFIG_REGULATOR=y
CONFIG_REGULATOR_FIXED_VOLTAGE=y
CONFIG_MEDIA_SUPPORT=y
# CONFIG_MEDIA_ANALOG_TV_SUPPORT is not set
# CONFIG_MEDIA_DIGITAL_TV_SUPPORT is not set
CONFIG_MEDIA_USB_SUPPORT=y
CONFIG_USB_VIDEO_CLASS=m
CONFIG_V4L_PLATFORM_DRIVERS=y
CONFIG_VIDEO_ASPEED=y
CONFIG_V4L_MEM2MEM_DRIVERS=y
# CONFIG_MEDIA_TUNER_SIMPLE is not set
# CONFIG_MEDIA_TUNER_TDA18250 is not set
# CONFIG_MEDIA_TUNER_TDA8290 is not set
# CONFIG_MEDIA_TUNER_TDA827X is not set
# CONFIG_MEDIA_TUNER_TDA18271 is not set
# CONFIG_MEDIA_TUNER_TDA9887 is not set
# CONFIG_MEDIA_TUNER_TEA5761 is not set
# CONFIG_MEDIA_TUNER_TEA5767 is not set
# CONFIG_MEDIA_TUNER_MSI001 is not set
# CONFIG_MEDIA_TUNER_MT20XX is not set
# CONFIG_MEDIA_TUNER_MT2060 is not set
# CONFIG_MEDIA_TUNER_MT2063 is not set
# CONFIG_MEDIA_TUNER_MT2266 is not set
# CONFIG_MEDIA_TUNER_MT2131 is not set
# CONFIG_MEDIA_TUNER_QT1010 is not set
# CONFIG_MEDIA_TUNER_XC2028 is not set
# CONFIG_MEDIA_TUNER_XC5000 is not set
# CONFIG_MEDIA_TUNER_XC4000 is not set
# CONFIG_MEDIA_TUNER_MXL5005S is not set
# CONFIG_MEDIA_TUNER_MXL5007T is not set
# CONFIG_MEDIA_TUNER_MC44S803 is not set
# CONFIG_MEDIA_TUNER_MAX2165 is not set
# CONFIG_MEDIA_TUNER_TDA18218 is not set
# CONFIG_MEDIA_TUNER_FC0011 is not set
# CONFIG_MEDIA_TUNER_FC0012 is not set
# CONFIG_MEDIA_TUNER_FC0013 is not set
# CONFIG_MEDIA_TUNER_TDA18212 is not set
# CONFIG_MEDIA_TUNER_E4000 is not set
# CONFIG_MEDIA_TUNER_FC2580 is not set
# CONFIG_MEDIA_TUNER_M88RS6000T is not set
# CONFIG_MEDIA_TUNER_TUA9001 is not set
# CONFIG_MEDIA_TUNER_SI2157 is not set
# CONFIG_MEDIA_TUNER_IT913X is not set
# CONFIG_MEDIA_TUNER_R820T is not set
# CONFIG_MEDIA_TUNER_MXL301RF is not set
# CONFIG_MEDIA_TUNER_QM1D1C0042 is not set
# CONFIG_MEDIA_TUNER_QM1D1B0004 is not set
CONFIG_DRM=y
CONFIG_DRM_PANEL_SIMPLE=y
CONFIG_DRM_PANEL_ILITEK_ILI9881C=y
CONFIG_DRM_PANEL_ILI9881D=y
CONFIG_DRM_VERISILICON=y
CONFIG_BACKLIGHT_CLASS_DEVICE=y
CONFIG_BACKLIGHT_PWM=y
CONFIG_FRAMEBUFFER_CONSOLE=y
CONFIG_LOGO=y
CONFIG_SOUND=y
CONFIG_SND=y
CONFIG_SND_USB_AUDIO=m
CONFIG_SND_SOC=y
CONFIG_SND_SOC_THEAD_LIGHT=y
CONFIG_SND_SOC_AW87519=y
CONFIG_SND_SOC_BT_SCO=y
CONFIG_SND_SOC_ES7210=y
CONFIG_SND_SOC_ES8156=y
CONFIG_SND_SOC_WM8960=y
CONFIG_SND_SIMPLE_CARD=y
CONFIG_SND_AUDIO_GRAPH_CARD=y
CONFIG_UHID=y
CONFIG_HID_PID=y
CONFIG_USB_HIDDEV=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_PLATFORM=y
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_USB_STORAGE_SDDR09=y
CONFIG_USB_STORAGE_SDDR55=y
CONFIG_USB_DWC3=m
# CONFIG_USB_DWC3_OF_SIMPLE is not set
CONFIG_USB_GADGET=y
CONFIG_USB_CONFIGFS=y
CONFIG_USB_CONFIGFS_F_FS=y
CONFIG_USB_CONFIGFS_F_ACC=y
CONFIG_USB_ZERO=m
CONFIG_USB_ETH=m
CONFIG_USB_ETH_EEM=y
CONFIG_USB_G_NCM=m
CONFIG_USB_MASS_STORAGE=m
CONFIG_USB_G_SERIAL=m
CONFIG_USB_G_MULTI=m
CONFIG_USB_G_MULTI_CDC=y
CONFIG_USB_ROLE_SWITCH=m
CONFIG_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_PLTFM=y
CONFIG_MMC_SDHCI_OF_DWCMSHC=y
CONFIG_NEW_LEDS=y
CONFIG_LEDS_CLASS=y
CONFIG_LEDS_GPIO=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_DRV_XGENE=y
CONFIG_DMADEVICES=y
CONFIG_DW_AXI_DMAC=y
CONFIG_DMATEST=y
CONFIG_SW_SYNC=y
CONFIG_UDMABUF=y
CONFIG_DMABUF_SELFTESTS=m
CONFIG_VIRTIO_MMIO=y
CONFIG_VIRTIO_KHV_MMIO=y
CONFIG_VHOST_NET=y
CONFIG_VHOST_VSOCK=y
CONFIG_CLK_LIGHT_FM=y
CONFIG_HWSPINLOCK=y
CONFIG_HWSPINLOCK_LIGHT=y
CONFIG_HWSPINLOCK_LIGHT_TEST=m
CONFIG_MAILBOX=y
CONFIG_EXTCON=y
CONFIG_IIO=y
CONFIG_IIO_SW_DEVICE=y
CONFIG_PWM=y
CONFIG_PWM_LIGHT=y
CONFIG_NVMEM_THEAD_LIGHT_EFUSE=y
CONFIG_TEE=y
CONFIG_OPTEE=y
CONFIG_OPTEE_BENCHMARK=y
CONFIG_LIGHT_GPU_VIV=m
# CONFIG_LIGHT_NET is not set
CONFIG_EXT4_FS=y
CONFIG_EXT4_FS_POSIX_ACL=y
CONFIG_AUTOFS4_FS=y
CONFIG_FUSE_FS=y
CONFIG_MSDOS_FS=y
CONFIG_VFAT_FS=y
CONFIG_TMPFS=y
CONFIG_TMPFS_POSIX_ACL=y
CONFIG_HUGETLBFS=y
CONFIG_JFFS2_FS=y
CONFIG_UBIFS_FS=y
CONFIG_NFS_FS=y
CONFIG_NFS_V4=y
CONFIG_NFS_V4_1=y
CONFIG_NFS_V4_2=y
CONFIG_ROOT_NFS=y
CONFIG_9P_FS=y
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_ISO8859_1=y
CONFIG_CRYPTO_AUTHENC=y
CONFIG_CRYPTO_DH=y
CONFIG_CRYPTO_CURVE25519=y
CONFIG_CRYPTO_CHACHA20POLY1305=y
CONFIG_CRYPTO_OFB=y
CONFIG_CRYPTO_MD5=y
CONFIG_CRYPTO_SHA512=y
CONFIG_CRYPTO_SHA3=y
CONFIG_CRYPTO_SM3=y
CONFIG_CRYPTO_DES=y
CONFIG_CRYPTO_USER_API_HASH=y
CONFIG_DMA_CMA=y
CONFIG_DMA_PERNUMA_CMA=y
CONFIG_CMA_SIZE_MBYTES=32
CONFIG_PRINTK_TIME=y
CONFIG_DYNAMIC_DEBUG=y
CONFIG_DEBUG_INFO=y
CONFIG_MAGIC_SYSRQ=y
CONFIG_DEBUG_FS=y
CONFIG_DETECT_HUNG_TASK=y
CONFIG_DEBUG_ATOMIC_SLEEP=y
# CONFIG_RCU_TRACE is not set
CONFIG_OVERLAY_FS=y
CONFIG_LOCKUP_DETECTOR=y
CONFIG_SOFTLOCKUP_DETECTOR=y
CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
# CONFIG_SUSPEND is not set
# CONFIG_PM_SLEEP is not set

View File

@@ -180,6 +180,5 @@ CONFIG_DEBUG_INFO=y
CONFIG_MAGIC_SYSRQ=y CONFIG_MAGIC_SYSRQ=y
CONFIG_DEBUG_FS=y CONFIG_DEBUG_FS=y
CONFIG_DETECT_HUNG_TASK=y CONFIG_DETECT_HUNG_TASK=y
CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=60
CONFIG_DEBUG_ATOMIC_SLEEP=y CONFIG_DEBUG_ATOMIC_SLEEP=y
# CONFIG_RCU_TRACE is not set # CONFIG_RCU_TRACE is not set

View File

@@ -1,34 +1,273 @@
CONFIG_COMPILE_TEST=y # see kernel/configs/android-5.10/android-base.config
CONFIG_SYSVIPC=y # KEEP ALPHABETICALLY SORTED
CONFIG_POSIX_MQUEUE=y # CONFIG_ANDROID_LOW_MEMORY_KILLER is not set
# CONFIG_ANDROID_PARANOID_NETWORK is not set
# CONFIG_BPFILTER is not set
# CONFIG_CRYPTO_MD4 is not set
# CONFIG_DEVMEM is not set
# CONFIG_FHANDLE is not set
# CONFIG_FW_CACHE is not set
# CONFIG_IP6_NF_NAT is not set
# CONFIG_MODULE_FORCE_UNLOAD is not set
# CONFIG_NFSD is not set
# CONFIG_NFS_FS is not set
# CONFIG_PM_AUTOSLEEP is not set
# CONFIG_RT_GROUP_SCHED is not set
# CONFIG_SYSVIPC is not set
# CONFIG_USELIB is not set
CONFIG_ADVISE_SYSCALLS=y
CONFIG_AIO=y
CONFIG_ANDROID=y
CONFIG_ANDROID_BINDER_DEVICES="binder,hwbinder,vndbinder"
CONFIG_ANDROID_BINDER_IPC=y
CONFIG_ANDROID_BINDERFS=y
CONFIG_ASHMEM=y
CONFIG_AUDIT=y CONFIG_AUDIT=y
CONFIG_NO_HZ=y CONFIG_BINFMT_ELF=y
CONFIG_BINFMT_SCRIPT=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLOCK=y
CONFIG_BPF_JIT=y
CONFIG_BPF_SYSCALL=y
CONFIG_CGROUPS=y
CONFIG_CGROUP_BPF=y
CONFIG_CGROUP_CPUACCT=y
CONFIG_CGROUP_FREEZER=y
CONFIG_CGROUP_SCHED=y
CONFIG_CROSS_MEMORY_ATTACH=y
CONFIG_CRYPTO_AES=y
CONFIG_CRYPTO_CBC=y
CONFIG_CRYPTO_CHACHA20POLY1305=y
CONFIG_CRYPTO_CMAC=y
CONFIG_CRYPTO_CTR=y
CONFIG_CRYPTO_ECB=y
CONFIG_CRYPTO_GCM=y
CONFIG_CRYPTO_HMAC=y
CONFIG_CRYPTO_MD5=y
CONFIG_CRYPTO_NULL=y
CONFIG_CRYPTO_SHA1=y
CONFIG_CRYPTO_SHA256=y
CONFIG_CRYPTO_SHA512=y
CONFIG_CRYPTO_XCBC=y
CONFIG_DEBUG_LIST=y
CONFIG_DEFAULT_SECURITY_SELINUX=y
CONFIG_DM_SNAPSHOT=y
CONFIG_DM_VERITY=y
CONFIG_DUMMY=y
CONFIG_EMBEDDED=y
CONFIG_EPOLL=y
CONFIG_EVENTFD=y
CONFIG_FILE_LOCKING=y
CONFIG_FS_ENCRYPTION=y
CONFIG_FS_VERITY=y
CONFIG_FS_VERITY_BUILTIN_SIGNATURES=y
CONFIG_FUSE_FS=y
CONFIG_FUTEX=y
CONFIG_HARDENED_USERCOPY=y
CONFIG_HID_GENERIC=y
CONFIG_HID_PLAYSTATION=y
CONFIG_PLAYSTATION_FF=y
CONFIG_HID_SONY=y
CONFIG_SONY_FF=y
CONFIG_HIGH_RES_TIMERS=y CONFIG_HIGH_RES_TIMERS=y
CONFIG_PREEMPT=y
CONFIG_TASKSTATS=y
CONFIG_TASK_DELAY_ACCT=y
CONFIG_TASK_XACCT=y
CONFIG_TASK_IO_ACCOUNTING=y
CONFIG_PSI=y
CONFIG_IKCONFIG=y CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y CONFIG_IKCONFIG_PROC=y
CONFIG_UCLAMP_TASK=y CONFIG_INET6_ESP=y
CONFIG_CGROUPS=y CONFIG_INET6_IPCOMP=y
CONFIG_CGROUP_SCHED=y CONFIG_INET=y
CONFIG_UCLAMP_TASK_GROUP=y CONFIG_INET_DIAG_DESTROY=y
CONFIG_CGROUP_FREEZER=y CONFIG_INET_ESP=y
CONFIG_CGROUP_CPUACCT=y CONFIG_INET_UDP_DIAG=y
CONFIG_CGROUP_BPF=y CONFIG_INOTIFY_USER=y
CONFIG_INPUT=y
CONFIG_INPUT_EVDEV=y
CONFIG_INPUT_JOYSTICK=y
CONFIG_IP6_NF_FILTER=y
CONFIG_IP6_NF_IPTABLES=y
CONFIG_IP6_NF_MANGLE=y
CONFIG_IP6_NF_MATCH_RPFILTER=y
CONFIG_IP6_NF_RAW=y
CONFIG_IP6_NF_TARGET_REJECT=y
CONFIG_IPV6=y
CONFIG_IPV6_MIP6=y
CONFIG_IPV6_MULTIPLE_TABLES=y
CONFIG_IPV6_OPTIMISTIC_DAD=y
CONFIG_IPV6_ROUTER_PREF=y
CONFIG_IPV6_ROUTE_INFO=y
CONFIG_IPV6_VTI=y
CONFIG_IP_ADVANCED_ROUTER=y
CONFIG_IP_MULTICAST=y
CONFIG_IP_MULTIPLE_TABLES=y
CONFIG_IP_NF_ARPFILTER=y
CONFIG_IP_NF_ARPTABLES=y
CONFIG_IP_NF_ARP_MANGLE=y
CONFIG_IP_NF_FILTER=y
CONFIG_IP_NF_IPTABLES=y
CONFIG_IP_NF_MANGLE=y
CONFIG_IP_NF_MATCH_ECN=y
CONFIG_IP_NF_MATCH_TTL=y
CONFIG_IP_NF_NAT=y
CONFIG_IP_NF_RAW=y
CONFIG_IP_NF_SECURITY=y
CONFIG_IP_NF_TARGET_MASQUERADE=y
CONFIG_IP_NF_TARGET_NETMAP=y
CONFIG_IP_NF_TARGET_REDIRECT=y
CONFIG_IP_NF_TARGET_REJECT=y
CONFIG_JOYSTICK_XPAD=y
CONFIG_L2TP=y
CONFIG_MAGIC_SYSRQ=y
CONFIG_MD=y
CONFIG_MEMBARRIER=y
CONFIG_MMU=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
CONFIG_MODVERSIONS=y
CONFIG_MULTIUSER=y
CONFIG_NAMESPACES=y CONFIG_NAMESPACES=y
CONFIG_NET=y
CONFIG_NETDEVICES=y
CONFIG_NETFILTER=y
CONFIG_NETFILTER_XT_MATCH_BPF=y
CONFIG_NETFILTER_XT_MATCH_COMMENT=y
CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y
CONFIG_NETFILTER_XT_MATCH_CONNMARK=y
CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y
CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=y
CONFIG_NETFILTER_XT_MATCH_HELPER=y
CONFIG_NETFILTER_XT_MATCH_IPRANGE=y
CONFIG_NETFILTER_XT_MATCH_LENGTH=y
CONFIG_NETFILTER_XT_MATCH_LIMIT=y
CONFIG_NETFILTER_XT_MATCH_MAC=y
CONFIG_NETFILTER_XT_MATCH_MARK=y
CONFIG_NETFILTER_XT_MATCH_OWNER=y
CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y
CONFIG_NETFILTER_XT_MATCH_POLICY=y
CONFIG_NETFILTER_XT_MATCH_QUOTA2=y
CONFIG_NETFILTER_XT_MATCH_QUOTA2_LOG=y
CONFIG_NETFILTER_XT_MATCH_QUOTA=y
CONFIG_NETFILTER_XT_MATCH_SOCKET=y
CONFIG_NETFILTER_XT_MATCH_STATE=y
CONFIG_NETFILTER_XT_MATCH_STATISTIC=y
CONFIG_NETFILTER_XT_MATCH_STRING=y
CONFIG_NETFILTER_XT_MATCH_TIME=y
CONFIG_NETFILTER_XT_MATCH_U32=y
CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y
CONFIG_NETFILTER_XT_TARGET_CONNMARK=y
CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=y
CONFIG_NETFILTER_XT_TARGET_CT=y
CONFIG_NETFILTER_XT_TARGET_IDLETIMER=y
CONFIG_NETFILTER_XT_TARGET_MARK=y
CONFIG_NETFILTER_XT_TARGET_NFLOG=y
CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y
CONFIG_NETFILTER_XT_TARGET_SECMARK=y
CONFIG_NETFILTER_XT_TARGET_TCPMSS=y
CONFIG_NETFILTER_XT_TARGET_TPROXY=y
CONFIG_NETFILTER_XT_TARGET_TRACE=y
CONFIG_NET_CLS_ACT=y
CONFIG_NET_CLS_BPF=y
CONFIG_NET_CLS_U32=y
CONFIG_NET_EMATCH=y
CONFIG_NET_EMATCH_U32=y
CONFIG_NET_IPGRE_DEMUX=y
CONFIG_NET_IPVTI=y
CONFIG_NET_KEY=y
CONFIG_NET_NS=y
CONFIG_NET_SCHED=y
CONFIG_NET_SCH_HTB=y
CONFIG_NET_SCH_INGRESS=y
CONFIG_NF_CONNTRACK=y
CONFIG_NF_CONNTRACK_AMANDA=y
CONFIG_NF_CONNTRACK_EVENTS=y
CONFIG_NF_CONNTRACK_FTP=y
CONFIG_NF_CONNTRACK_H323=y
CONFIG_NF_CONNTRACK_IRC=y
CONFIG_NF_CONNTRACK_NETBIOS_NS=y
CONFIG_NF_CONNTRACK_PPTP=y
CONFIG_NF_CONNTRACK_SANE=y
CONFIG_NF_CONNTRACK_SECMARK=y
CONFIG_NF_CONNTRACK_TFTP=y
CONFIG_NF_CT_NETLINK=y
CONFIG_NF_CT_PROTO_DCCP=y
CONFIG_NF_CT_PROTO_SCTP=y
CONFIG_NF_CT_PROTO_UDPLITE=y
CONFIG_NF_NAT=y
CONFIG_NF_SOCKET_IPV4=y
CONFIG_NF_SOCKET_IPV6=y
CONFIG_NO_HZ=y
CONFIG_PACKET=y
CONFIG_PM_WAKELOCKS=y
CONFIG_POSIX_TIMERS=y
CONFIG_PPP=y
CONFIG_PPPOL2TP=y
CONFIG_PPP_BSDCOMP=y
CONFIG_PPP_DEFLATE=y
CONFIG_PPP_MPPE=y
CONFIG_PPTP=y
CONFIG_PREEMPT=y
CONFIG_PROC_FS=y
CONFIG_PROFILING=y
CONFIG_PSI=y
CONFIG_QFMT_V2=y
CONFIG_QUOTA=y
CONFIG_QUOTACTL=y
CONFIG_RD_LZ4=y
CONFIG_RTC_CLASS=y
CONFIG_SCHED_DEBUG=y
CONFIG_SECCOMP=y
CONFIG_SECCOMP_FILTER=y
CONFIG_SECURITY=y
CONFIG_SECURITY_NETWORK=y
CONFIG_SECURITY_SELINUX=y
CONFIG_SHMEM=y
CONFIG_SIGNALFD=y
CONFIG_SND=y
CONFIG_SOUND=y
CONFIG_STACKPROTECTOR=y
CONFIG_STACKPROTECTOR_STRONG=y
CONFIG_STAGING=y
CONFIG_STATIC_USERMODEHELPER=y
CONFIG_STRICT_KERNEL_RWX=y
CONFIG_STRICT_MODULE_RWX=y
CONFIG_SUSPEND=y
CONFIG_SYNC_FILE=y
CONFIG_SYSFS=y
CONFIG_TASKSTATS=y
CONFIG_TASK_IO_ACCOUNTING=y
CONFIG_TASK_XACCT=y
CONFIG_TIMERFD=y
CONFIG_TRACE_GPU_MEM=y
CONFIG_TTY=y
CONFIG_TUN=y
CONFIG_UHID=y
CONFIG_UID_SYS_STATS=y
CONFIG_UNIX=y
CONFIG_USB=y
CONFIG_USB_CONFIGFS=y
CONFIG_USB_CONFIGFS_F_ACC=y
CONFIG_USB_CONFIGFS_F_AUDIO_SRC=y
CONFIG_USB_CONFIGFS_F_FS=y
CONFIG_USB_CONFIGFS_F_MIDI=y
CONFIG_USB_CONFIGFS_UEVENT=y
CONFIG_USB_GADGET=y
CONFIG_USB_SUPPORT=y
CONFIG_UTS_NS=y
CONFIG_VETH=y
CONFIG_XFRM_INTERFACE=y
CONFIG_XFRM_MIGRATE=y
CONFIG_XFRM_STATISTICS=y
CONFIG_XFRM_USER=y
# kernel/configs/android-5.10/android-base.config
CONFIG_COMPILE_TEST=y
CONFIG_POSIX_MQUEUE=y
CONFIG_TASK_DELAY_ACCT=y
CONFIG_UCLAMP_TASK=y
CONFIG_UCLAMP_TASK_GROUP=y
CONFIG_USER_NS=y CONFIG_USER_NS=y
CONFIG_CHECKPOINT_RESTORE=y CONFIG_CHECKPOINT_RESTORE=y
CONFIG_BLK_DEV_INITRD=y
# CONFIG_FHANDLE is not set
# CONFIG_BUG is not set # CONFIG_BUG is not set
CONFIG_KALLSYMS_ALL=y CONFIG_KALLSYMS_ALL=y
CONFIG_BPF_SYSCALL=y
CONFIG_EMBEDDED=y
CONFIG_PROFILING=y
CONFIG_SOC_SIFIVE=y CONFIG_SOC_SIFIVE=y
CONFIG_SOC_THEAD=y CONFIG_SOC_THEAD=y
CONFIG_SMP=y CONFIG_SMP=y
@@ -43,135 +282,29 @@ CONFIG_CPU_FREQ_GOV_USERSPACE=y
CONFIG_CPU_FREQ_GOV_ONDEMAND=y CONFIG_CPU_FREQ_GOV_ONDEMAND=y
CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
CONFIG_CPUFREQ_DT=y CONFIG_CPUFREQ_DT=y
CONFIG_RISV_THEAD_LIGHT_CPUFREQ=y CONFIG_RISV_THEAD_LIGHT_CPUFREQ=y
CONFIG_PM_WAKELOCKS=y CONFIG_PM_WAKELOCKS_LIMIT=0
# CONFIG_PM_WAKELOCKS_GC is not set
CONFIG_ENERGY_MODEL=y CONFIG_ENERGY_MODEL=y
CONFIG_VIRTUALIZATION=y CONFIG_VIRTUALIZATION=y
CONFIG_KVM=y CONFIG_KVM=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
CONFIG_MODVERSIONS=y
CONFIG_BLK_INLINE_ENCRYPTION=y CONFIG_BLK_INLINE_ENCRYPTION=y
# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
CONFIG_CMA=y CONFIG_CMA=y
CONFIG_CMA_DEBUGFS=y CONFIG_CMA_DEBUGFS=y
CONFIG_CMA_AREAS=16 CONFIG_CMA_AREAS=16
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_XFRM_USER=y
CONFIG_XFRM_INTERFACE=y
CONFIG_XFRM_MIGRATE=y
CONFIG_XFRM_STATISTICS=y
CONFIG_NET_KEY=y
CONFIG_INET=y
CONFIG_IP_MULTICAST=y
CONFIG_IP_ADVANCED_ROUTER=y
CONFIG_IP_MULTIPLE_TABLES=y
CONFIG_IP_PNP=y CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y CONFIG_IP_PNP_DHCP=y
CONFIG_IP_PNP_BOOTP=y CONFIG_IP_PNP_BOOTP=y
CONFIG_IP_PNP_RARP=y CONFIG_IP_PNP_RARP=y
CONFIG_NET_IPGRE_DEMUX=y
CONFIG_NET_IPVTI=y
CONFIG_INET_ESP=y
CONFIG_INET_UDP_DIAG=y
CONFIG_INET_DIAG_DESTROY=y
CONFIG_IPV6_ROUTER_PREF=y
CONFIG_IPV6_ROUTE_INFO=y
CONFIG_IPV6_OPTIMISTIC_DAD=y
CONFIG_INET6_ESP=y
CONFIG_INET6_IPCOMP=y
CONFIG_IPV6_MIP6=y
CONFIG_IPV6_VTI=y
CONFIG_IPV6_MULTIPLE_TABLES=y
CONFIG_NETFILTER=y
CONFIG_NF_CONNTRACK=y
CONFIG_NF_CONNTRACK_SECMARK=y
CONFIG_NF_CONNTRACK_EVENTS=y
CONFIG_NF_CONNTRACK_AMANDA=y
CONFIG_NF_CONNTRACK_FTP=y
CONFIG_NF_CONNTRACK_H323=y
CONFIG_NF_CONNTRACK_IRC=y
CONFIG_NF_CONNTRACK_NETBIOS_NS=y
CONFIG_NF_CONNTRACK_PPTP=y
CONFIG_NF_CONNTRACK_SANE=y
CONFIG_NF_CONNTRACK_TFTP=y
CONFIG_NF_CT_NETLINK=y
CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y
CONFIG_NETFILTER_XT_TARGET_CONNMARK=y
CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=y
CONFIG_NETFILTER_XT_TARGET_CT=y
CONFIG_NETFILTER_XT_TARGET_IDLETIMER=y
CONFIG_NETFILTER_XT_TARGET_MARK=y
CONFIG_NETFILTER_XT_TARGET_NFLOG=y
CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y
CONFIG_NETFILTER_XT_TARGET_TPROXY=y
CONFIG_NETFILTER_XT_TARGET_TRACE=y
CONFIG_NETFILTER_XT_TARGET_SECMARK=y
CONFIG_NETFILTER_XT_TARGET_TCPMSS=y
CONFIG_NETFILTER_XT_MATCH_BPF=y
CONFIG_NETFILTER_XT_MATCH_COMMENT=y
CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y
CONFIG_NETFILTER_XT_MATCH_CONNMARK=y
CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y
CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=y
CONFIG_NETFILTER_XT_MATCH_HELPER=y
CONFIG_NETFILTER_XT_MATCH_IPRANGE=y
CONFIG_NETFILTER_XT_MATCH_LENGTH=y
CONFIG_NETFILTER_XT_MATCH_LIMIT=y
CONFIG_NETFILTER_XT_MATCH_MAC=y
CONFIG_NETFILTER_XT_MATCH_MARK=y
CONFIG_NETFILTER_XT_MATCH_OWNER=y
CONFIG_NETFILTER_XT_MATCH_POLICY=y
CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y
CONFIG_NETFILTER_XT_MATCH_QUOTA=y
CONFIG_NETFILTER_XT_MATCH_QUOTA2=y
CONFIG_NETFILTER_XT_MATCH_QUOTA2_LOG=y
CONFIG_NETFILTER_XT_MATCH_SOCKET=y
CONFIG_NETFILTER_XT_MATCH_STATE=y
CONFIG_NETFILTER_XT_MATCH_STATISTIC=y
CONFIG_NETFILTER_XT_MATCH_STRING=y
CONFIG_NETFILTER_XT_MATCH_TIME=y
CONFIG_NETFILTER_XT_MATCH_U32=y
CONFIG_IP_NF_IPTABLES=y
CONFIG_IP_NF_MATCH_ECN=y
CONFIG_IP_NF_MATCH_TTL=y
CONFIG_IP_NF_FILTER=y
CONFIG_IP_NF_TARGET_REJECT=y
CONFIG_IP_NF_NAT=y
CONFIG_IP_NF_TARGET_MASQUERADE=y
CONFIG_IP_NF_TARGET_NETMAP=y
CONFIG_IP_NF_TARGET_REDIRECT=y
CONFIG_IP_NF_MANGLE=y
CONFIG_IP_NF_RAW=y
CONFIG_IP_NF_SECURITY=y
CONFIG_IP_NF_ARPTABLES=y
CONFIG_IP_NF_ARPFILTER=y
CONFIG_IP_NF_ARP_MANGLE=y
CONFIG_IP6_NF_IPTABLES=y
CONFIG_IP6_NF_MATCH_RPFILTER=y
CONFIG_IP6_NF_FILTER=y
CONFIG_IP6_NF_TARGET_REJECT=y
CONFIG_IP6_NF_MANGLE=y
CONFIG_IP6_NF_RAW=y
CONFIG_L2TP=y
CONFIG_BRIDGE=y CONFIG_BRIDGE=y
CONFIG_NET_SCHED=y
CONFIG_NET_SCH_HTB=y
CONFIG_NET_SCH_NETEM=y CONFIG_NET_SCH_NETEM=y
CONFIG_NET_SCH_INGRESS=y
CONFIG_NET_CLS_U32=y
CONFIG_NET_CLS_BPF=y
CONFIG_NET_EMATCH=y
CONFIG_NET_EMATCH_U32=y
CONFIG_NET_CLS_ACT=y
CONFIG_VSOCKETS=y CONFIG_VSOCKETS=y
# CONFIG_VSOCKETS_LOOPBACK is not set # CONFIG_VSOCKETS_LOOPBACK is not set
CONFIG_VIRTIO_VSOCKETS=y CONFIG_VIRTIO_VSOCKETS=y
CONFIG_NETLINK_DIAG=y CONFIG_NETLINK_DIAG=y
CONFIG_BPF_JIT=y
CONFIG_BT=y CONFIG_BT=y
CONFIG_BT_RFCOMM=y CONFIG_BT_RFCOMM=y
CONFIG_BT_RFCOMM_TTY=y CONFIG_BT_RFCOMM_TTY=y
@@ -194,48 +327,30 @@ CONFIG_MTD_PHRAM=m
CONFIG_MTD_SPI_NAND=y CONFIG_MTD_SPI_NAND=y
CONFIG_MTD_SPI_NOR=y CONFIG_MTD_SPI_NOR=y
CONFIG_MTD_UBI=y CONFIG_MTD_UBI=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_SIZE=8192 CONFIG_BLK_DEV_RAM_SIZE=8192
CONFIG_VIRTIO_BLK=y CONFIG_VIRTIO_BLK=y
CONFIG_UID_SYS_STATS=y
CONFIG_LIGHT_DSMART_CARD=y CONFIG_LIGHT_DSMART_CARD=y
CONFIG_EEPROM_AT24=y CONFIG_EEPROM_AT24=y
CONFIG_SCSI=y CONFIG_SCSI=y
CONFIG_BLK_DEV_SD=y CONFIG_BLK_DEV_SD=y
CONFIG_MD=y
CONFIG_BLK_DEV_DM=y CONFIG_BLK_DEV_DM=y
CONFIG_DM_CRYPT=y CONFIG_DM_CRYPT=y
CONFIG_DM_DEFAULT_KEY=y CONFIG_DM_DEFAULT_KEY=y
CONFIG_DM_SNAPSHOT=y
CONFIG_DM_UEVENT=y CONFIG_DM_UEVENT=y
CONFIG_DM_VERITY=y
CONFIG_DM_VERITY_FEC=y CONFIG_DM_VERITY_FEC=y
CONFIG_DM_BOW=y CONFIG_DM_BOW=y
CONFIG_NETDEVICES=y
CONFIG_DUMMY=y
CONFIG_TUN=y
CONFIG_VETH=y
CONFIG_VIRTIO_NET=y CONFIG_VIRTIO_NET=y
CONFIG_MACB=y CONFIG_MACB=y
CONFIG_STMMAC_ETH=y CONFIG_STMMAC_ETH=y
CONFIG_DWMAC_LIGHT=y CONFIG_DWMAC_LIGHT=y
CONFIG_MICROSEMI_PHY=y CONFIG_MICROSEMI_PHY=y
CONFIG_REALTEK_PHY=y CONFIG_REALTEK_PHY=y
CONFIG_PPP=y
CONFIG_PPP_BSDCOMP=y
CONFIG_PPP_DEFLATE=y
CONFIG_PPP_MPPE=y
CONFIG_PPTP=y
CONFIG_PPPOL2TP=y
CONFIG_USB_RTL8152=y CONFIG_USB_RTL8152=y
CONFIG_USB_USBNET=m CONFIG_USB_USBNET=m
CONFIG_RTL8723DS=y CONFIG_RTL8723DS=y
CONFIG_INPUT_MOUSEDEV=m CONFIG_INPUT_MOUSEDEV=m
CONFIG_INPUT_EVDEV=y
CONFIG_KEYBOARD_GPIO=y CONFIG_KEYBOARD_GPIO=y
CONFIG_INPUT_JOYSTICK=y
CONFIG_JOYSTICK_XPAD=y
CONFIG_JOYSTICK_XPAD_FF=y CONFIG_JOYSTICK_XPAD_FF=y
CONFIG_JOYSTICK_XPAD_LEDS=y CONFIG_JOYSTICK_XPAD_LEDS=y
CONFIG_INPUT_TABLET=y CONFIG_INPUT_TABLET=y
@@ -291,8 +406,6 @@ CONFIG_DRM_VERISILICON=y
CONFIG_BACKLIGHT_CLASS_DEVICE=y CONFIG_BACKLIGHT_CLASS_DEVICE=y
CONFIG_BACKLIGHT_PWM=y CONFIG_BACKLIGHT_PWM=y
CONFIG_LOGO=y CONFIG_LOGO=y
CONFIG_SOUND=y
CONFIG_SND=y
CONFIG_SND_USB_AUDIO=m CONFIG_SND_USB_AUDIO=m
CONFIG_SND_SOC=y CONFIG_SND_SOC=y
CONFIG_SND_SOC_THEAD_LIGHT=y CONFIG_SND_SOC_THEAD_LIGHT=y
@@ -301,7 +414,6 @@ CONFIG_SND_SOC_WM8960=y
CONFIG_SND_SIMPLE_CARD=y CONFIG_SND_SIMPLE_CARD=y
CONFIG_SND_AUDIO_GRAPH_CARD=y CONFIG_SND_AUDIO_GRAPH_CARD=y
CONFIG_HIDRAW=y CONFIG_HIDRAW=y
CONFIG_UHID=y
CONFIG_HID_A4TECH=y CONFIG_HID_A4TECH=y
CONFIG_HID_ACRUX=y CONFIG_HID_ACRUX=y
CONFIG_HID_ACRUX_FF=y CONFIG_HID_ACRUX_FF=y
@@ -340,14 +452,10 @@ CONFIG_HID_PANTHERLORD=y
CONFIG_PANTHERLORD_FF=y CONFIG_PANTHERLORD_FF=y
CONFIG_HID_PETALYNX=y CONFIG_HID_PETALYNX=y
CONFIG_HID_PICOLCD=y CONFIG_HID_PICOLCD=y
CONFIG_HID_PLAYSTATION=y
CONFIG_PLAYSTATION_FF=y
CONFIG_HID_PRIMAX=y CONFIG_HID_PRIMAX=y
CONFIG_HID_ROCCAT=y CONFIG_HID_ROCCAT=y
CONFIG_HID_SAITEK=y CONFIG_HID_SAITEK=y
CONFIG_HID_SAMSUNG=y CONFIG_HID_SAMSUNG=y
CONFIG_HID_SONY=y
CONFIG_SONY_FF=y
CONFIG_HID_SPEEDLINK=y CONFIG_HID_SPEEDLINK=y
CONFIG_HID_STEAM=y CONFIG_HID_STEAM=y
CONFIG_HID_SUNPLUS=y CONFIG_HID_SUNPLUS=y
@@ -374,13 +482,6 @@ CONFIG_USB_STORAGE_SDDR09=y
CONFIG_USB_STORAGE_SDDR55=y CONFIG_USB_STORAGE_SDDR55=y
CONFIG_USB_DWC3=m CONFIG_USB_DWC3=m
# CONFIG_USB_DWC3_OF_SIMPLE is not set # CONFIG_USB_DWC3_OF_SIMPLE is not set
CONFIG_USB_GADGET=y
CONFIG_USB_CONFIGFS=y
CONFIG_USB_CONFIGFS_UEVENT=y
CONFIG_USB_CONFIGFS_F_FS=y
CONFIG_USB_CONFIGFS_F_ACC=y
CONFIG_USB_CONFIGFS_F_AUDIO_SRC=y
CONFIG_USB_CONFIGFS_F_MIDI=y
CONFIG_USB_ZERO=m CONFIG_USB_ZERO=m
CONFIG_USB_ETH=m CONFIG_USB_ETH=m
CONFIG_USB_ETH_EEM=y CONFIG_USB_ETH_EEM=y
@@ -394,7 +495,6 @@ CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_PLTFM=y CONFIG_MMC_SDHCI_PLTFM=y
CONFIG_MMC_SDHCI_OF_DWCMSHC=y CONFIG_MMC_SDHCI_OF_DWCMSHC=y
CONFIG_LEDS_GPIO=y CONFIG_LEDS_GPIO=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_DRV_XGENE=y CONFIG_RTC_DRV_XGENE=y
CONFIG_DMADEVICES=y CONFIG_DMADEVICES=y
CONFIG_DW_AXI_DMAC=y CONFIG_DW_AXI_DMAC=y
@@ -410,8 +510,6 @@ CONFIG_DMABUF_HEAPS_SYSTEM=y
# CONFIG_VIRTIO_MENU is not set # CONFIG_VIRTIO_MENU is not set
CONFIG_VHOST_NET=y CONFIG_VHOST_NET=y
CONFIG_VHOST_VSOCK=y CONFIG_VHOST_VSOCK=y
CONFIG_STAGING=y
CONFIG_ASHMEM=y
CONFIG_ION=y CONFIG_ION=y
CONFIG_ION_SYSTEM_HEAP=y CONFIG_ION_SYSTEM_HEAP=y
CONFIG_ION_CMA_HEAP=y CONFIG_ION_CMA_HEAP=y
@@ -424,8 +522,6 @@ CONFIG_IIO=y
CONFIG_IIO_SW_DEVICE=y CONFIG_IIO_SW_DEVICE=y
CONFIG_PWM=y CONFIG_PWM=y
CONFIG_PWM_LIGHT=y CONFIG_PWM_LIGHT=y
CONFIG_ANDROID=y
CONFIG_ANDROID_BINDER_IPC=y
CONFIG_NVMEM_THEAD_LIGHT_EFUSE=y CONFIG_NVMEM_THEAD_LIGHT_EFUSE=y
CONFIG_LIGHT_GPU_VIV=m CONFIG_LIGHT_GPU_VIV=m
# CONFIG_LIGHT_NET is not set # CONFIG_LIGHT_NET is not set
@@ -434,14 +530,8 @@ CONFIG_EXT4_FS_POSIX_ACL=y
CONFIG_EXT4_FS_SECURITY=y CONFIG_EXT4_FS_SECURITY=y
CONFIG_F2FS_FS=y CONFIG_F2FS_FS=y
CONFIG_F2FS_FS_SECURITY=y CONFIG_F2FS_FS_SECURITY=y
CONFIG_FS_ENCRYPTION=y
CONFIG_FS_ENCRYPTION_INLINE_CRYPT=y CONFIG_FS_ENCRYPTION_INLINE_CRYPT=y
CONFIG_FS_VERITY=y
CONFIG_FS_VERITY_BUILTIN_SIGNATURES=y
CONFIG_QUOTA=y
CONFIG_QFMT_V2=y
CONFIG_AUTOFS4_FS=y CONFIG_AUTOFS4_FS=y
CONFIG_FUSE_FS=y
CONFIG_OVERLAY_FS=y CONFIG_OVERLAY_FS=y
CONFIG_MSDOS_FS=y CONFIG_MSDOS_FS=y
CONFIG_VFAT_FS=y CONFIG_VFAT_FS=y
@@ -457,17 +547,9 @@ CONFIG_PSTORE_RAM=y
CONFIG_9P_FS=y CONFIG_9P_FS=y
CONFIG_NLS_CODEPAGE_437=y CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_ISO8859_1=y CONFIG_NLS_ISO8859_1=y
CONFIG_SECURITY=y
CONFIG_SECURITY_NETWORK=y
CONFIG_HARDENED_USERCOPY=y
CONFIG_STATIC_USERMODEHELPER=y
CONFIG_SECURITY_SELINUX=y
CONFIG_CRYPTO_DH=y CONFIG_CRYPTO_DH=y
CONFIG_CRYPTO_CURVE25519=y CONFIG_CRYPTO_CURVE25519=y
CONFIG_CRYPTO_CHACHA20POLY1305=y
CONFIG_CRYPTO_OFB=y CONFIG_CRYPTO_OFB=y
CONFIG_CRYPTO_XCBC=y
CONFIG_CRYPTO_MD5=y
CONFIG_CRYPTO_SHA3=y CONFIG_CRYPTO_SHA3=y
CONFIG_CRYPTO_SM3=y CONFIG_CRYPTO_SM3=y
CONFIG_CRYPTO_DES=y CONFIG_CRYPTO_DES=y
@@ -477,14 +559,12 @@ CONFIG_DMA_PERNUMA_CMA=y
CONFIG_CMA_SIZE_MBYTES=32 CONFIG_CMA_SIZE_MBYTES=32
CONFIG_PRINTK_TIME=y CONFIG_PRINTK_TIME=y
CONFIG_DYNAMIC_DEBUG=y CONFIG_DYNAMIC_DEBUG=y
CONFIG_MAGIC_SYSRQ=y
CONFIG_DEBUG_FS=y CONFIG_DEBUG_FS=y
CONFIG_PANIC_TIMEOUT=5 CONFIG_PANIC_TIMEOUT=5
CONFIG_DETECT_HUNG_TASK=y CONFIG_DETECT_HUNG_TASK=y
CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=60
CONFIG_SCHEDSTATS=y CONFIG_SCHEDSTATS=y
CONFIG_DEBUG_ATOMIC_SLEEP=y CONFIG_DEBUG_ATOMIC_SLEEP=y
CONFIG_DEBUG_LIST=y
# CONFIG_GCC_PLUGINS is not set # CONFIG_GCC_PLUGINS is not set
# CONFIG_RCU_TRACE is not set # CONFIG_RCU_TRACE is not set
CONFIG_ENABLE_DEFAULT_TRACERS=y CONFIG_ENABLE_DEFAULT_TRACERS=y
CONFIG_GKI_HACKS_TO_FIX=y

View File

@@ -3,6 +3,10 @@ CONFIG_POSIX_MQUEUE=y
CONFIG_NO_HZ_IDLE=y CONFIG_NO_HZ_IDLE=y
CONFIG_HIGH_RES_TIMERS=y CONFIG_HIGH_RES_TIMERS=y
CONFIG_PREEMPT=y CONFIG_PREEMPT=y
CONFIG_TASKSTATS=y
CONFIG_TASK_DELAY_ACCT=y
CONFIG_TASK_XACCT=y
CONFIG_TASK_IO_ACCOUNTING=y
CONFIG_IKCONFIG=y CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y CONFIG_IKCONFIG_PROC=y
CONFIG_CGROUPS=y CONFIG_CGROUPS=y
@@ -31,7 +35,7 @@ CONFIG_CPU_FREQ_GOV_USERSPACE=y
CONFIG_CPU_FREQ_GOV_ONDEMAND=y CONFIG_CPU_FREQ_GOV_ONDEMAND=y
CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
CONFIG_CPUFREQ_DT=y CONFIG_CPUFREQ_DT=y
CONFIG_RISV_THEAD_LIGHT_CPUFREQ=y CONFIG_RISV_THEAD_LIGHT_CPUFREQ=y
CONFIG_VIRTUALIZATION=y CONFIG_VIRTUALIZATION=y
@@ -91,6 +95,7 @@ CONFIG_TUN=y
CONFIG_VIRTIO_NET=y CONFIG_VIRTIO_NET=y
CONFIG_MACB=y CONFIG_MACB=y
CONFIG_STMMAC_ETH=y CONFIG_STMMAC_ETH=y
CONFIG_STMMAC_RX_ZERO_COPY=y
CONFIG_DWMAC_LIGHT=y CONFIG_DWMAC_LIGHT=y
CONFIG_MICROSEMI_PHY=y CONFIG_MICROSEMI_PHY=y
CONFIG_REALTEK_PHY=y CONFIG_REALTEK_PHY=y
@@ -105,6 +110,7 @@ CONFIG_KEYBOARD_GPIO=y
# CONFIG_INPUT_MOUSE is not set # CONFIG_INPUT_MOUSE is not set
CONFIG_INPUT_TOUCHSCREEN=y CONFIG_INPUT_TOUCHSCREEN=y
CONFIG_TOUCHSCREEN_GOODIX=y CONFIG_TOUCHSCREEN_GOODIX=y
CONFIG_TOUCHSCREEN_GT9XX=y
CONFIG_INPUT_MISC=y CONFIG_INPUT_MISC=y
CONFIG_INPUT_UINPUT=y CONFIG_INPUT_UINPUT=y
CONFIG_SERIAL_8250=y CONFIG_SERIAL_8250=y
@@ -143,7 +149,8 @@ CONFIG_LIGHT_PMIC_WATCHDOG=y
CONFIG_WATCHDOG_PRETIMEOUT_GOV=y CONFIG_WATCHDOG_PRETIMEOUT_GOV=y
CONFIG_WATCHDOG_PRETIMEOUT_GOV_SEL=m CONFIG_WATCHDOG_PRETIMEOUT_GOV_SEL=m
CONFIG_WATCHDOG_PRETIMEOUT_GOV_PANIC=y CONFIG_WATCHDOG_PRETIMEOUT_GOV_PANIC=y
CONFIG_WATCHDOG_PRETIMEOUT_DEFAULT_GOV_PANIC=y #CONFIG_WATCHDOG_PRETIMEOUT_DEFAULT_GOV_PANIC=y
CONFIG_WATCHDOG_PRETIMEOUT_DEFAULT_GOV_NOOP=y
CONFIG_WATCHDOG_OPEN_TIMEOUT=32 CONFIG_WATCHDOG_OPEN_TIMEOUT=32
CONFIG_ABX500_CORE=y CONFIG_ABX500_CORE=y
CONFIG_REGULATOR=y CONFIG_REGULATOR=y
@@ -196,6 +203,10 @@ CONFIG_V4L_MEM2MEM_DRIVERS=y
CONFIG_DRM=y CONFIG_DRM=y
CONFIG_DRM_PANEL_SIMPLE=y CONFIG_DRM_PANEL_SIMPLE=y
CONFIG_DRM_PANEL_ILITEK_ILI9881C=y CONFIG_DRM_PANEL_ILITEK_ILI9881C=y
CONFIG_DRM_PANEL_ILI9881D=y
CONFIG_DRM_PANEL_HX8394=y
CONFIG_DRM_PANEL_JADARD_JD9365DA_H3=y
CONFIG_DRM_PANEL_HX8279=y
CONFIG_DRM_VERISILICON=y CONFIG_DRM_VERISILICON=y
CONFIG_BACKLIGHT_CLASS_DEVICE=y CONFIG_BACKLIGHT_CLASS_DEVICE=y
CONFIG_BACKLIGHT_PWM=y CONFIG_BACKLIGHT_PWM=y
@@ -262,13 +273,18 @@ CONFIG_HWSPINLOCK=y
CONFIG_HWSPINLOCK_LIGHT=y CONFIG_HWSPINLOCK_LIGHT=y
CONFIG_HWSPINLOCK_LIGHT_TEST=m CONFIG_HWSPINLOCK_LIGHT_TEST=m
CONFIG_MAILBOX=y CONFIG_MAILBOX=y
CONFIG_RPMSG=y
CONFIG_RPMSG_CHAR=y
CONFIG_RPMSG_VIRTIO=y
CONFIG_RPMSG_THEAD_LIGHT=y
CONFIG_EXTCON=y
CONFIG_IIO=y CONFIG_IIO=y
CONFIG_IIO_SW_DEVICE=y CONFIG_IIO_SW_DEVICE=y
CONFIG_PWM=y CONFIG_PWM=y
CONFIG_PWM_LIGHT=y CONFIG_PWM_LIGHT=y
CONFIG_NVMEM_THEAD_LIGHT_EFUSE=y CONFIG_NVMEM_THEAD_LIGHT_EFUSE=y
CONFIG_TEE=y CONFIG_TEE=m
CONFIG_OPTEE=y CONFIG_OPTEE=m
CONFIG_OPTEE_BENCHMARK=y CONFIG_OPTEE_BENCHMARK=y
CONFIG_LIGHT_GPU_VIV=m CONFIG_LIGHT_GPU_VIV=m
# CONFIG_LIGHT_NET is not set # CONFIG_LIGHT_NET is not set
@@ -295,13 +311,21 @@ CONFIG_CRYPTO_AUTHENC=y
CONFIG_CRYPTO_DH=y CONFIG_CRYPTO_DH=y
CONFIG_CRYPTO_CURVE25519=y CONFIG_CRYPTO_CURVE25519=y
CONFIG_CRYPTO_CHACHA20POLY1305=y CONFIG_CRYPTO_CHACHA20POLY1305=y
CONFIG_CRYPTO_CBC=y
CONFIG_CRYPTO_CTR=y
CONFIG_CRYPTO_OFB=y CONFIG_CRYPTO_OFB=y
CONFIG_CRYPTO_MD5=y CONFIG_CRYPTO_MD5=y
CONFIG_CRYPTO_SHA512=y CONFIG_CRYPTO_SHA512=y
CONFIG_CRYPTO_SHA3=y CONFIG_CRYPTO_SHA3=y
CONFIG_CRYPTO_SM3=y CONFIG_CRYPTO_SM3=y
CONFIG_CRYPTO_DES=y CONFIG_CRYPTO_DES=y
CONFIG_CRYPTO_SM4=y
CONFIG_CRYPTO_USER=y
CONFIG_CRYPTO_USER_API_HASH=y CONFIG_CRYPTO_USER_API_HASH=y
CONFIG_CRYPTO_USER_API_SKCIPHER=y
CONFIG_CRYPTO_USER_API_RNG=y
# CONFIG_CRYPTO_USER_API_RNG_CAVP is not set
CONFIG_CRYPTO_USER_API_AEAD=y
CONFIG_DMA_CMA=y CONFIG_DMA_CMA=y
CONFIG_DMA_PERNUMA_CMA=y CONFIG_DMA_PERNUMA_CMA=y
CONFIG_CMA_SIZE_MBYTES=32 CONFIG_CMA_SIZE_MBYTES=32
@@ -311,7 +335,26 @@ CONFIG_DEBUG_INFO=y
CONFIG_MAGIC_SYSRQ=y CONFIG_MAGIC_SYSRQ=y
CONFIG_DEBUG_FS=y CONFIG_DEBUG_FS=y
CONFIG_DETECT_HUNG_TASK=y CONFIG_DETECT_HUNG_TASK=y
CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=60
CONFIG_DEBUG_ATOMIC_SLEEP=y CONFIG_DEBUG_ATOMIC_SLEEP=y
# CONFIG_RCU_TRACE is not set # CONFIG_RCU_TRACE is not set
CONFIG_OVERLAY_FS=y CONFIG_OVERLAY_FS=y
CONFIG_LOCKUP_DETECTOR=y
CONFIG_SOFTLOCKUP_DETECTOR=y
CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
CONFIG_SCHED_INFO=y
CONFIG_PM=y
# CONFIG_SUSPEND is not set
# CONFIG_PM_SLEEP is not set
CONFIG_PM_DEVFREQ=y
CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y
CONFIG_DEVFREQ_GOV_PERFORMANCE=y
CONFIG_DEVFREQ_GOV_POWERSAVE=y
CONFIG_DEVFREQ_GOV_USERSPACE=y
CONFIG_DEVFREQ_GOV_PASSIVE=y
CONFIG_PM_DEVFREQ_EVENT=y
CONFIG_ENERGY_MODEL=y
# CONFIG_THERMAL_DEFAULT_GOV_POWER_ALLOCATOR is not set
CONFIG_THERMAL_GOV_POWER_ALLOCATOR=y
CONFIG_DEVFREQ_THERMAL=y
CONFIG_THERMAL_STATISTICS=y

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