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base: t-head:Linux_SDK_V1.0.3
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t-head:lpi4a t-head:huiwei t-head:thead-sdk t-head:fix-toolchains t-head:merged-ahead t-head:update/1.4.2/gpu/dvfs t-head:ahead-new t-head:ov5693 t-head:develop t-head:master
t-head:Linux_SDK_V1.4.2 t-head:Linux_SDK_V1.3.3 t-head:Linux_SDK_V1.2.1 t-head:Linux_SDK_V1.2.0 t-head:Linux_SDK_V1.1.2 t-head:Linux_SDK_V1.0.3 t-head:Linux_SDK_V1.0.2 t-head:Linux_SDK_V0.9.5
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compare: t-head:Linux_SDK_V1.3.3
Branches Tags
t-head:lpi4a t-head:huiwei t-head:thead-sdk t-head:fix-toolchains t-head:merged-ahead t-head:update/1.4.2/gpu/dvfs t-head:ahead-new t-head:ov5693 t-head:develop t-head:master
t-head:Linux_SDK_V1.4.2 t-head:Linux_SDK_V1.3.3 t-head:Linux_SDK_V1.2.1 t-head:Linux_SDK_V1.2.0 t-head:Linux_SDK_V1.1.2 t-head:Linux_SDK_V1.0.3 t-head:Linux_SDK_V1.0.2 t-head:Linux_SDK_V0.9.5

6 Commits
Linux_SDK_ ... Linux_SDK_

Author SHA1 Message Date
thead_admin
c20ad6292d Linux_SDK_V1.3.3 
Signed-off-by: thead_admin <occ_thead@service.alibaba.com>
 2023-12-24 19:36:38 +08:00
thead_admin
f4327ba402 Linux_SDK_V1.2.1 
Signed-off-by: thead_admin <occ_thead@service.alibaba.com>
 2023-08-19 00:37:34 +08:00
jianghai
599b048690 eth: gmac: adapt to support DMA 32-bit in skb 2023-07-30 04:42:32 +08:00
thead_admin
b269dc8fa7 apply lpi4a patches 2023-07-30 04:42:27 +08:00
Han Gao
87e5c31f94 Linux_SDK_V1.2.0 2023-07-30 04:39:12 +08:00
thead_admin
ada47f394b Linux_SDK_V1.1.2 2023-03-05 22:36:24 +08:00
225 changed files with 19724 additions and 3748 deletions
Expand all files Collapse all files

2
Documentation/devicetree/bindings/arm/msm/qcom,idle-state.txt
View File

@@ -81,4 +81,4 @@ Example:
};
};
[1]. Documentation/devicetree/bindings/arm/idle-states.yaml
[1]. Documentation/devicetree/bindings/cpu/idle-states.yaml

2
Documentation/devicetree/bindings/arm/psci.yaml
View File

@@ -101,7 +101,7 @@ properties:
bindings in [1]) must specify this property.
[1] Kernel documentation - ARM idle states bindings
Documentation/devicetree/bindings/arm/idle-states.yaml
Documentation/devicetree/bindings/cpu/idle-states.yaml
patternProperties:
"^power-domain-":

228
Documentation/devicetree/bindings/arm/idle-states.yaml → Documentation/devicetree/bindings/cpu/idle-states.yaml
View File

@@ -1,25 +1,30 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/idle-states.yaml#
$id: http://devicetree.org/schemas/cpu/idle-states.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: ARM idle states binding description
title: Idle states binding description
maintainers:
- Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
- Anup Patel <anup@brainfault.org>
description: |+
==========================================
1 - Introduction
==========================================
ARM systems contain HW capable of managing power consumption dynamically,
where cores can be put in different low-power states (ranging from simple wfi
to power gating) according to OS PM policies. The CPU states representing the
range of dynamic idle states that a processor can enter at run-time, can be
specified through device tree bindings representing the parameters required to
enter/exit specific idle states on a given processor.
ARM and RISC-V systems contain HW capable of managing power consumption
dynamically, where cores can be put in different low-power states (ranging
from simple wfi to power gating) according to OS PM policies. The CPU states
representing the range of dynamic idle states that a processor can enter at
run-time, can be specified through device tree bindings representing the
parameters required to enter/exit specific idle states on a given processor.
==========================================
2 - ARM idle states
==========================================
According to the Server Base System Architecture document (SBSA, [3]), the
power states an ARM CPU can be put into are identified by the following list:
@@ -43,8 +48,23 @@ description: |+
The device tree binding definition for ARM idle states is the subject of this
document.
==========================================
3 - RISC-V idle states
==========================================
On RISC-V systems, the HARTs (or CPUs) [6] can be put in platform specific
suspend (or idle) states (ranging from simple WFI, power gating, etc). The
RISC-V SBI v0.3 (or higher) [7] hart state management extension provides a
standard mechanism for OS to request HART state transitions.
The platform specific suspend (or idle) states of a hart can be either
retentive or non-rententive in nature. A retentive suspend state will
preserve HART registers and CSR values for all privilege modes whereas
a non-retentive suspend state will not preserve HART registers and CSR
values.
===========================================
2 - idle-states definitions
4 - idle-states definitions
===========================================
Idle states are characterized for a specific system through a set of
@@ -211,10 +231,10 @@ description: |+
properties specification that is the subject of the following sections.
===========================================
3 - idle-states node
5 - idle-states node
===========================================
ARM processor idle states are defined within the idle-states node, which is
The processor idle states are defined within the idle-states node, which is
a direct child of the cpus node [1] and provides a container where the
processor idle states, defined as device tree nodes, are listed.
@@ -223,7 +243,7 @@ description: |+
just supports idle_standby, an idle-states node is not required.
===========================================
4 - References
6 - References
===========================================
[1] ARM Linux Kernel documentation - CPUs bindings
@@ -238,9 +258,15 @@ description: |+
[4] ARM Architecture Reference Manuals
http://infocenter.arm.com/help/index.jsp
[6] ARM Linux Kernel documentation - Booting AArch64 Linux
[5] ARM Linux Kernel documentation - Booting AArch64 Linux
Documentation/arm64/booting.rst
[6] RISC-V Linux Kernel documentation - CPUs bindings
Documentation/devicetree/bindings/riscv/cpus.yaml
[7] RISC-V Supervisor Binary Interface (SBI)
http://github.com/riscv/riscv-sbi-doc/riscv-sbi.adoc
properties:
$nodename:
const: idle-states
@@ -253,7 +279,7 @@ properties:
On ARM 32-bit systems this property is optional
This assumes that the "enable-method" property is set to "psci" in the cpu
node[6] that is responsible for setting up CPU idle management in the OS
node[5] that is responsible for setting up CPU idle management in the OS
implementation.
const: psci
@@ -265,8 +291,8 @@ patternProperties:
as follows.
The idle state entered by executing the wfi instruction (idle_standby
SBSA,[3][4]) is considered standard on all ARM platforms and therefore
must not be listed.
SBSA,[3][4]) is considered standard on all ARM and RISC-V platforms and
therefore must not be listed.
In addition to the properties listed above, a state node may require
additional properties specific to the entry-method defined in the
@@ -275,7 +301,27 @@ patternProperties:
properties:
compatible:
const: arm,idle-state
enum:
- arm,idle-state
- riscv,idle-state
arm,psci-suspend-param:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
power_state parameter to pass to the ARM PSCI suspend call.
Device tree nodes that require usage of PSCI CPU_SUSPEND function
(i.e. idle states node with entry-method property is set to "psci")
must specify this property.
riscv,sbi-suspend-param:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
suspend_type parameter to pass to the RISC-V SBI HSM suspend call.
This property is required in idle state nodes of device tree meant
for RISC-V systems. For more details on the suspend_type parameter
refer the SBI specifiation v0.3 (or higher) [7].
local-timer-stop:
description:
@@ -317,6 +363,8 @@ patternProperties:
description:
A string used as a descriptive name for the idle state.
additionalProperties: false
required:
- compatible
- entry-latency-us
@@ -658,4 +706,150 @@ examples:
};
};
- |
// Example 3 (RISC-V 64-bit, 4-cpu systems, two clusters):
cpus {
#size-cells = <0>;
#address-cells = <1>;
cpu@0 {
device_type = "cpu";
compatible = "riscv";
reg = <0x0>;
riscv,isa = "rv64imafdc";
mmu-type = "riscv,sv48";
cpu-idle-states = <&CPU_RET_0_0 &CPU_NONRET_0_0
&CLUSTER_RET_0 &CLUSTER_NONRET_0>;
cpu_intc0: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
interrupt-controller;
};
};
cpu@1 {
device_type = "cpu";
compatible = "riscv";
reg = <0x1>;
riscv,isa = "rv64imafdc";
mmu-type = "riscv,sv48";
cpu-idle-states = <&CPU_RET_0_0 &CPU_NONRET_0_0
&CLUSTER_RET_0 &CLUSTER_NONRET_0>;
cpu_intc1: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
interrupt-controller;
};
};
cpu@10 {
device_type = "cpu";
compatible = "riscv";
reg = <0x10>;
riscv,isa = "rv64imafdc";
mmu-type = "riscv,sv48";
cpu-idle-states = <&CPU_RET_1_0 &CPU_NONRET_1_0
&CLUSTER_RET_1 &CLUSTER_NONRET_1>;
cpu_intc10: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
interrupt-controller;
};
};
cpu@11 {
device_type = "cpu";
compatible = "riscv";
reg = <0x11>;
riscv,isa = "rv64imafdc";
mmu-type = "riscv,sv48";
cpu-idle-states = <&CPU_RET_1_0 &CPU_NONRET_1_0
&CLUSTER_RET_1 &CLUSTER_NONRET_1>;
cpu_intc11: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
interrupt-controller;
};
};
idle-states {
CPU_RET_0_0: cpu-retentive-0-0 {
compatible = "riscv,idle-state";
riscv,sbi-suspend-param = <0x10000000>;
entry-latency-us = <20>;
exit-latency-us = <40>;
min-residency-us = <80>;
};
CPU_NONRET_0_0: cpu-nonretentive-0-0 {
compatible = "riscv,idle-state";
riscv,sbi-suspend-param = <0x90000000>;
entry-latency-us = <250>;
exit-latency-us = <500>;
min-residency-us = <950>;
};
CLUSTER_RET_0: cluster-retentive-0 {
compatible = "riscv,idle-state";
riscv,sbi-suspend-param = <0x11000000>;
local-timer-stop;
entry-latency-us = <50>;
exit-latency-us = <100>;
min-residency-us = <250>;
wakeup-latency-us = <130>;
};
CLUSTER_NONRET_0: cluster-nonretentive-0 {
compatible = "riscv,idle-state";
riscv,sbi-suspend-param = <0x91000000>;
local-timer-stop;
entry-latency-us = <600>;
exit-latency-us = <1100>;
min-residency-us = <2700>;
wakeup-latency-us = <1500>;
};
CPU_RET_1_0: cpu-retentive-1-0 {
compatible = "riscv,idle-state";
riscv,sbi-suspend-param = <0x10000010>;
entry-latency-us = <20>;
exit-latency-us = <40>;
min-residency-us = <80>;
};
CPU_NONRET_1_0: cpu-nonretentive-1-0 {
compatible = "riscv,idle-state";
riscv,sbi-suspend-param = <0x90000010>;
entry-latency-us = <250>;
exit-latency-us = <500>;
min-residency-us = <950>;
};
CLUSTER_RET_1: cluster-retentive-1 {
compatible = "riscv,idle-state";
riscv,sbi-suspend-param = <0x11000010>;
local-timer-stop;
entry-latency-us = <50>;
exit-latency-us = <100>;
min-residency-us = <250>;
wakeup-latency-us = <130>;
};
CLUSTER_NONRET_1: cluster-nonretentive-1 {
compatible = "riscv,idle-state";
riscv,sbi-suspend-param = <0x91000010>;
local-timer-stop;
entry-latency-us = <600>;
exit-latency-us = <1100>;
min-residency-us = <2700>;
wakeup-latency-us = <1500>;
};
};
};
...

6
Documentation/devicetree/bindings/riscv/cpus.yaml
View File

@@ -87,6 +87,12 @@ properties:
- compatible
- interrupt-controller
cpu-idle-states:
$ref: '/schemas/types.yaml#/definitions/phandle-array'
description: |
List of phandles to idle state nodes supported
by this hart (see ./idle-states.yaml).
required:
- riscv,isa
- interrupt-controller

14
MAINTAINERS
View File

@@ -4614,6 +4614,20 @@ S: Supported
F: drivers/cpuidle/cpuidle-psci.h
F: drivers/cpuidle/cpuidle-psci-domain.c
CPUIDLE DRIVER - DT IDLE PM DOMAIN
M: Ulf Hansson <ulf.hansson@linaro.org>
L: linux-pm@vger.kernel.org
S: Supported
F: drivers/cpuidle/dt_idle_genpd.c
F: drivers/cpuidle/dt_idle_genpd.h
CPUIDLE DRIVER - RISC-V SBI
M: Anup Patel <anup@brainfault.org>
L: linux-pm@vger.kernel.org
L: linux-riscv@lists.infradead.org
S: Maintained
F: drivers/cpuidle/cpuidle-riscv-sbi.c
CRAMFS FILESYSTEM
M: Nicolas Pitre <nico@fluxnic.net>
S: Maintained

11
arch/riscv/Kconfig
View File

@@ -21,7 +21,6 @@ config RISCV
select ARCH_HAS_GCOV_PROFILE_ALL
select ARCH_HAS_GIGANTIC_PAGE
select ARCH_HAS_KCOV
select ARCH_HAS_MMIOWB
select ARCH_HAS_PTE_SPECIAL
select ARCH_HAS_SET_DIRECT_MAP
select ARCH_HAS_SET_MEMORY
@@ -32,8 +31,10 @@ config RISCV
select ARCH_HAS_SYNC_DMA_FOR_DEVICE
select ARCH_HAS_DMA_WRITE_COMBINE
select ARCH_HAS_DMA_MMAP_PGPROT
select ARCH_KEEP_MEMBLOCK
select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX
select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT
select ARCH_USE_QUEUED_SPINLOCKS
select ARCH_USE_QUEUED_RWLOCKS
select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU
select ARCH_WANT_FRAME_POINTERS
@@ -41,7 +42,7 @@ config RISCV
select CLONE_BACKWARDS
select CLINT_TIMER if !MMU
select COMMON_CLK
select CPU_PM if (SUSPEND || CPU_IDLE)
select CPU_PM if CPU_IDLE
select COMPAT_BINFMT_ELF if BINFMT_ELF && COMPAT
select EDAC_SUPPORT
select DMA_DIRECT_REMAP
@@ -574,5 +575,11 @@ config ARCH_SUSPEND_POSSIBLE
endmenu
menu "CPU Power Management"
source "drivers/cpuidle/Kconfig"
endmenu
source "arch/riscv/kvm/Kconfig"
source "drivers/firmware/Kconfig"

3
arch/riscv/Kconfig.socs
View File

@@ -19,6 +19,9 @@ config SOC_VIRT
select GOLDFISH
select RTC_DRV_GOLDFISH if RTC_CLASS
select SIFIVE_PLIC
select PM_GENERIC_DOMAINS if PM
select PM_GENERIC_DOMAINS_OF if PM && OF
select RISCV_SBI_CPUIDLE if CPU_IDLE
help
This enables support for QEMU Virt Machine.

15
arch/riscv/boot/dts/thead/Makefile
View File

@@ -4,7 +4,7 @@ dtb-$(CONFIG_SOC_THEAD) += light-fm-emu.dtb light_mpw.dtb
dtb-$(CONFIG_SOC_THEAD) += light-fm-emu-npu-fce.dtb
dtb-$(CONFIG_SOC_THEAD) += light-fm-emu-gpu.dtb
dtb-$(CONFIG_SOC_THEAD) += light-fm-emu-dsp.dtb
dtb-$(CONFIG_SOC_THEAD) += light-fm-emu-audio.dtb
dtb-$(CONFIG_SOC_THEAD) += light-fm-emu-audio.dtb light-a-val-audio-hdmi.dtb
dtb-$(CONFIG_SOC_THEAD) += light-fm-emu-hdmi.dtb
dtb-$(CONFIG_SOC_THEAD) += light-fm-emu-dsi0-hdmi.dtb
dtb-$(CONFIG_SOC_THEAD) += light-a-val.dtb light-a-val-sv.dtb
@@ -12,26 +12,31 @@ dtb-$(CONFIG_SOC_THEAD) += light-a-val-ddr2G.dtb light-a-val-ddr1G.dtb
dtb-$(CONFIG_SOC_THEAD) += light-a-val-npu-fce.dtb
dtb-$(CONFIG_SOC_THEAD) += light-a-val-iso7816.dtb
dtb-$(CONFIG_SOC_THEAD) += light-a-val-nand.dtb
dtb-$(CONFIG_SOC_THEAD) += light-a-val-audio.dtb
dtb-$(CONFIG_SOC_THEAD) += light-a-val-dsi0.dtb light-a-val-dsi1.dtb light-a-val-hdmi.dtb light-a-val-dsi0-dsi1.dtb light-a-val-dsi0-hdmi.dtb light-a-val-dpi0.dtb light-a-val-dpi0-dpi1.dtb
dtb-$(CONFIG_SOC_THEAD) += light-a-val-audio.dtb light-a-val-audio-i2s-8ch.dtb
dtb-$(CONFIG_SOC_THEAD) += light-a-val-audio-tdm.dtb
dtb-$(CONFIG_SOC_THEAD) += light-a-val-audio-spdif.dtb
dtb-$(CONFIG_SOC_THEAD) += light-a-val-dsi0.dtb light-a-val-dsi1.dtb light-a-val-hdmi.dtb light-a-val-dsi0-dsi1.dtb light-a-val-dsi0-hdmi.dtb light-a-val-dsi0-hdmi-audio.dtb light-a-val-dpi0.dtb light-a-val-dpi0-dpi1.dtb
dtb-$(CONFIG_SOC_THEAD) += light-a-val-wcn.dtb
dtb-$(CONFIG_SOC_THEAD) += light-a-val-gpio-keys.dtb
dtb-$(CONFIG_SOC_THEAD) += light-a-val-khv.dtb
dtb-$(CONFIG_SOC_THEAD) += light-a-val-sec.dtb
dtb-$(CONFIG_SOC_THEAD) += light-a-val-miniapp-hdmi.dtb
dtb-$(CONFIG_SOC_THEAD) += light-a-product.dtb
dtb-$(CONFIG_SOC_THEAD) += light-b-product.dtb
dtb-$(CONFIG_SOC_THEAD) += light-b-product.dtb light-b-product-sec.dtb
dtb-$(CONFIG_SOC_THEAD) += light-b-product-ddr1G.dtb
dtb-$(CONFIG_SOC_THEAD) += light-b-product-miniapp-hdmi.dtb
dtb-$(CONFIG_SOC_THEAD) += light-a-val-full.dtb
dtb-$(CONFIG_SOC_THEAD) += light-ant-ref.dtb
dtb-$(CONFIG_SOC_THEAD) += light-ant-discrete.dtb
dtb-$(CONFIG_SOC_THEAD) += light-beagle.dtb
dtb-$(CONFIG_SOC_THEAD) += light-lpi4a.dtb light-lpi4a-ddr2G.dtb
dtb-$(CONFIG_SOC_THEAD) += light-a-ref.dtb light-a-ref-dsi0.dtb light-a-ref-dsi0-hdmi.dtb
dtb-$(CONFIG_SOC_THEAD) += light-b-ref.dtb
dtb-$(CONFIG_SOC_THEAD) += light-a-val-crash.dtb light-b-product-crash.dtb light-ant-ref-crash.dtb light-ant-discrete-crash.dtb
dtb-$(CONFIG_SOC_THEAD) += light-a-val-crash.dtb light-b-product-crash.dtb light-ant-ref-crash.dtb light-ant-discrete-crash.dtb light-lpi4a-crash.dtb light-lpi4a-camera-tuning.dtb light-lpi4a-hdmi.dtb
dtb-$(CONFIG_SOC_THEAD) += light-b-power.dtb
dtb-$(CONFIG_SOC_THEAD) += light-a-val-android.dtb
dtb-$(CONFIG_SOC_THEAD) += fire-emu.dtb fire-emu-crash.dtb
dtb-$(CONFIG_SOC_THEAD) += fire-emu-soc-base.dtb fire-emu-soc-c910x4.dtb fire-emu-gpu-dpu-dsi0.dtb fire-emu-vi-dsp-vo.dtb fire-emu-vi-vp-vo.dtb
dtb-$(CONFIG_SOC_THEAD) += fire-emu-soc-base-sec.dtb

288
arch/riscv/boot/dts/thead/fire-crash.dts
View File

@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2021 Alibaba Group Holding Limited.
* Copyright (C) 2021-2022 Alibaba Group Holding Limited.
*/
/dts-v1/;
@@ -9,8 +9,9 @@
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/gpio/gpio.h>
#include "light-vi-devices.dtsi"
/ {
model = "T-HEAD Fire emu board";
model = "T-HEAD fire fpga board";
compatible = "thead,fire-emu", "thead,fire";
chosen {
@@ -120,10 +121,6 @@
is_default_region;
};
iopmp_fce: IOPMP_FCE {
is_default_region;
};
iopmp0_dpu: IOPMP0_DPU {
bypass_en;
};
@@ -192,23 +189,6 @@
status = "okay";
};
reg_vref_1v8: regulator-adc-verf {
compatible = "regulator-fixed";
regulator-name = "vref-1v8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
status = "okay";
};
reg_tp_pwr_en: regulator-pwr-en {
compatible = "regulator-fixed";
regulator-name = "PWR_EN";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
gpio = <&gpio1_porta 12 1>;
enable-active-high;
regulator-always-on;
};
wcn_wifi: wireless-wlan {
compatible = "wlan-platdata";
@@ -217,33 +197,33 @@
keep_wifi_power_on;
pinctrl-names = "default";
wifi_chip_type = "rtl8723ds";
WIFI,poweren_gpio = <&gpio2_porta 29 0>;
WIFI,reset_n = <&gpio2_porta 24 0>;
status = "okay";
WIFI,poweren_gpio = <&gpio2_porta 26 0>;
WIFI,reset_n = <&gpio2_porta 28 0>;
status = "disabled";
};
wcn_bt: wireless-bluetooth {
compatible = "bluetooth-platdata";
pinctrl-names = "default", "rts_gpio";
BT,power_gpio = <&gpio2_porta 25 0>;
status = "okay";
BT,power_gpio = <&gpio2_porta 29 0>;
status = "disabled";
};
gpio-keys {
gpio_keys: gpio_keys{
compatible = "gpio-keys";
pinctrl-0 = <&pinctrl_volume>;
pinctrl-names = "default";
status = "disabled";
key-volumedown {
label = "Volume Down Key";
linux,code = <KEY_VOLUMEDOWN>;
debounce-interval = <1>;
gpios = <&ao_gpio_porta 11 0x1>;
linux,code = <KEY_1>;
debounce-interval = <2>;
gpios = <&ao_gpio_porta 4 GPIO_ACTIVE_LOW>;
};
key-volumeup {
label = "Volume Up Key";
linux,code = <KEY_VOLUMEUP>;
debounce-interval = <1>;
gpios = <&ao_gpio_porta 10 0x1>;
linux,code = <KEY_2>;
debounce-interval = <2>;
gpios = <&ao_gpio_porta 5 GPIO_ACTIVE_LOW>;
};
};
@@ -251,20 +231,27 @@
compatible = "thead,light-aon";
mbox-names = "aon";
mboxes = <&mbox_910t 1 0>;
status = "okay";
status = "disabled";
pd: light-aon-pd {
compatible = "thead,light-aon-pd";
#power-domain-cells = <1>;
status = "disabled";
};
aon_reg_dialog: light-dialog-reg {
compatible = "thead,light-dialog-pmic";
status = "disabled";
};
c910_cpufreq {
compatible = "thead,light-mpw-cpufreq";
status = "okay";
status = "disabled";
};
test: light-aon-test {
compatible = "thead,light-aon-test";
status = "disabled";
};
};
};
@@ -278,60 +265,64 @@
reg = <0x0 0x1a000000 0 0x4000000>;
no-map;
};
dsp0_mem: memory@20000000 { /**0x2000_0000~0x2040_0000 4M**/
reg = <0x0 0x20000000 0x0 0x00280000 /* DSP FW code&data section 2.5M*/
0x0 0x20280000 0x0 0x00001000 /* DSP communication area 4K*/
0x0 0x20281000 0x0 0x00007000 /* Panic/log page 28K */
0x0 0x20288000 0x0 0x00178000>; /* DSP shared memory 1.5M-32K*/
no-map;
};
dsp1_mem: memory@20400000 { /**0x2040_0000~0x2080_0000 4M**/
reg = <0x0 0x20400000 0x0 0x00280000 /* DSP FW code&data section */
0x0 0x20680000 0x0 0x00001000 /* DSP communication area */
0x0 0x20681000 0x0 0x00007000 /* Panic/log page*/
0x0 0x20688000 0x0 0x00178000>; /* DSP shared memory */
no-map;
};
vi_mem: framebuffer@0f800000 {
reg = <0x0 0x0F800000 0x0 0x05400000 /* vi_mem_pool_region[0] 84 MB (default) */
0x0 0x14C00000 0x0 0x01D00000 /* vi_mem_pool_region[1] 29 MB */
0x0 0x16900000 0x0 0x03200000>; /* vi_mem_pool_region[2] 50 MB */
no-map;
};
facelib_mem: memory@22000000 {
reg = <0x0 0x22000000 0x0 0x10000000>;
no-map;
};
dsp0_mem: memory@20000000 { /**0x2000_0000~0x2040_0000 4M**/
reg = <0x0 0x20000000 0x0 0x00280000 /* DSP FW code&data section 2.5M*/
0x0 0x20280000 0x0 0x00001000 /* DSP communication area 4K*/
0x0 0x20281000 0x0 0x00007000 /* Panic/log page 28K */
0x0 0x20288000 0x0 0x00178000>; /* DSP shared memory 1.5M-32K*/
no-map;
};
dsp1_mem: memory@20400000 { /**0x2040_0000~0x2080_0000 4M**/
reg = <0x0 0x20400000 0x0 0x00280000 /* DSP FW code&data section */
0x0 0x20680000 0x0 0x00001000 /* DSP communication area */
0x0 0x20681000 0x0 0x00007000 /* Panic/log page*/
0x0 0x20688000 0x0 0x00178000>; /* DSP shared memory */
no-map;
};
vi_mem: framebuffer@10000000 {
reg = <0x0 0x10000000 0x0 0x02C00000 /* vi_mem_pool_region[0] 44 MB (default) */
0x0 0x12C00000 0x0 0x01D00000 /* vi_mem_pool_region[1] 29 MB */
0x0 0x14900000 0x0 0x01E00000>; /* vi_mem_pool_region[2] 30 MB */
no-map;
};
facelib_mem: memory@17000000 {
reg = <0x0 0x17000000 0 0x02000000>;
no-map;
};
};
&adc {
vref-supply = <&reg_vref_1v8>;
status = "okay";
&clk {
status = "disabled";
};
&i2c0 {
clock-frequency = <100000>;
clock-frequency = <400000>;
status = "okay";
eeprom@50 {
compatible = "atmel,24c32";
reg = <0x50>;
pagesize = <32>;
};
touch@5d {
#gpio-cells = <2>;
compatible = "goodix,gt911";
status = "disabled";
reg = <0x5d>;
interrupt-parent = <&gpio1_porta>;
interrupts = <8 0>;
irq-gpios = <&gpio1_porta 8 0>;
reset-gpios = <&gpio1_porta 7 0>;
AVDD28-supply = <&reg_tp_pwr_en>;
touchscreen-size-x = <720>;
touchscreen-size-x = <800>;
touchscreen-size-y = <1280>;
};
};
&audio_i2c0 {
clock-frequency = <100000>;
status = "okay";
status = "disabled";
es8156_audio_codec: es8156@8 {
#sound-dai-cells = <0>;
@@ -344,25 +335,29 @@
compatible = "MicArray_0";
reg = <0x40>;
};
audio_aw87519_pa@58 {
compatible = "awinic,aw87519_pa";
reg = <0x58>;
reset-gpio = <&ao_gpio4_porta 9 0x1>;
status = "okay";
};
};
&i2c1 {
clock-frequency = <100000>;
status = "okay";
clock-frequency = <400000>;
status = "disabled";
touch1@5d {
#gpio-cells = <2>;
compatible = "goodix,gt911";
reg = <0x5d>;
interrupt-parent = <&gpio1_porta>;
interrupts = <12 0>;
irq-gpios = <&gpio1_porta 12 0>;
reset-gpios = <&gpio1_porta 11 0>;
touchscreen-size-x = <800>;
touchscreen-size-y = <1280>;
};
};
&spi0 {
num-cs = <1>;
cs-gpios = <&gpio2_porta 15 0>; // GPIO_ACTIVE_HIGH: 0
rx-sample-delay-ns = <10>;
status = "disabled";
status = "okay";
spi_norflash@0 {
#address-cells = <1>;
@@ -371,6 +366,7 @@
reg = <0>;
spi-max-frequency = <50000000>;
w25q,fast-read;
status = "disabled";
};
spidev@1 {
@@ -382,12 +378,6 @@
};
};
&uart0 {
clocks = <&dummy_clock_uart_sclk>;
clock-names = "baudclk";
clock-frequency = <100000000>;
};
&qspi0 {
num-cs = <1>;
cs-gpios = <&gpio2_porta 3 0>;
@@ -411,17 +401,23 @@
};
&qspi1 {
compatible = "snps,dw-apb-ssi";
num-cs = <1>;
cs-gpios = <&gpio0_porta 1 0>;
status = "disabled";
spidev@0 {
compatible = "spidev";
#address-cells = <0x1>;
#size-cells = <0x1>;
reg = <0x0>;
spi-max-frequency = <50000000>;
spi-flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spi-nand";
spi-max-frequency = <66000000>;
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
reg = <0>;
partition@0 {
label = "ubi2";
reg = <0x00000000 0x08000000>;
};
};
};
@@ -447,14 +443,6 @@
};
};
&gmac1 {
phy-mode = "rgmii-id";
rx-clk-delay = <0x00>; /* for RGMII */
tx-clk-delay = <0x00>; /* for RGMII */
phy-handle = <&phy_88E1111_1>;
status = "okay";
};
&emmc {
max-frequency = <198000000>;
non-removable;
@@ -489,7 +477,7 @@
cap-sd-highspeed;
keep-power-in-suspend;
wakeup-source;
status = "okay";
status = "disabled";
};
&padctrl0_apsys { /* right-pinctrl */
@@ -526,7 +514,7 @@
>;
};
pinctrl_audio_i2s0: i2s0grp {
pinctrl_light_i2s0: i2s0grp {
thead,pins = <
FM_QSPI0_SCLK 0x2 0x208
FM_QSPI0_CSN0 0x2 0x238
@@ -541,6 +529,7 @@
pinctrl_pwm: pwmgrp {
thead,pins = <
FM_GPIO3_2 0x1 0x208 /* pwm0 */
FM_GPIO3_3 0x1 0x208 /* pwm1 */
>;
};
};
@@ -593,57 +582,41 @@
};
};
&padctrl_aosys {
light-aon-padctrl {
/*
* Pin Configuration Node:
* Format: <pin_id mux_node config>
*/
pinctrl_audiopa1: audiopa1_grp {
thead,pins = <
FM_AUDIO_PA1 0x3 0x72
>;
};
pinctrl_audiopa2: audiopa2_grp {
thead,pins = <
FM_AUDIO_PA2 0x0 0x72
>;
};
pinctrl_volume: volume_grp {
thead,pins = <
FM_AOGPIO_11 0x0 0x208
FM_AOGPIO_10 0x3 0x208
>;
};
&i2c2 {
clock-frequency = <400000>;
status = "okay";
eeprom@50 {
compatible = "atmel,24c32";
reg = <0x50>;
pagesize = <32>;
};
};
&i2c0 {
clock-frequency = <400000>;
status = "okay";
};
&i2c1 {
clock-frequency = <400000>;
status = "okay";
};
&i2c2 {
clock-frequency = <400000>;
status = "okay";
};
&i2c3 {
clock-frequency = <400000>;
clock-frequency = <400000>;
status = "okay";
eeprom@50 {
compatible = "atmel,24c32";
reg = <0x50>;
pagesize = <32>;
};
};
&i2c4 {
clock-frequency = <400000>;
clock-frequency = <400000>;
status = "okay";
eeprom@50 {
compatible = "atmel,24c32";
reg = <0x50>;
pagesize = <32>;
};
pcal6408ahk_a: gpio@20 {
compatible = "nxp,pcal9554b";
reg = <0x20>;
gpio-controller;
#gpio-cells = <2>;
};
};
&isp0 {
@@ -691,6 +664,7 @@
};
&vi_pre {
//vi_pre_irq_en = <1>;
status = "disabled";
};
@@ -700,18 +674,20 @@
&xtensa_dsp0 {
status = "disabled";
memory-region = <&dsp0_mem>;
};
&xtensa_dsp1 {
status = "disabled";
&xtensa_dsp1{
status = "disabled";
memory-region = <&dsp1_mem>;
};
&vvcam_flash_led0{
status = "disabled";
};
&vvcam_sensor0 {
flash_led_name = "aw36413_aw36515";
floodlight_i2c_bus = /bits/ 8 <2>;
floodlight_en_pin = <&gpio1_porta 25 0>;
//projection_i2c_bus = /bits/ 8 <2>;
flash_led_touch_pin = <&gpio1_porta 27 0>; //flash led touch pin
status = "disabled";
};
@@ -851,19 +827,19 @@
};
&light_i2s {
status = "okay";
status = "disabled";
};
&i2s0 {
status = "okay";
status = "disabled";
};
&i2s1 {
status = "okay";
status = "disabled";
};
&i2s3 {
status = "okay";
status = "disabled";
};
&khvhost {

2
arch/riscv/boot/dts/thead/fire-emu-crash.dts
View File

@@ -8,7 +8,7 @@
&aon {
aon_reg_dialog: light-dialog-reg {
compatible = "thead,light-dialog-pmic";
status = "okay";
status = "disabled";
dvdd_cpu_reg: appcpu_dvdd {
regulator-name = "appcpu_dvdd";

107
arch/riscv/boot/dts/thead/fire-emu-gpu-dpu-dsi0.dts Normal file
View File

@@ -0,0 +1,107 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2021-2022 Alibaba Group Holding Limited.
*/
/dts-v1/;
#include "fire-emu.dts"
&gpu {
status = "okay";
};
&vosys_reg {
status = "okay";
};
&display_subsystem {
status = "okay";
};
&dpu_enc0 {
status = "okay";
ports {
/* output */
port@1 {
reg = <1>;
enc0_out: endpoint {
remote-endpoint = <&dsi0_in>;
};
};
};
};
&dpu {
status = "okay";
};
&dsi0 {
status = "okay";
};
&dhost_0 {
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dsi0_in: endpoint {
remote-endpoint = <&enc0_out>;
};
};
port@1 {
reg = <1>;
dsi0_out: endpoint {
remote-endpoint = <&panel0_in>;
};
};
};
panel0@0 {
compatible = "hlt,hpk070h275";
reg = <0>;
port {
panel0_in: endpoint {
remote-endpoint = <&dsi0_out>;
};
};
};
};
&aon {
status = "okay";
};
&mbox_910t {
status = "okay";
};
&mbox_910t_client1 {
status = "okay";
};
&mbox_910t_client2 {
status = "okay";
};
&dmac1 {
status = "okay";
};
&lightsound {
status = "okay";
};
&dmac2 {
status = "disabled";
};

13
arch/riscv/boot/dts/thead/fire-emu-soc-base-sec.dts Normal file
View File

@@ -0,0 +1,13 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2021 Alibaba Group Holding Limited.
*/
/dts-v1/;
/* #include "fire-emu.dts" */
#include "fire-emu-soc-base.dts"
&light_iopmp {
status = "disabled";
};

89
arch/riscv/boot/dts/thead/fire-emu-soc-base.dts Normal file
View File

@@ -0,0 +1,89 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2021-2022 Alibaba Group Holding Limited.
*/
/dts-v1/;
#include "fire-emu.dts"
&sdhci0 {
status = "okay";
};
&usb3_drd {
status = "okay";
};
&usb {
status = "okay";
};
&spi0 {
num-cs = <1>;
cs-gpios = <&gpio2_porta 15 0>; // GPIO_ACTIVE_HIGH: 0
rx-sample-delay-ns = <10>;
status = "okay";
spi_norflash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "winbond,w25q64jwm", "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <50000000>;
w25q,fast-read;
status = "okay";
};
spidev@1 {
compatible = "spidev";
#address-cells = <0x1>;
#size-cells = <0x1>;
reg = <0x1>;
spi-max-frequency = <50000000>;
};
};
&qspi0 {
num-cs = <1>;
cs-gpios = <&gpio2_porta 3 0>;
rx-sample-dly = <4>;
status = "okay";
spi-flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spi-nand";
spi-max-frequency = <100000000>;
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
reg = <0>;
partition@0 {
label = "ubi1";
reg = <0x00000000 0x08000000>;
};
};
};
&qspi1 {
num-cs = <1>;
cs-gpios = <&gpio0_porta 1 0>;
status = "okay";
spi-flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spi-nand";
spi-max-frequency = <66000000>;
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
reg = <0>;
partition@0 {
label = "ubi2";
reg = <0x00000000 0x08000000>;
};
};
};

19
arch/riscv/boot/dts/thead/fire-emu-soc-c910x4.dts Normal file
View File

@@ -0,0 +1,19 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2021-2022 Alibaba Group Holding Limited.
*/
#include "fire-emu.dts"
&c910_1 {
status = "okay";
};
&c910_2 {
status = "okay";
};
&c910_3 {
status = "okay";
};

57
arch/riscv/boot/dts/thead/fire-emu-vi-dsp-vo.dts Normal file
View File

@@ -0,0 +1,57 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2021-2022 Alibaba Group Holding Limited.
*/
/dts-v1/;
#include "fire-emu.dts"
&c910_1 {
status = "okay";
};
&vi_pre {
status = "okay";
};
&dewarp {
status = "okay";
};
&xtensa_dsp {
status = "okay";
};
&xtensa_dsp0 {
status = "okay";
};
&xtensa_dsp1 {
status = "okay";
};
&vosys_reg {
status = "okay";
};
&display_subsystem {
status = "okay";
};
&dpu {
status = "okay";
};
&hdmi_tx {
status = "okay";
};
&dsi0 {
status = "okay";
};
&dpu_enc0 {
status = "okay";
};

119
arch/riscv/boot/dts/thead/fire-emu-vi-vp-vo.dts Normal file
View File

@@ -0,0 +1,119 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2021-2022 Alibaba Group Holding Limited.
*/
/dts-v1/;
#include "fire-emu.dts"
&c910_1 {
status = "okay";
};
&vi_pre {
status = "okay";
};
&dewarp {
status = "okay";
};
&venc {
status = "okay";
};
&vdec {
status = "okay";
};
&g2d {
status = "okay";
};
&vosys_reg {
status = "okay";
};
&display_subsystem {
status = "okay";
};
&dpu_enc0 {
status = "okay";
ports {
/* output */
port@1 {
reg = <1>;
enc0_out: endpoint {
remote-endpoint = <&dsi0_in>;
};
};
};
};
&dsi0 {
status = "okay";
};
&dhost_0 {
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dsi0_in: endpoint {
remote-endpoint = <&enc0_out>;
};
};
port@1 {
reg = <1>;
dsi0_out: endpoint {
remote-endpoint = <&panel0_in>;
};
};
};
panel0@0 {
compatible = "hlt,hpk070h275";
reg = <0>;
port {
panel0_in: endpoint {
remote-endpoint = <&dsi0_out>;
};
};
};
};
&dpu_enc1 {
ports {
/delete-node/ port@0;
};
};
&disp1_out {
remote-endpoint = <&hdmi_tx_in>;
};
&dpu {
status = "okay";
};
&hdmi_tx {
status = "okay";
port@0 {
/* input */
hdmi_tx_in: endpoint {
remote-endpoint = <&disp1_out>;
};
};
};

1634
arch/riscv/boot/dts/thead/fire-emu.dts
View File

File diff suppressed because it is too large Load Diff

307
arch/riscv/boot/dts/thead/fire.dtsi
View File

@@ -23,7 +23,6 @@
aliases {
ethernet0 = &gmac0;
ethernet1 = &gmac1;
gpio0 = &gpio0;
gpio1 = &gpio1;
gpio2 = &gpio2;
@@ -93,7 +92,7 @@
};
};
thermal-zones {
thermal_zones: thermal-zones {
cpu-thermal-zone {
polling-delay-passive = <250>;
polling-delay = <2000>;
@@ -166,8 +165,6 @@
<&clk CPU_PLL0_FOUTPOSTDIV>;
clock-names = "c910_cclk", "c910_cclk_i0",
"cpu_pll1_foutpostdiv", "cpu_pll0_foutpostdiv";
dvdd-supply = <&dvdd_cpu_reg>;
dvddm-supply = <&dvddm_cpu_reg>;
cpu0_intc: interrupt-controller {
#interrupt-cells = <1>;
@@ -178,7 +175,7 @@
c910_1: cpu@1 {
device_type = "cpu";
reg = <1>;
status = "okay";
status = "disabled";
compatible = "riscv";
riscv,isa = "rv64imafdcvsu";
mmu-type = "riscv,sv39";
@@ -212,8 +209,6 @@
<&clk CPU_PLL0_FOUTPOSTDIV>;
clock-names = "c910_cclk", "c910_cclk_i0",
"cpu_pll1_foutpostdiv", "cpu_pll0_foutpostdiv";
dvdd-supply = <&dvdd_cpu_reg>;
dvddm-supply = <&dvddm_cpu_reg>;
cpu1_intc: interrupt-controller {
#interrupt-cells = <1>;
@@ -224,7 +219,7 @@
c910_2: cpu@2 {
device_type = "cpu";
reg = <2>;
status = "okay";
status = "disabled";
compatible = "riscv";
riscv,isa = "rv64imafdcvsu";
mmu-type = "riscv,sv39";
@@ -258,8 +253,6 @@
<&clk CPU_PLL0_FOUTPOSTDIV>;
clock-names = "c910_cclk", "c910_cclk_i0",
"cpu_pll1_foutpostdiv", "cpu_pll0_foutpostdiv";
dvdd-supply = <&dvdd_cpu_reg>;
dvddm-supply = <&dvddm_cpu_reg>;
cpu2_intc: interrupt-controller {
#interrupt-cells = <1>;
@@ -270,7 +263,7 @@
c910_3: cpu@3 {
device_type = "cpu";
reg = <3>;
status = "okay";
status = "disabled";
compatible = "riscv";
riscv,isa = "rv64imafdcvsu";
mmu-type = "riscv,sv39";
@@ -304,8 +297,6 @@
<&clk CPU_PLL0_FOUTPOSTDIV>;
clock-names = "c910_cclk", "c910_cclk_i0",
"cpu_pll1_foutpostdiv", "cpu_pll0_foutpostdiv";
dvdd-supply = <&dvdd_cpu_reg>;
dvddm-supply = <&dvddm_cpu_reg>;
cpu3_intc: interrupt-controller {
#interrupt-cells = <1>;
@@ -315,7 +306,7 @@
};
};
display-subsystem {
display_subsystem: display-subsystem {
compatible = "verisilicon,display-subsystem";
ports = <&dpu_disp0>, <&dpu_disp1>;
status = "disabled";
@@ -382,7 +373,7 @@
entry-cnt = <4>;
control-reg = <0xff 0xff015004>;
control-val = <0x1c>;
csr-copy = <0x7f3 0x7c0 0x7c1 0x7c2 0x7c3 0x7c5 0x7cc>;
csr-copy = <0x7f3 0x7c0 0x7c1 0x7c2 0x7c3 0x7c5 0x7cc 0x7ce>;
};
clint0: clint@ffdc000000 {
@@ -421,7 +412,7 @@
dummy_clock_apb: apb-clock@0 {
compatible = "fixed-clock";
reg = <0>; /* Not address, just for index */
clock-frequency = <62500000>;
clock-frequency = <50000000>;
clock-output-names = "dummy_clock_apb";
#clock-cells = <0>;
};
@@ -469,7 +460,7 @@
dummy_clock_dphy_ref: dphy-ref-clock@7 {
compatible = "fixed-clock";
reg = <7>; /* Not address, just for index */
clock-frequency = <24000000>;
clock-frequency = <40000000>;
clock-output-names = "dummy_clock_dphy_ref";
#clock-cells = <0>;
};
@@ -477,7 +468,7 @@
dummy_clock_dphy_cfg: dphy-cfg-clock@8 {
compatible = "fixed-clock";
reg = <8>; /* Not address, just for index */
clock-frequency = <24000000>;
clock-frequency = <40000000>;
clock-output-names = "dummy_clock_dphy_cfg";
#clock-cells = <0>;
};
@@ -485,7 +476,7 @@
dummy_clock_dpu_pixel0: dpu-pixel-clock@9 {
compatible = "fixed-clock";
reg = <9>;
clock-frequency = <72000000>;
clock-frequency = <25200000>;
clock-output-names = "dummy_clock_dpu_pixel0";
#clock-cells = <0>;
};
@@ -493,7 +484,7 @@
dummy_clock_dpu_pixel1: dpu-pixel-clock@10 {
compatible = "fixed-clock";
reg = <10>;
clock-frequency = <74250000>;
clock-frequency = <25200000>;
clock-output-names = "dummy_clock_dpu_pixel1";
#clock-cells = <0>;
};
@@ -525,7 +516,7 @@
dummy_clock_eip: eip-clock@14 {
compatible = "fixed-clock";
reg = <14>; /* Not address, just for index */
clock-frequency = <400000000>;
clock-frequency = <30000000>;
clock-output-names = "dummy_clock_eip";
#clock-cells = <0>;
};
@@ -533,7 +524,7 @@
dummy_clock_spi: spi-clock@15 {
compatible = "fixed-clock";
reg = <15>; /* Not address, just for index */
clock-frequency = <396000000>;
clock-frequency = <50000000>;
clock-output-names = "dummy_clock_spi";
#clock-cells = <0>;
};
@@ -541,7 +532,7 @@
dummy_clock_qspi: spi-clock@16 {
compatible = "fixed-clock";
reg = <15>; /* Not address, just for index */
clock-frequency = <792000000>;
clock-frequency = <50000000>;
clock-output-names = "dummy_clock_qspi";
#clock-cells = <0>;
};
@@ -549,7 +540,7 @@
dummy_gmac_ahb: gmac-ahb-clock@16 {
compatible = "fixed-clock";
reg = <16>;
clock-frequency = <250000000>;
clock-frequency = <50000000>;
clock-output-names = "dummy_gmac_ahb";
#clock-cells = <0>;
};
@@ -557,7 +548,7 @@
dummy_clock_gmac: gmac-clock@17 {
compatible = "fixed-clock";
reg = <17>;
clock-frequency = <500000000>;
clock-frequency = <50000000>;
clock-output-names = "dummy_clock_gmac";
#clock-cells = <0>;
};
@@ -565,7 +556,7 @@
dummy_clock_sdhci: sdhci-clock@18 {
compatible = "fixed-clock";
reg = <18>; /* Not address, just for index */
clock-frequency = <198000000>;
clock-frequency = <50000000>;
clock-output-names = "dummy_clock_sdhci";
#clock-cells = <0>;
};
@@ -573,16 +564,16 @@
dummy_clock_aonsys_clk: aonsys-clk-clock@19 {
compatible = "fixed-clock";
reg = <19>; /* Not address, just for index */
clock-frequency = <73728000>;
clock-frequency = <24000000>;
clock-output-names = "dummy_clock_aonsys_clk";
#clock-cells = <0>;
};
dummy_clock_uart_sclk: uart-sclk-clock@20 {
dummy_clock_uart: uart-sclk-clock@20 {
compatible = "fixed-clock";
reg = <20>; /* Not address, just for index */
clock-frequency = <100000000>;
clock-output-names = "dummy_clock_uart_sclk";
clock-frequency = <50000000>;
clock-output-names = "dummy_clock_uart";
#clock-cells = <0>;
};
@@ -592,6 +583,20 @@
clock-frequency = <24000000>;
#clock-cells = <0>;
};
dummy_clock_vipre: vipre-dummy-clock@22 {
compatible = "fixed-clock";
reg = <22>;
clock-frequency = <13000000>;
#clock-cells = <0>;
};
dummy_clock_vpsys: vpsys-dummy-clock@23 {
compatible = "fixed-clock";
reg = <23>;
clock-frequency = <24000000>;
#clock-cells = <0>;
};
};
iso7816: iso7816-card@fff7f30000 {
@@ -644,9 +649,6 @@
reg = <0xb0 6>;
};
gmac1_mac_address: mac-address@184 {
reg = <0xb8 6>;
};
};
misc_sysreg: misc_sysreg@ffec02c000 {
@@ -797,9 +799,8 @@
compatible = "thead,pwm-light";
reg = <0xff 0xec01c000 0x0 0x4000>;
#pwm-cells = <2>;
clocks = <&clk CLKGEN_PWM_PCLK>,
<&clk CLKGEN_PWM_CCLK>;
clock-names = "pclk", "cclk";
clocks = <&dummy_clock_apb>;
clock-names = "pwm";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm>;
};
@@ -809,7 +810,7 @@
reg = <0xff 0xefc32000 0x0 0x14>;
clocks = <&dummy_clock_apb>;
clock-names = "timer";
clock-frequency = <62500000>;
clock-frequency = <50000000>;
interrupts = <16>;
interrupt-parent = <&intc>;
status = "okay";
@@ -820,7 +821,7 @@
reg = <0xff 0xefc32014 0x0 0x14>;
clocks = <&dummy_clock_apb>;
clock-names = "timer";
clock-frequency = <62500000>;
clock-frequency = <50000000>;
interrupts = <17>;
interrupt-parent = <&intc>;
status = "okay";
@@ -831,7 +832,7 @@
reg = <0xff 0xefc32028 0x0 0x14>;
clocks = <&dummy_clock_apb>;
clock-names = "timer";
clock-frequency = <62500000>;
clock-frequency = <50000000>;
interrupts = <18>;
interrupt-parent = <&intc>;
status = "disabled";
@@ -842,7 +843,7 @@
reg = <0xff 0xefc3203c 0x0 0x14>;
clocks = <&dummy_clock_apb>;
clock-names = "timer";
clock-frequency = <62500000>;
clock-frequency = <50000000>;
interrupts = <19>;
interrupt-parent = <&intc>;
status = "disabled";
@@ -851,7 +852,7 @@
padctrl_aosys: padctrl-aosys@fffff4a000 {
compatible = "thead,light-fm-aon-pinctrl";
reg = <0xff 0xfff4a000 0x0 0x2000>;
status = "okay";
status = "disabled";
};
timer4: timer@ffffc33000 {
@@ -859,7 +860,7 @@
reg = <0xff 0xffc33000 0x0 0x14>;
clocks = <&dummy_clock_apb>;
clock-names = "timer";
clock-frequency = <62500000>;
clock-frequency = <50000000>;
interrupts = <20>;
interrupt-parent = <&intc>;
status = "disabled";
@@ -870,7 +871,7 @@
reg = <0xff 0xffc33014 0x0 0x14>;
clocks = <&dummy_clock_apb>;
clock-names = "timer";
clock-frequency = <62500000>;
clock-frequency = <50000000>;
interrupts = <21>;
interrupt-parent = <&intc>;
status = "disabled";
@@ -881,7 +882,7 @@
reg = <0xff 0xffc33028 0x0 0x14>;
clocks = <&dummy_clock_apb>;
clock-names = "timer";
clock-frequency = <62500000>;
clock-frequency = <50000000>;
interrupts = <22>;
interrupt-parent = <&intc>;
status = "disabled";
@@ -892,7 +893,7 @@
reg = <0xff 0xffc3303c 0x0 0x14>;
clocks = <&dummy_clock_apb>;
clock-names = "timer";
clock-frequency = <62500000>;
clock-frequency = <50000000>;
interrupts = <23>;
interrupt-parent = <&intc>;
status = "disabled";
@@ -903,7 +904,7 @@
reg = <0xff 0xe7014000 0x0 0x4000>;
interrupt-parent = <&intc>;
interrupts = <36>;
clocks = <&clk CLKGEN_UART0_SCLK>;
clocks = <&dummy_clock_uart>;
clock-names = "baudclk";
reg-shift = <2>;
reg-io-width = <4>;
@@ -916,7 +917,7 @@
reg = <0xff 0xe7f00000 0x0 0x4000>;
interrupt-parent = <&intc>;
interrupts = <37>;
clocks = <&clk CLKGEN_UART1_SCLK>;
clocks = <&dummy_clock_uart>;
clock-names = "baudclk";
reg-shift = <2>;
reg-io-width = <4>;
@@ -929,7 +930,7 @@
reg = <0xff 0xec010000 0x0 0x4000>;
interrupt-parent = <&intc>;
interrupts = <38>;
clocks = <&clk CLKGEN_UART2_SCLK>;
clocks = <&dummy_clock_uart>;
clock-names = "baudclk";
reg-shift = <2>;
reg-io-width = <4>;
@@ -942,7 +943,7 @@
reg = <0xff 0xe7f04000 0x0 0x4000>;
interrupt-parent = <&intc>;
interrupts = <39>;
clocks = <&clk CLKGEN_UART3_SCLK>;
clocks = <&dummy_clock_uart>;
clock-names = "baudclk";
reg-shift = <2>;
reg-io-width = <4>;
@@ -955,7 +956,7 @@
reg = <0xff 0xf7f08000 0x0 0x4000>;
interrupt-parent = <&intc>;
interrupts = <40>;
clocks = <&clk CLKGEN_UART4_SCLK>;
clocks = <&dummy_clock_uart>;
clock-names = "baudclk";
reg-shift = <2>;
reg-io-width = <4>;
@@ -968,7 +969,7 @@
reg = <0xff 0xf7f0c000 0x0 0x4000>;
interrupt-parent = <&intc>;
interrupts = <41>;
clocks = <&clk CLKGEN_UART5_SCLK>;
clocks = <&dummy_clock_uart>;
clock-names = "baudclk";
reg-shift = <2>;
reg-io-width = <4>;
@@ -1030,9 +1031,9 @@
interrupt-parent = <&intc>;
interrupts = <101>;
interrupt-names = "irq_2d";
clocks = <&vpsys_clk_gate LIGHT_VPSYS_G2D_PCLK>,
<&vpsys_clk_gate LIGHT_VPSYS_G2D_ACLK>,
<&vpsys_clk_gate LIGHT_VPSYS_G2D_CCLK>;
clocks = <&dummy_clock_vpsys>,
<&dummy_clock_vpsys>,
<&dummy_clock_vpsys>;
clock-names = "pclk", "aclk", "cclk";
status = "okay";
};
@@ -1046,11 +1047,11 @@
compatible = "thead,light-mipi-dphy";
regmap = <&dsi0>;
vosys-regmap = <&vosys_reg>;
clocks = <&vosys_clk_gate LIGHT_CLKGEN_MIPIDSI0_REFCLK>,
<&vosys_clk_gate LIGHT_CLKGEN_MIPIDSI0_CFG_CLK>,
<&vosys_clk_gate LIGHT_CLKGEN_MIPIDSI0_PCLK>,
<&clk OSC_24M>,
<&clk OSC_24M>;
clocks = <&dummy_clock_dphy_ref>,
<&dummy_clock_dphy_cfg>,
<&dummy_clock_dphy_ref>,
<&dummy_clock_dpu_pixel0>,
<&dummy_clock_dphy_cfg>;
clock-names = "refclk", "cfgclk", "pclk", "prefclk", "pcfgclk";
#phy-cells = <0>;
};
@@ -1060,8 +1061,8 @@
regmap = <&dsi0>;
interrupt-parent = <&intc>;
interrupts = <129>;
clocks = <&vosys_clk_gate LIGHT_CLKGEN_MIPIDSI0_PCLK>,
<&vosys_clk_gate LIGHT_CLKGEN_MIPIDSI0_PIXCLK>;
clocks = <&dummy_clock_dphy_cfg>,
<&dummy_clock_dpu_pixel0>;
clock-names = "pclk", "pixclk";
phys = <&dphy_0>;
phy-names = "dphy";
@@ -1079,11 +1080,11 @@
compatible = "thead,light-mipi-dphy";
regmap = <&dsi1>;
vosys-regmap = <&vosys_reg>;
clocks = <&vosys_clk_gate LIGHT_CLKGEN_MIPIDSI1_REFCLK>,
<&vosys_clk_gate LIGHT_CLKGEN_MIPIDSI1_CFG_CLK>,
<&vosys_clk_gate LIGHT_CLKGEN_MIPIDSI1_PCLK>,
<&clk OSC_24M>,
<&clk OSC_24M>;
clocks = <&dummy_clock_dphy_ref>,
<&dummy_clock_dphy_cfg>,
<&dummy_clock_dphy_ref>,
<&dummy_clock_dpu_pixel1>,
<&dummy_clock_dphy_cfg>;
clock-names = "refclk", "cfgclk", "pclk", "prefclk", "pcfgclk";
#phy-cells = <0>;
};
@@ -1093,8 +1094,8 @@
regmap = <&dsi1>;
interrupt-parent = <&intc>;
interrupts = <129>;
clocks = <&vosys_clk_gate LIGHT_CLKGEN_MIPIDSI1_PCLK>,
<&vosys_clk_gate LIGHT_CLKGEN_MIPIDSI1_PIXCLK>;
clocks = <&dummy_clock_dphy_cfg>,
<&dummy_clock_dpu_pixel1>;
clock-names = "pclk", "pixclk";
phys = <&dphy_1>;
phy-names = "dphy";
@@ -1114,11 +1115,11 @@
reg = <0xff 0xef540000 0x0 0x40000>;
interrupt-parent = <&intc>;
interrupts = <111>;
clocks = <&vosys_clk_gate LIGHT_CLKGEN_HDMI_PCLK>,
<&vosys_clk_gate LIGHT_CLKGEN_HDMI_SFR_CLK>,
<&vosys_clk_gate LIGHT_CLKGEN_HDMI_CEC_CLK>,
<&vosys_clk_gate LIGHT_CLKGEN_HDMI_PIXCLK>,
<&vosys_clk_gate LIGHT_CLKGEN_HDMI_I2S_CLK>;
clocks = <&dummy_clock_dpu_pixel0>,
<&dummy_clock_dpu_pixel0>,
<&dummy_clock_dpu_pixel0>,
<&dummy_clock_dpu_pixel0>,
<&dummy_clock_dpu_pixel0>;
clock-names = "iahb", "isfr", "cec", "pixclk", "i2s";
reg-io-width = <4>;
phy_version = <301>;
@@ -1135,19 +1136,19 @@
<0xff 0xef630010 0x0 0x60>;
interrupt-parent = <&intc>;
interrupts = <93>;
clocks = <&vosys_clk_gate LIGHT_CLKGEN_DPU_CCLK>,
<&vosys_clk_gate LIGHT_CLKGEN_DPU_PIXCLK0>,
<&vosys_clk_gate LIGHT_CLKGEN_DPU_PIXCLK1>,
<&vosys_clk_gate LIGHT_CLKGEN_DPU_ACLK>,
<&vosys_clk_gate LIGHT_CLKGEN_DPU_HCLK>,
<&clk DPU0_PLL_DIV_CLK>,
<&clk DPU1_PLL_DIV_CLK>,
<&clk DPU0_PLL_FOUTPOSTDIV>,
<&clk DPU1_PLL_FOUTPOSTDIV>;
clocks = <&dummy_clock_dpu_pixel0>,
<&dummy_clock_dpu_pixel0>,
<&dummy_clock_dpu_pixel0>,
<&dummy_clock_dpu_pixel0>,
<&dummy_clock_dpu_pixel0>,
<&dummy_clock_dpu_pixel0>,
<&dummy_clock_dpu_pixel0>,
<&dummy_clock_dpu_pixel0>,
<&dummy_clock_dpu_pixel0>;
clock-names = "core_clk", "pix_clk0", "pix_clk1",
"axi_clk", "cfg_clk", "pixclk0",
"pixclk1", "dpu0_pll_foutpostdiv",
"dpu1_pll_foutpostdiv";
"axi_clk", "cfg_clk", "pixclk0",
"pixclk1", "dpu0_pll_foutpostdiv",
"dpu1_pll_foutpostdiv";
status = "disabled";
dpu_disp0: port@0 {
@@ -1172,7 +1173,7 @@
reg = <0xff 0xefc30000 0x0 0x1000>;
interrupt-parent = <&intc>;
interrupts = <24>;
clocks = <&clk CLKGEN_WDT0_PCLK>;
clocks = <&dummy_clock_apb>;
clock-names = "tclk";
resets = <&rst LIGHT_RESET_WDT0>;
status = "okay";
@@ -1183,7 +1184,7 @@
reg = <0xff 0xefc31000 0x0 0x1000>;
interrupt-parent = <&intc>;
interrupts = <25>;
clocks = <&clk CLKGEN_WDT1_PCLK>;
clocks = <&dummy_clock_apb>;
clock-names = "tclk";
resets = <&rst LIGHT_RESET_WDT1>;
status = "okay";
@@ -1221,7 +1222,7 @@
dma-mask = <0xf 0xffffffff>;
snps,usb3_lpm_capable;
snps,usb_sofitpsync;
status = "okay";
status = "disabled";
};
};
@@ -1323,7 +1324,7 @@
interrupt-parent = <&intc>;
interrupts = <66>;
interrupt-names = "macirq";
clocks = <&clk CLKGEN_GMAC0_CCLK>;
clocks = <&dummy_clock_gmac>;
clock-names = "gmac_pll_clk";
snps,pbl = <32>;
snps,fixed-burst;
@@ -1332,29 +1333,9 @@
nvmem-cell-names = "mac-address";
};
gmac1: ethernet@ffe7060000 {
compatible = "thead,light-dwmac";
reg = <0xff 0xe7060000 0x0 0x2000
0xff 0xec00401c 0x0 0x4
0xff 0xec004020 0x0 0x4
0xff 0xec004000 0x0 0x1c>;
reg-names = "gmac", "phy_if_reg", "txclk_dir_reg", "clk_mgr_reg";
interrupt-parent = <&intc>;
interrupts = <67>;
interrupt-names = "macirq";
clocks = <&clk CLKGEN_GMAC1_CCLK>;
clock-names = "gmac_pll_clk";
snps,pbl = <32>;
snps,fixed-burst;
snps,axi-config = <&stmmac_axi_setup>;
nvmem-cells = <&gmac1_mac_address>;
nvmem-cell-names = "mac-address";
};
emmc: sdhci@ffe7080000 {
compatible = "snps,dwcmshc-sdhci";
reg = <0xff 0xe7080000 0x0 0x10000
0xff 0xef014060 0x0 0x4>;
reg = <0xff 0xe7080000 0x0 0x10000>;
interrupt-parent = <&intc>;
interrupts = <62>;
interrupt-names = "sdhciirq";
@@ -1364,8 +1345,7 @@
sdhci0: sd@ffe7090000 {
compatible = "snps,dwcmshc-sdhci";
reg = <0xff 0xe7090000 0x0 0x10000
0xff 0xef014064 0x0 0x4>;
reg = <0xff 0xe7090000 0x0 0x10000>;
interrupt-parent = <&intc>;
interrupts = <64>;
interrupt-names = "sdhci0irq";
@@ -1375,8 +1355,7 @@
sdhci1: sd@ffe70a0000 {
compatible = "snps,dwcmshc-sdhci";
reg = <0xff 0xe70a0000 0x0 0x10000
0xff 0xef014064 0x0 0x4>;
reg = <0xff 0xe70a0000 0x0 0x10000>;
interrupt-parent = <&intc>;
interrupts = <71>;
interrupt-names = "sdhci1irq";
@@ -1397,11 +1376,11 @@
interrupts = <102>;
interrupt-names = "gpuirq";
vosys-regmap = <&vosys_reg>;
power-domains = <&pd LIGHT_AON_GPU_PD>;
clocks = <&vosys_clk_gate LIGHT_CLKGEN_GPU_CORE_CLK>,
<&vosys_clk_gate LIGHT_CLKGEN_GPU_CFG_ACLK>;
clock-names = "cclk", "aclk";
gpu_clk_rate = <18000000>;
//power-domains = <&pd LIGHT_AON_GPU_PD>;
clocks = <&dummy_clock_gpu>,
<&dummy_clock_gpu>;
clock-names = "cclk", "aclk";
gpu_clk_rate = <18000000>;
dma-mask = <0xf 0xffffffff>;
status = "disabled";
};
@@ -1411,10 +1390,10 @@
reg = <0xff 0xecc00000 0x0 0x8000>;
interrupt-parent = <&intc>;
interrupts = <131>;
power-domains = <&pd LIGHT_AON_VDEC_PD>;
clocks = <&vpsys_clk_gate LIGHT_VPSYS_VDEC_ACLK>,
<&vpsys_clk_gate LIGHT_VPSYS_VDEC_CCLK>,
<&vpsys_clk_gate LIGHT_VPSYS_VDEC_PCLK>;
//power-domains = <&pd LIGHT_AON_VDEC_PD>;
clocks = <&dummy_clock_vpsys>,
<&dummy_clock_vpsys>,
<&dummy_clock_vpsys>;
clock-names = "aclk", "cclk", "pclk";
status = "disabled";
};
@@ -1424,10 +1403,10 @@
reg = <0xff 0xecc10000 0x0 0x8000>;
interrupt-parent = <&intc>;
interrupts = <133>;
power-domains = <&pd LIGHT_AON_VENC_PD>;
clocks = <&vpsys_clk_gate LIGHT_VPSYS_VENC_ACLK>,
<&vpsys_clk_gate LIGHT_VPSYS_VENC_CCLK>,
<&vpsys_clk_gate LIGHT_VPSYS_VENC_PCLK>;
//power-domains = <&pd LIGHT_AON_VENC_PD>;
clocks = <&dummy_clock_vpsys>,
<&dummy_clock_vpsys>,
<&dummy_clock_vpsys>;
clock-names = "aclk", "cclk", "pclk";
status = "disabled";
};
@@ -1443,7 +1422,7 @@
vidmem: vidmem@ffecc08000 {
compatible = "thead,light-vidmem";
reg = <0xff 0xecc08000 0x0 0x1000>;
status = "disabled";
status = "okay";
};
light_i2s: light_i2s@ffe7034000 {
@@ -1451,7 +1430,7 @@
compatible = "light,light-i2s";
reg = <0xff 0xe7034000 0x0 0x4000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_audio_i2s0>;
pinctrl-0 = <&pinctrl_light_i2s0>;
light,mode = "i2s-master";
light,sel = "ap_i2s";
interrupt-parent = <&intc>;
@@ -1532,7 +1511,7 @@
reg-names = "common", "ts", "pd", "vm";
clocks = <&dummy_clock_aonsys_clk>;
#thermal-sensor-cells = <1>;
status = "okay";
status = "disabled";
};
i2c0: i2c@ffe7f20000 {
@@ -1660,10 +1639,10 @@
reg = <0xff 0xe4100000 0x0 0x10000>;
interrupt-parent = <&intc>;
interrupts = <117>,<118>;
clocks = <&visys_clk_gate LIGHT_CLKGEN_ISP0_ACLK>,
<&visys_clk_gate LIGHT_CLKGEN_ISP0_HCLK>,
<&visys_clk_gate LIGHT_CLKGEN_ISP0_PIXELCLK>,
<&visys_clk_gate LIGHT_CLKGEN_ISP0_CLK>;
clocks = <&dummy_clock_visys>,
<&dummy_clock_visys>,
<&dummy_clock_visys>,
<&dummy_clock_visys>;
clock-names = "aclk", "hclk", "isp0_pclk", "cclk";
status = "disabled";
};
@@ -1673,11 +1652,11 @@
reg = <0xff 0xe4110000 0x0 0x10000>;
interrupt-parent = <&intc>;
interrupts = <120>,<121>;
clocks = <&visys_clk_gate LIGHT_CLKGEN_ISP0_ACLK>,
<&visys_clk_gate LIGHT_CLKGEN_ISP0_HCLK>,
<&visys_clk_gate LIGHT_CLKGEN_ISP0_PIXELCLK>,
<&visys_clk_gate LIGHT_CLKGEN_ISP1_CLK>,
<&visys_clk_gate LIGHT_CLKGEN_ISP1_PIXELCLK>;
clocks = <&dummy_clock_visys>,
<&dummy_clock_visys>,
<&dummy_clock_visys>,
<&dummy_clock_visys>,
<&dummy_clock_visys>;
clock-names = "aclk", "hclk", "isp0_pclk", "cclk", "isp1_pclk";
status = "disabled";
};
@@ -1687,9 +1666,9 @@
reg = <0xff 0xe4120000 0x0 0x10000>;
interrupt-parent = <&intc>;
interrupts = <123>,<124>;
clocks = <&visys_clk_gate LIGHT_CLKGEN_ISP_RY_ACLK>,
<&visys_clk_gate LIGHT_CLKGEN_ISP_RY_HCLK>,
<&visys_clk_gate LIGHT_CLKGEN_ISP_RY_CCLK>;
clocks = <&dummy_clock_visys>,
<&dummy_clock_visys>,
<&dummy_clock_visys>;
clock-names = "aclk", "hclk", "cclk";
status = "disabled";
};
@@ -1699,10 +1678,10 @@
reg = <0xff 0xe4130000 0x0 0x10000>;
interrupt-parent = <&intc>;
interrupts = <98>,<99>;
clocks = <&visys_clk_gate LIGHT_CLKGEN_DW200_ACLK>,
<&visys_clk_gate LIGHT_CLKGEN_DW200_HCLK>,
<&visys_clk_gate LIGHT_CLKGEN_DW200_CLK_VSE>,
<&visys_clk_gate LIGHT_CLKGEN_DW200_CLK_DWE>;
clocks = <&dummy_clock_visys>,
<&dummy_clock_visys>,
<&dummy_clock_visys>,
<&dummy_clock_visys>;
clock-names = "aclk", "hclk", "vseclk", "dweclk";
status = "disabled";
};
@@ -1738,10 +1717,10 @@
interrupts = <128>;
dphyglueiftester = <0x180>;
sysreg_mipi_csi_ctrl = <0x140>;
clocks = <&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI0_PCLK>,
<&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI0_PIXCLK>,
<&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI0_CFG_CLK>;
clock-names = "pclk", "pixclk", "cfg_clk";
clocks = <&dummy_clock_visys>,
<&dummy_clock_visys>,
<&dummy_clock_visys>;
clock-names = "pclk", "pixclk", "cfg_clk";
phy_name = "CSI_4LANE";
status = "disabled";
};
@@ -1761,10 +1740,10 @@
sysreg_mipi_csi_ctrl = <0x148>;
visys-regmap = <&visys_reg>;
csia-regmap = <&csia_reg>;
clocks = <&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI1_PCLK>,
<&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI1_PIXCLK>,
<&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI1_CFG_CLK>;
clock-names = "pclk", "pixclk", "cfg_clk";
clocks = <&dummy_clock_visys>,
<&dummy_clock_visys>,
<&dummy_clock_visys>;
clock-names = "pclk", "pixclk", "cfg_clk";
phy_name = "CSI_B";
status = "disabled";
};
@@ -1776,10 +1755,10 @@
interrupts = <127>;
dphyglueiftester = <0x184>;
sysreg_mipi_csi_ctrl = <0x144>;
clocks = <&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI2_PCLK>,
<&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI2_PIXCLK>,
<&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI2_CFG_CLK>;
clock-names = "pclk", "pixclk", "cfg_clk";
clocks = <&dummy_clock_visys>,
<&dummy_clock_visys>,
<&dummy_clock_visys>;
clock-names = "pclk", "pixclk", "cfg_clk";
phy_name = "CSI_A";
status = "disabled";
};
@@ -1808,9 +1787,9 @@
reg = <0xff 0xe4030000 0x0 0x1000>;
interrupt-parent = <&intc>;
interrupts = <134>;
clocks = <&visys_clk_gate LIGHT_CLKGEN_VIPRE_ACLK>,
<&visys_clk_gate LIGHT_CLKGEN_VIPRE_PCLK>,
<&visys_clk_gate LIGHT_CLKGEN_VIPRE_PIXELCLK>;
clocks = <&dummy_clock_vipre>,
<&dummy_clock_vipre>,
<&dummy_clock_vipre>;
clock-names ="aclk", "pclk", "pixclk";
status = "disabled";
};
@@ -2016,11 +1995,6 @@
};
};
pmp: pmp@ffdc020000 {
compatible = "pmp";
reg = <0xff 0xdc020000 0x0 0x1000>;
};
mrvbr: mrvbr@ffff018050 {
compatible = "mrvbr";
reg = <0xff 0xff019050 0x0 0x1000>;
@@ -2056,6 +2030,7 @@
clock-names = "ipg";
icu_cpu_id = <0>;
#mbox-cells = <2>;
status = "disabled";
};
trng: rng@ffff300000 {

24
arch/riscv/boot/dts/thead/light-a-product.dts
View File

@@ -162,6 +162,14 @@
iopmp_dsp1: IOPMP_DSP1 {
is_default_region;
};
iopmp_audio0: IOPMP_AUDIO0 {
is_default_region;
};
iopmp_audio1: IOPMP_AUDIO1 {
is_default_region;
};
};
mbox_910t_client1: mbox_910t_client1 {
@@ -517,15 +525,6 @@
pagesize = <32>;
};
codec: wm8960@1a {
#sound-dai-cells = <0>;
compatible = "wlf,wm8960";
reg = <0x1a>;
wlf,shared-lrclk;
wlf,hp-cfg = <3 2 3>;
wlf,gpio-cfg = <1 3>;
};
touch@5d {
#gpio-cells = <2>;
compatible = "goodix,gt911";
@@ -535,7 +534,7 @@
irq-gpios = <&gpio1_porta 8 0>;
reset-gpios = <&gpio1_porta 7 0>;
AVDD28-supply = <&reg_tp_pwr_en>;
touchscreen-size-x = <720>;
touchscreen-size-x = <800>;
touchscreen-size-y = <1280>;
};
};
@@ -552,7 +551,7 @@
irq-gpios = <&gpio1_porta 12 0>;
reset-gpios = <&gpio1_porta 11 0>;
AVDD28-supply = <&reg_tp1_pwr_en>;
touchscreen-size-x = <720>;
touchscreen-size-x = <800>;
touchscreen-size-y = <1280>;
};
};
@@ -687,6 +686,7 @@
no-mmc;
non-removable;
io_fixed_1v8;
rxclk-sample-delay = <80>;
post-power-on-delay-ms = <50>;
wprtn_ignore;
cap-sd-highspeed;
@@ -729,7 +729,7 @@
>;
};
pinctrl_audio_i2s0: i2s0grp {
pinctrl_light_i2s0: i2s0grp {
thead,pins = <
FM_QSPI0_SCLK 0x2 0x208
FM_QSPI0_CSN0 0x2 0x238

67
arch/riscv/boot/dts/thead/light-a-val-android.dts
View File

@@ -30,45 +30,54 @@
&lightsound {
status = "okay";
simple-audio-card,widgets =
"Microphone", "Mic Jack",
"Speaker", "Speaker",
"Headphone", "Headphone Jack";
simple-audio-card,routing =
"Headphone Jack", "HP_L",
"Headphone Jack", "HP_R",
"Speaker", "SPK_LP",
"Speaker", "SPK_LN",
"Speaker", "SPK_RP",
"Speaker", "SPK_RN",
"Mic Jack","MICB",
"LINPUT1", "Mic Jack",
"LINPUT3", "Mic Jack";
simple-audio-card,dai-link@0 { /* I2S - CODEC */
reg = <0>;
format = "i2s";
cpu {
sound-dai = <&light_i2s 0>;
};
codec {
sound-dai = <&codec>;
};
};
simple-audio-card,dai-link@1 { /* I2S - HDMI */
simple-audio-card,dai-link@0 { /* I2S - AUDIO SYS CODEC 8156*/
reg = <0>;
format = "i2s";
cpu {
sound-dai = <&i2s0 0>;
};
codec {
sound-dai = <&es8156_audio_codec>;
};
};
simple-audio-card,dai-link@1 { /* I2S - AUDIO SYS CODEC 7210*/
reg = <1>;
format = "i2s";
cpu {
sound-dai = <&light_i2s 1>;
sound-dai = <&i2s_8ch_sd2 2>;
};
codec {
sound-dai = <&dummy_codec 2>;
sound-dai = <&es7210_audio_codec_adc0>;
};
};
};
simple-audio-card,dai-link@2 { /* I2S - HDMI */
reg = <2>;
format = "i2s";
cpu {
sound-dai = <&light_i2s 1>;
};
codec {
sound-dai = <&dummy_codec>;
};
};
};
&light_i2s {
status = "okay";
};
&i2s0 {
status = "okay";
};
&i2s_8ch_sd2 {
status = "okay";
};
&es7210_audio_codec_adc0 {
status = "okay";
};

58
arch/riscv/boot/dts/thead/light-a-val-audio-hdmi.dts Normal file
View File

@@ -0,0 +1,58 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2021 Alibaba Group Holding Limited.
*/
/dts-v1/;
#include "light-a-val-audio.dts"
/ {
display-subsystem {
status = "okay";
};
};
&dpu_enc1 {
ports {
/delete-node/ port@0;
};
};
&disp1_out {
remote-endpoint = <&hdmi_tx_in>;
};
&dpu {
status = "okay";
};
&hdmi_tx {
status = "okay";
port@0 {
/* input */
hdmi_tx_in: endpoint {
remote-endpoint = <&disp1_out>;
};
};
};
&lightsound {
status = "okay";
simple-audio-card,dai-link@2 { /* I2S - HDMI */
reg = <2>;
format = "i2s";
cpu {
sound-dai = <&light_i2s 1>;
};
codec {
sound-dai = <&dummy_codec>;
};
};
};
&light_i2s {
status = "okay";
};

100
arch/riscv/boot/dts/thead/light-a-val-audio-i2s-8ch.dts Normal file
View File

@@ -0,0 +1,100 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2021 Alibaba Group Holding Limited.
*/
#include "light-a-val-audio.dts"
/ {
model = "T-HEAD Light FM Audio VAL board";
compatible = "thead,light-val-audio-i2s-8ch", "thead,light";
};
&lightsound {
status = "okay";
simple-audio-card,dai-link@1 { /* I2S - AUDIO SYS CODEC 7210*/
reg = <1>;
format = "i2s";
cpu {
sound-dai = <&i2s_8ch_sd2 2>;
};
codec {
mclk-fs = <512>;
sound-dai = <&es7210_audio_codec_adc0>;
};
};
simple-audio-card,dai-link@2 { /* I2S - AUDIO SYS CODEC 7210*/
reg = <2>;
format = "i2s";
cpu {
sound-dai = <&i2s_8ch_sd3 3>;
};
codec {
mclk-fs = <512>;
sound-dai = <&es7210_audio_codec_adc0>;
};
};
simple-audio-card,dai-link@3 { /* I2S - AUDIO SYS CODEC 7210_1*/
reg = <3>;
format = "i2s";
cpu {
sound-dai = <&i2s_8ch_sd0 0>;
};
codec {
mclk-fs = <512>;
sound-dai = <&es7210_audio_codec_adc1>;
};
};
simple-audio-card,dai-link@4 { /* I2S - AUDIO SYS CODEC 7210_1*/
reg = <4>;
format = "i2s";
cpu {
sound-dai = <&i2s_8ch_sd1 1>;
};
codec {
mclk-fs = <512>;
sound-dai = <&es7210_audio_codec_adc1>;
};
};
};
&i2s_8ch_sd0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_audiopa4>,
<&pinctrl_audio_i2s_8ch_sd0>,
<&pinctrl_audiopa2>,
<&pinctrl_audiopa3>,
<&pinctrl_audiopa8>,
<&pinctrl_audio_i2s_8ch_bus>;
};
&i2s_8ch_sd1 {
status = "okay";
};
&i2s_8ch_sd2 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_audiopa0>,
<&pinctrl_audio_i2s_8ch_sd2>;
};
&i2s_8ch_sd3 {
status = "okay";
};
&es7210_audio_codec_adc0 {
status = "okay";
channels-max = <8>;
};
&es7210_audio_codec_adc1 {
status = "okay";
channels-max = <8>;
};

42
arch/riscv/boot/dts/thead/light-a-val-audio-spdif.dts Normal file
View File

@@ -0,0 +1,42 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2021 Alibaba Group Holding Limited.
*/
#include "light-a-val.dts"
&spdif0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_audio_spdif0>;
status = "okay";
};
&spdif1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_audio_spdif1>;
status = "okay";
};
&lightsound {
status = "okay";
simple-audio-card,dai-link@0 { /* SPDIF0 */
reg = <1>;
format = "i2s";
cpu {
sound-dai = <&spdif0>;
};
codec {
sound-dai = <&dummy_codec>;
};
};
simple-audio-card,dai-link@1 { /* SPDIF1 */
reg = <1>;
format = "i2s";
cpu {
sound-dai = <&spdif1>;
};
codec {
sound-dai = <&dummy_codec>;
};
};
};

182
arch/riscv/boot/dts/thead/light-a-val-audio-tdm.dts Normal file
View File

@@ -0,0 +1,182 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2021 Alibaba Group Holding Limited.
*/
#include "light-a-val.dts"
&tdm_slot1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_audio_tdm>;
status = "okay";
};
&tdm_slot2 {
status = "okay";
};
&tdm_slot3 {
status = "okay";
};
&tdm_slot4 {
status = "okay";
};
&tdm_slot5 {
status = "okay";
};
&tdm_slot6 {
status = "okay";
};
&tdm_slot7 {
status = "okay";
};
&tdm_slot8 {
status = "okay";
};
&audio_i2c0 {
clock-frequency = <100000>;
status = "okay";
es7210_adc2: es7210@42 {
#sound-dai-cells = <0>;
compatible = "MicArray_0";
reg = <0x42>;
work-mode = "ES7210_TDM_1LRCK_DSPB";
channels-max = <8>;
sound-name-prefix = "ES7210_ADC2";
MVDD-supply = <&soc_aud_adc_3v3_en_reg>;
AVDD-supply = <&soc_aud_adc_3v3_en_reg>;
DVDD-supply = <&soc_dvdd18_aon_reg>;
PVDD-supply = <&soc_dvdd18_aon_reg>;
};
es7210_adc3: es7210@43 {
#sound-dai-cells = <0>;
compatible = "MicArray_1";
reg = <0x43>;
work-mode = "ES7210_TDM_1LRCK_DSPB";
channels-max = <8>;
sound-name-prefix = "ES7210_ADC3";
MVDD-supply = <&soc_aud_adc_3v3_en_reg>;
AVDD-supply = <&soc_aud_adc_3v3_en_reg>;
DVDD-supply = <&soc_dvdd18_aon_reg>;
PVDD-supply = <&soc_dvdd18_aon_reg>;
};
};
&lightsound {
status = "okay";
simple-audio-card,widgets = "Speaker", "Speaker";
simple-audio-card,routing =
"AW87519 IN", "ES8156 ROUT",
"Speaker", "AW87519 VO";
simple-audio-card,aux-devs = <&audio_aw87519_pa>;
simple-audio-card,dai-link@0 { /* I2S - AUDIO SYS CODEC 8156*/
reg = <0>;
format = "i2s";
cpu {
sound-dai = <&i2s0 0>;
};
codec {
sound-dai = <&es8156_audio_codec>;
};
};
simple-audio-card,dai-link@1 { /* TDM - AUDIO SYS CODEC 7210*/
reg = <1>;
format = "dsp_b";
cpu {
sound-dai = <&tdm_slot1>;
};
codec {
sound-dai = <&es7210_adc2>;
};
};
simple-audio-card,dai-link@2 {
reg = <1>;
format = "dsp_b";
cpu {
sound-dai = <&tdm_slot2>;
};
codec {
sound-dai = <&es7210_adc2>;
};
};
simple-audio-card,dai-link@3 {
reg = <1>;
format = "dsp_b";
cpu {
sound-dai = <&tdm_slot3>;
};
codec {
sound-dai = <&es7210_adc2>;
};
};
simple-audio-card,dai-link@4 {
reg = <1>;
format = "dsp_b";
cpu {
sound-dai = <&tdm_slot4>;
};
codec {
sound-dai = <&es7210_adc2>;
};
};
simple-audio-card,dai-link@5 {
reg = <1>;
format = "dsp_b";
cpu {
sound-dai = <&tdm_slot5>;
};
codec {
sound-dai = <&es7210_adc2>;
};
};
simple-audio-card,dai-link@6 {
reg = <1>;
format = "dsp_b";
cpu {
sound-dai = <&tdm_slot6>;
};
codec {
sound-dai = <&es7210_adc2>;
};
};
simple-audio-card,dai-link@7 {
reg = <1>;
format = "dsp_b";
cpu {
sound-dai = <&tdm_slot7>;
};
codec {
sound-dai = <&es7210_adc2>;
};
};
simple-audio-card,dai-link@8 {
reg = <1>;
format = "dsp_b";
cpu {
sound-dai = <&tdm_slot8>;
};
codec {
sound-dai = <&es7210_adc2>;
};
};
};
&i2s0 {
status = "okay";
};

24
arch/riscv/boot/dts/thead/light-a-val-audio.dts
View File

@@ -11,8 +11,12 @@
};
&lightsound {
status = "okay";
status = "okay";
simple-audio-card,widgets = "Speaker", "Speaker";
simple-audio-card,routing =
"Speaker", "AW87519 VO",
"AW87519 IN", "ES8156 ROUT";
simple-audio-card,aux-devs = <&audio_aw87519_pa>;
simple-audio-card,dai-link@0 { /* I2S - AUDIO SYS CODEC 8156*/
reg = <0>;
format = "i2s";
@@ -28,22 +32,24 @@
reg = <1>;
format = "i2s";
cpu {
sound-dai = <&i2s3 0>;
sound-dai = <&i2s_8ch_sd2 2>;
};
codec {
sound-dai = <&es7210_audio_codec>;
sound-dai = <&es7210_audio_codec_adc0>;
};
};
};
&light_i2s {
status = "okay";
};
&i2s0 {
status = "okay";
};
&i2s3 {
&i2s_8ch_sd2 {
status = "okay";
};
&es7210_audio_codec_adc0 {
status = "okay";
};

2
arch/riscv/boot/dts/thead/light-a-val-ddr1G.dts
View File

@@ -11,7 +11,7 @@
memory@0 {
device_type = "memory";
reg = <0x0 0x00000000 0x0 0x40000000>;
reg = <0x0 0x200000 0x0 0x3fe00000>;
};
};

2
arch/riscv/boot/dts/thead/light-a-val-ddr2G.dts
View File

@@ -11,7 +11,7 @@
memory@0 {
device_type = "memory";
reg = <0x0 0x00000000 0x0 0x80000000>;
reg = <0x0 0x200000 0x0 0x7fe00000>;
};
};

64
arch/riscv/boot/dts/thead/light-a-val-dsi0-hdmi-audio.dts Normal file
View File

@@ -0,0 +1,64 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2021 Alibaba Group Holding Limited.
*/
/dts-v1/;
#include "light-a-val-dsi0-hdmi.dts"
&lightsound {
status = "okay";
simple-audio-card,widgets = "Speaker", "Speaker";
simple-audio-card,routing =
"Speaker", "AW87519 VO",
"AW87519 IN", "ES8156 ROUT";
simple-audio-card,aux-devs = <&audio_aw87519_pa>;
simple-audio-card,dai-link@0 { /* I2S - AUDIO SYS CODEC 8156*/
reg = <0>;
format = "i2s";
cpu {
sound-dai = <&i2s0 0>;
};
codec {
sound-dai = <&es8156_audio_codec>;
};
};
simple-audio-card,dai-link@1 { /* I2S - AUDIO SYS CODEC 7210*/
reg = <1>;
format = "i2s";
cpu {
sound-dai = <&i2s_8ch_sd2 2>;
};
codec {
sound-dai = <&es7210_audio_codec_adc0>;
};
};
simple-audio-card,dai-link@2 { /* I2S - HDMI */
reg = <2>;
format = "i2s";
cpu {
sound-dai = <&light_i2s 1>;
};
codec {
sound-dai = <&dummy_codec>;
};
};
};
&light_i2s {
status = "okay";
};
&i2s0 {
status = "okay";
};
&i2s_8ch_sd2 {
status = "okay";
};
&es7210_audio_codec_adc0 {
status = "okay";
};

18
arch/riscv/boot/dts/thead/light-a-val-full.dts
View File

@@ -95,7 +95,11 @@
&lightsound {
status = "okay";
simple-audio-card,widgets = "Speaker", "Speaker";
simple-audio-card,routing =
"Speaker", "AW87519 VO",
"AW87519 IN", "ES8156 ROUT";
simple-audio-card,aux-devs = <&audio_aw87519_pa>;
simple-audio-card,dai-link@0 { /* I2S - AUDIO SYS CODEC 8156*/
reg = <0>;
format = "i2s";
@@ -111,23 +115,27 @@
reg = <1>;
format = "i2s";
cpu {
sound-dai = <&i2s3 0>;
sound-dai = <&i2s_8ch_sd2 2>;
};
codec {
sound-dai = <&es7210_audio_codec>;
sound-dai = <&es7210_audio_codec_adc0>;
};
};
};
&light_i2s {
status = "okay";
status = "okay";
};
&i2s0 {
status = "okay";
};
&i2s3 {
&i2s_8ch_sd2 {
status = "okay";
};
&es7210_audio_codec_adc0 {
status = "okay";
};

2
arch/riscv/boot/dts/thead/light-a-val-hdmi.dts
View File

@@ -48,7 +48,7 @@
sound-dai = <&light_i2s 1>;
};
codec {
sound-dai = <&dummy_codec 2>;
sound-dai = <&dummy_codec>;
};
};
};

31
arch/riscv/boot/dts/thead/light-a-val-miniapp-dsi0.dts
View File

@@ -74,6 +74,26 @@
};
};
&padctrl_audiosys {
status = "okay";
light-audio-padctrl {
/*
* Pin Configuration Node:
* Format: <pin_id mux_node config>
*/
pinctrl_audio_i2s_8ch: audio_i2s_8ch_grp {
thead,pins = <
FM_AUDIO_IO_PA0 0x2 0x008
FM_AUDIO_IO_PA2 0x2 0x008
FM_AUDIO_IO_PA3 0x2 0x008
FM_AUDIO_IO_PA8 0x2 0x008
>;
};
};
};
&lightsound {
status = "okay";
@@ -92,15 +112,14 @@
reg = <1>;
format = "i2s";
cpu {
sound-dai = <&i2s3 0>;
sound-dai = <&i2s_8ch_sd2 2>;
};
codec {
sound-dai = <&es7210_audio_codec>;
sound-dai = <&es7210_audio_codec_adc0>;
};
};
};
&light_i2s {
status = "okay";
};
@@ -109,7 +128,11 @@
status = "okay";
};
&i2s3 {
&i2s_8ch_sd2 {
status = "okay";
};
&es7210_audio_codec_adc0 {
status = "okay";
};

10
arch/riscv/boot/dts/thead/light-a-val-miniapp-hdmi.dts
View File

@@ -56,10 +56,10 @@
reg = <1>;
format = "i2s";
cpu {
sound-dai = <&i2s3 0>;
sound-dai = <&i2s_8ch_sd2 2>;
};
codec {
sound-dai = <&es7210_audio_codec>;
sound-dai = <&es7210_audio_codec_adc0>;
};
};
};
@@ -73,7 +73,11 @@
status = "okay";
};
&i2s3 {
&i2s_8ch_sd2 {
status = "okay";
};
&es7210_audio_codec_adc0 {
status = "okay";
};

9
arch/riscv/boot/dts/thead/light-a-val-sec.dts
View File

@@ -5,9 +5,16 @@
/dts-v1/;
#include "light-a-val-dsi0-hdmi.dts"
#include "light-a-val-audio-hdmi.dts"
&light_iopmp {
status = "disabled";
};
&qspi1 {
status = "disabled";
};
&eip_28 {
status = "disabled";
};

624
arch/riscv/boot/dts/thead/light-a-val.dts
View File

@@ -16,7 +16,7 @@
chosen {
bootargs = "console=ttyS0,115200 crashkernel=256M-:128M earlycon clk_ignore_unused sram=0xffe0000000,0x180000";
stdout-path = "serial0:115200n8";
stdout-path = "serial0";
};
leds {
@@ -165,6 +165,14 @@
iopmp_dsp1: IOPMP_DSP1 {
is_default_region;
};
iopmp_audio0: IOPMP_AUDIO0 {
is_default_region;
};
iopmp_audio1: IOPMP_AUDIO1 {
is_default_region;
};
};
mbox_910t_client1: mbox_910t_client1 {
@@ -179,7 +187,8 @@
compatible = "thead,light-mbox-client";
mbox-names = "906";
mboxes = <&mbox_910t 2 0>;
status = "disabled";
audio-mbox-regmap = <&audio_mbox>;
status = "okay";
};
lightsound: lightsound@1 {
@@ -192,9 +201,24 @@
status = "disabled";
};
light_rpmsg: light_rpmsg {
compatible = "light,rpmsg-bus", "simple-bus";
memory-region = <&rpmsgmem>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
rpmsg: rpmsg{
vdev-nums = <1>;
reg = <0x0 0x1E000000 0 0x10000>;
compatible = "light,light-rpmsg";
status = "okay";
};
};
dummy_codec: dummy_codec {
#sound-dai-cells = <1>;
compatible = "linux,bt-sco";
#sound-dai-cells = <0>;
compatible = "thead,light-dummy-pcm";
sound-name-prefix = "DUMMY";
status = "okay";
};
@@ -262,6 +286,24 @@
enable-active-high;
};
soc_aud_adc_3v3_en_reg: soc-aud-adc-3v3-en {
compatible = "regulator-fixed";
regulator-name = "soc_aud_adc_3v3_en";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&pcal6408ahk_b 1 1>;
enable-active-high;
};
soc_aud_dac_3v3_en_reg: soc-aud-dac-3v3-en {
compatible = "regulator-fixed";
regulator-name = "soc_aud_dac_3v3_en";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&pcal6408ahk_b 2 1>;
enable-active-high;
};
wcn_wifi: wireless-wlan {
compatible = "wlan-platdata";
clock-names = "clk_wifi";
@@ -288,12 +330,14 @@
status = "disabled";
key-volumedown {
label = "Volume Down Key";
wakeup-source;
linux,code = <KEY_1>;
debounce-interval = <2>;
gpios = <&ao_gpio_porta 4 GPIO_ACTIVE_LOW>;
};
key-volumeup {
label = "Volume Up Key";
wakeup-source;
linux,code = <KEY_2>;
debounce-interval = <2>;
gpios = <&ao_gpio_porta 5 GPIO_ACTIVE_LOW>;
@@ -512,7 +556,14 @@
reg = <0x0 0x22000000 0x0 0x10000000>;
no-map;
};
audio_mem: memory@32000000 {
reg = <0x0 0x32000000 0x0 0x6400000>;
no-map;
};
rpmsgmem: memory@1E000000 {
reg = <0x0 0x1E000000 0x0 0x10000>;
no-map;
};
};
&adc {
@@ -523,22 +574,14 @@
&i2c0 {
clock-frequency = <400000>;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c0>;
eeprom@50 {
compatible = "atmel,24c32";
reg = <0x50>;
pagesize = <32>;
};
codec: wm8960@1a {
#sound-dai-cells = <0>;
compatible = "wlf,wm8960";
reg = <0x1a>;
wlf,shared-lrclk;
wlf,hp-cfg = <3 2 3>;
wlf,gpio-cfg = <1 3>;
};
touch@5d {
#gpio-cells = <2>;
compatible = "goodix,gt911";
@@ -548,7 +591,7 @@
irq-gpios = <&gpio1_porta 8 0>;
reset-gpios = <&gpio1_porta 7 0>;
AVDD28-supply = <&reg_tp_pwr_en>;
touchscreen-size-x = <720>;
touchscreen-size-x = <800>;
touchscreen-size-y = <1280>;
};
};
@@ -556,23 +599,82 @@
&audio_i2c0 {
clock-frequency = <100000>;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_audiopa6>,
<&pinctrl_audiopa7>,
<&pinctrl_audio_i2c0>;
es8156_audio_codec: es8156@8 {
#sound-dai-cells = <0>;
compatible = "everest,es8156";
reg = <0x08>;
};
es8156_audio_codec: es8156@8 {
#sound-dai-cells = <0>;
compatible = "everest,es8156";
reg = <0x08>;
sound-name-prefix = "ES8156";
AVDD-supply = <&soc_aud_dac_3v3_en_reg>;
DVDD-supply = <&soc_dvdd18_aon_reg>;
PVDD-supply = <&soc_dvdd18_aon_reg>;
mclk-sclk-ratio = <4>;
};
es7210_audio_codec: es7210@40 {
es7210_audio_codec_adc0: es7210@40 {
#sound-dai-cells = <0>;
compatible = "MicArray_0";
reg = <0x40>;
status = "disabled";
work-mode = "ES7210_NORMAL_I2S";
channels-max = <2>;
mclk-sclk-ratio = <4>;
sound-name-prefix = "ES7210_ADC0";
MVDD-supply = <&soc_aud_adc_3v3_en_reg>;
AVDD-supply = <&soc_aud_adc_3v3_en_reg>;
DVDD-supply = <&soc_dvdd18_aon_reg>;
PVDD-supply = <&soc_dvdd18_aon_reg>;
};
es7210_audio_codec_adc1: es7210@41 {
#sound-dai-cells = <0>;
compatible = "MicArray_1";
reg = <0x41>;
status = "disabled";
work-mode = "ES7210_NORMAL_I2S";
channels-max = <2>;
mclk-sclk-ratio = <4>;
sound-name-prefix = "ES7210_ADC1";
MVDD-supply = <&soc_aud_adc_3v3_en_reg>;
AVDD-supply = <&soc_aud_adc_3v3_en_reg>;
DVDD-supply = <&soc_dvdd18_aon_reg>;
PVDD-supply = <&soc_dvdd18_aon_reg>;
};
audio_aw87519_pa: amp@58 {
compatible = "awinic,aw87519_pa";
reg = <0x58>;
reset-gpio = <&pcal6408ahk_b 3 0x1>;
sound-name-prefix = "AW87519";
status = "okay";
};
};
&audio_i2c1 {
clock-frequency = <100000>;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_audiopa13>,
<&pinctrl_audiopa16>,
<&pinctrl_audio_i2c1>;
pcal6408ahk_b: gpio@20 {
compatible = "nxp,pcal9554b";
reg = <0x20>;
gpio-controller;
#gpio-cells = <2>;
};
};
&i2c1 {
clock-frequency = <400000>;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
touch1@5d {
#gpio-cells = <2>;
compatible = "goodix,gt911";
@@ -582,7 +684,7 @@
irq-gpios = <&gpio1_porta 12 0>;
reset-gpios = <&gpio1_porta 11 0>;
AVDD28-supply = <&reg_tp1_pwr_en>;
touchscreen-size-x = <720>;
touchscreen-size-x = <800>;
touchscreen-size-y = <1280>;
};
};
@@ -591,9 +693,9 @@
num-cs = <1>;
cs-gpios = <&gpio2_porta 15 0>; // GPIO_ACTIVE_HIGH: 0
rx-sample-delay-ns = <10>;
status = "okay";
spi_norflash@0 {
status = "okay";
#address-cells = <1>;
#size-cells = <1>;
compatible = "winbond,w25q64jwm", "jedec,spi-nor";
@@ -603,6 +705,7 @@
};
spidev@1 {
status = "disable";
compatible = "spidev";
#address-cells = <0x1>;
#size-cells = <0x1>;
@@ -613,13 +716,30 @@
&uart0 {
clock-frequency = <100000000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart0>;
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
};
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
};
&uart4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart4>;
};
&qspi0 {
num-cs = <1>;
cs-gpios = <&gpio2_porta 3 0>;
rx-sample-dly = <4>;
status = "disabled";
rx-sample-dly = <5>;
status = "okay";
spi-flash@0 {
#address-cells = <1>;
@@ -640,7 +760,8 @@
&qspi1 {
num-cs = <1>;
cs-gpios = <&gpio0_porta 1 0>;
status = "disabled";
rx-sample-dly = <5>;
status = "okay";
spi-flash@0 {
#address-cells = <1>;
@@ -663,6 +784,8 @@
rx-clk-delay = <0x00>; /* for RGMII */
tx-clk-delay = <0x00>; /* for RGMII */
phy-handle = <&phy_88E1111_0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gmac0>;
status = "okay";
mdio0 {
@@ -685,6 +808,8 @@
rx-clk-delay = <0x00>; /* for RGMII */
tx-clk-delay = <0x00>; /* for RGMII */
phy-handle = <&phy_88E1111_1>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gmac1>;
status = "okay";
};
@@ -706,6 +831,8 @@
bus-width = <4>;
pull_up;
wprtn_ignore;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sdio0>;
status = "okay";
};
@@ -717,6 +844,7 @@
no-mmc;
non-removable;
io_fixed_1v8;
rxclk-sample-delay = <80>;
post-power-on-delay-ms = <50>;
wprtn_ignore;
cap-sd-highspeed;
@@ -733,17 +861,8 @@
*/
pinctrl_uart0: uart0grp {
thead,pins = <
FM_UART0_TXD 0x0 0x72
FM_UART0_RXD 0x0 0x72
>;
};
pinctrl_spi0: spi0grp {
thead,pins = <
FM_SPI_CSN 0x3 0x20a
FM_SPI_SCLK 0x0 0x20a
FM_SPI_MISO 0x0 0x23a
FM_SPI_MOSI 0x0 0x23a
FM_UART0_TXD 0x0 0x234
FM_UART0_RXD 0x0 0x234
>;
};
@@ -759,7 +878,7 @@
>;
};
pinctrl_audio_i2s0: i2s0grp {
pinctrl_light_i2s0: i2s0grp {
thead,pins = <
FM_QSPI0_SCLK 0x2 0x208
FM_QSPI0_CSN0 0x2 0x238
@@ -771,12 +890,87 @@
>;
};
pinctrl_i2c2: i2c2grp {
thead,pins = <
FM_I2C2_SCL 0x0 0x204
FM_I2C2_SDA 0x0 0x204
>;
};
pinctrl_i2c3: i2c3grp {
thead,pins = <
FM_I2C3_SCL 0x0 0x204
FM_I2C3_SDA 0x0 0x204
>;
};
pinctrl_spi0: spi0grp {
thead,pins = <
FM_SPI_CSN 0x3 0x20a
FM_SPI_SCLK 0x0 0x20a
FM_SPI_MISO 0x0 0x23a
FM_SPI_MOSI 0x0 0x23a
>;
};
pinctrl_gmac1: gmac1grp {
thead,pins = <
FM_GPIO2_18 0x1 0x20f /* GMAC1_TX_CLK */
FM_GPIO2_19 0x1 0x20f /* GMAC1_RX_CLK */
FM_GPIO2_20 0x1 0x20f /* GMAC1_TXEN */
FM_GPIO2_21 0x1 0x20f /* GMAC1_TXD0 */
FM_GPIO2_22 0x1 0x20f /* GMAC1_TXD1 */
FM_GPIO2_23 0x1 0x20f /* GMAC1_TXD2 */
FM_GPIO2_24 0x1 0x20f /* GMAC1_TXD3 */
FM_GPIO2_25 0x1 0x20f /* GMAC1_RXDV */
FM_GPIO2_30 0x1 0x20f /* GMAC1_RXD0 */
FM_GPIO2_31 0x1 0x20f /* GMAC1_RXD1 */
FM_GPIO3_0 0x1 0x20f /* GMAC1_RXD2 */
FM_GPIO3_1 0x1 0x20f /* GMAC1_RXD3 */
>;
};
pinctrl_sdio0: sdio0grp {
thead,pins = <
FM_SDIO0_DETN 0x0 0x208
>;
};
pinctrl_pwm: pwmgrp {
thead,pins = <
FM_GPIO3_2 0x1 0x208 /* pwm0 */
FM_GPIO3_3 0x1 0x208 /* pwm1 */
>;
};
pinctrl_hdmi: hdmigrp {
thead,pins = <
FM_HDMI_SCL 0x0 0x208
FM_HDMI_SDA 0x0 0x208
FM_HDMI_CEC 0x0 0x208
>;
};
pinctrl_gmac0: gmac0grp {
thead,pins = <
FM_GMAC0_TX_CLK 0x0 0x20f /* GMAC0_TX_CLK */
FM_GMAC0_RX_CLK 0x0 0x20f /* GMAC0_RX_CLK */
FM_GMAC0_TXEN 0x0 0x20f /* GMAC0_TXEN */
FM_GMAC0_TXD0 0x0 0x20f /* GMAC0_TXD0 */
FM_GMAC0_TXD1 0x0 0x20f /* GMAC0_TXD1 */
FM_GMAC0_TXD2 0x0 0x20f /* GMAC0_TXD2 */
FM_GMAC0_TXD3 0x0 0x20f /* GMAC0_TXD3 */
FM_GMAC0_RXDV 0x0 0x20f /* GMAC0_RXDV */
FM_GMAC0_RXD0 0x0 0x20f /* GMAC0_RXD0 */
FM_GMAC0_RXD1 0x0 0x20f /* GMAC0_RXD1 */
FM_GMAC0_RXD2 0x0 0x20f /* GMAC0_RXD2 */
FM_GMAC0_RXD3 0x0 0x20f /* GMAC0_RXD3 */
FM_GMAC0_MDC 0x0 0x208 /* GMAC0_MDC */
FM_GMAC0_MDIO 0x0 0x208 /* GMAC0_MDIO */
FM_GMAC0_COL 0x3 0x232 /* PHY0_nRST */
FM_GMAC0_CRS 0x3 0x232 /* PHY0_nINT */
>;
};
};
};
@@ -786,22 +980,6 @@
* Pin Configuration Node:
* Format: <pin_id mux_node config>
*/
pinctrl_uart3: uart3grp {
thead,pins = <
FM_UART3_TXD 0x0 0x72
FM_UART3_RXD 0x0 0x72
>;
};
pinctrl_uart4: uart4grp {
thead,pins = <
FM_UART4_TXD 0x0 0x72
FM_UART4_RXD 0x0 0x72
FM_UART4_CTSN 0x0 0x72
FM_UART4_RTSN 0x0 0x72
>;
};
pinctrl_qspi1: qspi1grp {
thead,pins = <
FM_QSPI1_SCLK 0x0 0x20a
@@ -813,7 +991,6 @@
>;
};
pinctrl_iso7816: iso7816grp {
thead,pins = <
FM_QSPI1_SCLK 0x1 0x208
@@ -824,6 +1001,51 @@
>;
};
pinctrl_i2c0: i2c0grp {
thead,pins = <
FM_I2C0_SCL 0x0 0x204
FM_I2C0_SDA 0x0 0x204
>;
};
pinctrl_i2c1: i2c1grp {
thead,pins = <
FM_I2C1_SCL 0x0 0x204
FM_I2C1_SDA 0x0 0x204
>;
};
pinctrl_uart1: uart1grp {
thead,pins = <
FM_UART1_TXD 0x0 0x234
FM_UART1_RXD 0x0 0x234
>;
};
pinctrl_uart4: uart4grp {
thead,pins = <
FM_UART4_TXD 0x0 0x208
FM_UART4_RXD 0x0 0x208
FM_UART4_CTSN 0x0 0x208
FM_UART4_RTSN 0x0 0x208
>;
};
pinctrl_uart3: uart3grp {
thead,pins = <
FM_UART3_TXD 0x1 0x202
FM_UART3_RXD 0x1 0x202
FM_GPIO0_20 0x2 0x202 /* UART3_IR_OUT */
FM_GPIO0_21 0x2 0x202 /* UART3_IR_IN */
>;
};
pinctrl_i2c4: i2c4grp {
thead,pins = <
FM_GPIO0_18 0x1 0x204 /* I2C4_SCL */
FM_GPIO0_19 0x1 0x204 /* I2C4_SDA */
>;
};
};
};
@@ -834,22 +1056,151 @@
* Format: <pin_id mux_node config>
*/
pinctrl_audiopa1: audiopa1_grp {
thead,pins = <
FM_AUDIO_PA1 0x3 0x72
>;
pinctrl_audiopa0: audiopa0 {
thead,pins = < FM_AUDIO_PA0 LIGHT_PIN_FUNC_0 0x000 >;
};
pinctrl_audiopa2: audiopa2_grp {
thead,pins = <
FM_AUDIO_PA2 0x0 0x72
>;
pinctrl_audiopa1: audiopa1 {
thead,pins = < FM_AUDIO_PA1 LIGHT_PIN_FUNC_0 0x000 >;
};
pinctrl_audiopa2: audiopa2 {
thead,pins = < FM_AUDIO_PA2 LIGHT_PIN_FUNC_0 0x000 >;
};
pinctrl_audiopa3: audiopa3 {
thead,pins = < FM_AUDIO_PA3 LIGHT_PIN_FUNC_0 0x000 >;
};
pinctrl_audiopa4: audiopa4 {
thead,pins = < FM_AUDIO_PA4 LIGHT_PIN_FUNC_0 0x000 >;
};
pinctrl_audiopa5: audiopa5 {
thead,pins = < FM_AUDIO_PA5 LIGHT_PIN_FUNC_0 0x000 >;
};
pinctrl_audiopa6: audiopa6 {
thead,pins = < FM_AUDIO_PA6 LIGHT_PIN_FUNC_0 0x000 >;
};
pinctrl_audiopa7: audiopa7 {
thead,pins = < FM_AUDIO_PA7 LIGHT_PIN_FUNC_0 0x000 >;
};
pinctrl_audiopa8: audiopa8 {
thead,pins = < FM_AUDIO_PA8 LIGHT_PIN_FUNC_0 0x000 >;
};
pinctrl_audiopa9: audiopa9 {
thead,pins = < FM_AUDIO_PA9 LIGHT_PIN_FUNC_0 0x000 >;
};
pinctrl_audiopa10: audiopa10 {
thead,pins = < FM_AUDIO_PA10 LIGHT_PIN_FUNC_0 0x000 >;
};
pinctrl_audiopa11: audiopa11 {
thead,pins = < FM_AUDIO_PA11 LIGHT_PIN_FUNC_0 0x000 >;
};
pinctrl_audiopa12: audiopa12 {
thead,pins = < FM_AUDIO_PA12 LIGHT_PIN_FUNC_0 0x000 >;
};
pinctrl_audiopa13: audiopa13 {
thead,pins = < FM_AUDIO_PA13 LIGHT_PIN_FUNC_0 0x000 >;
};
pinctrl_audiopa14: audiopa14 {
thead,pins = < FM_AUDIO_PA14 LIGHT_PIN_FUNC_0 0x000 >;
};
pinctrl_audiopa15: audiopa15 {
thead,pins = < FM_AUDIO_PA15 LIGHT_PIN_FUNC_0 0x000 >;
};
pinctrl_audiopa16: audiopa16 {
thead,pins = < FM_AUDIO_PA16 LIGHT_PIN_FUNC_0 0x000 >;
};
pinctrl_audiopa17: audiopa17 {
thead,pins = < FM_AUDIO_PA17 LIGHT_PIN_FUNC_0 0x000 >;
};
pinctrl_volume: volume_grp {
thead,pins = <
FM_CPU_JTG_TDI 0x3 0x208
FM_CPU_JTG_TDO 0x3 0x208
FM_CPU_JTG_TDI 0x3 0x238
FM_CPU_JTG_TDO 0x3 0x238
>;
};
};
};
&padctrl_audiosys {
status = "okay";
light-audio-padctrl {
/*
* Pin Configuration Node:
* Format: <pin_id mux_node config>
*/
pinctrl_audio_i2c0: audio_i2c0_grp {
thead,pins = <
FM_AUDIO_IO_PA6 LIGHT_PIN_FUNC_0 0x004
FM_AUDIO_IO_PA7 LIGHT_PIN_FUNC_0 0x004
>;
};
pinctrl_audio_i2c1: audio_i2c1_grp {
thead,pins = <
FM_AUDIO_IO_PA13 LIGHT_PIN_FUNC_1 0x004
FM_AUDIO_IO_PA16 LIGHT_PIN_FUNC_3 0x004
>;
};
pinctrl_audio_i2s0: audio_i2s0_grp {
thead,pins = <
FM_AUDIO_IO_PA9 LIGHT_PIN_FUNC_0 0x008
FM_AUDIO_IO_PA10 LIGHT_PIN_FUNC_0 0x008
FM_AUDIO_IO_PA11 LIGHT_PIN_FUNC_0 0x008
FM_AUDIO_IO_PA12 LIGHT_PIN_FUNC_0 0x008
>;
};
pinctrl_audio_i2s1: audio_i2s1_grp {
thead,pins = <
FM_AUDIO_IO_PA14 LIGHT_PIN_FUNC_0 0x008
FM_AUDIO_IO_PA15 LIGHT_PIN_FUNC_0 0x008
FM_AUDIO_IO_PA17 LIGHT_PIN_FUNC_0 0x008
>;
};
pinctrl_audio_i2s_8ch_bus: audio_i2s_8ch_bus_grp {
thead,pins = <
FM_AUDIO_IO_PA2 LIGHT_PIN_FUNC_3 0x008
FM_AUDIO_IO_PA3 LIGHT_PIN_FUNC_3 0x008
FM_AUDIO_IO_PA8 LIGHT_PIN_FUNC_3 0x008
>;
};
pinctrl_audio_i2s_8ch_sd0: audio_i2s_8ch_sd0_grp {
thead,pins = <
FM_AUDIO_IO_PA4 LIGHT_PIN_FUNC_3 0x008
>;
};
pinctrl_audio_i2s_8ch_sd1: audio_i2s_8ch_sd1_grp {
thead,pins = <
FM_AUDIO_IO_PA5 LIGHT_PIN_FUNC_3 0x008
>;
};
pinctrl_audio_i2s_8ch_sd2: audio_i2s_8ch_sd2_grp {
thead,pins = <
FM_AUDIO_IO_PA0 LIGHT_PIN_FUNC_3 0x008
>;
};
pinctrl_audio_i2s_8ch_sd3: audio_i2s_8ch_sd3_grp {
thead,pins = <
FM_AUDIO_IO_PA1 LIGHT_PIN_FUNC_3 0x008
>;
};
pinctrl_audio_tdm: audio_tdm_grp {
thead,pins = <
FM_AUDIO_IO_PA27 LIGHT_PIN_FUNC_1 0x007
FM_AUDIO_IO_PA28 LIGHT_PIN_FUNC_1 0x007
FM_AUDIO_IO_PA29 LIGHT_PIN_FUNC_1 0x000
>;
};
pinctrl_audio_spdif0: audio_spdif0_grp {
thead,pins = <
FM_AUDIO_IO_PA21 LIGHT_PIN_FUNC_1 0x000
FM_AUDIO_IO_PA22 LIGHT_PIN_FUNC_1 0x007
>;
};
pinctrl_audio_spdif1: audio_spdif1_grp {
thead,pins = <
FM_AUDIO_IO_PA23 LIGHT_PIN_FUNC_1 0x007
FM_AUDIO_IO_PA24 LIGHT_PIN_FUNC_1 0x000
>;
};
};
@@ -858,6 +1209,8 @@
&i2c2 {
clock-frequency = <400000>;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
eeprom@50 {
compatible = "atmel,24c32";
reg = <0x50>;
@@ -868,6 +1221,8 @@
&i2c3 {
clock-frequency = <400000>;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
eeprom@50 {
compatible = "atmel,24c32";
reg = <0x50>;
@@ -878,6 +1233,8 @@
&i2c4 {
clock-frequency = <400000>;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c4>;
eeprom@50 {
compatible = "atmel,24c32";
reg = <0x50>;
@@ -989,6 +1346,24 @@
status = "disabled";
};
&vvcam_sensor1 {
sensor_name = "OV5693";
sensor_regulators = "DOVDD18_RGB", "DVDD12_RGB", "AVDD28_RGB";
sensor_regulator_voltage_uV = <1800000 1200000 2800000>;
sensor_regulator_timing_us = <70 50 20>;
sensor_rst = <&gpio1_porta 16 0>;
sensor_pdn_delay_us = <4000>; //powerdown pin / shutdown pin actived till I2C ready
DOVDD18_RGB-supply = <&soc_dovdd18_rgb_reg>;
DVDD12_RGB-supply = <&soc_dvdd12_rgb_reg>;
AVDD28_RGB-supply = <&soc_avdd28_rgb_reg>;
i2c_reg_width = /bits/ 8 <2>;
i2c_data_width = /bits/ 8 <1>;
i2c_addr = /bits/ 8 <0x36>;
i2c_bus = /bits/ 8 <3>;
status = "okay";
};
&vvcam_sensor2 {
sensor_name = "GC5035";
sensor_regulators = "DOVDD18_SCAN", "DVDD12_SCAN", "AVDD28_SCAN";
@@ -1017,6 +1392,9 @@
DVDD12_SCAN-supply = <&soc_dvdd12_scan_reg>;
AVDD28_SCAN-supply = <&soc_avdd28_scan_en_reg>;
i2c_bus = /bits/ 8 <4>;
i2c_reg_width = /bits/ 8 <2>;
i2c_data_width = /bits/ 8 <1>;
i2c_addr = /bits/ 8 <0x30>;
status = "okay";
};
@@ -1070,7 +1448,24 @@
status = "okay";
};
&vvcam_sensor7 {
sensor_name = "IMX334";
sensor_regulators = "DOVDD18_RGB", "DVDD12_RGB", "AVDD28_RGB";
sensor_regulator_timing_us = <70 50 20>;
sensor_rst = <&gpio1_porta 16 0>;
sensor_pdn_delay_us = <1000>; //powerdown pin / shutdown pin actived till I2C ready
DOVDD18_RGB-supply = <&soc_dovdd18_rgb_reg>;
DVDD12_RGB-supply = <&soc_dvdd12_rgb_reg>;
AVDD28_RGB-supply = <&soc_avdd28_rgb_reg>;
i2c_reg_width = /bits/ 8 <2>;
i2c_data_width = /bits/ 8 <1>;
i2c_addr = /bits/ 8 <0x1a>;
i2c_bus = /bits/ 8 <3>;
status = "okay";
};
&video0{
status = "okay";
vi_mem_pool_region = <2>; // vi_mem: framebuffer, region[2]
channel0 {
sensor0 {
@@ -1157,6 +1552,7 @@
&video1{
status = "okay";
vi_mem_pool_region = <2>; // vi_mem: framebuffer, region[2]
channel0 {
sensor0 {
@@ -1260,6 +1656,7 @@
};
&video2{
status = "okay";
vi_mem_pool_region = <0>; // vi_mem: framebuffer, region[0]
channel0 {
sensor0 {
@@ -1276,13 +1673,20 @@
mode_idx = <0>;
path_type = "SENSOR_1600x1200_RAW10_LINER";
};
sensor2 {
subdev_name = "vivcam";
idx = <7>; //imx334
csi_idx = <0>; //<0>=CSI2
mode_idx = <0>;
path_type = "SENSOR_3840x2180_RAW12_LINER";
};
isp {
subdev_name = "isp";
idx = <1>;
path_type = "ISP_MI_PATH_MP";
output {
max_width = <1920>;
max_height = <1088>;
max_width = <3840>;
max_height = <2180>;
bit_per_pixel = <16>;
frame_count = <3>;
};
@@ -1345,6 +1749,7 @@
};
&video3{
status = "okay";
vi_mem_pool_region = <0>; // vi_mem: framebuffer, region[0]
channel0 {
sensor0 {
@@ -1448,6 +1853,7 @@
};
&video4{
status = "okay";
vi_mem_pool_region = <0>; // vi_mem: framebuffer, region[0]
channel0 {
sensor0 {
@@ -1599,6 +2005,7 @@
};
&video5{
status = "okay";
vi_mem_pool_region = <0>; // vi_mem: framebuffer, region[0]
channel0 {
sensor0 {
@@ -1768,6 +2175,7 @@
};
&video6{
status = "okay";
vi_mem_pool_region = <1>; // vi_mem: framebuffer, region[1]
channel0 {
sensor0 {
@@ -1808,6 +2216,7 @@
};
&video7{
status = "okay";
channel0 {
sensor0 {
subdev_name = "vivcam";
@@ -1977,6 +2386,7 @@
&video8{
status = "okay";
vi_mem_pool_region = <1>; // vi_mem: framebuffer, region[1]
channel0 {
sensor0 {
@@ -2008,6 +2418,7 @@
};
&video9{
status = "okay";
channel0 {
sensor0 {
subdev_name = "vivcam";
@@ -2029,6 +2440,7 @@
&video10{
status = "okay";
channel0 {
sensor0 {
subdev_name = "vivcam";
@@ -2050,6 +2462,7 @@
};
&video11{
status = "okay";
channel0 {
channel_id = <0>;
status = "okay";
@@ -2076,6 +2489,7 @@
};
&video12{ // TUNINGTOOL
status = "okay";
channel0 { // CSI2
sensor0 {
subdev_name = "vivcam";
@@ -2096,6 +2510,35 @@
};
};
&video15{
status = "okay";
vi_mem_pool_region = <0>;
channel0 {
channel_id = <0>;
status = "okay";
sensor0 {
subdev_name = "vivcam";
idx = <0>; //<0>=vivcam0 :2310
csi_idx = <0>; //<0>=CSI2
flash_led_idx = <0>;
mode_idx = <1>;
path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER";
};
sensor1 {
subdev_name = "vivcam";
idx = <7>; //imx334
csi_idx = <0>; //<0>=CSI2
mode_idx = <0>;
path_type = "SENSOR_3840x2180_RAW12_LINER";
};
dma {
subdev_name = "vipre";
idx = <0>;
path_type = "VIPRE_CSI0_DDR";
};
};
};
&trng {
status = "disabled";
};
@@ -2135,6 +2578,44 @@
status = "okay";
};
&i2s0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_audiopa9>,
<&pinctrl_audiopa10>,
<&pinctrl_audiopa11>,
<&pinctrl_audiopa12>,
<&pinctrl_audio_i2s0>;
};
&i2s_8ch_sd0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_audiopa4>,
<&pinctrl_audio_i2s_8ch_sd0>;
};
&i2s_8ch_sd1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_audiopa5>,
<&pinctrl_audio_i2s_8ch_sd1>;
};
&i2s_8ch_sd2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_audiopa0>,
<&pinctrl_audio_i2s_8ch_sd2>,
<&pinctrl_audiopa2>,
<&pinctrl_audiopa3>,
<&pinctrl_audiopa8>,
<&pinctrl_audio_i2s_8ch_bus>;
};
&i2s_8ch_sd3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_audiopa1>,
<&pinctrl_audio_i2s_8ch_sd3>;
};
&cpus {
c910_0: cpu@0 {
operating-points = <
@@ -2203,3 +2684,8 @@
>;
};
};
&hdmi_tx {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hdmi>;
};

52
arch/riscv/boot/dts/thead/light-ant-discrete.dts
View File

@@ -15,7 +15,7 @@
memory@0 {
device_type = "memory";
reg = <0x0 0x00000000 0x0 0x80000000>;
reg = <0x0 0x200000 0x0 0x7fe00000>;
};
chosen {
@@ -194,9 +194,10 @@
};
dummy_codec: dummy_codec {
#sound-dai-cells = <1>;
compatible = "linux,bt-sco";
#sound-dai-cells = <0>;
compatible = "thead,light-dummy-pcm";
status = "okay";
sound-name-prefix = "DUMMY";
};
reg_vref_1v8: regulator-adc-verf {
@@ -571,7 +572,7 @@
irq-gpios = <&gpio1_porta 8 0>;
reset-gpios = <&gpio1_porta 7 0>;
AVDD28-supply = <&reg_tp_pwr_en>;
touchscreen-size-x = <720>;
touchscreen-size-x = <800>;
touchscreen-size-y = <1280>;
};
@@ -581,24 +582,31 @@
clock-frequency = <100000>;
status = "okay";
es8156_audio_codec: es8156@8 {
#sound-dai-cells = <0>;
compatible = "everest,es8156";
reg = <0x08>;
};
es8156_audio_codec: es8156@8 {
#sound-dai-cells = <0>;
compatible = "everest,es8156";
reg = <0x08>;
sound-name-prefix = "ES8156";
AVDD-supply = <&soc_aud_3v3_en_reg>;
DVDD-supply = <&soc_aud_1v8_en_reg>;
PVDD-supply = <&soc_aud_1v8_en_reg>;
};
es7210_audio_codec: es7210@40 {
#sound-dai-cells = <0>;
compatible = "MicArray_0";
reg = <0x40>;
sound-name-prefix = "ES7210";
status = "disabled";
};
audio_aw87519_pa@58 {
compatible = "awinic,aw87519_pa";
reg = <0x58>;
reset-gpio = <&ao_gpio4_porta 9 0x1>;
status = "okay";
};
audio_aw87519_pa: amp@58 {
compatible = "awinic,aw87519_pa";
reg = <0x58>;
reset-gpio = <&ao_gpio4_porta 9 0x1>;
sound-name-prefix = "AW87519";
status = "okay";
};
};
&i2c1 {
@@ -731,6 +739,7 @@
no-mmc;
non-removable;
io_fixed_1v8;
rxclk-sample-delay = <80>;
post-power-on-delay-ms = <50>;
wprtn_ignore;
cap-sd-highspeed;
@@ -773,7 +782,7 @@
>;
};
pinctrl_audio_i2s0: i2s0grp {
pinctrl_light_i2s0: i2s0grp {
thead,pins = <
FM_QSPI0_SCLK 0x2 0x208
FM_QSPI0_CSN0 0x2 0x238
@@ -2091,6 +2100,11 @@
&lightsound {
status = "okay";
simple-audio-card,widgets = "Speaker", "Speaker";
simple-audio-card,routing =
"Speaker", "AW87519 VO",
"AW87519 IN", "ES8156 ROUT";
simple-audio-card,aux-devs = <&audio_aw87519_pa>;
simple-audio-card,dai-link@0 { /* I2S - AUDIO SYS CODEC 8156*/
reg = <0>;
format = "i2s";
@@ -2105,7 +2119,7 @@
reg = <1>;
format = "i2s";
cpu {
sound-dai = <&i2s3 0>;
sound-dai = <&i2s_8ch_sd2 2>;
};
codec {
sound-dai = <&es7210_audio_codec>;
@@ -2118,7 +2132,7 @@
sound-dai = <&light_i2s 1>;
};
codec {
sound-dai = <&dummy_codec 2>;
sound-dai = <&dummy_codec>;
};
};
};
@@ -2135,7 +2149,7 @@
status = "okay";
};
&i2s3 {
&i2s_8ch_sd2 {
status = "okay";
};

89
arch/riscv/boot/dts/thead/light-ant-ref.dts
View File

@@ -15,7 +15,7 @@
memory@0 {
device_type = "memory";
reg = <0x0 0x00000000 0x0 0x80000000>;
reg = <0x0 0x200000 0x0 0x7fe00000>;
};
chosen {
@@ -166,6 +166,14 @@
iopmp_dsp1: IOPMP_DSP1 {
is_default_region;
};
iopmp_audio0: IOPMP_AUDIO0 {
is_default_region;
};
iopmp_audio1: IOPMP_AUDIO1 {
is_default_region;
};
};
mbox_910t_client1: mbox_910t_client1 {
@@ -194,9 +202,10 @@
};
dummy_codec: dummy_codec {
#sound-dai-cells = <1>;
compatible = "linux,bt-sco";
#sound-dai-cells = <0>;
compatible = "thead,light-dummy-pcm";
status = "okay";
sound-name-prefix = "DUMMY";
};
reg_vref_1v8: regulator-adc-verf {
@@ -238,7 +247,8 @@
gpio-keys {
compatible = "gpio-keys";
pinctrl-0 = <&pinctrl_volume>;
pinctrl-0 = <&pinctrl_volume_up
&pinctrl_volume_down>;
pinctrl-names = "default";
key-volumedown {
label = "Volume Down Key";
@@ -578,7 +588,7 @@
irq-gpios = <&gpio1_porta 8 0>;
reset-gpios = <&gpio1_porta 7 0>;
AVDD28-supply = <&reg_tp_pwr_en>;
touchscreen-size-x = <720>;
touchscreen-size-x = <800>;
touchscreen-size-y = <1280>;
};
@@ -588,24 +598,31 @@
clock-frequency = <100000>;
status = "okay";
es8156_audio_codec: es8156@8 {
#sound-dai-cells = <0>;
compatible = "everest,es8156";
reg = <0x08>;
};
es8156_audio_codec: es8156@8 {
#sound-dai-cells = <0>;
compatible = "everest,es8156";
reg = <0x08>;
sound-name-prefix = "ES8156";
AVDD-supply = <&soc_aud_3v3_en_reg>;
DVDD-supply = <&soc_aud_1v8_en_reg>;
PVDD-supply = <&soc_aud_1v8_en_reg>;
};
es7210_audio_codec: es7210@40 {
#sound-dai-cells = <0>;
compatible = "MicArray_0";
reg = <0x40>;
sound-name-prefix = "ES7210";
status = "disabled";
};
audio_aw87519_pa@58 {
compatible = "awinic,aw87519_pa";
reg = <0x58>;
reset-gpio = <&ao_gpio4_porta 9 0x1>;
status = "okay";
};
audio_aw87519_pa: amp@58 {
compatible = "awinic,aw87519_pa";
reg = <0x58>;
reset-gpio = <&ao_gpio4_porta 9 0x1>;
sound-name-prefix = "AW87519";
status = "okay";
};
};
&i2c1 {
@@ -738,6 +755,7 @@
no-mmc;
non-removable;
io_fixed_1v8;
rxclk-sample-delay = <80>;
post-power-on-delay-ms = <50>;
wprtn_ignore;
cap-sd-highspeed;
@@ -780,7 +798,7 @@
>;
};
pinctrl_audio_i2s0: i2s0grp {
pinctrl_light_i2s0: i2s0grp {
thead,pins = <
FM_QSPI0_SCLK 0x2 0x208
FM_QSPI0_CSN0 0x2 0x238
@@ -797,6 +815,12 @@
FM_GPIO3_2 0x1 0x208 /* pwm0 */
>;
};
pinctrl_volume_up: volume_up_grp {
thead,pins = <
FM_GPIO2_25 0x0 0x238
>;
};
};
};
@@ -842,9 +866,9 @@
>;
};
pinctrl_volume: volume_grp {
pinctrl_volume_down: volume_down_grp {
thead,pins = <
FM_CLK_OUT_2 0x3 0x208
FM_CLK_OUT_2 0x3 0x238
>;
};
};
@@ -2048,18 +2072,11 @@
path_type = "SENSOR_1920X1088_30FPS_RAW12_LINER";
skip_init = <1>;
};
sensor1 {
subdev_name = "vivcam";
idx = <6>; //gc02m1b
csi_idx = <1>; //<1>=CSI2_B
mode_idx = <0>;
path_type = "SENSOR_1600x1200_RAW10_LINER";
skip_init = <1>;
dma {
path_type = "VIPRE_CSI1_ISP0";
};
};
dma {
path_type = "VIPRE_CSI1_ISP0";
};
};
&video13{
@@ -2262,6 +2279,9 @@
&hdmi_tx {
status = "okay";
max_width = /bits/ 16 <1280>;
max_height = /bits/ 16 <720>;
port@0 {
/* input */
hdmi_tx_in: endpoint {
@@ -2272,6 +2292,11 @@
&lightsound {
status = "okay";
simple-audio-card,widgets = "Speaker", "Speaker";
simple-audio-card,routing =
"Speaker", "AW87519 VO",
"AW87519 IN", "ES8156 ROUT";
simple-audio-card,aux-devs = <&audio_aw87519_pa>;
simple-audio-card,dai-link@0 { /* I2S - AUDIO SYS CODEC 8156*/
reg = <0>;
format = "i2s";
@@ -2286,7 +2311,7 @@
reg = <1>;
format = "i2s";
cpu {
sound-dai = <&i2s3 0>;
sound-dai = <&i2s_8ch_sd2 2>;
};
codec {
sound-dai = <&es7210_audio_codec>;
@@ -2299,7 +2324,7 @@
sound-dai = <&light_i2s 1>;
};
codec {
sound-dai = <&dummy_codec 2>;
sound-dai = <&dummy_codec>;
};
};
};
@@ -2316,7 +2341,7 @@
status = "okay";
};
&i2s3 {
&i2s_8ch_sd2 {
status = "okay";
};

2525
arch/riscv/boot/dts/thead/light-b-audio-hdmi.dts Normal file
View File

File diff suppressed because it is too large Load Diff

2
arch/riscv/boot/dts/thead/light-b-product-ddr1G.dts
View File

@@ -11,7 +11,7 @@
memory@0 {
device_type = "memory";
reg = <0x0 0x00000000 0x0 0x40000000>;
reg = <0x0 0x200000 0x0 0x3fe00000>;
};
};

2
arch/riscv/boot/dts/thead/light-b-product-sec.dts
View File

@@ -5,7 +5,7 @@
/dts-v1/;
#include "light-b-product.dts"
#include "light-b-audio-hdmi.dts"

464
arch/riscv/boot/dts/thead/light-b-product.dts
View File

@@ -15,7 +15,7 @@
memory@0 {
device_type = "memory";
reg = <0x0 0x00000000 0x0 0x80000000>;
reg = <0x0 0x200000 0x0 0x7fe00000>;
};
chosen {
@@ -166,6 +166,14 @@
iopmp_dsp1: IOPMP_DSP1 {
is_default_region;
};
iopmp_audio0: IOPMP_AUDIO0 {
is_default_region;
};
iopmp_audio1: IOPMP_AUDIO1 {
is_default_region;
};
};
mbox_910t_client1: mbox_910t_client1 {
@@ -180,7 +188,8 @@
compatible = "thead,light-mbox-client";
mbox-names = "906";
mboxes = <&mbox_910t 2 0>;
status = "disabled";
audio-mbox-regmap = <&audio_mbox>;
status = "okay";
};
lightsound: lightsound@1 {
@@ -193,10 +202,25 @@
status = "disabled";
};
light_rpmsg: light_rpmsg {
compatible = "light,rpmsg-bus", "simple-bus";
memory-region = <&rpmsgmem>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
rpmsg: rpmsg{
vdev-nums = <1>;
reg = <0x0 0x1E000000 0 0x10000>;
compatible = "light,light-rpmsg";
status = "okay";
};
};
dummy_codec: dummy_codec {
#sound-dai-cells = <1>;
compatible = "linux,bt-sco";
#sound-dai-cells = <0>;
compatible = "thead,light-dummy-pcm";
status = "okay";
sound-name-prefix = "DUMMY";
};
reg_vref_1v8: regulator-adc-verf {
@@ -223,6 +247,7 @@
ref-clock-frequency = <24000000>;
keep_wifi_power_on;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wifi>;
wifi_chip_type = "rtl8723ds";
WIFI,poweren_gpio = <&gpio2_porta 29 0>;
WIFI,reset_n = <&gpio2_porta 24 0>;
@@ -231,7 +256,8 @@
wcn_bt: wireless-bluetooth {
compatible = "bluetooth-platdata";
pinctrl-names = "default", "rts_gpio";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_bt>;
BT,power_gpio = <&gpio2_porta 25 0>;
status = "okay";
};
@@ -242,12 +268,14 @@
pinctrl-names = "default";
key-volumedown {
label = "Volume Down Key";
wakeup-source;
linux,code = <KEY_VOLUMEDOWN>;
debounce-interval = <1>;
gpios = <&ao_gpio_porta 11 0x1>;
};
key-volumeup {
label = "Volume Up Key";
wakeup-source;
linux,code = <KEY_VOLUMEUP>;
debounce-interval = <1>;
gpios = <&ao_gpio_porta 10 0x1>;
@@ -270,6 +298,8 @@
regulator-name = "soc_aud_3v3_en";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_audio_3v3_en>;
gpio = <&ao_gpio_porta 7 1>;
enable-active-high;
regulator-always-on;
@@ -280,6 +310,8 @@
regulator-name = "soc_aud_1v8_en";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_audio_1v8_en>;
gpio = <&ao_gpio_porta 8 1>;
enable-active-high;
regulator-always-on;
@@ -569,7 +601,14 @@
reg = <0x0 0x17000000 0 0x02000000>;
no-map;
};
audio_mem: memory@32000000 {
reg = <0x0 0x32000000 0x0 0x6400000>;
no-map;
};
rpmsgmem: memory@1E000000 {
reg = <0x0 0x1E000000 0x0 0x10000>;
no-map;
};
};
@@ -591,7 +630,7 @@
irq-gpios = <&gpio1_porta 8 0>;
reset-gpios = <&gpio1_porta 7 0>;
AVDD28-supply = <&reg_tp_pwr_en>;
touchscreen-size-x = <720>;
touchscreen-size-x = <800>;
touchscreen-size-y = <1280>;
};
@@ -600,23 +639,43 @@
&audio_i2c0 {
clock-frequency = <100000>;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_audiopa6>,
<&pinctrl_audiopa7>,
<&pinctrl_audio_i2c0>;
es8156_audio_codec: es8156@8 {
#sound-dai-cells = <0>;
compatible = "everest,es8156";
reg = <0x08>;
};
es8156_audio_codec: es8156@8 {
#sound-dai-cells = <0>;
compatible = "everest,es8156";
reg = <0x08>;
sound-name-prefix = "ES8156";
AVDD-supply = <&soc_aud_3v3_en_reg>;
DVDD-supply = <&soc_aud_1v8_en_reg>;
PVDD-supply = <&soc_aud_1v8_en_reg>;
mclk-sclk-ratio = <4>;
};
es7210_audio_codec: es7210@40 {
#sound-dai-cells = <0>;
compatible = "MicArray_0";
reg = <0x40>;
work-mode = "ES7210_NORMAL_I2S";
channels-max = <2>;
mclk-sclk-ratio = <4>;
sound-name-prefix = "ES7210_ADC0";
MVDD-supply = <&soc_aud_3v3_en_reg>;
AVDD-supply = <&soc_aud_3v3_en_reg>;
DVDD-supply = <&soc_aud_1v8_en_reg>;
PVDD-supply = <&soc_aud_1v8_en_reg>;
};
audio_aw87519_pa@58 {
audio_aw87519_pa: amp@58 {
compatible = "awinic,aw87519_pa";
reg = <0x58>;
pingctrl-names = "default";
pinctrl-0 = <&pinctrl_audio_pa_rst0>;
reset-gpio = <&ao_gpio4_porta 9 0x1>;
sound-name-prefix = "AW87519";
status = "okay";
};
};
@@ -652,6 +711,23 @@
&uart0 {
clock-frequency = <100000000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart0>;
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
};
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
};
&uart4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart4>;
};
&qspi0 {
@@ -697,6 +773,8 @@
tx-clk-delay = <0x00>; /* for RGMII */
phy-handle = <&phy_88E1111_0>;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gmac0>;
mdio0 {
#address-cells = <1>;
@@ -740,6 +818,8 @@
pull_up;
wprtn_ignore;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sdio0>;
};
&sdhci1 {
@@ -750,6 +830,7 @@
no-mmc;
non-removable;
io_fixed_1v8;
rxclk-sample-delay = <80>;
post-power-on-delay-ms = <50>;
wprtn_ignore;
cap-sd-highspeed;
@@ -766,17 +847,8 @@
*/
pinctrl_uart0: uart0grp {
thead,pins = <
FM_UART0_TXD 0x0 0x72
FM_UART0_RXD 0x0 0x72
>;
};
pinctrl_spi0: spi0grp {
thead,pins = <
FM_SPI_CSN 0x3 0x20a
FM_SPI_SCLK 0x0 0x20a
FM_SPI_MISO 0x0 0x23a
FM_SPI_MOSI 0x0 0x23a
FM_UART0_TXD 0x0 0x234
FM_UART0_RXD 0x0 0x234
>;
};
@@ -792,7 +864,7 @@
>;
};
pinctrl_audio_i2s0: i2s0grp {
pinctrl_light_i2s0: i2s0grp {
thead,pins = <
FM_QSPI0_SCLK 0x2 0x208
FM_QSPI0_CSN0 0x2 0x238
@@ -804,9 +876,81 @@
>;
};
pinctrl_i2c2: i2c2grp {
thead,pins = <
FM_I2C2_SCL 0x0 0x204
FM_I2C2_SDA 0x0 0x204
>;
};
pinctrl_i2c3: i2c3grp {
thead,pins = <
FM_I2C3_SCL 0x0 0x204
FM_I2C3_SDA 0x0 0x204
>;
};
pinctrl_spi0: spi0grp {
thead,pins = <
FM_SPI_CSN 0x3 0x20a
FM_SPI_SCLK 0x0 0x20a
FM_SPI_MISO 0x0 0x23a
FM_SPI_MOSI 0x0 0x23a
>;
};
pinctrl_wifi: wifi_grp {
thead,pins = <
FM_GPIO2_22 0x0 0x202
FM_GPIO2_24 0x0 0x202
>;
};
pinctrl_bt: bt_grp {
thead,pins = <
FM_GPIO2_23 0x0 0x202
FM_GPIO2_25 0x0 0x202
>;
};
pinctrl_sdio0: sdio0grp {
thead,pins = <
FM_SDIO0_DETN 0x0 0x208
>;
};
pinctrl_pwm: pwmgrp {
thead,pins = <
FM_GPIO3_2 0x1 0x208 /* pwm0 */
FM_GPIO3_2 0x1 0x20f /* pwm0 */
>;
};
pinctrl_hdmi: hdmigrp {
thead,pins = <
FM_HDMI_SCL 0x0 0x208
FM_HDMI_SDA 0x0 0x208
FM_HDMI_CEC 0x0 0x208
>;
};
pinctrl_gmac0: gmac0grp {
thead,pins = <
FM_GMAC0_TX_CLK 0x0 0x20f /* GMAC0_TX_CLK */
FM_GMAC0_RX_CLK 0x0 0x20f /* GMAC0_RX_CLK */
FM_GMAC0_TXEN 0x0 0x20f /* GMAC0_TXEN */
FM_GMAC0_TXD0 0x0 0x20f /* GMAC0_TXD0 */
FM_GMAC0_TXD1 0x0 0x20f /* GMAC0_TXD1 */
FM_GMAC0_TXD2 0x0 0x20f /* GMAC0_TXD2 */
FM_GMAC0_TXD3 0x0 0x20f /* GMAC0_TXD3 */
FM_GMAC0_RXDV 0x0 0x20f /* GMAC0_RXDV */
FM_GMAC0_RXD0 0x0 0x20f /* GMAC0_RXD0 */
FM_GMAC0_RXD1 0x0 0x20f /* GMAC0_RXD1 */
FM_GMAC0_RXD2 0x0 0x20f /* GMAC0_RXD2 */
FM_GMAC0_RXD3 0x0 0x20f /* GMAC0_RXD3 */
FM_GMAC0_MDC 0x0 0x208 /* GMAC0_MDC */
FM_GMAC0_MDIO 0x0 0x208 /* GMAC0_MDIO */
FM_GMAC0_COL 0x3 0x232 /* PHY0_nRST */
FM_GMAC0_CRS 0x3 0x232 /* PHY0_nINT */
>;
};
};
@@ -818,22 +962,6 @@
* Pin Configuration Node:
* Format: <pin_id mux_node config>
*/
pinctrl_uart3: uart3grp {
thead,pins = <
FM_UART3_TXD 0x0 0x72
FM_UART3_RXD 0x0 0x72
>;
};
pinctrl_uart4: uart4grp {
thead,pins = <
FM_UART4_TXD 0x0 0x72
FM_UART4_RXD 0x0 0x72
FM_UART4_CTSN 0x0 0x72
FM_UART4_RTSN 0x0 0x72
>;
};
pinctrl_qspi1: qspi1grp {
thead,pins = <
FM_QSPI1_SCLK 0x0 0x20a
@@ -845,7 +973,6 @@
>;
};
pinctrl_iso7816: iso7816grp {
thead,pins = <
FM_QSPI1_SCLK 0x1 0x208
@@ -856,6 +983,49 @@
>;
};
pinctrl_i2c0: i2c0grp {
thead,pins = <
FM_I2C0_SCL 0x0 0x204
FM_I2C0_SDA 0x0 0x204
>;
};
pinctrl_i2c1: i2c1grp {
thead,pins = <
FM_I2C1_SCL 0x0 0x204
FM_I2C1_SDA 0x0 0x204
>;
};
pinctrl_uart1: uart1grp {
thead,pins = <
FM_UART1_TXD 0x0 0x234
FM_UART1_RXD 0x0 0x234
>;
};
pinctrl_uart4: uart4grp {
thead,pins = <
FM_UART4_TXD 0x0 0x208
FM_UART4_RXD 0x0 0x208
FM_UART4_CTSN 0x0 0x208
FM_UART4_RTSN 0x0 0x208
>;
};
pinctrl_uart3: uart3grp {
thead,pins = <
FM_UART3_TXD 0x1 0x202
FM_UART3_RXD 0x1 0x202
>;
};
pinctrl_i2c4: i2c4grp {
thead,pins = <
FM_GPIO0_18 0x1 0x204 /* I2C4_SCL */
FM_GPIO0_19 0x1 0x204 /* I2C4_SDA */
>;
};
};
};
@@ -866,50 +1036,136 @@
* Format: <pin_id mux_node config>
*/
pinctrl_audiopa1: audiopa1_grp {
thead,pins = <
FM_AUDIO_PA1 0x3 0x72
>;
pinctrl_audiopa0: audiopa0 {
thead,pins = < FM_AUDIO_PA0 LIGHT_PIN_FUNC_0 0x000 >;
};
pinctrl_audiopa2: audiopa2_grp {
thead,pins = <
FM_AUDIO_PA2 0x0 0x72
>;
pinctrl_audiopa1: audiopa1 {
thead,pins = < FM_AUDIO_PA1 LIGHT_PIN_FUNC_0 0x000 >;
};
pinctrl_audiopa2: audiopa2 {
thead,pins = < FM_AUDIO_PA2 LIGHT_PIN_FUNC_0 0x000 >;
};
pinctrl_audiopa3: audiopa3 {
thead,pins = < FM_AUDIO_PA3 LIGHT_PIN_FUNC_0 0x000 >;
};
pinctrl_audiopa6: audiopa6 {
thead,pins = < FM_AUDIO_PA6 LIGHT_PIN_FUNC_0 0x000 >;
};
pinctrl_audiopa7: audiopa7 {
thead,pins = < FM_AUDIO_PA7 LIGHT_PIN_FUNC_0 0x000 >;
};
pinctrl_audiopa8: audiopa8 {
thead,pins = < FM_AUDIO_PA8 LIGHT_PIN_FUNC_0 0x000 >;
};
pinctrl_audio_pa_rst0: audio_pa_rst0 {
thead,pins = < FM_AUDIO_PA9 LIGHT_PIN_FUNC_3 0x000 >;
};
pinctrl_audiopa13: audiopa13 {
thead,pins = < FM_AUDIO_PA13 LIGHT_PIN_FUNC_0 0x000 >;
};
pinctrl_audiopa14: audiopa14 {
thead,pins = < FM_AUDIO_PA14 LIGHT_PIN_FUNC_0 0x000 >;
};
pinctrl_audiopa15: audiopa15 {
thead,pins = < FM_AUDIO_PA15 LIGHT_PIN_FUNC_0 0x000 >;
};
pinctrl_audiopa17: audiopa17 {
thead,pins = < FM_AUDIO_PA17 LIGHT_PIN_FUNC_0 0x000 >;
};
pinctrl_audio_3v3_en: audio_3v3_en {
thead,pins = < FM_AOGPIO_7 LIGHT_PIN_FUNC_3 0x008 >;
};
pinctrl_audio_1v8_en: audio_1v8_en {
thead,pins = < FM_AOGPIO_8 LIGHT_PIN_FUNC_3 0x008 >;
};
pinctrl_volume: volume_grp {
thead,pins = <
FM_AOGPIO_11 0x0 0x208
FM_AOGPIO_10 0x3 0x208
FM_AOGPIO_11 0x0 0x238
FM_AOGPIO_10 0x3 0x238
>;
};
};
};
&padctrl_audiosys {
status = "okay";
light-audio-padctrl {
/*
* Pin Configuration Node:
* Format: <pin_id mux_node config>
*/
pinctrl_audio_i2c0: audio_i2c0_grp {
thead,pins = <
FM_AUDIO_IO_PA6 LIGHT_PIN_FUNC_0 0x004
FM_AUDIO_IO_PA7 LIGHT_PIN_FUNC_0 0x004
>;
};
pinctrl_audio_i2s1: audio_i2s1_grp {
thead,pins = <
FM_AUDIO_IO_PA13 LIGHT_PIN_FUNC_0 0x008
FM_AUDIO_IO_PA14 LIGHT_PIN_FUNC_0 0x008
FM_AUDIO_IO_PA15 LIGHT_PIN_FUNC_0 0x008
FM_AUDIO_IO_PA17 LIGHT_PIN_FUNC_0 0x008
>;
};
pinctrl_audio_i2s_8ch_bus: audio_i2s_8ch_bus_grp {
thead,pins = <
FM_AUDIO_IO_PA2 LIGHT_PIN_FUNC_3 0x008
FM_AUDIO_IO_PA3 LIGHT_PIN_FUNC_3 0x008
FM_AUDIO_IO_PA8 LIGHT_PIN_FUNC_3 0x008
>;
};
pinctrl_audio_i2s_8ch_sd2: audio_i2s_8ch_sd2_grp {
thead,pins = <
FM_AUDIO_IO_PA0 LIGHT_PIN_FUNC_3 0x008
>;
};
pinctrl_audio_i2s_8ch_sd3: audio_i2s_8ch_sd3_grp {
thead,pins = <
FM_AUDIO_IO_PA1 LIGHT_PIN_FUNC_3 0x008
>;
};
};
};
&i2c0 {
clock-frequency = <400000>;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c0>;
};
&i2c1 {
clock-frequency = <400000>;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
};
&i2c2 {
clock-frequency = <400000>;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
};
&i2c3 {
clock-frequency = <400000>;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
};
&i2c4 {
clock-frequency = <400000>;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c4>;
};
&isp0 {
@@ -1000,30 +1256,21 @@
status = "okay";
};
/*
&vvcam_sensor0 {
sensor_name = "IMX334";
sensor_regulators = "DOVDD18_RGB", "DVDD12_RGB", "AVDD28_RGB";
sensor_regulator_timing_us = <70 50 20>;
sensor_rst = <&gpio1_porta 16 0>;
sensor_pdn_delay_us = <1000>; //powerdown pin / shutdown pin actived till I2C ready
DOVDD18_RGB-supply = <&soc_dovdd18_rgb_reg>;
DVDD12_RGB-supply = <&soc_dvdd12_rgb_reg>;
AVDD28_RGB-supply = <&soc_avdd28_rgb_reg>;
&vvcam_sensor1 {
sensor_name = "OV5693";
sensor_regulators = "DOVDD18_RGB", "DVDD12_RGB", "AVDD28_RGB";
sensor_regulator_voltage_uV = <1800000 1200000 2800000>;
sensor_regulator_timing_us = <70 50 20>;
sensor_rst = <&gpio1_porta 16 0>;
sensor_pdn_delay_us = <4000>; //powerdown pin / shutdown pin actived till I2C ready
DOVDD18_RGB-supply = <&soc_dovdd18_rgb_reg>;
DVDD12_RGB-supply = <&soc_dvdd12_rgb_reg>;
AVDD28_RGB-supply = <&soc_avdd28_rgb_reg>;
i2c_reg_width = /bits/ 8 <2>;
i2c_data_width = /bits/ 8 <1>;
i2c_addr = /bits/ 8 <0x1a>;
i2c_bus = /bits/ 8 <3>;
status = "okay";
};
*/
&vvcam_sensor1 {
sensor_name = "OV5693";
i2c_bus = /bits/ 8 <3>;
i2c_reg_width = /bits/ 8 <1>;
i2c_data_width = /bits/ 8 <1>;
status = "disabled";
i2c_addr = /bits/ 8 <0x36>;
i2c_bus = /bits/ 8 <3>;
status = "okay";
};
&vvcam_sensor2 {
@@ -1054,6 +1301,9 @@
DVDD12_SCAN-supply = <&soc_dvdd12_scan_reg>;
AVDD28_SCAN-supply = <&soc_avdd28_scan_en_reg>;
i2c_bus = /bits/ 8 <4>;
i2c_reg_width = /bits/ 8 <2>;
i2c_data_width = /bits/ 8 <1>;
i2c_addr = /bits/ 8 <0x30>;
status = "okay";
};
@@ -1105,7 +1355,24 @@
status = "okay";
};
&vvcam_sensor7 {
sensor_name = "IMX334";
sensor_regulators = "DOVDD18_RGB", "DVDD12_RGB", "AVDD28_RGB";
sensor_regulator_timing_us = <70 50 20>;
sensor_rst = <&gpio1_porta 16 0>;
sensor_pdn_delay_us = <1000>; //powerdown pin / shutdown pin actived till I2C ready
DOVDD18_RGB-supply = <&soc_dovdd18_rgb_reg>;
DVDD12_RGB-supply = <&soc_dvdd12_rgb_reg>;
AVDD28_RGB-supply = <&soc_avdd28_rgb_reg>;
i2c_reg_width = /bits/ 8 <2>;
i2c_data_width = /bits/ 8 <1>;
i2c_addr = /bits/ 8 <0x1a>;
i2c_bus = /bits/ 8 <3>;
status = "okay";
};
&video0{
status = "okay";
vi_mem_pool_region = <2>; // vi_mem: framebuffer, region[2]
channel0 {
sensor0 {
@@ -1192,6 +1459,7 @@
&video1{
status = "okay";
vi_mem_pool_region = <2>; // vi_mem: framebuffer, region[2]
channel0 {
sensor0 {
@@ -1295,6 +1563,7 @@
};
&video2{
status = "okay";
vi_mem_pool_region = <0>; // vi_mem: framebuffer, region[0]
channel0 {
sensor0 {
@@ -1380,6 +1649,7 @@
};
&video3{
status = "okay";
vi_mem_pool_region = <0>; // vi_mem: framebuffer, region[0]
channel0 {
sensor0 {
@@ -1483,6 +1753,7 @@
};
&video4{
status = "okay";
vi_mem_pool_region = <0>; // vi_mem: framebuffer, region[0]
channel0 {
sensor0 {
@@ -1634,6 +1905,7 @@
};
&video5{
status = "okay";
vi_mem_pool_region = <0>; // vi_mem: framebuffer, region[0]
channel0 {
sensor0 {
@@ -1803,6 +2075,7 @@
};
&video6{
status = "okay";
vi_mem_pool_region = <1>; // vi_mem: framebuffer, region[1]
channel0 {
sensor0 {
@@ -1844,6 +2117,7 @@
};
&video7{
status = "okay";
channel0 {
sensor0 {
subdev_name = "vivcam";
@@ -2013,6 +2287,7 @@
&video8{
status = "okay";
vi_mem_pool_region = <1>; // vi_mem: framebuffer, region[1]
channel0 {
sensor0 {
@@ -2044,6 +2319,7 @@
};
&video9{
status = "okay";
channel0 {
sensor0 {
subdev_name = "vivcam";
@@ -2065,6 +2341,7 @@
&video10{ // TUNINGTOOL
status = "okay";
channel0 {
sensor0 {
subdev_name = "vivcam";
@@ -2086,6 +2363,7 @@
};
&video11{
status = "okay";
channel0 {
channel_id = <0>;
status = "okay";
@@ -2112,6 +2390,7 @@
};
&video12{ // TUNINGTOOL
status = "okay";
channel0 { // CSI2
sensor0 {
subdev_name = "vivcam";
@@ -2133,6 +2412,7 @@
};
&video14{
status = "okay";
vi_mem_pool_region = <2>; // vi_mem: framebuffer, region[0]
status = "okay";
channel0 {
@@ -2299,6 +2579,8 @@
&hdmi_tx {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hdmi>;
port@0 {
/* input */
@@ -2310,6 +2592,11 @@
&lightsound {
status = "okay";
simple-audio-card,widgets = "Speaker", "Speaker";
simple-audio-card,routing =
"Speaker", "AW87519 VO",
"AW87519 IN", "ES8156 ROUT";
simple-audio-card,aux-devs = <&audio_aw87519_pa>;
simple-audio-card,dai-link@0 { /* I2S - AUDIO SYS CODEC 8156*/
reg = <0>;
format = "i2s";
@@ -2324,7 +2611,7 @@
reg = <1>;
format = "i2s";
cpu {
sound-dai = <&i2s3 0>;
sound-dai = <&i2s_8ch_sd2 2>;
};
codec {
sound-dai = <&es7210_audio_codec>;
@@ -2337,7 +2624,7 @@
sound-dai = <&light_i2s 1>;
};
codec {
sound-dai = <&dummy_codec 2>;
sound-dai = <&dummy_codec>;
};
};
};
@@ -2352,10 +2639,29 @@
&i2s1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_audiopa13>,
<&pinctrl_audiopa14>,
<&pinctrl_audiopa15>,
<&pinctrl_audiopa17>,
<&pinctrl_audio_i2s1>;
};
&i2s3 {
&i2s_8ch_sd2 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_audiopa0>,
<&pinctrl_audio_i2s_8ch_sd2>,
<&pinctrl_audiopa2>,
<&pinctrl_audiopa3>,
<&pinctrl_audiopa8>,
<&pinctrl_audio_i2s_8ch_bus>;
};
&i2s_8ch_sd3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_audiopa1>,
<&pinctrl_audio_i2s_8ch_sd3>;
};
&cpus {

61
arch/riscv/boot/dts/thead/light-beagle-ref.dts
View File

@@ -15,7 +15,7 @@
memory@0 {
device_type = "memory";
reg = <0x0 0x00000000 0x0 0x80000000>;
reg = <0x0 0x200000 0x0 0x7fe00000>;
};
chosen {
@@ -166,6 +166,14 @@
iopmp_dsp1: IOPMP_DSP1 {
is_default_region;
};
iopmp_audio0: IOPMP_AUDIO0 {
is_default_region;
};
iopmp_audio1: IOPMP_AUDIO1 {
is_default_region;
};
};
mbox_910t_client1: mbox_910t_client1 {
@@ -194,9 +202,10 @@
};
dummy_codec: dummy_codec {
#sound-dai-cells = <1>;
compatible = "linux,bt-sco";
#sound-dai-cells = <0>;
compatible = "thead,light-dummy-pcm";
status = "okay";
sound-name-prefix = "DUMMY";
};
reg_vref_1v8: regulator-adc-verf {
@@ -569,24 +578,34 @@
clock-frequency = <100000>;
status = "okay";
es8156_audio_codec: es8156@8 {
#sound-dai-cells = <0>;
compatible = "everest,es8156";
reg = <0x08>;
};
es8156_audio_codec: es8156@8 {
#sound-dai-cells = <0>;
compatible = "everest,es8156";
reg = <0x08>;
sound-name-prefix = "ES8156";
AVDD-supply = <&soc_aud_3v3_en_reg>;
DVDD-supply = <&soc_aud_1v8_en_reg>;
PVDD-supply = <&soc_aud_1v8_en_reg>;
};
es7210_audio_codec: es7210@40 {
#sound-dai-cells = <0>;
compatible = "MicArray_0";
reg = <0x40>;
sound-name-prefix = "ES7210";
MVDD-supply = <&soc_aud_3v3_en_reg>;
AVDD-supply = <&soc_aud_3v3_en_reg>;
DVDD-supply = <&soc_aud_1v8_en_reg>;
PVDD-supply = <&soc_aud_1v8_en_reg>;
};
audio_aw87519_pa@58 {
compatible = "awinic,aw87519_pa";
reg = <0x58>;
reset-gpio = <&ao_gpio4_porta 9 0x1>;
status = "okay";
};
audio_aw87519_pa: amp@58 {
compatible = "awinic,aw87519_pa";
reg = <0x58>;
reset-gpio = <&ao_gpio4_porta 9 0x1>;
sound-name-prefix = "AW87519";
status = "okay";
};
};
&i2c1 {
@@ -719,6 +738,7 @@
no-mmc;
non-removable;
io_fixed_1v8;
rxclk-sample-delay = <80>;
post-power-on-delay-ms = <50>;
wprtn_ignore;
cap-sd-highspeed;
@@ -761,7 +781,7 @@
>;
};
pinctrl_audio_i2s0: i2s0grp {
pinctrl_light_i2s0: i2s0grp {
thead,pins = <
FM_QSPI0_SCLK 0x2 0x208
FM_QSPI0_CSN0 0x2 0x238
@@ -2249,6 +2269,11 @@
&lightsound {
status = "okay";
simple-audio-card,widgets = "Speaker", "Speaker";
simple-audio-card,routing =
"Speaker", "AW87519 VO",
"AW87519 IN", "ES8156 ROUT";
simple-audio-card,aux-devs = <&audio_aw87519_pa>;
simple-audio-card,dai-link@0 { /* I2S - AUDIO SYS CODEC 8156*/
reg = <0>;
format = "i2s";
@@ -2263,7 +2288,7 @@
reg = <1>;
format = "i2s";
cpu {
sound-dai = <&i2s3 0>;
sound-dai = <&i2s_8ch_sd2 2>;
};
codec {
sound-dai = <&es7210_audio_codec>;
@@ -2276,7 +2301,7 @@
sound-dai = <&light_i2s 1>;
};
codec {
sound-dai = <&dummy_codec 2>;
sound-dai = <&dummy_codec>;
};
};
};
@@ -2293,7 +2318,7 @@
status = "okay";
};
&i2s3 {
&i2s_8ch_sd2 {
status = "okay";
};

41
arch/riscv/boot/dts/thead/light-crash.dts
View File

@@ -163,6 +163,14 @@
iopmp_dsp1: IOPMP_DSP1 {
is_default_region;
};
iopmp_audio0: IOPMP_AUDIO0 {
is_default_region;
};
iopmp_audio1: IOPMP_AUDIO1 {
is_default_region;
};
};
mbox_910t_client1: mbox_910t_client1 {
@@ -191,8 +199,9 @@
};
dummy_codec: dummy_codec {
#sound-dai-cells = <1>;
compatible = "linux,bt-sco";
#sound-dai-cells = <0>;
compatible = "thead,light-dummy-pcm";
sound-name-prefix = "DUMMY";
status = "okay";
};
@@ -327,7 +336,7 @@
irq-gpios = <&gpio1_porta 8 0>;
reset-gpios = <&gpio1_porta 7 0>;
AVDD28-supply = <&reg_tp_pwr_en>;
touchscreen-size-x = <720>;
touchscreen-size-x = <800>;
touchscreen-size-y = <1280>;
};
@@ -341,18 +350,23 @@
#sound-dai-cells = <0>;
compatible = "everest,es8156";
reg = <0x08>;
sound-name-prefix = "ES8156";
status = "disabled";
};
es7210_audio_codec: es7210@40 {
#sound-dai-cells = <0>;
compatible = "MicArray_0";
reg = <0x40>;
sound-name-prefix = "ES7210";
status = "disabled";
};
audio_aw87519_pa@58 {
audio_aw87519_pa: amp@58 {
compatible = "awinic,aw87519_pa";
reg = <0x58>;
reset-gpio = <&ao_gpio4_porta 9 0x1>;
sound-name-prefix = "AW87519";
status = "okay";
};
};
@@ -488,6 +502,7 @@
no-mmc;
non-removable;
io_fixed_1v8;
rxclk-sample-delay = <80>;
post-power-on-delay-ms = <50>;
wprtn_ignore;
cap-sd-highspeed;
@@ -530,7 +545,7 @@
>;
};
pinctrl_audio_i2s0: i2s0grp {
pinctrl_light_i2s0: i2s0grp {
thead,pins = <
FM_QSPI0_SCLK 0x2 0x208
FM_QSPI0_CSN0 0x2 0x238
@@ -862,22 +877,6 @@
status = "disabled";
};
&light_i2s {
status = "okay";
};
&i2s0 {
status = "okay";
};
&i2s1 {
status = "okay";
};
&i2s3 {
status = "okay";
};
&khvhost {
status = "disabled";
};

2
arch/riscv/boot/dts/thead/light-emu.dtsi
View File

@@ -309,7 +309,7 @@
entry-cnt = <4>;
control-reg = <0xff 0xff015004>;
control-val = <0x1c>;
csr-copy = <0x7f3 0x7c0 0x7c1 0x7c2 0x7c3 0x7c5 0x7cc>;
csr-copy = <0x7f3 0x7c0 0x7c1 0x7c2 0x7c3 0x7c5 0x7cc 0x7ce>;
};
clint0: clint@ffdc000000 {

13
arch/riscv/boot/dts/thead/light-evb.dtsi
View File

@@ -318,7 +318,7 @@
entry-cnt = <4>;
control-reg = <0xff 0xff015004>;
control-val = <0x1c>;
csr-copy = <0x7f3 0x7c0 0x7c1 0x7c2 0x7c3 0x7c5 0x7cc>;
csr-copy = <0x7f3 0x7c0 0x7c1 0x7c2 0x7c3 0x7c5 0x7cc 0x7ce>;
};
clint0: clint@ffdc000000 {
@@ -1193,8 +1193,7 @@
emmc: sdhci@ffe7080000 {
compatible = "snps,dwcmshc-sdhci";
reg = <0xff 0xe7080000 0x0 0x10000
0xff 0xef014060 0x0 0x4>;
reg = <0xff 0xe7080000 0x0 0x10000>;
interrupt-parent = <&intc>;
interrupts = <62>;
interrupt-names = "sdhciirq";
@@ -1204,8 +1203,7 @@
sdhci0: sd@ffe7090000 {
compatible = "snps,dwcmshc-sdhci";
reg = <0xff 0xe7090000 0x0 0x10000
0xff 0xef014064 0x0 0x4>;
reg = <0xff 0xe7090000 0x0 0x10000>;
interrupt-parent = <&intc>;
interrupts = <64>;
interrupt-names = "sdhci0irq";
@@ -1215,8 +1213,7 @@
sdhci1: sd@ffe70a0000 {
compatible = "snps,dwcmshc-sdhci";
reg = <0xff 0xe70a0000 0x0 0x10000
0xff 0xef014064 0x0 0x4>;
reg = <0xff 0xe70a0000 0x0 0x10000>;
interrupt-parent = <&intc>;
interrupts = <71>;
interrupt-names = "sdhci1irq";
@@ -1302,7 +1299,7 @@
compatible = "light,light-i2s";
reg = <0xff 0xe7034000 0x0 0x4000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_audio_i2s0>;
pinctrl-0 = <&pinctrl_light_i2s0>;
light,mode = "i2s-master";
interrupt-parent = <&intc>;
interrupts = <70>;

4
arch/riscv/boot/dts/thead/light-fm-emu.dts
View File

@@ -185,7 +185,7 @@
sound-dai = <&light_i2s 0>;
};
codec {
sound-dai = <&dummy_codec 2>;
sound-dai = <&dummy_codec>;
};
};
@@ -196,7 +196,7 @@
sound-dai = <&light_i2s 1>;
};
codec {
sound-dai = <&dummy_codec 2>;
sound-dai = <&dummy_codec>;
};
};
};

53
arch/riscv/boot/dts/thead/light-lpi4a-camera-tuning.dts Normal file
View File

@@ -0,0 +1,53 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2021 Alibaba Group Holding Limited.
*/
/dts-v1/;
#include "light-lpi4a.dts"
&video10{ // TUNINGTOOL
status = "okay";
channel0 {
sensor1 {
subdev_name = "vivcam";
idx = <3>;
csi_idx = <0>;
mode_idx = <1>; // 0=640 480 1=2592x1944
path_type = "SENSOR_2592x1944_LINER";
};
dma {
path_type = "VIPRE_CSI0_ISP0";
};
};
};
&video15{
status = "okay";
vi_mem_pool_region = <0>; // vi_mem: framebuffer, region[0]
channel0 {
status = "okay";
sensor0 {
subdev_name = "vivcam";
idx = <0>;
csi_idx = <0>;
mode_idx = <0>;
path_type = "SENSOR_VGA_RAW12_LINER";
};
sensor1 {
subdev_name = "vivcam";
idx = <3>;
csi_idx = <0>;
mode_idx = <1>;
path_type = "SENSOR_2592x1944_LINER";
};
dma {
subdev_name = "vipre";
idx = <0>;
path_type = "VIPRE_CSI0_DDR";
};
};
};

98
arch/riscv/boot/dts/thead/light-lpi4a-crash.dts Normal file
View File

@@ -0,0 +1,98 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2023 Alibaba Group Holding Limited.
*/
#include "light-crash.dts"
&aon {
aon_reg_dialog: light-dialog-reg {
compatible = "thead,light-dialog-pmic-ant";
status = "okay";
dvdd_cpu_reg: appcpu_dvdd {
regulator-name = "appcpu_dvdd";
regulator-min-microvolt = <300000>;
regulator-max-microvolt = <1570000>;
regulator-boot-on;
regulator-always-on;
};
dvddm_cpu_reg: appcpu_dvddm {
regulator-name = "appcpu_dvddm";
regulator-min-microvolt = <300000>;
regulator-max-microvolt = <1570000>;
regulator-boot-on;
regulator-always-on;
};
};
};
&cpus {
c910_0: cpu@0 {
operating-points = <
/* kHz uV */
300000 600000
800000 700000
1500000 800000
1848000 1000000
>;
light,dvddm-operating-points = <
/* kHz uV */
300000 800000
800000 800000
1500000 800000
1848000 1000000
>;
};
c910_1: cpu@1 {
operating-points = <
/* kHz uV */
300000 600000
800000 700000
1500000 800000
1848000 1000000
>;
light,dvddm-operating-points = <
/* kHz uV */
300000 800000
800000 800000
1500000 800000
1848000 1000000
>;
};
c910_2: cpu@2 {
operating-points = <
/* kHz uV */
300000 600000
800000 700000
1500000 800000
1848000 1000000
>;
light,dvddm-operating-points = <
/* kHz uV */
300000 800000
800000 800000
1500000 800000
1848000 1000000
>;
};
c910_3: cpu@3 {
operating-points = <
/* kHz uV */
300000 600000
800000 700000
1500000 800000
1848000 1000000
>;
light,dvddm-operating-points = <
/* kHz uV */
300000 800000
800000 800000
1500000 800000
1848000 1000000
>;
};
};

20
arch/riscv/boot/dts/thead/light-lpi4a-ddr2G.dts Normal file
View File

@@ -0,0 +1,20 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2022 Alibaba Group Holding Limited.
*/
#include "light-lpi4a.dts"
/ {
model = "T-HEAD Light Lichee Pi 4A configuration for 2GB DDR board";
compatible = "thead,light-val", "thead,light-lpi4a-ddr2G", "thead,light";
memory@0 {
device_type = "memory";
reg = <0x0 0x200000 0x0 0x7fe00000>;
};
};
&cmamem {
alloc-ranges = <0 0x64000000 0 0x14000000>; // [0x6400_0000 ~ 0x7800_0000]
};

50
arch/riscv/boot/dts/thead/light-lpi4a-hdmi.dts Normal file
View File

@@ -0,0 +1,50 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2021 Alibaba Group Holding Limited.
*/
/dts-v1/;
#include "light-lpi4a.dts"
&lightsound {
status = "okay";
simple-audio-card,dai-link@0 { /* I2S - HDMI*/
reg = <0>;
format = "i2s";
cpu {
sound-dai = <&light_i2s 1>;
};
codec {
sound-dai = <&dummy_codec>;
};
};
simple-audio-card,dai-link@1 { /* I2S - AUDIO SYS CODEC 7210*/
reg = <1>;
format = "i2s";
cpu {
sound-dai = <&i2s1 0>;
};
codec {
sound-dai = <&es7210_audio_codec>;
};
};
simple-audio-card,dai-link@2 { /* I2S - AUDIO SYS CODEC 8156*/
reg = <2>;
format = "i2s";
cpu {
sound-dai = <&i2s1 0>;
};
codec {
sound-dai = <&es8156_audio_codec>;
};
};
};
&dpu_enc0 {
status = "disabled";
};
&dsi0 {
status = "disabled";
};

60
arch/riscv/boot/dts/thead/light-lpi4a-hx8279.dts Normal file
View File

@@ -0,0 +1,60 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2022-2023 Alibaba Group Holding Limited.
*/
#include "light-lpi4a-ref.dts"
/ {
model = "T-HEAD Light Lichee Pi 4A configuration for 8GB DDR board";
compatible = "thead,light-val", "thead,light-lpi4a", "thead,light";
memory@0 {
device_type = "memory";
reg = <0x0 0x200000 0x1 0xffe00000>;
};
};
&cmamem {
size = <0 0x20000000>; // 512MB on lpi4a (SOM)
alloc-ranges = <0 0xd8000000 0 0x20000000>; // [0x0D800_0000 ~ 0x0F800_0000]
};
&i2c3 {
touch@14 {
#gpio-cells = <2>;
compatible = "goodix,gt9271";
reg = <0x14>;
interrupt-parent = <&ao_gpio_porta>;
interrupts = <3 0>;
irq-gpios = <&ao_gpio_porta 3 0>;
reset-gpios = <&pcal6408ahk_d 0 0>;
AVDD28-supply = <&reg_tp_pwr_en>;
touchscreen-size-x = <1200>;
touchscreen-size-y = <1920>;
tp-size = <9271>;
status = "okay";
};
};
&dsi0 {
status = "okay";
};
&dhost_0 {
panel0@0 {
compatible = "himax,hx8279";
reg = <0>;
backlight = <&lcd0_backlight>;
reset-gpio = <&pcal6408ahk_d 7 0>; /* active low */
hsvcc-supply = <&soc_vdd18_lcd0_en_reg>;
vspn3v3-supply = <&soc_vdd33_lcd0_en_reg>;
port {
panel0_in: endpoint {
remote-endpoint = <&dsi0_out>;
};
};
};
};

1828
arch/riscv/boot/dts/thead/light-lpi4a-ref.dts Normal file
View File

File diff suppressed because it is too large Load Diff

18
arch/riscv/boot/dts/thead/light-lpi4a-sec.dts Normal file
View File

@@ -0,0 +1,18 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2021 Alibaba Group Holding Limited.
*/
/dts-v1/;
#include "light-lpi4a-hdmi.dts"
&light_iopmp {
status = "disabled";
};
&qspi1 {
status = "disabled";
};

59
arch/riscv/boot/dts/thead/light-lpi4a.dts Normal file
View File

@@ -0,0 +1,59 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2022-2023 Alibaba Group Holding Limited.
*/
#include "light-lpi4a-ref.dts"
/ {
model = "T-HEAD Light Lichee Pi 4A configuration for 8GB DDR board";
compatible = "thead,light-val", "thead,light-lpi4a", "thead,light";
memory@0 {
device_type = "memory";
reg = <0x0 0x200000 0x1 0xffe00000>;
};
};
&cmamem {
size = <0 0x20000000>; // 512MB on lpi4a (SOM)
alloc-ranges = <0 0xd8000000 0 0x20000000>; // [0x0D800_0000 ~ 0x0F800_0000]
};
&i2c3 {
touch@14 {
#gpio-cells = <2>;
compatible = "goodix,gt9271";
reg = <0x14>;
interrupt-parent = <&ao_gpio_porta>;
interrupts = <3 0>;
irq-gpios = <&ao_gpio_porta 3 0>;
reset-gpios = <&pcal6408ahk_d 0 0>;
AVDD28-supply = <&reg_tp_pwr_en>;
touchscreen-size-x = <800>;
touchscreen-size-y = <1200>;
tp-size = <9271>;
status = "okay";
};
};
&dsi0 {
status = "okay";
};
&dhost_0 {
panel0@0 {
compatible = "chongzhou,cz101b4001", "jadard,jd9365da-h3";
reg = <0>;
backlight = <&lcd0_backlight>;
reset-gpio = <&pcal6408ahk_d 7 0>; /* active low */
hsvcc-supply = <&soc_vdd18_lcd0_en_reg>;
vspn3v3-supply = <&soc_vdd33_lcd0_en_reg>;
port {
panel0_in: endpoint {
remote-endpoint = <&dsi0_out>;
};
};
};
};

32
arch/riscv/boot/dts/thead/light-vi-devices.dtsi
View File

@@ -4,7 +4,7 @@
*/
&video0{
status = "okay";
status = "disabled";
channel0 {
channel_id = <0>;
status = "okay";
@@ -86,7 +86,7 @@
};
&video1{
status = "okay";
status = "disabled";
channel0 { // VSE0
channel_id = <0>;
status = "okay";
@@ -183,7 +183,7 @@
};
&video2 {
status = "okay";
status = "disabled";
channel0 {
channel_id = <0>;
status = "okay";
@@ -199,6 +199,12 @@
csi_idx = <0xff>;
path_type = "SENSOR_VGA_RAW10_LINER";
};
sensor2 {
subdev_name = "vivcam";
idx = <0xff>; // invalid
csi_idx = <0xff>;
path_type = "SENSOR_VGA_RAW10_LINER";
};
dma {
subdev_name = "vipre";
idx = <0>;
@@ -266,7 +272,7 @@
};
&video3 {
status = "okay";
status = "disabled";
channel0 {
channel_id = <0>;
status = "okay";
@@ -364,7 +370,7 @@
};
&video4 {
status = "okay";
status = "disabled";
channel0 {
channel_id = <0>;
status = "okay";
@@ -477,7 +483,7 @@
};
&video5 {
status = "okay";
status = "disabled";
channel0 {
channel_id = <0>;
status = "okay";
@@ -606,7 +612,7 @@
&video6 {
status = "okay";
status = "disabled";
channel0 {
channel_id = <0>;
status = "okay";
@@ -663,7 +669,7 @@
&video7{
status = "okay";
status = "disabled";
channel0 {
channel_id = <0>;
status = "okay";
@@ -792,7 +798,7 @@
&video8{
status = "okay";
status = "disabled";
channel0 {
channel_id = <0>;
status = "okay";
@@ -823,7 +829,7 @@
&video9 { //IR debug
status = "okay";
status = "disabled";
channel0 {
channel_id = <0>;
status = "okay";
@@ -856,7 +862,7 @@
&video10{ // TUNING TOOL
status = "okay";
status = "disabled";
channel0 { // CSI2X2_B
status = "okay";
sensor0 {
@@ -883,7 +889,7 @@
&video11{
status = "okay";
status = "disabled";
channel0 {
channel_id = <0>;
status = "okay";
@@ -914,7 +920,7 @@
&video12{ // TUNING TOOL
status = "okay";
status = "disabled";
channel0 { // CSI2
status = "okay";
sensor0 {

603
arch/riscv/boot/dts/thead/light.dtsi
View File

@@ -6,12 +6,16 @@
#include <dt-bindings/pinctrl/light-fm-left-pinctrl.h>
#include <dt-bindings/pinctrl/light-fm-right-pinctrl.h>
#include <dt-bindings/pinctrl/light-fm-aon-pinctrl.h>
#include <dt-bindings/pinctrl/light-fm-audio-pinctrl.h>
#include <dt-bindings/pinctrl/light-fm-pinctrl-def.h>
#include <dt-bindings/clock/light-fm-ap-clock.h>
#include <dt-bindings/clock/light-vpsys.h>
#include <dt-bindings/clock/light-vosys.h>
#include <dt-bindings/clock/light-visys.h>
#include <dt-bindings/clock/light-dspsys.h>
#include <dt-bindings/clock/light-audiosys.h>
#include <dt-bindings/firmware/thead/rsrc.h>
#include <dt-bindings/clock/light-miscsys.h>
#include <dt-bindings/soc/thead,light-iopmp.h>
#include <dt-bindings/thermal/thermal.h>
#include <dt-bindings/reset/light-reset.h>
@@ -34,6 +38,7 @@
i2c3 = &i2c3;
i2c4 = &i2c4;
audio_i2c0 = &audio_i2c0;
audio_i2c1 = &audio_i2c1;
mmc0 = &emmc;
mmc1 = &sdhci0;
serial0 = &uart0;
@@ -54,6 +59,7 @@
vivcam4 = &vvcam_sensor4;
vivcam5 = &vvcam_sensor5;
vivcam6 = &vvcam_sensor6;
vivcam7 = &vvcam_sensor7;
viv_video0 = &video0;
viv_video1 = &video1;
@@ -93,6 +99,11 @@
};
};
aon_iram: aon-iram@ffffef8000 {
compatible = "syscon";
reg = <0xff 0xffef8000 0x0 0x10000>;
};
thermal-zones {
cpu-thermal-zone {
polling-delay-passive = <250>;
@@ -175,6 +186,7 @@
interrupt-controller;
};
};
c910_1: cpu@1 {
device_type = "cpu";
reg = <1>;
@@ -313,6 +325,44 @@
interrupt-controller;
};
};
idle_states: idle-states {
CPU_RET_0_0: cpu-retentive-0-0 {
compatible = "riscv,idle-state";
riscv,sbi-suspend-param = <0x10000000>;
entry-latency-us = <20>;
exit-latency-us = <40>;
min-residency-us = <80>;
};
CPU_NONRET_0_0: cpu-nonretentive-0-0 {
compatible = "riscv,idle-state";
riscv,sbi-suspend-param = <0x90000000>;
entry-latency-us = <250>;
exit-latency-us = <500>;
min-residency-us = <950>;
};
CLUSTER_RET_0: cluster-retentive-0 {
compatible = "riscv,idle-state";
riscv,sbi-suspend-param = <0x11000000>;
local-timer-stop;
entry-latency-us = <50>;
exit-latency-us = <100>;
min-residency-us = <250>;
wakeup-latency-us = <130>;
};
CLUSTER_NONRET_0: cluster-nonretentive-0 {
compatible = "riscv,idle-state";
riscv,sbi-suspend-param = <0x91000000>;
local-timer-stop;
entry-latency-us = <600>;
exit-latency-us = <1100>;
min-residency-us = <2700>;
wakeup-latency-us = <1500>;
};
};
};
display-subsystem {
@@ -382,7 +432,7 @@
entry-cnt = <4>;
control-reg = <0xff 0xff015004>;
control-val = <0x1c>;
csr-copy = <0x7f3 0x7c0 0x7c1 0x7c2 0x7c3 0x7c5 0x7cc>;
csr-copy = <0x7f3 0x7c0 0x7c1 0x7c2 0x7c3 0x7c5 0x7cc 0x7ce>;
};
clint0: clint@ffdc000000 {
@@ -621,6 +671,18 @@
status = "okay";
};
miscsys_reg: miscsys-reg@ffec02c000 {
compatible = "thead,light-miscsys-reg", "syscon";
reg = <0xff 0xec02c000 0x0 0x1000>;
status = "okay";
};
tee_miscsys_reg: tee_miscsys-reg@fffc02d000 {
compatible = "thead,light-miscsys-reg", "syscon";
reg = <0xff 0xfc02d000 0x0 0x1000>;
status = "okay";
};
audio_ioctrl: audio_ioctrl@ffcb01d000 {
compatible = "thead,light-audio-ioctrl-reg", "syscon";
reg = <0xff 0xcb01d000 0x0 0x1000>;
@@ -633,12 +695,20 @@
status = "okay";
};
audio_mbox: audio_mbox@0xffefc48000 {
compatible = "thead,light-audio-mbox-reg", "syscon";
reg = <0xff 0xefc48000 0x0 0x1000>;
status = "okay";
};
nvmem_controller: efuse@ffff210000 {
compatible = "thead,light-fm-efuse", "syscon";
reg = <0xff 0xff210000 0x0 0x10000>;
thead,teesys = <&teesys_syscon>;
#address-cells = <1>;
#size-cells = <1>;
clocks = <&miscsys_clk_gate CLKGEN_MISCSYS_EFUSE_PCLK>;
clock-names = "pclk";
gmac0_mac_address: mac-address@176 {
reg = <0xb0 6>;
@@ -666,7 +736,9 @@
reg = <0xff 0xec005000 0x0 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clk CLKGEN_GPIO0_PCLK>,
<&clk CLKGEN_GPIO0_DBCLK>;
clock-names = "bus", "db";
gpio0_porta: gpio0-controller@0 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
@@ -686,7 +758,9 @@
reg = <0xff 0xec006000 0x0 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clk CLKGEN_GPIO1_PCLK>,
<&clk CLKGEN_GPIO1_DBCLK>;
clock-names = "bus", "db";
gpio1_porta: gpio1-controller@0 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
@@ -706,7 +780,9 @@
reg = <0xff 0xe7f34000 0x0 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clk CLKGEN_GPIO2_PCLK>,
<&clk CLKGEN_GPIO2_DBCLK>;
clock-names = "bus", "db";
gpio2_porta: gpio2-controller@0 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
@@ -726,7 +802,9 @@
reg = <0xff 0xe7f38000 0x0 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clk CLKGEN_GPIO3_PCLK>,
<&clk CLKGEN_GPIO3_DBCLK>;
clock-names = "bus", "db";
gpio3_porta: gpio3-controller@0 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
@@ -781,15 +859,19 @@
};
};
padctrl1_apsys: pinctrl1-apsys@ffe7f3c000 {
padctrl1_apsys: padctrl1-apsys@ffe7f3c000 {
compatible = "thead,light-fm-left-pinctrl";
reg = <0xff 0xe7f3c000 0x0 0x1000>;
clocks = <&clk CLKGEN_PADCTRL1_APSYS_PCLK>;
clock-names = "pclk";
status = "okay";
};
padctrl0_apsys: padctrl0-apsys@ffec007000 {
compatible = "thead,light-fm-right-pinctrl";
reg = <0xff 0xec007000 0x0 0x1000>;
clocks = <&clk CLKGEN_PADCTRL0_APSYS_PCLK>;
clock-names = "pclk";
status = "okay";
};
@@ -854,6 +936,12 @@
status = "okay";
};
padctrl_audiosys: padctrl-audiosys@ffcb01d000 {
compatible = "thead,light-fm-audio-pinctrl";
reg = <0xff 0xcb01d000 0x0 0x1000>;
status = "disabled";
};
timer4: timer@ffffc33000 {
compatible = "snps,dw-apb-timer";
reg = <0xff 0xffc33000 0x0 0x14>;
@@ -899,7 +987,7 @@
};
uart0: serial@ffe7014000 { /* Normal serial, for C910 log */
compatible = "snps,dw-apb-uart";
compatible = "snps,dw-apb-uart", "light,uart0";
reg = <0xff 0xe7014000 0x0 0x4000>;
interrupt-parent = <&intc>;
interrupts = <36>;
@@ -994,7 +1082,9 @@
pinctrl-0 = <&pinctrl_spi0>;
interrupt-parent = <&intc>;
interrupts = <54>;
clocks = <&dummy_clock_spi>;
clocks = <&clk CLKGEN_SPI_SSI_CLK>,
<&clk CLKGEN_SPI_PCLK>;
clock-names = "sclk", "pclk";
num-cs = <2>;
#address-cells = <1>;
#size-cells = <0>;
@@ -1007,7 +1097,9 @@
pinctrl-0 = <&pinctrl_qspi0>;
interrupt-parent = <&intc>;
interrupts = <52>;
clocks = <&dummy_clock_qspi>;
clocks = <&clk CLKGEN_QSPI0_SSI_CLK>,
<&clk CLKGEN_QSPI0_PCLK>;
clock-names = "sclk", "pclk";
#address-cells = <1>;
#size-cells = <0>;
};
@@ -1019,7 +1111,9 @@
pinctrl-0 = <&pinctrl_qspi1>;
interrupt-parent = <&intc>;
interrupts = <53>;
clocks = <&dummy_clock_spi>;
clocks = <&clk CLKGEN_QSPI1_SSI_CLK>,
<&clk CLKGEN_QSPI1_PCLK>;
clock-names = "sclk", "pclk";
#address-cells = <1>;
#size-cells = <0>;
};
@@ -1117,9 +1211,8 @@
clocks = <&vosys_clk_gate LIGHT_CLKGEN_HDMI_PCLK>,
<&vosys_clk_gate LIGHT_CLKGEN_HDMI_SFR_CLK>,
<&vosys_clk_gate LIGHT_CLKGEN_HDMI_CEC_CLK>,
<&vosys_clk_gate LIGHT_CLKGEN_HDMI_PIXCLK>,
<&vosys_clk_gate LIGHT_CLKGEN_HDMI_I2S_CLK>;
clock-names = "iahb", "isfr", "cec", "pixclk", "i2s";
<&vosys_clk_gate LIGHT_CLKGEN_HDMI_PIXCLK>;
clock-names = "iahb", "isfr", "cec", "pixclk";
reg-io-width = <4>;
phy_version = <301>;
/* TODO: add phy property */
@@ -1135,6 +1228,7 @@
<0xff 0xef630010 0x0 0x60>;
interrupt-parent = <&intc>;
interrupts = <93>;
vosys-regmap = <&vosys_reg>;
clocks = <&vosys_clk_gate LIGHT_CLKGEN_DPU_CCLK>,
<&vosys_clk_gate LIGHT_CLKGEN_DPU_PIXCLK0>,
<&vosys_clk_gate LIGHT_CLKGEN_DPU_PIXCLK1>,
@@ -1196,6 +1290,7 @@
interrupts = <74>;
clocks = <&dummy_clock_rtc>;
clock-names = "rtc";
wakeup-source;
status = "okay";
};
@@ -1203,6 +1298,11 @@
compatible = "thead,dwc3";
usb3-misc-regmap = <&misc_sysreg>;
usb3-drd-regmap = <&usb3_drd>;
clocks = <&miscsys_clk_gate CLKGEN_MISCSYS_USB3_DRD_CLK>,
<&miscsys_clk_gate CLKGEN_MISCSYS_USB3_DRD_CTRL_REF_CLK>,
<&miscsys_clk_gate CLKGEN_MISCSYS_USB3_DRD_PHY_REF_CLK>,
<&miscsys_clk_gate CLKGEN_MISCSYS_USB3_DRD_SUSPEND_CLK>;
clock-names = "drd", "ctrl", "phy", "suspend";
#address-cells = <2>;
#size-cells = <2>;
ranges;
@@ -1212,8 +1312,6 @@
reg = <0xff 0xe7040000 0x0 0x10000>;
interrupt-parent = <&intc>;
interrupts = <68>;
clocks = <&dummy_clock_ref>, <&dummy_clock_apb>, <&dummy_clock_suspend>;
clock-names = "ref", "bus_early", "suspend";
reg-shift = <2>;
reg-io-width = <4>;
maximum-speed = "super-speed";
@@ -1247,6 +1345,13 @@
status = "okay";
};
vpsys_rst: vpsys-reset-controller@ffecc30000 {
compatible = "thead,light-vpsys-reset-src","syscon";
reg = <0xff 0xecc30000 0x0 0x1000>;
#reset-cells = <1>;
status = "okay";
};
sys_reg: sys_reg@ffef010100 {
compatible = "thead,light_sys_reg";
reg = <0xff 0xef010100 0x0 0x100>;
@@ -1258,7 +1363,7 @@
reg = <0xff 0xefc00000 0x0 0x1000>;
interrupt-parent = <&intc>;
interrupts = <27>;
clocks = <&dummy_clock_apb>, <&dummy_clock_apb>;
clocks = <&clk CLKGEN_DMAC_CPUSYS_ACLK>, <&clk CLKGEN_DMAC_CPUSYS_HCLK>;
clock-names = "core-clk", "cfgr-clk";
#dma-cells = <1>;
dma-channels = <4>;
@@ -1275,7 +1380,7 @@
reg = <0xff 0xff340000 0x0 0x1000>;
interrupt-parent = <&intc>;
interrupts = <150>;
clocks = <&dummy_clock_apb>, <&dummy_clock_apb>;
clocks = <&clk CLKGEN_DMAC_CPUSYS_ACLK>, <&clk CLKGEN_DMAC_CPUSYS_HCLK>;
clock-names = "core-clk", "cfgr-clk";
#dma-cells = <1>;
dma-channels = <4>;
@@ -1292,7 +1397,7 @@
reg = <0xff 0xc8000000 0x0 0x2000>;
interrupt-parent = <&intc>;
interrupts = <167>;
clocks = <&dummy_clock_apb>, <&dummy_clock_apb>;
clocks = <&clk CLKGEN_DMAC_CPUSYS_ACLK>, <&clk CLKGEN_DMAC_CPUSYS_HCLK>;
clock-names = "core-clk", "cfgr-clk";
#dma-cells = <1>;
dma-channels = <16>;
@@ -1300,7 +1405,7 @@
65536 65536 65536 65536
65536 65536 65536 65536
65536 65536 65536 65536>;
snps,priority = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>;
snps,priority = <0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0>; // <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>;
snps,dma-masters = <1>;
snps,data-width = <4>;
snps,axi-max-burst-len = <16>;
@@ -1323,8 +1428,11 @@
interrupt-parent = <&intc>;
interrupts = <66>;
interrupt-names = "macirq";
clocks = <&clk CLKGEN_GMAC0_CCLK>;
clock-names = "gmac_pll_clk";
clocks = <&clk CLKGEN_GMAC0_CCLK>,
<&clk CLKGEN_GMAC0_PCLK>,
<&clk CLKGEN_GMAC_AXI_ACLK>,
<&clk CLKGEN_GMAC_AXI_PCLK>;
clock-names = "gmac_pll_clk","pclk","axi_aclk","axi_pclk";
snps,pbl = <32>;
snps,fixed-burst;
snps,axi-config = <&stmmac_axi_setup>;
@@ -1342,8 +1450,11 @@
interrupt-parent = <&intc>;
interrupts = <67>;
interrupt-names = "macirq";
clocks = <&clk CLKGEN_GMAC1_CCLK>;
clock-names = "gmac_pll_clk";
clocks = <&clk CLKGEN_GMAC1_CCLK>,
<&clk CLKGEN_GMAC1_PCLK>,
<&clk CLKGEN_GMAC_AXI_ACLK>,
<&clk CLKGEN_GMAC_AXI_PCLK>;
clock-names = "gmac_pll_clk","pclk","axi_aclk","axi_pclk";
snps,pbl = <32>;
snps,fixed-burst;
snps,axi-config = <&stmmac_axi_setup>;
@@ -1353,35 +1464,35 @@
emmc: sdhci@ffe7080000 {
compatible = "snps,dwcmshc-sdhci";
reg = <0xff 0xe7080000 0x0 0x10000
0xff 0xef014060 0x0 0x4>;
reg = <0xff 0xe7080000 0x0 0x10000>;
interrupt-parent = <&intc>;
interrupts = <62>;
interrupt-names = "sdhciirq";
clocks = <&dummy_clock_sdhci>;
clock-names = "core";
clocks = <&clk CLKGEN_EMMC_SDIO_REF_CLK>,
<&miscsys_clk_gate CLKGEN_MISCSYS_EMMC_CLK>;
clock-names = "core", "bus";
};
sdhci0: sd@ffe7090000 {
compatible = "snps,dwcmshc-sdhci";
reg = <0xff 0xe7090000 0x0 0x10000
0xff 0xef014064 0x0 0x4>;
reg = <0xff 0xe7090000 0x0 0x10000>;
interrupt-parent = <&intc>;
interrupts = <64>;
interrupt-names = "sdhci0irq";
clocks = <&dummy_clock_sdhci>;
clock-names = "core";
clocks = <&clk CLKGEN_EMMC_SDIO_REF_CLK>,
<&miscsys_clk_gate CLKGEN_MISCSYS_EMMC_CLK>;
clock-names = "core", "bus";
};
sdhci1: sd@ffe70a0000 {
compatible = "snps,dwcmshc-sdhci";
reg = <0xff 0xe70a0000 0x0 0x10000
0xff 0xef014064 0x0 0x4>;
interrupt-parent = <&intc>;
interrupts = <71>;
interrupt-names = "sdhci1irq";
clocks = <&dummy_clock_sdhci>;
clock-names = "core";
compatible = "snps,dwcmshc-sdhci";
reg = <0xff 0xe70a0000 0x0 0x10000>;
interrupt-parent = <&intc>;
interrupts = <71>;
interrupt-names = "sdhci1irq";
clocks = <&clk CLKGEN_EMMC_SDIO_REF_CLK>,
<&miscsys_clk_gate CLKGEN_MISCSYS_EMMC_CLK>;
clock-names = "core", "bus";
};
hwspinlock: hwspinlock@ffefc10000 {
@@ -1402,7 +1513,8 @@
clock-names = "pclk", "aclk";
vha_clk_rate = <1000000000>;
ldo_vha-supply = <&npu>;
dma-mask = <0xf 0xffffffff>;
dma-mask = <0xff 0xffffffff>;
resets = <&rst LIGHT_RESET_NPU>;
status = "disabled";
};
@@ -1431,6 +1543,7 @@
clocks = <&vpsys_clk_gate LIGHT_VPSYS_FCE_ACLK>,
<&vpsys_clk_gate LIGHT_VPSYS_FCE_PCLK>;
clock-names = "aclk", "pclk";
resets = <&vpsys_rst LIGHT_RESET_FCE>;
dma-mask = <0xf 0xffffffff>;
status = "disabled";
};
@@ -1479,8 +1592,6 @@
#sound-dai-cells = <1>;
compatible = "light,light-i2s";
reg = <0xff 0xe7034000 0x0 0x4000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_audio_i2s0>;
light,mode = "i2s-master";
light,sel = "ap_i2s";
interrupt-parent = <&intc>;
@@ -1489,7 +1600,7 @@
dma-names = "tx", "rx";
light,dma_maxburst = <4>;
#dma-cells = <1>;
clocks = <&dummy_clock_apb>;
clocks = <&vosys_clk_gate LIGHT_CLKGEN_HDMI_I2S_CLK>;
clock-names = "pclk";
status = "disabled";
};
@@ -1505,11 +1616,11 @@
light,sel = "i2s0";
interrupt-parent = <&intc>;
interrupts = <174>;
dmas = <&dmac2 9>, <&dmac2 16>;
dmas = <&dmac2 9>, <&dmac2 8>;
dma-names = "tx", "rx";
light,dma_maxburst = <4>;
#dma-cells = <1>;
clocks = <&dummy_clock_apb>;
clocks = <&audiosys_clk_gate LIGHT_CLKGEN_AUDIO_I2S0>;
clock-names = "pclk";
status = "disabled";
};
@@ -1525,33 +1636,317 @@
light,sel = "i2s1";
interrupt-parent = <&intc>;
interrupts = <175>;
dmas = <&dmac2 11>, <&dmac2 17>;
dmas = <&dmac2 11>, <&dmac2 10>;
dma-names = "tx", "rx";
light,dma_maxburst = <4>;
#dma-cells = <1>;
clocks = <&dummy_clock_apb>;
clocks = <&audiosys_clk_gate LIGHT_CLKGEN_AUDIO_I2S1>;
clock-names = "pclk";
status = "disabled";
};
i2s3: audio_i2s3@0xffcb017000 {
i2s2: audio_i2s2@0xffcb016000 {
#sound-dai-cells = <1>;
compatible = "light,light-i2s";
reg = <0xff 0xcb017000 0x0 0x1000>;
reg = <0xff 0xcb016000 0x0 0x1000>;
audio-pin-regmap = <&audio_ioctrl>;
audio-cpr-regmap = <&audio_cpr>;
pinctrl-names = "default";
light,mode = "i2s-master";
light,sel = "i2s3";
light,sel = "i2s2";
interrupt-parent = <&intc>;
interrupts = <177>;
dmas = <&dmac2 14>, <&dmac2 16>;
interrupts = <176>;
dmas = <&dmac2 13>, <&dmac2 12>;
dma-names = "tx", "rx";
light,dma_maxburst = <4>;
#dma-cells = <1>;
clocks = <&dummy_clock_apb>;
clocks = <&audiosys_clk_gate LIGHT_CLKGEN_AUDIO_I2S2>;
clock-names = "pclk";
status = "disabled";
};
i2s_8ch_sd0: audio_i2s_8ch_sd0@0xffcb017000 {
#sound-dai-cells = <1>;
compatible = "light,light-i2s-8ch";
reg = <0xff 0xcb017000 0x0 0x1000>;
audio-cpr-regmap = <&audio_cpr>;
pinctrl-names = "default";
light,mode = "i2s-master";
light,sel = "i2s_8ch_sd0";
interrupt-parent = <&intc>;
interrupts = <177>;
dmas = <&dmac2 36>, <&dmac2 14>;
dma-names = "tx", "rx";
light,dma_maxburst = <4>;
#dma-cells = <1>;
clocks = <&audiosys_clk_gate LIGHT_CLKGEN_AUDIO_I2S8CH>;
clock-names = "pclk";
status = "disabled";
};
i2s_8ch_sd1: audio_i2s_8ch_sd1@0xffcb017000 {
#sound-dai-cells = <1>;
compatible = "light,light-i2s-8ch";
reg = <0xff 0xcb017000 0x0 0x1000>;
audio-cpr-regmap = <&audio_cpr>;
pinctrl-names = "default";
light,mode = "i2s-master";
light,sel = "i2s_8ch_sd1";
interrupt-parent = <&intc>;
interrupts = <177>;
dmas = <&dmac2 37>, <&dmac2 15>;
dma-names = "tx", "rx";
light,dma_maxburst = <4>;
#dma-cells = <1>;
clocks = <&audiosys_clk_gate LIGHT_CLKGEN_AUDIO_I2S8CH>;
clock-names = "pclk";
status = "disabled";
};
i2s_8ch_sd2: audio_i2s_8ch_sd2@0xffcb017000 {
#sound-dai-cells = <1>;
compatible = "light,light-i2s-8ch";
reg = <0xff 0xcb017000 0x0 0x1000>;
audio-cpr-regmap = <&audio_cpr>;
pinctrl-names = "default";
light,mode = "i2s-master";
light,sel = "i2s_8ch_sd2";
interrupt-parent = <&intc>;
interrupts = <177>;
dmas = <&dmac2 38>, <&dmac2 16>;
dma-names = "tx", "rx";
light,dma_maxburst = <4>;
#dma-cells = <1>;
clocks = <&audiosys_clk_gate LIGHT_CLKGEN_AUDIO_I2S8CH>;
clock-names = "pclk";
status = "disabled";
};
i2s_8ch_sd3: audio_i2s_8ch_sd3@0xffcb017000 {
#sound-dai-cells = <1>;
compatible = "light,light-i2s-8ch";
reg = <0xff 0xcb017000 0x0 0x1000>;
audio-cpr-regmap = <&audio_cpr>;
pinctrl-names = "default";
light,mode = "i2s-master";
light,sel = "i2s_8ch_sd3";
interrupt-parent = <&intc>;
interrupts = <177>;
dmas = <&dmac2 39>, <&dmac2 17>;
dma-names = "tx", "rx";
light,dma_maxburst = <4>;
#dma-cells = <1>;
clocks = <&audiosys_clk_gate LIGHT_CLKGEN_AUDIO_I2S8CH>;
clock-names = "pclk";
status = "disabled";
};
tdm_slot1: audio_tdm_slot1@0xffcb012000 {
#sound-dai-cells = <0>;
compatible = "light,light-tdm";
reg = <0xff 0xcb012000 0x0 0x1000>;
audio-pin-regmap = <&audio_ioctrl>;
audio-cpr-regmap = <&audio_cpr>;
pinctrl-names = "default";
light,mode = "i2s-master";
light,tdm_slots = <8>;
light,tdm_slot_num = <1>;
interrupt-parent = <&intc>;
interrupts = <178>;
dmas = <&dmac2 28>;
dma-names = "rx";
light,dma_maxburst = <4>;
#dma-cells = <1>;
clocks = <&audiosys_clk_gate LIGHT_CLKGEN_AUDIO_TDM>;
clock-names = "pclk";
status = "disabled";
};
tdm_slot2: audio_tdm_slot2@0xffcb012000 {
#sound-dai-cells = <0>;
compatible = "light,light-tdm";
reg = <0xff 0xcb012000 0x0 0x1000>;
audio-pin-regmap = <&audio_ioctrl>;
audio-cpr-regmap = <&audio_cpr>;
pinctrl-names = "default";
light,mode = "i2s-master";
light,tdm_slots = <8>;
light,tdm_slot_num = <2>;
interrupt-parent = <&intc>;
interrupts = <178>;
dmas = <&dmac2 29>;
dma-names = "rx";
light,dma_maxburst = <4>;
#dma-cells = <1>;
clocks = <&audiosys_clk_gate LIGHT_CLKGEN_AUDIO_TDM>;
clock-names = "pclk";
status = "disabled";
};
tdm_slot3: audio_tdm_slot3@0xffcb012000 {
#sound-dai-cells = <0>;
compatible = "light,light-tdm";
reg = <0xff 0xcb012000 0x0 0x1000>;
audio-pin-regmap = <&audio_ioctrl>;
audio-cpr-regmap = <&audio_cpr>;
pinctrl-names = "default";
light,mode = "i2s-master";
light,tdm_slots = <8>;
light,tdm_slot_num = <3>;
interrupt-parent = <&intc>;
interrupts = <178>;
dmas = <&dmac2 30>;
dma-names = "rx";
light,dma_maxburst = <4>;
#dma-cells = <1>;
clocks = <&audiosys_clk_gate LIGHT_CLKGEN_AUDIO_TDM>;
clock-names = "pclk";
status = "disabled";
};
tdm_slot4: audio_tdm_slot4@0xffcb012000 {
#sound-dai-cells = <0>;
compatible = "light,light-tdm";
reg = <0xff 0xcb012000 0x0 0x1000>;
audio-pin-regmap = <&audio_ioctrl>;
audio-cpr-regmap = <&audio_cpr>;
pinctrl-names = "default";
light,mode = "i2s-master";
light,tdm_slots = <8>;
light,tdm_slot_num = <4>;
interrupt-parent = <&intc>;
interrupts = <178>;
dmas = <&dmac2 31>;
dma-names = "rx";
light,dma_maxburst = <4>;
#dma-cells = <1>;
clocks = <&audiosys_clk_gate LIGHT_CLKGEN_AUDIO_TDM>;
clock-names = "pclk";
status = "disabled";
};
tdm_slot5: audio_tdm_slot5@0xffcb012000 {
#sound-dai-cells = <0>;
compatible = "light,light-tdm";
reg = <0xff 0xcb012000 0x0 0x1000>;
audio-pin-regmap = <&audio_ioctrl>;
audio-cpr-regmap = <&audio_cpr>;
pinctrl-names = "default";
light,mode = "i2s-master";
light,tdm_slots = <8>;
light,tdm_slot_num = <5>;
interrupt-parent = <&intc>;
interrupts = <178>;
dmas = <&dmac2 32>;
dma-names = "rx";
light,dma_maxburst = <4>;
#dma-cells = <1>;
clocks = <&audiosys_clk_gate LIGHT_CLKGEN_AUDIO_TDM>;
clock-names = "pclk";
status = "disabled";
};
tdm_slot6: audio_tdm_slot6@0xffcb012000 {
#sound-dai-cells = <0>;
compatible = "light,light-tdm";
reg = <0xff 0xcb012000 0x0 0x1000>;
audio-pin-regmap = <&audio_ioctrl>;
audio-cpr-regmap = <&audio_cpr>;
pinctrl-names = "default";
light,mode = "i2s-master";
light,tdm_slots = <8>;
light,tdm_slot_num = <6>;
interrupt-parent = <&intc>;
interrupts = <178>;
dmas = <&dmac2 33>;
dma-names = "rx";
light,dma_maxburst = <4>;
#dma-cells = <1>;
clocks = <&audiosys_clk_gate LIGHT_CLKGEN_AUDIO_TDM>;
clock-names = "pclk";
status = "disabled";
};
tdm_slot7: audio_tdm_slot7@0xffcb012000 {
#sound-dai-cells = <0>;
compatible = "light,light-tdm";
reg = <0xff 0xcb012000 0x0 0x1000>;
audio-pin-regmap = <&audio_ioctrl>;
audio-cpr-regmap = <&audio_cpr>;
pinctrl-names = "default";
light,mode = "i2s-master";
light,tdm_slots = <8>;
light,tdm_slot_num = <7>;
interrupt-parent = <&intc>;
interrupts = <178>;
dmas = <&dmac2 34>;
dma-names = "rx";
light,dma_maxburst = <4>;
#dma-cells = <1>;
clocks = <&audiosys_clk_gate LIGHT_CLKGEN_AUDIO_TDM>;
clock-names = "pclk";
status = "disabled";
};
tdm_slot8: audio_tdm_slot8@0xffcb012000 {
#sound-dai-cells = <0>;
compatible = "light,light-tdm";
reg = <0xff 0xcb012000 0x0 0x1000>;
audio-pin-regmap = <&audio_ioctrl>;
audio-cpr-regmap = <&audio_cpr>;
pinctrl-names = "default";
light,mode = "i2s-master";
light,tdm_slots = <8>;
light,tdm_slot_num = <8>;
interrupt-parent = <&intc>;
interrupts = <178>;
dmas = <&dmac2 35>;
dma-names = "rx";
light,dma_maxburst = <4>;
#dma-cells = <1>;
clocks = <&audiosys_clk_gate LIGHT_CLKGEN_AUDIO_TDM>;
clock-names = "pclk";
status = "disabled";
};
spdif0: audio_spdif0@0xffcb018000 {
#sound-dai-cells = <0>;
compatible = "light,light-spdif";
reg = <0xff 0xcb018000 0x0 0x1000>;
audio-pin-regmap = <&audio_ioctrl>;
audio-cpr-regmap = <&audio_cpr>;
pinctrl-names = "default";
interrupt-parent = <&intc>;
interrupts = <179>;
dmas = <&dmac2 25>, <&dmac2 24>;
dma-names = "tx", "rx";
light,dma_maxburst = <4>;
#dma-cells = <1>;
clocks = <&audiosys_clk_gate LIGHT_CLKGEN_AUDIO_SPDIF0>;
clock-names = "pclk";
id = <0>;
status = "disabled";
};
spdif1: audio_spdif1@0xffcb019000 {
#sound-dai-cells = <0>;
compatible = "light,light-spdif";
reg = <0xff 0xcb019000 0x0 0x1000>;
audio-pin-regmap = <&audio_ioctrl>;
audio-cpr-regmap = <&audio_cpr>;
pinctrl-names = "default";
interrupt-parent = <&intc>;
interrupts = <180>;
dmas = <&dmac2 27>, <&dmac2 26>;
dma-names = "tx", "rx";
light,dma_maxburst = <4>;
#dma-cells = <1>;
clocks = <&audiosys_clk_gate LIGHT_CLKGEN_AUDIO_SPDIF1>;
clock-names = "pclk";
id = <1>;
status = "disabled";
};
pvt: pvt@fffff4e000 {
compatible = "moortec,mr75203";
reg = <0xff 0xfff4e000 0x0 0x80>,
@@ -1569,8 +1964,13 @@
reg = <0xff 0xe7f20000 0x0 0x4000>;
interrupt-parent = <&intc>;
interrupts = <44>;
clocks = <&dummy_clock_apb>;
clocks = <&clk CLKGEN_I2C0_PCLK>;
clock-names = "pclk";
clock-frequency = <100000>;
i2c_mode = "dma";
dmas = <&dmac0 12>, <&dmac0 13>;
dma-names = "tx", "rx";
#dma-cells = <1>;
ss_hcnt = /bits/ 16 <0x104>;
ss_lcnt = /bits/ 16 <0xec>;
fs_hcnt = /bits/ 16 <0x37>;
@@ -1588,8 +1988,13 @@
reg = <0xff 0xe7f24000 0x0 0x4000>;
interrupt-parent = <&intc>;
interrupts = <45>;
clocks = <&dummy_clock_apb>;
clocks = <&clk CLKGEN_I2C1_PCLK>;
clock-names = "pclk";
clock-frequency = <100000>;
i2c_mode = "dma";
dmas = <&dmac0 14>, <&dmac0 15>;
dma-names = "tx", "rx";
#dma-cells = <1>;
ss_hcnt = /bits/ 16 <0x104>;
ss_lcnt = /bits/ 16 <0xec>;
fs_hcnt = /bits/ 16 <0x37>;
@@ -1607,8 +2012,13 @@
reg = <0xff 0xec00c000 0x0 0x4000>;
interrupt-parent = <&intc>;
interrupts = <46>;
clocks = <&dummy_clock_apb>;
clocks = <&clk CLKGEN_I2C2_PCLK>;
clock-names = "pclk";
clock-frequency = <100000>;
i2c_mode = "dma";
dmas = <&dmac0 16>, <&dmac0 17>;
dma-names = "tx", "rx";
#dma-cells = <1>;
ss_hcnt = /bits/ 16 <0x104>;
ss_lcnt = /bits/ 16 <0xec>;
fs_hcnt = /bits/ 16 <0x37>;
@@ -1628,8 +2038,13 @@
reg = <0xff 0xec014000 0x0 0x4000>;
interrupt-parent = <&intc>;
interrupts = <47>;
clocks = <&dummy_clock_apb>;
clocks = <&clk CLKGEN_I2C3_PCLK>;
clock-names = "pclk";
clock-frequency = <100000>;
i2c_mode = "dma";
dmas = <&dmac0 18>, <&dmac0 19>;
dma-names = "tx", "rx";
#dma-cells = <1>;
ss_hcnt = /bits/ 16 <0x104>;
ss_lcnt = /bits/ 16 <0xec>;
fs_hcnt = /bits/ 16 <0x37>;
@@ -1649,8 +2064,13 @@
reg = <0xff 0xe7f28000 0x0 0x4000>;
interrupt-parent = <&intc>;
interrupts = <48>;
clocks = <&dummy_clock_apb>;
clocks = <&clk CLKGEN_I2C4_PCLK>;
clock-names = "pclk";
clock-frequency = <100000>;
i2c_mode = "dma";
dmas = <&dmac0 20>, <&dmac0 21>;
dma-names = "tx", "rx";
#dma-cells = <1>;
ss_hcnt = /bits/ 16 <0x104>;
ss_lcnt = /bits/ 16 <0xec>;
fs_hcnt = /bits/ 16 <0x37>;
@@ -1672,6 +2092,10 @@
interrupts = <182>;
clocks = <&dummy_clock_apb>;
clock-frequency = <100000>;
i2c_mode = "dma";
dmas = <&dmac2 21>, <&dmac2 20>;
dma-names = "tx", "rx";
#dma-cells = <1>;
ss_hcnt = /bits/ 16 <0x82>;
ss_lcnt = /bits/ 16 <0x78>;
fs_hcnt = /bits/ 16 <0x37>;
@@ -1684,6 +2108,31 @@
#size-cells = <0>;
};
audio_i2c1: i2c@0xffcb01b000 {
compatible = "snps,designware-i2c";
reg = <0xff 0xcb01b000 0x0 0x1000>;
interrupt-parent = <&intc>;
interrupts = <183>;
clocks = <&dummy_clock_apb>;
clock-frequency = <100000>;
i2c_mode = "dma";
dmas = <&dmac2 23>, <&dmac2 22>;
dma-names = "tx", "rx";
#dma-cells = <1>;
ss_hcnt = /bits/ 16 <0x82>;
ss_lcnt = /bits/ 16 <0x78>;
fs_hcnt = /bits/ 16 <0x37>;
fs_lcnt = /bits/ 16 <0x42>;
fp_hcnt = /bits/ 16 <0x14>;
fp_lcnt = /bits/ 16 <0x1a>;
hs_hcnt = /bits/ 16 <0x5>;
hs_lcnt = /bits/ 16 <0x15>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
isp0: isp@ffe4100000 {
compatible = "thead,light-isp";
reg = <0xff 0xe4100000 0x0 0x10000>;
@@ -1963,6 +2412,11 @@
status = "disabled";
};
vvcam_sensor7: vvcam_sensor@7 {
compatible = "thead,light-vvcam-sensor";
status = "disabled";
};
xtensa_dsp: dsp@01{
compatible = "thead,dsp-hw-common";
reg = <0xff 0xef040000 0x0 0x001000 >; /*DSP_SYSREG(0x0000-0xFFF) */
@@ -2102,7 +2556,11 @@
reg = <0xff 0xff300000 0x0 0x40000>;
interrupt-parent = <&intc>;
interrupts = <144>,<145>,<146>,<147>;
clocks = <&dummy_clock_eip>;
clocks = <&miscsys_clk_gate CLKGEN_MISCSYS_EIP120SI_CLK>,
<&miscsys_clk_gate CLKGEN_MISCSYS_EIP120SII_CLK>,
<&miscsys_clk_gate CLKGEN_MISCSYS_EIP120SIII_CLK>,
<&miscsys_clk_gate CLKGEN_MISCSYS_EIP150B_HCLK>;
clock-names = "120si_clk","120sii_clk","120siii_clk","hclk";
status = "disabled";
};
@@ -2112,6 +2570,17 @@
interrupts = <215>; /* TEE INT SRC_7 */
};
light_event: light-event {
compatible = "thead,light-event";
aon-iram-regmap = <&aon_iram>;
status = "okay";
};
aon_suspend_ctrl: aon_suspend_ctrl {
compatible = "thead,light-aon-suspend-ctrl";
status = "okay";
};
visys_clk_gate: visys-clk-gate { /* VI_SYSREG_R */
compatible = "thead,visys-gate-controller";
visys-regmap = <&visys_reg>;
@@ -2139,6 +2608,22 @@
#clock-cells = <1>;
status = "okay";
};
audiosys_clk_gate: audiosys-clk-gate {
compatible = "thead,audiosys-gate-controller";
audiosys-regmap = <&audio_cpr>;
#clock-cells = <1>;
status = "okay";
};
miscsys_clk_gate: miscsys-clk-gate {
compatible = "thead,miscsys-gate-controller";
miscsys-regmap = <&miscsys_reg>;
tee-miscsys-regmap = <&tee_miscsys_reg>;
#clock-cells = <1>;
status = "okay";
};
};
};

7
arch/riscv/configs/defconfig
View File

@@ -17,6 +17,12 @@ CONFIG_PERF_EVENTS=y
CONFIG_SOC_THEAD=y
CONFIG_SMP=y
CONFIG_VECTOR=y
CONFIG_HOTPLUG_CPU=y
CONFIG_PM=y
CONFIG_CPU_IDLE=y
CONFIG_VIRTUALIZATION=y
CONFIG_KVM=m
CONFIG_JUMP_LABEL=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
CONFIG_PARTITION_ADVANCED=y
@@ -183,6 +189,5 @@ CONFIG_DEBUG_INFO=y
CONFIG_MAGIC_SYSRQ=y
CONFIG_DEBUG_FS=y
CONFIG_DETECT_HUNG_TASK=y
CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=60
CONFIG_DEBUG_ATOMIC_SLEEP=y
# CONFIG_RCU_TRACE is not set

3
arch/riscv/configs/fire_defconfig
View File

@@ -80,6 +80,7 @@ CONFIG_STMMAC_ETH=y
CONFIG_DWMAC_LIGHT=y
CONFIG_MICROSEMI_PHY=y
CONFIG_REALTEK_PHY=y
CONFIG_MARVELL_PHY=y
CONFIG_USB_USBNET=m
# CONFIG_USB_NET_AX8817X is not set
# CONFIG_USB_NET_AX88179_178A is not set
@@ -250,6 +251,7 @@ CONFIG_HWSPINLOCK=y
CONFIG_HWSPINLOCK_LIGHT=y
CONFIG_HWSPINLOCK_LIGHT_TEST=m
CONFIG_MAILBOX=y
CONFIG_EXTCON=y
CONFIG_IIO=y
CONFIG_IIO_SW_DEVICE=y
CONFIG_PWM=y
@@ -299,7 +301,6 @@ CONFIG_DEBUG_INFO=y
CONFIG_MAGIC_SYSRQ=y
CONFIG_DEBUG_FS=y
CONFIG_DETECT_HUNG_TASK=y
CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=60
CONFIG_DEBUG_ATOMIC_SLEEP=y
# CONFIG_RCU_TRACE is not set
CONFIG_OVERLAY_FS=y

4
arch/riscv/configs/fire_emu_defconfig
View File

@@ -17,6 +17,7 @@ CONFIG_PERF_EVENTS=y
CONFIG_FORCE_MAX_ZONEORDER=15
CONFIG_SOC_SIFIVE=y
CONFIG_SOC_THEAD=y
CONFIG_SOC_THEAD_LIGHT_EMU=y
CONFIG_SMP=y
CONFIG_VECTOR=y
CONFIG_VECTOR_0_7=y
@@ -80,6 +81,7 @@ CONFIG_STMMAC_ETH=y
CONFIG_DWMAC_LIGHT=y
CONFIG_MICROSEMI_PHY=y
CONFIG_REALTEK_PHY=y
CONFIG_MARVELL_PHY=y
CONFIG_USB_USBNET=m
# CONFIG_USB_NET_AX8817X is not set
# CONFIG_USB_NET_AX88179_178A is not set
@@ -250,6 +252,7 @@ CONFIG_HWSPINLOCK=y
CONFIG_HWSPINLOCK_LIGHT=y
CONFIG_HWSPINLOCK_LIGHT_TEST=m
CONFIG_MAILBOX=y
CONFIG_EXTCON=y
CONFIG_IIO=y
CONFIG_IIO_SW_DEVICE=y
CONFIG_PWM=y
@@ -299,7 +302,6 @@ CONFIG_DEBUG_INFO=y
CONFIG_MAGIC_SYSRQ=y
CONFIG_DEBUG_FS=y
CONFIG_DETECT_HUNG_TASK=y
CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=60
CONFIG_DEBUG_ATOMIC_SLEEP=y
# CONFIG_RCU_TRACE is not set
CONFIG_OVERLAY_FS=y

1
arch/riscv/configs/ice_defconfig
View File

@@ -180,6 +180,5 @@ CONFIG_DEBUG_INFO=y
CONFIG_MAGIC_SYSRQ=y
CONFIG_DEBUG_FS=y
CONFIG_DETECT_HUNG_TASK=y
CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=60
CONFIG_DEBUG_ATOMIC_SLEEP=y
# CONFIG_RCU_TRACE is not set

1
arch/riscv/configs/light-android_defconfig
View File

@@ -561,7 +561,6 @@ CONFIG_DYNAMIC_DEBUG=y
CONFIG_DEBUG_FS=y
CONFIG_PANIC_TIMEOUT=5
CONFIG_DETECT_HUNG_TASK=y
CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=60
CONFIG_SCHEDSTATS=y
CONFIG_DEBUG_ATOMIC_SLEEP=y
# CONFIG_GCC_PLUGINS is not set

32
arch/riscv/configs/light_defconfig
View File

@@ -3,6 +3,10 @@ CONFIG_POSIX_MQUEUE=y
CONFIG_NO_HZ_IDLE=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_PREEMPT=y
CONFIG_TASKSTATS=y
CONFIG_TASK_DELAY_ACCT=y
CONFIG_TASK_XACCT=y
CONFIG_TASK_IO_ACCOUNTING=y
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_CGROUPS=y
@@ -91,6 +95,7 @@ CONFIG_TUN=y
CONFIG_VIRTIO_NET=y
CONFIG_MACB=y
CONFIG_STMMAC_ETH=y
CONFIG_STMMAC_RX_ZERO_COPY=y
CONFIG_DWMAC_LIGHT=y
CONFIG_MICROSEMI_PHY=y
CONFIG_REALTEK_PHY=y
@@ -105,6 +110,7 @@ CONFIG_KEYBOARD_GPIO=y
# CONFIG_INPUT_MOUSE is not set
CONFIG_INPUT_TOUCHSCREEN=y
CONFIG_TOUCHSCREEN_GOODIX=y
CONFIG_TOUCHSCREEN_GT9XX=y
CONFIG_INPUT_MISC=y
CONFIG_INPUT_UINPUT=y
CONFIG_SERIAL_8250=y
@@ -198,6 +204,9 @@ CONFIG_DRM=y
CONFIG_DRM_PANEL_SIMPLE=y
CONFIG_DRM_PANEL_ILITEK_ILI9881C=y
CONFIG_DRM_PANEL_ILI9881D=y
CONFIG_DRM_PANEL_HX8394=y
CONFIG_DRM_PANEL_JADARD_JD9365DA_H3=y
CONFIG_DRM_PANEL_HX8279=y
CONFIG_DRM_VERISILICON=y
CONFIG_BACKLIGHT_CLASS_DEVICE=y
CONFIG_BACKLIGHT_PWM=y
@@ -264,6 +273,11 @@ CONFIG_HWSPINLOCK=y
CONFIG_HWSPINLOCK_LIGHT=y
CONFIG_HWSPINLOCK_LIGHT_TEST=m
CONFIG_MAILBOX=y
CONFIG_RPMSG=y
CONFIG_RPMSG_CHAR=y
CONFIG_RPMSG_VIRTIO=y
CONFIG_RPMSG_THEAD_LIGHT=y
CONFIG_EXTCON=y
CONFIG_IIO=y
CONFIG_IIO_SW_DEVICE=y
CONFIG_PWM=y
@@ -297,13 +311,21 @@ CONFIG_CRYPTO_AUTHENC=y
CONFIG_CRYPTO_DH=y
CONFIG_CRYPTO_CURVE25519=y
CONFIG_CRYPTO_CHACHA20POLY1305=y
CONFIG_CRYPTO_CBC=y
CONFIG_CRYPTO_CTR=y
CONFIG_CRYPTO_OFB=y
CONFIG_CRYPTO_MD5=y
CONFIG_CRYPTO_SHA512=y
CONFIG_CRYPTO_SHA3=y
CONFIG_CRYPTO_SM3=y
CONFIG_CRYPTO_DES=y
CONFIG_CRYPTO_SM4=y
CONFIG_CRYPTO_USER=y
CONFIG_CRYPTO_USER_API_HASH=y
CONFIG_CRYPTO_USER_API_SKCIPHER=y
CONFIG_CRYPTO_USER_API_RNG=y
# CONFIG_CRYPTO_USER_API_RNG_CAVP is not set
CONFIG_CRYPTO_USER_API_AEAD=y
CONFIG_DMA_CMA=y
CONFIG_DMA_PERNUMA_CMA=y
CONFIG_CMA_SIZE_MBYTES=32
@@ -313,13 +335,21 @@ CONFIG_DEBUG_INFO=y
CONFIG_MAGIC_SYSRQ=y
CONFIG_DEBUG_FS=y
CONFIG_DETECT_HUNG_TASK=y
CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=60
CONFIG_DEBUG_ATOMIC_SLEEP=y
# CONFIG_RCU_TRACE is not set
CONFIG_OVERLAY_FS=y
CONFIG_LOCKUP_DETECTOR=y
CONFIG_SOFTLOCKUP_DETECTOR=y
CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
CONFIG_SCHED_INFO=y
CONFIG_PM=y
# CONFIG_SUSPEND is not set
# CONFIG_PM_SLEEP is not set
CONFIG_PM_DEVFREQ=y
CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y
CONFIG_DEVFREQ_GOV_PERFORMANCE=y
CONFIG_DEVFREQ_GOV_POWERSAVE=y
CONFIG_DEVFREQ_GOV_USERSPACE=y
CONFIG_DEVFREQ_GOV_PASSIVE=y
CONFIG_PM_DEVFREQ_EVENT=y

1
arch/riscv/configs/light_emu_defconfig
View File

@@ -189,7 +189,6 @@ CONFIG_DYNAMIC_DEBUG=y
CONFIG_DEBUG_INFO=y
CONFIG_DEBUG_FS=y
CONFIG_DETECT_HUNG_TASK=y
CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=60
CONFIG_DEBUG_ATOMIC_SLEEP=y
# CONFIG_RCU_TRACE is not set
CONFIG_FORCE_MAX_ZONEORDER=15

5
arch/riscv/configs/rv32_defconfig
View File

@@ -18,6 +18,11 @@ CONFIG_SOC_SIFIVE=y
CONFIG_SOC_VIRT=y
CONFIG_ARCH_RV32I=y
CONFIG_SMP=y
CONFIG_HOTPLUG_CPU=y
CONFIG_PM=y
CONFIG_CPU_IDLE=y
CONFIG_VIRTUALIZATION=y
CONFIG_KVM=m
CONFIG_JUMP_LABEL=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y

1
arch/riscv/configs/vector_0_7_defconfig
View File

@@ -184,6 +184,5 @@ CONFIG_DEBUG_INFO=y
CONFIG_MAGIC_SYSRQ=y
CONFIG_DEBUG_FS=y
CONFIG_DETECT_HUNG_TASK=y
CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=60
CONFIG_DEBUG_ATOMIC_SLEEP=y
# CONFIG_RCU_TRACE is not set

3
arch/riscv/include/asm/Kbuild
View File

@@ -3,7 +3,8 @@ generic-y += early_ioremap.h
generic-y += extable.h
generic-y += flat.h
generic-y += kvm_para.h
generic-y += mcs_spinlock.h
generic-y += qspinlock.h
generic-y += qrwlock.h
generic-y += qrwlock_types.h
generic-y += user.h
generic-y += vmlinux.lds.h

27
arch/riscv/include/asm/asm.h
View File

@@ -66,4 +66,31 @@
#error "Unexpected __SIZEOF_SHORT__"
#endif
#ifdef __ASSEMBLY__
/* Common assembly source macros */
#ifdef CONFIG_XIP_KERNEL
.macro XIP_FIXUP_OFFSET reg
REG_L t0, _xip_fixup
add \reg, \reg, t0
.endm
.macro XIP_FIXUP_FLASH_OFFSET reg
la t1, __data_loc
li t0, XIP_OFFSET_MASK
and t1, t1, t0
li t1, XIP_OFFSET
sub t0, t0, t1
sub \reg, \reg, t0
.endm
_xip_fixup: .dword CONFIG_PHYS_RAM_BASE - CONFIG_XIP_PHYS_ADDR - XIP_OFFSET
#else
.macro XIP_FIXUP_OFFSET reg
.endm
.macro XIP_FIXUP_FLASH_OFFSET reg
.endm
#endif /* CONFIG_XIP_KERNEL */
#endif /* __ASSEMBLY__ */
#endif /* _ASM_RISCV_ASM_H */

24
arch/riscv/include/asm/cmpxchg.h
View File

@@ -11,12 +11,36 @@
#include <asm/barrier.h>
#include <asm/fence.h>
static inline ulong __xchg16_relaxed(ulong new, void *ptr)
{
ulong ret, tmp;
ulong shif = ((ulong)ptr & 2) ? 16 : 0;
ulong mask = 0xffff << shif;
ulong *__ptr = (ulong *)((ulong)ptr & ~2);
__asm__ __volatile__ (
"0: lr.w %0, %2\n"
" and %1, %0, %z3\n"
" or %1, %1, %z4\n"
" sc.w %1, %1, %2\n"
" bnez %1, 0b\n"
: "=&r" (ret), "=&r" (tmp), "+A" (*__ptr)
: "rJ" (~mask), "rJ" (new << shif)
: "memory");
return (ulong)((ret & mask) >> shif);
}
#define __xchg_relaxed(ptr, new, size) \
({ \
__typeof__(ptr) __ptr = (ptr); \
__typeof__(new) __new = (new); \
__typeof__(*(ptr)) __ret; \
switch (size) { \
case 2: { \
__ret = (__typeof__(*(ptr))) \
__xchg16_relaxed((ulong)__new, __ptr); \
break;} \
case 4: \
__asm__ __volatile__ ( \
" amoswap.w %0, %2, %1\n" \

25
arch/riscv/include/asm/cpu_ops_sbi.h Normal file
View File

@@ -0,0 +1,25 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2021 by Rivos Inc.
*/
#ifndef __ASM_CPU_OPS_SBI_H
#define __ASM_CPU_OPS_SBI_H
#ifndef __ASSEMBLY__
#include <linux/init.h>
#include <linux/sched.h>
#include <linux/threads.h>
/**
* struct sbi_hart_boot_data - Hart specific boot used during booting and
* cpu hotplug.
* @task_ptr: A pointer to the hart specific tp
* @stack_ptr: A pointer to the hart specific sp
*/
struct sbi_hart_boot_data {
void *task_ptr;
void *stack_ptr;
};
#endif
#endif /* ifndef __ASM_CPU_OPS_SBI_H */

1
arch/riscv/include/asm/io.h
View File

@@ -13,7 +13,6 @@
#include <linux/types.h>
#include <linux/pgtable.h>
#include <asm/mmiowb.h>
#include <asm/early_ioremap.h>
/*

2
arch/riscv/include/asm/mmio.h
View File

@@ -133,7 +133,7 @@ static inline u64 __raw_readq(const volatile void __iomem *addr)
#define __io_br() do {} while (0)
#define __io_ar(v) __asm__ __volatile__ ("fence i,r" : : : "memory")
#define __io_bw() __asm__ __volatile__ ("fence w,o" : : : "memory")
#define __io_aw() mmiowb_set_pending()
#define __io_aw() __asm__ __volatile__ ("fence o,w" : : : "memory")
#define readb(c) ({ u8 __v; __io_br(); __v = readb_cpu(c); __io_ar(__v); __v; })
#define readw(c) ({ u16 __v; __io_br(); __v = readw_cpu(c); __io_ar(__v); __v; })

15
arch/riscv/include/asm/mmiowb.h
View File

@@ -1,15 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _ASM_RISCV_MMIOWB_H
#define _ASM_RISCV_MMIOWB_H
/*
* "o,w" is sufficient to ensure that all writes to the device have completed
* before the write to the spinlock is allowed to commit.
*/
#define mmiowb() __asm__ __volatile__ ("fence o,w" : : : "memory");
#include <linux/smp.h>
#include <asm-generic/mmiowb.h>
#endif /* _ASM_RISCV_MMIOWB_H */

2
arch/riscv/include/asm/pgtable.h
View File

@@ -446,7 +446,7 @@ static inline pgprot_t pgprot_writecombine(pgprot_t _prot)
return __pgprot(prot);
}
#define pgprot_dmacoherent pgprot_writecombine
/*
* Encode and decode a swap entry
*

42
arch/riscv/include/asm/sbi.h
View File

@@ -61,13 +61,45 @@ enum sbi_ext_hsm_fid {
SBI_EXT_HSM_HART_START = 0,
SBI_EXT_HSM_HART_STOP,
SBI_EXT_HSM_HART_STATUS,
SBI_EXT_HSM_HART_SUSPEND,
};
enum sbi_hsm_hart_status {
SBI_HSM_HART_STATUS_STARTED = 0,
SBI_HSM_HART_STATUS_STOPPED,
SBI_HSM_HART_STATUS_START_PENDING,
SBI_HSM_HART_STATUS_STOP_PENDING,
enum sbi_hsm_hart_state {
SBI_HSM_STATE_STARTED = 0,
SBI_HSM_STATE_STOPPED,
SBI_HSM_STATE_START_PENDING,
SBI_HSM_STATE_STOP_PENDING,
SBI_HSM_STATE_SUSPENDED,
SBI_HSM_STATE_SUSPEND_PENDING,
SBI_HSM_STATE_RESUME_PENDING,
};
#define SBI_HSM_SUSP_BASE_MASK 0x7fffffff
#define SBI_HSM_SUSP_NON_RET_BIT 0x80000000
#define SBI_HSM_SUSP_PLAT_BASE 0x10000000
#define SBI_HSM_SUSPEND_RET_DEFAULT 0x00000000
#define SBI_HSM_SUSPEND_RET_PLATFORM SBI_HSM_SUSP_PLAT_BASE
#define SBI_HSM_SUSPEND_RET_LAST SBI_HSM_SUSP_BASE_MASK
#define SBI_HSM_SUSPEND_NON_RET_DEFAULT SBI_HSM_SUSP_NON_RET_BIT
#define SBI_HSM_SUSPEND_NON_RET_PLATFORM (SBI_HSM_SUSP_NON_RET_BIT | \
SBI_HSM_SUSP_PLAT_BASE)
#define SBI_HSM_SUSPEND_NON_RET_LAST (SBI_HSM_SUSP_NON_RET_BIT | \
SBI_HSM_SUSP_BASE_MASK)
enum sbi_ext_srst_fid {
SBI_EXT_SRST_RESET = 0,
};
enum sbi_srst_reset_type {
SBI_SRST_RESET_TYPE_SHUTDOWN = 0,
SBI_SRST_RESET_TYPE_COLD_REBOOT,
SBI_SRST_RESET_TYPE_WARM_REBOOT,
};
enum sbi_srst_reset_reason {
SBI_SRST_RESET_REASON_NONE = 0,
SBI_SRST_RESET_REASON_SYS_FAILURE,
};
#define SBI_SPEC_VERSION_DEFAULT 0x1

85
arch/riscv/include/asm/spinlock.h
View File

@@ -1,92 +1,9 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* 'Generic' ticket-lock implementation.
*
* It relies on atomic_fetch_add() having well defined forward progress
* guarantees under contention. If your architecture cannot provide this, stick
* to a test-and-set lock.
*
* It also relies on atomic_fetch_add() being safe vs smp_store_release() on a
* sub-word of the value. This is generally true for anything LL/SC although
* you'd be hard pressed to find anything useful in architecture specifications
* about this. If your architecture cannot do this you might be better off with
* a test-and-set.
*
* It further assumes atomic_*_release() + atomic_*_acquire() is RCpc and hence
* uses atomic_fetch_add() which is RCsc to create an RCsc hot path, along with
* a full fence after the spin to upgrade the otherwise-RCpc
* atomic_cond_read_acquire().
*
* The implementation uses smp_cond_load_acquire() to spin, so if the
* architecture has WFE like instructions to sleep instead of poll for word
* modifications be sure to implement that (see ARM64 for example).
*
*/
#ifndef __ASM_GENERIC_SPINLOCK_H
#define __ASM_GENERIC_SPINLOCK_H
#include <linux/atomic.h>
#include <asm/spinlock_types.h>
static __always_inline void arch_spin_lock(arch_spinlock_t *lock)
{
u32 val = atomic_fetch_add(1<<16, lock);
u16 ticket = val >> 16;
if (ticket == (u16)val)
return;
/*
* atomic_cond_read_acquire() is RCpc, but rather than defining a
* custom cond_read_rcsc() here we just emit a full fence. We only
* need the prior reads before subsequent writes ordering from
* smb_mb(), but as atomic_cond_read_acquire() just emits reads and we
* have no outstanding writes due to the atomic_fetch_add() the extra
* orderings are free.
*/
atomic_cond_read_acquire(lock, ticket == (u16)VAL);
smp_mb();
}
static __always_inline bool arch_spin_trylock(arch_spinlock_t *lock)
{
u32 old = atomic_read(lock);
if ((old >> 16) != (old & 0xffff))
return false;
return atomic_try_cmpxchg(lock, &old, old + (1<<16)); /* SC, for RCsc */
}
static __always_inline void arch_spin_unlock(arch_spinlock_t *lock)
{
u16 *ptr = (u16 *)lock + IS_ENABLED(CONFIG_CPU_BIG_ENDIAN);
u32 val = atomic_read(lock);
smp_store_release(ptr, (u16)val + 1);
}
static __always_inline int arch_spin_is_locked(arch_spinlock_t *lock)
{
u32 val = atomic_read(lock);
return ((val >> 16) != (val & 0xffff));
}
static __always_inline int arch_spin_is_contended(arch_spinlock_t *lock)
{
u32 val = atomic_read(lock);
return (s16)((val >> 16) - (val & 0xffff)) > 1;
}
static __always_inline int arch_spin_value_unlocked(arch_spinlock_t lock)
{
return !arch_spin_is_locked(&lock);
}
#include <asm-generic/qspinlock.h>
#include <asm/qrwlock.h>
#endif /* __ASM_GENERIC_SPINLOCK_H */

12
arch/riscv/include/asm/spinlock_types.h
View File

@@ -3,15 +3,7 @@
#ifndef __ASM_GENERIC_SPINLOCK_TYPES_H
#define __ASM_GENERIC_SPINLOCK_TYPES_H
#include <linux/types.h>
typedef atomic_t arch_spinlock_t;
/*
* qrwlock_types depends on arch_spinlock_t, so we must typedef that before the
* include.
*/
#include <asm/qrwlock_types.h>
#define __ARCH_SPIN_LOCK_UNLOCKED ATOMIC_INIT(0)
#include <asm-generic/qspinlock_types.h>
#include <asm-generic/qrwlock_types.h>
#endif /* __ASM_GENERIC_SPINLOCK_TYPES_H */

36
arch/riscv/include/asm/suspend.h Normal file
View File

@@ -0,0 +1,36 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2021 Western Digital Corporation or its affiliates.
* Copyright (c) 2022 Ventana Micro Systems Inc.
*/
#ifndef _ASM_RISCV_SUSPEND_H
#define _ASM_RISCV_SUSPEND_H
#include <asm/ptrace.h>
struct suspend_context {
/* Saved and restored by low-level functions */
struct pt_regs regs;
/* Saved and restored by high-level functions */
unsigned long scratch;
unsigned long tvec;
unsigned long ie;
#ifdef CONFIG_MMU
unsigned long satp;
#endif
};
/* Low-level CPU suspend entry function */
int __cpu_suspend_enter(struct suspend_context *context);
/* High-level CPU suspend which will save context and call finish() */
int cpu_suspend(unsigned long arg,
int (*finish)(unsigned long arg,
unsigned long entry,
unsigned long context));
/* Low-level CPU resume entry function */
int __cpu_resume_enter(unsigned long hartid, unsigned long context);
#endif

2
arch/riscv/kernel/Makefile
View File

@@ -48,6 +48,8 @@ obj-$(CONFIG_SMP) += cpu_ops_spinwait.o
obj-$(CONFIG_MODULES) += module.o
obj-$(CONFIG_MODULE_SECTIONS) += module-sections.o
obj-$(CONFIG_CPU_PM) += suspend_entry.o suspend.o
obj-$(CONFIG_FUNCTION_TRACER) += mcount.o ftrace.o
obj-$(CONFIG_DYNAMIC_FTRACE) += mcount-dyn.o

165
arch/riscv/kernel/asm-offsets.c
View File

@@ -10,6 +10,10 @@
#include <linux/sched.h>
#include <asm/thread_info.h>
#include <asm/ptrace.h>
#include <asm/cpu_ops_sbi.h>
#include <asm/suspend.h>
void asm_offsets(void);
void asm_offsets(void)
{
@@ -149,6 +153,162 @@ void asm_offsets(void)
OFFSET(PT_BADADDR, pt_regs, badaddr);
OFFSET(PT_CAUSE, pt_regs, cause);
OFFSET(SUSPEND_CONTEXT_REGS, suspend_context, regs);
#if 0
OFFSET(KVM_ARCH_GUEST_ZERO, kvm_vcpu_arch, guest_context.zero);
OFFSET(KVM_ARCH_GUEST_RA, kvm_vcpu_arch, guest_context.ra);
OFFSET(KVM_ARCH_GUEST_SP, kvm_vcpu_arch, guest_context.sp);
OFFSET(KVM_ARCH_GUEST_GP, kvm_vcpu_arch, guest_context.gp);
OFFSET(KVM_ARCH_GUEST_TP, kvm_vcpu_arch, guest_context.tp);
OFFSET(KVM_ARCH_GUEST_T0, kvm_vcpu_arch, guest_context.t0);
OFFSET(KVM_ARCH_GUEST_T1, kvm_vcpu_arch, guest_context.t1);
OFFSET(KVM_ARCH_GUEST_T2, kvm_vcpu_arch, guest_context.t2);
OFFSET(KVM_ARCH_GUEST_S0, kvm_vcpu_arch, guest_context.s0);
OFFSET(KVM_ARCH_GUEST_S1, kvm_vcpu_arch, guest_context.s1);
OFFSET(KVM_ARCH_GUEST_A0, kvm_vcpu_arch, guest_context.a0);
OFFSET(KVM_ARCH_GUEST_A1, kvm_vcpu_arch, guest_context.a1);
OFFSET(KVM_ARCH_GUEST_A2, kvm_vcpu_arch, guest_context.a2);
OFFSET(KVM_ARCH_GUEST_A3, kvm_vcpu_arch, guest_context.a3);
OFFSET(KVM_ARCH_GUEST_A4, kvm_vcpu_arch, guest_context.a4);
OFFSET(KVM_ARCH_GUEST_A5, kvm_vcpu_arch, guest_context.a5);
OFFSET(KVM_ARCH_GUEST_A6, kvm_vcpu_arch, guest_context.a6);
OFFSET(KVM_ARCH_GUEST_A7, kvm_vcpu_arch, guest_context.a7);
OFFSET(KVM_ARCH_GUEST_S2, kvm_vcpu_arch, guest_context.s2);
OFFSET(KVM_ARCH_GUEST_S3, kvm_vcpu_arch, guest_context.s3);
OFFSET(KVM_ARCH_GUEST_S4, kvm_vcpu_arch, guest_context.s4);
OFFSET(KVM_ARCH_GUEST_S5, kvm_vcpu_arch, guest_context.s5);
OFFSET(KVM_ARCH_GUEST_S6, kvm_vcpu_arch, guest_context.s6);
OFFSET(KVM_ARCH_GUEST_S7, kvm_vcpu_arch, guest_context.s7);
OFFSET(KVM_ARCH_GUEST_S8, kvm_vcpu_arch, guest_context.s8);
OFFSET(KVM_ARCH_GUEST_S9, kvm_vcpu_arch, guest_context.s9);
OFFSET(KVM_ARCH_GUEST_S10, kvm_vcpu_arch, guest_context.s10);
OFFSET(KVM_ARCH_GUEST_S11, kvm_vcpu_arch, guest_context.s11);
OFFSET(KVM_ARCH_GUEST_T3, kvm_vcpu_arch, guest_context.t3);
OFFSET(KVM_ARCH_GUEST_T4, kvm_vcpu_arch, guest_context.t4);
OFFSET(KVM_ARCH_GUEST_T5, kvm_vcpu_arch, guest_context.t5);
OFFSET(KVM_ARCH_GUEST_T6, kvm_vcpu_arch, guest_context.t6);
OFFSET(KVM_ARCH_GUEST_SEPC, kvm_vcpu_arch, guest_context.sepc);
OFFSET(KVM_ARCH_GUEST_SSTATUS, kvm_vcpu_arch, guest_context.sstatus);
OFFSET(KVM_ARCH_GUEST_HSTATUS, kvm_vcpu_arch, guest_context.hstatus);
OFFSET(KVM_ARCH_GUEST_SCOUNTEREN, kvm_vcpu_arch, guest_csr.scounteren);
OFFSET(KVM_ARCH_HOST_ZERO, kvm_vcpu_arch, host_context.zero);
OFFSET(KVM_ARCH_HOST_RA, kvm_vcpu_arch, host_context.ra);
OFFSET(KVM_ARCH_HOST_SP, kvm_vcpu_arch, host_context.sp);
OFFSET(KVM_ARCH_HOST_GP, kvm_vcpu_arch, host_context.gp);
OFFSET(KVM_ARCH_HOST_TP, kvm_vcpu_arch, host_context.tp);
OFFSET(KVM_ARCH_HOST_T0, kvm_vcpu_arch, host_context.t0);
OFFSET(KVM_ARCH_HOST_T1, kvm_vcpu_arch, host_context.t1);
OFFSET(KVM_ARCH_HOST_T2, kvm_vcpu_arch, host_context.t2);
OFFSET(KVM_ARCH_HOST_S0, kvm_vcpu_arch, host_context.s0);
OFFSET(KVM_ARCH_HOST_S1, kvm_vcpu_arch, host_context.s1);
OFFSET(KVM_ARCH_HOST_A0, kvm_vcpu_arch, host_context.a0);
OFFSET(KVM_ARCH_HOST_A1, kvm_vcpu_arch, host_context.a1);
OFFSET(KVM_ARCH_HOST_A2, kvm_vcpu_arch, host_context.a2);
OFFSET(KVM_ARCH_HOST_A3, kvm_vcpu_arch, host_context.a3);
OFFSET(KVM_ARCH_HOST_A4, kvm_vcpu_arch, host_context.a4);
OFFSET(KVM_ARCH_HOST_A5, kvm_vcpu_arch, host_context.a5);
OFFSET(KVM_ARCH_HOST_A6, kvm_vcpu_arch, host_context.a6);
OFFSET(KVM_ARCH_HOST_A7, kvm_vcpu_arch, host_context.a7);
OFFSET(KVM_ARCH_HOST_S2, kvm_vcpu_arch, host_context.s2);
OFFSET(KVM_ARCH_HOST_S3, kvm_vcpu_arch, host_context.s3);
OFFSET(KVM_ARCH_HOST_S4, kvm_vcpu_arch, host_context.s4);
OFFSET(KVM_ARCH_HOST_S5, kvm_vcpu_arch, host_context.s5);
OFFSET(KVM_ARCH_HOST_S6, kvm_vcpu_arch, host_context.s6);
OFFSET(KVM_ARCH_HOST_S7, kvm_vcpu_arch, host_context.s7);
OFFSET(KVM_ARCH_HOST_S8, kvm_vcpu_arch, host_context.s8);
OFFSET(KVM_ARCH_HOST_S9, kvm_vcpu_arch, host_context.s9);
OFFSET(KVM_ARCH_HOST_S10, kvm_vcpu_arch, host_context.s10);
OFFSET(KVM_ARCH_HOST_S11, kvm_vcpu_arch, host_context.s11);
OFFSET(KVM_ARCH_HOST_T3, kvm_vcpu_arch, host_context.t3);
OFFSET(KVM_ARCH_HOST_T4, kvm_vcpu_arch, host_context.t4);
OFFSET(KVM_ARCH_HOST_T5, kvm_vcpu_arch, host_context.t5);
OFFSET(KVM_ARCH_HOST_T6, kvm_vcpu_arch, host_context.t6);
OFFSET(KVM_ARCH_HOST_SEPC, kvm_vcpu_arch, host_context.sepc);
OFFSET(KVM_ARCH_HOST_SSTATUS, kvm_vcpu_arch, host_context.sstatus);
OFFSET(KVM_ARCH_HOST_HSTATUS, kvm_vcpu_arch, host_context.hstatus);
OFFSET(KVM_ARCH_HOST_SSCRATCH, kvm_vcpu_arch, host_sscratch);
OFFSET(KVM_ARCH_HOST_STVEC, kvm_vcpu_arch, host_stvec);
OFFSET(KVM_ARCH_HOST_SCOUNTEREN, kvm_vcpu_arch, host_scounteren);
OFFSET(KVM_ARCH_TRAP_SEPC, kvm_cpu_trap, sepc);
OFFSET(KVM_ARCH_TRAP_SCAUSE, kvm_cpu_trap, scause);
OFFSET(KVM_ARCH_TRAP_STVAL, kvm_cpu_trap, stval);
OFFSET(KVM_ARCH_TRAP_HTVAL, kvm_cpu_trap, htval);
OFFSET(KVM_ARCH_TRAP_HTINST, kvm_cpu_trap, htinst);
/* F extension */
OFFSET(KVM_ARCH_FP_F_F0, kvm_cpu_context, fp.f.f[0]);
OFFSET(KVM_ARCH_FP_F_F1, kvm_cpu_context, fp.f.f[1]);
OFFSET(KVM_ARCH_FP_F_F2, kvm_cpu_context, fp.f.f[2]);
OFFSET(KVM_ARCH_FP_F_F3, kvm_cpu_context, fp.f.f[3]);
OFFSET(KVM_ARCH_FP_F_F4, kvm_cpu_context, fp.f.f[4]);
OFFSET(KVM_ARCH_FP_F_F5, kvm_cpu_context, fp.f.f[5]);
OFFSET(KVM_ARCH_FP_F_F6, kvm_cpu_context, fp.f.f[6]);
OFFSET(KVM_ARCH_FP_F_F7, kvm_cpu_context, fp.f.f[7]);
OFFSET(KVM_ARCH_FP_F_F8, kvm_cpu_context, fp.f.f[8]);
OFFSET(KVM_ARCH_FP_F_F9, kvm_cpu_context, fp.f.f[9]);
OFFSET(KVM_ARCH_FP_F_F10, kvm_cpu_context, fp.f.f[10]);
OFFSET(KVM_ARCH_FP_F_F11, kvm_cpu_context, fp.f.f[11]);
OFFSET(KVM_ARCH_FP_F_F12, kvm_cpu_context, fp.f.f[12]);
OFFSET(KVM_ARCH_FP_F_F13, kvm_cpu_context, fp.f.f[13]);
OFFSET(KVM_ARCH_FP_F_F14, kvm_cpu_context, fp.f.f[14]);
OFFSET(KVM_ARCH_FP_F_F15, kvm_cpu_context, fp.f.f[15]);
OFFSET(KVM_ARCH_FP_F_F16, kvm_cpu_context, fp.f.f[16]);
OFFSET(KVM_ARCH_FP_F_F17, kvm_cpu_context, fp.f.f[17]);
OFFSET(KVM_ARCH_FP_F_F18, kvm_cpu_context, fp.f.f[18]);
OFFSET(KVM_ARCH_FP_F_F19, kvm_cpu_context, fp.f.f[19]);
OFFSET(KVM_ARCH_FP_F_F20, kvm_cpu_context, fp.f.f[20]);
OFFSET(KVM_ARCH_FP_F_F21, kvm_cpu_context, fp.f.f[21]);
OFFSET(KVM_ARCH_FP_F_F22, kvm_cpu_context, fp.f.f[22]);
OFFSET(KVM_ARCH_FP_F_F23, kvm_cpu_context, fp.f.f[23]);
OFFSET(KVM_ARCH_FP_F_F24, kvm_cpu_context, fp.f.f[24]);
OFFSET(KVM_ARCH_FP_F_F25, kvm_cpu_context, fp.f.f[25]);
OFFSET(KVM_ARCH_FP_F_F26, kvm_cpu_context, fp.f.f[26]);
OFFSET(KVM_ARCH_FP_F_F27, kvm_cpu_context, fp.f.f[27]);
OFFSET(KVM_ARCH_FP_F_F28, kvm_cpu_context, fp.f.f[28]);
OFFSET(KVM_ARCH_FP_F_F29, kvm_cpu_context, fp.f.f[29]);
OFFSET(KVM_ARCH_FP_F_F30, kvm_cpu_context, fp.f.f[30]);
OFFSET(KVM_ARCH_FP_F_F31, kvm_cpu_context, fp.f.f[31]);
OFFSET(KVM_ARCH_FP_F_FCSR, kvm_cpu_context, fp.f.fcsr);
/* D extension */
OFFSET(KVM_ARCH_FP_D_F0, kvm_cpu_context, fp.d.f[0]);
OFFSET(KVM_ARCH_FP_D_F1, kvm_cpu_context, fp.d.f[1]);
OFFSET(KVM_ARCH_FP_D_F2, kvm_cpu_context, fp.d.f[2]);
OFFSET(KVM_ARCH_FP_D_F3, kvm_cpu_context, fp.d.f[3]);
OFFSET(KVM_ARCH_FP_D_F4, kvm_cpu_context, fp.d.f[4]);
OFFSET(KVM_ARCH_FP_D_F5, kvm_cpu_context, fp.d.f[5]);
OFFSET(KVM_ARCH_FP_D_F6, kvm_cpu_context, fp.d.f[6]);
OFFSET(KVM_ARCH_FP_D_F7, kvm_cpu_context, fp.d.f[7]);
OFFSET(KVM_ARCH_FP_D_F8, kvm_cpu_context, fp.d.f[8]);
OFFSET(KVM_ARCH_FP_D_F9, kvm_cpu_context, fp.d.f[9]);
OFFSET(KVM_ARCH_FP_D_F10, kvm_cpu_context, fp.d.f[10]);
OFFSET(KVM_ARCH_FP_D_F11, kvm_cpu_context, fp.d.f[11]);
OFFSET(KVM_ARCH_FP_D_F12, kvm_cpu_context, fp.d.f[12]);
OFFSET(KVM_ARCH_FP_D_F13, kvm_cpu_context, fp.d.f[13]);
OFFSET(KVM_ARCH_FP_D_F14, kvm_cpu_context, fp.d.f[14]);
OFFSET(KVM_ARCH_FP_D_F15, kvm_cpu_context, fp.d.f[15]);
OFFSET(KVM_ARCH_FP_D_F16, kvm_cpu_context, fp.d.f[16]);
OFFSET(KVM_ARCH_FP_D_F17, kvm_cpu_context, fp.d.f[17]);
OFFSET(KVM_ARCH_FP_D_F18, kvm_cpu_context, fp.d.f[18]);
OFFSET(KVM_ARCH_FP_D_F19, kvm_cpu_context, fp.d.f[19]);
OFFSET(KVM_ARCH_FP_D_F20, kvm_cpu_context, fp.d.f[20]);
OFFSET(KVM_ARCH_FP_D_F21, kvm_cpu_context, fp.d.f[21]);
OFFSET(KVM_ARCH_FP_D_F22, kvm_cpu_context, fp.d.f[22]);
OFFSET(KVM_ARCH_FP_D_F23, kvm_cpu_context, fp.d.f[23]);
OFFSET(KVM_ARCH_FP_D_F24, kvm_cpu_context, fp.d.f[24]);
OFFSET(KVM_ARCH_FP_D_F25, kvm_cpu_context, fp.d.f[25]);
OFFSET(KVM_ARCH_FP_D_F26, kvm_cpu_context, fp.d.f[26]);
OFFSET(KVM_ARCH_FP_D_F27, kvm_cpu_context, fp.d.f[27]);
OFFSET(KVM_ARCH_FP_D_F28, kvm_cpu_context, fp.d.f[28]);
OFFSET(KVM_ARCH_FP_D_F29, kvm_cpu_context, fp.d.f[29]);
OFFSET(KVM_ARCH_FP_D_F30, kvm_cpu_context, fp.d.f[30]);
OFFSET(KVM_ARCH_FP_D_F31, kvm_cpu_context, fp.d.f[31]);
OFFSET(KVM_ARCH_FP_D_FCSR, kvm_cpu_context, fp.d.fcsr);
#endif
/*
* THREAD_{F,X}* might be larger than a S-type offset can handle, but
* these are used in performance-sensitive assembly so we can't resort
@@ -500,4 +660,9 @@ void asm_offsets(void)
* ensures the alignment is sane.
*/
DEFINE(PT_SIZE_ON_STACK, ALIGN(sizeof(struct pt_regs), STACK_ALIGN));
#if 0
OFFSET(KERNEL_MAP_VIRT_ADDR, kernel_mapping, virt_addr);
#endif
OFFSET(SBI_HART_BOOT_TASK_PTR_OFFSET, sbi_hart_boot_data, task_ptr);
OFFSET(SBI_HART_BOOT_STACK_PTR_OFFSET, sbi_hart_boot_data, stack_ptr);
}

26
arch/riscv/kernel/cpu_ops_sbi.c
View File

@@ -7,13 +7,22 @@
#include <linux/init.h>
#include <linux/mm.h>
#include <linux/sched/task_stack.h>
#include <asm/cpu_ops.h>
#include <asm/cpu_ops_sbi.h>
#include <asm/sbi.h>
#include <asm/smp.h>
extern char secondary_start_sbi[];
const struct cpu_operations cpu_ops_sbi;
/*
* Ordered booting via HSM brings one cpu at a time. However, cpu hotplug can
* be invoked from multiple threads in parallel. Define a per cpu data
* to handle that.
*/
DEFINE_PER_CPU(struct sbi_hart_boot_data, boot_data);
static int sbi_hsm_hart_start(unsigned long hartid, unsigned long saddr,
unsigned long priv)
{
@@ -55,14 +64,19 @@ static int sbi_hsm_hart_get_status(unsigned long hartid)
static int sbi_cpu_start(unsigned int cpuid, struct task_struct *tidle)
{
int rc;
unsigned long boot_addr = __pa_symbol(secondary_start_sbi);
int hartid = cpuid_to_hartid_map(cpuid);
unsigned long hsm_data;
struct sbi_hart_boot_data *bdata = &per_cpu(boot_data, cpuid);
cpu_update_secondary_bootdata(cpuid, tidle);
rc = sbi_hsm_hart_start(hartid, boot_addr, 0);
return rc;
/* Make sure tidle is updated */
smp_mb();
bdata->task_ptr = tidle;
bdata->stack_ptr = task_stack_page(tidle) + THREAD_SIZE;
/* Make sure boot data is updated */
smp_mb();
hsm_data = __pa(bdata);
return sbi_hsm_hart_start(hartid, boot_addr, hsm_data);
}
static int sbi_cpu_prepare(unsigned int cpuid)
@@ -97,7 +111,7 @@ static int sbi_cpu_is_stopped(unsigned int cpuid)
rc = sbi_hsm_hart_get_status(hartid);
if (rc == SBI_HSM_HART_STATUS_STOPPED)
if (rc == SBI_HSM_STATE_STOPPED)
return 0;
return rc;
}

26
arch/riscv/kernel/head.S
View File

@@ -10,6 +10,7 @@
#include <asm/thread_info.h>
#include <asm/page.h>
#include <asm/csr.h>
#include <asm/cpu_ops_sbi.h>
#include <asm/hwcap.h>
#include <asm/image.h>
#include "efi-header.S"
@@ -67,7 +68,8 @@ pe_head_start:
.align 2
#ifdef CONFIG_MMU
relocate:
.global relocate_enable_mmu
relocate_enable_mmu:
/* Relocate return address */
li a1, PAGE_OFFSET
la a2, _start
@@ -142,13 +144,15 @@ secondary_start_sbi:
la a3, .Lsecondary_park
csrw CSR_TVEC, a3
slli a3, a0, LGREG
la a4, __cpu_up_stack_pointer
la a5, __cpu_up_task_pointer
add a4, a3, a4
add a5, a3, a5
REG_L sp, (a4)
REG_L tp, (a5)
/* a0 contains the hartid & a1 contains boot data */
li a2, SBI_HART_BOOT_TASK_PTR_OFFSET
XIP_FIXUP_OFFSET a2
add a2, a2, a1
REG_L tp, (a2)
li a3, SBI_HART_BOOT_STACK_PTR_OFFSET
XIP_FIXUP_OFFSET a3
add a3, a3, a1
REG_L sp, (a3)
.global secondary_start_common
secondary_start_common:
@@ -156,7 +160,8 @@ secondary_start_common:
#ifdef CONFIG_MMU
/* Enable virtual memory and relocate to virtual address */
la a0, swapper_pg_dir
call relocate
XIP_FIXUP_OFFSET a0
call relocate_enable_mmu
#endif
call setup_trap_vector
tail smp_callin
@@ -266,7 +271,8 @@ clear_bss_done:
call setup_vm
#ifdef CONFIG_MMU
la a0, early_pg_dir
call relocate
XIP_FIXUP_OFFSET a0
call relocate_enable_mmu
#endif /* CONFIG_MMU */
call setup_trap_vector

5
arch/riscv/kernel/machine_kexec.c
View File

@@ -179,9 +179,10 @@ machine_crash_shutdown(struct pt_regs *regs)
{
local_irq_disable();
#ifdef CONFIG_SMP
/* shutdown non-crashing cpus */
crash_smp_send_stop();
#endif
crash_save_cpu(regs, smp_processor_id());
machine_kexec_mask_interrupts();
@@ -211,8 +212,10 @@ machine_kexec(struct kimage *image)
void *control_code_buffer = page_address(image->control_code_page);
riscv_kexec_method kexec_method = NULL;
#ifdef CONFIG_SMP
WARN(smp_crash_stop_failed(),
"Some CPUs may be stale, kdump will be unreliable.\n");
#endif
if (image->type != KEXEC_TYPE_CRASH)
kexec_method = control_code_buffer;

6
arch/riscv/kernel/perf_callchain.c
View File

@@ -75,13 +75,13 @@ void perf_callchain_user(struct perf_callchain_entry_ctx *entry,
fp = user_backtrace(entry, fp, 0);
}
bool fill_callchain(unsigned long pc, void *entry)
bool fill_callchain(unsigned long pc, unsigned long regs, void *entry)
{
return perf_callchain_store(entry, pc) == 0;
return perf_callchain_store(entry, pc);
}
void notrace walk_stackframe(struct task_struct *task,
struct pt_regs *regs, bool (*fn)(unsigned long, void *), void *arg);
struct pt_regs *regs, bool (*fn)(unsigned long, unsigned long, void *), void *arg);
void perf_callchain_kernel(struct perf_callchain_entry_ctx *entry,
struct pt_regs *regs)
{

5
arch/riscv/kernel/probes/decode-insn.c
View File

@@ -38,11 +38,10 @@ riscv_probe_decode_insn(probe_opcode_t *addr, struct arch_probe_insn *api)
RISCV_INSN_REJECTED(c_ebreak, insn);
#endif
RISCV_INSN_REJECTED(auipc, insn);
RISCV_INSN_REJECTED(branch, insn);
RISCV_INSN_SET_SIMULATE(jal, insn);
RISCV_INSN_SET_SIMULATE(jalr, insn);
RISCV_INSN_SET_SIMULATE(auipc, insn);
RISCV_INSN_SET_SIMULATE(branch, insn);
return INSN_GOOD;
}

18
arch/riscv/kernel/probes/kprobes.c
View File

@@ -46,6 +46,21 @@ static void __kprobes arch_simulate_insn(struct kprobe *p, struct pt_regs *regs)
post_kprobe_handler(kcb, regs);
}
static bool __kprobes arch_check_kprobe(struct kprobe *p)
{
unsigned long tmp = (unsigned long)p->addr - p->offset;
unsigned long addr = (unsigned long)p->addr;
while (tmp <= addr) {
if (tmp == addr)
return true;
tmp += GET_INSN_LENGTH(*(u16 *)tmp);
}
return false;
}
int __kprobes arch_prepare_kprobe(struct kprobe *p)
{
unsigned long probe_addr = (unsigned long)p->addr;
@@ -56,6 +71,9 @@ int __kprobes arch_prepare_kprobe(struct kprobe *p)
return -EINVAL;
}
if (!arch_check_kprobe(p))
return -EILSEQ;
/* copy instruction */
p->opcode = le32_to_cpu(*p->addr);

112
arch/riscv/kernel/probes/simulate-insn.c
View File

@@ -83,3 +83,115 @@ bool __kprobes simulate_jalr(u32 opcode, unsigned long addr, struct pt_regs *reg
return ret;
}
#define auipc_rd_idx(opcode) \
((opcode >> 7) & 0x1f)
#define auipc_imm(opcode) \
((((opcode) >> 12) & 0xfffff) << 12)
#if __riscv_xlen == 64
#define auipc_offset(opcode) sign_extend64(auipc_imm(opcode), 31)
#elif __riscv_xlen == 32
#define auipc_offset(opcode) auipc_imm(opcode)
#else
#error "Unexpected __riscv_xlen"
#endif
bool __kprobes simulate_auipc(u32 opcode, unsigned long addr, struct pt_regs *regs)
{
/*
* auipc instruction:
* 31 12 11 7 6 0
* | imm[31:12] | rd | opcode |
* 20 5 7
*/
u32 rd_idx = auipc_rd_idx(opcode);
unsigned long rd_val = addr + auipc_offset(opcode);
if (!rv_insn_reg_set_val(regs, rd_idx, rd_val))
return false;
instruction_pointer_set(regs, addr + 4);
return true;
}
#define branch_rs1_idx(opcode) \
(((opcode) >> 15) & 0x1f)
#define branch_rs2_idx(opcode) \
(((opcode) >> 20) & 0x1f)
#define branch_funct3(opcode) \
(((opcode) >> 12) & 0x7)
#define branch_imm(opcode) \
(((((opcode) >> 8) & 0xf ) << 1) | \
((((opcode) >> 25) & 0x3f) << 5) | \
((((opcode) >> 7) & 0x1 ) << 11) | \
((((opcode) >> 31) & 0x1 ) << 12))
#define branch_offset(opcode) \
sign_extend32((branch_imm(opcode)), 12)
#define BRANCH_BEQ 0x0
#define BRANCH_BNE 0x1
#define BRANCH_BLT 0x4
#define BRANCH_BGE 0x5
#define BRANCH_BLTU 0x6
#define BRANCH_BGEU 0x7
bool __kprobes simulate_branch(u32 opcode, unsigned long addr, struct pt_regs *regs)
{
/*
* branch instructions:
* 31 30 25 24 20 19 15 14 12 11 8 7 6 0
* | imm[12] | imm[10:5] | rs2 | rs1 | funct3 | imm[4:1] | imm[11] | opcode |
* 1 6 5 5 3 4 1 7
* imm[12|10:5] rs2 rs1 000 imm[4:1|11] 1100011 BEQ
* imm[12|10:5] rs2 rs1 001 imm[4:1|11] 1100011 BNE
* imm[12|10:5] rs2 rs1 100 imm[4:1|11] 1100011 BLT
* imm[12|10:5] rs2 rs1 101 imm[4:1|11] 1100011 BGE
* imm[12|10:5] rs2 rs1 110 imm[4:1|11] 1100011 BLTU
* imm[12|10:5] rs2 rs1 111 imm[4:1|11] 1100011 BGEU
*/
s32 offset;
s32 offset_tmp;
unsigned long rs1_val;
unsigned long rs2_val;
if (!rv_insn_reg_get_val(regs, branch_rs1_idx(opcode), &rs1_val) ||
!rv_insn_reg_get_val(regs, branch_rs2_idx(opcode), &rs2_val))
return false;
offset_tmp = branch_offset(opcode);
switch (branch_funct3(opcode)) {
case BRANCH_BEQ:
offset = (rs1_val == rs2_val) ? offset_tmp : 4;
break;
case BRANCH_BNE:
offset = (rs1_val != rs2_val) ? offset_tmp : 4;
break;
case BRANCH_BLT:
offset = ((long)rs1_val < (long)rs2_val) ? offset_tmp : 4;
break;
case BRANCH_BGE:
offset = ((long)rs1_val >= (long)rs2_val) ? offset_tmp : 4;
break;
case BRANCH_BLTU:
offset = (rs1_val < rs2_val) ? offset_tmp : 4;
break;
case BRANCH_BGEU:
offset = (rs1_val >= rs2_val) ? offset_tmp : 4;
break;
default:
return false;
}
instruction_pointer_set(regs, addr + offset);
return true;
}

3
arch/riscv/kernel/process.c
View File

@@ -23,6 +23,7 @@
#include <asm/string.h>
#include <asm/switch_to.h>
#include <asm/thread_info.h>
#include <asm/cpuidle.h>
register unsigned long gp_in_global __asm__("gp");
@@ -37,7 +38,7 @@ extern asmlinkage void ret_from_kernel_thread(void);
void arch_cpu_idle(void)
{
wait_for_interrupt();
cpu_do_idle();
raw_local_irq_enable();
}

1
arch/riscv/kernel/ptrace.c
View File

@@ -97,6 +97,7 @@ static int riscv_vr_get(struct task_struct *target,
struct __riscv_v_state *vstate = &target->thread.vstate;
membuf_write(&to, vstate, offsetof(struct __riscv_v_state, vtype));
membuf_store(&to, vstate->vtype);
return membuf_zero(&to, 4); // explicitly pad
}

87
arch/riscv/kernel/suspend.c Normal file
View File

@@ -0,0 +1,87 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2021 Western Digital Corporation or its affiliates.
* Copyright (c) 2022 Ventana Micro Systems Inc.
*/
#include <linux/ftrace.h>
#include <asm/csr.h>
#include <asm/suspend.h>
static void suspend_save_csrs(struct suspend_context *context)
{
context->scratch = csr_read(CSR_SCRATCH);
context->tvec = csr_read(CSR_TVEC);
context->ie = csr_read(CSR_IE);
/*
* No need to save/restore IP CSR (i.e. MIP or SIP) because:
*
* 1. For no-MMU (M-mode) kernel, the bits in MIP are set by
* external devices (such as interrupt controller, timer, etc).
* 2. For MMU (S-mode) kernel, the bits in SIP are set by
* M-mode firmware and external devices (such as interrupt
* controller, etc).
*/
#ifdef CONFIG_MMU
context->satp = csr_read(CSR_SATP);
#endif
}
static void suspend_restore_csrs(struct suspend_context *context)
{
csr_write(CSR_SCRATCH, context->scratch);
csr_write(CSR_TVEC, context->tvec);
csr_write(CSR_IE, context->ie);
#ifdef CONFIG_MMU
csr_write(CSR_SATP, context->satp);
#endif
}
int cpu_suspend(unsigned long arg,
int (*finish)(unsigned long arg,
unsigned long entry,
unsigned long context))
{
int rc = 0;
struct suspend_context context = { 0 };
/* Finisher should be non-NULL */
if (!finish)
return -EINVAL;
/* Save additional CSRs*/
suspend_save_csrs(&context);
/*
* Function graph tracer state gets incosistent when the kernel
* calls functions that never return (aka finishers) hence disable
* graph tracing during their execution.
*/
pause_graph_tracing();
/* Save context on stack */
if (__cpu_suspend_enter(&context)) {
/* Call the finisher */
rc = finish(arg, __pa_symbol(__cpu_resume_enter),
(ulong)&context);
/*
* Should never reach here, unless the suspend finisher
* fails. Successful cpu_suspend() should return from
* __cpu_resume_entry()
*/
if (!rc)
rc = -EOPNOTSUPP;
}
/* Enable function graph tracer */
unpause_graph_tracing();
/* Restore additional CSRs */
suspend_restore_csrs(&context);
return rc;
}

124
arch/riscv/kernel/suspend_entry.S Normal file
View File

@@ -0,0 +1,124 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2021 Western Digital Corporation or its affiliates.
* Copyright (c) 2022 Ventana Micro Systems Inc.
*/
#include <linux/linkage.h>
#include <asm/asm.h>
#include <asm/asm-offsets.h>
#include <asm/csr.h>
.text
.altmacro
.option norelax
ENTRY(__cpu_suspend_enter)
/* Save registers (except A0 and T0-T6) */
REG_S ra, (SUSPEND_CONTEXT_REGS + PT_RA)(a0)
REG_S sp, (SUSPEND_CONTEXT_REGS + PT_SP)(a0)
REG_S gp, (SUSPEND_CONTEXT_REGS + PT_GP)(a0)
REG_S tp, (SUSPEND_CONTEXT_REGS + PT_TP)(a0)
REG_S s0, (SUSPEND_CONTEXT_REGS + PT_S0)(a0)
REG_S s1, (SUSPEND_CONTEXT_REGS + PT_S1)(a0)
REG_S a1, (SUSPEND_CONTEXT_REGS + PT_A1)(a0)
REG_S a2, (SUSPEND_CONTEXT_REGS + PT_A2)(a0)
REG_S a3, (SUSPEND_CONTEXT_REGS + PT_A3)(a0)
REG_S a4, (SUSPEND_CONTEXT_REGS + PT_A4)(a0)
REG_S a5, (SUSPEND_CONTEXT_REGS + PT_A5)(a0)
REG_S a6, (SUSPEND_CONTEXT_REGS + PT_A6)(a0)
REG_S a7, (SUSPEND_CONTEXT_REGS + PT_A7)(a0)
REG_S s2, (SUSPEND_CONTEXT_REGS + PT_S2)(a0)
REG_S s3, (SUSPEND_CONTEXT_REGS + PT_S3)(a0)
REG_S s4, (SUSPEND_CONTEXT_REGS + PT_S4)(a0)
REG_S s5, (SUSPEND_CONTEXT_REGS + PT_S5)(a0)
REG_S s6, (SUSPEND_CONTEXT_REGS + PT_S6)(a0)
REG_S s7, (SUSPEND_CONTEXT_REGS + PT_S7)(a0)
REG_S s8, (SUSPEND_CONTEXT_REGS + PT_S8)(a0)
REG_S s9, (SUSPEND_CONTEXT_REGS + PT_S9)(a0)
REG_S s10, (SUSPEND_CONTEXT_REGS + PT_S10)(a0)
REG_S s11, (SUSPEND_CONTEXT_REGS + PT_S11)(a0)
/* Save CSRs */
csrr t0, CSR_EPC
REG_S t0, (SUSPEND_CONTEXT_REGS + PT_EPC)(a0)
csrr t0, CSR_STATUS
REG_S t0, (SUSPEND_CONTEXT_REGS + PT_STATUS)(a0)
csrr t0, CSR_TVAL
REG_S t0, (SUSPEND_CONTEXT_REGS + PT_BADADDR)(a0)
csrr t0, CSR_CAUSE
REG_S t0, (SUSPEND_CONTEXT_REGS + PT_CAUSE)(a0)
/* Return non-zero value */
li a0, 1
/* Return to C code */
ret
END(__cpu_suspend_enter)
ENTRY(__cpu_resume_enter)
/* Load the global pointer */
.option push
.option norelax
la gp, __global_pointer$
.option pop
#ifdef CONFIG_MMU
/* Save A0 and A1 */
add t0, a0, zero
add t1, a1, zero
/* Enable MMU */
la a0, swapper_pg_dir
XIP_FIXUP_OFFSET a0
call relocate_enable_mmu
/* Restore A0 and A1 */
add a0, t0, zero
add a1, t1, zero
#endif
/* Make A0 point to suspend context */
add a0, a1, zero
/* Restore CSRs */
REG_L t0, (SUSPEND_CONTEXT_REGS + PT_EPC)(a0)
csrw CSR_EPC, t0
REG_L t0, (SUSPEND_CONTEXT_REGS + PT_STATUS)(a0)
csrw CSR_STATUS, t0
REG_L t0, (SUSPEND_CONTEXT_REGS + PT_BADADDR)(a0)
csrw CSR_TVAL, t0
REG_L t0, (SUSPEND_CONTEXT_REGS + PT_CAUSE)(a0)
csrw CSR_CAUSE, t0
/* Restore registers (except A0 and T0-T6) */
REG_L ra, (SUSPEND_CONTEXT_REGS + PT_RA)(a0)
REG_L sp, (SUSPEND_CONTEXT_REGS + PT_SP)(a0)
REG_L gp, (SUSPEND_CONTEXT_REGS + PT_GP)(a0)
REG_L tp, (SUSPEND_CONTEXT_REGS + PT_TP)(a0)
REG_L s0, (SUSPEND_CONTEXT_REGS + PT_S0)(a0)
REG_L s1, (SUSPEND_CONTEXT_REGS + PT_S1)(a0)
REG_L a1, (SUSPEND_CONTEXT_REGS + PT_A1)(a0)
REG_L a2, (SUSPEND_CONTEXT_REGS + PT_A2)(a0)
REG_L a3, (SUSPEND_CONTEXT_REGS + PT_A3)(a0)
REG_L a4, (SUSPEND_CONTEXT_REGS + PT_A4)(a0)
REG_L a5, (SUSPEND_CONTEXT_REGS + PT_A5)(a0)
REG_L a6, (SUSPEND_CONTEXT_REGS + PT_A6)(a0)
REG_L a7, (SUSPEND_CONTEXT_REGS + PT_A7)(a0)
REG_L s2, (SUSPEND_CONTEXT_REGS + PT_S2)(a0)
REG_L s3, (SUSPEND_CONTEXT_REGS + PT_S3)(a0)
REG_L s4, (SUSPEND_CONTEXT_REGS + PT_S4)(a0)
REG_L s5, (SUSPEND_CONTEXT_REGS + PT_S5)(a0)
REG_L s6, (SUSPEND_CONTEXT_REGS + PT_S6)(a0)
REG_L s7, (SUSPEND_CONTEXT_REGS + PT_S7)(a0)
REG_L s8, (SUSPEND_CONTEXT_REGS + PT_S8)(a0)
REG_L s9, (SUSPEND_CONTEXT_REGS + PT_S9)(a0)
REG_L s10, (SUSPEND_CONTEXT_REGS + PT_S10)(a0)
REG_L s11, (SUSPEND_CONTEXT_REGS + PT_S11)(a0)
/* Return zero value */
add a0, zero, zero
/* Return to C code */
ret
END(__cpu_resume_enter)

105
arch/riscv/kvm/vcpu_sbi_hsm.c Normal file
View File

@@ -0,0 +1,105 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2021 Western Digital Corporation or its affiliates.
*
* Authors:
* Atish Patra <atish.patra@wdc.com>
*/
#include <linux/errno.h>
#include <linux/err.h>
#include <linux/kvm_host.h>
#include <asm/csr.h>
#include <asm/sbi.h>
#include <asm/kvm_vcpu_sbi.h>
static int kvm_sbi_hsm_vcpu_start(struct kvm_vcpu *vcpu)
{
struct kvm_cpu_context *reset_cntx;
struct kvm_cpu_context *cp = &vcpu->arch.guest_context;
struct kvm_vcpu *target_vcpu;
unsigned long target_vcpuid = cp->a0;
target_vcpu = kvm_get_vcpu_by_id(vcpu->kvm, target_vcpuid);
if (!target_vcpu)
return -EINVAL;
if (!target_vcpu->arch.power_off)
return -EALREADY;
reset_cntx = &target_vcpu->arch.guest_reset_context;
/* start address */
reset_cntx->sepc = cp->a1;
/* target vcpu id to start */
reset_cntx->a0 = target_vcpuid;
/* private data passed from kernel */
reset_cntx->a1 = cp->a2;
kvm_make_request(KVM_REQ_VCPU_RESET, target_vcpu);
kvm_riscv_vcpu_power_on(target_vcpu);
return 0;
}
static int kvm_sbi_hsm_vcpu_stop(struct kvm_vcpu *vcpu)
{
if (vcpu->arch.power_off)
return -EINVAL;
kvm_riscv_vcpu_power_off(vcpu);
return 0;
}
static int kvm_sbi_hsm_vcpu_get_status(struct kvm_vcpu *vcpu)
{
struct kvm_cpu_context *cp = &vcpu->arch.guest_context;
unsigned long target_vcpuid = cp->a0;
struct kvm_vcpu *target_vcpu;
target_vcpu = kvm_get_vcpu_by_id(vcpu->kvm, target_vcpuid);
if (!target_vcpu)
return -EINVAL;
if (!target_vcpu->arch.power_off)
return SBI_HSM_STATE_STARTED;
else
return SBI_HSM_STATE_STOPPED;
}
static int kvm_sbi_ext_hsm_handler(struct kvm_vcpu *vcpu, struct kvm_run *run,
unsigned long *out_val,
struct kvm_cpu_trap *utrap,
bool *exit)
{
int ret = 0;
struct kvm_cpu_context *cp = &vcpu->arch.guest_context;
struct kvm *kvm = vcpu->kvm;
unsigned long funcid = cp->a6;
switch (funcid) {
case SBI_EXT_HSM_HART_START:
mutex_lock(&kvm->lock);
ret = kvm_sbi_hsm_vcpu_start(vcpu);
mutex_unlock(&kvm->lock);
break;
case SBI_EXT_HSM_HART_STOP:
ret = kvm_sbi_hsm_vcpu_stop(vcpu);
break;
case SBI_EXT_HSM_HART_STATUS:
ret = kvm_sbi_hsm_vcpu_get_status(vcpu);
if (ret >= 0) {
*out_val = ret;
ret = 0;
}
break;
default:
ret = -EOPNOTSUPP;
}
return ret;
}
const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_hsm = {
.extid_start = SBI_EXT_HSM,
.extid_end = SBI_EXT_HSM,
.handler = kvm_sbi_ext_hsm_handler,
};

5
drivers/block/zram/zram_drv.c
View File

@@ -1385,14 +1385,13 @@ compress_again:
__GFP_KSWAPD_RECLAIM |
__GFP_NOWARN |
__GFP_HIGHMEM |
__GFP_MOVABLE |
__GFP_CMA);
__GFP_MOVABLE);
if (!handle) {
zcomp_stream_put(zram->comp);
atomic64_inc(&zram->stats.writestall);
handle = zs_malloc(zram->mem_pool, comp_len,
GFP_NOIO | __GFP_HIGHMEM |
__GFP_MOVABLE | __GFP_CMA);
__GFP_MOVABLE);
if (handle)
goto compress_again;
return -ENOMEM;

49
drivers/clk/thead/clk-light-fm.c
View File

@@ -50,6 +50,7 @@ static u32 share_cnt_spi_clk_en;
static u32 share_cnt_uart0_clk_en;
static u32 share_cnt_uart2_clk_en;
static u32 share_cnt_i2c2_clk_en;
static u32 share_cnt_i2c3_clk_en;
static u32 share_cnt_peri_i2s_clk_en;
static u32 share_cnt_qspi1_clk_en;
static u32 share_cnt_uart1_clk_en;
@@ -378,31 +379,31 @@ static int light_clocks_probe(struct platform_device *pdev)
clks[AONSYS_BUS_CLK] = thead_clk_fixed("aonsys_hclk", 101606400); //from sys_pll, maybe change ?
/* Light Fullmask AP MUX */
clks[CPU_PLL0_BYPASS] = thead_light_clk_mux_flags("cpu_pll0_bypass", ap_base + 0x4, 30, 1, cpu_pll0_bypass_sels, ARRAY_SIZE(cpu_pll0_bypass_sels), CLK_SET_RATE_PARENT);
clks[CPU_PLL1_BYPASS] = thead_light_clk_mux_flags("cpu_pll1_bypass", ap_base + 0x14, 30, 1, cpu_pll1_bypass_sels, ARRAY_SIZE(cpu_pll1_bypass_sels), CLK_SET_RATE_PARENT);
clks[GMAC_PLL_BYPASS] = thead_light_clk_mux_flags("gmac_pll_bypass", ap_base + 0x24, 30, 1, gmac_pll_bypass_sels, ARRAY_SIZE(gmac_pll_bypass_sels), CLK_SET_RATE_PARENT);
clks[VIDEO_PLL_BYPASS] = thead_light_clk_mux_flags("video_pll_bypass", ap_base + 0x34, 30, 1, video_pll_bypass_sels, ARRAY_SIZE(video_pll_bypass_sels), CLK_SET_RATE_PARENT);
clks[TEE_PLL_BYPASS] = thead_light_clk_mux_flags("tee_pll_bypass", ap_base + 0x64, 30, 1, tee_pll_bypass_sels, ARRAY_SIZE(tee_pll_bypass_sels), CLK_SET_RATE_PARENT);
clks[DPU0_PLL_BYPASS] = thead_light_clk_mux_flags("dpu0_pll_bypass", ap_base + 0x44, 30, 1, dpu0_pll_bypass_sels, ARRAY_SIZE(dpu0_pll_bypass_sels), CLK_SET_RATE_PARENT);
clks[DPU1_PLL_BYPASS] = thead_light_clk_mux_flags("dpu1_pll_bypass", ap_base + 0x54, 30, 1, dpu1_pll_bypass_sels, ARRAY_SIZE(dpu1_pll_bypass_sels), CLK_SET_RATE_PARENT);
clks[CPU_PLL0_BYPASS] = thead_light_clk_mux_flags("cpu_pll0_bypass", ap_base + 0x4, 30, 1, cpu_pll0_bypass_sels, ARRAY_SIZE(cpu_pll0_bypass_sels), CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT);
clks[CPU_PLL1_BYPASS] = thead_light_clk_mux_flags("cpu_pll1_bypass", ap_base + 0x14, 30, 1, cpu_pll1_bypass_sels, ARRAY_SIZE(cpu_pll1_bypass_sels), CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT);
clks[GMAC_PLL_BYPASS] = thead_light_clk_mux_flags("gmac_pll_bypass", ap_base + 0x24, 30, 1, gmac_pll_bypass_sels, ARRAY_SIZE(gmac_pll_bypass_sels), CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT);
clks[VIDEO_PLL_BYPASS] = thead_light_clk_mux_flags("video_pll_bypass", ap_base + 0x34, 30, 1, video_pll_bypass_sels, ARRAY_SIZE(video_pll_bypass_sels), CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT);
clks[TEE_PLL_BYPASS] = thead_light_clk_mux_flags("tee_pll_bypass", ap_base + 0x64, 30, 1, tee_pll_bypass_sels, ARRAY_SIZE(tee_pll_bypass_sels), CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT);
clks[DPU0_PLL_BYPASS] = thead_light_clk_mux_flags("dpu0_pll_bypass", ap_base + 0x44, 30, 1, dpu0_pll_bypass_sels, ARRAY_SIZE(dpu0_pll_bypass_sels), CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT);
clks[DPU1_PLL_BYPASS] = thead_light_clk_mux_flags("dpu1_pll_bypass", ap_base + 0x54, 30, 1, dpu1_pll_bypass_sels, ARRAY_SIZE(dpu1_pll_bypass_sels), CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT);
clks[AHB2_CPUSYS_HCLK] = thead_light_clk_mux_flags("ahb2_cpusys_hclk", ap_base + 0x120, 5, 1, ahb2_cpusys_hclk_sels, ARRAY_SIZE(ahb2_cpusys_hclk_sels), CLK_SET_RATE_PARENT);
clks[C910_CCLK_I0] = thead_light_clk_mux_flags("c910_cclk_i0", ap_base + 0x100, 1, 1, c910_cclk_i0_sels, ARRAY_SIZE(c910_cclk_i0_sels), CLK_SET_RATE_PARENT);
clks[C910_CCLK] = thead_light_clk_mux_flags("c910_cclk", ap_base + 0x100, 0, 1, c910_cclk_sels, ARRAY_SIZE(c910_cclk_sels), CLK_SET_RATE_PARENT);
clks[CFG_AXI_ACLK] = thead_light_clk_mux_flags("cfg_axi_aclk", ap_base + 0x138, 5, 1, cfg_axi_aclk_sels, ARRAY_SIZE(cfg_axi_aclk_sels), CLK_SET_RATE_PARENT);
clks[AHB2_CPUSYS_HCLK] = thead_light_clk_mux_flags("ahb2_cpusys_hclk", ap_base + 0x120, 5, 1, ahb2_cpusys_hclk_sels, ARRAY_SIZE(ahb2_cpusys_hclk_sels), CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT);
clks[C910_CCLK_I0] = thead_light_clk_mux_flags("c910_cclk_i0", ap_base + 0x100, 1, 1, c910_cclk_i0_sels, ARRAY_SIZE(c910_cclk_i0_sels), CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT);
clks[C910_CCLK] = thead_light_clk_mux_flags("c910_cclk", ap_base + 0x100, 0, 1, c910_cclk_sels, ARRAY_SIZE(c910_cclk_sels), CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT);
clks[CFG_AXI_ACLK] = thead_light_clk_mux_flags("cfg_axi_aclk", ap_base + 0x138, 5, 1, cfg_axi_aclk_sels, ARRAY_SIZE(cfg_axi_aclk_sels), CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT);
if (teesys)
clks[TEESYS_HCLK] = thead_light_clk_mux_flags("teesys_hclk", ap_base + 0x1cc, 13, 1, teesys_hclk_sels, ARRAY_SIZE(teesys_hclk_sels), CLK_SET_RATE_PARENT); //just for teesys!!!
clks[TEESYS_HCLK] = thead_light_clk_mux_flags("teesys_hclk", ap_base + 0x1cc, 13, 1, teesys_hclk_sels, ARRAY_SIZE(teesys_hclk_sels), CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT); //just for teesys!!!
clks[PERISYS_AHB_HCLK] = thead_light_clk_mux_flags("perisys_ahb_hclk", ap_base + 0x140, 5, 1, perisys_ahb_hclk_sels, ARRAY_SIZE(perisys_ahb_hclk_sels), CLK_SET_RATE_PARENT);
clks[CLK_OUT_1] = thead_light_clk_mux_flags("clk_out_1", ap_base + 0x1b4, 4, 1, clk_out_1_sels, ARRAY_SIZE(clk_out_1_sels), CLK_SET_RATE_PARENT);
clks[CLK_OUT_2] = thead_light_clk_mux_flags("clk_out_2", ap_base + 0x1b8, 4, 1, clk_out_2_sels, ARRAY_SIZE(clk_out_2_sels), CLK_SET_RATE_PARENT);
clks[CLK_OUT_3] = thead_light_clk_mux_flags("clk_out_3", ap_base + 0x1bc, 4, 1, clk_out_3_sels, ARRAY_SIZE(clk_out_3_sels), CLK_SET_RATE_PARENT);
clks[CLK_OUT_4] = thead_light_clk_mux_flags("clk_out_4", ap_base + 0x1c0, 4, 1, clk_out_4_sels, ARRAY_SIZE(clk_out_4_sels), CLK_SET_RATE_PARENT);
clks[PERI_I2S_SRC_CLK] = thead_light_clk_mux_flags("peri_i2s_src_clk", ap_base + 0x1f0, 0, 1, peri_i2s_src_clk_sels, ARRAY_SIZE(peri_i2s_src_clk_sels), CLK_SET_RATE_PARENT);
clks[PERISYS_AHB_HCLK] = thead_light_clk_mux_flags("perisys_ahb_hclk", ap_base + 0x140, 5, 1, perisys_ahb_hclk_sels, ARRAY_SIZE(perisys_ahb_hclk_sels), CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT);
clks[CLK_OUT_1] = thead_light_clk_mux_flags("clk_out_1", ap_base + 0x1b4, 4, 1, clk_out_1_sels, ARRAY_SIZE(clk_out_1_sels), CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT);
clks[CLK_OUT_2] = thead_light_clk_mux_flags("clk_out_2", ap_base + 0x1b8, 4, 1, clk_out_2_sels, ARRAY_SIZE(clk_out_2_sels), CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT);
clks[CLK_OUT_3] = thead_light_clk_mux_flags("clk_out_3", ap_base + 0x1bc, 4, 1, clk_out_3_sels, ARRAY_SIZE(clk_out_3_sels), CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT);
clks[CLK_OUT_4] = thead_light_clk_mux_flags("clk_out_4", ap_base + 0x1c0, 4, 1, clk_out_4_sels, ARRAY_SIZE(clk_out_4_sels), CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT);
clks[PERI_I2S_SRC_CLK] = thead_light_clk_mux_flags("peri_i2s_src_clk", ap_base + 0x1f0, 0, 1, peri_i2s_src_clk_sels, ARRAY_SIZE(peri_i2s_src_clk_sels), CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT);
clks[NPU_CCLK] = thead_light_clk_mux_flags("npu_cclk", ap_base + 0x1c8, 6, 1, npu_cclk_sels, ARRAY_SIZE(npu_cclk_sels), CLK_SET_RATE_PARENT);
clks[CFG_APB_PCLK] = thead_light_clk_mux_flags("cfg_apb_pclk", ap_base + 0x1c4, 7, 1, cfg_apb_pclk_sels, ARRAY_SIZE(cfg_apb_pclk_sels), CLK_SET_RATE_PARENT);
clks[UART_SCLK] = thead_light_clk_mux_flags("uart_sclk", ap_base + 0x210, 0, 1, uart_sclk_sels, ARRAY_SIZE(uart_sclk_sels), CLK_SET_RATE_PARENT);
clks[CFG_APB_PCLK] = thead_light_clk_mux_flags("cfg_apb_pclk", ap_base + 0x1c4, 7, 1, cfg_apb_pclk_sels, ARRAY_SIZE(cfg_apb_pclk_sels), CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT);
clks[UART_SCLK] = thead_light_clk_mux_flags("uart_sclk", ap_base + 0x210, 0, 1, uart_sclk_sels, ARRAY_SIZE(uart_sclk_sels), CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT);
/* Light Fullmask AP Divider */
clks[AHB2_CPUSYS_HCLK_OUT_DIV] = thead_clk_light_divider("ahb2_cpusys_hclk_out_div", "gmac_pll_fout1ph0", ap_base + 0x120, 0, 3, 4, MUX_TYPE_DIV, 2, 7);
@@ -436,7 +437,7 @@ static int light_clocks_probe(struct platform_device *pdev)
/* Light Fullmask PLL FOUT */
clks[GMAC_PLL_FOUT1PH0] = thead_light_clk_fixed_factor("gmac_pll_fout1ph0", "gmac_pll_bypass", 1, 2);
clks[GMAC_PLL_FOUT4] = thead_light_clk_fixed_factor("gmac_pll_fout4", "gmac_pll_bypass", 1, 8);
clks[VIDEO_PLL_FOUT1PH0] = thead_light_clk_fixed_factor("video_pll_fout1ph0", "video_pll_bybass", 1, 2);
clks[VIDEO_PLL_FOUT1PH0] = thead_light_clk_fixed_factor("video_pll_fout1ph0", "video_pll_bypass", 1, 2);
clks[VIDEO_PLL_FOUT4] = thead_light_clk_fixed_factor("video_pll_fout4", "video_pll_bypass", 1, 8);
clks[TEE_PLL_FOUT4] = thead_light_clk_fixed_factor("tee_pll_fout4", "tee_pll_bypass", 1, 8);
clks[CPU_PLL0_FOUT4] = thead_light_clk_fixed_factor("cpu_pll0_fout4", "cpu_pll0_bypass", 1, 8);
@@ -450,7 +451,7 @@ static int light_clocks_probe(struct platform_device *pdev)
clks[QSPI0_SSI_CLK] = thead_light_clk_fixed_factor("qspi0_ssi_clk", "qspi_ssi_clk", 1, 1);
clks[QSPI1_SSI_CLK] = thead_light_clk_fixed_factor("qspi1_ssi_clk", "video_pll_fout1ph0", 1, 1);
clks[SPI_SSI_CLK] = thead_light_clk_fixed_factor("spi_ssi_clk", "video_pll_fout1ph0", 1, 1);
clks[EMMC_SDIO_REF_CLK] = thead_light_clk_fixed_factor("emmc_sdio_ref_clk", "video_pll_foutpostdiv", 1, 1); /* Note: no mux to select, use default value */
clks[EMMC_SDIO_REF_CLK] = thead_light_clk_fixed_factor("emmc_sdio_ref_clk", "video_pll_foutpostdiv", 1, 4); /* Note: base clk is div 4 to 198M*/
clks[PWM_CCLK] = thead_light_clk_fixed_factor("pwm_cclk", "osc_24m", 1, 1);
clks[CHIP_DBG_CCLK] = thead_light_clk_fixed_factor("chip_dbg_cclk", "osc_24m", 1, 1);
clks[GMAC_CCLK] = thead_light_clk_fixed_factor("gmac_cclk", "gmac_pll_fout1ph0", 1, 1);
@@ -568,8 +569,8 @@ static int light_clocks_probe(struct platform_device *pdev)
clks[CLKGEN_UART2_SCLK] = thead_clk_light_gate_shared("clkgen_uart2_sclk", "uart_sclk", ap_base + 0x204, 12, &share_cnt_uart2_clk_en);
clks[CLKGEN_I2C2_PCLK] = thead_clk_light_gate_shared("clkgen_i2c2_pclk", "perisys_apb_pclk", ap_base + 0x204, 3, &share_cnt_i2c2_clk_en);
clks[CLKGEN_I2C2_IC_CLK] = thead_clk_light_gate_shared("clkgen_i2c2_ic_clk", "i2c_ic_clk", ap_base + 0x204, 3, &share_cnt_i2c2_clk_en);
clks[CLKGEN_I2C3_PCLK] = thead_clk_light_gate_shared("clkgen_i2c3_pclk", "perisys_apb_pclk", ap_base + 0x204, 2, &share_cnt_i2c2_clk_en);
clks[CLKGEN_I2C3_IC_CLK] = thead_clk_light_gate_shared("clkgen_i2c3_ic_clk", "i2c_ic_clk", ap_base + 0x204, 2, &share_cnt_i2c2_clk_en);
clks[CLKGEN_I2C3_PCLK] = thead_clk_light_gate_shared("clkgen_i2c3_pclk", "perisys_apb_pclk", ap_base + 0x204, 2, &share_cnt_i2c3_clk_en);
clks[CLKGEN_I2C3_IC_CLK] = thead_clk_light_gate_shared("clkgen_i2c3_ic_clk", "i2c_ic_clk", ap_base + 0x204, 2, &share_cnt_i2c3_clk_en);
clks[CLKGEN_I2S_PCLK] = thead_clk_light_gate_shared("clkgen_i2s_pclk", "perisys_apb_pclk", ap_base + 0x1f0, 1, &share_cnt_peri_i2s_clk_en);
clks[CLKGEN_I2S_SRC_CLK] = thead_clk_light_gate_shared("clkgen_i2s_src_clk", "peri_i2s_src_clk", ap_base + 0x1f0, 1, &share_cnt_peri_i2s_clk_en);
clks[CLKGEN_QSPI1_PCLK] = thead_clk_light_gate_shared("clkgen_qspi1_pclk", "peri2sys_apb_pclk", ap_base + 0x204, 16, &share_cnt_qspi1_clk_en);

2
drivers/clk/thead/clk.h
View File

@@ -111,7 +111,7 @@ static inline struct clk *thead_light_clk_mux_flags(const char *name,
unsigned long flags)
{
return clk_register_mux(NULL, name, parents, num_parents,
flags | CLK_SET_RATE_NO_REPARENT, reg, shift, width, 0,
flags , reg, shift, width, 0,
&thead_light_clk_lock);
}
#endif

2
drivers/clk/thead/gate/Makefile
View File

@@ -1,3 +1,3 @@
# SPDX-License-Identifier: GPL-2.0
obj-$(CONFIG_CLK_LIGHT_FM) += thead-gate.o visys-gate.o vpsys-gate.o vosys-gate.o dspsys-gate.o
obj-$(CONFIG_CLK_LIGHT_FM) += thead-gate.o visys-gate.o vpsys-gate.o vosys-gate.o dspsys-gate.o audiosys-gate.o miscsys-gate.o

124
drivers/clk/thead/gate/audiosys-gate.c Normal file
View File

@@ -0,0 +1,124 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2022 Alibaba Group Holding Limited.
*/
#include <dt-bindings/clock/light-fm-ap-clock.h>
#include <dt-bindings/clock/light-audiosys.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/of_address.h>
#include <linux/platform_device.h>
#include <linux/types.h>
#include "clk-gate.h"
#include "../clk.h"
static struct clk *gates[LIGHT_CLKGEN_AUDIO_CLK_END];
static struct clk_onecell_data clk_gate_data;
static int light_audiosys_clk_probe(struct platform_device *pdev)
{
struct regmap *audiosys_regmap;
struct device *dev = &pdev->dev;
struct device_node *np = dev->of_node;
int ret;
audiosys_regmap = syscon_regmap_lookup_by_phandle(np, "audiosys-regmap");
if (IS_ERR(audiosys_regmap)) {
dev_err(&pdev->dev, "cannot find regmap for vi system register\n");
return PTR_ERR(audiosys_regmap);
}
printk("%s audiosys_regmap=0x%px\n", __func__, audiosys_regmap);
/* we assume that the gate clock is a root clock */
gates[LIGHT_CLKGEN_AUDIO_CPU] = thead_gate_clk_register("clkgen_audiosys_cpu_clk", NULL,
audiosys_regmap, 0x10, 0, GATE_NOT_SHARED, NULL, dev);
gates[LIGHT_CLKGEN_AUDIO_SRAM0] = thead_gate_clk_register("clkgen_audiosys_sram0_clk", NULL,
audiosys_regmap, 0x10, 1, GATE_NOT_SHARED, NULL, dev);
gates[LIGHT_CLKGEN_AUDIO_SRAM1] = thead_gate_clk_register("clkgen_audiosys_sram1_clk", NULL,
audiosys_regmap, 0x10, 2, GATE_NOT_SHARED, NULL, dev);
gates[LIGHT_CLKGEN_AUDIO_DMA] = thead_gate_clk_register("clkgen_audiosys_dma_clk", NULL,
audiosys_regmap, 0x10, 3, GATE_NOT_SHARED, NULL, dev);
gates[LIGHT_CLKGEN_AUDIO_BSM] = thead_gate_clk_register("clkgen_audiosys_bsm_clk", NULL,
audiosys_regmap, 0x10, 4, GATE_NOT_SHARED, NULL, dev);
gates[LIGHT_CLKGEN_AUDIO_TIMER] = thead_gate_clk_register("clkgen_audiosys_timer_clk", NULL,
audiosys_regmap, 0x10, 8, GATE_NOT_SHARED, NULL, dev);
gates[LIGHT_CLKGEN_AUDIO_TIMER_CNT1] = thead_gate_clk_register("clkgen_audiosys_timer_cnt1_clk", NULL,
audiosys_regmap, 0x10, 9, GATE_NOT_SHARED, NULL, dev);
gates[LIGHT_CLKGEN_AUDIO_TIMER_CNT2] = thead_gate_clk_register("clkgen_audiosys_timer_cnt2_clk", NULL,
audiosys_regmap, 0x10, 10, GATE_NOT_SHARED, NULL, dev);
gates[LIGHT_CLKGEN_AUDIO_TIMER_CNT3] = thead_gate_clk_register("clkgen_audiosys_timer_cnt3_clk", NULL,
audiosys_regmap, 0x10, 11, GATE_NOT_SHARED, NULL, dev);
gates[LIGHT_CLKGEN_AUDIO_TIMER_CNT4] = thead_gate_clk_register("clkgen_audiosys_timer_cnt4_clk", NULL,
audiosys_regmap, 0x10, 12, GATE_NOT_SHARED, NULL, dev);
gates[LIGHT_CLKGEN_AUDIO_WDR] = thead_gate_clk_register("clkgen_audiosys_wdr_clk", NULL,
audiosys_regmap, 0x10, 13, GATE_NOT_SHARED, NULL, dev);
gates[LIGHT_CLKGEN_AUDIO_I2C0] = thead_gate_clk_register("clkgen_audiosys_i2c0_clk", NULL,
audiosys_regmap, 0x10, 14, GATE_NOT_SHARED, NULL, dev);
gates[LIGHT_CLKGEN_AUDIO_I2C1] = thead_gate_clk_register("clkgen_audiosys_i2c1_clk", NULL,
audiosys_regmap, 0x10, 15, GATE_NOT_SHARED, NULL, dev);
gates[LIGHT_CLKGEN_AUDIO_UART] = thead_gate_clk_register("clkgen_audiosys_uart_clk", NULL,
audiosys_regmap, 0x10, 16, GATE_NOT_SHARED, NULL, dev);
gates[LIGHT_CLKGEN_AUDIO_I2S0] = thead_gate_clk_register("clkgen_audiosys_i2s0_clk", NULL,
audiosys_regmap, 0x10, 17, GATE_NOT_SHARED, NULL, dev);
gates[LIGHT_CLKGEN_AUDIO_I2S1] = thead_gate_clk_register("clkgen_audiosys_i2s1_clk", NULL,
audiosys_regmap, 0x10, 18, GATE_NOT_SHARED, NULL, dev);
gates[LIGHT_CLKGEN_AUDIO_I2S2] = thead_gate_clk_register("clkgen_audiosys_i2s2_clk", NULL,
audiosys_regmap, 0x10, 19, GATE_NOT_SHARED, NULL, dev);
gates[LIGHT_CLKGEN_AUDIO_I2S8CH] = thead_gate_clk_register("clkgen_audiosys_i2s8ch_clk", NULL,
audiosys_regmap, 0x10, 20, GATE_NOT_SHARED, NULL, dev);
gates[LIGHT_CLKGEN_AUDIO_TDM] = thead_gate_clk_register("clkgen_audiosys_tdm_clk", NULL,
audiosys_regmap, 0x10, 21, GATE_NOT_SHARED, NULL, dev);
gates[LIGHT_CLKGEN_AUDIO_GPIO] = thead_gate_clk_register("clkgen_audiosys_gpio_clk", NULL,
audiosys_regmap, 0x10, 22, GATE_NOT_SHARED, NULL, dev);
gates[LIGHT_CLKGEN_AUDIO_SPDIF0] = thead_gate_clk_register("clkgen_audiosys_spdif0_clk", NULL,
audiosys_regmap, 0x10, 23, GATE_NOT_SHARED, NULL, dev);
gates[LIGHT_CLKGEN_AUDIO_SPDIF1] = thead_gate_clk_register("clkgen_audiosys_spdif1_clk", NULL,
audiosys_regmap, 0x10, 24, GATE_NOT_SHARED, NULL, dev);
gates[LIGHT_CLKGEN_AUDIO_VAD] = thead_gate_clk_register("clkgen_audiosys_vad_clk", NULL,
audiosys_regmap, 0x10, 25, GATE_NOT_SHARED, NULL, dev);
gates[LIGHT_CLKGEN_AUDIO_IOMUX] = thead_gate_clk_register("clkgen_audiosys_iomux_clk", NULL,
audiosys_regmap, 0x10, 26, GATE_NOT_SHARED, NULL, dev);
clk_gate_data.clks = gates;
clk_gate_data.clk_num = ARRAY_SIZE(gates);
ret = of_clk_add_provider(np, of_clk_src_onecell_get, &clk_gate_data);
if (ret < 0) {
dev_err(dev, "failed to register gate clks for light audiosys\n");
goto unregister_clks;
}
dev_info(dev, "succeed to register audiosys gate clock provider\n");
return 0;
unregister_clks:
thead_unregister_clocks(gates, ARRAY_SIZE(gates));
return ret;
}
static const struct of_device_id audiosys_clk_gate_of_match[] = {
{ .compatible = "thead,audiosys-gate-controller" },
{ /* sentinel */ },
};
MODULE_DEVICE_TABLE(of, audiosys_clk_gate_of_match);
static struct platform_driver light_audiosys_clk_driver = {
.probe = light_audiosys_clk_probe,
.driver = {
.name = "audiosys-clk-gate-provider",
.of_match_table = of_match_ptr(audiosys_clk_gate_of_match),
},
};
module_platform_driver(light_audiosys_clk_driver);
MODULE_AUTHOR("nanli.yd <nanli.yd@linux.alibaba.com>");
MODULE_DESCRIPTION("Thead Light Fullmask audiosys clock gate provider");
MODULE_LICENSE("GPL v2");

18
drivers/clk/thead/gate/dspsys-gate.c
View File

@@ -20,12 +20,16 @@
static struct clk *gates[LIGHT_CLKGEN_DSPSYS_CLK_END];
static struct clk_onecell_data clk_gate_data;
static const char * const dsp0_cclk_sels[] = {"gmac_pll_foutpostdiv", "dspsys_dsp_clk"};
static const char * const dsp1_cclk_sels[] = {"gmac_pll_foutpostdiv", "dspsys_dsp_clk"};
static int light_dspsys_clk_probe(struct platform_device *pdev)
{
struct regmap *dspsys_regmap, *tee_dspsys_regmap;
struct device *dev = &pdev->dev;
struct device_node *np = dev->of_node;
struct device_node *np_reg = of_parse_phandle(np, "dspsys-regmap", 0);
void __iomem *gate_base;
int ret;
dspsys_regmap = syscon_regmap_lookup_by_phandle(np, "dspsys-regmap");
@@ -39,14 +43,24 @@ static int light_dspsys_clk_probe(struct platform_device *pdev)
dev_warn(&pdev->dev, "cannot find regmap for tee dsp system register\n");
tee_dspsys_regmap = NULL;
}
gate_base = of_iomap(np_reg,0);
// MUX
gates[DSPSYS_DSP0_CLK_SWITCH] = thead_light_clk_mux_flags("dspsys_dsp0_clk_switch", gate_base + 0x1c, 0, 1, dsp0_cclk_sels, ARRAY_SIZE(dsp0_cclk_sels), 0);
gates[DSPSYS_DSP1_CLK_SWITCH] = thead_light_clk_mux_flags("dspsys_dsp1_clk_switch", gate_base + 0x20, 0, 1, dsp1_cclk_sels, ARRAY_SIZE(dsp1_cclk_sels), 0);
// DIV & CDE
gates[DSPSYS_DSP_CLK] = thead_light_clk_fixed_factor("dspsys_dsp_clk", "video_pll_foutvco", 1, 3);
gates[DSPSYS_DSP0_CLK_CDE] = thead_clk_light_divider("dspsys_dsp0_clk_cde", "dspsys_dsp0_clk_switch", gate_base + 0x0, 0, 3, 4, MUX_TYPE_CDE, 0, 7);
gates[DSPSYS_DSP1_CLK_CDE] = thead_clk_light_divider("dspsys_dsp1_clk_cde", "dspsys_dsp1_clk_switch", gate_base + 0x4, 0, 3, 4, MUX_TYPE_CDE, 0, 7);
// gate
gates[CLKGEN_DSP0_PCLK] = thead_gate_clk_register("clkgen_dsp0_pclk", NULL, dspsys_regmap,
0x24, 0, GATE_NOT_SHARED, NULL, dev);
gates[CLKGEN_DSP1_PCLK] = thead_gate_clk_register("clkgen_dsp1_pclk", NULL, dspsys_regmap,
0x24, 1, GATE_NOT_SHARED, NULL, dev);
gates[CLKGEN_DSP1_CCLK] = thead_gate_clk_register("clkgen_dsp1_cclk", NULL, dspsys_regmap,
gates[CLKGEN_DSP1_CCLK] = thead_gate_clk_register("clkgen_dsp1_cclk", "dspsys_dsp1_clk_cde", dspsys_regmap,
0x24, 2, GATE_NOT_SHARED, NULL, dev);
gates[CLKGEN_DSP0_CCLK] = thead_gate_clk_register("clkgen_dsp0_cclk", NULL, dspsys_regmap,
gates[CLKGEN_DSP0_CCLK] = thead_gate_clk_register("clkgen_dsp0_cclk", "dspsys_dsp0_clk_cde", dspsys_regmap,
0x24, 3, GATE_NOT_SHARED, NULL, dev);
gates[CLKGEN_X2X_DSP2_ACLK_S] = thead_gate_clk_register("clkgen_x2x_dsp2_aclk_s", NULL, dspsys_regmap,
0x24, 4, GATE_NOT_SHARED, NULL, dev);

108
drivers/clk/thead/gate/miscsys-gate.c Normal file
View File

@@ -0,0 +1,108 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2022 Alibaba Group Holding Limited.
*/
#include <dt-bindings/clock/light-miscsys.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/of_address.h>
#include <linux/platform_device.h>
#include <linux/types.h>
#include "clk-gate.h"
#include "../clk.h"
static struct clk *gates[CLKGEN_MISCSYS_CLK_END];
static struct clk_onecell_data clk_gate_data;
static int light_miscsys_clk_probe(struct platform_device *pdev)
{
struct regmap *miscsys_regmap, *tee_miscsys_regmap = NULL;
struct device *dev = &pdev->dev;
struct device_node *np = dev->of_node;
int ret;
miscsys_regmap = syscon_regmap_lookup_by_phandle(np, "miscsys-regmap");
if (IS_ERR(miscsys_regmap)) {
dev_err(&pdev->dev, "cannot find regmap for misc system register\n");
return PTR_ERR(miscsys_regmap);
}
tee_miscsys_regmap = syscon_regmap_lookup_by_phandle(np, "tee-miscsys-regmap");
if (IS_ERR(tee_miscsys_regmap)) {
dev_err(&pdev->dev, "cannot find regmap for tee misc system register\n");
return PTR_ERR(tee_miscsys_regmap);
}
/* we assume that the gate clock is a root clock */
gates[CLKGEN_MISCSYS_MISCSYS_ACLK] = thead_gate_clk_register("clkgen_missys_aclk", NULL,
miscsys_regmap, 0x100, 0, GATE_NOT_SHARED, NULL, dev);
gates[CLKGEN_MISCSYS_USB3_DRD_CLK] = thead_gate_clk_register("clkgen_usb3_drd_clk", NULL,
miscsys_regmap, 0x104, 0, GATE_NOT_SHARED, NULL, dev);
gates[CLKGEN_MISCSYS_USB3_DRD_CTRL_REF_CLK] = thead_gate_clk_register("clkgen_usb3_drd_ctrl_ref_clk", "osc_24m",
miscsys_regmap, 0x104, 1, GATE_NOT_SHARED, NULL, dev);
gates[CLKGEN_MISCSYS_USB3_DRD_PHY_REF_CLK] = thead_gate_clk_register("clkgen_usb3_drd_phy_ref_clk", "osc_24m",
miscsys_regmap, 0x104, 2, GATE_NOT_SHARED, NULL, dev);
gates[CLKGEN_MISCSYS_USB3_DRD_SUSPEND_CLK] = thead_gate_clk_register("clkgen_usb3_drd_suspend_clk", NULL,
miscsys_regmap, 0x104, 3, GATE_NOT_SHARED, NULL, dev);
gates[CLKGEN_MISCSYS_EMMC_CLK] = thead_gate_clk_register("clkgen_emmc_clk", "osc_24m",
miscsys_regmap, 0x108, 0, GATE_NOT_SHARED, NULL, dev);
gates[CLKGEN_MISCSYS_SDIO0_CLK] = thead_gate_clk_register("clkgen_sdio0_clk", "osc_24m",
miscsys_regmap, 0x10c, 0, GATE_NOT_SHARED, NULL, dev);
gates[CLKGEN_MISCSYS_SDIO1_CLK] = thead_gate_clk_register("clkgen_sdio1_clk", "osc_24m",
miscsys_regmap, 0x110, 0, GATE_NOT_SHARED, NULL, dev);
if (tee_miscsys_regmap) {
gates[CLKGEN_MISCSYS_AHB2_TEESYS_HCLK] = thead_gate_clk_register("clkgen_ahb2_teesys_hclk", NULL,
tee_miscsys_regmap, 0x120, 0, GATE_NOT_SHARED, NULL, dev);
gates[CLKGEN_MISCSYS_APB3_TEESYS_HCLK] = thead_gate_clk_register("clkgen_apb3_teesys_hclk", NULL,
tee_miscsys_regmap, 0x120, 1, GATE_NOT_SHARED, NULL, dev);
gates[CLKGEN_MISCSYS_AXI4_TEESYS_ACLK] = thead_gate_clk_register("clkgen_axi4_teesys_aclk", NULL,
tee_miscsys_regmap, 0x120, 2, GATE_NOT_SHARED, NULL, dev);
gates[CLKGEN_MISCSYS_EIP120SI_CLK] = thead_gate_clk_register("clkgen_eip120si_clk", NULL,
tee_miscsys_regmap, 0x120, 3, GATE_NOT_SHARED, NULL, dev);
gates[CLKGEN_MISCSYS_EIP120SII_CLK] = thead_gate_clk_register("clkgen_eip120sii_clk", NULL,
tee_miscsys_regmap, 0x120, 4, GATE_NOT_SHARED, NULL, dev);
gates[CLKGEN_MISCSYS_EIP120SIII_CLK] = thead_gate_clk_register("clkgen_eip120siii_clk", NULL,
tee_miscsys_regmap, 0x120, 5, GATE_NOT_SHARED, NULL, dev);
gates[CLKGEN_MISCSYS_TEEDMAC_CLK] = thead_gate_clk_register("clkgen_teedmac_clk", NULL,
tee_miscsys_regmap, 0x120, 6, GATE_NOT_SHARED, NULL, dev);
gates[CLKGEN_MISCSYS_EIP150B_HCLK] = thead_gate_clk_register("clkgen_eip150b_hclk", NULL,
tee_miscsys_regmap, 0x120, 7, GATE_NOT_SHARED, NULL, dev);
gates[CLKGEN_MISCSYS_OCRAM_HCLK] = thead_gate_clk_register("clkgen_ocram_hclk", NULL,
tee_miscsys_regmap, 0x120, 8, GATE_NOT_SHARED, NULL, dev);
gates[CLKGEN_MISCSYS_EFUSE_PCLK] = thead_gate_clk_register("clkgen_efuse_pclk", NULL,
tee_miscsys_regmap, 0x120, 9, GATE_NOT_SHARED, NULL, dev);
gates[CLKGEN_MISCSYS_TEE_SYSREG_PCLK] = thead_gate_clk_register("clkgen_tee_sysreg_pclk", NULL,
tee_miscsys_regmap, 0x120, 10, GATE_NOT_SHARED, NULL, dev);
}
clk_gate_data.clks = gates;
clk_gate_data.clk_num = ARRAY_SIZE(gates);
ret = of_clk_add_provider(np, of_clk_src_onecell_get, &clk_gate_data);
if (ret < 0) {
dev_err(dev, "failed to register gate clks for light miscsys\n");
goto unregister_clks;
}
dev_info(dev, "succeed to register miscsys gate clock provider\n");
return 0;
unregister_clks:
thead_unregister_clocks(gates, ARRAY_SIZE(gates));
return ret;
}
static const struct of_device_id miscsys_clk_gate_of_match[] = {
{ .compatible = "thead,miscsys-gate-controller" },
{ /* sentinel */ },
};
MODULE_DEVICE_TABLE(of, miscsys_clk_gate_of_match);
static struct platform_driver light_miscsys_clk_driver = {
.probe = light_miscsys_clk_probe,
.driver = {
.name = "miscsys-clk-gate-provider",
.owner = THIS_MODULE,
.of_match_table = of_match_ptr(miscsys_clk_gate_of_match),
},
};
module_platform_driver(light_miscsys_clk_driver);
MODULE_AUTHOR("wei.liu <lw312886@linux.alibaba.com>");
MODULE_AUTHOR("Esther.Z <Esther.Z@linux.alibaba.com>");
MODULE_DESCRIPTION("Thead Light Fullmask miscsys clock gate provider");
MODULE_LICENSE("GPL v2");

9
drivers/clk/thead/gate/vpsys-gate.c
View File

@@ -34,15 +34,18 @@ static int light_vpsys_clk_probe(struct platform_device *pdev)
if (WARN_ON(IS_ERR(gate_base)))
return PTR_ERR(gate_base);
/* we assume that the gate clock is a root clock */
// DIV & CDE
gates[LIGHT_VPSYS_G2D_CCLK_DIV] = thead_clk_light_divider("light_vpsys_g2d_cclk_div", "video_pll_foutvco", gate_base + 0x30, 0, 4, 4, MUX_TYPE_DIV, 3, 9);
/* G2D clock configuration : Completed the upward configuration of CCLK */
gates[LIGHT_VPSYS_G2D_PCLK] = thead_clk_light_gate_shared("clkgen_vpsys_g2d_pclk", NULL,
gate_base + 0x20, 3, &share_cnt_g2d_clk_en);
gates[LIGHT_VPSYS_G2D_ACLK] = thead_clk_light_gate_shared("clkgen_vpsys_g2d_aclk", NULL,
gate_base + 0x20, 3, &share_cnt_g2d_clk_en);
gates[LIGHT_VPSYS_G2D_CCLK] = thead_clk_light_gate_shared("clkgen_vpsys_g2d_cclk", NULL,
gates[LIGHT_VPSYS_G2D_CCLK] = thead_clk_light_gate_shared("clkgen_vpsys_g2d_cclk", "light_vpsys_g2d_cclk_div",
gate_base + 0x20, 3, &share_cnt_g2d_clk_en);
/* we assume that the gate clock is a root clock */
gates[LIGHT_VPSYS_FCE_PCLK] = thead_clk_light_gate_shared("clkgen_vpsys_fce_pclk", NULL,
gate_base + 0x20, 2, &share_cnt_fce_clk_en);
gates[LIGHT_VPSYS_FCE_ACLK] = thead_clk_light_gate_shared("clkgen_vpsys_fce_aclk", NULL,

101
drivers/cpufreq/light-mpw-cpufreq.c
View File

@@ -40,6 +40,9 @@ enum LIGHT_MPW_CPUFREQ_CLKS {
#define LIGHT_C910_BUS_CLK_DIV_RATIO_2 0x100
#define LIGHT_C910_BUS_CLK_DIV_RATIO_3 0x200
#define LIGHT_CPU_PLL_IDX(x) (x)
#define LIGHT_CPU_PLL_COUNT 2
static int num_clks;
static struct clk_bulk_data clks[] = {
{ .id = "c910_cclk" },
@@ -51,6 +54,7 @@ static struct clk_bulk_data clks[] = {
static struct device *cpu_dev;
static struct cpufreq_frequency_table *freq_table;
static unsigned int max_freq;
static unsigned int min_freq;
static unsigned int transition_latency;
static void __iomem *ap_sys_reg;
static bool light_dvfs_sv = false;
@@ -58,6 +62,40 @@ static bool light_dvfs_sv = false;
static u32 *light_dvddm_volt;
static u32 soc_opp_count = 0;
static int _light_get_pllid(void)
{
int ret;
if (!strcmp(__clk_get_name(clk_get_parent(clks[LIGHT_C910_CCLK].clk)),
__clk_get_name(clks[LIGHT_C910_CCLK_I0].clk))) // pll index 0
ret = LIGHT_CPU_PLL_IDX(0);
else // pll index 1
ret = LIGHT_CPU_PLL_IDX(1);
return ret;
}
static int _light_switch_pllid(int pllid, int target_freq)
{
pr_debug("[%s] switchto pll[%d], freq[%u]\n", __func__, pllid, target_freq);
if (pllid == LIGHT_CPU_PLL_IDX(1)) {
clk_prepare_enable(clks[LIGHT_CPU_PLL1_FOUTPOSTDIV].clk);
clk_set_rate(clks[LIGHT_CPU_PLL1_FOUTPOSTDIV].clk, target_freq * 1000);
clk_set_parent(clks[LIGHT_C910_CCLK].clk, clks[LIGHT_CPU_PLL1_FOUTPOSTDIV].clk);
udelay(1);
clk_disable_unprepare(clks[LIGHT_CPU_PLL0_FOUTPOSTDIV].clk);
} else {
clk_prepare_enable(clks[LIGHT_CPU_PLL0_FOUTPOSTDIV].clk);
clk_set_rate(clks[LIGHT_CPU_PLL0_FOUTPOSTDIV].clk, target_freq * 1000);
clk_set_parent(clks[LIGHT_C910_CCLK].clk, clks[LIGHT_C910_CCLK_I0].clk);
udelay(1);
clk_disable_unprepare(clks[LIGHT_CPU_PLL1_FOUTPOSTDIV].clk);
}
return 0;
}
static int light_set_target(struct cpufreq_policy *policy, unsigned int index)
{
struct dev_pm_opp *opp;
@@ -140,20 +178,8 @@ static int light_set_target(struct cpufreq_policy *policy, unsigned int index)
}
}
if (!strcmp(__clk_get_name(clk_get_parent(clks[LIGHT_C910_CCLK].clk)),
__clk_get_name(clks[LIGHT_C910_CCLK_I0].clk))) {
clk_prepare_enable(clks[LIGHT_CPU_PLL1_FOUTPOSTDIV].clk);
clk_set_rate(clks[LIGHT_CPU_PLL1_FOUTPOSTDIV].clk, new_freq * 1000);
ret = clk_set_parent(clks[LIGHT_C910_CCLK].clk, clks[LIGHT_CPU_PLL1_FOUTPOSTDIV].clk);
udelay(1);
clk_disable_unprepare(clks[LIGHT_CPU_PLL0_FOUTPOSTDIV].clk);
} else {
clk_prepare_enable(clks[LIGHT_CPU_PLL0_FOUTPOSTDIV].clk);
clk_set_rate(clks[LIGHT_CPU_PLL0_FOUTPOSTDIV].clk, new_freq * 1000);
ret = clk_set_parent(clks[LIGHT_C910_CCLK].clk, clks[LIGHT_C910_CCLK_I0].clk);
udelay(1);
clk_disable_unprepare(clks[LIGHT_CPU_PLL1_FOUTPOSTDIV].clk);
}
/* switch pll */
_light_switch_pllid((_light_get_pllid()+1)&(LIGHT_CPU_PLL_COUNT-1), new_freq);
/*add delay for clk-switch*/
udelay(1);
@@ -200,6 +226,35 @@ static int light_set_target(struct cpufreq_policy *policy, unsigned int index)
return 0;
}
static int light_cpufreq_suspend(struct cpufreq_policy *policy)
{
int ret;
int index;
pr_debug("%s: cpu: %d, %u KHz to %u KHz\n",
__func__, policy->cpu, policy->cur, policy->suspend_freq);
ret = cpufreq_generic_suspend(policy);
if (ret) {
pr_err("%s: failed\n", __func__);
return ret;
}
/*
* Only CPU PLL0 would be active after STR resume. We should switch
* CPU PLL to be PLL0 after policy stopped.
*/
if (_light_get_pllid() == LIGHT_CPU_PLL_IDX(1))
_light_switch_pllid(LIGHT_CPU_PLL_IDX(0), policy->suspend_freq);
return 0;
}
static int light_cpufreq_resume(struct cpufreq_policy *policy)
{
return 0;
}
static int light_cpufreq_init(struct cpufreq_policy *policy)
{
policy->clk = clks[LIGHT_C910_CCLK].clk;
@@ -234,7 +289,8 @@ static struct cpufreq_driver light_cpufreq_driver = {
.init = light_cpufreq_init,
.name = "light-cpufreq",
.attr = cpufreq_generic_attr,
.suspend = cpufreq_generic_suspend,
.suspend = light_cpufreq_suspend,
.resume = light_cpufreq_resume,
};
static int light_cpufreq_pm_notify(struct notifier_block *nb,
@@ -274,15 +330,9 @@ static int panic_cpufreq_notifier_call(struct notifier_block *nb,
* set CPU PLL1's frequency as minimum to compatible voltage
* becarefull if the PLL1 is serving the cpu core, swith to PLL0 first
*/
if (strcmp(__clk_get_name(clk_get_parent(clks[LIGHT_C910_CCLK].clk)),
__clk_get_name(clks[LIGHT_C910_CCLK_I0].clk))) {
pr_debug("[%s,%d]\n", __func__, __LINE__);
clk_prepare_enable(clks[LIGHT_CPU_PLL0_FOUTPOSTDIV].clk);
clk_set_rate(clks[LIGHT_CPU_PLL0_FOUTPOSTDIV].clk, policy->min * 1000);
udelay(1);
clk_set_parent(clks[LIGHT_C910_CCLK].clk, clks[LIGHT_C910_CCLK_I0].clk);
if (_light_get_pllid() == LIGHT_CPU_PLL_IDX(1)) {
pr_debug("[%s,%d]\n", __func__, __LINE__);
_light_switch_pllid(LIGHT_CPU_PLL_IDX(0), policy->min);
}
pr_debug("[%s,%d]\n", __func__, __LINE__);
@@ -292,9 +342,7 @@ static int panic_cpufreq_notifier_call(struct notifier_block *nb,
* set the CPU PLL1's frequency as minimum in advance, otherwise the
* system may crash in crash kernel stage.
*/
clk_prepare_enable(clks[LIGHT_CPU_PLL1_FOUTPOSTDIV].clk);
clk_set_rate(clks[LIGHT_CPU_PLL1_FOUTPOSTDIV].clk, policy->min * 1000);
udelay(1);
_light_switch_pllid(LIGHT_CPU_PLL_IDX(1), policy->min);
pr_info("finish to execute cpufreq notifier callback on panic\n");
@@ -411,6 +459,7 @@ soc_opp_out:
transition_latency = CPUFREQ_ETERNAL;
max_freq = freq_table[--num].frequency;
min_freq = freq_table[0].frequency;
ret = cpufreq_register_driver(&light_cpufreq_driver);
if (ret) {

4
drivers/cpuidle/Kconfig
View File

@@ -47,6 +47,10 @@ config CPU_IDLE_GOV_HALTPOLL
config DT_IDLE_STATES
bool
config DT_IDLE_GENPD
depends on PM_GENERIC_DOMAINS_OF
bool
menu "ARM CPU Idle Drivers"
depends on ARM || ARM64
source "drivers/cpuidle/Kconfig.arm"

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