Linux_SDK_V1.1.2

arch/riscv/Kconfig

@@ -32,6 +32,7 @@ config RISCV
 	select ARCH_HAS_SYNC_DMA_FOR_DEVICE
 	select ARCH_HAS_DMA_WRITE_COMBINE
 	select ARCH_HAS_DMA_MMAP_PGPROT
+	select ARCH_KEEP_MEMBLOCK
 	select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX
 	select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT
 	select ARCH_USE_QUEUED_RWLOCKS

arch/riscv/boot/dts/thead/Makefile

@@ -4,7 +4,7 @@ dtb-$(CONFIG_SOC_THEAD) += light-fm-emu.dtb light_mpw.dtb
 dtb-$(CONFIG_SOC_THEAD) += light-fm-emu-npu-fce.dtb
 dtb-$(CONFIG_SOC_THEAD) += light-fm-emu-gpu.dtb
 dtb-$(CONFIG_SOC_THEAD) += light-fm-emu-dsp.dtb
-dtb-$(CONFIG_SOC_THEAD) += light-fm-emu-audio.dtb
+dtb-$(CONFIG_SOC_THEAD) += light-fm-emu-audio.dtb light-a-val-audio-hdmi.dtb
 dtb-$(CONFIG_SOC_THEAD) += light-fm-emu-hdmi.dtb
 dtb-$(CONFIG_SOC_THEAD) += light-fm-emu-dsi0-hdmi.dtb
 dtb-$(CONFIG_SOC_THEAD) += light-a-val.dtb light-a-val-sv.dtb
@@ -27,6 +27,7 @@ dtb-$(CONFIG_SOC_THEAD) += light-a-val-full.dtb
 dtb-$(CONFIG_SOC_THEAD) += light-ant-ref.dtb
 dtb-$(CONFIG_SOC_THEAD) += light-ant-discrete.dtb
 dtb-$(CONFIG_SOC_THEAD) += light-beagle.dtb
+dtb-$(CONFIG_SOC_THEAD) += light-lpi4a.dtb light-lpi4a-ddr2G.dtb
 dtb-$(CONFIG_SOC_THEAD) += light-a-ref.dtb light-a-ref-dsi0.dtb light-a-ref-dsi0-hdmi.dtb
 dtb-$(CONFIG_SOC_THEAD) += light-b-ref.dtb
 dtb-$(CONFIG_SOC_THEAD) += light-a-val-crash.dtb light-b-product-crash.dtb light-ant-ref-crash.dtb light-ant-discrete-crash.dtb
@@ -35,3 +36,4 @@ dtb-$(CONFIG_SOC_THEAD) += light-b-power.dtb
 dtb-$(CONFIG_SOC_THEAD) += light-a-val-android.dtb
 
 dtb-$(CONFIG_SOC_THEAD) += fire-emu.dtb fire-emu-crash.dtb
+dtb-$(CONFIG_SOC_THEAD) += fire-emu-soc-base.dtb fire-emu-soc-c910x4.dtb fire-emu-gpu-dpu-dsi0.dtb fire-emu-vi-dsp-vo.dtb fire-emu-vi-vp-vo.dtb

arch/riscv/boot/dts/thead/fire-crash.dts

@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0 */
 /*
- * Copyright (C) 2021 Alibaba Group Holding Limited.
+ * Copyright (C) 2021-2022 Alibaba Group Holding Limited.
  */
 
 /dts-v1/;
@@ -9,8 +9,9 @@
 #include <dt-bindings/input/linux-event-codes.h>
 #include <dt-bindings/gpio/gpio.h>
 #include "light-vi-devices.dtsi"
+
 / {
-	model = "T-HEAD Fire emu board";
+	model = "T-HEAD fire fpga board";
 	compatible = "thead,fire-emu", "thead,fire";
 
 	chosen {
@@ -120,10 +121,6 @@
 			is_default_region;
 		};
 
-		iopmp_fce: IOPMP_FCE {
-			is_default_region;
-		};
-
 		iopmp0_dpu: IOPMP0_DPU {
 			bypass_en;
 		};
@@ -192,23 +189,6 @@
 		status = "okay";
 	};
 
-	reg_vref_1v8: regulator-adc-verf {
-			compatible = "regulator-fixed";
-			regulator-name = "vref-1v8";
-			regulator-min-microvolt = <1800000>;
-			regulator-max-microvolt = <1800000>;
-	status = "okay";
-	};
-
-        reg_tp_pwr_en: regulator-pwr-en {
-                compatible = "regulator-fixed";
-                regulator-name = "PWR_EN";
-                regulator-min-microvolt = <2800000>;
-                regulator-max-microvolt = <2800000>;
-                gpio = <&gpio1_porta 12 1>;
-                enable-active-high;
-                regulator-always-on;
-        };
 
 	wcn_wifi: wireless-wlan {
 		compatible = "wlan-platdata";
@@ -217,33 +197,33 @@
 		keep_wifi_power_on;
 		pinctrl-names = "default";
 		wifi_chip_type = "rtl8723ds";
-		WIFI,poweren_gpio = <&gpio2_porta 29 0>;
+		WIFI,poweren_gpio = <&gpio2_porta 26 0>;
-		WIFI,reset_n = <&gpio2_porta 24 0>;
+		WIFI,reset_n = <&gpio2_porta 28 0>;
-		status = "okay";
+		status = "disabled";
 	};
 
 	wcn_bt: wireless-bluetooth {
 		compatible = "bluetooth-platdata";
 		pinctrl-names = "default", "rts_gpio";
-		BT,power_gpio    = <&gpio2_porta 25 0>;
+		BT,power_gpio    = <&gpio2_porta 29 0>;
-		status = "okay";
+		status = "disabled";
 	};
 
-	gpio-keys {
+	gpio_keys: gpio_keys{
 		compatible = "gpio-keys";
-		pinctrl-0 = <&pinctrl_volume>;
 		pinctrl-names = "default";
+		status = "disabled";
 		key-volumedown {
 			label = "Volume Down Key";
-			linux,code = <KEY_VOLUMEDOWN>;
+			linux,code = <KEY_1>;
-			debounce-interval = <1>;
+			debounce-interval = <2>;
-			gpios = <&ao_gpio_porta 11 0x1>;
+			gpios = <&ao_gpio_porta 4 GPIO_ACTIVE_LOW>;
 		};
 		key-volumeup {
 			label = "Volume Up Key";
-			linux,code = <KEY_VOLUMEUP>;
+			linux,code = <KEY_2>;
-			debounce-interval = <1>;
+			debounce-interval = <2>;
-			gpios = <&ao_gpio_porta 10 0x1>;
+			gpios = <&ao_gpio_porta 5 GPIO_ACTIVE_LOW>;
 		};
 	};
 
@@ -251,20 +231,27 @@
 		compatible = "thead,light-aon";
 		mbox-names = "aon";
 		mboxes = <&mbox_910t 1 0>;
-		status = "okay";
+		status = "disabled";
 
 		pd: light-aon-pd {
 			compatible = "thead,light-aon-pd";
 			#power-domain-cells = <1>;
+			status = "disabled";
+		};
+
+		aon_reg_dialog: light-dialog-reg {
+			compatible = "thead,light-dialog-pmic";
+			status = "disabled";
 		};
 
 		c910_cpufreq {
 			compatible = "thead,light-mpw-cpufreq";
-			status = "okay";
+			status = "disabled";
 		};
 
 		test: light-aon-test {
 			compatible = "thead,light-aon-test";
+			status = "disabled";
 		};
 	};
 };
@@ -278,60 +265,73 @@
 		reg = <0x0 0x1a000000 0 0x4000000>;
 		no-map;
 	};
+	dsp0_mem: memory@20000000 {			/**0x2000_0000~0x2040_0000 4M**/
+		reg = <0x0 0x20000000 0x0 0x00280000	/* DSP FW code&data section 2.5M*/
+		       0x0 0x20280000 0x0 0x00001000	/* DSP communication area 4K*/
+		       0x0 0x20281000 0x0 0x00007000	/* Panic/log page 28K */
+		       0x0 0x20288000 0x0 0x00178000>;	/* DSP shared memory 1.5M-32K*/
+		no-map;
+	};
+	dsp1_mem: memory@20400000 {			/**0x2040_0000~0x2080_0000 4M**/
+		reg = <0x0 0x20400000 0x0 0x00280000	/* DSP FW code&data section */
+		       0x0 0x20680000 0x0 0x00001000	/* DSP communication area */
+		       0x0 0x20681000 0x0 0x00007000	/* Panic/log page*/
+		       0x0 0x20688000 0x0 0x00178000>;	/* DSP shared memory */
+		no-map;
+	};
+    vi_mem: framebuffer@0f800000 {
+		reg = <0x0 0x0F800000 0x0 0x05400000	/* vi_mem_pool_region[0]  84 MB (default) */
+		       0x0 0x14C00000 0x0 0x01D00000	/* vi_mem_pool_region[1]  29 MB */
+		       0x0 0x16900000 0x0 0x03200000>;	/* vi_mem_pool_region[2]  50 MB */
+		no-map;
+	};
+	facelib_mem: memory@22000000 {
+		reg = <0x0 0x22000000 0x0 0x10000000>;
+		no-map;
+	};
 
-	dsp0_mem: memory@20000000 {             /**0x2000_0000~0x2040_0000 4M**/
-		reg = <0x0 0x20000000 0x0 0x00280000   /* DSP FW code&data section 2.5M*/ 
-               0x0 0x20280000 0x0 0x00001000   /* DSP communication area 4K*/ 
-               0x0 0x20281000 0x0 0x00007000  /* Panic/log page 28K */
-               0x0 0x20288000 0x0 0x00178000>;  /* DSP shared memory 1.5M-32K*/
-		no-map;
-	};
-    dsp1_mem: memory@20400000 {             /**0x2040_0000~0x2080_0000 4M**/
-        reg = <0x0 0x20400000 0x0 0x00280000  /* DSP FW code&data section */ 
-               0x0 0x20680000 0x0 0x00001000 /* DSP communication area */
-               0x0 0x20681000 0x0 0x00007000    /* Panic/log page*/ 
-               0x0 0x20688000 0x0 0x00178000>;  /* DSP shared memory */
-        no-map;
-    };
-	vi_mem: framebuffer@10000000 {
-		reg = <0x0 0x10000000 0x0 0x02C00000	/* vi_mem_pool_region[0]  44 MB (default) */
-		       0x0 0x12C00000 0x0 0x01D00000	/* vi_mem_pool_region[1]  29 MB */
-		       0x0 0x14900000 0x0 0x01E00000>;	/* vi_mem_pool_region[2]  30 MB */
-		no-map;
-	};
-	facelib_mem: memory@17000000 {
-		reg = <0x0 0x17000000 0 0x02000000>;
-		no-map;
-	};
 };
 
-&adc {
+&clk {
-	vref-supply = <&reg_vref_1v8>;
+	status = "disabled";
-	status = "okay";
 };
 
 &i2c0 {
-	clock-frequency = <100000>;
+	clock-frequency = <400000>;
 	status = "okay";
 
+	eeprom@50 {
+		compatible = "atmel,24c32";
+		reg = <0x50>;
+		pagesize = <32>;
+	};
+
+	codec: wm8960@1a {
+		#sound-dai-cells = <0>;
+		compatible = "wlf,wm8960";
+		reg = <0x1a>;
+		wlf,shared-lrclk;
+		wlf,hp-cfg = <3 2 3>;
+		wlf,gpio-cfg = <1 3>;
+	};
+
        touch@5d {
                #gpio-cells = <2>;
                compatible = "goodix,gt911";
+			   status = "disabled";
                reg = <0x5d>;
                interrupt-parent = <&gpio1_porta>;
                interrupts = <8 0>;
                irq-gpios = <&gpio1_porta 8 0>;
                reset-gpios = <&gpio1_porta 7 0>;
-               AVDD28-supply = <&reg_tp_pwr_en>;
+               touchscreen-size-x = <800>;
-               touchscreen-size-x = <720>;
                touchscreen-size-y = <1280>;
        };
-
 };
 
 &audio_i2c0 {
         clock-frequency = <100000>;
-        status = "okay";
+        status = "disabled";
 
        es8156_audio_codec: es8156@8 {
                #sound-dai-cells = <0>;
@@ -344,25 +344,29 @@
                 compatible = "MicArray_0";
                 reg = <0x40>;
         };
-
-	audio_aw87519_pa@58 {
-		compatible = "awinic,aw87519_pa";
-		reg = <0x58>;
-		reset-gpio = <&ao_gpio4_porta 9 0x1>;
-		status = "okay";
-	};
 };
 
 &i2c1 {
-        clock-frequency = <100000>;
+        clock-frequency = <400000>;
-        status = "okay";
+        status = "disabled";
+        touch1@5d {
+                #gpio-cells = <2>;
+                compatible = "goodix,gt911";
+                reg = <0x5d>;
+                interrupt-parent = <&gpio1_porta>;
+                interrupts = <12 0>;
+                irq-gpios = <&gpio1_porta 12 0>;
+                reset-gpios = <&gpio1_porta 11 0>;
+                touchscreen-size-x = <800>;
+                touchscreen-size-y = <1280>;
+        };
 };
 
 &spi0 {
 	num-cs = <1>;
 	cs-gpios = <&gpio2_porta 15 0>; // GPIO_ACTIVE_HIGH: 0
 	rx-sample-delay-ns = <10>;
-	status = "disabled";
+	status = "okay";
 
 	spi_norflash@0 {
 		#address-cells = <1>;
@@ -371,6 +375,7 @@
 		reg = <0>;
 		spi-max-frequency = <50000000>;
 		w25q,fast-read;
+		status = "disabled";
 	};
 
 	spidev@1 {
@@ -382,12 +387,6 @@
 	};
 };
 
-&uart0 {
-	clocks = <&dummy_clock_uart_sclk>;
-	clock-names = "baudclk";
-	clock-frequency = <100000000>;
-};
-
 &qspi0 {
 	num-cs = <1>;
 	cs-gpios = <&gpio2_porta 3 0>;
@@ -411,17 +410,23 @@
 };
 
 &qspi1 {
-	compatible = "snps,dw-apb-ssi";
 	num-cs = <1>;
 	cs-gpios = <&gpio0_porta 1 0>;
 	status = "disabled";
 
-	spidev@0 {
+	spi-flash@0 {
-		compatible = "spidev";
+		#address-cells = <1>;
-		#address-cells = <0x1>;
+		#size-cells = <1>;
-		#size-cells = <0x1>;
+		compatible = "spi-nand";
-		reg = <0x0>;
+		spi-max-frequency = <66000000>;
-		spi-max-frequency = <50000000>;
+		spi-tx-bus-width = <4>;
+		spi-rx-bus-width = <4>;
+		reg = <0>;
+
+		partition@0 {
+			label = "ubi2";
+			reg = <0x00000000 0x08000000>;
+		};
 	};
 };
 
@@ -447,14 +452,6 @@
 	};
 };
 
-&gmac1 {
-	phy-mode = "rgmii-id";
-	rx-clk-delay = <0x00>; /* for RGMII */
-	tx-clk-delay = <0x00>; /* for RGMII */
-	phy-handle = <&phy_88E1111_1>;
-	status = "okay";
-};
-
 &emmc {
 	max-frequency = <198000000>;
 	non-removable;
@@ -489,7 +486,7 @@
 	cap-sd-highspeed;
 	keep-power-in-suspend;
 	wakeup-source;
-	status = "okay";
+	status = "disabled";
 };
 
 &padctrl0_apsys { /* right-pinctrl */
@@ -541,6 +538,7 @@
 			pinctrl_pwm: pwmgrp {
 				thead,pins = <
 					FM_GPIO3_2	0x1	0x208	/* pwm0 */
+					FM_GPIO3_3	0x1	0x208	/* pwm1 */
 				>;
 			};
 		};
@@ -593,57 +591,41 @@
 		};
 };
 
-&padctrl_aosys {
+&i2c2 {
-	light-aon-padctrl {
+    clock-frequency = <400000>;
-			/*
+	status = "okay";
-			 * Pin Configuration Node:
+	eeprom@50 {
-			 * Format: <pin_id mux_node config>
+		compatible = "atmel,24c32";
-			 */
+		reg = <0x50>;
-
+		pagesize = <32>;
-			pinctrl_audiopa1: audiopa1_grp {
-				thead,pins = <
-					FM_AUDIO_PA1	0x3	0x72
-				>;
-			};
-
-			pinctrl_audiopa2: audiopa2_grp {
-				thead,pins = <
-					FM_AUDIO_PA2	0x0	0x72
-				>;
-			};
-
-			pinctrl_volume: volume_grp {
-				thead,pins = <
-					FM_AOGPIO_11  0x0     0x208
-					FM_AOGPIO_10  0x3     0x208
-				>;
-			};
 	};
 };
 
-&i2c0 {
-	clock-frequency = <400000>;
-	status = "okay";
-};
-
-&i2c1 {
-	clock-frequency = <400000>;
-	status = "okay";
-};
-
-&i2c2 {
-	clock-frequency = <400000>;
-	status = "okay";
-};
-
 &i2c3 {
-	clock-frequency = <400000>;
+    clock-frequency = <400000>;
 	status = "okay";
+	eeprom@50 {
+		compatible = "atmel,24c32";
+		reg = <0x50>;
+		pagesize = <32>;
+	};
 };
 
 &i2c4 {
-	clock-frequency = <400000>;
+    clock-frequency = <400000>;
 	status = "okay";
+	eeprom@50 {
+		compatible = "atmel,24c32";
+		reg = <0x50>;
+		pagesize = <32>;
+	};
+
+	pcal6408ahk_a: gpio@20 {
+		compatible = "nxp,pcal9554b";
+		reg = <0x20>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
 };
 
 &isp0 {
@@ -691,6 +673,7 @@
 };
 
 &vi_pre {
+	//vi_pre_irq_en = <1>;
 	status = "disabled";
 };
 
@@ -700,18 +683,20 @@
 
 &xtensa_dsp0 {
 	status = "disabled";
+    memory-region = <&dsp0_mem>;
 };
 
-&xtensa_dsp1 {
+&xtensa_dsp1{
-	status = "disabled";
+    status = "disabled";
+    memory-region = <&dsp1_mem>;
 };
 
 &vvcam_flash_led0{
-       status = "disabled";
+    flash_led_name = "aw36413_aw36515";
-};
+	floodlight_i2c_bus = /bits/ 8 <2>;
-
+	floodlight_en_pin = <&gpio1_porta 25 0>;
-
+	//projection_i2c_bus = /bits/ 8 <2>;
-&vvcam_sensor0 {
+	flash_led_touch_pin = <&gpio1_porta 27 0>; //flash led touch pin
 	status = "disabled";
 };
 
@@ -851,19 +836,19 @@
 };
 
 &light_i2s {
-        status = "okay";
+        status = "disabled";
 };
 
 &i2s0 {
-        status = "okay";
+        status = "disabled";
 };
 
 &i2s1 {
-        status = "okay";
+        status = "disabled";
 };
 
 &i2s3 {
-        status = "okay";
+        status = "disabled";
 };
 
 &khvhost {

arch/riscv/boot/dts/thead/fire-emu-crash.dts

@@ -8,7 +8,7 @@
 &aon {
 	aon_reg_dialog: light-dialog-reg {
 		compatible = "thead,light-dialog-pmic";
-		status = "okay";
+		status = "disabled";
 
 		dvdd_cpu_reg: appcpu_dvdd {
 			regulator-name = "appcpu_dvdd";

arch/riscv/boot/dts/thead/fire-emu-gpu-dpu-dsi0.dts

@@ -0,0 +1,107 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2021-2022 Alibaba Group Holding Limited.
+ */
+
+/dts-v1/;
+
+#include "fire-emu.dts"
+
+&gpu {
+	status = "okay";
+};
+
+&vosys_reg {
+	status = "okay";
+};
+
+&display_subsystem {
+	status = "okay";
+};
+
+&dpu_enc0 {
+	status = "okay";
+
+	ports {
+		/* output */
+		port@1 {
+			reg = <1>;
+
+			enc0_out: endpoint {
+				remote-endpoint = <&dsi0_in>;
+			};
+		};
+	};
+};
+
+&dpu {
+	status = "okay";
+};
+
+
+&dsi0 {
+	status = "okay";
+};
+
+&dhost_0 {
+	ports {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		port@0 {
+			reg = <0>;
+
+			dsi0_in: endpoint {
+				remote-endpoint = <&enc0_out>;
+			};
+		};
+
+		port@1 {
+			reg = <1>;
+
+			dsi0_out: endpoint {
+				remote-endpoint = <&panel0_in>;
+			};
+		};
+	};
+
+	panel0@0 {
+		compatible = "hlt,hpk070h275";
+		reg = <0>;
+
+		port {
+			panel0_in: endpoint {
+				remote-endpoint = <&dsi0_out>;
+			};
+		};
+	};
+};
+
+&aon {
+	status = "okay";
+};
+
+&mbox_910t {
+	status = "okay";
+};
+
+&mbox_910t_client1 {
+	status = "okay";
+};
+
+&mbox_910t_client2 {
+	status = "okay";
+};
+
+&dmac1 {
+	status = "okay";
+};
+
+&lightsound {
+	status = "okay";
+};
+
+&dmac2 {
+    status = "disabled";
+};
+

arch/riscv/boot/dts/thead/fire-emu-soc-base.dts

@@ -0,0 +1,89 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2021-2022 Alibaba Group Holding Limited.
+ */
+
+/dts-v1/;
+
+#include "fire-emu.dts"
+
+&sdhci0 {
+	status = "okay";
+};
+
+&usb3_drd {
+	status = "okay";
+};
+
+&usb {
+	status = "okay";
+};
+
+&spi0 {
+	num-cs = <1>;
+	cs-gpios = <&gpio2_porta 15 0>; // GPIO_ACTIVE_HIGH: 0
+	rx-sample-delay-ns = <10>;
+	status = "okay";
+
+	spi_norflash@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "winbond,w25q64jwm", "jedec,spi-nor";
+		reg = <0>;
+		spi-max-frequency = <50000000>;
+		w25q,fast-read;
+		status = "okay";
+	};
+
+	spidev@1 {
+		compatible = "spidev";
+		#address-cells = <0x1>;
+		#size-cells = <0x1>;
+		reg = <0x1>;
+		spi-max-frequency = <50000000>;
+	};
+};
+
+&qspi0 {
+	num-cs = <1>;
+	cs-gpios = <&gpio2_porta 3 0>;
+	rx-sample-dly = <4>;
+	status = "okay";
+
+	spi-flash@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "spi-nand";
+		spi-max-frequency = <100000000>;
+		spi-tx-bus-width = <4>;
+		spi-rx-bus-width = <4>;
+		reg = <0>;
+
+		partition@0 {
+			label = "ubi1";
+			reg = <0x00000000 0x08000000>;
+		};
+	};
+};
+
+&qspi1 {
+	num-cs = <1>;
+	cs-gpios = <&gpio0_porta 1 0>;
+	status = "okay";
+
+	spi-flash@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "spi-nand";
+		spi-max-frequency = <66000000>;
+		spi-tx-bus-width = <4>;
+		spi-rx-bus-width = <4>;
+		reg = <0>;
+
+		partition@0 {
+			label = "ubi2";
+			reg = <0x00000000 0x08000000>;
+		};
+	};
+};
+

arch/riscv/boot/dts/thead/fire-emu-soc-c910x4.dts

@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2021-2022 Alibaba Group Holding Limited.
+ */
+
+#include "fire-emu.dts"
+
+&c910_1 {
+	status = "okay";
+};
+
+&c910_2 {
+	status = "okay";
+};
+
+&c910_3 {
+	status = "okay";
+};
+

arch/riscv/boot/dts/thead/fire-emu-vi-dsp-vo.dts

@@ -0,0 +1,57 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2021-2022 Alibaba Group Holding Limited.
+ */
+
+/dts-v1/;
+
+#include "fire-emu.dts"
+
+&c910_1 {
+	status = "okay";
+};
+
+&vi_pre {
+	status = "okay";
+};
+
+&dewarp {
+	status = "okay";
+};
+
+&xtensa_dsp {
+	status = "okay";
+};
+
+&xtensa_dsp0 {
+	status = "okay";
+};
+
+&xtensa_dsp1 {
+	status = "okay";
+};
+
+&vosys_reg {
+	status = "okay";
+};
+
+&display_subsystem {
+	status = "okay";
+};
+
+&dpu {
+	status = "okay";
+};
+
+&hdmi_tx {
+	status = "okay";
+};
+
+&dsi0 {
+	status = "okay";
+};
+
+&dpu_enc0 {
+	status = "okay";
+};
+

arch/riscv/boot/dts/thead/fire-emu-vi-vp-vo.dts

@@ -0,0 +1,119 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2021-2022 Alibaba Group Holding Limited.
+ */
+
+/dts-v1/;
+
+#include "fire-emu.dts"
+
+&c910_1 {
+	status = "okay";
+};
+
+&vi_pre {
+	status = "okay";
+};
+
+&dewarp {
+	status = "okay";
+};
+
+&venc {
+	status = "okay";
+};
+
+&vdec {
+	status = "okay";
+};
+
+&g2d {
+	status = "okay";
+};
+
+&vosys_reg {
+	status = "okay";
+};
+
+&display_subsystem {
+	status = "okay";
+};
+
+&dpu_enc0 {
+	status = "okay";
+
+	ports {
+		/* output */
+		port@1 {
+			reg = <1>;
+
+			enc0_out: endpoint {
+				remote-endpoint = <&dsi0_in>;
+			};
+		};
+	};
+};
+
+&dsi0 {
+	status = "okay";
+};
+
+&dhost_0 {
+	ports {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		port@0 {
+			reg = <0>;
+
+			dsi0_in: endpoint {
+				remote-endpoint = <&enc0_out>;
+			};
+		};
+
+		port@1 {
+			reg = <1>;
+
+			dsi0_out: endpoint {
+				remote-endpoint = <&panel0_in>;
+			};
+		};
+	};
+
+	panel0@0 {
+		compatible = "hlt,hpk070h275";
+		reg = <0>;
+
+		port {
+			panel0_in: endpoint {
+				remote-endpoint = <&dsi0_out>;
+			};
+		};
+	};
+};
+
+&dpu_enc1 {
+	ports {
+		/delete-node/ port@0;
+	};
+};
+
+&disp1_out {
+	remote-endpoint = <&hdmi_tx_in>;
+};
+
+&dpu {
+	status = "okay";
+};
+
+&hdmi_tx {
+	status = "okay";
+
+	port@0 {
+		/* input */
+		hdmi_tx_in: endpoint {
+			remote-endpoint = <&disp1_out>;
+		};
+	};
+};
+

arch/riscv/boot/dts/thead/fire.dtsi

@@ -23,7 +23,6 @@
 
 	aliases {
 		ethernet0 = &gmac0;
-		ethernet1 = &gmac1;
 		gpio0 = &gpio0;
 		gpio1 = &gpio1;
 		gpio2 = &gpio2;
@@ -93,7 +92,7 @@
 		};
 	};
 
-	thermal-zones {
+	thermal_zones: thermal-zones {
 		cpu-thermal-zone {
 			polling-delay-passive = <250>;
 			polling-delay = <2000>;
@@ -166,8 +165,6 @@
 				 <&clk CPU_PLL0_FOUTPOSTDIV>;
 			clock-names = "c910_cclk", "c910_cclk_i0",
 				      "cpu_pll1_foutpostdiv", "cpu_pll0_foutpostdiv";
-			dvdd-supply = <&dvdd_cpu_reg>;
-			dvddm-supply = <&dvddm_cpu_reg>;
 
 			cpu0_intc: interrupt-controller {
 				#interrupt-cells = <1>;
@@ -178,7 +175,7 @@
 		c910_1: cpu@1 {
 			device_type = "cpu";
 			reg = <1>;
-			status = "okay";
+			status = "disabled";
 			compatible = "riscv";
 			riscv,isa = "rv64imafdcvsu";
 			mmu-type = "riscv,sv39";
@@ -212,8 +209,6 @@
 				 <&clk CPU_PLL0_FOUTPOSTDIV>;
 			clock-names = "c910_cclk", "c910_cclk_i0",
 				      "cpu_pll1_foutpostdiv", "cpu_pll0_foutpostdiv";
-			dvdd-supply = <&dvdd_cpu_reg>;
-			dvddm-supply = <&dvddm_cpu_reg>;
 
 			cpu1_intc: interrupt-controller {
 				#interrupt-cells = <1>;
@@ -224,7 +219,7 @@
 		c910_2: cpu@2 {
 			device_type = "cpu";
 			reg = <2>;
-			status = "okay";
+			status = "disabled";
 			compatible = "riscv";
 			riscv,isa = "rv64imafdcvsu";
 			mmu-type = "riscv,sv39";
@@ -258,8 +253,6 @@
 				 <&clk CPU_PLL0_FOUTPOSTDIV>;
 			clock-names = "c910_cclk", "c910_cclk_i0",
 				      "cpu_pll1_foutpostdiv", "cpu_pll0_foutpostdiv";
-			dvdd-supply = <&dvdd_cpu_reg>;
-			dvddm-supply = <&dvddm_cpu_reg>;
 
 			cpu2_intc: interrupt-controller {
 				#interrupt-cells = <1>;
@@ -270,7 +263,7 @@
 		c910_3: cpu@3 {
 			device_type = "cpu";
 			reg = <3>;
-			status = "okay";
+			status = "disabled";
 			compatible = "riscv";
 			riscv,isa = "rv64imafdcvsu";
 			mmu-type = "riscv,sv39";
@@ -304,8 +297,6 @@
 				 <&clk CPU_PLL0_FOUTPOSTDIV>;
 			clock-names = "c910_cclk", "c910_cclk_i0",
 				      "cpu_pll1_foutpostdiv", "cpu_pll0_foutpostdiv";
-			dvdd-supply = <&dvdd_cpu_reg>;
-			dvddm-supply = <&dvddm_cpu_reg>;
 
 			cpu3_intc: interrupt-controller {
 				#interrupt-cells = <1>;
@@ -315,7 +306,7 @@
 		};
 	};
 
-	display-subsystem {
+	display_subsystem: display-subsystem {
 		compatible = "verisilicon,display-subsystem";
 		ports = <&dpu_disp0>, <&dpu_disp1>;
 		status = "disabled";
@@ -421,7 +412,7 @@
 			dummy_clock_apb: apb-clock@0 {
 				compatible = "fixed-clock";
 				reg = <0>;	/* Not address, just for index */
-				clock-frequency = <62500000>;
+				clock-frequency = <50000000>;
 				clock-output-names = "dummy_clock_apb";
 				#clock-cells = <0>;
 			};
@@ -469,7 +460,7 @@
 			dummy_clock_dphy_ref: dphy-ref-clock@7 {
 				compatible = "fixed-clock";
 				reg = <7>;      /* Not address, just for index */
-				clock-frequency = <24000000>;
+				clock-frequency = <40000000>;
 				clock-output-names = "dummy_clock_dphy_ref";
 				#clock-cells = <0>;
 			};
@@ -477,7 +468,7 @@
 			dummy_clock_dphy_cfg: dphy-cfg-clock@8 {
 				compatible = "fixed-clock";
 				reg = <8>;      /* Not address, just for index */
-				clock-frequency = <24000000>;
+				clock-frequency = <40000000>;
 				clock-output-names = "dummy_clock_dphy_cfg";
 				#clock-cells = <0>;
 			};
@@ -485,7 +476,7 @@
 			dummy_clock_dpu_pixel0: dpu-pixel-clock@9 {
 				compatible = "fixed-clock";
 				reg = <9>;
-				clock-frequency = <72000000>;
+				clock-frequency = <25200000>;
 				clock-output-names = "dummy_clock_dpu_pixel0";
 				#clock-cells = <0>;
 			};
@@ -493,7 +484,7 @@
 			dummy_clock_dpu_pixel1: dpu-pixel-clock@10 {
 				compatible = "fixed-clock";
 				reg = <10>;
-				clock-frequency = <74250000>;
+				clock-frequency = <25200000>;
 				clock-output-names = "dummy_clock_dpu_pixel1";
 				#clock-cells = <0>;
 			};
@@ -525,7 +516,7 @@
 			dummy_clock_eip: eip-clock@14 {
 				compatible = "fixed-clock";
 				reg = <14>;	/* Not address, just for index */
-				clock-frequency = <400000000>;
+				clock-frequency = <30000000>;
 				clock-output-names = "dummy_clock_eip";
 				#clock-cells = <0>;
 			};
@@ -533,7 +524,7 @@
 			dummy_clock_spi: spi-clock@15 {
 				compatible = "fixed-clock";
 				reg = <15>;	/* Not address, just for index */
-				clock-frequency = <396000000>;
+				clock-frequency = <50000000>;
 				clock-output-names = "dummy_clock_spi";
 				#clock-cells = <0>;
 			};
@@ -541,7 +532,7 @@
 			dummy_clock_qspi: spi-clock@16 {
 				compatible = "fixed-clock";
 				reg = <15>;	/* Not address, just for index */
-				clock-frequency = <792000000>;
+				clock-frequency = <50000000>;
 				clock-output-names = "dummy_clock_qspi";
 				#clock-cells = <0>;
 			};
@@ -549,7 +540,7 @@
 			dummy_gmac_ahb: gmac-ahb-clock@16 {
 				compatible = "fixed-clock";
 				reg = <16>;
-				clock-frequency = <250000000>;
+				clock-frequency = <50000000>;
 				clock-output-names = "dummy_gmac_ahb";
 				#clock-cells = <0>;
 			};
@@ -557,7 +548,7 @@
 			dummy_clock_gmac: gmac-clock@17 {
 				compatible = "fixed-clock";
 				reg = <17>;
-				clock-frequency = <500000000>;
+				clock-frequency = <50000000>;
 				clock-output-names = "dummy_clock_gmac";
 				#clock-cells = <0>;
 			};
@@ -565,7 +556,7 @@
 			dummy_clock_sdhci: sdhci-clock@18 {
 				compatible = "fixed-clock";
 				reg = <18>;	/* Not address, just for index */
-				clock-frequency = <198000000>;
+				clock-frequency = <50000000>;
 				clock-output-names = "dummy_clock_sdhci";
 				#clock-cells = <0>;
 			};
@@ -573,16 +564,16 @@
 			dummy_clock_aonsys_clk: aonsys-clk-clock@19 {
 				compatible = "fixed-clock";
 				reg = <19>;	/* Not address, just for index */
-				clock-frequency = <73728000>;
+				clock-frequency = <24000000>;
 				clock-output-names = "dummy_clock_aonsys_clk";
 				#clock-cells = <0>;
 			};
 
-			dummy_clock_uart_sclk: uart-sclk-clock@20 {
+			dummy_clock_uart: uart-sclk-clock@20 {
 				compatible = "fixed-clock";
 				reg = <20>;	/* Not address, just for index */
-				clock-frequency = <100000000>;
+				clock-frequency = <50000000>;
-				clock-output-names = "dummy_clock_uart_sclk";
+				clock-output-names = "dummy_clock_uart";
 				#clock-cells = <0>;
 			};
 
@@ -592,6 +583,20 @@
 				clock-frequency = <24000000>;
 				#clock-cells = <0>;
 			};
+
+			dummy_clock_vipre: vipre-dummy-clock@22 {
+				compatible = "fixed-clock";
+				reg = <22>;
+				clock-frequency = <13000000>;
+				#clock-cells = <0>;
+			};
+
+			dummy_clock_vpsys: vpsys-dummy-clock@23 {
+				compatible = "fixed-clock";
+				reg = <23>;
+				clock-frequency = <24000000>;
+				#clock-cells = <0>;
+			};
 		};
 
 		iso7816: iso7816-card@fff7f30000 {
@@ -644,9 +649,6 @@
 				reg = <0xb0 6>;
 			};
 
-			gmac1_mac_address: mac-address@184 {
-				reg = <0xb8 6>;
-			};
 		};
 
 		misc_sysreg: misc_sysreg@ffec02c000 {
@@ -797,9 +799,8 @@
 			compatible = "thead,pwm-light";
 			reg = <0xff 0xec01c000 0x0 0x4000>;
 			#pwm-cells = <2>;
-			clocks = <&clk CLKGEN_PWM_PCLK>,
+			clocks = <&dummy_clock_apb>;
-			         <&clk CLKGEN_PWM_CCLK>;
+			clock-names = "pwm";
-			clock-names = "pclk", "cclk";
 			pinctrl-names = "default";
 			pinctrl-0 = <&pinctrl_pwm>;
 		};
@@ -809,7 +810,7 @@
 			reg = <0xff 0xefc32000 0x0 0x14>;
 			clocks = <&dummy_clock_apb>;
 			clock-names = "timer";
-			clock-frequency = <62500000>;
+			clock-frequency = <50000000>;
 			interrupts = <16>;
 			interrupt-parent = <&intc>;
 			status = "okay";
@@ -820,7 +821,7 @@
 			reg = <0xff 0xefc32014 0x0 0x14>;
 			clocks = <&dummy_clock_apb>;
 			clock-names = "timer";
-			clock-frequency = <62500000>;
+			clock-frequency = <50000000>;
 			interrupts = <17>;
 			interrupt-parent = <&intc>;
 			status = "okay";
@@ -831,7 +832,7 @@
 			reg = <0xff 0xefc32028 0x0 0x14>;
 			clocks = <&dummy_clock_apb>;
 			clock-names = "timer";
-			clock-frequency = <62500000>;
+			clock-frequency = <50000000>;
 			interrupts = <18>;
 			interrupt-parent = <&intc>;
 			status = "disabled";
@@ -842,7 +843,7 @@
 			reg = <0xff 0xefc3203c 0x0 0x14>;
 			clocks = <&dummy_clock_apb>;
 			clock-names = "timer";
-			clock-frequency = <62500000>;
+			clock-frequency = <50000000>;
 			interrupts = <19>;
 			interrupt-parent = <&intc>;
 			status = "disabled";
@@ -851,7 +852,7 @@
 		padctrl_aosys: padctrl-aosys@fffff4a000 {
 			compatible = "thead,light-fm-aon-pinctrl";
 			reg = <0xff 0xfff4a000 0x0 0x2000>;
-			status = "okay";
+			status = "disabled";
 		};
 
 		timer4: timer@ffffc33000 {
@@ -859,7 +860,7 @@
 			reg = <0xff 0xffc33000 0x0 0x14>;
 			clocks = <&dummy_clock_apb>;
 			clock-names = "timer";
-			clock-frequency = <62500000>;
+			clock-frequency = <50000000>;
 			interrupts = <20>;
 			interrupt-parent = <&intc>;
 			status = "disabled";
@@ -870,7 +871,7 @@
 			reg = <0xff 0xffc33014 0x0 0x14>;
 			clocks = <&dummy_clock_apb>;
 			clock-names = "timer";
-			clock-frequency = <62500000>;
+			clock-frequency = <50000000>;
 			interrupts = <21>;
 			interrupt-parent = <&intc>;
 			status = "disabled";
@@ -881,7 +882,7 @@
 			reg = <0xff 0xffc33028 0x0 0x14>;
 			clocks = <&dummy_clock_apb>;
 			clock-names = "timer";
-			clock-frequency = <62500000>;
+			clock-frequency = <50000000>;
 			interrupts = <22>;
 			interrupt-parent = <&intc>;
 			status = "disabled";
@@ -892,7 +893,7 @@
 			reg = <0xff 0xffc3303c 0x0 0x14>;
 			clocks = <&dummy_clock_apb>;
 			clock-names = "timer";
-			clock-frequency = <62500000>;
+			clock-frequency = <50000000>;
 			interrupts = <23>;
 			interrupt-parent = <&intc>;
 			status = "disabled";
@@ -903,7 +904,7 @@
 			reg = <0xff 0xe7014000 0x0 0x4000>;
 			interrupt-parent = <&intc>;
 			interrupts = <36>;
-			clocks = <&clk CLKGEN_UART0_SCLK>;
+			clocks = <&dummy_clock_uart>;
 			clock-names = "baudclk";
 			reg-shift = <2>;
 			reg-io-width = <4>;
@@ -916,7 +917,7 @@
 			reg = <0xff 0xe7f00000 0x0 0x4000>;
 			interrupt-parent = <&intc>;
 			interrupts = <37>;
-			clocks = <&clk CLKGEN_UART1_SCLK>;
+			clocks = <&dummy_clock_uart>;
 			clock-names = "baudclk";
 			reg-shift = <2>;
 			reg-io-width = <4>;
@@ -929,7 +930,7 @@
 			reg = <0xff 0xec010000 0x0 0x4000>;
 			interrupt-parent = <&intc>;
 			interrupts = <38>;
-			clocks = <&clk CLKGEN_UART2_SCLK>;
+			clocks = <&dummy_clock_uart>;
 			clock-names = "baudclk";
 			reg-shift = <2>;
 			reg-io-width = <4>;
@@ -942,7 +943,7 @@
 			reg = <0xff 0xe7f04000 0x0 0x4000>;
 			interrupt-parent = <&intc>;
 			interrupts = <39>;
-			clocks = <&clk CLKGEN_UART3_SCLK>;
+			clocks = <&dummy_clock_uart>;
 			clock-names = "baudclk";
 			reg-shift = <2>;
 			reg-io-width = <4>;
@@ -955,7 +956,7 @@
 			reg = <0xff 0xf7f08000 0x0 0x4000>;
 			interrupt-parent = <&intc>;
 			interrupts = <40>;
-			clocks = <&clk CLKGEN_UART4_SCLK>;
+			clocks = <&dummy_clock_uart>;
 			clock-names = "baudclk";
 			reg-shift = <2>;
 			reg-io-width = <4>;
@@ -968,7 +969,7 @@
 			reg = <0xff 0xf7f0c000 0x0 0x4000>;
 			interrupt-parent = <&intc>;
 			interrupts = <41>;
-			clocks = <&clk CLKGEN_UART5_SCLK>;
+			clocks = <&dummy_clock_uart>;
 			clock-names = "baudclk";
 			reg-shift = <2>;
 			reg-io-width = <4>;
@@ -1030,9 +1031,9 @@
 			interrupt-parent = <&intc>;
 			interrupts = <101>;
 			interrupt-names = "irq_2d";
-			clocks = <&vpsys_clk_gate LIGHT_VPSYS_G2D_PCLK>,
+			clocks = <&dummy_clock_vpsys>,
-				 <&vpsys_clk_gate LIGHT_VPSYS_G2D_ACLK>,
+				<&dummy_clock_vpsys>,
-				 <&vpsys_clk_gate LIGHT_VPSYS_G2D_CCLK>;
+				<&dummy_clock_vpsys>;
 			clock-names = "pclk", "aclk", "cclk";
 			status = "okay";
 		};
@@ -1046,11 +1047,11 @@
 				compatible = "thead,light-mipi-dphy";
 				regmap = <&dsi0>;
 				vosys-regmap = <&vosys_reg>;
-				clocks = <&vosys_clk_gate LIGHT_CLKGEN_MIPIDSI0_REFCLK>,
+				clocks = <&dummy_clock_dphy_ref>,
-					 <&vosys_clk_gate LIGHT_CLKGEN_MIPIDSI0_CFG_CLK>,
+					<&dummy_clock_dphy_cfg>,
-					 <&vosys_clk_gate LIGHT_CLKGEN_MIPIDSI0_PCLK>,
+					<&dummy_clock_dphy_ref>,
-					 <&clk OSC_24M>,
+					<&dummy_clock_dpu_pixel0>,
-					 <&clk OSC_24M>;
+					<&dummy_clock_dphy_cfg>;
 				clock-names = "refclk", "cfgclk", "pclk", "prefclk", "pcfgclk";
 				#phy-cells = <0>;
 			};
@@ -1060,8 +1061,8 @@
 				regmap = <&dsi0>;
 				interrupt-parent = <&intc>;
 				interrupts = <129>;
-				clocks = <&vosys_clk_gate LIGHT_CLKGEN_MIPIDSI0_PCLK>,
+				clocks = <&dummy_clock_dphy_cfg>,
-					 <&vosys_clk_gate LIGHT_CLKGEN_MIPIDSI0_PIXCLK>;
+					<&dummy_clock_dpu_pixel0>;
 				clock-names = "pclk", "pixclk";
 				phys = <&dphy_0>;
 				phy-names = "dphy";
@@ -1079,11 +1080,11 @@
 				compatible = "thead,light-mipi-dphy";
 				regmap = <&dsi1>;
 				vosys-regmap = <&vosys_reg>;
-				clocks = <&vosys_clk_gate LIGHT_CLKGEN_MIPIDSI1_REFCLK>,
+				clocks = <&dummy_clock_dphy_ref>,
-					 <&vosys_clk_gate LIGHT_CLKGEN_MIPIDSI1_CFG_CLK>,
+					<&dummy_clock_dphy_cfg>,
-					 <&vosys_clk_gate LIGHT_CLKGEN_MIPIDSI1_PCLK>,
+					<&dummy_clock_dphy_ref>,
-					 <&clk OSC_24M>,
+					<&dummy_clock_dpu_pixel1>,
-					 <&clk OSC_24M>;
+					<&dummy_clock_dphy_cfg>;
 				clock-names = "refclk", "cfgclk", "pclk", "prefclk", "pcfgclk";
 				#phy-cells = <0>;
 			};
@@ -1093,8 +1094,8 @@
 				regmap = <&dsi1>;
 				interrupt-parent = <&intc>;
 				interrupts = <129>;
-				clocks = <&vosys_clk_gate LIGHT_CLKGEN_MIPIDSI1_PCLK>,
+				clocks = <&dummy_clock_dphy_cfg>,
-					 <&vosys_clk_gate LIGHT_CLKGEN_MIPIDSI1_PIXCLK>;
+					<&dummy_clock_dpu_pixel1>;
 				clock-names = "pclk", "pixclk";
 				phys = <&dphy_1>;
 				phy-names = "dphy";
@@ -1114,11 +1115,11 @@
 			reg = <0xff 0xef540000 0x0 0x40000>;
 			interrupt-parent = <&intc>;
 			interrupts = <111>;
-			clocks = <&vosys_clk_gate LIGHT_CLKGEN_HDMI_PCLK>,
+			clocks = <&dummy_clock_dpu_pixel0>,
-				 <&vosys_clk_gate LIGHT_CLKGEN_HDMI_SFR_CLK>,
+				<&dummy_clock_dpu_pixel0>,
-				 <&vosys_clk_gate LIGHT_CLKGEN_HDMI_CEC_CLK>,
+				<&dummy_clock_dpu_pixel0>,
-				 <&vosys_clk_gate LIGHT_CLKGEN_HDMI_PIXCLK>,
+				<&dummy_clock_dpu_pixel0>,
-				 <&vosys_clk_gate LIGHT_CLKGEN_HDMI_I2S_CLK>;
+				<&dummy_clock_dpu_pixel0>;
 			clock-names = "iahb", "isfr", "cec", "pixclk", "i2s";
 			reg-io-width = <4>;
 			phy_version = <301>;
@@ -1135,19 +1136,19 @@
 			      <0xff 0xef630010 0x0 0x60>;
 			interrupt-parent = <&intc>;
 			interrupts = <93>;
-			clocks = <&vosys_clk_gate LIGHT_CLKGEN_DPU_CCLK>,
+			clocks = <&dummy_clock_dpu_pixel0>,
-				 <&vosys_clk_gate LIGHT_CLKGEN_DPU_PIXCLK0>,
+				<&dummy_clock_dpu_pixel0>,
-				 <&vosys_clk_gate LIGHT_CLKGEN_DPU_PIXCLK1>,
+				<&dummy_clock_dpu_pixel0>,
-				 <&vosys_clk_gate LIGHT_CLKGEN_DPU_ACLK>,
+				<&dummy_clock_dpu_pixel0>,
-				 <&vosys_clk_gate LIGHT_CLKGEN_DPU_HCLK>,
+				<&dummy_clock_dpu_pixel0>,
-				 <&clk DPU0_PLL_DIV_CLK>,
+				<&dummy_clock_dpu_pixel0>,
-				 <&clk DPU1_PLL_DIV_CLK>,
+				<&dummy_clock_dpu_pixel0>,
-				 <&clk DPU0_PLL_FOUTPOSTDIV>,
+				<&dummy_clock_dpu_pixel0>,
-				 <&clk DPU1_PLL_FOUTPOSTDIV>;
+				<&dummy_clock_dpu_pixel0>;
 			clock-names = "core_clk", "pix_clk0", "pix_clk1",
-				      "axi_clk", "cfg_clk", "pixclk0",
+						"axi_clk", "cfg_clk", "pixclk0",
-				      "pixclk1", "dpu0_pll_foutpostdiv",
+						"pixclk1", "dpu0_pll_foutpostdiv",
-				      "dpu1_pll_foutpostdiv";
+						"dpu1_pll_foutpostdiv";
 			status = "disabled";
 
 			dpu_disp0: port@0 {
@@ -1172,7 +1173,7 @@
 			reg = <0xff 0xefc30000 0x0 0x1000>;
 			interrupt-parent = <&intc>;
 			interrupts = <24>;
-			clocks = <&clk CLKGEN_WDT0_PCLK>;
+			clocks = <&dummy_clock_apb>;
 			clock-names = "tclk";
 			resets = <&rst LIGHT_RESET_WDT0>; 
 			status = "okay";
@@ -1183,7 +1184,7 @@
 			reg = <0xff 0xefc31000 0x0 0x1000>;
 			interrupt-parent = <&intc>;
 			interrupts = <25>;
-			clocks = <&clk CLKGEN_WDT1_PCLK>;
+			clocks = <&dummy_clock_apb>;
 			clock-names = "tclk";
 			resets = <&rst LIGHT_RESET_WDT1>; 
 			status = "okay";
@@ -1221,7 +1222,7 @@
 				dma-mask = <0xf 0xffffffff>;
 				snps,usb3_lpm_capable;
 				snps,usb_sofitpsync;
-				status = "okay";
+				status = "disabled";
 			};
 		};
 
@@ -1323,7 +1324,7 @@
 			interrupt-parent = <&intc>;
 			interrupts = <66>;
 			interrupt-names = "macirq";
-			clocks = <&clk CLKGEN_GMAC0_CCLK>;
+			clocks = <&dummy_clock_gmac>;
 			clock-names = "gmac_pll_clk";
 			snps,pbl = <32>;
 			snps,fixed-burst;
@@ -1332,25 +1333,6 @@
 			nvmem-cell-names = "mac-address";
 		};
 
-		gmac1: ethernet@ffe7060000 {
-			compatible = "thead,light-dwmac";
-			reg = <0xff 0xe7060000 0x0 0x2000
-			       0xff 0xec00401c 0x0 0x4
-			       0xff 0xec004020 0x0 0x4
-			       0xff 0xec004000 0x0 0x1c>;
-			reg-names = "gmac", "phy_if_reg", "txclk_dir_reg", "clk_mgr_reg";
-			interrupt-parent = <&intc>;
-			interrupts = <67>;
-			interrupt-names = "macirq";
-			clocks = <&clk CLKGEN_GMAC1_CCLK>;
-			clock-names = "gmac_pll_clk";
-			snps,pbl = <32>;
-			snps,fixed-burst;
-			snps,axi-config = <&stmmac_axi_setup>;
-			nvmem-cells = <&gmac1_mac_address>;
-			nvmem-cell-names = "mac-address";
-		};
-
 		emmc: sdhci@ffe7080000 {
 			compatible = "snps,dwcmshc-sdhci";
 			reg = <0xff 0xe7080000 0x0 0x10000
@@ -1397,11 +1379,11 @@
 		    interrupts = <102>;
 		    interrupt-names = "gpuirq";
 			vosys-regmap = <&vosys_reg>;
-			power-domains = <&pd LIGHT_AON_GPU_PD>;
+			//power-domains = <&pd LIGHT_AON_GPU_PD>;
-            clocks = <&vosys_clk_gate LIGHT_CLKGEN_GPU_CORE_CLK>,
+            clocks = <&dummy_clock_gpu>,
-                     <&vosys_clk_gate LIGHT_CLKGEN_GPU_CFG_ACLK>;
+					<&dummy_clock_gpu>;
-            clock-names = "cclk", "aclk";
+		    clock-names = "cclk", "aclk";
-		    gpu_clk_rate = <18000000>;
+			gpu_clk_rate = <18000000>;
 		    dma-mask = <0xf 0xffffffff>;
 		    status = "disabled";
 		};
@@ -1411,10 +1393,10 @@
 			reg = <0xff 0xecc00000 0x0 0x8000>;
 			interrupt-parent = <&intc>;
 			interrupts = <131>;
-			power-domains = <&pd LIGHT_AON_VDEC_PD>;
+			//power-domains = <&pd LIGHT_AON_VDEC_PD>;
-			clocks = <&vpsys_clk_gate LIGHT_VPSYS_VDEC_ACLK>,
+			clocks = <&dummy_clock_vpsys>,
-				<&vpsys_clk_gate LIGHT_VPSYS_VDEC_CCLK>,
+				<&dummy_clock_vpsys>,
-				<&vpsys_clk_gate LIGHT_VPSYS_VDEC_PCLK>;
+				<&dummy_clock_vpsys>;
 			clock-names = "aclk", "cclk", "pclk";
 			status = "disabled";
 		};
@@ -1424,10 +1406,10 @@
 			reg = <0xff 0xecc10000 0x0 0x8000>;
 			interrupt-parent = <&intc>;
 			interrupts = <133>;
-			power-domains = <&pd LIGHT_AON_VENC_PD>;
+			//power-domains = <&pd LIGHT_AON_VENC_PD>;
-			clocks = <&vpsys_clk_gate LIGHT_VPSYS_VENC_ACLK>,
+			clocks = <&dummy_clock_vpsys>,
-				<&vpsys_clk_gate LIGHT_VPSYS_VENC_CCLK>,
+				<&dummy_clock_vpsys>,
-				<&vpsys_clk_gate LIGHT_VPSYS_VENC_PCLK>;
+				<&dummy_clock_vpsys>;
 			clock-names = "aclk", "cclk", "pclk";
 			status = "disabled";
 		};
@@ -1443,7 +1425,7 @@
 		vidmem: vidmem@ffecc08000 {
 			compatible = "thead,light-vidmem";
 			reg = <0xff 0xecc08000 0x0 0x1000>;
-			status = "disabled";
+			status = "okay";
 		};
 
 		light_i2s: light_i2s@ffe7034000 {
@@ -1532,7 +1514,7 @@
 		    reg-names = "common", "ts", "pd", "vm";
 		    clocks = <&dummy_clock_aonsys_clk>;
 		    #thermal-sensor-cells = <1>;
-		    status = "okay";
+		    status = "disabled";
 		};
 
 		i2c0: i2c@ffe7f20000 {
@@ -1660,10 +1642,10 @@
 			reg = <0xff 0xe4100000 0x0 0x10000>;
 			interrupt-parent = <&intc>;
 			interrupts = <117>,<118>;
-			clocks =  <&visys_clk_gate LIGHT_CLKGEN_ISP0_ACLK>,
+			clocks =  <&dummy_clock_visys>,
-			          <&visys_clk_gate LIGHT_CLKGEN_ISP0_HCLK>,
+				<&dummy_clock_visys>,
-				  <&visys_clk_gate LIGHT_CLKGEN_ISP0_PIXELCLK>,
+				<&dummy_clock_visys>,
-				  <&visys_clk_gate LIGHT_CLKGEN_ISP0_CLK>;
+				<&dummy_clock_visys>;
 			clock-names = "aclk", "hclk", "isp0_pclk", "cclk";
 			status = "disabled";
 		};
@@ -1673,11 +1655,11 @@
 			reg = <0xff 0xe4110000 0x0 0x10000>;
 			interrupt-parent = <&intc>;
 			interrupts = <120>,<121>;
-			clocks = <&visys_clk_gate LIGHT_CLKGEN_ISP0_ACLK>,
+			clocks = <&dummy_clock_visys>,
-			         <&visys_clk_gate LIGHT_CLKGEN_ISP0_HCLK>,
+					<&dummy_clock_visys>,
-				 <&visys_clk_gate LIGHT_CLKGEN_ISP0_PIXELCLK>,
+					<&dummy_clock_visys>,
-				 <&visys_clk_gate LIGHT_CLKGEN_ISP1_CLK>,
+					<&dummy_clock_visys>,
-				 <&visys_clk_gate LIGHT_CLKGEN_ISP1_PIXELCLK>;
+					<&dummy_clock_visys>;
 			clock-names = "aclk", "hclk", "isp0_pclk", "cclk", "isp1_pclk";
 			status = "disabled";
 		};
@@ -1687,9 +1669,9 @@
 			reg = <0xff 0xe4120000 0x0 0x10000>;
 			interrupt-parent = <&intc>;
 			interrupts = <123>,<124>;
-			clocks = <&visys_clk_gate LIGHT_CLKGEN_ISP_RY_ACLK>,
+			clocks = <&dummy_clock_visys>,
-			         <&visys_clk_gate LIGHT_CLKGEN_ISP_RY_HCLK>,
+					<&dummy_clock_visys>,
-				 <&visys_clk_gate LIGHT_CLKGEN_ISP_RY_CCLK>;
+					<&dummy_clock_visys>;
 			clock-names = "aclk", "hclk", "cclk";
 			status = "disabled";
 		};
@@ -1699,10 +1681,10 @@
 			reg = <0xff 0xe4130000 0x0 0x10000>;
 			interrupt-parent = <&intc>;
 			interrupts = <98>,<99>;
-			clocks = <&visys_clk_gate LIGHT_CLKGEN_DW200_ACLK>,
+			clocks = <&dummy_clock_visys>,
-			         <&visys_clk_gate LIGHT_CLKGEN_DW200_HCLK>,
+					<&dummy_clock_visys>,
-				 <&visys_clk_gate LIGHT_CLKGEN_DW200_CLK_VSE>,
+					<&dummy_clock_visys>,
-				 <&visys_clk_gate LIGHT_CLKGEN_DW200_CLK_DWE>;
+					<&dummy_clock_visys>;
 			clock-names = "aclk", "hclk", "vseclk", "dweclk";
 			status = "disabled";
 		};
@@ -1738,10 +1720,10 @@
 		    interrupts = <128>;
 		    dphyglueiftester = <0x180>;
 		    sysreg_mipi_csi_ctrl = <0x140>;
-		    clocks = <&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI0_PCLK>,
+		    clocks = <&dummy_clock_visys>,
-		             <&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI0_PIXCLK>,
+					<&dummy_clock_visys>,
-		             <&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI0_CFG_CLK>;
+					<&dummy_clock_visys>;
-		    clock-names = "pclk", "pixclk", "cfg_clk";
+			clock-names = "pclk", "pixclk", "cfg_clk";
 		    phy_name = "CSI_4LANE";
 		    status = "disabled";
 		};
@@ -1761,10 +1743,10 @@
 		    sysreg_mipi_csi_ctrl = <0x148>;
 		    visys-regmap = <&visys_reg>;
 		    csia-regmap = <&csia_reg>;
-		    clocks = <&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI1_PCLK>,
+		    clocks = <&dummy_clock_visys>,
-		             <&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI1_PIXCLK>,
+					<&dummy_clock_visys>,
-		             <&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI1_CFG_CLK>;
+					<&dummy_clock_visys>;
-		    clock-names = "pclk", "pixclk", "cfg_clk";
+			clock-names = "pclk", "pixclk", "cfg_clk";
 		    phy_name = "CSI_B";
 		    status = "disabled";
 		};
@@ -1776,10 +1758,10 @@
 		    interrupts = <127>;
 		    dphyglueiftester = <0x184>;
 		    sysreg_mipi_csi_ctrl = <0x144>;
-		    clocks = <&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI2_PCLK>,
+		    clocks = <&dummy_clock_visys>,
-		             <&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI2_PIXCLK>,
+					<&dummy_clock_visys>,
-		             <&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI2_CFG_CLK>;
+					<&dummy_clock_visys>;
-		    clock-names = "pclk", "pixclk", "cfg_clk";
+			clock-names = "pclk", "pixclk", "cfg_clk";
 		    phy_name = "CSI_A";
 		    status = "disabled";
 		};
@@ -1808,9 +1790,9 @@
 			reg = <0xff 0xe4030000 0x0 0x1000>;
 			interrupt-parent = <&intc>;
 			interrupts = <134>;
-			clocks = <&visys_clk_gate LIGHT_CLKGEN_VIPRE_ACLK>,
+			clocks = <&dummy_clock_vipre>,
-			         <&visys_clk_gate LIGHT_CLKGEN_VIPRE_PCLK>,
+					<&dummy_clock_vipre>,
-				 <&visys_clk_gate LIGHT_CLKGEN_VIPRE_PIXELCLK>;
+					<&dummy_clock_vipre>;
 			clock-names ="aclk", "pclk", "pixclk";
 			status = "disabled";
 		};
@@ -2016,11 +1998,6 @@
 			};
 		};
 
-		pmp: pmp@ffdc020000 {
-			compatible = "pmp";
-			reg = <0xff 0xdc020000 0x0 0x1000>;
-		};
-
 		mrvbr: mrvbr@ffff018050 {
 			compatible = "mrvbr";
 			reg = <0xff 0xff019050 0x0 0x1000>;
@@ -2056,6 +2033,7 @@
 		       clock-names = "ipg";
 		       icu_cpu_id = <0>;
 		       #mbox-cells = <2>;
+		       status = "disabled";
 		};
 
 		trng: rng@ffff300000 {

arch/riscv/boot/dts/thead/light-a-product.dts

@@ -535,7 +535,7 @@
                irq-gpios = <&gpio1_porta 8 0>;
                reset-gpios = <&gpio1_porta 7 0>;
                AVDD28-supply = <&reg_tp_pwr_en>;
-               touchscreen-size-x = <720>;
+               touchscreen-size-x = <800>;
                touchscreen-size-y = <1280>;
        };
 };
@@ -552,7 +552,7 @@
                 irq-gpios = <&gpio1_porta 12 0>;
                 reset-gpios = <&gpio1_porta 11 0>;
                 AVDD28-supply = <&reg_tp1_pwr_en>;
-                touchscreen-size-x = <720>;
+                touchscreen-size-x = <800>;
                 touchscreen-size-y = <1280>;
         };
 };

arch/riscv/boot/dts/thead/light-a-val-audio-hdmi.dts

@@ -0,0 +1,89 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2021 Alibaba Group Holding Limited.
+ */
+
+/dts-v1/;
+
+#include "light-a-val.dts"
+
+/ {
+	display-subsystem {
+		status = "okay";
+	};
+};
+
+&dpu_enc1 {
+	ports {
+		/delete-node/ port@0;
+	};
+};
+
+&disp1_out {
+	remote-endpoint = <&hdmi_tx_in>;
+};
+
+&dpu {
+	status = "okay";
+};
+
+&hdmi_tx {
+	status = "okay";
+
+	port@0 {
+		/* input */
+		hdmi_tx_in: endpoint {
+			remote-endpoint = <&disp1_out>;
+		};
+	};
+};
+
+&lightsound {
+	status = "okay";
+
+        simple-audio-card,dai-link@0 {          /* I2S - AUDIO SYS CODEC 8156*/
+                reg = <0>;
+                format = "i2s";
+                cpu {
+                        sound-dai = <&i2s0 0>;
+                };
+                codec {
+                        sound-dai = <&es8156_audio_codec>;
+                };
+        };
+
+        simple-audio-card,dai-link@1 {          /* I2S - AUDIO SYS CODEC 7210*/
+                reg = <1>;
+                format = "i2s";
+                cpu {
+                        sound-dai = <&i2s3 0>;
+                };
+                codec {
+                        sound-dai = <&es7210_audio_codec>;
+                };
+        };
+	
+	simple-audio-card,dai-link@2 {          /* I2S - HDMI */
+		reg = <2>;
+		format = "i2s";
+		cpu {
+			sound-dai = <&light_i2s 1>;
+		};
+		codec {
+			sound-dai = <&dummy_codec 2>;
+		};
+	};
+};
+
+&light_i2s {
+        status = "okay";
+};
+
+&i2s0 {
+        status = "okay";
+};
+
+&i2s3 {
+        status = "okay";
+};
+

arch/riscv/boot/dts/thead/light-a-val.dts

@@ -548,7 +548,7 @@
                irq-gpios = <&gpio1_porta 8 0>;
                reset-gpios = <&gpio1_porta 7 0>;
                AVDD28-supply = <&reg_tp_pwr_en>;
-               touchscreen-size-x = <720>;
+               touchscreen-size-x = <800>;
                touchscreen-size-y = <1280>;
        };
 };
@@ -582,7 +582,7 @@
                 irq-gpios = <&gpio1_porta 12 0>;
                 reset-gpios = <&gpio1_porta 11 0>;
                 AVDD28-supply = <&reg_tp1_pwr_en>;
-                touchscreen-size-x = <720>;
+                touchscreen-size-x = <800>;
                 touchscreen-size-y = <1280>;
         };
 };
@@ -1017,6 +1017,9 @@
 	DVDD12_SCAN-supply = <&soc_dvdd12_scan_reg>;
 	AVDD28_SCAN-supply = <&soc_avdd28_scan_en_reg>;
 	i2c_bus = /bits/ 8 <4>;
+    i2c_reg_width = /bits/ 8 <2>;
+    i2c_data_width = /bits/ 8 <1>;
+    i2c_addr = /bits/ 8 <0x30>;
 	status = "okay";
 };
 

arch/riscv/boot/dts/thead/light-ant-discrete.dts

@@ -571,7 +571,7 @@
                irq-gpios = <&gpio1_porta 8 0>;
                reset-gpios = <&gpio1_porta 7 0>;
                AVDD28-supply = <&reg_tp_pwr_en>;
-               touchscreen-size-x = <720>;
+               touchscreen-size-x = <800>;
                touchscreen-size-y = <1280>;
        };
 

arch/riscv/boot/dts/thead/light-ant-ref.dts

@@ -578,7 +578,7 @@
                irq-gpios = <&gpio1_porta 8 0>;
                reset-gpios = <&gpio1_porta 7 0>;
                AVDD28-supply = <&reg_tp_pwr_en>;
-               touchscreen-size-x = <720>;
+               touchscreen-size-x = <800>;
                touchscreen-size-y = <1280>;
        };
 
@@ -2048,18 +2048,11 @@
 			path_type = "SENSOR_1920X1088_30FPS_RAW12_LINER";
 			skip_init = <1>;
 		};
-		sensor1 {
+		dma {
-			subdev_name = "vivcam";
+				path_type = "VIPRE_CSI1_ISP0";
-			idx = <6>; //gc02m1b
-			csi_idx = <1>; //<1>=CSI2_B
-			mode_idx = <0>;
-			path_type = "SENSOR_1600x1200_RAW10_LINER";
-			skip_init = <1>;
 		};
 	};
-    dma {
+
-			path_type = "VIPRE_CSI1_ISP0";
-    };
 };
 
 &video13{

arch/riscv/boot/dts/thead/light-b-product.dts

@@ -591,7 +591,7 @@
                irq-gpios = <&gpio1_porta 8 0>;
                reset-gpios = <&gpio1_porta 7 0>;
                AVDD28-supply = <&reg_tp_pwr_en>;
-               touchscreen-size-x = <720>;
+               touchscreen-size-x = <800>;
                touchscreen-size-y = <1280>;
        };
 
@@ -1054,6 +1054,9 @@
 	DVDD12_SCAN-supply = <&soc_dvdd12_scan_reg>;
 	AVDD28_SCAN-supply = <&soc_avdd28_scan_en_reg>;
 	i2c_bus = /bits/ 8 <4>;
+    i2c_reg_width = /bits/ 8 <2>;
+    i2c_data_width = /bits/ 8 <1>;
+    i2c_addr = /bits/ 8 <0x30>;
 	status = "okay";
 };
 

arch/riscv/boot/dts/thead/light-crash.dts

@@ -327,7 +327,7 @@
                irq-gpios = <&gpio1_porta 8 0>;
                reset-gpios = <&gpio1_porta 7 0>;
                AVDD28-supply = <&reg_tp_pwr_en>;
-               touchscreen-size-x = <720>;
+               touchscreen-size-x = <800>;
                touchscreen-size-y = <1280>;
        };
 

arch/riscv/boot/dts/thead/light-lpi4a-ddr2G.dts

@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2022 Alibaba Group Holding Limited.
+ */
+
+#include "light-lpi4a.dts"
+
+/ {
+	model = "T-HEAD Light Lichee Pi 4A configuration for 2GB DDR board";
+	compatible = "thead,light-val", "thead,light-lpi4a-ddr2G", "thead,light";
+
+	memory@0 {
+		device_type = "memory";
+		reg = <0x0 0x00000000 0x0 0x80000000>;
+	};
+};
+
+&cmamem {
+	alloc-ranges = <0 0x64000000 0 0x14000000>; // [0x6400_0000 ~ 0x7800_0000]
+};

arch/riscv/boot/dts/thead/light-lpi4a.dts

@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2022 Alibaba Group Holding Limited.
+ */
+
+#include "light-lpi4a-ref.dts"
+
+/ {
+	model = "T-HEAD Light Lichee Pi 4A configuration for 4GB DDR board";
+	compatible = "thead,light-val", "thead,light-lpi4a", "thead,light";
+
+	memory@0 {
+		device_type = "memory";
+		reg = <0x0 0x00000000 0x1 0x00000000>;
+	};
+};
+
+&cmamem {
+	alloc-ranges = <0 0xe4000000 0 0x14000000>; // [0xE400_0000 ~ 0xF800_0000]
+};
+
+&usb_1 {
+	hubswitch-gpio = <&ao_gpio_porta 4 0>;
+	vbus-supply = <&soc_vbus_en_reg>;
+	hub1v2-supply = <&reg_usb_hub_vdd1v2>;
+	hub5v-supply = <&reg_usb_hub_vcc5v>;
+};

arch/riscv/boot/dts/thead/light.dtsi

@@ -34,6 +34,7 @@
 		i2c3 = &i2c3;
 		i2c4 = &i2c4;
 		audio_i2c0 = &audio_i2c0;
+		audio_i2c1 = &audio_i2c1;
 		mmc0 = &emmc;
 		mmc1 = &sdhci0;
 		serial0 = &uart0;
@@ -1534,6 +1535,26 @@
 			status = "disabled";
 		};
 
+		i2s2: audio_i2s2@0xffcb016000 {
+			#sound-dai-cells = <1>;
+			compatible = "light,light-i2s";
+			reg = <0xff 0xcb016000 0x0 0x1000>;
+			audio-pin-regmap = <&audio_ioctrl>;
+			audio-cpr-regmap = <&audio_cpr>;
+			pinctrl-names = "default";
+			light,mode = "i2s-master";
+			light,sel = "i2s2";
+			interrupt-parent = <&intc>;
+			interrupts = <176>;
+			dmas = <&dmac2 13>, <&dmac2 12>;
+			dma-names = "tx", "rx";
+			light,dma_maxburst = <4>;
+			#dma-cells = <1>;
+			clocks = <&dummy_clock_apb>;
+			clock-names = "pclk";
+			status = "disabled";
+		};
+
 		i2s3: audio_i2s3@0xffcb017000 {
 			#sound-dai-cells = <1>;
 			compatible = "light,light-i2s";
@@ -1684,6 +1705,27 @@
 			#size-cells = <0>;
 		};
 
+		audio_i2c1: i2c@0xffcb01b000 {
+			compatible = "snps,designware-i2c";
+			reg = <0xff 0xcb01b000 0x0 0x1000>;
+			interrupt-parent = <&intc>;
+			interrupts = <183>;
+			clocks = <&dummy_clock_apb>;
+			clock-frequency = <100000>;
+			ss_hcnt = /bits/ 16 <0x82>;
+			ss_lcnt = /bits/ 16 <0x78>;
+			fs_hcnt = /bits/ 16 <0x37>;
+			fs_lcnt = /bits/ 16 <0x42>;
+			fp_hcnt = /bits/ 16 <0x14>;
+			fp_lcnt = /bits/ 16 <0x1a>;
+			hs_hcnt = /bits/ 16 <0x5>;
+			hs_lcnt = /bits/ 16 <0x15>;
+			status = "disabled";
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
 		isp0: isp@ffe4100000 {
 			compatible = "thead,light-isp";
 			reg = <0xff 0xe4100000 0x0 0x10000>;

arch/riscv/configs/defconfig

@@ -183,6 +183,5 @@ CONFIG_DEBUG_INFO=y
 CONFIG_MAGIC_SYSRQ=y
 CONFIG_DEBUG_FS=y
 CONFIG_DETECT_HUNG_TASK=y
-CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=60
 CONFIG_DEBUG_ATOMIC_SLEEP=y
 # CONFIG_RCU_TRACE is not set

arch/riscv/configs/fire_defconfig

@@ -80,6 +80,7 @@ CONFIG_STMMAC_ETH=y
 CONFIG_DWMAC_LIGHT=y
 CONFIG_MICROSEMI_PHY=y
 CONFIG_REALTEK_PHY=y
+CONFIG_MARVELL_PHY=y
 CONFIG_USB_USBNET=m
 # CONFIG_USB_NET_AX8817X is not set
 # CONFIG_USB_NET_AX88179_178A is not set
@@ -299,7 +300,6 @@ CONFIG_DEBUG_INFO=y
 CONFIG_MAGIC_SYSRQ=y
 CONFIG_DEBUG_FS=y
 CONFIG_DETECT_HUNG_TASK=y
-CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=60
 CONFIG_DEBUG_ATOMIC_SLEEP=y
 # CONFIG_RCU_TRACE is not set
 CONFIG_OVERLAY_FS=y

arch/riscv/configs/fire_emu_defconfig

@@ -17,6 +17,7 @@ CONFIG_PERF_EVENTS=y
 CONFIG_FORCE_MAX_ZONEORDER=15
 CONFIG_SOC_SIFIVE=y
 CONFIG_SOC_THEAD=y
+CONFIG_SOC_THEAD_LIGHT_EMU=y
 CONFIG_SMP=y
 CONFIG_VECTOR=y
 CONFIG_VECTOR_0_7=y
@@ -80,6 +81,7 @@ CONFIG_STMMAC_ETH=y
 CONFIG_DWMAC_LIGHT=y
 CONFIG_MICROSEMI_PHY=y
 CONFIG_REALTEK_PHY=y
+CONFIG_MARVELL_PHY=y
 CONFIG_USB_USBNET=m
 # CONFIG_USB_NET_AX8817X is not set
 # CONFIG_USB_NET_AX88179_178A is not set
@@ -299,7 +301,6 @@ CONFIG_DEBUG_INFO=y
 CONFIG_MAGIC_SYSRQ=y
 CONFIG_DEBUG_FS=y
 CONFIG_DETECT_HUNG_TASK=y
-CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=60
 CONFIG_DEBUG_ATOMIC_SLEEP=y
 # CONFIG_RCU_TRACE is not set
 CONFIG_OVERLAY_FS=y

arch/riscv/configs/ice_defconfig

@@ -180,6 +180,5 @@ CONFIG_DEBUG_INFO=y
 CONFIG_MAGIC_SYSRQ=y
 CONFIG_DEBUG_FS=y
 CONFIG_DETECT_HUNG_TASK=y
-CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=60
 CONFIG_DEBUG_ATOMIC_SLEEP=y
 # CONFIG_RCU_TRACE is not set

arch/riscv/configs/light-android_defconfig

@@ -561,7 +561,6 @@ CONFIG_DYNAMIC_DEBUG=y
 CONFIG_DEBUG_FS=y
 CONFIG_PANIC_TIMEOUT=5
 CONFIG_DETECT_HUNG_TASK=y
-CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=60
 CONFIG_SCHEDSTATS=y
 CONFIG_DEBUG_ATOMIC_SLEEP=y
 # CONFIG_GCC_PLUGINS is not set

arch/riscv/configs/light_defconfig

@@ -198,6 +198,7 @@ CONFIG_DRM=y
 CONFIG_DRM_PANEL_SIMPLE=y
 CONFIG_DRM_PANEL_ILITEK_ILI9881C=y
 CONFIG_DRM_PANEL_ILI9881D=y
+CONFIG_DRM_PANEL_HX8394=y
 CONFIG_DRM_VERISILICON=y
 CONFIG_BACKLIGHT_CLASS_DEVICE=y
 CONFIG_BACKLIGHT_PWM=y
@@ -313,7 +314,6 @@ CONFIG_DEBUG_INFO=y
 CONFIG_MAGIC_SYSRQ=y
 CONFIG_DEBUG_FS=y
 CONFIG_DETECT_HUNG_TASK=y
-CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=60
 CONFIG_DEBUG_ATOMIC_SLEEP=y
 # CONFIG_RCU_TRACE is not set
 CONFIG_OVERLAY_FS=y

arch/riscv/configs/light_emu_defconfig

@@ -189,7 +189,6 @@ CONFIG_DYNAMIC_DEBUG=y
 CONFIG_DEBUG_INFO=y
 CONFIG_DEBUG_FS=y
 CONFIG_DETECT_HUNG_TASK=y
-CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=60
 CONFIG_DEBUG_ATOMIC_SLEEP=y
 # CONFIG_RCU_TRACE is not set
 CONFIG_FORCE_MAX_ZONEORDER=15

arch/riscv/configs/vector_0_7_defconfig

@@ -184,6 +184,5 @@ CONFIG_DEBUG_INFO=y
 CONFIG_MAGIC_SYSRQ=y
 CONFIG_DEBUG_FS=y
 CONFIG_DETECT_HUNG_TASK=y
-CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=60
 CONFIG_DEBUG_ATOMIC_SLEEP=y
 # CONFIG_RCU_TRACE is not set

arch/riscv/kernel/machine_kexec.c

@@ -179,9 +179,10 @@ machine_crash_shutdown(struct pt_regs *regs)
 {
 	local_irq_disable();
 
+#ifdef CONFIG_SMP
 	/* shutdown non-crashing cpus */
 	crash_smp_send_stop();
-
+#endif
 	crash_save_cpu(regs, smp_processor_id());
 	machine_kexec_mask_interrupts();
 
@@ -211,8 +212,10 @@ machine_kexec(struct kimage *image)
 	void *control_code_buffer = page_address(image->control_code_page);
 	riscv_kexec_method kexec_method = NULL;
 
+#ifdef CONFIG_SMP
 	WARN(smp_crash_stop_failed(),
 		"Some CPUs may be stale, kdump will be unreliable.\n");
+#endif
 
 	if (image->type != KEXEC_TYPE_CRASH)
 		kexec_method = control_code_buffer;

arch/riscv/kernel/perf_callchain.c

@@ -75,13 +75,13 @@ void perf_callchain_user(struct perf_callchain_entry_ctx *entry,
 		fp = user_backtrace(entry, fp, 0);
 }
 
-bool fill_callchain(unsigned long pc, void *entry)
+bool fill_callchain(unsigned long pc, unsigned long regs, void *entry)
 {
 	return perf_callchain_store(entry, pc) == 0;
 }
 
 void notrace walk_stackframe(struct task_struct *task,
-	struct pt_regs *regs, bool (*fn)(unsigned long, void *), void *arg);
+	struct pt_regs *regs, bool (*fn)(unsigned long, unsigned long, void *), void *arg);
 void perf_callchain_kernel(struct perf_callchain_entry_ctx *entry,
 			   struct pt_regs *regs)
 {

arch/riscv/kernel/probes/kprobes.c

@@ -46,6 +46,21 @@ static void __kprobes arch_simulate_insn(struct kprobe *p, struct pt_regs *regs)
 	post_kprobe_handler(kcb, regs);
 }
 
+static bool __kprobes arch_check_kprobe(struct kprobe *p)
+{
+	unsigned long tmp  = (unsigned long)p->addr - p->offset;
+	unsigned long addr = (unsigned long)p->addr;
+
+	while (tmp <= addr) {
+		if (tmp == addr)
+			return true;
+
+		tmp += GET_INSN_LENGTH(*(u16 *)tmp);
+	}
+
+	return false;
+}
+
 int __kprobes arch_prepare_kprobe(struct kprobe *p)
 {
 	unsigned long probe_addr = (unsigned long)p->addr;
@@ -56,6 +71,9 @@ int __kprobes arch_prepare_kprobe(struct kprobe *p)
 		return -EINVAL;
 	}
 
+	if (!arch_check_kprobe(p))
+		return -EILSEQ;
+
 	/* copy instruction */
 	p->opcode = le32_to_cpu(*p->addr);
 

drivers/gpu/drm/panel/Kconfig

@@ -510,4 +510,13 @@ config DRM_PANEL_ILI9881D
 	  Say Y if you want to enable support for panels based on the
 	  ILI9881d controller.
 
+config DRM_PANEL_HX8394
+	tristate "HX8394-based panels"
+	depends on OF
+	depends on DRM_MIPI_DSI
+	depends on BACKLIGHT_CLASS_DEVICE
+	help
+	  Say Y if you want to enable support for panels based on the
+	  HX8394 controller.
+
 endmenu

drivers/gpu/drm/panel/Makefile

@@ -54,3 +54,4 @@ obj-$(CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA) += panel-truly-nt35597.o
 obj-$(CONFIG_DRM_PANEL_VISIONOX_RM69299) += panel-visionox-rm69299.o
 obj-$(CONFIG_DRM_PANEL_XINPENG_XPP055C272) += panel-xinpeng-xpp055c272.o
 obj-$(CONFIG_DRM_PANEL_ILI9881D) += panel-ili9881d.o
+obj-$(CONFIG_DRM_PANEL_HX8394) += panel-himax8394.o

drivers/gpu/drm/panel/panel-himax8394.c

@@ -0,0 +1,429 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Diiver for panels based on Himax HX8394 controller
+ * Copyright (c) 2023, Alibaba-inc Co., Ltd
+ *
+ */
+
+#include <linux/delay.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+
+#include <linux/gpio/consumer.h>
+#include <linux/regulator/consumer.h>
+
+#include <drm/drm_device.h>
+#include <drm/drm_mipi_dsi.h>
+#include <drm/drm_modes.h>
+#include <drm/drm_panel.h>
+
+#include <video/mipi_display.h>
+
+struct hx8394_panel_cmd {
+	char cmdlen;
+	char cmddata[0x40];
+};
+
+struct hx8394_panel_desc {
+	const struct drm_display_mode *display_mode;
+
+	unsigned long mode_flags;
+	enum mipi_dsi_pixel_format format;
+	unsigned int lanes;
+	const struct hx8394_panel_cmd *on_cmds;
+	unsigned int on_cmds_num;
+};
+
+struct panel_info {
+	struct drm_panel base;
+	struct mipi_dsi_device *link;
+	const struct hx8394_panel_desc *desc;
+
+	struct gpio_desc	*reset;
+	struct regulator	*hsvcc;
+	struct regulator	*vspn3v3;
+
+	bool prepared;
+	bool enabled;
+};
+
+static inline struct panel_info *to_panel_info(struct drm_panel *panel)
+{
+	return container_of(panel, struct panel_info, base);
+}
+
+static int hx8394_send_mipi_cmds(struct drm_panel *panel, const struct hx8394_panel_cmd *cmds)
+{
+	struct panel_info *pinfo = to_panel_info(panel);
+	unsigned int i = 0;
+	int err;
+
+	for (i = 0; i < pinfo->desc->on_cmds_num; i++) {
+		err = mipi_dsi_dcs_write_buffer(pinfo->link, &(cmds[i].cmddata[0]), cmds[i].cmdlen);
+		if (err < 0)
+			return err;
+	}
+
+	return 0;
+}
+
+static int hx8394_panel_disable(struct drm_panel *panel)
+{
+	struct panel_info *pinfo = to_panel_info(panel);
+	int err;
+
+	if (!pinfo->enabled)
+		return 0;
+
+	err = mipi_dsi_dcs_set_display_off(pinfo->link);
+	if (err < 0) {
+		dev_err(panel->dev, "failed to set display off: %d\n", err);
+		return err;
+	}
+
+	pinfo->enabled = false;
+
+	return 0;
+}
+
+static int hx8394_panel_unprepare(struct drm_panel *panel)
+{
+	struct panel_info *pinfo = to_panel_info(panel);
+	int err;
+
+	if (!pinfo->prepared)
+		return 0;
+
+	err = mipi_dsi_dcs_set_display_off(pinfo->link);
+	if (err < 0)
+		dev_err(panel->dev, "failed to set display off: %d\n", err);
+
+	err = mipi_dsi_dcs_enter_sleep_mode(pinfo->link);
+	if (err < 0)
+		dev_err(panel->dev, "failed to enter sleep mode: %d\n", err);
+
+	/* sleep_mode_delay: 1ms - 2ms */
+	usleep_range(1000, 2000);
+
+	gpiod_set_value(pinfo->reset, 1);
+	regulator_disable(pinfo->hsvcc);
+	regulator_disable(pinfo->vspn3v3);
+
+	pinfo->prepared = false;
+
+	return 0;
+}
+
+static int hx8394_panel_prepare(struct drm_panel *panel)
+{
+	struct panel_info *pinfo = to_panel_info(panel);
+	int ret;
+
+	if (pinfo->prepared)
+		return 0;
+	gpiod_set_value(pinfo->reset, 1);
+
+	/* Power the panel */
+	ret = regulator_enable(pinfo->hsvcc);
+	if (ret) {
+		dev_err(pinfo->base.dev, "Failed to enable hsvcc supply: %d\n", ret);
+		return ret;
+	}
+
+	usleep_range(1000, 2000);
+	ret = regulator_enable(pinfo->vspn3v3);
+	if (ret) {
+		dev_err(pinfo->base.dev, "Failed to enable vspn3v3 supply: %d\n", ret);
+		goto fail;
+	}
+	usleep_range(5000, 6000);
+
+	gpiod_set_value(pinfo->reset, 0);
+	msleep(180);
+
+	pinfo->prepared = true;
+
+	return 0;
+
+fail:
+	gpiod_set_value(pinfo->reset, 1);
+	regulator_disable(pinfo->hsvcc);
+	return ret;
+}
+
+static int hx8394_read_id(struct mipi_dsi_device *dsi, u8 *id1)
+{
+	int ret;
+
+	ret = mipi_dsi_dcs_read(dsi, 0xDA, id1, 1);
+	if (ret < 0) {
+		dev_err(&dsi->dev, "could not read ID1\n");
+		return ret;
+	}
+	dev_info(&dsi->dev, "ID1 : 0x%02x\n", *id1);
+
+	return 0;
+}
+
+static int hx8394_panel_enable(struct drm_panel *panel)
+{
+	struct panel_info *pinfo = to_panel_info(panel);
+	int ret;
+	u8 id1;
+
+	if (pinfo->enabled)
+		return 0;
+
+	ret = hx8394_read_id(pinfo->link, &id1);
+	if (ret < 0)
+		dev_info(panel->dev, "No LCD connected,pls check your hardware! ret:%d\n", ret);
+
+	/* send init code */
+	ret = hx8394_send_mipi_cmds(panel, pinfo->desc->on_cmds);
+	if (ret < 0) {
+		dev_err(panel->dev, "failed to send DCS Init Code: %d\n", ret);
+		return ret;
+	}
+
+	ret = mipi_dsi_dcs_exit_sleep_mode(pinfo->link);
+	if (ret < 0) {
+		dev_err(panel->dev, "failed to exit sleep mode: %d\n", ret);
+		return ret;
+	}
+
+	msleep(120);
+
+	ret = mipi_dsi_dcs_set_display_on(pinfo->link);
+	if (ret < 0) {
+		dev_err(panel->dev, "failed to set display on: %d\n", ret);
+		return ret;
+	}
+
+	pinfo->enabled = true;
+
+	return 0;
+}
+
+static int hx8394_panel_get_modes(struct drm_panel *panel,
+			       struct drm_connector *connector)
+{
+	struct panel_info *pinfo = to_panel_info(panel);
+	const struct drm_display_mode *m = pinfo->desc->display_mode;
+	struct drm_display_mode *mode;
+
+	mode = drm_mode_duplicate(connector->dev, m);
+	if (!mode) {
+		dev_err(pinfo->base.dev, "failed to add mode %ux%u@%u\n",
+			m->hdisplay, m->vdisplay, drm_mode_vrefresh(m));
+		return -ENOMEM;
+	}
+
+	drm_mode_set_name(mode);
+
+	mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
+	drm_mode_probed_add(connector, mode);
+
+	connector->display_info.width_mm = mode->width_mm;
+	connector->display_info.height_mm = mode->height_mm;
+
+	return 1;
+}
+
+static const struct drm_panel_funcs panel_funcs = {
+	.disable = hx8394_panel_disable,
+	.unprepare = hx8394_panel_unprepare,
+	.prepare = hx8394_panel_prepare,
+	.enable = hx8394_panel_enable,
+	.get_modes = hx8394_panel_get_modes,
+};
+
+static const struct drm_display_mode hx8394_default_mode = {
+	.clock		= 76000,
+	.hdisplay	= 720,
+	.hsync_start	= 720 + 45,
+	.hsync_end	= 720 + 45 + 8,
+	.htotal		= 720 + 45 + 8 + 45,
+
+	.vdisplay	= 1280,
+	.vsync_start	= 1280 + 16,
+	.vsync_end	= 1280 + 16 + 8,
+	.vtotal		= 1280 + 16 + 8 + 16,
+
+	.width_mm	= 62,
+	.height_mm	= 110,
+	.flags          = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
+};
+
+static const struct hx8394_panel_cmd hx8394_on_cmds[] = {
+	{ .cmdlen = 4,	.cmddata = {0xB9, 0xFF, 0x83, 0x94} },
+	{ .cmdlen = 11,	.cmddata = {0xB1, 0x48, 0x0A, 0x6A, 0x09, 0x33, 0x54,
+				0x71, 0x71, 0x2E, 0x45} },
+	{ .cmdlen = 7,	.cmddata = {0xBA, 0x63, 0x03, 0x68, 0x6B, 0xB2, 0xC0} },
+	{ .cmdlen = 7,	.cmddata = {0xB2, 0x00, 0x80, 0x64, 0x0C, 0x06, 0x2F} },
+	{ .cmdlen = 22, .cmddata = {0xB4, 0x1C, 0x78, 0x1C, 0x78, 0x1C, 0x78, 0x01,
+				0x0C, 0x86, 0x75, 0x00, 0x3F, 0x1C, 0x78, 0x1C,
+				0x78, 0x1C, 0x78, 0x01, 0x0C, 0x86} },
+	{ .cmdlen = 34, .cmddata = {0xD3, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08,
+				0x08, 0x32, 0x10, 0x05, 0x00, 0x05, 0x32, 0x13,
+				0xC1, 0x00, 0x01, 0x32, 0x10, 0x08, 0x00, 0x00,
+				0x37, 0x03, 0x07, 0x07, 0x37, 0x05, 0x05, 0x37,
+				0x0C, 0x40} },
+	{ .cmdlen = 45, .cmddata = {0xD5, 0x18, 0x18, 0x18, 0x18, 0x22, 0x23, 0x20,
+				0x21, 0x04, 0x05, 0x06, 0x07, 0x00, 0x01, 0x02,
+				0x03, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
+				0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
+				0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
+				0x18, 0x19, 0x19, 0x19, 0x19} },
+	{ .cmdlen = 45, .cmddata = {0xD6, 0x18, 0x18, 0x19, 0x19, 0x21, 0x20, 0x23,
+				0x22, 0x03, 0x02, 0x01, 0x00, 0x07, 0x06, 0x05,
+				0x04, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
+				0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
+				0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
+				0x18, 0x19, 0x19, 0x18, 0x18} },
+	{ .cmdlen = 59, .cmddata = {0xE0, 0x07, 0x08, 0x09, 0x0D, 0x10, 0x14, 0x16,
+				0x13, 0x24, 0x36, 0x48, 0x4A, 0x58, 0x6F, 0x76,
+				0x80, 0x97, 0xA5, 0xA8, 0xB5, 0xC6, 0x62, 0x63,
+				0x68, 0x6F, 0x72, 0x78, 0x7F, 0x7F, 0x00, 0x02,
+				0x08, 0x0D, 0x0C, 0x0E, 0x0F, 0x10, 0x24, 0x36,
+				0x48, 0x4A, 0x58, 0x6F, 0x78, 0x82, 0x99, 0xA4,
+				0xA0, 0xB1, 0xC0, 0x5E, 0x5E, 0x64, 0x6B, 0x6C,
+				0x73, 0x7F, 0x7F} },
+	{ .cmdlen = 2, .cmddata = {0xCC, 0x03} },
+	{ .cmdlen = 3, .cmddata = {0xC0, 0x1F, 0x73} },
+	{ .cmdlen = 3, .cmddata = {0xB6, 0x90, 0x90} },
+	{ .cmdlen = 2, .cmddata = {0xD4, 0x02} },
+	{ .cmdlen = 2, .cmddata = {0xBD, 0x01} },
+	{ .cmdlen = 2, .cmddata = {0xB1, 0x00} },
+	{ .cmdlen = 2, .cmddata = {0xBD, 0x00} },
+	{ .cmdlen = 8, .cmddata = {0xBF, 0x40, 0x81, 0x50, 0x00, 0x1A, 0xFC, 0x01} },
+
+	{ .cmdlen = 2, .cmddata = {0x36, 0x02} },
+};
+
+static const struct hx8394_panel_desc hx8394_desc = {
+	.display_mode = &hx8394_default_mode,
+	.mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_VIDEO_BURST,
+	.format = MIPI_DSI_FMT_RGB888,
+	.lanes = 4,
+	.on_cmds = hx8394_on_cmds,
+	.on_cmds_num = ARRAY_SIZE(hx8394_on_cmds),
+};
+
+static const struct of_device_id panel_of_match[] = {
+	{
+		.compatible = "himax,hx8394",
+		.data = &hx8394_desc,
+	},
+	{
+		/* sentinel */
+	}
+};
+MODULE_DEVICE_TABLE(of, panel_of_match);
+
+static int hx8394_panel_add(struct panel_info *pinfo)
+{
+	struct device *dev = &pinfo->link->dev;
+	int ret;
+
+	pinfo->reset = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
+	if (IS_ERR(pinfo->reset))
+		return dev_err_probe(dev, PTR_ERR(pinfo->reset),
+				"Couldn't get our reset GPIO\n");
+
+	pinfo->hsvcc =  devm_regulator_get(dev, "hsvcc");
+	if (IS_ERR(pinfo->hsvcc))
+		return dev_err_probe(dev, PTR_ERR(pinfo->hsvcc),
+				"Failed to request hsvcc regulator\n");
+
+	pinfo->vspn3v3 =  devm_regulator_get(dev, "vspn3v3");
+	if (IS_ERR(pinfo->vspn3v3))
+		return dev_err_probe(dev, PTR_ERR(pinfo->vspn3v3),
+				"Failed to request vspn3v3 regulator\n");
+
+	drm_panel_init(&pinfo->base, dev, &panel_funcs,
+		       DRM_MODE_CONNECTOR_DSI);
+
+	ret = drm_panel_of_backlight(&pinfo->base);
+	if (ret)
+		return ret;
+
+	drm_panel_add(&pinfo->base);
+
+	return 0;
+}
+
+static int hx8394_panel_probe(struct mipi_dsi_device *dsi)
+{
+	struct panel_info *pinfo;
+	const struct hx8394_panel_desc *desc;
+	int err;
+
+	pinfo = devm_kzalloc(&dsi->dev, sizeof(*pinfo), GFP_KERNEL);
+	if (!pinfo)
+		return -ENOMEM;
+
+	desc = of_device_get_match_data(&dsi->dev);
+	dsi->mode_flags = desc->mode_flags;
+	dsi->format = desc->format;
+	dsi->lanes = desc->lanes;
+	pinfo->desc = desc;
+
+	pinfo->link = dsi;
+	mipi_dsi_set_drvdata(dsi, pinfo);
+
+	err = hx8394_panel_add(pinfo);
+	if (err < 0)
+		return err;
+
+	err = mipi_dsi_attach(dsi);
+	if (err < 0)
+		drm_panel_remove(&pinfo->base);
+
+	return err;
+}
+
+static int hx8394_panel_remove(struct mipi_dsi_device *dsi)
+{
+	struct panel_info *pinfo = mipi_dsi_get_drvdata(dsi);
+	int err;
+
+	err = hx8394_panel_disable(&pinfo->base);
+	if (err < 0)
+		dev_err(&dsi->dev, "failed to disable panel: %d\n", err);
+
+	err = hx8394_panel_unprepare(&pinfo->base);
+	if (err < 0)
+		dev_err(&dsi->dev, "failed to unprepare panel: %d\n", err);
+
+	err = mipi_dsi_detach(dsi);
+	if (err < 0)
+		dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err);
+
+	drm_panel_remove(&pinfo->base);
+
+	return 0;
+}
+
+static void hx8394_panel_shutdown(struct mipi_dsi_device *dsi)
+{
+	struct panel_info *pinfo = mipi_dsi_get_drvdata(dsi);
+
+	hx8394_panel_disable(&pinfo->base);
+	hx8394_panel_unprepare(&pinfo->base);
+}
+
+static struct mipi_dsi_driver panel_driver = {
+	.driver = {
+		.name = "panel-himax8394",
+		.of_match_table = panel_of_match,
+	},
+	.probe = hx8394_panel_probe,
+	.remove = hx8394_panel_remove,
+	.shutdown = hx8394_panel_shutdown,
+};
+module_mipi_dsi_driver(panel_driver);
+
+MODULE_DESCRIPTION("Himax8394 driver");
+MODULE_LICENSE("GPL v2");

drivers/irqchip/irq-riscv-intc.c

@@ -30,6 +30,7 @@ static asmlinkage void riscv_intc_irq(struct pt_regs *regs)
 #define MATCH_DCACHE_CVAL1 0x0240000b
 #define MASK_DCACHE_CVAL1 0xfff07fff
 
+	pagefault_disable();
 	if ((epc & 0x7f) != 4)
 		goto out;
 
@@ -47,6 +48,7 @@ static asmlinkage void riscv_intc_irq(struct pt_regs *regs)
 
 	instruction_pointer_set(regs, epc - 4);
 out:
+	pagefault_enable();
 	if (unlikely(cause >= BITS_PER_LONG))
 		panic("unexpected interrupt cause");
 

drivers/net/phy/realtek.c

@@ -635,6 +635,7 @@ static struct phy_driver realtek_drvs[] = {
 		.name		= "RTL8211F Gigabit Ethernet",
 		.config_init	= &rtl8211f_config_init,
 		.ack_interrupt	= &rtl8211f_ack_interrupt,
+		.read_status	= rtlgen_read_status,
 		.config_intr	= &rtl8211f_config_intr,
 		.suspend	= genphy_suspend,
 		.resume		= rtl821x_resume,

drivers/phy/synopsys/phy-dw-mipi-dphy.c

@@ -473,7 +473,7 @@ static int dw_dphy_get_pll_cfg(struct dw_dphy *dphy,
 
 	vco_div = 1 << (range->vco_range >> 4);
 	fout = fout * vco_div;
-	pr_info("%s: vco_div = %u\n", __func__, vco_div);
+	pr_debug("%s: vco_div = %u\n", __func__, vco_div);
 
 	n_min = DIV_ROUND_UP_ULL(fin, FIN_DIV_N_FREQ_MAX * 1000);
 	n_max = DIV_ROUND_UP_ULL(fin, FIN_DIV_N_FREQ_MIN * 1000);

drivers/usb/dwc3/dwc3-thead.c

@@ -14,6 +14,8 @@
 #include <linux/kernel.h>
 #include <linux/extcon.h>
 #include <linux/of_platform.h>
+#include <linux/gpio/consumer.h>
+#include <linux/regulator/consumer.h>
 #include <linux/mfd/syscon.h>
 #include <linux/regmap.h>
 #include <linux/platform_device.h>
@@ -83,6 +85,11 @@ struct dwc3_thead {
 	struct notifier_block	vbus_nb;
 	struct notifier_block	host_nb;
 
+	struct gpio_desc	*hubswitch;
+	struct regulator	*hub1v2;
+	struct regulator	*hub5v;
+	struct regulator	*vbus;
+
 	enum usb_dr_mode	mode;
 	bool			is_suspended;
 	bool			pm_suspended;
@@ -248,6 +255,28 @@ static int dwc3_thead_probe(struct platform_device *pdev)
 	platform_set_drvdata(pdev, thead);
 	thead->dev = &pdev->dev;
 
+	thead->hubswitch = devm_gpiod_get(dev, "hubswitch", GPIOD_OUT_HIGH);
+	if (IS_ERR(thead->hubswitch))
+		dev_dbg(dev, "no need to get hubswitch GPIO\n");
+
+	thead->vbus = devm_regulator_get(dev, "vbus");
+	if (IS_ERR(thead->vbus))
+		dev_dbg(dev, "no need to get vbus\n");
+	else
+		regulator_enable(thead->vbus);
+
+	thead->hub1v2 = devm_regulator_get(dev, "hub1v2");
+	if (IS_ERR(thead->hub1v2))
+		dev_dbg(dev, "no need to set hub1v2\n");
+	else
+		regulator_enable(thead->hub1v2);
+
+	thead->hub5v = devm_regulator_get(dev, "hub5v");
+	if (IS_ERR(thead->hub5v))
+		dev_dbg(dev, "no need to set hub5v\n");
+	else
+		regulator_enable(thead->hub5v);
+
 	thead->misc_sysreg = syscon_regmap_lookup_by_phandle(np, "usb3-misc-regmap");
 	if (IS_ERR(thead->misc_sysreg))
 		return PTR_ERR(thead->misc_sysreg);

include/dt-bindings/pinctrl/light-fm-aon-pinctrl.h

@@ -43,4 +43,36 @@
 #define FM_AUDIO_PA29			45
 #define FM_AUDIO_PA30			46
 
+#define FM_AUDIO_CFG_PA0			25
+#define FM_AUDIO_CFG_PA1			26
+#define FM_AUDIO_CFG_PA2			27
+#define FM_AUDIO_CFG_PA3			28
+#define FM_AUDIO_CFG_PA4			29
+#define FM_AUDIO_CFG_PA5			30
+#define FM_AUDIO_CFG_PA6			31
+#define FM_AUDIO_CFG_PA7			32
+#define FM_AUDIO_CFG_PA8			33
+#define FM_AUDIO_CFG_PA9			34
+#define FM_AUDIO_CFG_PA10			35
+#define FM_AUDIO_CFG_PA11			36
+#define FM_AUDIO_CFG_PA12			37
+#define FM_AUDIO_CFG_PA13			38
+#define FM_AUDIO_CFG_PA14			39
+#define FM_AUDIO_CFG_PA15			40
+#define FM_AUDIO_CFG_PA16			41
+#define FM_AUDIO_CFG_PA17			42
+#define FM_AUDIO_CFG_PA18			43
+#define FM_AUDIO_CFG_PA19			44
+#define FM_AUDIO_CFG_PA20			45
+#define FM_AUDIO_CFG_PA21			46
+#define FM_AUDIO_CFG_PA22			47
+#define FM_AUDIO_CFG_PA23			48
+#define FM_AUDIO_CFG_PA24			49
+#define FM_AUDIO_CFG_PA25			50
+#define FM_AUDIO_CFG_PA26			51
+#define FM_AUDIO_CFG_PA27			52
+#define FM_AUDIO_CFG_PA28			53
+#define FM_AUDIO_CFG_PA29			54
+#define FM_AUDIO_CFG_PA30			55
+
 #endif	/* _LIGHT_FM_AUDIO_PINCTRL_H */

sound/soc/thead/light-i2s.c

@@ -39,6 +39,7 @@
 #define AP_I2S		"ap_i2s"
 #define AUDIO_I2S0	"i2s0"
 #define AUDIO_I2S1	"i2s1"
+#define AUDIO_I2S2	"i2s2"
 #define AUDIO_I2S3	"i2s3"
 
 #define LIGHT_I2S_DMABUF_SIZE     (64 * 1024)
@@ -89,6 +90,14 @@ static void light_i2s_set_div_sclk(struct light_i2s_priv *chip, u32 sample_rate,
 				light_audio_cpr_set(chip, CPR_PERI_CLK_SEL_REG, CPR_I2S1_SRC_SEL_MSK, CPR_I2S1_SRC_SEL(2));
 				div = AUDIO_IIS_SRC1_CLK / IIS_MCLK_SEL;
 			}
+		} else if (!strcmp(chip->name, AUDIO_I2S2)) {
+			if (!i2s_src_clk) {
+				light_audio_cpr_set(chip, CPR_PERI_CLK_SEL_REG, CPR_I2S2_SRC_SEL_MSK, CPR_I2S2_SRC_SEL(0));
+				div = AUDIO_IIS_SRC0_CLK / IIS_MCLK_SEL;
+			} else {
+				light_audio_cpr_set(chip, CPR_PERI_CLK_SEL_REG, CPR_I2S2_SRC_SEL_MSK, CPR_I2S2_SRC_SEL(2));
+				div = AUDIO_IIS_SRC1_CLK / IIS_MCLK_SEL;
+			}
 		} else if (!strcmp(chip->name, AUDIO_I2S3)) {
 				div = AUDIO_IIS_SRC0_CLK / IIS_MCLK_SEL;
 		}
@@ -552,19 +561,26 @@ static int light_audio_pinctrl(struct device *dev)
 	struct light_i2s_priv *i2s_priv = dev_get_drvdata(dev);
 
 	if (!strcmp(i2s_priv->name, AUDIO_I2S0)) {
-		light_audio_pinconf_set(i2s_priv->dev, FM_AUDIO_PA6, 0x4);
+		light_audio_pinconf_set(i2s_priv->dev, FM_AUDIO_CFG_PA6, 0x4);
-		light_audio_pinconf_set(i2s_priv->dev, FM_AUDIO_PA7, 0x4);
+		light_audio_pinconf_set(i2s_priv->dev, FM_AUDIO_CFG_PA7, 0x4);
-		light_audio_pinconf_set(i2s_priv->dev, FM_AUDIO_PA9, 0x8);
+		light_audio_pinconf_set(i2s_priv->dev, FM_AUDIO_CFG_PA9, 0x8);
-		light_audio_pinconf_set(i2s_priv->dev, FM_AUDIO_PA10, 0x8);
+		light_audio_pinconf_set(i2s_priv->dev, FM_AUDIO_CFG_PA10, 0x8);
-		light_audio_pinconf_set(i2s_priv->dev, FM_AUDIO_PA11, 0x8);
+		light_audio_pinconf_set(i2s_priv->dev, FM_AUDIO_CFG_PA11, 0x8);
-		light_audio_pinconf_set(i2s_priv->dev, FM_AUDIO_PA12, 0x8);
+		light_audio_pinconf_set(i2s_priv->dev, FM_AUDIO_CFG_PA12, 0x8);
 	} else if (!strcmp(i2s_priv->name, AUDIO_I2S1)) {
-		light_audio_pinconf_set(i2s_priv->dev, FM_AUDIO_PA6, 0x4);
+		light_audio_pinconf_set(i2s_priv->dev, FM_AUDIO_CFG_PA6, 0x4);
-		light_audio_pinconf_set(i2s_priv->dev, FM_AUDIO_PA7, 0x4);
+		light_audio_pinconf_set(i2s_priv->dev, FM_AUDIO_CFG_PA7, 0x4);
-		light_audio_pinconf_set(i2s_priv->dev, FM_AUDIO_PA13, 0x8);
+		light_audio_pinconf_set(i2s_priv->dev, FM_AUDIO_CFG_PA13, 0x8);
-		light_audio_pinconf_set(i2s_priv->dev, FM_AUDIO_PA14, 0x8);
+		light_audio_pinconf_set(i2s_priv->dev, FM_AUDIO_CFG_PA14, 0x8);
-		light_audio_pinconf_set(i2s_priv->dev, FM_AUDIO_PA15, 0x8);
+		light_audio_pinconf_set(i2s_priv->dev, FM_AUDIO_CFG_PA15, 0x8);
-		light_audio_pinconf_set(i2s_priv->dev, FM_AUDIO_PA17, 0x8);
+		light_audio_pinconf_set(i2s_priv->dev, FM_AUDIO_CFG_PA17, 0x8);
+	} else if (!strcmp(i2s_priv->name, AUDIO_I2S2)) {
+		light_audio_pinconf_set(i2s_priv->dev, FM_AUDIO_CFG_PA6, 0x5);
+		light_audio_pinconf_set(i2s_priv->dev, FM_AUDIO_CFG_PA7, 0x5);
+		light_audio_pinconf_set(i2s_priv->dev, FM_AUDIO_CFG_PA18, 0x8);
+		light_audio_pinconf_set(i2s_priv->dev, FM_AUDIO_CFG_PA19, 0x8);
+		light_audio_pinconf_set(i2s_priv->dev, FM_AUDIO_CFG_PA21, 0x8);
+		light_audio_pinconf_set(i2s_priv->dev, FM_AUDIO_CFG_PA22, 0x8);
 	}
 
 	return 0;
@@ -656,7 +672,7 @@ static int light_audio_i2s_probe(struct platform_device *pdev)
                 return PTR_ERR(i2s_priv->regmap);
         }
 
-	if (!strcmp(i2s_priv->name, AUDIO_I2S0) || !strcmp(i2s_priv->name, AUDIO_I2S1)) {
+	if (!strcmp(i2s_priv->name, AUDIO_I2S0) || !strcmp(i2s_priv->name, AUDIO_I2S1) || !strcmp(i2s_priv->name, AUDIO_I2S2)) {
 		i2s_priv->audio_pin_regmap = syscon_regmap_lookup_by_phandle(np, "audio-pin-regmap");
 		if (IS_ERR(i2s_priv->audio_pin_regmap)) {
 			dev_err(&pdev->dev, "cannot find regmap for audio system register\n");
@@ -700,7 +716,7 @@ static int light_audio_i2s_probe(struct platform_device *pdev)
 	if (!strcmp(i2s_priv->name, AP_I2S)) {
 		i2s_priv->dma_params_tx.addr = res->start + I2S_DR;
 		i2s_priv->dma_params_rx.addr = res->start + I2S_DR1;
-	} else if (!strcmp(i2s_priv->name, AUDIO_I2S0) || !strcmp(i2s_priv->name, AUDIO_I2S1)) {
+	} else if (!strcmp(i2s_priv->name, AUDIO_I2S0) || !strcmp(i2s_priv->name, AUDIO_I2S1) || !strcmp(i2s_priv->name, AUDIO_I2S2)) {
 		i2s_priv->dma_params_tx.addr = res->start + I2S_DR;
 		i2s_priv->dma_params_rx.addr = res->start + I2S_DR;
 	} else if (!strcmp(i2s_priv->name, AUDIO_I2S3)) {

sound/soc/thead/light-i2s.h

@@ -477,6 +477,12 @@
 #define CPR_I2S1_SRC_SEL_24M                   (0x1U << AUDIOSYS_I2S1_SRC_SEL_POS)
 #define CPR_I2S1_SRC_SEL_AUDIO_DIVCLK1         (0x2U << AUDIOSYS_I2S1_SRC_SEL_POS)
 
+#define CPR_I2S2_SRC_SEL_POS                   (8U)
+#define CPR_I2S2_SRC_SEL_MSK                   (0x3U << CPR_I2S2_SRC_SEL_POS)
+#define CPR_I2S2_SRC_SEL(X)                    (X << CPR_I2S2_SRC_SEL_POS)
+#define CPR_I2S2_SRC_SEL_24M                   (0x1U << AUDIOSYS_I2S2_SRC_SEL_POS)
+#define CPR_I2S2_SRC_SEL_AUDIO_DIVCLK1         (0x2U << AUDIOSYS_I2S2_SRC_SEL_POS)
+
 struct light_i2s_priv {
 	void __iomem *base;
 	phys_addr_t phys;