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f72e7cd077
This version update involves a lot of content, so the previous version has been deleted and the new version has been re-merged into the kernel. The configuration file for the GPU driver originates from a previous version. Signed-off-by: Mingzheng Xing <xingmingzheng@iscas.ac.cn>
483 lines
23 KiB
C
483 lines
23 KiB
C
/*************************************************************************/ /*!
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@File
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@Title RGX HWPerf and Debug Types and Defines Header
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@Copyright Copyright (c) Imagination Technologies Ltd. All Rights Reserved
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@Description Common data types definitions for hardware performance API
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@License Dual MIT/GPLv2
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The contents of this file are subject to the MIT license as set out below.
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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Alternatively, the contents of this file may be used under the terms of
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the GNU General Public License Version 2 ("GPL") in which case the provisions
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of GPL are applicable instead of those above.
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If you wish to allow use of your version of this file only under the terms of
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GPL, and not to allow others to use your version of this file under the terms
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of the MIT license, indicate your decision by deleting the provisions above
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and replace them with the notice and other provisions required by GPL as set
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out in the file called "GPL-COPYING" included in this distribution. If you do
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not delete the provisions above, a recipient may use your version of this file
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under the terms of either the MIT license or GPL.
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This License is also included in this distribution in the file called
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"MIT-COPYING".
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EXCEPT AS OTHERWISE STATED IN A NEGOTIATED AGREEMENT: (A) THE SOFTWARE IS
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PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
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BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
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PURPOSE AND NONINFRINGEMENT; AND (B) IN NO EVENT SHALL THE AUTHORS OR
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COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/ /**************************************************************************/
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#ifndef RGX_HWPERF_COMMON_H_
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#define RGX_HWPERF_COMMON_H_
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#if defined(__cplusplus)
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extern "C" {
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#endif
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/* These structures are used on both GPU and CPU and must be a size that is a
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* multiple of 64 bits, 8 bytes to allow the FW to write 8 byte quantities at
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* 8 byte aligned addresses. RGX_FW_STRUCT_*_ASSERT() is used to check this.
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*/
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/******************************************************************************
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* Includes and Defines
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*****************************************************************************/
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#include "img_types.h"
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#include "img_defs.h"
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#include "rgx_common_asserts.h"
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#include "pvrsrv_tlcommon.h"
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/******************************************************************************
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* Packet Event Type Enumerations
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*****************************************************************************/
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/*! Type used to encode the event that generated the packet.
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* NOTE: When this type is updated the corresponding hwperfbin2json tool
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* source needs to be updated as well. The RGX_HWPERF_EVENT_MASK_* macros will
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* also need updating when adding new types.
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*
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* @par
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* The event type values are incrementing integers for use as a shift ordinal
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* in the event filtering process at the point events are generated.
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* This scheme thus implies a limit of 63 event types.
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*/
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typedef IMG_UINT32 RGX_HWPERF_EVENT_TYPE;
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#define RGX_HWPERF_INVALID 0x00U /*!< Invalid. Reserved value. */
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/*! FW types 0x01..0x06 */
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#define RGX_HWPERF_FW_EVENT_RANGE_FIRST_TYPE 0x01U
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#define RGX_HWPERF_FW_BGSTART 0x01U /*!< Background task processing start */
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#define RGX_HWPERF_FW_BGEND 0x02U /*!< Background task end */
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#define RGX_HWPERF_FW_IRQSTART 0x03U /*!< IRQ task processing start */
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#define RGX_HWPERF_FW_IRQEND 0x04U /*!< IRQ task end */
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#define RGX_HWPERF_FW_DBGSTART 0x05U /*!< Debug event start */
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#define RGX_HWPERF_FW_DBGEND 0x06U /*!< Debug event end */
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#define RGX_HWPERF_FW_EVENT_RANGE_LAST_TYPE 0x06U
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/*! HW types 0x07..0x19 */
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#define RGX_HWPERF_HW_EVENT_RANGE0_FIRST_TYPE 0x07U
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#define RGX_HWPERF_HW_PMOOM_TAPAUSE 0x07U /*!< TA Pause at PM Out of Memory */
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#define RGX_HWPERF_HW_TAKICK 0x08U /*!< TA task started */
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#define RGX_HWPERF_HW_TAFINISHED 0x09U /*!< TA task finished */
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#define RGX_HWPERF_HW_3DTQKICK 0x0AU /*!< 3D TQ started */
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#define RGX_HWPERF_HW_3DKICK 0x0BU /*!< 3D task started */
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#define RGX_HWPERF_HW_3DFINISHED 0x0CU /*!< 3D task finished */
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#define RGX_HWPERF_HW_CDMKICK 0x0DU /*!< CDM task started */
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#define RGX_HWPERF_HW_CDMFINISHED 0x0EU /*!< CDM task finished */
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#define RGX_HWPERF_HW_TLAKICK 0x0FU /*!< TLA task started */
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#define RGX_HWPERF_HW_TLAFINISHED 0x10U /*!< TLS task finished */
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#define RGX_HWPERF_HW_3DSPMKICK 0x11U /*!< 3D SPM task started */
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#define RGX_HWPERF_HW_PERIODIC 0x12U /*!< Periodic event with updated HW counters */
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#define RGX_HWPERF_HW_RTUKICK 0x13U /*!< Reserved, future use */
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#define RGX_HWPERF_HW_RTUFINISHED 0x14U /*!< Reserved, future use */
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#define RGX_HWPERF_HW_SHGKICK 0x15U /*!< Reserved, future use */
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#define RGX_HWPERF_HW_SHGFINISHED 0x16U /*!< Reserved, future use */
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#define RGX_HWPERF_HW_3DTQFINISHED 0x17U /*!< 3D TQ finished */
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#define RGX_HWPERF_HW_3DSPMFINISHED 0x18U /*!< 3D SPM task finished */
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#define RGX_HWPERF_HW_PMOOM_TARESUME 0x19U /*!< TA Resume after PM Out of Memory */
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/*! HW_EVENT_RANGE0 used up. Use next empty range below to add new hardware events */
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#define RGX_HWPERF_HW_EVENT_RANGE0_LAST_TYPE 0x19U
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/*! other types 0x1A..0x1F */
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#define RGX_HWPERF_CLKS_CHG 0x1AU /*!< Clock speed change in GPU */
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#define RGX_HWPERF_GPU_STATE_CHG 0x1BU /*!< GPU work state change */
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/*! power types 0x20..0x27 */
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#define RGX_HWPERF_PWR_EST_RANGE_FIRST_TYPE 0x20U
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#define RGX_HWPERF_PWR_EST_REQUEST 0x20U /*!< Power estimate requested (via GPIO) */
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#define RGX_HWPERF_PWR_EST_READY 0x21U /*!< Power estimate inputs ready */
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#define RGX_HWPERF_PWR_EST_RESULT 0x22U /*!< Power estimate result calculated */
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#define RGX_HWPERF_PWR_EST_RANGE_LAST_TYPE 0x22U
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#define RGX_HWPERF_PWR_CHG 0x23U /*!< Power state change */
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/*! HW_EVENT_RANGE1 0x28..0x2F, for accommodating new hardware events */
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#define RGX_HWPERF_HW_EVENT_RANGE1_FIRST_TYPE 0x28U
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#define RGX_HWPERF_HW_TDMKICK 0x28U /*!< TDM task started */
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#define RGX_HWPERF_HW_TDMFINISHED 0x29U /*!< TDM task finished */
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#define RGX_HWPERF_HW_NULLKICK 0x2AU /*!< NULL event */
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#define RGX_HWPERF_HW_EVENT_RANGE1_LAST_TYPE 0x2AU
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/*! context switch types 0x30..0x31 */
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#define RGX_HWPERF_CSW_START 0x30U /*!< HW context store started */
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#define RGX_HWPERF_CSW_FINISHED 0x31U /*!< HW context store finished */
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/*! DVFS events */
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#define RGX_HWPERF_DVFS 0x32U /*!< Dynamic voltage/frequency scaling events */
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/*! firmware misc 0x38..0x39 */
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#define RGX_HWPERF_UFO 0x38U /*!< FW UFO Check / Update */
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#define RGX_HWPERF_FWACT 0x39U /*!< FW Activity notification */
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/*! last */
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#define RGX_HWPERF_LAST_TYPE 0x3BU
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/*! This enumeration must have a value that is a power of two as it is
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* used in masks and a filter bit field (currently 64 bits long).
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*/
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#define RGX_HWPERF_MAX_TYPE 0x40U
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static_assert(RGX_HWPERF_LAST_TYPE < RGX_HWPERF_MAX_TYPE, "Too many HWPerf event types");
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/*! Macro used to check if an event type ID is present in the known set of hardware type events */
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#define HWPERF_PACKET_IS_HW_TYPE(_etype) (((_etype) >= RGX_HWPERF_HW_EVENT_RANGE0_FIRST_TYPE && (_etype) <= RGX_HWPERF_HW_EVENT_RANGE0_LAST_TYPE) || \
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((_etype) >= RGX_HWPERF_HW_EVENT_RANGE1_FIRST_TYPE && (_etype) <= RGX_HWPERF_HW_EVENT_RANGE1_LAST_TYPE))
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/*! Macro used to check if an event type ID is present in the known set of firmware type events */
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#define HWPERF_PACKET_IS_FW_TYPE(_etype) \
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((_etype) >= RGX_HWPERF_FW_EVENT_RANGE_FIRST_TYPE && \
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(_etype) <= RGX_HWPERF_FW_EVENT_RANGE_LAST_TYPE)
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typedef enum {
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RGX_HWPERF_HOST_INVALID = 0x00, /*!< Invalid, do not use. */
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RGX_HWPERF_HOST_ENQ = 0x01, /*!< ``0x01`` Kernel driver has queued GPU work.
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See RGX_HWPERF_HOST_ENQ_DATA */
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RGX_HWPERF_HOST_UFO = 0x02, /*!< ``0x02`` UFO updated by the driver.
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See RGX_HWPERF_HOST_UFO_DATA */
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RGX_HWPERF_HOST_ALLOC = 0x03, /*!< ``0x03`` Resource allocated.
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See RGX_HWPERF_HOST_ALLOC_DATA */
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RGX_HWPERF_HOST_CLK_SYNC = 0x04, /*!< ``0x04`` GPU / Host clocks correlation data.
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See RGX_HWPERF_HOST_CLK_SYNC_DATA */
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RGX_HWPERF_HOST_FREE = 0x05, /*!< ``0x05`` Resource freed,
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See RGX_HWPERF_HOST_FREE_DATA */
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RGX_HWPERF_HOST_MODIFY = 0x06, /*!< ``0x06`` Resource modified / updated.
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See RGX_HWPERF_HOST_MODIFY_DATA */
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RGX_HWPERF_HOST_DEV_INFO = 0x07, /*!< ``0x07`` Device Health status.
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See RGX_HWPERF_HOST_DEV_INFO_DATA */
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RGX_HWPERF_HOST_INFO = 0x08, /*!< ``0x08`` Device memory usage information.
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See RGX_HWPERF_HOST_INFO_DATA */
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RGX_HWPERF_HOST_SYNC_FENCE_WAIT = 0x09, /*!< ``0x09`` Wait for sync event.
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See RGX_HWPERF_HOST_SYNC_FENCE_WAIT_DATA */
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RGX_HWPERF_HOST_SYNC_SW_TL_ADVANCE = 0x0A, /*!< ``0x0A`` Software timeline advanced.
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See RGX_HWPERF_HOST_SYNC_SW_TL_ADV_DATA */
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RGX_HWPERF_HOST_CLIENT_INFO = 0x0B, /*!< ``0x0B`` Additional client info.
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See RGX_HWPERF_HOST_CLIENT_INFO_DATA */
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/*! last */
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RGX_HWPERF_HOST_LAST_TYPE,
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/*! This enumeration must have a value that is a power of two as it is
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* used in masks and a filter bit field (currently 32 bits long).
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*/
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RGX_HWPERF_HOST_MAX_TYPE = 0x20
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} RGX_HWPERF_HOST_EVENT_TYPE;
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/*!< The event type values are incrementing integers for use as a shift ordinal
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* in the event filtering process at the point events are generated.
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* This scheme thus implies a limit of 31 event types.
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*/
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static_assert(RGX_HWPERF_HOST_LAST_TYPE < RGX_HWPERF_HOST_MAX_TYPE, "Too many HWPerf host event types");
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/******************************************************************************
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* Packet Header Format Version 2 Types
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*****************************************************************************/
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/*! Major version number of the protocol in operation
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*/
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#define RGX_HWPERF_V2_FORMAT 2
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/*! Signature ASCII pattern 'HWP2' found in the first word of a HWPerfV2 packet
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*/
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#define HWPERF_PACKET_V2_SIG 0x48575032
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/*! Signature ASCII pattern 'HWPA' found in the first word of a HWPerfV2a packet
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*/
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#define HWPERF_PACKET_V2A_SIG 0x48575041
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/*! Signature ASCII pattern 'HWPB' found in the first word of a HWPerfV2b packet
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*/
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#define HWPERF_PACKET_V2B_SIG 0x48575042
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/*! Signature ASCII pattern 'HWPC' found in the first word of a HWPerfV2c packet
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*/
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#define HWPERF_PACKET_V2C_SIG 0x48575043
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#define HWPERF_PACKET_ISVALID(_val) (((_val) == HWPERF_PACKET_V2_SIG) || ((_val) == HWPERF_PACKET_V2A_SIG) || ((_val) == HWPERF_PACKET_V2B_SIG) || ((_val) == HWPERF_PACKET_V2C_SIG))
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/*!< Checks that the packet signature is one of the supported versions */
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/*! Type defines the HWPerf packet header common to all events. */
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typedef struct
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{
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IMG_UINT32 ui32Sig; /*!< Always the value HWPERF_PACKET_SIG */
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IMG_UINT32 ui32Size; /*!< Overall packet size in bytes */
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IMG_UINT32 eTypeId; /*!< Event type information field */
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IMG_UINT32 ui32Ordinal; /*!< Sequential number of the packet */
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IMG_UINT64 ui64Timestamp; /*!< Event timestamp */
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} RGX_HWPERF_V2_PACKET_HDR, *RGX_PHWPERF_V2_PACKET_HDR;
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RGX_FW_STRUCT_OFFSET_ASSERT(RGX_HWPERF_V2_PACKET_HDR, ui64Timestamp);
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RGX_FW_STRUCT_SIZE_ASSERT(RGX_HWPERF_V2_PACKET_HDR);
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/*! Mask for use with the IMG_UINT32 ui32Size header field */
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#define RGX_HWPERF_SIZE_MASK 0xFFFFU
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/*! This macro defines an upper limit to which the size of the largest variable
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* length HWPerf packet must fall within, currently 3KB. This constant may be
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* used to allocate a buffer to hold one packet.
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* This upper limit is policed by packet producing code.
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*/
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#define RGX_HWPERF_MAX_PACKET_SIZE 0xC00U
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/*! Defines an upper limit to the size of a variable length packet payload.
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*/
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#define RGX_HWPERF_MAX_PAYLOAD_SIZE ((IMG_UINT32)(RGX_HWPERF_MAX_PACKET_SIZE-\
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sizeof(RGX_HWPERF_V2_PACKET_HDR)))
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/*! Macro which takes a structure name and provides the packet size for
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* a fixed size payload packet, rounded up to 8 bytes to align packets
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* for 64 bit architectures. */
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#define RGX_HWPERF_MAKE_SIZE_FIXED(_struct) ((IMG_UINT32)(RGX_HWPERF_SIZE_MASK&(sizeof(RGX_HWPERF_V2_PACKET_HDR)+PVR_ALIGN(sizeof(_struct), PVRSRVTL_PACKET_ALIGNMENT))))
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/*! Macro which takes the number of bytes written in the data payload of a
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* packet for a variable size payload packet, rounded up to 8 bytes to
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* align packets for 64 bit architectures. */
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#define RGX_HWPERF_MAKE_SIZE_VARIABLE(_size) ((IMG_UINT32)(RGX_HWPERF_SIZE_MASK&((IMG_UINT32)sizeof(RGX_HWPERF_V2_PACKET_HDR)+PVR_ALIGN((_size), PVRSRVTL_PACKET_ALIGNMENT))))
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/*! Macro to obtain the size of the packet */
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#define RGX_HWPERF_GET_SIZE(_packet_addr) ((IMG_UINT16)(((_packet_addr)->ui32Size) & RGX_HWPERF_SIZE_MASK))
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/*! Macro to obtain the size of the packet data */
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#define RGX_HWPERF_GET_DATA_SIZE(_packet_addr) (RGX_HWPERF_GET_SIZE(_packet_addr) - sizeof(RGX_HWPERF_V2_PACKET_HDR))
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/*! Masks for use with the IMG_UINT32 eTypeId header field */
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#define RGX_HWPERF_TYPEID_MASK 0x0007FFFFU
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#define RGX_HWPERF_TYPEID_EVENT_MASK 0x00007FFFU
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#define RGX_HWPERF_TYPEID_THREAD_MASK 0x00008000U
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#define RGX_HWPERF_TYPEID_STREAM_MASK 0x00070000U
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#define RGX_HWPERF_TYPEID_META_DMA_MASK 0x00080000U
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#define RGX_HWPERF_TYPEID_M_CORE_MASK 0x00100000U
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#define RGX_HWPERF_TYPEID_OSID_MASK 0x07000000U
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/*! Meta thread macros for encoding the ID into the type field of a packet */
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#define RGX_HWPERF_META_THREAD_SHIFT 15U
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#define RGX_HWPERF_META_THREAD_ID0 0x0U /*!< Meta Thread 0 ID */
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#define RGX_HWPERF_META_THREAD_ID1 0x1U /*!< Meta Thread 1 ID */
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/*! Obsolete, kept for source compatibility */
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#define RGX_HWPERF_META_THREAD_MASK 0x1U
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/*! Stream ID macros for encoding the ID into the type field of a packet */
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#define RGX_HWPERF_STREAM_SHIFT 16U
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/*! Meta DMA macro for encoding how the packet was generated into the type field of a packet */
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#define RGX_HWPERF_META_DMA_SHIFT 19U
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/*! Bit-shift macro used for encoding multi-core data into the type field of a packet */
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#define RGX_HWPERF_M_CORE_SHIFT 20U
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/*! OSID bit-shift macro used for encoding OSID into type field of a packet */
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#define RGX_HWPERF_OSID_SHIFT 24U
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typedef enum {
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RGX_HWPERF_STREAM_ID0_FW, /*!< Events from the Firmware/GPU */
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RGX_HWPERF_STREAM_ID1_HOST, /*!< Events from the Server host driver component */
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RGX_HWPERF_STREAM_ID2_CLIENT, /*!< Events from the Client host driver component */
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RGX_HWPERF_STREAM_ID_LAST,
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} RGX_HWPERF_STREAM_ID;
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/* Checks if all stream IDs can fit under RGX_HWPERF_TYPEID_STREAM_MASK. */
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static_assert(((IMG_UINT32)RGX_HWPERF_STREAM_ID_LAST - 1U) < (RGX_HWPERF_TYPEID_STREAM_MASK >> RGX_HWPERF_STREAM_SHIFT),
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"Too many HWPerf stream IDs.");
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/*! Compile-time value used to seed the Multi-Core (MC) bit in the typeID field.
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* Only set by RGX_FIRMWARE builds.
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*/
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#if defined(RGX_FIRMWARE)
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# if defined(RGX_FEATURE_GPU_MULTICORE_SUPPORT)
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#define RGX_HWPERF_M_CORE_VALUE 1U /*!< 1 => Multi-core supported */
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# else
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#define RGX_HWPERF_M_CORE_VALUE 0U /*!< 0 => Multi-core not supported */
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# endif
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#else
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#define RGX_HWPERF_M_CORE_VALUE 0U /*!< 0 => Multi-core not supported */
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#endif
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/*! Macros used to set the packet type and encode meta thread ID (0|1),
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* HWPerf stream ID, multi-core capability and OSID within the typeID */
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#define RGX_HWPERF_MAKE_TYPEID(_stream, _type, _thread, _metadma, _osid)\
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((IMG_UINT32) ((RGX_HWPERF_TYPEID_STREAM_MASK&((IMG_UINT32)(_stream) << RGX_HWPERF_STREAM_SHIFT)) | \
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(RGX_HWPERF_TYPEID_THREAD_MASK & ((IMG_UINT32)(_thread) << RGX_HWPERF_META_THREAD_SHIFT)) | \
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(RGX_HWPERF_TYPEID_EVENT_MASK & (IMG_UINT32)(_type)) | \
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(RGX_HWPERF_TYPEID_META_DMA_MASK & ((IMG_UINT32)(_metadma) << RGX_HWPERF_META_DMA_SHIFT)) | \
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(RGX_HWPERF_TYPEID_OSID_MASK & ((IMG_UINT32)(_osid) << RGX_HWPERF_OSID_SHIFT)) | \
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(RGX_HWPERF_TYPEID_M_CORE_MASK & ((IMG_UINT32)(RGX_HWPERF_M_CORE_VALUE) << RGX_HWPERF_M_CORE_SHIFT))))
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/*! Obtains the event type that generated the packet */
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#define RGX_HWPERF_GET_TYPE(_packet_addr) (((_packet_addr)->eTypeId) & RGX_HWPERF_TYPEID_EVENT_MASK)
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/*! Obtains the META Thread number that generated the packet */
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#define RGX_HWPERF_GET_THREAD_ID(_packet_addr) (((((_packet_addr)->eTypeId) & RGX_HWPERF_TYPEID_THREAD_MASK) >> RGX_HWPERF_META_THREAD_SHIFT))
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/*! Determines if the packet generated contains multi-core data */
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#define RGX_HWPERF_GET_M_CORE(_packet_addr) (((_packet_addr)->eTypeId & RGX_HWPERF_TYPEID_M_CORE_MASK) >> RGX_HWPERF_M_CORE_SHIFT)
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/*! Obtains the guest OSID which resulted in packet generation */
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#define RGX_HWPERF_GET_OSID(_packet_addr) (((_packet_addr)->eTypeId & RGX_HWPERF_TYPEID_OSID_MASK) >> RGX_HWPERF_OSID_SHIFT)
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/*! Obtain stream id */
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#define RGX_HWPERF_GET_STREAM_ID(_packet_addr) (((((_packet_addr)->eTypeId) & RGX_HWPERF_TYPEID_STREAM_MASK) >> RGX_HWPERF_STREAM_SHIFT))
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/*! Obtain information about how the packet was generated, which might affect payload total size */
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#define RGX_HWPERF_GET_META_DMA_INFO(_packet_addr) (((((_packet_addr)->eTypeId) & RGX_HWPERF_TYPEID_META_DMA_MASK) >> RGX_HWPERF_META_DMA_SHIFT))
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/*! Obtains a typed pointer to a packet given a buffer address */
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#define RGX_HWPERF_GET_PACKET(_buffer_addr) ((RGX_HWPERF_V2_PACKET_HDR *)(void *) (_buffer_addr))
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/*! Obtains a typed pointer to a data structure given a packet address */
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#define RGX_HWPERF_GET_PACKET_DATA_BYTES(_packet_addr) (IMG_OFFSET_ADDR((_packet_addr), sizeof(RGX_HWPERF_V2_PACKET_HDR)))
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/*! Obtains a typed pointer to the next packet given a packet address */
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#define RGX_HWPERF_GET_NEXT_PACKET(_packet_addr) ((RGX_HWPERF_V2_PACKET_HDR *) (IMG_OFFSET_ADDR((_packet_addr), RGX_HWPERF_SIZE_MASK&((_packet_addr)->ui32Size))))
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/*! Obtains a typed pointer to a packet header given the packet data address */
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#define RGX_HWPERF_GET_PACKET_HEADER(_packet_addr) ((RGX_HWPERF_V2_PACKET_HDR *) (IMG_OFFSET_ADDR((_packet_addr), -(IMG_INT32)sizeof(RGX_HWPERF_V2_PACKET_HDR))))
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/******************************************************************************
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* Other Common Defines
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*****************************************************************************/
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/*! This macro is not a real array size, but indicates the array has a variable
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* length only known at run-time but always contains at least 1 element. The
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* final size of the array is deduced from the size field of a packet header.
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*/
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#define RGX_HWPERF_ONE_OR_MORE_ELEMENTS 1U
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/*! This macro is not a real array size, but indicates the array is optional
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* and if present has a variable length only known at run-time. The final
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* size of the array is deduced from the size field of a packet header. */
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#define RGX_HWPERF_ZERO_OR_MORE_ELEMENTS 1U
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/*! Masks for use with the IMG_UINT32 ui32BlkInfo field */
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#define RGX_HWPERF_BLKINFO_BLKCOUNT_MASK 0xFFFF0000U
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#define RGX_HWPERF_BLKINFO_BLKOFFSET_MASK 0x0000FFFFU
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/*! Shift for the NumBlocks and counter block offset field in ui32BlkInfo */
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#define RGX_HWPERF_BLKINFO_BLKCOUNT_SHIFT 16U
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#define RGX_HWPERF_BLKINFO_BLKOFFSET_SHIFT 0U
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/*! Macro used to set the block info word as a combination of two 16-bit integers */
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#define RGX_HWPERF_MAKE_BLKINFO(_numblks, _blkoffset) ((IMG_UINT32) ((RGX_HWPERF_BLKINFO_BLKCOUNT_MASK&((_numblks) << RGX_HWPERF_BLKINFO_BLKCOUNT_SHIFT)) | (RGX_HWPERF_BLKINFO_BLKOFFSET_MASK&((_blkoffset) << RGX_HWPERF_BLKINFO_BLKOFFSET_SHIFT))))
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/*! Macro used to obtain the number of counter blocks present in the packet */
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#define RGX_HWPERF_GET_BLKCOUNT(_blkinfo) (((_blkinfo) & RGX_HWPERF_BLKINFO_BLKCOUNT_MASK) >> RGX_HWPERF_BLKINFO_BLKCOUNT_SHIFT)
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/*! Obtains the offset of the counter block stream in the packet */
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#define RGX_HWPERF_GET_BLKOFFSET(_blkinfo) (((_blkinfo) & RGX_HWPERF_BLKINFO_BLKOFFSET_MASK) >> RGX_HWPERF_BLKINFO_BLKOFFSET_SHIFT)
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/*! This macro gets the number of blocks depending on the packet version */
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#define RGX_HWPERF_GET_NUMBLKS(_sig, _packet_data, _numblocks) \
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do { \
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if (HWPERF_PACKET_V2B_SIG == (_sig) || HWPERF_PACKET_V2C_SIG == (_sig)) \
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{ \
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(_numblocks) = RGX_HWPERF_GET_BLKCOUNT((_packet_data)->ui32BlkInfo);\
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} \
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else \
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{ \
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IMG_UINT32 ui32VersionOffset = (((_sig) == HWPERF_PACKET_V2_SIG) ? 1 : 3);\
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(_numblocks) = *(IMG_UINT16 *)(IMG_OFFSET_ADDR(&(_packet_data)->ui32WorkTarget, ui32VersionOffset)); \
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} \
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} while (0)
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/*! This macro gets the counter stream pointer depending on the packet version */
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#define RGX_HWPERF_GET_CNTSTRM(_sig, _hw_packet_data, _cntstream_ptr) \
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{ \
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if (HWPERF_PACKET_V2B_SIG == (_sig) || HWPERF_PACKET_V2C_SIG == (_sig)) \
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{ \
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(_cntstream_ptr) = (IMG_UINT32 *)(IMG_OFFSET_ADDR((_hw_packet_data), RGX_HWPERF_GET_BLKOFFSET((_hw_packet_data)->ui32BlkInfo))); \
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} \
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else \
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{ \
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IMG_UINT32 ui32BlkStreamOffsetInWords = (((_sig) == HWPERF_PACKET_V2_SIG) ? 6 : 8); \
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(_cntstream_ptr) = (IMG_UINT32 *)(IMG_OFFSET_ADDR_DW((_hw_packet_data), ui32BlkStreamOffsetInWords)); \
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} \
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}
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/*! Masks for use with the IMG_UINT32 ui32KickInfo field */
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#define RGX_HWPERF_KICKINFO_KICKID_MASK 0x000000FFU
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/*! Shift for the Kick ID field in ui32KickInfo */
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#define RGX_HWPERF_KICKINFO_KICKID_SHIFT 0U
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/*! Macro used to set the kick info field. */
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#define RGX_HWPERF_MAKE_KICKINFO(_kickid) ((IMG_UINT32) (RGX_HWPERF_KICKINFO_KICKID_MASK&((_kickid) << RGX_HWPERF_KICKINFO_KICKID_SHIFT)))
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/*! Macro used to obtain the Kick ID if present in the packet */
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#define RGX_HWPERF_GET_KICKID(_kickinfo) (((_kickinfo) & RGX_HWPERF_KICKINFO_KICKID_MASK) >> RGX_HWPERF_KICKINFO_KICKID_SHIFT)
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/*! Masks for use with the RGX_HWPERF_UFO_EV eEvType field */
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#define RGX_HWPERF_UFO_STREAMSIZE_MASK 0xFFFF0000U
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#define RGX_HWPERF_UFO_STREAMOFFSET_MASK 0x0000FFFFU
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/*! Shift for the UFO count and data stream fields */
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#define RGX_HWPERF_UFO_STREAMSIZE_SHIFT 16U
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#define RGX_HWPERF_UFO_STREAMOFFSET_SHIFT 0U
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/*! Macro used to set UFO stream info word as a combination of two 16-bit integers */
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#define RGX_HWPERF_MAKE_UFOPKTINFO(_ssize, _soff) \
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((IMG_UINT32) ((RGX_HWPERF_UFO_STREAMSIZE_MASK&((_ssize) << RGX_HWPERF_UFO_STREAMSIZE_SHIFT)) | \
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(RGX_HWPERF_UFO_STREAMOFFSET_MASK&((_soff) << RGX_HWPERF_UFO_STREAMOFFSET_SHIFT))))
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/*! Macro used to obtain UFO count*/
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#define RGX_HWPERF_GET_UFO_STREAMSIZE(_streaminfo) \
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(((_streaminfo) & RGX_HWPERF_UFO_STREAMSIZE_MASK) >> RGX_HWPERF_UFO_STREAMSIZE_SHIFT)
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/*! Obtains the offset of the UFO stream in the packet */
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#define RGX_HWPERF_GET_UFO_STREAMOFFSET(_streaminfo) \
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(((_streaminfo) & RGX_HWPERF_UFO_STREAMOFFSET_MASK) >> RGX_HWPERF_UFO_STREAMOFFSET_SHIFT)
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#if defined(__cplusplus)
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}
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#endif
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#endif /* RGX_HWPERF_COMMON_H_ */
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/******************************************************************************
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End of file
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******************************************************************************/
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