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feat: update gpu to Linux_SDK_V1.2.1

Browse Source 
This version update involves a lot of content, so the previous version
has been deleted and the new version has been re-merged into the kernel.

The configuration file for the GPU driver originates from a previous
version.

Signed-off-by: Mingzheng Xing <xingmingzheng@iscas.ac.cn>
This commit is contained in:
Mingzheng Xing
2023-08-30 21:19:50 +08:00
committed by Han Gao
parent 807db9d981
commit f72e7cd077
250 changed files with 10635 additions and 7697 deletions
Download Patch File Download Diff File Expand all files Collapse all files

21
drivers/gpu/drm/img-rogue/allocmem.c
View File

@@ -54,19 +54,6 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#endif
#include "osfunc.h"
/*
* DEBUG_MEMSTATS_ALLOC_RECORD_VALUES needs to be different from
* DEBUG_MEMSTATS_VALUES defined in process_stats.h.
* The reason for this is that the file and line where the allocation happens
* are tracked from the OSAllocMem params. If DEBUG_MEMSTATS_VALUES were to be
* used, all OSAllocMem allocation statistics would point to allocmem.c, which
* is not expected behaviour.
*/
#if defined(PVRSRV_DEBUG_LINUX_MEMORY_STATS_ON)
#define DEBUG_MEMSTATS_ALLOC_RECORD_VALUES ,pvAllocFromFile, ui32AllocFromLine
#else
#define DEBUG_MEMSTATS_ALLOC_RECORD_VALUES
#endif
/*
* When memory statistics are disabled, memory records are used instead.
@@ -167,7 +154,7 @@ static inline void _pvr_alloc_stats_add(void *pvAddr, IMG_UINT32 ui32Size DEBUG_
ksize(pvAddr),
NULL,
OSGetCurrentClientProcessIDKM()
DEBUG_MEMSTATS_ALLOC_RECORD_VALUES);
DEBUG_MEMSTATS_ARGS);
#else
{
/* Store the PID in the final additional 4 bytes allocated */
@@ -189,7 +176,7 @@ static inline void _pvr_alloc_stats_add(void *pvAddr, IMG_UINT32 ui32Size DEBUG_
((ui32Size + PAGE_SIZE-1) & ~(PAGE_SIZE-1)),
NULL,
OSGetCurrentClientProcessIDKM()
DEBUG_MEMSTATS_ALLOC_RECORD_VALUES);
DEBUG_MEMSTATS_ARGS);
#else
PVRSRVStatsIncrMemAllocStatAndTrack(PVRSRV_MEM_ALLOC_TYPE_VMALLOC,
((ui32Size + PAGE_SIZE-1) & ~(PAGE_SIZE-1)),
@@ -256,7 +243,7 @@ void *(OSAllocMem)(IMG_UINT32 ui32Size DEBUG_MEMSTATS_PARAMS)
if (pvRet != NULL)
{
_pvr_alloc_stats_add(pvRet, ui32Size DEBUG_MEMSTATS_ALLOC_RECORD_VALUES);
_pvr_alloc_stats_add(pvRet, ui32Size DEBUG_MEMSTATS_ARGS);
}
return pvRet;
@@ -286,7 +273,7 @@ void *(OSAllocZMem)(IMG_UINT32 ui32Size DEBUG_MEMSTATS_PARAMS)
if (pvRet != NULL)
{
_pvr_alloc_stats_add(pvRet, ui32Size DEBUG_MEMSTATS_ALLOC_RECORD_VALUES);
_pvr_alloc_stats_add(pvRet, ui32Size DEBUG_MEMSTATS_ARGS);
}
return pvRet;

103
drivers/gpu/drm/img-rogue/allocmem.h
View File

@@ -51,7 +51,47 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
extern "C" {
#endif
#if !defined(PVRSRV_DEBUG_LINUX_MEMORY_STATS) || !defined(DEBUG) || !defined(PVRSRV_ENABLE_PROCESS_STATS) || !defined(PVRSRV_ENABLE_MEMORY_STATS) || defined(DOXYGEN)
/*
* PVRSRV_ENABLE_PROCESS_STATS enables process statistics regarding events,
* resources and memory across all processes
* PVRSRV_ENABLE_MEMORY_STATS enables recording of Linux kernel memory
* allocations, provided that PVRSRV_ENABLE_PROCESS_STATS is enabled
* - Output can be found in:
* /(sys/kernel/debug|proc)/pvr/proc_stats/[live|retired]_pids_stats/mem_area
* PVRSRV_DEBUG_LINUX_MEMORY_STATS provides more details about memory
* statistics in conjunction with PVRSRV_ENABLE_MEMORY_STATS
* PVRSRV_DEBUG_LINUX_MEMORY_STATS_ON is defined to encompass both memory
* allocation statistics functionalities described above in a single macro
*/
#if defined(PVRSRV_ENABLE_PROCESS_STATS) && defined(PVRSRV_ENABLE_MEMORY_STATS) && defined(PVRSRV_DEBUG_LINUX_MEMORY_STATS) && defined(DEBUG)
#define PVRSRV_DEBUG_LINUX_MEMORY_STATS_ON
#endif
/*
* When using detailed memory allocation statistics, the line number and
* file name where the allocation happened are also provided.
* When this feature is not used, these parameters are not needed.
*/
#if defined(PVRSRV_DEBUG_LINUX_MEMORY_STATS_ON)
#define DEBUG_MEMSTATS_PARAMS ,void *pvAllocFromFile, IMG_UINT32 ui32AllocFromLine
#define DEBUG_MEMSTATS_ARGS ,pvAllocFromFile, ui32AllocFromLine
#define DEBUG_MEMSTATS_UNREF (void)pvAllocFromFile; (void)ui32AllocFromLine;
#define DEBUG_MEMSTATS_VALUES ,__FILE__, __LINE__
#else
#define DEBUG_MEMSTATS_PARAMS /*!<
* Used for PVRSRV_DEBUG_LINUX_MEMORY_STATS_ON
* build option. */
#define DEBUG_MEMSTATS_ARGS /*!<
* Used for PVRSRV_DEBUG_LINUX_MEMORY_STATS_ON
* build option. */
#define DEBUG_MEMSTATS_UNREF /*!<
* Used for PVRSRV_DEBUG_LINUX_MEMORY_STATS_ON
* build option. */
#define DEBUG_MEMSTATS_VALUES /*!<
* Used for PVRSRV_DEBUG_LINUX_MEMORY_STATS_ON
* build option. */
#endif
/**************************************************************************/ /*!
@Function OSAllocMem
@@ -62,8 +102,13 @@ extern "C" {
@Return Pointer to allocated memory on success.
Otherwise NULL.
*/ /**************************************************************************/
#if defined(DOXYGEN)
void *OSAllocMem(IMG_UINT32 ui32Size);
#define OSAllocMem(_size) (OSAllocMem)((_size))
#else
void *OSAllocMem(IMG_UINT32 ui32Size DEBUG_MEMSTATS_PARAMS);
#define OSAllocMem(_size) (OSAllocMem)((_size) DEBUG_MEMSTATS_VALUES)
#endif
/**************************************************************************/ /*!
@Function OSAllocZMem
@Description Allocates CPU memory and initializes the contents to zero.
@@ -73,27 +118,25 @@ void *OSAllocMem(IMG_UINT32 ui32Size);
@Return Pointer to allocated memory on success.
Otherwise NULL.
*/ /**************************************************************************/
#if defined(DOXYGEN)
void *OSAllocZMem(IMG_UINT32 ui32Size);
#define OSAllocZMem(_size) (OSAllocZMem)((_size))
#else
void *OSAllocMem(IMG_UINT32 ui32Size, void *pvAllocFromFile, IMG_UINT32 ui32AllocFromLine);
void *OSAllocZMem(IMG_UINT32 ui32Size, void *pvAllocFromFile, IMG_UINT32 ui32AllocFromLine);
#define OSAllocMem(_size) (OSAllocMem)((_size), (__FILE__), (__LINE__))
#define OSAllocZMem(_size) (OSAllocZMem)((_size), (__FILE__), (__LINE__))
void *OSAllocZMem(IMG_UINT32 ui32Size DEBUG_MEMSTATS_PARAMS);
#define OSAllocZMem(_size) (OSAllocZMem)((_size) DEBUG_MEMSTATS_VALUES)
#endif
/**************************************************************************/ /*!
@Function OSAllocMemNoStats
@Description Allocates CPU memory. Contents are uninitialized.
If passed a size of zero, function should not assert,
but just return a NULL pointer.
The allocated memory is not accounted for by process stats.
Process stats are an optional feature (enabled only when
PVRSRV_ENABLE_PROCESS_STATS is defined) which track the amount
of memory allocated to help in debugging. Where this is not
required, OSAllocMem() and OSAllocMemNoStats() equate to
the same operation.
If passed a size of zero, function should not assert,
but just return a NULL pointer.
The allocated memory is not accounted for by process stats.
Process stats are an optional feature (enabled only when
PVRSRV_ENABLE_PROCESS_STATS is defined) which track the amount
of memory allocated to help in debugging. Where this is not
required, OSAllocMem() and OSAllocMemNoStats() equate to
the same operation.
@Input ui32Size Size of required allocation (in bytes)
@Return Pointer to allocated memory on success.
Otherwise NULL.
@@ -103,14 +146,14 @@ void *OSAllocMemNoStats(IMG_UINT32 ui32Size);
/**************************************************************************/ /*!
@Function OSAllocZMemNoStats
@Description Allocates CPU memory and initializes the contents to zero.
If passed a size of zero, function should not assert,
but just return a NULL pointer.
The allocated memory is not accounted for by process stats.
Process stats are an optional feature (enabled only when
PVRSRV_ENABLE_PROCESS_STATS is defined) which track the amount
of memory allocated to help in debugging. Where this is not
required, OSAllocZMem() and OSAllocZMemNoStats() equate to
the same operation.
If passed a size of zero, function should not assert,
but just return a NULL pointer.
The allocated memory is not accounted for by process stats.
Process stats are an optional feature (enabled only when
PVRSRV_ENABLE_PROCESS_STATS is defined) which track the amount
of memory allocated to help in debugging. Where this is not
required, OSAllocZMem() and OSAllocZMemNoStats() equate to
the same operation.
@Input ui32Size Size of required allocation (in bytes)
@Return Pointer to allocated memory on success.
Otherwise NULL.
@@ -128,12 +171,12 @@ void OSFreeMem(void *pvCpuVAddr);
/**************************************************************************/ /*!
@Function OSFreeMemNoStats
@Description Frees previously allocated CPU memory.
The freed memory does not update the figures in process stats.
Process stats are an optional feature (enabled only when
PVRSRV_ENABLE_PROCESS_STATS is defined) which track the amount
of memory allocated to help in debugging. Where this is not
required, OSFreeMem() and OSFreeMemNoStats() equate to the
same operation.
The freed memory does not update the figures in process stats.
Process stats are an optional feature (enabled only when
PVRSRV_ENABLE_PROCESS_STATS is defined) which track the amount
of memory allocated to help in debugging. Where this is not
required, OSFreeMem() and OSFreeMemNoStats() equate to the
same operation.
@Input pvCpuVAddr Pointer to the memory to be freed.
@Return None.
*/ /**************************************************************************/

1310
drivers/gpu/drm/img-rogue/cache_km.c
View File

File diff suppressed because it is too large Load Diff

21
drivers/gpu/drm/img-rogue/cache_km.h
View File

@@ -132,21 +132,7 @@ PVRSRV_ERROR CacheOpQueue(CONNECTION_DATA *psConnection,
IMG_DEVMEM_OFFSET_T *puiOffset,
IMG_DEVMEM_SIZE_T *puiSize,
PVRSRV_CACHE_OP *puiCacheOp,
IMG_UINT32 ui32OpTimeline,
IMG_UINT32 uiCurrentFenceSeqNum,
IMG_UINT32 *puiNextFenceSeqNum);
/*
* CacheOpFence()
*
* This is used for fencing for any client in-flight cache maintenance
* operations that might have been deferred by the use of CacheOpQueue().
* This should be called before any subsequent HW device kicks to ensure
* device memory is coherent with the HW before the kick.
*/
PVRSRV_ERROR CacheOpFence(PPVRSRV_DEVICE_NODE psDevNode,
RGXFWIF_DM eOpType,
IMG_UINT32 ui32OpSeqNum);
IMG_UINT32 ui32OpTimeline);
/*
* CacheOpLog()
@@ -158,9 +144,8 @@ PVRSRV_ERROR CacheOpLog(PMR *psPMR,
IMG_UINT64 uiAddress,
IMG_DEVMEM_OFFSET_T uiOffset,
IMG_DEVMEM_SIZE_T uiSize,
IMG_UINT64 ui64QueuedTimeMs,
IMG_UINT64 ui64ExecuteTimeMs,
IMG_UINT32 ui32NumRBF,
IMG_UINT64 ui64StartTime,
IMG_UINT64 ui64EndTime,
PVRSRV_CACHE_OP uiCacheOp);
#endif /* CACHE_KM_H */

9
drivers/gpu/drm/img-rogue/client_cache_bridge.h
View File

@@ -61,9 +61,7 @@ IMG_INTERNAL PVRSRV_ERROR BridgeCacheOpQueue(IMG_HANDLE hBridge,
IMG_DEVMEM_OFFSET_T * puiOffset,
IMG_DEVMEM_SIZE_T * puiSize,
PVRSRV_CACHE_OP * piuCacheOp,
IMG_UINT32 ui32OpTimeline,
IMG_UINT32 ui32CurrentFenceSeqNum,
IMG_UINT32 * pui32NextFenceSeqNum);
IMG_UINT32 ui32OpTimeline);
IMG_INTERNAL PVRSRV_ERROR BridgeCacheOpExec(IMG_HANDLE hBridge,
IMG_HANDLE hPMR,
@@ -76,8 +74,7 @@ IMG_INTERNAL PVRSRV_ERROR BridgeCacheOpLog(IMG_HANDLE hBridge,
IMG_UINT64 ui64Address,
IMG_DEVMEM_OFFSET_T uiOffset,
IMG_DEVMEM_SIZE_T uiSize,
IMG_INT64 i64QueuedTimeUs,
IMG_INT64 i64ExecuteTimeUs,
IMG_INT32 i32NumRBF, PVRSRV_CACHE_OP iuCacheOp);
IMG_INT64 i64StartTime,
IMG_INT64 i64EndTime, PVRSRV_CACHE_OP iuCacheOp);
#endif /* CLIENT_CACHE_BRIDGE_H */

18
drivers/gpu/drm/img-rogue/client_cache_direct_bridge.c
View File

@@ -58,9 +58,7 @@ IMG_INTERNAL PVRSRV_ERROR BridgeCacheOpQueue(IMG_HANDLE hBridge,
IMG_DEVMEM_OFFSET_T * puiOffset,
IMG_DEVMEM_SIZE_T * puiSize,
PVRSRV_CACHE_OP * piuCacheOp,
IMG_UINT32 ui32OpTimeline,
IMG_UINT32 ui32CurrentFenceSeqNum,
IMG_UINT32 * pui32NextFenceSeqNum)
IMG_UINT32 ui32OpTimeline)
{
PVRSRV_ERROR eError;
PMR **psPMRInt;
@@ -70,11 +68,7 @@ IMG_INTERNAL PVRSRV_ERROR BridgeCacheOpQueue(IMG_HANDLE hBridge,
eError =
CacheOpQueue(NULL, (PVRSRV_DEVICE_NODE *) ((void *)hBridge),
ui32NumCacheOps,
psPMRInt,
pui64Address,
puiOffset,
puiSize,
piuCacheOp, ui32OpTimeline, ui32CurrentFenceSeqNum, pui32NextFenceSeqNum);
psPMRInt, pui64Address, puiOffset, puiSize, piuCacheOp, ui32OpTimeline);
return eError;
}
@@ -101,9 +95,8 @@ IMG_INTERNAL PVRSRV_ERROR BridgeCacheOpLog(IMG_HANDLE hBridge,
IMG_UINT64 ui64Address,
IMG_DEVMEM_OFFSET_T uiOffset,
IMG_DEVMEM_SIZE_T uiSize,
IMG_INT64 i64QueuedTimeUs,
IMG_INT64 i64ExecuteTimeUs,
IMG_INT32 i32NumRBF, PVRSRV_CACHE_OP iuCacheOp)
IMG_INT64 i64StartTime,
IMG_INT64 i64EndTime, PVRSRV_CACHE_OP iuCacheOp)
{
PVRSRV_ERROR eError;
PMR *psPMRInt;
@@ -113,8 +106,7 @@ IMG_INTERNAL PVRSRV_ERROR BridgeCacheOpLog(IMG_HANDLE hBridge,
eError =
CacheOpLog(psPMRInt,
ui64Address,
uiOffset, uiSize, i64QueuedTimeUs, i64ExecuteTimeUs, i32NumRBF, iuCacheOp);
ui64Address, uiOffset, uiSize, i64StartTime, i64EndTime, iuCacheOp);
return eError;
}

11
drivers/gpu/drm/img-rogue/client_mm_bridge.h
View File

@@ -251,4 +251,15 @@ IMG_INTERNAL PVRSRV_ERROR BridgeDevmemGetFaultAddress(IMG_HANDLE hBridge,
IMG_INTERNAL PVRSRV_ERROR BridgePVRSRVUpdateOOMStats(IMG_HANDLE hBridge,
IMG_UINT32 ui32ui32StatType, IMG_PID ui32pid);
IMG_INTERNAL PVRSRV_ERROR BridgePhysHeapGetMemInfoPkd(IMG_HANDLE hBridge,
IMG_UINT32 ui32PhysHeapCount,
PVRSRV_PHYS_HEAP * peaPhysHeapID,
PHYS_HEAP_MEM_STATS_PKD *
psapPhysHeapMemStats);
IMG_INTERNAL PVRSRV_ERROR BridgeGetHeapPhysMemUsagePkd(IMG_HANDLE hBridge,
IMG_UINT32 ui32PhysHeapCount,
PHYS_HEAP_MEM_STATS_PKD *
psapPhysHeapMemStats);
#endif /* CLIENT_MM_BRIDGE_H */

29
drivers/gpu/drm/img-rogue/client_mm_direct_bridge.c
View File

@@ -773,3 +773,32 @@ IMG_INTERNAL PVRSRV_ERROR BridgePVRSRVUpdateOOMStats(IMG_HANDLE hBridge,
return PVRSRV_ERROR_NOT_IMPLEMENTED;
#endif
}
IMG_INTERNAL PVRSRV_ERROR BridgePhysHeapGetMemInfoPkd(IMG_HANDLE hBridge,
IMG_UINT32 ui32PhysHeapCount,
PVRSRV_PHYS_HEAP * peaPhysHeapID,
PHYS_HEAP_MEM_STATS_PKD *
psapPhysHeapMemStats)
{
PVRSRV_ERROR eError;
eError =
PVRSRVPhysHeapGetMemInfoPkdKM(NULL, (PVRSRV_DEVICE_NODE *) ((void *)hBridge),
ui32PhysHeapCount, peaPhysHeapID, psapPhysHeapMemStats);
return eError;
}
IMG_INTERNAL PVRSRV_ERROR BridgeGetHeapPhysMemUsagePkd(IMG_HANDLE hBridge,
IMG_UINT32 ui32PhysHeapCount,
PHYS_HEAP_MEM_STATS_PKD *
psapPhysHeapMemStats)
{
PVRSRV_ERROR eError;
eError =
PVRSRVGetHeapPhysMemUsagePkdKM(NULL, (PVRSRV_DEVICE_NODE *) ((void *)hBridge),
ui32PhysHeapCount, psapPhysHeapMemStats);
return eError;
}

7
drivers/gpu/drm/img-rogue/common_cache_bridge.h
View File

@@ -71,7 +71,6 @@ typedef struct PVRSRV_BRIDGE_IN_CACHEOPQUEUE_TAG
IMG_DEVMEM_OFFSET_T *puiOffset;
IMG_DEVMEM_SIZE_T *puiSize;
IMG_HANDLE *phPMR;
IMG_UINT32 ui32CurrentFenceSeqNum;
IMG_UINT32 ui32NumCacheOps;
IMG_UINT32 ui32OpTimeline;
} __packed PVRSRV_BRIDGE_IN_CACHEOPQUEUE;
@@ -80,7 +79,6 @@ typedef struct PVRSRV_BRIDGE_IN_CACHEOPQUEUE_TAG
typedef struct PVRSRV_BRIDGE_OUT_CACHEOPQUEUE_TAG
{
PVRSRV_ERROR eError;
IMG_UINT32 ui32NextFenceSeqNum;
} __packed PVRSRV_BRIDGE_OUT_CACHEOPQUEUE;
/*******************************************
@@ -110,13 +108,12 @@ typedef struct PVRSRV_BRIDGE_OUT_CACHEOPEXEC_TAG
/* Bridge in structure for CacheOpLog */
typedef struct PVRSRV_BRIDGE_IN_CACHEOPLOG_TAG
{
IMG_INT64 i64ExecuteTimeUs;
IMG_INT64 i64QueuedTimeUs;
IMG_INT64 i64EndTime;
IMG_INT64 i64StartTime;
IMG_UINT64 ui64Address;
IMG_DEVMEM_OFFSET_T uiOffset;
IMG_DEVMEM_SIZE_T uiSize;
IMG_HANDLE hPMR;
IMG_INT32 i32NumRBF;
PVRSRV_CACHE_OP iuCacheOp;
} __packed PVRSRV_BRIDGE_IN_CACHEOPLOG;

50
drivers/gpu/drm/img-rogue/common_dmabuf_bridge.h
View File

@@ -55,9 +55,9 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define PVRSRV_BRIDGE_DMABUF_CMD_FIRST 0
#define PVRSRV_BRIDGE_DMABUF_PHYSMEMIMPORTDMABUF PVRSRV_BRIDGE_DMABUF_CMD_FIRST+0
#define PVRSRV_BRIDGE_DMABUF_PHYSMEMEXPORTDMABUF PVRSRV_BRIDGE_DMABUF_CMD_FIRST+1
#define PVRSRV_BRIDGE_DMABUF_PHYSMEMIMPORTSPARSEDMABUF PVRSRV_BRIDGE_DMABUF_CMD_FIRST+2
#define PVRSRV_BRIDGE_DMABUF_PHYSMEMIMPORTDMABUFLOCKED PVRSRV_BRIDGE_DMABUF_CMD_FIRST+3
#define PVRSRV_BRIDGE_DMABUF_PHYSMEMIMPORTDMABUFLOCKED PVRSRV_BRIDGE_DMABUF_CMD_FIRST+1
#define PVRSRV_BRIDGE_DMABUF_PHYSMEMEXPORTDMABUF PVRSRV_BRIDGE_DMABUF_CMD_FIRST+2
#define PVRSRV_BRIDGE_DMABUF_PHYSMEMIMPORTSPARSEDMABUF PVRSRV_BRIDGE_DMABUF_CMD_FIRST+3
#define PVRSRV_BRIDGE_DMABUF_CMD_LAST (PVRSRV_BRIDGE_DMABUF_CMD_FIRST+3)
/*******************************************
@@ -82,6 +82,28 @@ typedef struct PVRSRV_BRIDGE_OUT_PHYSMEMIMPORTDMABUF_TAG
PVRSRV_ERROR eError;
} __packed PVRSRV_BRIDGE_OUT_PHYSMEMIMPORTDMABUF;
/*******************************************
PhysmemImportDmaBufLocked
*******************************************/
/* Bridge in structure for PhysmemImportDmaBufLocked */
typedef struct PVRSRV_BRIDGE_IN_PHYSMEMIMPORTDMABUFLOCKED_TAG
{
const IMG_CHAR *puiName;
IMG_INT ifd;
IMG_UINT32 ui32NameSize;
PVRSRV_MEMALLOCFLAGS_T uiFlags;
} __packed PVRSRV_BRIDGE_IN_PHYSMEMIMPORTDMABUFLOCKED;
/* Bridge out structure for PhysmemImportDmaBufLocked */
typedef struct PVRSRV_BRIDGE_OUT_PHYSMEMIMPORTDMABUFLOCKED_TAG
{
IMG_DEVMEM_ALIGN_T uiAlign;
IMG_DEVMEM_SIZE_T uiSize;
IMG_HANDLE hPMRPtr;
PVRSRV_ERROR eError;
} __packed PVRSRV_BRIDGE_OUT_PHYSMEMIMPORTDMABUFLOCKED;
/*******************************************
PhysmemExportDmaBuf
*******************************************/
@@ -125,26 +147,4 @@ typedef struct PVRSRV_BRIDGE_OUT_PHYSMEMIMPORTSPARSEDMABUF_TAG
PVRSRV_ERROR eError;
} __packed PVRSRV_BRIDGE_OUT_PHYSMEMIMPORTSPARSEDMABUF;
/*******************************************
PhysmemImportDmaBufLocked
*******************************************/
/* Bridge in structure for PhysmemImportDmaBufLocked */
typedef struct PVRSRV_BRIDGE_IN_PHYSMEMIMPORTDMABUFLOCKED_TAG
{
const IMG_CHAR *puiName;
IMG_INT ifd;
IMG_UINT32 ui32NameSize;
PVRSRV_MEMALLOCFLAGS_T uiFlags;
} __packed PVRSRV_BRIDGE_IN_PHYSMEMIMPORTDMABUFLOCKED;
/* Bridge out structure for PhysmemImportDmaBufLocked */
typedef struct PVRSRV_BRIDGE_OUT_PHYSMEMIMPORTDMABUFLOCKED_TAG
{
IMG_DEVMEM_ALIGN_T uiAlign;
IMG_DEVMEM_SIZE_T uiSize;
IMG_HANDLE hPMRPtr;
PVRSRV_ERROR eError;
} __packed PVRSRV_BRIDGE_OUT_PHYSMEMIMPORTDMABUFLOCKED;
#endif /* COMMON_DMABUF_BRIDGE_H */

41
drivers/gpu/drm/img-rogue/common_mm_bridge.h
View File

@@ -96,7 +96,9 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define PVRSRV_BRIDGE_MM_GETHEAPPHYSMEMUSAGE PVRSRV_BRIDGE_MM_CMD_FIRST+37
#define PVRSRV_BRIDGE_MM_DEVMEMGETFAULTADDRESS PVRSRV_BRIDGE_MM_CMD_FIRST+38
#define PVRSRV_BRIDGE_MM_PVRSRVUPDATEOOMSTATS PVRSRV_BRIDGE_MM_CMD_FIRST+39
#define PVRSRV_BRIDGE_MM_CMD_LAST (PVRSRV_BRIDGE_MM_CMD_FIRST+39)
#define PVRSRV_BRIDGE_MM_PHYSHEAPGETMEMINFOPKD PVRSRV_BRIDGE_MM_CMD_FIRST+40
#define PVRSRV_BRIDGE_MM_GETHEAPPHYSMEMUSAGEPKD PVRSRV_BRIDGE_MM_CMD_FIRST+41
#define PVRSRV_BRIDGE_MM_CMD_LAST (PVRSRV_BRIDGE_MM_CMD_FIRST+41)
/*******************************************
PMRExportPMR
@@ -837,4 +839,41 @@ typedef struct PVRSRV_BRIDGE_OUT_PVRSRVUPDATEOOMSTATS_TAG
PVRSRV_ERROR eError;
} __packed PVRSRV_BRIDGE_OUT_PVRSRVUPDATEOOMSTATS;
/*******************************************
PhysHeapGetMemInfoPkd
*******************************************/
/* Bridge in structure for PhysHeapGetMemInfoPkd */
typedef struct PVRSRV_BRIDGE_IN_PHYSHEAPGETMEMINFOPKD_TAG
{
PHYS_HEAP_MEM_STATS_PKD *psapPhysHeapMemStats;
PVRSRV_PHYS_HEAP *peaPhysHeapID;
IMG_UINT32 ui32PhysHeapCount;
} __packed PVRSRV_BRIDGE_IN_PHYSHEAPGETMEMINFOPKD;
/* Bridge out structure for PhysHeapGetMemInfoPkd */
typedef struct PVRSRV_BRIDGE_OUT_PHYSHEAPGETMEMINFOPKD_TAG
{
PHYS_HEAP_MEM_STATS_PKD *psapPhysHeapMemStats;
PVRSRV_ERROR eError;
} __packed PVRSRV_BRIDGE_OUT_PHYSHEAPGETMEMINFOPKD;
/*******************************************
GetHeapPhysMemUsagePkd
*******************************************/
/* Bridge in structure for GetHeapPhysMemUsagePkd */
typedef struct PVRSRV_BRIDGE_IN_GETHEAPPHYSMEMUSAGEPKD_TAG
{
PHYS_HEAP_MEM_STATS_PKD *psapPhysHeapMemStats;
IMG_UINT32 ui32PhysHeapCount;
} __packed PVRSRV_BRIDGE_IN_GETHEAPPHYSMEMUSAGEPKD;
/* Bridge out structure for GetHeapPhysMemUsagePkd */
typedef struct PVRSRV_BRIDGE_OUT_GETHEAPPHYSMEMUSAGEPKD_TAG
{
PHYS_HEAP_MEM_STATS_PKD *psapPhysHeapMemStats;
PVRSRV_ERROR eError;
} __packed PVRSRV_BRIDGE_OUT_GETHEAPPHYSMEMUSAGEPKD;
#endif /* COMMON_MM_BRIDGE_H */

1
drivers/gpu/drm/img-rogue/common_rgxcmp_bridge.h
View File

@@ -174,7 +174,6 @@ typedef struct PVRSRV_BRIDGE_IN_RGXKICKCDM2_TAG
IMG_HANDLE *phSyncPMRs;
PVRSRV_FENCE hCheckFenceFd;
PVRSRV_TIMELINE hUpdateTimeline;
IMG_UINT32 ui32ClientCacheOpSeqNum;
IMG_UINT32 ui32ClientUpdateCount;
IMG_UINT32 ui32CmdSize;
IMG_UINT32 ui32ExtJobRef;

1
drivers/gpu/drm/img-rogue/common_rgxkicksync_bridge.h
View File

@@ -110,7 +110,6 @@ typedef struct PVRSRV_BRIDGE_IN_RGXKICKSYNC2_TAG
IMG_HANDLE *phUpdateUFODevVarBlock;
PVRSRV_FENCE hCheckFenceFD;
PVRSRV_TIMELINE hTimelineFenceFD;
IMG_UINT32 ui32ClientCacheOpSeqNum;
IMG_UINT32 ui32ClientUpdateCount;
IMG_UINT32 ui32ExtJobRef;
} __packed PVRSRV_BRIDGE_IN_RGXKICKSYNC2;

28
drivers/gpu/drm/img-rogue/common_rgxta3d_bridge.h
View File

@@ -80,32 +80,32 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
/* Bridge in structure for RGXCreateHWRTDataSet */
typedef struct PVRSRV_BRIDGE_IN_RGXCREATEHWRTDATASET_TAG
{
IMG_DEV_VIRTADDR sTailPtrsDevVAddr;
IMG_DEV_VIRTADDR ssRTCDevVAddr;
IMG_DEV_VIRTADDR ssVHeapTableDevVAddr;
IMG_UINT64 ui64FlippedMultiSampleCtl;
IMG_UINT64 ui64MultiSampleCtl;
IMG_DEV_VIRTADDR *psMacrotileArrayDevVAddr;
IMG_DEV_VIRTADDR *psPMMlistDevVAddr;
IMG_DEV_VIRTADDR *psRTCDevVAddr;
IMG_DEV_VIRTADDR *psRgnHeaderDevVAddr;
IMG_DEV_VIRTADDR *psTailPtrsDevVAddr;
IMG_DEV_VIRTADDR *psVHeapTableDevVAddr;
IMG_HANDLE *phKmHwRTDataSet;
IMG_HANDLE *phapsFreeLists;
IMG_UINT32 ui32ISPMergeLowerX;
IMG_UINT32 ui32ISPMergeLowerY;
IMG_UINT32 ui32ISPMergeScaleX;
IMG_UINT32 ui32ISPMergeScaleY;
IMG_UINT32 ui32ISPMergeUpperX;
IMG_UINT32 ui32ISPMergeUpperY;
IMG_UINT32 ui32ISPMtileSize;
IMG_UINT32 ui32MTileStride;
IMG_UINT32 ui32PPPScreen;
IMG_UINT32 ui32RgnHeaderSize;
IMG_UINT32 ui32TEAA;
IMG_UINT32 ui32TEMTILE1;
IMG_UINT32 ui32TEMTILE2;
IMG_UINT32 ui32TEScreen;
IMG_UINT32 ui32TPCSize;
IMG_UINT32 ui32TPCStride;
IMG_UINT32 ui32ui32ISPMergeLowerX;
IMG_UINT32 ui32ui32ISPMergeLowerY;
IMG_UINT32 ui32ui32ISPMergeScaleX;
IMG_UINT32 ui32ui32ISPMergeScaleY;
IMG_UINT32 ui32ui32ISPMergeUpperX;
IMG_UINT32 ui32ui32ISPMergeUpperY;
IMG_UINT32 ui32ui32ISPMtileSize;
IMG_UINT32 ui32uiRgnHeaderSize;
IMG_UINT16 ui16MaxRTs;
} __packed PVRSRV_BRIDGE_IN_RGXCREATEHWRTDATASET;
@@ -261,6 +261,7 @@ typedef struct PVRSRV_BRIDGE_IN_RGXCREATERENDERCONTEXT_TAG
IMG_UINT32 ui32PackedCCBSizeU8888;
IMG_UINT32 ui32Priority;
IMG_UINT32 ui32StaticRenderContextStateSize;
IMG_UINT32 ui32ui32CallStackDepth;
} __packed PVRSRV_BRIDGE_IN_RGXCREATERENDERCONTEXT;
/* Bridge out structure for RGXCreateRenderContext */
@@ -359,16 +360,15 @@ typedef struct PVRSRV_BRIDGE_IN_RGXKICKTA3D2_TAG
IMG_UINT32 ui323DCmdSize;
IMG_UINT32 ui323DPRCmdSize;
IMG_UINT32 ui32Client3DUpdateCount;
IMG_UINT32 ui32ClientCacheOpSeqNum;
IMG_UINT32 ui32ClientTAFenceCount;
IMG_UINT32 ui32ClientTAUpdateCount;
IMG_UINT32 ui32ExtJobRef;
IMG_UINT32 ui32FRFenceUFOSyncOffset;
IMG_UINT32 ui32FRFenceValue;
IMG_UINT32 ui32NumberOfDrawCalls;
IMG_UINT32 ui32NumberOfIndices;
IMG_UINT32 ui32NumberOfMRTs;
IMG_UINT32 ui32PDumpFlags;
IMG_UINT32 ui32PRFenceUFOSyncOffset;
IMG_UINT32 ui32PRFenceValue;
IMG_UINT32 ui32RenderTargetSize;
IMG_UINT32 ui32SyncPMRCount;
IMG_UINT32 ui32TACmdSize;

4
drivers/gpu/drm/img-rogue/common_rgxtq2_bridge.h
View File

@@ -72,10 +72,11 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
/* Bridge in structure for RGXTDMCreateTransferContext */
typedef struct PVRSRV_BRIDGE_IN_RGXTDMCREATETRANSFERCONTEXT_TAG
{
IMG_UINT64 ui64RobustnessAddress;
IMG_HANDLE hPrivData;
IMG_BYTE *pui8FrameworkCmd;
IMG_UINT32 ui32ContextFlags;
IMG_UINT32 ui32FrameworkCmdize;
IMG_UINT32 ui32FrameworkCmdSize;
IMG_UINT32 ui32PackedCCBSizeU88;
IMG_UINT32 ui32Priority;
} __packed PVRSRV_BRIDGE_IN_RGXTDMCREATETRANSFERCONTEXT;
@@ -157,7 +158,6 @@ typedef struct PVRSRV_BRIDGE_IN_RGXTDMSUBMITTRANSFER2_TAG
PVRSRV_TIMELINE hUpdateTimeline;
IMG_UINT32 ui32Characteristic1;
IMG_UINT32 ui32Characteristic2;
IMG_UINT32 ui32ClientCacheOpSeqNum;
IMG_UINT32 ui32ClientUpdateCount;
IMG_UINT32 ui32CommandSize;
IMG_UINT32 ui32ExternalJobReference;

2
drivers/gpu/drm/img-rogue/common_rgxtq_bridge.h
View File

@@ -69,6 +69,7 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
/* Bridge in structure for RGXCreateTransferContext */
typedef struct PVRSRV_BRIDGE_IN_RGXCREATETRANSFERCONTEXT_TAG
{
IMG_UINT64 ui64RobustnessAddress;
IMG_HANDLE hPrivData;
IMG_BYTE *pui8FrameworkCmd;
IMG_UINT32 ui32ContextFlags;
@@ -140,7 +141,6 @@ typedef struct PVRSRV_BRIDGE_IN_RGXSUBMITTRANSFER2_TAG
PVRSRV_TIMELINE h2DUpdateTimeline;
PVRSRV_TIMELINE h3DUpdateTimeline;
PVRSRV_FENCE hCheckFenceFD;
IMG_UINT32 ui32ClientCacheOpSeqNum;
IMG_UINT32 ui32ExtJobRef;
IMG_UINT32 ui32PrepareCount;
IMG_UINT32 ui32SyncPMRCount;

21
drivers/gpu/drm/img-rogue/config_kernel.h
View File

@@ -3,12 +3,11 @@
#define RGX_FW_FILENAME "rgx.fw"
#define RGX_SH_FILENAME "rgx.sh"
#define PVR_BUILD_DIR "thead_linux"
#define PVR_BUILD_TYPE "release"
#define PVRSRV_MODNAME "pvrsrvkm"
#define PVRSYNC_MODNAME "pvr_sync"
#define SUPPORT_RGX 1
#define DISPLAY_CONTROLLER drm_nulldisp
#define RELEASE
#define PVRSRV_HWPERF_COUNTERS_PERBLK 12
#define RGX_BVNC_CORE_KM_HEADER "cores/rgxcore_km_36.52.104.182.h"
#define RGX_BNC_CONFIG_KM_HEADER "configs/rgxconfig_km_36.V.104.182.h"
#define PVRSRV_NEED_PVR_DPF
@@ -51,7 +50,6 @@
#define PVRSRV_APPHINT_ENABLERANDOMCONTEXTSWITCH 0
#define PVRSRV_APPHINT_ENABLESOFTRESETCNTEXTSWITCH 0
#define PVRSRV_APPHINT_ENABLEFWCONTEXTSWITCH RGXFWIF_INICFG_OS_CTXSWITCH_DM_ALL
#define PVRSRV_APPHINT_VDMCONTEXTSWITCHMODE RGXFWIF_INICFG_VDM_CTX_STORE_MODE_INDEX
#define PVRSRV_APPHINT_ENABLERDPOWERISLAND RGX_RD_POWER_ISLAND_DEFAULT
#define PVRSRV_APPHINT_FIRMWAREPERF FW_PERF_CONF_NONE
#define PVRSRV_APPHINT_FWCONTEXTSWITCHPROFILE RGXFWIF_CTXSWITCH_PROFILE_MEDIUM_EN
@@ -104,6 +102,7 @@
#define PVRSRV_APPHINT_PHYSMEMTESTPASSES APPHNT_PHYSMEMTEST_ENABLE
#define PVRSRV_APPHINT_TESTSLRINTERVAL 0
#define PVRSRV_APPHINT_RISCVDMITEST 0
#define PVRSRV_APPHINT_VALIDATESOCUSCTIMERS 0
#define SOC_TIMER_FREQ 20
#define PDVFS_COM_HOST 1
#define PDVFS_COM_AP 2
@@ -115,8 +114,9 @@
#define PVR_GPIO_MODE PVR_GPIO_MODE_GENERAL
#define PVRSRV_ENABLE_PROCESS_STATS
#define SUPPORT_USC_BREAKPOINT
#define SUPPORT_AGP
#define RGXFW_SAFETY_WATCHDOG_PERIOD_IN_US 1000000
#define PVR_ANNOTATION_MAX_LEN 63
#define PVRSRV_DEVICE_INIT_MODE PVRSRV_LINUX_DEV_INIT_ON_CONNECT
#define SUPPORT_DI_BRG_IMPL
#define PVR_LINUX_PHYSMEM_MAX_POOL_PAGES 10240
#define PVR_LINUX_PHYSMEM_MAX_EXCESS_POOL_PAGES 20480
@@ -148,3 +148,16 @@
#define PVRSRV_RGX_LOG2_CLIENT_CCB_MAX_SIZE_TDM 17
#define PVRSRV_RGX_LOG2_CLIENT_CCB_MAX_SIZE_RDM 15
#define SUPPORT_BUFFER_SYNC 1
#ifdef CONFIG_DRM_POWERVR_ROGUE_DEBUG
#define DEBUG
#define DEBUG_BRIDGE_KM
#define PVRSRV_ENABLE_GPU_MEMORY_INFO
#define PVRSRV_ENABLE_SYNC_POISONING
#define PVR_ANNOTATION_MAX_LEN 96
#define PVR_BUILD_TYPE "debug"
#define TRACK_FW_BOOT
#else
#define PVR_ANNOTATION_MAX_LEN 63
#define PVR_BUILD_TYPE "release"
#define RELEASE
#endif

4
drivers/gpu/drm/img-rogue/config_kernel.mk
View File

@@ -1,3 +1,4 @@
override PVRSRV_DIR := services
override HOST_PRIMARY_ARCH := host_x86_64
override HOST_32BIT_ARCH := host_i386
override HOST_FORCE_32BIT := -m32
@@ -20,7 +21,9 @@ override PVR_SYSTEM := rgx_thead
override PVR_LOADER :=
override SORT_BRIDGE_STRUCTS := 1
override DEBUGLINK := 1
override RGX_BNC := 36.V.104.182
override SUPPORT_PHYSMEM_TEST := 1
override SUPPORT_MIPS_64K_PAGE_SIZE :=
override RGX_NUM_OS_SUPPORTED := 1
override VMM_TYPE := stub
override SUPPORT_POWMON_COMPONENT := 1
@@ -48,4 +51,3 @@ else
override BUILD := release
override PVR_BUILD_TYPE := release
endif

2
drivers/gpu/drm/img-rogue/configs/rgxconfig_km_1.V.4.5.h
View File

@@ -59,6 +59,8 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define RGX_FEATURE_COMPUTE_OVERLAP
#define RGX_FEATURE_FBCDC_ALGORITHM (1U)
#define RGX_FEATURE_FBCDC_ARCHITECTURE (1U)
#define RGX_FEATURE_FBC_MAX_DEFAULT_DESCRIPTORS (0U)
#define RGX_FEATURE_FBC_MAX_LARGE_DESCRIPTORS (0U)
#define RGX_FEATURE_GS_RTA_SUPPORT
#define RGX_FEATURE_LAYOUT_MARS (0U)
#define RGX_FEATURE_META (MTP218)

4
drivers/gpu/drm/img-rogue/configs/rgxconfig_km_36.V.104.182.h
View File

@@ -62,6 +62,8 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define RGX_FEATURE_FBCDC (50U)
#define RGX_FEATURE_FBCDC_ALGORITHM (50U)
#define RGX_FEATURE_FBCDC_ARCHITECTURE (7U)
#define RGX_FEATURE_FBC_MAX_DEFAULT_DESCRIPTORS (0U)
#define RGX_FEATURE_FBC_MAX_LARGE_DESCRIPTORS (0U)
#define RGX_FEATURE_GPU_MULTICORE_SUPPORT
#define RGX_FEATURE_GPU_VIRTUALISATION
#define RGX_FEATURE_GS_RTA_SUPPORT
@@ -87,12 +89,14 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
/* size must be sourced from */
/* register. */
#define RGX_FEATURE_SLC_SIZE_IN_KILOBYTES (16U)
#define RGX_FEATURE_SOC_TIMER
#define RGX_FEATURE_SYS_BUS_SECURE_RESET
#define RGX_FEATURE_TILE_SIZE_X (16U)
#define RGX_FEATURE_TILE_SIZE_Y (16U)
#define RGX_FEATURE_TPU_CEM_DATAMASTER_GLOBAL_REGISTERS
#define RGX_FEATURE_TPU_DM_GLOBAL_REGISTERS
#define RGX_FEATURE_VIRTUAL_ADDRESS_SPACE_BITS (40U)
#define RGX_FEATURE_XE_ARCHITECTURE (1U)
#define RGX_FEATURE_XE_MEMORY_HIERARCHY
#define RGX_FEATURE_XPU_MAX_REGBANKS_ADDR_WIDTH (19U)
#define RGX_FEATURE_XPU_MAX_SLAVES (3U)

221
drivers/gpu/drm/img-rogue/connection_server.c
View File

@@ -53,6 +53,7 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#include "pdump_km.h"
#include "osfunc.h"
#include "tlstream.h"
#include "rgxhwperf_common.h"
/* PID associated with Connection currently being purged by Cleanup thread */
static IMG_PID gCurrentPurgeConnectionPid;
@@ -91,41 +92,9 @@ static PVRSRV_ERROR ConnectionDataDestroy(CONNECTION_DATA *psConnection)
if (psProcessHandleBase != NULL)
{
/* acquire the lock now to ensure unref and removal from the
* hash table is atomic.
* if the refcount becomes zero then the lock needs to be held
* until the entry is removed from the hash table.
*/
OSLockAcquire(psPVRSRVData->hProcessHandleBase_Lock);
/* In case the refcount becomes 0 we can remove the process handle base */
if (OSAtomicDecrement(&psProcessHandleBase->iRefCount) == 0)
{
uintptr_t uiHashValue;
uiHashValue = HASH_Remove(psPVRSRVData->psProcessHandleBase_Table, psConnection->pid);
OSLockRelease(psPVRSRVData->hProcessHandleBase_Lock);
if (!uiHashValue)
{
PVR_DPF((PVR_DBG_ERROR,
"%s: Failed to remove handle base from hash table.",
__func__));
return PVRSRV_ERROR_UNABLE_TO_REMOVE_HASH_VALUE;
}
eError = PVRSRVFreeKernelHandles(psProcessHandleBase->psHandleBase);
PVR_LOG_RETURN_IF_ERROR(eError, "PVRSRVFreeKernelHandles");
eError = PVRSRVFreeHandleBase(psProcessHandleBase->psHandleBase, ui64MaxBridgeTime);
PVR_LOG_RETURN_IF_ERROR(eError, "PVRSRVFreeHandleBase:1");
OSFreeMem(psProcessHandleBase);
}
else
{
OSLockRelease(psPVRSRVData->hProcessHandleBase_Lock);
}
eError = PVRSRVReleaseProcessHandleBase(psProcessHandleBase, psConnection->pid,
ui64MaxBridgeTime);
PVR_LOG_RETURN_IF_ERROR(eError, "PVRSRVReleaseProcessHandleBase");
psConnection->psProcessHandleBase = NULL;
}
@@ -195,7 +164,6 @@ PVRSRV_ERROR PVRSRVCommonConnectionConnect(void **ppvPrivData, void *pvOSData)
CONNECTION_DATA *psConnection;
PVRSRV_ERROR eError;
PROCESS_HANDLE_BASE *psProcessHandleBase;
PVRSRV_DATA *psPVRSRVData = PVRSRVGetPVRSRVData();
/* Allocate connection data area, no stats since process not registered yet */
psConnection = OSAllocZMemNoStats(sizeof(*psConnection));
@@ -245,46 +213,14 @@ PVRSRV_ERROR PVRSRVCommonConnectionConnect(void **ppvPrivData, void *pvOSData)
PVRSRV_HANDLE_BASE_TYPE_CONNECTION);
PVR_LOG_GOTO_IF_ERROR(eError, "PVRSRVAllocHandleBase", failure);
/* Try to get process handle base if it already exists */
OSLockAcquire(psPVRSRVData->hProcessHandleBase_Lock);
psProcessHandleBase = (PROCESS_HANDLE_BASE*) HASH_Retrieve(PVRSRVGetPVRSRVData()->psProcessHandleBase_Table,
psConnection->pid);
/* In case there is none we are going to allocate one */
if (psProcessHandleBase == NULL)
{
psProcessHandleBase = OSAllocZMem(sizeof(PROCESS_HANDLE_BASE));
PVR_LOG_GOTO_IF_NOMEM(psProcessHandleBase, eError, failureLock);
OSAtomicWrite(&psProcessHandleBase->iRefCount, 0);
/* Allocate handle base for this process */
eError = PVRSRVAllocHandleBase(&psProcessHandleBase->psHandleBase,
PVRSRV_HANDLE_BASE_TYPE_PROCESS);
if (eError != PVRSRV_OK)
{
PVR_LOG_ERROR(eError, "PVRSRVAllocHandleBase");
OSFreeMem(psProcessHandleBase);
goto failureLock;
}
/* Insert the handle base into the global hash table */
if (!HASH_Insert(PVRSRVGetPVRSRVData()->psProcessHandleBase_Table,
psConnection->pid,
(uintptr_t) psProcessHandleBase))
{
PVRSRVFreeHandleBase(psProcessHandleBase->psHandleBase, 0);
OSFreeMem(psProcessHandleBase);
PVR_GOTO_WITH_ERROR(eError, PVRSRV_ERROR_UNABLE_TO_INSERT_HASH_VALUE, failureLock);
}
}
OSAtomicIncrement(&psProcessHandleBase->iRefCount);
OSLockRelease(psPVRSRVData->hProcessHandleBase_Lock);
/* get process handle base (if it doesn't exist it will be allocated) */
eError = PVRSRVAcquireProcessHandleBase(psConnection->pid, &psProcessHandleBase);
PVR_LOG_GOTO_IF_ERROR(eError, "PVRSRVAcquireProcessHandleBase", failure);
/* hConnectionsLock now resides in PVRSRV_DEVICE_NODE */
{
IMG_BOOL bHostStreamIsNull;
PVRSRV_RGXDEV_INFO *psRgxDevInfo;
PVRSRV_DEVICE_NODE *psDevNode = OSGetDevNode(psConnection);
OSLockAcquire(psDevNode->hConnectionsLock);
@@ -294,6 +230,24 @@ PVRSRV_ERROR PVRSRVCommonConnectionConnect(void **ppvPrivData, void *pvOSData)
psDevNode->sDevId.ui32InternalID));
#endif
OSLockRelease(psDevNode->hConnectionsLock);
if (!PVRSRV_VZ_MODE_IS(GUEST))
{
psRgxDevInfo = _RGX_DEVICE_INFO_FROM_NODE(psDevNode);
OSLockAcquire(psRgxDevInfo->hLockHWPerfHostStream);
bHostStreamIsNull = (IMG_BOOL)(psRgxDevInfo->hHWPerfHostStream == NULL);
OSLockRelease(psRgxDevInfo->hLockHWPerfHostStream);
if (!bHostStreamIsNull)
{
if (TLStreamIsOpenForReading(psRgxDevInfo->hHWPerfHostStream))
{
/* Announce this client connection in the host stream, if event mask is set */
RGXSRV_HWPERF_HOST_CLIENT_INFO_PROCESS_NAME(psDevNode, psConnection->pid, psConnection->pszProcName);
}
}
}
}
psConnection->psProcessHandleBase = psProcessHandleBase;
@@ -302,8 +256,6 @@ PVRSRV_ERROR PVRSRVCommonConnectionConnect(void **ppvPrivData, void *pvOSData)
return PVRSRV_OK;
failureLock:
OSLockRelease(psPVRSRVData->hProcessHandleBase_Lock);
failure:
ConnectionDataDestroy(psConnection);
@@ -461,80 +413,79 @@ void PVRSRVConnectionDebugNotify(PVRSRV_DEVICE_NODE *psDevNode,
if (psDevNode->eDevState != PVRSRV_DEVICE_STATE_ACTIVE)
{
PVR_DUMPDEBUG_LOG("Connections: No Devices: No active connections");
return;
}
OSLockAcquire(psDevNode->hConnectionsLock);
if (dllist_is_empty(&psDevNode->sConnections))
{
PVR_DUMPDEBUG_LOG(CONNECTIONS_PREFIX " No active connections",
(unsigned char)psDevNode->sDevId.ui32InternalID,
(unsigned char)psDevNode->sDevId.i32OsDeviceID);
}
else
{
OSLockAcquire(psDevNode->hConnectionsLock);
if (dllist_is_empty(&psDevNode->sConnections))
{
PVR_DUMPDEBUG_LOG(CONNECTIONS_PREFIX " No active connections",
(unsigned char)psDevNode->sDevId.ui32InternalID,
(unsigned char)psDevNode->sDevId.i32OsDeviceID);
}
else
{
IMG_CHAR sActiveConnections[MAX_DEBUG_DUMP_STRING_LEN];
IMG_UINT16 i, uiPos = 0;
IMG_BOOL bPrinted = IMG_FALSE;
size_t uiSize = sizeof(sActiveConnections);
IMG_CHAR sActiveConnections[MAX_DEBUG_DUMP_STRING_LEN];
IMG_UINT16 i, uiPos = 0;
IMG_BOOL bPrinted = IMG_FALSE;
size_t uiSize = sizeof(sActiveConnections);
IMG_CHAR szTmpConBuff[MAX_CONNECTIONS_PREFIX + 1];
i = OSSNPrintf(szTmpConBuff,
MAX_CONNECTIONS_PREFIX,
CONNECTIONS_PREFIX,
(unsigned char)psDevNode->sDevId.ui32InternalID,
(unsigned char)psDevNode->sDevId.i32OsDeviceID);
OSStringLCopy(sActiveConnections+uiPos, szTmpConBuff, uiSize);
IMG_CHAR szTmpConBuff[MAX_CONNECTIONS_PREFIX + 1];
i = OSSNPrintf(szTmpConBuff,
MAX_CONNECTIONS_PREFIX,
CONNECTIONS_PREFIX,
(unsigned char)psDevNode->sDevId.ui32InternalID,
(unsigned char)psDevNode->sDevId.i32OsDeviceID);
OSStringLCopy(sActiveConnections+uiPos, szTmpConBuff, uiSize);
/* Move the write offset to the end of the current string */
uiPos += i;
/* Update the amount of remaining space available to copy into */
uiSize -= i;
dllist_foreach_node(&psDevNode->sConnections, pNode, pNext)
{
CONNECTION_DATA *sData = IMG_CONTAINER_OF(pNode, CONNECTION_DATA, sConnectionListNode);
IMG_CHAR sTmpBuff[MAX_DEBUG_DUMP_CONNECTION_STR_LEN];
i = OSSNPrintf(sTmpBuff, MAX_DEBUG_DUMP_CONNECTION_STR_LEN,
DEBUG_DUMP_CONNECTION_FORMAT_STR, sData->pid, sData->vpid, sData->tid, sData->pszProcName);
i = MIN(MAX_DEBUG_DUMP_CONNECTION_STR_LEN, i);
bPrinted = IMG_FALSE;
OSStringLCopy(sActiveConnections+uiPos, sTmpBuff, uiSize);
/* Move the write offset to the end of the current string */
uiPos += i;
/* Update the amount of remaining space available to copy into */
uiSize -= i;
dllist_foreach_node(&psDevNode->sConnections, pNode, pNext)
/* If there is not enough space to add another connection to this line, output the line */
if (uiSize <= MAX_DEBUG_DUMP_CONNECTION_STR_LEN)
{
CONNECTION_DATA *sData = IMG_CONTAINER_OF(pNode, CONNECTION_DATA, sConnectionListNode);
IMG_CHAR sTmpBuff[MAX_DEBUG_DUMP_CONNECTION_STR_LEN];
i = OSSNPrintf(sTmpBuff, MAX_DEBUG_DUMP_CONNECTION_STR_LEN,
DEBUG_DUMP_CONNECTION_FORMAT_STR, sData->pid, sData->vpid, sData->tid, sData->pszProcName);
i = MIN(MAX_DEBUG_DUMP_CONNECTION_STR_LEN, i);
bPrinted = IMG_FALSE;
OSStringLCopy(sActiveConnections+uiPos, sTmpBuff, uiSize);
/* Move the write offset to the end of the current string */
uiPos += i;
/* Update the amount of remaining space available to copy into */
uiSize -= i;
/* If there is not enough space to add another connection to this line, output the line */
if (uiSize <= MAX_DEBUG_DUMP_CONNECTION_STR_LEN)
{
PVR_DUMPDEBUG_LOG("%s", sActiveConnections);
/*
* Remove the "Connections:" prefix from the buffer.
* Leave the subsequent buffer contents indented by the same
* amount to aid in interpreting the debug output.
*/
uiPos = sizeof(CONNECTIONS_PREFIX) - 1;
/* Reset the amount of space available to copy into */
uiSize = MAX_DEBUG_DUMP_STRING_LEN - uiPos;
bPrinted = IMG_TRUE;
}
}
/* Only print the current line if it hasn't already been printed */
if (!bPrinted)
{
// Strip of the final comma
sActiveConnections[OSStringNLength(sActiveConnections, MAX_DEBUG_DUMP_STRING_LEN) - 1] = '\0';
PVR_DUMPDEBUG_LOG("%s", sActiveConnections);
/*
* Remove the "Connections:" prefix from the buffer.
* Leave the subsequent buffer contents indented by the same
* amount to aid in interpreting the debug output.
*/
uiPos = sizeof(CONNECTIONS_PREFIX) - 1;
/* Reset the amount of space available to copy into */
uiSize = MAX_DEBUG_DUMP_STRING_LEN - uiPos;
bPrinted = IMG_TRUE;
}
}
/* Only print the current line if it hasn't already been printed */
if (!bPrinted)
{
/* Strip off the final comma */
sActiveConnections[OSStringNLength(sActiveConnections, MAX_DEBUG_DUMP_STRING_LEN) - 1] = '\0';
PVR_DUMPDEBUG_LOG("%s", sActiveConnections);
}
#undef MAX_DEBUG_DUMP_STRING_LEN
#undef MAX_DEBUG_DUMP_CONNECTIONS_PER_LINE
}
OSLockRelease(psDevNode->hConnectionsLock);
}
OSLockRelease(psDevNode->hConnectionsLock);
}

9
drivers/gpu/drm/img-rogue/connection_server.h
View File

@@ -117,6 +117,15 @@ typedef struct _CONNECTION_DATA_
PVRSRV_ERROR PVRSRVCommonConnectionConnect(void **ppvPrivData, void *pvOSData);
void PVRSRVCommonConnectionDisconnect(void *pvPrivData);
/**************************************************************************/ /*!
@Function PVRSRVGetPurgeConnectionPid
@Description Returns PID associated with Connection currently being purged by
Cleanup Thread. If no Connection is purged 0 is returned.
@Return PID associated with currently purged connection or 0 if no
connection is being purged
*/ /***************************************************************************/
IMG_PID PVRSRVGetPurgeConnectionPid(void);
void PVRSRVConnectionDebugNotify(PVRSRV_DEVICE_NODE *psDevNode,

2
drivers/gpu/drm/img-rogue/cores/rgxcore_km_1.82.4.5.h
View File

@@ -42,7 +42,7 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#ifndef RGXCORE_KM_1_82_4_5_H
#define RGXCORE_KM_1_82_4_5_H
/* Automatically generated file (29/06/2021 09:01:16): Do not edit manually */
/* Automatically generated file (04/10/2021 09:01:50): Do not edit manually */
/* CS: @2503111 */
/******************************************************************************

2
drivers/gpu/drm/img-rogue/cores/rgxcore_km_36.52.104.182.h
View File

@@ -42,7 +42,7 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#ifndef RGXCORE_KM_36_52_104_182_H
#define RGXCORE_KM_36_52_104_182_H
/* Automatically generated file (29/06/2021 09:01:17): Do not edit manually */
/* Automatically generated file (04/10/2021 09:01:50): Do not edit manually */
/* CS: @5849605 */
/******************************************************************************

276
drivers/gpu/drm/img-rogue/debug_common.c
View File

@@ -58,17 +58,13 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#include "rgxdevice.h"
#include "rgxdebug.h"
#include "rgxinit.h"
#include "rgxmmudefs_km.h"
static IMG_HANDLE ghGpuUtilUserDebugFS;
#endif
static DI_ENTRY *gpsVersionDIEntry;
static DI_ENTRY *gpsStatusDIEntry;
#ifdef SUPPORT_RGX
#ifdef SUPPORT_FIRMWARE_GCOV
static DI_ENTRY *gpsFirmwareGcovDIEntry;
#endif /* SUPPORT_FIRMWARE_GCOV */
#endif /* SUPPORT_RGX */
#ifdef SUPPORT_VALIDATION
static DI_ENTRY *gpsTestMemLeakDIEntry;
#endif /* SUPPORT_VALIDATION */
@@ -108,6 +104,7 @@ static void *_VersionDIStart(OSDI_IMPL_ENTRY *psEntry, IMG_UINT64 *pui64Pos)
{
PVRSRV_DATA *psPVRSRVData = DIGetPrivData(psEntry);
IMG_UINT64 uiCurrentPosition = 1;
PVRSRV_DEVICE_NODE *psDeviceNode;
PVR_UNREFERENCED_PARAMETER(psEntry);
@@ -121,10 +118,14 @@ static void *_VersionDIStart(OSDI_IMPL_ENTRY *psEntry, IMG_UINT64 *pui64Pos)
return DI_START_TOKEN;
}
return List_PVRSRV_DEVICE_NODE_Any_va(psPVRSRVData->psDeviceNodeList,
OSWRLockAcquireRead(psPVRSRVData->hDeviceNodeListLock);
psDeviceNode = List_PVRSRV_DEVICE_NODE_Any_va(psPVRSRVData->psDeviceNodeList,
_DebugVersionCompare_AnyVaCb,
&uiCurrentPosition,
*pui64Pos);
OSWRLockReleaseRead(psPVRSRVData->hDeviceNodeListLock);
return psDeviceNode;
}
static void _VersionDIStop(OSDI_IMPL_ENTRY *psEntry, void *pvPriv)
@@ -138,13 +139,18 @@ static void *_VersionDINext(OSDI_IMPL_ENTRY *psEntry,void *pvPriv,
{
PVRSRV_DATA *psPVRSRVData = DIGetPrivData(psEntry);
IMG_UINT64 uiCurrentPosition = 1;
PVRSRV_DEVICE_NODE *psDeviceNode;
(*pui64Pos)++;
return List_PVRSRV_DEVICE_NODE_Any_va(psPVRSRVData->psDeviceNodeList,
OSWRLockAcquireRead(psPVRSRVData->hDeviceNodeListLock);
psDeviceNode = List_PVRSRV_DEVICE_NODE_Any_va(psPVRSRVData->psDeviceNodeList,
_DebugVersionCompare_AnyVaCb,
&uiCurrentPosition,
*pui64Pos);
OSWRLockReleaseRead(psPVRSRVData->hDeviceNodeListLock);
return psDeviceNode;
}
#define DI_PRINT_VERSION_FMTSPEC \
@@ -518,16 +524,21 @@ static void *_DebugStatusDIStart(OSDI_IMPL_ENTRY *psEntry, IMG_UINT64 *pui64Pos)
{
PVRSRV_DATA *psPVRSRVData = DIGetPrivData(psEntry);
IMG_UINT64 uiCurrentPosition = 1;
PVRSRV_DEVICE_NODE *psDeviceNode;
if (*pui64Pos == 0)
{
return DI_START_TOKEN;
}
return List_PVRSRV_DEVICE_NODE_Any_va(psPVRSRVData->psDeviceNodeList,
OSWRLockAcquireRead(psPVRSRVData->hDeviceNodeListLock);
psDeviceNode = List_PVRSRV_DEVICE_NODE_Any_va(psPVRSRVData->psDeviceNodeList,
_DebugStatusCompare_AnyVaCb,
&uiCurrentPosition,
*pui64Pos);
OSWRLockReleaseRead(psPVRSRVData->hDeviceNodeListLock);
return psDeviceNode;
}
static void _DebugStatusDIStop(OSDI_IMPL_ENTRY *psEntry, void *pvData)
@@ -542,15 +553,20 @@ static void *_DebugStatusDINext(OSDI_IMPL_ENTRY *psEntry,
{
PVRSRV_DATA *psPVRSRVData = DIGetPrivData(psEntry);
IMG_UINT64 uiCurrentPosition = 1;
PVRSRV_DEVICE_NODE *psDeviceNode;
PVR_UNREFERENCED_PARAMETER(pvData);
(*pui64Pos)++;
return List_PVRSRV_DEVICE_NODE_Any_va(psPVRSRVData->psDeviceNodeList,
OSWRLockAcquireRead(psPVRSRVData->hDeviceNodeListLock);
psDeviceNode = List_PVRSRV_DEVICE_NODE_Any_va(psPVRSRVData->psDeviceNodeList,
_DebugStatusCompare_AnyVaCb,
&uiCurrentPosition,
*pui64Pos);
OSWRLockReleaseRead(psPVRSRVData->hDeviceNodeListLock);
return psDeviceNode;
}
static int _DebugStatusDIShow(OSDI_IMPL_ENTRY *psEntry, void *pvData)
@@ -779,26 +795,155 @@ static int _DebugFWTraceDIShow(OSDI_IMPL_ENTRY *psEntry, void *pvData)
return 0;
}
#ifdef SUPPORT_FIRMWARE_GCOV
/*************************************************************************/ /*!
Firmware Translated Page Tables DebugFS entry
*/ /**************************************************************************/
static PVRSRV_RGXDEV_INFO *getPsDevInfo(OSDI_IMPL_ENTRY *psEntry)
static void _DocumentFwMapping(OSDI_IMPL_ENTRY *psEntry,
PVRSRV_RGXDEV_INFO *psDevInfo,
IMG_UINT32 ui32FwVA,
IMG_CPU_PHYADDR sCpuPA,
IMG_DEV_PHYADDR sDevPA,
IMG_UINT64 ui64PTE)
{
PVRSRV_DATA *psPVRSRVData = DIGetPrivData(psEntry);
if (psPVRSRVData != NULL)
#if defined(RGX_FEATURE_MIPS_BIT_MASK)
if (RGX_IS_FEATURE_SUPPORTED(psDevInfo, MIPS))
{
if (psPVRSRVData->psDeviceNodeList != NULL)
DIPrintf(psEntry, "| 0x%8X | "
"0x%16" IMG_UINT64_FMTSPECX " | "
"0x%16" IMG_UINT64_FMTSPECX " | "
"%s%s%s |\n",
ui32FwVA,
(IMG_UINT64) sCpuPA.uiAddr,
sDevPA.uiAddr,
gapszMipsPermissionPTFlags[RGXMIPSFW_TLB_GET_INHIBIT(ui64PTE)],
gapszMipsDirtyGlobalValidPTFlags[RGXMIPSFW_TLB_GET_DGV(ui64PTE)],
gapszMipsCoherencyPTFlags[RGXMIPSFW_TLB_GET_COHERENCY(ui64PTE)]);
}
else
#endif
{
/* META and RISCV use a subset of the GPU's virtual address space */
DIPrintf(psEntry, "| 0x%8X | "
"0x%16" IMG_UINT64_FMTSPECX " | "
"0x%16" IMG_UINT64_FMTSPECX " | "
"%s%s%s%s%s%s |\n",
ui32FwVA,
(IMG_UINT64) sCpuPA.uiAddr,
sDevPA.uiAddr,
BITMASK_HAS(ui64PTE, RGX_MMUCTRL_PT_DATA_ENTRY_PENDING_EN) ? "P" : " ",
BITMASK_HAS(ui64PTE, RGX_MMUCTRL_PT_DATA_PM_SRC_EN) ? "PM" : " ",
#if defined(RGX_MMUCTRL_PT_DATA_SLC_BYPASS_CTRL_EN)
BITMASK_HAS(ui64PTE, RGX_MMUCTRL_PT_DATA_SLC_BYPASS_CTRL_EN) ? "B" : " ",
#else
" ",
#endif
BITMASK_HAS(ui64PTE, RGX_MMUCTRL_PT_DATA_CC_EN) ? "C" : " ",
BITMASK_HAS(ui64PTE, RGX_MMUCTRL_PT_DATA_READ_ONLY_EN) ? "RO" : "RW",
BITMASK_HAS(ui64PTE, RGX_MMUCTRL_PT_DATA_VALID_EN) ? "V" : " ");
}
}
static int _FirmwareMappingsDIShow(OSDI_IMPL_ENTRY *psEntry, void *pvData)
{
PVRSRV_DEVICE_NODE *psDeviceNode;
PVRSRV_RGXDEV_INFO *psDevInfo;
IMG_UINT32 ui32FwVA;
IMG_UINT32 ui32FwPageSize;
IMG_UINT32 ui32OSID;
psDeviceNode = DIGetPrivData(psEntry);
if ((psDeviceNode == NULL) ||
(psDeviceNode->pvDevice == NULL) ||
(((PVRSRV_RGXDEV_INFO *)psDeviceNode->pvDevice)->psKernelMMUCtx == NULL))
{
/* The Kernel MMU context containing the Firmware mappings is not initialised */
return 0;
}
psDevInfo = psDeviceNode->pvDevice;
DIPrintf(psEntry, "+-----------------+------------------------+------------------------+--------------+\n"
"| Firmware | CPU | Device | PTE |\n"
"| Virtual Address | Physical Address | Physical Address | Flags |\n"
"+-----------------+------------------------+------------------------+ +\n");
#if defined(RGX_FEATURE_MIPS_BIT_MASK)
if (RGX_IS_FEATURE_SUPPORTED(psDevInfo, MIPS))
{
DIPrintf(psEntry, "| RI/XI = Read / Execution Inhibit |\n"
"| C = Cache Coherent |\n"
"| D = Dirty Page Table Entry |\n"
"| V = Valid Page Table Entry |\n"
"| G = Global Page Table Entry |\n"
"+-----------------+------------------------+------------------------+--------------+\n");
/* MIPS uses the same page size as the OS */
ui32FwPageSize = OSGetPageSize();
}
else
#endif
{
DIPrintf(psEntry, "| P = Pending Page Table Entry |\n"
"| PM = Parameter Manager Source |\n"
"| B = Bypass SLC |\n"
"| C = Cache Coherent |\n"
"| RW/RO = Device Access Rights |\n"
"| V = Valid Page Table Entry |\n"
"+-----------------+------------------------+------------------------+--------------+\n");
ui32FwPageSize = BIT(RGX_MMUCTRL_PAGE_4KB_RANGE_SHIFT);
}
for (ui32OSID = 0; ui32OSID < RGX_NUM_OS_SUPPORTED; ui32OSID++)
{
IMG_UINT32 ui32FwHeapBase = (IMG_UINT32) ((RGX_FIRMWARE_RAW_HEAP_BASE +
(ui32OSID * RGX_FIRMWARE_RAW_HEAP_SIZE)) & UINT_MAX);
IMG_UINT32 ui32FwHeapEnd = ui32FwHeapBase + (IMG_UINT32) (RGX_FIRMWARE_RAW_HEAP_SIZE & UINT_MAX);
DIPrintf(psEntry, "| OS ID %u |\n"
"+-----------------+------------------------+------------------------+--------------+\n", ui32OSID);
for (ui32FwVA = ui32FwHeapBase;
ui32FwVA < ui32FwHeapEnd;
ui32FwVA += ui32FwPageSize)
{
PVRSRV_RGXDEV_INFO *psDevInfo = (PVRSRV_RGXDEV_INFO*)psPVRSRVData->psDeviceNodeList->pvDevice;
return psDevInfo;
PVRSRV_ERROR eError;
IMG_UINT64 ui64PTE = 0U;
IMG_CPU_PHYADDR sCpuPA = {0U};
IMG_DEV_PHYADDR sDevPA = {0U};
eError = RGXGetFwMapping(psDevInfo, ui32FwVA, &sCpuPA, &sDevPA, &ui64PTE);
if (eError == PVRSRV_OK)
{
_DocumentFwMapping(psEntry, psDevInfo, ui32FwVA, sCpuPA, sDevPA, ui64PTE);
}
else if (eError != PVRSRV_ERROR_DEVICEMEM_NO_MAPPING)
{
PVR_LOG_ERROR(eError, "RGXGetFwMapping");
return -EIO;
}
}
DIPrintf(psEntry, "+-----------------+------------------------+------------------------+--------------+\n");
if (PVRSRV_VZ_MODE_IS(NATIVE))
{
break;
}
}
return NULL;
return 0;
}
#ifdef SUPPORT_FIRMWARE_GCOV
static void *_FirmwareGcovDIStart(OSDI_IMPL_ENTRY *psEntry, IMG_UINT64 *pui64Pos)
{
PVRSRV_RGXDEV_INFO *psDevInfo = getPsDevInfo(psEntry);
PVRSRV_DEVICE_NODE *psDeviceNode = DIGetPrivData(psEntry);
PVRSRV_RGXDEV_INFO *psDevInfo = psDeviceNode->pvDevice;
if (psDevInfo != NULL)
{
@@ -815,7 +960,8 @@ static void *_FirmwareGcovDIStart(OSDI_IMPL_ENTRY *psEntry, IMG_UINT64 *pui64Pos
static void _FirmwareGcovDIStop(OSDI_IMPL_ENTRY *psEntry, void *pvData)
{
PVRSRV_RGXDEV_INFO *psDevInfo = getPsDevInfo(psEntry);
PVRSRV_DEVICE_NODE *psDeviceNode = DIGetPrivData(psEntry);
PVRSRV_RGXDEV_INFO *psDevInfo = psDeviceNode->pvDevice;
PVR_UNREFERENCED_PARAMETER(pvData);
@@ -840,7 +986,8 @@ static void *_FirmwareGcovDINext(OSDI_IMPL_ENTRY *psEntry,
static int _FirmwareGcovDIShow(OSDI_IMPL_ENTRY *psEntry, void *pvData)
{
PVRSRV_RGXDEV_INFO *psDevInfo = getPsDevInfo(psEntry);
PVRSRV_DEVICE_NODE *psDeviceNode = DIGetPrivData(psEntry);
PVRSRV_RGXDEV_INFO *psDevInfo = psDeviceNode->pvDevice;
if (psDevInfo != NULL)
{
@@ -1225,35 +1372,22 @@ PVRSRV_ERROR DebugCommonInitDriver(void)
.pfnStop = _DebugStatusDIStop,
.pfnNext = _DebugStatusDINext,
.pfnShow = _DebugStatusDIShow,
.pfnWrite = DebugStatusSet
.pfnWrite = DebugStatusSet,
//'K' expected + Null terminator
.ui32WriteLenMax= ((1U)+1U)
};
eError = DICreateEntry("status", NULL, &sIterator, psPVRSRVData,
DI_ENTRY_TYPE_GENERIC, &gpsStatusDIEntry);
PVR_GOTO_IF_ERROR(eError, return_error_);
}
#ifdef SUPPORT_RGX
#ifdef SUPPORT_FIRMWARE_GCOV
{
DI_ITERATOR_CB sIterator = {
.pfnStart = _FirmwareGcovDIStart,
.pfnStop = _FirmwareGcovDIStop,
.pfnNext = _FirmwareGcovDINext,
.pfnShow = _FirmwareGcovDIShow
};
eError = DICreateEntry("firmware_gcov", NULL, &sIterator, psPVRSRVData,
DI_ENTRY_TYPE_GENERIC, &gpsFirmwareGcovDIEntry);
PVR_GOTO_IF_ERROR(eError, return_error_);
}
#endif /* SUPPORT_FIRMWARE_GCOV */
#endif /* SUPPORT_RGX */
#ifdef SUPPORT_VALIDATION
{
DI_ITERATOR_CB sIterator = {
.pfnShow = TestMemLeakDIShow,
.pfnWrite = TestMemLeakDISet
.pfnWrite = TestMemLeakDISet,
//Function only allows max 15 chars + Null terminator
.ui32WriteLenMax = ((15U)+1U)
};
eError = DICreateEntry("test_memleak", NULL, &sIterator, psPVRSRVData,
DI_ENTRY_TYPE_GENERIC, &gpsTestMemLeakDIEntry);
@@ -1265,7 +1399,9 @@ PVRSRV_ERROR DebugCommonInitDriver(void)
{
DI_ITERATOR_CB sIterator = {
.pfnShow = DebugLevelDIShow,
.pfnWrite = DebugLevelSet
.pfnWrite = DebugLevelSet,
//Max value of 255(3 char) + Null terminator
.ui32WriteLenMax =((3U)+1U)
};
eError = DICreateEntry("debug_level", NULL, &sIterator, NULL,
DI_ENTRY_TYPE_GENERIC, &gpsDebugLevelDIEntry);
@@ -1298,15 +1434,6 @@ void DebugCommonDeInitDriver(void)
}
#endif /* defined(SUPPORT_RGX) && !defined(NO_HARDWARE) */
#ifdef SUPPORT_RGX
#ifdef SUPPORT_FIRMWARE_GCOV
if (gpsFirmwareGcovDIEntry != NULL)
{
DIDestroyEntry(gpsFirmwareGcovDIEntry);
}
#endif /* SUPPORT_FIRMWARE_GCOV */
#endif /* SUPPORT_RGX */
#ifdef SUPPORT_VALIDATION
if (gpsTestMemLeakDIEntry != NULL)
{
@@ -1359,11 +1486,36 @@ PVRSRV_ERROR DebugCommonInitDevice(PVRSRV_DEVICE_NODE *psDeviceNode)
PVR_GOTO_IF_ERROR(eError, return_error_);
}
#ifdef SUPPORT_FIRMWARE_GCOV
{
DI_ITERATOR_CB sIterator = {
.pfnStart = _FirmwareGcovDIStart,
.pfnStop = _FirmwareGcovDIStop,
.pfnNext = _FirmwareGcovDINext,
.pfnShow = _FirmwareGcovDIShow
};
eError = DICreateEntry("firmware_gcov", psDebugInfo->psGroup, &sIterator,
psDeviceNode, DI_ENTRY_TYPE_GENERIC,
&psDebugInfo->psFWGCOVEntry);
PVR_GOTO_IF_ERROR(eError, return_error_);
}
#endif /* SUPPORT_FIRMWARE_GCOV */
{
DI_ITERATOR_CB sIterator = {.pfnShow = _FirmwareMappingsDIShow};
eError = DICreateEntry("firmware_mappings", psDebugInfo->psGroup, &sIterator,
psDeviceNode, DI_ENTRY_TYPE_GENERIC,
&psDebugInfo->psFWMappingsEntry);
PVR_GOTO_IF_ERROR(eError, return_error_);
}
#if defined(SUPPORT_VALIDATION) || defined(SUPPORT_RISCV_GDB)
{
DI_ITERATOR_CB sIterator = {
.pfnRead = _RiscvDmiRead,
.pfnWrite = _RiscvDmiWrite
.pfnWrite = _RiscvDmiWrite,
.ui32WriteLenMax = ((RISCV_DMI_SIZE)+1U)
};
eError = DICreateEntry("riscv_dmi", psDebugInfo->psGroup, &sIterator, psDeviceNode,
DI_ENTRY_TYPE_RANDOM_ACCESS, &psDebugInfo->psRiscvDmiDIEntry);
@@ -1377,7 +1529,9 @@ PVRSRV_ERROR DebugCommonInitDevice(PVRSRV_DEVICE_NODE *psDeviceNode)
DI_ITERATOR_CB sIterator = {
.pfnSeek = _RgxRegsSeek,
.pfnRead = _RgxRegsRead,
.pfnWrite = _RgxRegsWrite
.pfnWrite = _RgxRegsWrite,
//Max size of input binary data is 4 bytes (UINT32) or 8 bytes (UINT64)
.ui32WriteLenMax = ((8U)+1U)
};
eError = DICreateEntry("rgxregs", psDebugInfo->psGroup, &sIterator, psDeviceNode,
DI_ENTRY_TYPE_RANDOM_ACCESS, &psDebugInfo->psRGXRegsEntry);
@@ -1401,7 +1555,9 @@ PVRSRV_ERROR DebugCommonInitDevice(PVRSRV_DEVICE_NODE *psDeviceNode)
{
DI_ITERATOR_CB sIterator = {
.pfnShow = _DebugPowerDataDIShow,
.pfnWrite = PowerDataSet
.pfnWrite = PowerDataSet,
//Expects '0' or '1' plus Null terminator
.ui32WriteLenMax = ((1U)+1U)
};
eError = DICreateEntry("power_data", psDebugInfo->psGroup, &sIterator, psDeviceNode,
DI_ENTRY_TYPE_GENERIC, &psDebugInfo->psPowerDataEntry);
@@ -1453,6 +1609,20 @@ void DebugCommonDeInitDevice(PVRSRV_DEVICE_NODE *psDeviceNode)
psDebugInfo->psFWTraceEntry = NULL;
}
#ifdef SUPPORT_FIRMWARE_GCOV
if (psDebugInfo->psFWGCOVEntry != NULL)
{
DIDestroyEntry(psDebugInfo->psFWGCOVEntry);
psDebugInfo->psFWGCOVEntry = NULL;
}
#endif
if (psDebugInfo->psFWMappingsEntry != NULL)
{
DIDestroyEntry(psDebugInfo->psFWMappingsEntry);
psDebugInfo->psFWMappingsEntry = NULL;
}
#if defined(SUPPORT_VALIDATION) || defined(SUPPORT_RISCV_GDB)
if (psDebugInfo->psRiscvDmiDIEntry != NULL)
{

78
drivers/gpu/drm/img-rogue/device.h
View File

@@ -124,33 +124,6 @@ typedef struct _DEVICE_MEMORY_INFO_
DEVMEM_HEAP_BLUEPRINT *psDeviceMemoryHeap;
} DEVICE_MEMORY_INFO;
typedef struct _PG_HANDLE_
{
union
{
void *pvHandle;
IMG_UINT64 ui64Handle;
}u;
/* The allocation order is log2 value of the number of pages to allocate.
* As such this is a correspondingly small value. E.g, for order 4 we
* are talking 2^4 * PAGE_SIZE contiguous allocation.
* DevPxAlloc API does not need to support orders higher than 4.
*/
#if defined(SUPPORT_GPUVIRT_VALIDATION)
IMG_BYTE uiOrder; /* Order of the corresponding allocation */
IMG_BYTE uiOSid; /* OSid to use for allocation arena.
* Connection-specific. */
IMG_BYTE uiPad1,
uiPad2; /* Spare */
#else
IMG_BYTE uiOrder; /* Order of the corresponding allocation */
IMG_BYTE uiPad1,
uiPad2,
uiPad3; /* Spare */
#endif
} PG_HANDLE;
#define MMU_BAD_PHYS_ADDR (0xbadbad00badULL)
#define DUMMY_PAGE ("DUMMY_PAGE")
#define DEV_ZERO_PAGE ("DEV_ZERO_PAGE")
@@ -208,36 +181,6 @@ typedef enum _PVRSRV_DEVICE_DEBUG_DUMP_STATUS_
PVRSRV_DEVICE_DEBUG_DUMP_CAPTURE
} PVRSRV_DEVICE_DEBUG_DUMP_STATUS;
typedef struct _MMU_PX_SETUP_
{
#if defined(SUPPORT_GPUVIRT_VALIDATION)
PVRSRV_ERROR (*pfnDevPxAllocGPV)(struct _PVRSRV_DEVICE_NODE_ *psDevNode, size_t uiSize,
PG_HANDLE *psMemHandle, IMG_DEV_PHYADDR *psDevPAddr,
IMG_UINT32 ui32OSid, IMG_PID uiPid);
#endif
PVRSRV_ERROR (*pfnDevPxAlloc)(struct _PVRSRV_DEVICE_NODE_ *psDevNode, size_t uiSize,
PG_HANDLE *psMemHandle, IMG_DEV_PHYADDR *psDevPAddr,
IMG_PID uiPid);
void (*pfnDevPxFree)(struct _PVRSRV_DEVICE_NODE_ *psDevNode, PG_HANDLE *psMemHandle);
PVRSRV_ERROR (*pfnDevPxMap)(struct _PVRSRV_DEVICE_NODE_ *psDevNode, PG_HANDLE *pshMemHandle,
size_t uiSize, IMG_DEV_PHYADDR *psDevPAddr,
void **pvPtr);
void (*pfnDevPxUnMap)(struct _PVRSRV_DEVICE_NODE_ *psDevNode,
PG_HANDLE *psMemHandle, void *pvPtr);
PVRSRV_ERROR (*pfnDevPxClean)(struct _PVRSRV_DEVICE_NODE_ *psDevNode,
PG_HANDLE *pshMemHandle,
IMG_UINT32 uiOffset,
IMG_UINT32 uiLength);
IMG_UINT32 uiMMUPxLog2AllocGran;
RA_ARENA *psPxRA;
} MMU_PX_SETUP;
#ifndef DI_GROUP_DEFINED
#define DI_GROUP_DEFINED
typedef struct DI_GROUP DI_GROUP;
@@ -253,6 +196,10 @@ typedef struct _PVRSRV_DEVICE_DEBUG_INFO_
DI_ENTRY *psDumpDebugEntry;
#ifdef SUPPORT_RGX
DI_ENTRY *psFWTraceEntry;
#ifdef SUPPORT_FIRMWARE_GCOV
DI_ENTRY *psFWGCOVEntry;
#endif
DI_ENTRY *psFWMappingsEntry;
#if defined(SUPPORT_VALIDATION) || defined(SUPPORT_RISCV_GDB)
DI_ENTRY *psRiscvDmiDIEntry;
IMG_UINT64 ui64RiscvDmi;
@@ -325,7 +272,7 @@ typedef struct _PVRSRV_DEVICE_NODE_
/* Device specific MMU firmware attributes, used only in some devices */
MMU_DEVICEATTRIBS *psFirmwareMMUDevAttrs;
MMU_PX_SETUP sDevMMUPxSetup;
PHYS_HEAP *psMMUPhysHeap;
/* lock for power state transitions */
POS_LOCK hPowerLock;
@@ -431,8 +378,6 @@ typedef struct _PVRSRV_DEVICE_NODE_
#if defined(SUPPORT_GPUVIRT_VALIDATION)
RA_ARENA *psOSSharedArena;
RA_ARENA *psOSidSubArena[GPUVIRT_VALIDATION_NUM_OS];
/* Number of supported OSid for this device node given available memory */
IMG_UINT32 ui32NumOSId;
#endif
/* FW_MAIN, FW_CONFIG and FW_GUEST heaps. Should be part of registered heaps? */
@@ -455,9 +400,11 @@ typedef struct _PVRSRV_DEVICE_NODE_
PHYS_HEAP *apsPhysHeap[PVRSRV_PHYS_HEAP_LAST];
IMG_UINT32 ui32UserAllocHeapCount;
/* RA reserved for storing the MMU mappings of firmware.
* The memory backing up this RA must persist between driver or OS reboots */
RA_ARENA *psFwMMUReservedMemArena;
#if defined(SUPPORT_AUTOVZ)
/* Phys Heap reserved for storing the MMU mappings of firmware.
* The memory backing up this Phys Heap must persist between driver or OS reboots */
PHYS_HEAP *psFwMMUReservedPhysHeap;
#endif
/* Flag indicating if the firmware has been initialised during the
* 1st boot of the Host driver according to the AutoVz life-cycle. */
@@ -507,6 +454,7 @@ typedef struct _PVRSRV_DEVICE_NODE_
IMG_HANDLE hCmdCompNotify;
IMG_HANDLE hDbgReqNotify;
IMG_HANDLE hAppHintDbgReqNotify;
IMG_HANDLE hPhysHeapDbgReqNotify;
PVRSRV_DEF_PAGE sDummyPage;
PVRSRV_DEF_PAGE sDevZeroPage;
@@ -551,11 +499,13 @@ typedef struct _PVRSRV_DEVICE_NODE_
#endif
#if defined(SUPPORT_VALIDATION)
POS_LOCK hValidationLock;
POS_LOCK hValidationLock;
#endif
/* Members for linking which connections are open on this device */
POS_LOCK hConnectionsLock; /*!< Lock protecting sConnections */
DLLIST_NODE sConnections; /*!< The list of currently active connection objects for this device node */
#if defined(PVRSRV_DEBUG_LISR_EXECUTION)
LISR_EXECUTION_INFO sLISRExecutionInfo; /*!< Information about the last execution of the LISR */
IMG_UINT64 ui64nLISR; /*!< Number of LISR calls seen */

107
drivers/gpu/drm/img-rogue/devicemem.c
View File

@@ -81,10 +81,12 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#include "pvr_ricommon.h"
#include "pvrsrv_apphint.h"
#include "oskm_apphint.h"
#include "srvcore.h"
#if defined(__linux__)
#include "linux/kernel.h"
#endif
#else
#include "srvcore_intern.h"
#include "rgxdefs.h"
#endif
@@ -108,8 +110,7 @@ IMG_UINT64 _GetPremappedVA(PMR *psPMR, PVRSRV_DEVICE_NODE *psDevNode)
IMG_DEV_PHYADDR sDevAddr;
IMG_BOOL bValid;
PVRSRV_PHYS_HEAP eFirstHeap = (PVRSRV_VZ_MODE_IS(GUEST) ? PVRSRV_PHYS_HEAP_FW_CONFIG : PVRSRV_PHYS_HEAP_FW_MAIN);
PHYS_HEAP *psPhysHeap = psDevNode->apsPhysHeap[eFirstHeap];
PHYS_HEAP *psPhysHeap = psDevNode->apsPhysHeap[PVRSRV_PHYS_HEAP_FW_MAIN];
IMG_DEV_PHYADDR sHeapAddr;
eError = PhysHeapGetDevPAddr(psPhysHeap, &sHeapAddr);
@@ -881,8 +882,10 @@ DevmemDestroyContext(DEVMEM_CONTEXT *psCtx)
goto e1;
}
eError = BridgeDevmemIntCtxDestroy(GetBridgeHandle(psCtx->hDevConnection),
psCtx->hDevMemServerContext);
eError = DestroyServerResource(psCtx->hDevConnection,
NULL,
BridgeDevmemIntCtxDestroy,
psCtx->hDevMemServerContext);
if (bDoCheck)
{
PVR_LOG_GOTO_IF_ERROR(eError, "BridgeDevMemIntCtxDestroy", e1);
@@ -1293,8 +1296,11 @@ DevmemDestroyHeap(DEVMEM_HEAP *psHeap)
}
}
eError = BridgeDevmemIntHeapDestroy(GetBridgeHandle(psHeap->psCtx->hDevConnection),
psHeap->hDevMemServerHeap);
eError = DestroyServerResource(psHeap->psCtx->hDevConnection,
NULL,
BridgeDevmemIntHeapDestroy,
psHeap->hDevMemServerHeap);
#if defined(PVRSRV_FORCE_UNLOAD_IF_BAD_STATE)
if (bDoCheck)
#endif
@@ -1361,27 +1367,12 @@ DevmemSubAllocateAndMap(IMG_UINT8 uiPreAllocMultiplier,
fail_map:
DevmemFree(*ppsMemDescPtr);
fail_alloc:
ppsMemDescPtr = NULL;
*ppsMemDescPtr = NULL;
PVR_ASSERT(eError != PVRSRV_OK);
return eError;
}
static INLINE void _MemSet(void *pvMem,
IMG_UINT8 uiPattern,
IMG_DEVMEM_SIZE_T uiSize,
PVRSRV_MEMALLOCFLAGS_T uiFlags)
{
if (PVRSRV_CHECK_CPU_UNCACHED(uiFlags))
{
OSDeviceMemSet(pvMem, uiPattern, uiSize);
}
else
{
/* it's safe to use OSCachedMemSet() for cached and wc memory */
OSCachedMemSet(pvMem, uiPattern, uiSize);
}
}
IMG_INTERNAL PVRSRV_ERROR
DevmemSubAllocate(IMG_UINT8 uiPreAllocMultiplier,
DEVMEM_HEAP *psHeap,
@@ -1524,6 +1515,10 @@ DevmemSubAllocate(IMG_UINT8 uiPreAllocMultiplier,
psImport,
uiSize);
#if defined(DEBUG)
DevmemMemDescSetPoF(psMemDesc, uiFlags);
#endif
bImportClean = ((uiProperties & DEVMEM_PROPERTIES_IMPORT_IS_CLEAN) != 0);
/* Zero the memory */
@@ -1546,7 +1541,7 @@ DevmemSubAllocate(IMG_UINT8 uiPreAllocMultiplier,
*/
PVR_ASSERT(uiSize < IMG_UINT32_MAX);
_MemSet(pvAddr, 0, uiSize, uiFlags);
DevmemCPUMemSet(pvAddr, 0, uiSize, uiFlags);
#if defined(PDUMP)
DevmemPDumpLoadZeroMem(psMemDesc, 0, uiSize, PDUMP_FLAGS_CONTINUOUS);
@@ -1565,7 +1560,7 @@ DevmemSubAllocate(IMG_UINT8 uiPreAllocMultiplier,
eError = DevmemAcquireCpuVirtAddr(psMemDesc, &pvAddr);
PVR_GOTO_IF_ERROR(eError, failMaintenance);
_MemSet(pvAddr, PVRSRV_POISON_ON_ALLOC_VALUE, uiSize, uiFlags);
DevmemCPUMemSet(pvAddr, PVRSRV_POISON_ON_ALLOC_VALUE, uiSize, uiFlags);
bPoisonOnAlloc = IMG_TRUE;
}
@@ -1574,8 +1569,6 @@ DevmemSubAllocate(IMG_UINT8 uiPreAllocMultiplier,
/* Flush or invalidate */
if (bCPUCached && !bImportClean && (bZero || bCPUCleanFlag || bPoisonOnAlloc))
{
/* BridgeCacheOpQueue _may_ be deferred so use BridgeCacheOpExec
to ensure this cache maintenance is actioned immediately */
eError = BridgeCacheOpExec (GetBridgeHandle(psMemDesc->psImport->hDevConnection),
psMemDesc->psImport->hPMR,
(IMG_UINT64)(uintptr_t)
@@ -1695,6 +1688,10 @@ DevmemAllocateExportable(SHARED_DEV_CONNECTION hDevConnection,
psImport,
uiSize);
#if defined(DEBUG)
DevmemMemDescSetPoF(psMemDesc, uiFlags);
#endif
*ppsMemDescPtr = psMemDesc;
/* copy the allocation descriptive name and size so it can be passed to DevicememHistory when
@@ -1795,6 +1792,10 @@ DevmemAllocateSparse(SHARED_DEV_CONNECTION hDevConnection,
psImport,
uiSize);
#if defined(DEBUG)
DevmemMemDescSetPoF(psMemDesc, uiFlags);
#endif
/* copy the allocation descriptive name and size so it can be passed to DevicememHistory when
* the allocation gets mapped/unmapped
*/
@@ -1858,7 +1859,10 @@ IMG_INTERNAL PVRSRV_ERROR
DevmemUnmakeLocalImportHandle(SHARED_DEV_CONNECTION hDevConnection,
IMG_HANDLE hLocalImportHandle)
{
return BridgePMRUnmakeLocalImportHandle(GetBridgeHandle(hDevConnection), hLocalImportHandle);
return DestroyServerResource(hDevConnection,
NULL,
BridgePMRUnmakeLocalImportHandle,
hLocalImportHandle);
}
/*****************************************************************************
@@ -1925,8 +1929,10 @@ _Mapping_Unexport(DEVMEM_IMPORT *psImport,
PVR_ASSERT (psImport != NULL);
eError = BridgePMRUnexportPMR(GetBridgeHandle(psImport->hDevConnection),
hPMRExportHandle);
eError = DestroyServerResource(psImport->hDevConnection,
NULL,
BridgePMRUnexportPMR,
hPMRExportHandle);
PVR_ASSERT(eError == PVRSRV_OK);
}
@@ -2553,45 +2559,12 @@ DevmemAcquireCpuVirtAddr(DEVMEM_MEMDESC *psMemDesc,
void **ppvCpuVirtAddr)
{
PVRSRV_ERROR eError;
DEVMEM_PROPERTIES_T uiProperties;
PVR_ASSERT(psMemDesc != NULL);
PVR_ASSERT(ppvCpuVirtAddr != NULL);
uiProperties = GetImportProperties(psMemDesc->psImport);
if (uiProperties &
(DEVMEM_PROPERTIES_UNPINNED | DEVMEM_PROPERTIES_SECURE))
{
#if defined(SUPPORT_SECURITY_VALIDATION)
if (uiProperties & DEVMEM_PROPERTIES_SECURE)
{
PVR_DPF((PVR_DBG_WARNING,
"%s: Allocation is a secure buffer. "
"It should not be possible to map to CPU, but for security "
"validation this will be allowed for testing purposes, "
"as long as the buffer is pinned.",
__func__));
}
if (uiProperties & DEVMEM_PROPERTIES_UNPINNED)
#endif
{
PVR_DPF((PVR_DBG_ERROR,
"%s: Allocation is currently unpinned or a secure buffer. "
"Not possible to map to CPU!",
__func__));
return PVRSRV_ERROR_INVALID_MAP_REQUEST;
}
}
if (uiProperties & DEVMEM_PROPERTIES_NO_CPU_MAPPING)
{
PVR_DPF((PVR_DBG_ERROR,
"%s: CPU Mapping is not possible on this allocation!",
__func__));
return PVRSRV_ERROR_INVALID_MAP_REQUEST;
}
eError = DevmemCPUMapCheckImportProperties(psMemDesc);
PVR_LOG_RETURN_IF_ERROR(eError, "DevmemCPUMapCheckImportProperties");
OSLockAcquire(psMemDesc->sCPUMemDesc.hLock);
DEVMEM_REFCOUNT_PRINT("%s (%p) %d->%d",
@@ -2758,7 +2731,7 @@ DevmemGetReservation(DEVMEM_MEMDESC *psMemDesc,
* memdescs of buffers allocated in the FW memory context
* that is created in the Server
*/
PVRSRV_ERROR
void
DevmemGetPMRData(DEVMEM_MEMDESC *psMemDesc,
IMG_HANDLE *phPMR,
IMG_DEVMEM_OFFSET_T *puiPMROffset)
@@ -2771,8 +2744,6 @@ DevmemGetPMRData(DEVMEM_MEMDESC *psMemDesc,
PVR_ASSERT(psImport);
*phPMR = psImport->hPMR;
return PVRSRV_OK;
}
#if defined(__KERNEL__)

2
drivers/gpu/drm/img-rogue/devicemem.h
View File

@@ -636,7 +636,7 @@ PVRSRV_ERROR
DevmemGetReservation(DEVMEM_MEMDESC *psMemDesc,
IMG_HANDLE *hReservation);
IMG_INTERNAL PVRSRV_ERROR
IMG_INTERNAL void
DevmemGetPMRData(DEVMEM_MEMDESC *psMemDesc,
IMG_HANDLE *hPMR,
IMG_DEVMEM_OFFSET_T *puiPMROffset);

172
drivers/gpu/drm/img-rogue/devicemem_server.c
View File

@@ -64,6 +64,8 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#include "pvrsrv.h" /* for PVRSRVGetPVRSRVData() */
#define DEVMEMCTX_FLAGS_FAULT_ADDRESS_AVAILABLE (1 << 0)
#define DEVMEMHEAP_REFCOUNT_MIN 1
#define DEVMEMHEAP_REFCOUNT_MAX IMG_INT32_MAX
struct _DEVMEMINT_CTX_
{
@@ -111,7 +113,7 @@ struct _DEVMEMINT_HEAP_
{
struct _DEVMEMINT_CTX_ *psDevmemCtx;
IMG_UINT32 uiLog2PageSize;
ATOMIC_T hRefCount;
ATOMIC_T uiRefCount;
};
struct _DEVMEMINT_RESERVATION_
@@ -193,11 +195,21 @@ static INLINE void DevmemIntCtxRelease(DEVMEMINT_CTX *psDevmemCtx)
/*************************************************************************/ /*!
@Function DevmemIntHeapAcquire
@Description Acquire a reference to the provided device memory heap.
@Return None
@Return IMG_TRUE if referenced and IMG_FALSE in case of error
*/ /**************************************************************************/
static INLINE void DevmemIntHeapAcquire(DEVMEMINT_HEAP *psDevmemHeap)
static INLINE IMG_BOOL DevmemIntHeapAcquire(DEVMEMINT_HEAP *psDevmemHeap)
{
OSAtomicIncrement(&psDevmemHeap->hRefCount);
IMG_BOOL bSuccess = OSAtomicAddUnless(&psDevmemHeap->uiRefCount, 1,
DEVMEMHEAP_REFCOUNT_MAX);
if (!bSuccess)
{
PVR_DPF((PVR_DBG_ERROR, "%s(): Failed to acquire the device memory "
"heap, reference count has overflowed.", __func__));
return IMG_FALSE;
}
return IMG_TRUE;
}
/*************************************************************************/ /*!
@@ -209,7 +221,14 @@ static INLINE void DevmemIntHeapAcquire(DEVMEMINT_HEAP *psDevmemHeap)
*/ /**************************************************************************/
static INLINE void DevmemIntHeapRelease(DEVMEMINT_HEAP *psDevmemHeap)
{
OSAtomicDecrement(&psDevmemHeap->hRefCount);
IMG_BOOL bSuccess = OSAtomicSubtractUnless(&psDevmemHeap->uiRefCount, 1,
DEVMEMHEAP_REFCOUNT_MIN);
if (!bSuccess)
{
PVR_DPF((PVR_DBG_ERROR, "%s(): Failed to acquire the device memory "
"heap, reference count has underflowed.", __func__));
}
}
PVRSRV_ERROR
@@ -495,7 +514,7 @@ DevmemIntHeapCreate(DEVMEMINT_CTX *psDevmemCtx,
DevmemIntCtxAcquire(psDevmemHeap->psDevmemCtx);
OSAtomicWrite(&psDevmemHeap->hRefCount, 1);
OSAtomicWrite(&psDevmemHeap->uiRefCount, 1);
psDevmemHeap->uiLog2PageSize = uiLog2DataPageSize;
@@ -603,6 +622,9 @@ DevmemIntMapPages(DEVMEMINT_RESERVATION *psReservation,
{
PVRSRV_ERROR eError;
PVR_LOG_RETURN_IF_INVALID_PARAM((ui32PageCount < PMR_MAX_SUPPORTED_PAGE_COUNT), "ui32PageCount");
PVR_LOG_RETURN_IF_INVALID_PARAM((ui32PhysicalPgOffset < PMR_MAX_SUPPORTED_PAGE_COUNT), "ui32PhysicalPgOffset");
if (psReservation->psDevmemHeap->uiLog2PageSize > PMR_GetLog2Contiguity(psPMR))
{
PVR_DPF((PVR_DBG_ERROR,
@@ -632,6 +654,8 @@ DevmemIntUnmapPages(DEVMEMINT_RESERVATION *psReservation,
IMG_DEV_VIRTADDR sDevVAddrBase,
IMG_UINT32 ui32PageCount)
{
PVR_LOG_RETURN_IF_INVALID_PARAM((ui32PageCount < PMR_MAX_SUPPORTED_PAGE_COUNT), "ui32PageCount");
/* Unmap the pages and mark them invalid in the MMU PTE */
MMU_UnmapPages(psReservation->psDevmemHeap->psDevmemCtx->psMMUContext,
0,
@@ -674,13 +698,21 @@ DevmemIntMapPMR(DEVMEMINT_HEAP *psDevmemHeap,
__func__,
uiLog2HeapContiguity,
PMR_GetLog2Contiguity(psPMR) ));
PVR_GOTO_WITH_ERROR(eError, PVRSRV_ERROR_INVALID_PARAMS, e0);
PVR_GOTO_WITH_ERROR(eError, PVRSRV_ERROR_INVALID_PARAMS, ErrorReturnError);
}
psDevNode = psDevmemHeap->psDevmemCtx->psDevNode;
/* Don't bother with refcount on reservation, as a reservation
only ever holds one mapping, so we directly increment the
refcount on the heap instead */
if (!DevmemIntHeapAcquire(psDevmemHeap))
{
PVR_GOTO_WITH_ERROR(eError, PVRSRV_ERROR_REFCOUNT_OVERFLOW, ErrorReturnError);
}
/* allocate memory to record the mapping info */
psMapping = OSAllocMem(sizeof(*psMapping));
PVR_LOG_GOTO_IF_NOMEM(psMapping, eError, e0);
PVR_LOG_GOTO_IF_NOMEM(psMapping, eError, ErrorUnreference);
uiAllocationSize = psReservation->uiLength;
@@ -688,7 +720,7 @@ DevmemIntMapPMR(DEVMEMINT_HEAP *psDevmemHeap,
PVR_ASSERT((IMG_DEVMEM_SIZE_T) ui32NumDevPages << uiLog2HeapContiguity == uiAllocationSize);
eError = PMRLockSysPhysAddresses(psPMR);
PVR_GOTO_IF_ERROR(eError, e2);
PVR_GOTO_IF_ERROR(eError, ErrorFreeMapping);
sAllocationDevVAddr = psReservation->sBase;
@@ -731,7 +763,7 @@ DevmemIntMapPMR(DEVMEMINT_HEAP *psDevmemHeap,
uiInitValue,
pszPageName,
IMG_TRUE);
PVR_GOTO_IF_ERROR(eError, e3);
PVR_GOTO_IF_ERROR(eError, ErrorUnlockPhysAddr);
}
/* N.B. We pass mapping permission flags to MMU_MapPages and let
@@ -744,7 +776,7 @@ DevmemIntMapPMR(DEVMEMINT_HEAP *psDevmemHeap,
ui32NumDevPages,
NULL,
uiLog2HeapContiguity);
PVR_GOTO_IF_ERROR(eError, e4);
PVR_GOTO_IF_ERROR(eError, ErrorFreeDefBackingPage);
}
else
{
@@ -754,22 +786,18 @@ DevmemIntMapPMR(DEVMEMINT_HEAP *psDevmemHeap,
(IMG_DEVMEM_SIZE_T) ui32NumDevPages << uiLog2HeapContiguity,
uiMapFlags,
uiLog2HeapContiguity);
PVR_GOTO_IF_ERROR(eError, e3);
PVR_GOTO_IF_ERROR(eError, ErrorUnlockPhysAddr);
}
psMapping->psReservation = psReservation;
psMapping->uiNumPages = ui32NumDevPages;
psMapping->psPMR = psPMR;
/* Don't bother with refcount on reservation, as a reservation
only ever holds one mapping, so we directly increment the
refcount on the heap instead */
DevmemIntHeapAcquire(psMapping->psReservation->psDevmemHeap);
*ppsMappingPtr = psMapping;
return PVRSRV_OK;
e4:
ErrorFreeDefBackingPage:
if (bNeedBacking)
{
/*if the mapping failed, the allocated dummy ref count need
@@ -778,18 +806,24 @@ e4:
psDefPage,
pszPageName);
}
e3:
ErrorUnlockPhysAddr:
{
PVRSRV_ERROR eError1=PVRSRV_OK;
PVRSRV_ERROR eError1 = PVRSRV_OK;
eError1 = PMRUnlockSysPhysAddresses(psPMR);
PVR_LOG_IF_ERROR(eError1, "PMRUnlockSysPhysAddresses");
*ppsMappingPtr = NULL;
}
e2:
ErrorFreeMapping:
OSFreeMem(psMapping);
e0:
ErrorUnreference:
/* if fails there's not much to do (the function will print an error) */
DevmemIntHeapRelease(psDevmemHeap);
ErrorReturnError:
PVR_ASSERT (eError != PVRSRV_OK);
return eError;
}
@@ -851,14 +885,13 @@ DevmemIntUnmapPMR(DEVMEMINT_MAPPING *psMapping)
psMapping->psReservation->psDevmemHeap->uiLog2PageSize);
}
eError = PMRUnlockSysPhysAddresses(psMapping->psPMR);
PVR_ASSERT(eError == PVRSRV_OK);
/* Don't bother with refcount on reservation, as a reservation
only ever holds one mapping, so we directly decrement the
refcount on the heap instead */
/* Don't bother with refcount on reservation, as a reservation only ever
* holds one mapping, so we directly decrement the refcount on the heap
* instead.
* Function will print an error if the heap could not be unreferenced. */
DevmemIntHeapRelease(psDevmemHeap);
OSFreeMem(psMapping);
@@ -876,9 +909,15 @@ DevmemIntReserveRange(DEVMEMINT_HEAP *psDevmemHeap,
PVRSRV_ERROR eError;
DEVMEMINT_RESERVATION *psReservation;
if (!DevmemIntHeapAcquire(psDevmemHeap))
{
PVR_GOTO_WITH_ERROR(eError, PVRSRV_ERROR_REFCOUNT_OVERFLOW,
ErrorReturnError);
}
/* allocate memory to record the reservation info */
psReservation = OSAllocMem(sizeof(*psReservation));
PVR_LOG_GOTO_IF_NOMEM(psReservation, eError, e0);
PVR_LOG_GOTO_IF_NOMEM(psReservation, eError, ErrorUnreference);
psReservation->sBase = sAllocationDevVAddr;
psReservation->uiLength = uiAllocationSize;
@@ -890,14 +929,12 @@ DevmemIntReserveRange(DEVMEMINT_HEAP *psDevmemHeap,
0, /* alignment is n/a since we supply devvaddr */
&sAllocationDevVAddr,
psDevmemHeap->uiLog2PageSize);
PVR_GOTO_IF_ERROR(eError, e1);
PVR_GOTO_IF_ERROR(eError, ErrorFreeReservation);
/* since we supplied the virt addr, MMU_Alloc shouldn't have
chosen a new one for us */
PVR_ASSERT(sAllocationDevVAddr.uiAddr == psReservation->sBase.uiAddr);
DevmemIntHeapAcquire(psDevmemHeap);
psReservation->psDevmemHeap = psDevmemHeap;
*ppsReservationPtr = psReservation;
@@ -907,10 +944,14 @@ DevmemIntReserveRange(DEVMEMINT_HEAP *psDevmemHeap,
* error exit paths follow
*/
e1:
ErrorFreeReservation:
OSFreeMem(psReservation);
e0:
ErrorUnreference:
/* if fails there's not much to do (the function will print an error) */
DevmemIntHeapRelease(psDevmemHeap);
ErrorReturnError:
PVR_ASSERT(eError != PVRSRV_OK);
return eError;
}
@@ -927,22 +968,27 @@ DevmemIntUnreserveRange(DEVMEMINT_RESERVATION *psReservation)
uiLength,
uiLog2DataPageSize);
/* Don't bother with refcount on reservation, as a reservation only ever
* holds one mapping, so we directly decrement the refcount on the heap
* instead.
* Function will print an error if the heap could not be unreferenced. */
DevmemIntHeapRelease(psReservation->psDevmemHeap);
OSFreeMem(psReservation);
return PVRSRV_OK;
return PVRSRV_OK;
}
PVRSRV_ERROR
DevmemIntHeapDestroy(DEVMEMINT_HEAP *psDevmemHeap)
{
if (OSAtomicRead(&psDevmemHeap->hRefCount) != 1)
if (OSAtomicRead(&psDevmemHeap->uiRefCount) != DEVMEMHEAP_REFCOUNT_MIN)
{
PVR_DPF((PVR_DBG_ERROR, "BUG! %s called but has too many references (%d) "
"which probably means allocations have been made from the heap and not freed",
__func__,
OSAtomicRead(&psDevmemHeap->hRefCount)));
"which probably means reservations & mappings have been made from "
"the heap and not freed", __func__,
OSAtomicRead(&psDevmemHeap->uiRefCount)));
/*
* Try again later when you've freed all the memory
@@ -958,7 +1004,7 @@ DevmemIntHeapDestroy(DEVMEMINT_HEAP *psDevmemHeap)
return PVRSRV_ERROR_RETRY;
}
PVR_ASSERT(OSAtomicRead(&psDevmemHeap->hRefCount) == 1);
PVR_ASSERT(OSAtomicRead(&psDevmemHeap->uiRefCount) == DEVMEMHEAP_REFCOUNT_MIN);
DevmemIntCtxRelease(psDevmemHeap->psDevmemCtx);
@@ -1660,54 +1706,6 @@ DevmemIntPDumpSaveToFileVirtual(DEVMEMINT_CTX *psDevmemCtx,
return PVRSRV_OK;
}
PVRSRV_ERROR
DevmemIntPDumpBitmap(CONNECTION_DATA * psConnection,
PVRSRV_DEVICE_NODE *psDeviceNode,
IMG_CHAR *pszFileName,
IMG_UINT32 ui32FileOffset,
IMG_UINT32 ui32Width,
IMG_UINT32 ui32Height,
IMG_UINT32 ui32StrideInBytes,
IMG_DEV_VIRTADDR sDevBaseAddr,
DEVMEMINT_CTX *psDevMemContext,
IMG_UINT32 ui32Size,
PDUMP_PIXEL_FORMAT ePixelFormat,
IMG_UINT32 ui32AddrMode,
IMG_UINT32 ui32PDumpFlags)
{
IMG_UINT32 ui32ContextID;
PVRSRV_ERROR eError;
PVR_UNREFERENCED_PARAMETER(psConnection);
eError = MMU_AcquirePDumpMMUContext(psDevMemContext->psMMUContext, &ui32ContextID, ui32PDumpFlags);
if (eError != PVRSRV_OK)
{
PVR_LOG_ERROR(eError, "MMU_AcquirePDumpMMUContext");
return PVRSRV_ERROR_FAILED_TO_ALLOC_MMUCONTEXT_ID;
}
eError = PDumpBitmapKM(psDeviceNode,
pszFileName,
ui32FileOffset,
ui32Width,
ui32Height,
ui32StrideInBytes,
sDevBaseAddr,
ui32ContextID,
ui32Size,
ePixelFormat,
ui32AddrMode,
ui32PDumpFlags);
/* Don't care about return value */
MMU_ReleasePDumpMMUContext(psDevMemContext->psMMUContext, ui32PDumpFlags);
return eError;
}
PVRSRV_ERROR
DevmemIntPDumpImageDescriptor(CONNECTION_DATA * psConnection,
PVRSRV_DEVICE_NODE *psDeviceNode,

49
drivers/gpu/drm/img-rogue/devicemem_server.h
View File

@@ -478,21 +478,6 @@ DevmemIntPDumpSaveToFileVirtual(DEVMEMINT_CTX *psDevmemCtx,
IMG_UINT32
DevmemIntMMUContextID(DEVMEMINT_CTX *psDevMemContext);
PVRSRV_ERROR
DevmemIntPDumpBitmap(CONNECTION_DATA * psConnection,
PVRSRV_DEVICE_NODE *psDeviceNode,
IMG_CHAR *pszFileName,
IMG_UINT32 ui32FileOffset,
IMG_UINT32 ui32Width,
IMG_UINT32 ui32Height,
IMG_UINT32 ui32StrideInBytes,
IMG_DEV_VIRTADDR sDevBaseAddr,
DEVMEMINT_CTX *psDevMemContext,
IMG_UINT32 ui32Size,
PDUMP_PIXEL_FORMAT ePixelFormat,
IMG_UINT32 ui32AddrMode,
IMG_UINT32 ui32PDumpFlags);
PVRSRV_ERROR
DevmemIntPDumpImageDescriptor(CONNECTION_DATA * psConnection,
PVRSRV_DEVICE_NODE *psDeviceNode,
@@ -550,40 +535,6 @@ DevmemIntPDumpSaveToFileVirtual(DEVMEMINT_CTX *psDevmemCtx,
return PVRSRV_OK;
}
#ifdef INLINE_IS_PRAGMA
#pragma inline(DevmemIntPDumpBitmap)
#endif
static INLINE PVRSRV_ERROR
DevmemIntPDumpBitmap(CONNECTION_DATA * psConnection,
PVRSRV_DEVICE_NODE *psDeviceNode,
IMG_CHAR *pszFileName,
IMG_UINT32 ui32FileOffset,
IMG_UINT32 ui32Width,
IMG_UINT32 ui32Height,
IMG_UINT32 ui32StrideInBytes,
IMG_DEV_VIRTADDR sDevBaseAddr,
DEVMEMINT_CTX *psDevMemContext,
IMG_UINT32 ui32Size,
PDUMP_PIXEL_FORMAT ePixelFormat,
IMG_UINT32 ui32AddrMode,
IMG_UINT32 ui32PDumpFlags)
{
PVR_UNREFERENCED_PARAMETER(psConnection);
PVR_UNREFERENCED_PARAMETER(psDeviceNode);
PVR_UNREFERENCED_PARAMETER(pszFileName);
PVR_UNREFERENCED_PARAMETER(ui32FileOffset);
PVR_UNREFERENCED_PARAMETER(ui32Width);
PVR_UNREFERENCED_PARAMETER(ui32Height);
PVR_UNREFERENCED_PARAMETER(ui32StrideInBytes);
PVR_UNREFERENCED_PARAMETER(sDevBaseAddr);
PVR_UNREFERENCED_PARAMETER(psDevMemContext);
PVR_UNREFERENCED_PARAMETER(ui32Size);
PVR_UNREFERENCED_PARAMETER(ePixelFormat);
PVR_UNREFERENCED_PARAMETER(ui32AddrMode);
PVR_UNREFERENCED_PARAMETER(ui32PDumpFlags);
return PVRSRV_OK;
}
#ifdef INLINE_IS_PRAGMA
#pragma inline(DevmemIntPDumpImageDescriptor)
#endif

16
drivers/gpu/drm/img-rogue/devicemem_server_utils.h
View File

@@ -68,11 +68,7 @@ static INLINE PVRSRV_ERROR DevmemCPUCacheMode(PVRSRV_DEVICE_NODE *psDeviceNode,
break;
case PVRSRV_MEMALLOCFLAG_CPU_CACHE_INCOHERENT:
#if defined(SAFETY_CRITICAL_BUILD)
ui32Ret = PVRSRV_MEMALLOCFLAG_CPU_UNCACHED_WC;
#else
ui32Ret = PVRSRV_MEMALLOCFLAG_CPU_CACHED;
#endif
break;
case PVRSRV_MEMALLOCFLAG_CPU_CACHE_COHERENT:
@@ -90,11 +86,7 @@ static INLINE PVRSRV_ERROR DevmemCPUCacheMode(PVRSRV_DEVICE_NODE *psDeviceNode,
}
else
{
#if defined(SAFETY_CRITICAL_BUILD)
ui32Ret = PVRSRV_MEMALLOCFLAG_CPU_UNCACHED_WC;
#else
ui32Ret = PVRSRV_MEMALLOCFLAG_CPU_CACHED;
#endif
}
break;
@@ -136,11 +128,7 @@ static INLINE PVRSRV_ERROR DevmemDeviceCacheMode(PVRSRV_DEVICE_NODE *psDeviceNod
break;
case PVRSRV_MEMALLOCFLAG_GPU_CACHE_INCOHERENT:
#if defined(SAFETY_CRITICAL_BUILD)
ui32Ret = PVRSRV_MEMALLOCFLAG_GPU_UNCACHED_WC;
#else
ui32Ret = PVRSRV_MEMALLOCFLAG_GPU_CACHED;
#endif
break;
case PVRSRV_MEMALLOCFLAG_GPU_CACHE_COHERENT:
@@ -158,11 +146,7 @@ static INLINE PVRSRV_ERROR DevmemDeviceCacheMode(PVRSRV_DEVICE_NODE *psDeviceNod
}
else
{
#if defined(SAFETY_CRITICAL_BUILD)
ui32Ret = PVRSRV_MEMALLOCFLAG_GPU_UNCACHED_WC;
#else
ui32Ret = PVRSRV_MEMALLOCFLAG_GPU_CACHED;
#endif
}
break;

2
drivers/gpu/drm/img-rogue/devicemem_typedefs.h
View File

@@ -137,6 +137,6 @@ typedef IMG_UINT32 SPARSE_MEM_RESIZE_FLAGS;
/* Defines the max length for PMR, MemDesc, Device memory History and RI debug
* annotations stored in memory, including the null terminator.
*/
#define DEVMEM_ANNOTATION_MAX_LEN (PVR_ANNOTATION_MAX_LEN + 1U)
#define DEVMEM_ANNOTATION_MAX_LEN ((IMG_UINT32)PVR_ANNOTATION_MAX_LEN + 1U)
#endif /* #ifndef DEVICEMEM_TYPEDEFS_H */

107
drivers/gpu/drm/img-rogue/devicemem_utils.c
View File

@@ -49,6 +49,7 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#include "ra.h"
#include "devicemem_utils.h"
#include "client_mm_bridge.h"
#include "client_cache_bridge.h"
#if defined(PVRSRV_ENABLE_GPU_MEMORY_INFO)
#include "client_ri_bridge.h"
#if defined(__KERNEL__)
@@ -62,6 +63,12 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#include "proc_stats.h"
#endif
#if defined(__KERNEL__)
#include "srvcore.h"
#else
#include "srvcore_intern.h"
#endif
/*
SVM heap management support functions for CPU (un)mapping
*/
@@ -371,8 +378,12 @@ IMG_BOOL DevmemImportStructRelease(DEVMEM_IMPORT *psImport)
if (iRefCount == 0)
{
BridgePMRUnrefPMR(GetBridgeHandle(psImport->hDevConnection),
psImport->hPMR);
PVRSRV_ERROR eError = DestroyServerResource(psImport->hDevConnection,
NULL,
BridgePMRUnrefPMR,
psImport->hPMR);
PVR_ASSERT(eError == PVRSRV_OK);
OSLockDestroy(psImport->sCPUImport.hLock);
OSLockDestroy(psImport->sDeviceImport.hLock);
OSLockDestroy(psImport->hLock);
@@ -455,9 +466,24 @@ void DevmemMemDescInit(DEVMEM_MEMDESC *psMemDesc,
psMemDesc->hPrivData = NULL;
psMemDesc->ui32AllocationIndex = DEVICEMEM_HISTORY_ALLOC_INDEX_NONE;
#if defined(DEBUG)
psMemDesc->bPoisonOnFree = IMG_FALSE;
#endif
OSAtomicWrite(&psMemDesc->hRefCount, 1);
}
#if defined(DEBUG)
IMG_INTERNAL
void DevmemMemDescSetPoF(DEVMEM_MEMDESC *psMemDesc, PVRSRV_MEMALLOCFLAGS_T uiFlags)
{
if (PVRSRV_CHECK_POISON_ON_FREE(uiFlags))
{
psMemDesc->bPoisonOnFree = IMG_TRUE;
}
}
#endif
IMG_INTERNAL
void DevmemMemDescAcquire(DEVMEM_MEMDESC *psMemDesc)
{
@@ -473,6 +499,48 @@ void DevmemMemDescAcquire(DEVMEM_MEMDESC *psMemDesc)
PVR_UNREFERENCED_PARAMETER(iRefCount);
}
#if defined(DEBUG)
static void _DevmemPoisonOnFree(DEVMEM_MEMDESC *psMemDesc)
{
void *pvAddr = NULL;
IMG_UINT8 *pui8CPUVAddr;
PVRSRV_ERROR eError;
eError = DevmemCPUMapCheckImportProperties(psMemDesc);
PVR_LOG_RETURN_VOID_IF_ERROR(eError, "DevmemCPUMapCheckImportProperties");
OSLockAcquire(psMemDesc->sCPUMemDesc.hLock);
eError = DevmemImportStructCPUMap(psMemDesc->psImport);
OSLockRelease(psMemDesc->sCPUMemDesc.hLock);
PVR_LOG_RETURN_VOID_IF_ERROR(eError, "DevmemImportStructCPUMap");
pui8CPUVAddr = psMemDesc->psImport->sCPUImport.pvCPUVAddr;
pui8CPUVAddr += psMemDesc->uiOffset;
pvAddr = pui8CPUVAddr;
DevmemCPUMemSet(pvAddr,
PVRSRV_POISON_ON_FREE_VALUE,
psMemDesc->uiAllocSize,
psMemDesc->psImport->uiFlags);
if (PVRSRV_CHECK_CPU_CACHE_COHERENT(psMemDesc->psImport->uiFlags) ||
PVRSRV_CHECK_CPU_CACHE_INCOHERENT(psMemDesc->psImport->uiFlags))
{
eError = BridgeCacheOpExec(GetBridgeHandle(psMemDesc->psImport->hDevConnection),
psMemDesc->psImport->hPMR,
(IMG_UINT64) (uintptr_t)
pvAddr - psMemDesc->uiOffset,
psMemDesc->uiOffset,
psMemDesc->uiAllocSize,
PVRSRV_CACHE_OP_FLUSH);
PVR_LOG_IF_ERROR(eError, "BridgeCacheOpExec");
}
DevmemImportStructCPUUnmap(psMemDesc->psImport);
pvAddr = NULL;
}
#endif
IMG_INTERNAL
IMG_BOOL DevmemMemDescRelease(DEVMEM_MEMDESC *psMemDesc)
{
@@ -496,8 +564,10 @@ IMG_BOOL DevmemMemDescRelease(DEVMEM_MEMDESC *psMemDesc)
{
PVRSRV_ERROR eError;
eError = BridgeRIDeleteMEMDESCEntry(GetBridgeHandle(psMemDesc->psImport->hDevConnection),
psMemDesc->hRIHandle);
eError = DestroyServerResource(psMemDesc->psImport->hDevConnection,
NULL,
BridgeRIDeleteMEMDESCEntry,
psMemDesc->hRIHandle);
PVR_LOG_IF_ERROR(eError, "BridgeRIDeleteMEMDESCEntry");
}
#endif
@@ -508,7 +578,6 @@ IMG_BOOL DevmemMemDescRelease(DEVMEM_MEMDESC *psMemDesc)
/* As soon as the first sub-allocation on the psImport is freed
* we might get dirty memory when reusing it.
* We have to delete the ZEROED, CLEAN & POISONED flag */
psMemDesc->psImport->uiProperties &=
~(DEVMEM_PROPERTIES_IMPORT_IS_ZEROED |
DEVMEM_PROPERTIES_IMPORT_IS_CLEAN |
@@ -516,6 +585,13 @@ IMG_BOOL DevmemMemDescRelease(DEVMEM_MEMDESC *psMemDesc)
OSLockRelease(psMemDesc->psImport->hLock);
#if defined(DEBUG)
if (psMemDesc->bPoisonOnFree)
{
_DevmemPoisonOnFree(psMemDesc);
}
#endif
RA_Free(psMemDesc->psImport->sDeviceImport.psHeap->psSubAllocRA,
psMemDesc->psImport->sDeviceImport.sDevVAddr.uiAddr +
psMemDesc->uiOffset);
@@ -579,8 +655,13 @@ PVRSRV_ERROR DevmemValidateParams(IMG_DEVMEM_SIZE_T uiSize,
return PVRSRV_ERROR_INVALID_PARAMS;
}
/* If zero flag is set we have to have write access to the page. */
if (PVRSRV_CHECK_ZERO_ON_ALLOC(*puiFlags) || PVRSRV_CHECK_CPU_WRITEABLE(*puiFlags))
/* If zero or poison flags are set we have to have write access to the page. */
if (PVRSRV_CHECK_ZERO_ON_ALLOC(*puiFlags) ||
PVRSRV_CHECK_POISON_ON_ALLOC(*puiFlags) ||
#if defined(DEBUG)
PVRSRV_CHECK_POISON_ON_FREE(*puiFlags) ||
#endif
PVRSRV_CHECK_CPU_WRITEABLE(*puiFlags))
{
(*puiFlags) |= PVRSRV_MEMALLOCFLAG_CPU_WRITEABLE |
PVRSRV_MEMALLOCFLAG_CPU_READABLE;
@@ -1035,13 +1116,17 @@ IMG_BOOL DevmemImportStructDevUnmap(DEVMEM_IMPORT *psImport)
{
if (psDeviceImport->bMapped)
{
eError = BridgeDevmemIntUnmapPMR(GetBridgeHandle(psImport->hDevConnection),
psDeviceImport->hMapping);
eError = DestroyServerResource(psImport->hDevConnection,
NULL,
BridgeDevmemIntUnmapPMR,
psDeviceImport->hMapping);
PVR_ASSERT(eError == PVRSRV_OK);
}
eError = BridgeDevmemIntUnreserveRange(GetBridgeHandle(psImport->hDevConnection),
psDeviceImport->hReservation);
eError = DestroyServerResource(psImport->hDevConnection,
NULL,
BridgeDevmemIntUnreserveRange,
psDeviceImport->hReservation);
PVR_ASSERT(eError == PVRSRV_OK);
}

85
drivers/gpu/drm/img-rogue/devicemem_utils.h
View File

@@ -54,6 +54,7 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#include "osfunc.h"
#include "lock.h"
#include "osmmap.h"
#include "pvrsrv_memallocflags_internal.h"
#define DEVMEM_HEAPNAME_MAXLENGTH 160
@@ -288,6 +289,10 @@ struct DEVMEM_MEMDESC_TAG
IMG_UINT32 ui32AllocationIndex;
#if defined(DEBUG)
IMG_BOOL bPoisonOnFree;
#endif
#if defined(PVRSRV_ENABLE_GPU_MEMORY_INFO)
IMG_HANDLE hRIHandle; /*!< Handle to RI information */
#endif
@@ -444,7 +449,7 @@ IMG_BOOL DevmemImportStructRelease(DEVMEM_IMPORT *psImport);
/******************************************************************************
@Function DevmemImportDiscard
@Description Discard a created, but unitilised import structure.
@Description Discard a created, but uninitialised import structure.
This must only be called before DevmemImportStructInit
after which DevmemImportStructRelease must be used to
"free" the import structure.
@@ -459,6 +464,16 @@ void DevmemImportDiscard(DEVMEM_IMPORT *psImport);
******************************************************************************/
PVRSRV_ERROR DevmemMemDescAlloc(DEVMEM_MEMDESC **ppsMemDesc);
#if defined(DEBUG)
/******************************************************************************
@Function DevmemMemDescSetPoF
@Description Sets the Poison on Free flag to true for this MemDesc if the
given MemAllocFlags have the Poison on Free bit set.
Poison on Free is a debug only feature.
******************************************************************************/
void DevmemMemDescSetPoF(DEVMEM_MEMDESC *psMemDesc, PVRSRV_MEMALLOCFLAGS_T uiFlags);
#endif
/******************************************************************************
@Function DevmemMemDescInit
@Description Sets the given offset and import struct fields in the MemDesc.
@@ -519,4 +534,72 @@ static INLINE DEVMEM_PROPERTIES_T GetImportProperties(DEVMEM_IMPORT *psImport)
return uiProperties;
}
/******************************************************************************
@Function DevmemCPUMemSet
@Description Given a CPU Mapped Devmem address, set the memory at that
range (address, address + size) to the uiPattern provided.
Flags determine the OS abstracted MemSet method to use.
******************************************************************************/
static INLINE void DevmemCPUMemSet(void *pvMem,
IMG_UINT8 uiPattern,
IMG_DEVMEM_SIZE_T uiSize,
PVRSRV_MEMALLOCFLAGS_T uiFlags)
{
if (PVRSRV_CHECK_CPU_UNCACHED(uiFlags))
{
OSDeviceMemSet(pvMem, uiPattern, uiSize);
}
else
{
/* it's safe to use OSCachedMemSet() for cached and wc memory */
OSCachedMemSet(pvMem, uiPattern, uiSize);
}
}
/******************************************************************************
@Function DevmemCPUMapCheckImportProperties
@Description Given a MemDesc check that the import properties are correct
to allow for mapping the MemDesc to the CPU.
Returns PVRSRV_OK on success.
******************************************************************************/
static INLINE PVRSRV_ERROR DevmemCPUMapCheckImportProperties(DEVMEM_MEMDESC *psMemDesc)
{
DEVMEM_PROPERTIES_T uiProperties = GetImportProperties(psMemDesc->psImport);
if (uiProperties &
(DEVMEM_PROPERTIES_UNPINNED | DEVMEM_PROPERTIES_SECURE))
{
#if defined(SUPPORT_SECURITY_VALIDATION)
if (uiProperties & DEVMEM_PROPERTIES_SECURE)
{
PVR_DPF((PVR_DBG_WARNING,
"%s: Allocation is a secure buffer. "
"It should not be possible to map to CPU, but for security "
"validation this will be allowed for testing purposes, "
"as long as the buffer is pinned.",
__func__));
}
if (uiProperties & DEVMEM_PROPERTIES_UNPINNED)
#endif
{
PVR_DPF((PVR_DBG_ERROR,
"%s: Allocation is currently unpinned or a secure buffer. "
"Not possible to map to CPU!",
__func__));
return PVRSRV_ERROR_INVALID_MAP_REQUEST;
}
}
if (uiProperties & DEVMEM_PROPERTIES_NO_CPU_MAPPING)
{
PVR_DPF((PVR_DBG_ERROR,
"%s: CPU Mapping is not possible on this allocation!",
__func__));
return PVRSRV_ERROR_INVALID_MAP_REQUEST;
}
return PVRSRV_OK;
}
#endif /* DEVICEMEM_UTILS_H */

4
drivers/gpu/drm/img-rogue/di_common.h
View File

@@ -226,9 +226,11 @@ typedef struct DI_ITERATOR_CB
DI_PFN_SEEK pfnSeek; /*!< Sets data pointer in an entry. */
DI_PFN_READ pfnRead; /*!< Reads data from an entry. */
/* Optional writing to entry interface. */
/* Optional writing to entry interface. Null terminated. */
DI_PFN_WRITE pfnWrite; /*!< Performs write operation on an entry. */
IMG_UINT32 ui32WriteLenMax; /*!< Maximum char length of entry
accepted for write. Includes \0 */
} DI_ITERATOR_CB;
#endif /* DI_COMMON_H */

7
drivers/gpu/drm/img-rogue/di_impl_brg.c
View File

@@ -193,6 +193,12 @@ static void _WriteWithRetires(void *pvNativeHandle, const IMG_CHAR *pszStr,
PVR_LOG_IF_ERROR(eError, "TLStreamWrite");
}
static void _WriteData(void *pvNativeHandle, const void *pvData,
IMG_UINT32 uiSize)
{
_WriteWithRetires(pvNativeHandle, pvData, uiSize);
}
__printf(2, 0)
static void _VPrintf(void *pvNativeHandle, const IMG_CHAR *pszFmt,
va_list pArgs)
@@ -216,6 +222,7 @@ static IMG_BOOL _HasOverflowed(void *pvNativeHandle)
}
static OSDI_IMPL_ENTRY_CB _g_sEntryCallbacks = {
.pfnWrite = _WriteData,
.pfnVPrintf = _VPrintf,
.pfnPuts = _Puts,
.pfnHasOverflowed = _HasOverflowed,

13
drivers/gpu/drm/img-rogue/di_server.c
View File

@@ -265,7 +265,7 @@ static PVRSRV_ERROR _CreateNativeEntry(DI_ENTRY *psEntry,
psEntry->pvPrivData,
psNativeParent->pvHandle,
&psNativeEntry->pvHandle);
PVR_LOG_GOTO_IF_ERROR(eError, "psImpl->sCb.pfnCreateGroup", free_memory_);
PVR_LOG_GOTO_IF_ERROR(eError, "psImpl->sCb.pfnCreateEntry", free_memory_);
psNativeEntry->psDiImpl = psImpl;
@@ -526,6 +526,17 @@ void *DIGetPrivData(const OSDI_IMPL_ENTRY *psEntry)
return psEntry->pvPrivData;
}
void DIWrite(const OSDI_IMPL_ENTRY *psEntry, const void *pvData,
IMG_UINT32 uiSize)
{
PVR_ASSERT(psEntry != NULL);
PVR_ASSERT(psEntry->psCb != NULL);
PVR_ASSERT(psEntry->psCb->pfnWrite != NULL);
PVR_ASSERT(psEntry->pvNative != NULL);
psEntry->psCb->pfnWrite(psEntry->pvNative, pvData, uiSize);
}
void DIPrintf(const OSDI_IMPL_ENTRY *psEntry, const IMG_CHAR *pszFmt, ...)
{
va_list args;

25
drivers/gpu/drm/img-rogue/di_server.h
View File

@@ -43,7 +43,17 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#ifndef DI_SERVER_H
#define DI_SERVER_H
#include <stdarg.h>
#if defined(__linux__)
#include <linux/version.h>
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 15, 0))
#include <linux/stdarg.h>
#else
#include <stdarg.h>
#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(5, 15, 0) */
#else
#include <stdarg.h>
#endif /* __linux__ */
#include "di_common.h"
#include "pvrsrv_error.h"
@@ -150,6 +160,19 @@ void DIDestroyGroup(DI_GROUP *psGroup);
*/
void *DIGetPrivData(const OSDI_IMPL_ENTRY *psEntry);
/*! @Function DIWrite
*
* @Description
* Writes the binary data of the DI entry to the output sync, whatever that may
* be for the DI implementation.
*
* @Input psEntry pointer to OSDI_IMPL_ENTRY object
* @Input pvData data
* @Input uiSize pvData length
*/
void DIWrite(const OSDI_IMPL_ENTRY *psEntry, const void *pvData,
IMG_UINT32 uiSize);
/*! @Function DIPrintf
*
* @Description

47
drivers/gpu/drm/img-rogue/drm_nulldisp_drv.c
View File

@@ -2064,7 +2064,9 @@ static int nulldisp_early_load(struct drm_device *dev)
goto err_workqueue_cleanup;
}
#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 15, 0))
dev->irq_enabled = true;
#endif
nulldisp_dev->nlpvrdpy = nlpvrdpy_create(dev,
nulldisp_nl_disconnect_cb,
@@ -2087,7 +2089,9 @@ err_vblank_cleanup:
#endif
err_workqueue_cleanup:
destroy_workqueue(nulldisp_dev->workqueue);
#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 15, 0))
dev->irq_enabled = false;
#endif
err_gem_cleanup:
#if defined(LMA)
pdp_gem_cleanup(nulldisp_dev->pdp_gem_priv);
@@ -2143,7 +2147,9 @@ static void nulldisp_late_unload(struct drm_device *dev)
#endif
destroy_workqueue(nulldisp_dev->workqueue);
#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 15, 0))
dev->irq_enabled = false;
#endif
#if defined(LMA)
pdp_gem_cleanup(nulldisp_dev->pdp_gem_priv);
@@ -2248,24 +2254,6 @@ static const struct vm_operations_struct nulldisp_gem_vm_ops = {
#endif
};
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 9, 0))
const struct drm_gem_object_funcs nulldisp_gem_funcs = {
#if defined(LMA)
.free = pdp_gem_object_free,
.export = pdp_gem_prime_export,
#else
.export = drm_gem_prime_export,
.pin = nulldisp_gem_prime_pin,
.unpin = nulldisp_gem_prime_unpin,
.get_sg_table = nulldisp_gem_prime_get_sg_table,
.vmap = nulldisp_gem_prime_vmap,
.vunmap = nulldisp_gem_prime_vunmap,
.free = nulldisp_gem_object_free,
#endif /* defined(LMA) */
.vm_ops = &nulldisp_gem_vm_ops,
};
#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(5, 9, 0) */
#if defined(LMA)
static int pdp_gem_dumb_create(struct drm_file *file,
struct drm_device *dev,
@@ -2366,15 +2354,32 @@ static int nulldisp_gem_object_cpu_fini_ioctl(struct drm_device *dev,
return pdp_gem_object_cpu_fini_ioctl(dev, &pdp_args, file);
}
static void pdp_gem_object_free(struct drm_gem_object *obj)
static void nulldisp_pdp_gem_object_free(struct drm_gem_object *obj)
{
struct nulldisp_display_device *nulldisp_dev = obj->dev->dev_private;
pdp_gem_object_free_priv(nulldisp_dev->pdp_gem_priv, obj);
}
#endif
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 9, 0))
const struct drm_gem_object_funcs nulldisp_gem_funcs = {
#if defined(LMA)
.free = nulldisp_pdp_gem_object_free,
.export = pdp_gem_prime_export,
#else
.export = drm_gem_prime_export,
.pin = nulldisp_gem_prime_pin,
.unpin = nulldisp_gem_prime_unpin,
.get_sg_table = nulldisp_gem_prime_get_sg_table,
.vmap = nulldisp_gem_prime_vmap,
.vunmap = nulldisp_gem_prime_vunmap,
.free = nulldisp_gem_object_free,
#endif /* defined(LMA) */
.vm_ops = &nulldisp_gem_vm_ops,
};
#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(5, 9, 0) */
static const struct drm_ioctl_desc nulldisp_ioctls[] = {
DRM_IOCTL_DEF_DRV(NULLDISP_GEM_CREATE,
nulldisp_gem_object_create_ioctl,
@@ -2462,7 +2467,7 @@ static struct drm_driver nulldisp_drm_driver = {
#if defined(LMA)
#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 9, 0))
.gem_free_object = pdp_gem_object_free,
.gem_free_object = nulldisp_pdp_gem_object_free,
.gem_prime_export = pdp_gem_prime_export,
#endif /* LINUX_VERSION_CODE < KERNEL_VERSION(5, 9, 0) */
.gem_prime_import = pdp_gem_prime_import,

4
drivers/gpu/drm/img-rogue/drm_nulldisp_gem.c
View File

@@ -463,7 +463,7 @@ int nulldisp_gem_object_cpu_prep_ioctl(struct drm_device *dev, void *data,
if (wait) {
long lerr;
lerr = dma_resv_wait_timeout_rcu(nulldisp_obj->resv,
lerr = dma_resv_wait_timeout(nulldisp_obj->resv,
write,
true,
30 * HZ);
@@ -480,7 +480,7 @@ int nulldisp_gem_object_cpu_prep_ioctl(struct drm_device *dev, void *data,
* Remap return value (false indicates busy state,
* true success).
*/
if (!dma_resv_test_signaled_rcu(nulldisp_obj->resv,
if (!dma_resv_test_signaled(nulldisp_obj->resv,
write))
err = -EBUSY;
else

668
drivers/gpu/drm/img-rogue/handle.c
View File

@@ -62,10 +62,12 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#include "handle_impl.h"
#include "allocmem.h"
#include "pvr_debug.h"
#include "osfunc.h"
#include "lock.h"
#include "connection_server.h"
#include "pvrsrv.h"
#define HANDLE_HASH_TAB_INIT_SIZE 32
#define HANDLE_HASH_TAB_INIT_SIZE 32
#define HANDLE_PROC_HANDLE_HASH_INIT_SIZE 10
#define TEST_FLAG(v, f) BITMASK_HAS(v, f)
#define TEST_ALLOC_FLAG(psHandleData, f) BITMASK_HAS((psHandleData)->eFlag, f)
@@ -107,10 +109,13 @@ typedef struct _HANDLE_DATA_
/* List entry for sibling subhandles */
HANDLE_LIST sSiblings;
/* Reference count. The pfnReleaseData callback gets called when the
* reference count hits zero
*/
IMG_UINT32 ui32RefCount;
/* Reference count of lookups made. It helps track which resources are in
* use in concurrent bridge calls. */
IMG_INT32 iLookupCount;
/* State of a handle. If the handle was already destroyed this is false.
* If this is false and iLookupCount is 0 the pfnReleaseData callback is
* called on the handle. */
IMG_BOOL bCanLookup;
#if defined(PVRSRV_DEBUG_HANDLE_LOCK)
/* Store the handle base used for this handle, so we
@@ -179,6 +184,12 @@ static HANDLE_IMPL_FUNCTAB const *gpsHandleFuncs;
static POS_LOCK gKernelHandleLock;
static IMG_BOOL gbLockInitialised = IMG_FALSE;
/* Pointer to process handle base currently being freed */
static PVRSRV_HANDLE_BASE *g_psProcessHandleBaseBeingFreed;
/* Lock for the process handle base table */
static POS_LOCK g_hProcessHandleBaseLock;
/* Hash table with process handle bases */
static HASH_TABLE *g_psProcessHandleBaseTable;
void LockHandle(PVRSRV_HANDLE_BASE *psBase)
{
@@ -196,11 +207,11 @@ void UnlockHandle(PVRSRV_HANDLE_BASE *psBase)
*/
PVRSRV_HANDLE_BASE *gpsKernelHandleBase = NULL;
/* Increase the reference count on the given handle.
/* Increase the lookup reference count on the given handle.
* The handle lock must already be acquired.
* Returns: the reference count after the increment
*/
static inline IMG_UINT32 _HandleRef(HANDLE_DATA *psHandleData)
static inline IMG_UINT32 HandleGet(HANDLE_DATA *psHandleData)
{
#if defined(PVRSRV_DEBUG_HANDLE_LOCK)
if (!OSLockIsLocked(psHandleData->psBase->hLock))
@@ -209,15 +220,23 @@ static inline IMG_UINT32 _HandleRef(HANDLE_DATA *psHandleData)
OSDumpStack();
}
#endif
psHandleData->ui32RefCount++;
return psHandleData->ui32RefCount;
#ifdef DEBUG_REFCNT
PVR_DPF((PVR_DBG_ERROR, "%s: bCanLookup = %u, iLookupCount %d -> %d",
__func__, psHandleData->bCanLookup, psHandleData->iLookupCount,
psHandleData->iLookupCount + 1));
#endif /* DEBUG_REFCNT */
PVR_ASSERT(psHandleData->bCanLookup);
return ++psHandleData->iLookupCount;
}
/* Decrease the reference count on the given handle.
/* Decrease the lookup reference count on the given handle.
* The handle lock must already be acquired.
* Returns: the reference count after the decrement
*/
static inline IMG_UINT32 _HandleUnref(HANDLE_DATA *psHandleData)
static inline IMG_UINT32 HandlePut(HANDLE_DATA *psHandleData)
{
#if defined(PVRSRV_DEBUG_HANDLE_LOCK)
if (!OSLockIsLocked(psHandleData->psBase->hLock))
@@ -226,10 +245,22 @@ static inline IMG_UINT32 _HandleUnref(HANDLE_DATA *psHandleData)
OSDumpStack();
}
#endif
PVR_ASSERT(psHandleData->ui32RefCount > 0);
psHandleData->ui32RefCount--;
return psHandleData->ui32RefCount;
#ifdef DEBUG_REFCNT
PVR_DPF((PVR_DBG_ERROR, "%s: bCanLookup = %u, iLookupCount %d -> %d",
__func__, psHandleData->bCanLookup, psHandleData->iLookupCount,
psHandleData->iLookupCount - 1));
#endif /* DEBUG_REFCNT */
/* psHandleData->bCanLookup can be false at this point */
PVR_ASSERT(psHandleData->iLookupCount > 0);
return --psHandleData->iLookupCount;
}
static inline IMG_BOOL IsRetryError(PVRSRV_ERROR eError)
{
return eError == PVRSRV_ERROR_RETRY || eError == PVRSRV_ERROR_KERNEL_CCB_FULL;
}
#if defined(PVRSRV_NEED_PVR_DPF)
@@ -266,6 +297,21 @@ static const IMG_CHAR *HandleBaseTypeToString(PVRSRV_HANDLE_BASE_TYPE eType)
}
#endif
static PVRSRV_ERROR HandleUnrefAndMaybeMarkForFree(PVRSRV_HANDLE_BASE *psBase,
HANDLE_DATA *psHandleData,
IMG_HANDLE hHandle,
PVRSRV_HANDLE_TYPE eType);
static PVRSRV_ERROR HandleFreePrivData(PVRSRV_HANDLE_BASE *psBase,
HANDLE_DATA *psHandleData,
IMG_HANDLE hHandle,
PVRSRV_HANDLE_TYPE eType);
static PVRSRV_ERROR HandleFreeDestroy(PVRSRV_HANDLE_BASE *psBase,
HANDLE_DATA *psHandleData,
IMG_HANDLE hHandle,
PVRSRV_HANDLE_TYPE eType);
/*!
*******************************************************************************
@Function GetHandleData
@@ -817,107 +863,6 @@ void InitKey(HAND_KEY aKey,
aKey[HAND_KEY_PARENT] = (uintptr_t)hParent;
}
static PVRSRV_ERROR FreeHandleWrapper(PVRSRV_HANDLE_BASE *psBase, IMG_HANDLE hHandle);
/*!
*******************************************************************************
@Function FreeHandle
@Description Free a handle data structure.
@Input psBase - Pointer to handle base structure
hHandle - Handle to be freed
eType - Type of the handle to be freed
ppvData - Location for data associated with the freed handle
@Output ppvData - Points to the data associated with the freed handle
@Return PVRSRV_OK or PVRSRV_ERROR
******************************************************************************/
static PVRSRV_ERROR FreeHandle(PVRSRV_HANDLE_BASE *psBase,
IMG_HANDLE hHandle,
PVRSRV_HANDLE_TYPE eType,
void **ppvData)
{
HANDLE_DATA *psHandleData = NULL;
HANDLE_DATA *psReleasedHandleData;
PVRSRV_ERROR eError;
eError = GetHandleData(psBase, &psHandleData, hHandle, eType);
PVR_LOG_RETURN_IF_ERROR(eError, "GetHandleData");
if (_HandleUnref(psHandleData) > 0)
{
/* this handle still has references so do not destroy it
* or the underlying object yet
*/
return PVRSRV_OK;
}
/* Call the release data callback for each reference on the handle */
if (psHandleData->pfnReleaseData != NULL)
{
eError = psHandleData->pfnReleaseData(psHandleData->pvData);
if (eError == PVRSRV_ERROR_RETRY)
{
PVR_DPF((PVR_DBG_MESSAGE,
"%s: "
"Got retry while calling release data callback for %p (type = %d)",
__func__,
hHandle,
(IMG_UINT32)psHandleData->eType));
/* the caller should retry, so retain a reference on the handle */
_HandleRef(psHandleData);
return eError;
}
else if (eError != PVRSRV_OK)
{
return eError;
}
}
if (!TEST_ALLOC_FLAG(psHandleData, PVRSRV_HANDLE_ALLOC_FLAG_MULTI))
{
HAND_KEY aKey;
IMG_HANDLE hRemovedHandle;
InitKey(aKey, psBase, psHandleData->pvData, psHandleData->eType, ParentIfPrivate(psHandleData));
hRemovedHandle = (IMG_HANDLE)HASH_Remove_Extended(psBase->psHashTab, aKey);
PVR_ASSERT(hRemovedHandle != NULL);
PVR_ASSERT(hRemovedHandle == psHandleData->hHandle);
PVR_UNREFERENCED_PARAMETER(hRemovedHandle);
}
eError = UnlinkFromParent(psBase, psHandleData);
PVR_LOG_RETURN_IF_ERROR(eError, "UnlinkFromParent");
/* Free children */
eError = IterateOverChildren(psBase, psHandleData, FreeHandleWrapper);
PVR_LOG_RETURN_IF_ERROR(eError, "IterateOverChildren");
eError = gpsHandleFuncs->pfnReleaseHandle(psBase->psImplBase,
psHandleData->hHandle,
(void **)&psReleasedHandleData);
if (unlikely(eError == PVRSRV_OK))
{
PVR_ASSERT(psReleasedHandleData == psHandleData);
}
if (ppvData)
{
*ppvData = psHandleData->pvData;
}
OSFreeMem(psHandleData);
return eError;
}
static PVRSRV_ERROR FreeHandleWrapper(PVRSRV_HANDLE_BASE *psBase, IMG_HANDLE hHandle)
{
return FreeHandle(psBase, hHandle, PVRSRV_HANDLE_TYPE_NONE, NULL);
}
/*!
*******************************************************************************
@Function FindHandle
@@ -1013,7 +958,12 @@ static PVRSRV_ERROR AllocHandle(PVRSRV_HANDLE_BASE *psBase,
psNewHandleData->eFlag = eFlag;
psNewHandleData->pvData = pvData;
psNewHandleData->pfnReleaseData = pfnReleaseData;
psNewHandleData->ui32RefCount = 1;
psNewHandleData->iLookupCount = 0;
psNewHandleData->bCanLookup = IMG_TRUE;
#ifdef DEBUG_REFCNT
PVR_DPF((PVR_DBG_ERROR, "%s: bCanLookup = true", __func__));
#endif /* DEBUG_REFCNT */
InitParentList(psNewHandleData);
#if defined(DEBUG)
@@ -1197,7 +1147,7 @@ PVRSRV_ERROR PVRSRVAllocSubHandleUnlocked(PVRSRV_HANDLE_BASE *psBase,
return PVRSRV_OK;
ExitFreeHandle:
(void) FreeHandle(psBase, hHandle, eType, NULL);
PVRSRVDestroyHandleUnlocked(psBase, hHandle, eType);
Exit:
return eError;
}
@@ -1337,14 +1287,16 @@ PVRSRV_ERROR PVRSRVLookupHandleUnlocked(PVRSRV_HANDLE_BASE *psBase,
return eError;
}
if (psHandleData->ui32RefCount == 0)
/* If bCanLookup is false it means that a destroy operation was already
* called on this handle; therefore it can no longer be looked up. */
if (!psHandleData->bCanLookup)
{
return PVRSRV_ERROR_HANDLE_INDEX_OUT_OF_RANGE;
return PVRSRV_ERROR_HANDLE_NOT_ALLOCATED;
}
if (bRef)
{
_HandleRef(psHandleData);
HandleGet(psHandleData);
}
*ppvData = psHandleData->pvData;
@@ -1424,17 +1376,13 @@ ExitUnlock:
eType - handle type
@Return Error code or PVRSRV_OK
******************************************************************************/
PVRSRV_ERROR PVRSRVReleaseHandle(PVRSRV_HANDLE_BASE *psBase,
IMG_HANDLE hHandle,
PVRSRV_HANDLE_TYPE eType)
void PVRSRVReleaseHandle(PVRSRV_HANDLE_BASE *psBase,
IMG_HANDLE hHandle,
PVRSRV_HANDLE_TYPE eType)
{
PVRSRV_ERROR eError;
LockHandle(psBase);
eError = PVRSRVReleaseHandleUnlocked(psBase, hHandle, eType);
PVRSRVReleaseHandleUnlocked(psBase, hHandle, eType);
UnlockHandle(psBase);
return eError;
}
@@ -1446,19 +1394,40 @@ PVRSRV_ERROR PVRSRVReleaseHandle(PVRSRV_HANDLE_BASE *psBase,
hold the lock when called.
@Input hHandle - handle from client
eType - handle type
@Return Error code or PVRSRV_OK
******************************************************************************/
PVRSRV_ERROR PVRSRVReleaseHandleUnlocked(PVRSRV_HANDLE_BASE *psBase,
IMG_HANDLE hHandle,
PVRSRV_HANDLE_TYPE eType)
void PVRSRVReleaseHandleUnlocked(PVRSRV_HANDLE_BASE *psBase,
IMG_HANDLE hHandle,
PVRSRV_HANDLE_TYPE eType)
{
HANDLE_DATA *psHandleData = NULL;
PVRSRV_ERROR eError;
/* PVRSRV_HANDLE_TYPE_NONE is reserved for internal use */
PVR_ASSERT(psBase != NULL);
PVR_ASSERT(eType != PVRSRV_HANDLE_TYPE_NONE);
PVR_ASSERT(gpsHandleFuncs);
PVR_LOG_RETURN_IF_INVALID_PARAM(psBase != NULL, "psBase");
PVR_LOG_RETURN_VOID_IF_FALSE(psBase != NULL, "invalid psBase");
return FreeHandle(psBase, hHandle, eType, NULL);
eError = GetHandleData(psBase, &psHandleData, hHandle, eType);
if (unlikely(eError != PVRSRV_OK))
{
PVR_DPF((PVR_DBG_ERROR, "%s: Error (%s) looking up handle %p of type %s "
"for base %p of type %s.", __func__, PVRSRVGetErrorString(eError),
(void*) hHandle, HandleTypeToString(eType), psBase,
HandleBaseTypeToString(psBase->eType)));
PVR_ASSERT(eError == PVRSRV_OK);
return;
}
PVR_ASSERT(psHandleData->bCanLookup);
PVR_ASSERT(psHandleData->iLookupCount > 0);
/* If there are still outstanding lookups for this handle or the handle
* has not been destroyed yet, return early */
HandlePut(psHandleData);
}
/*!
@@ -1483,88 +1452,94 @@ PVRSRV_ERROR PVRSRVPurgeHandles(PVRSRV_HANDLE_BASE *psBase)
return eError;
}
static PVRSRV_ERROR HandleUnrefAndMaybeMarkForFree(PVRSRV_HANDLE_BASE *psBase,
IMG_HANDLE hHandle,
PVRSRV_HANDLE_TYPE eType);
static PVRSRV_ERROR HandleUnrefAndMaybeMarkForFreeWrapper(PVRSRV_HANDLE_BASE *psBase,
IMG_HANDLE hHandle)
{
return HandleUnrefAndMaybeMarkForFree(psBase, hHandle, PVRSRV_HANDLE_TYPE_NONE);
HANDLE_DATA *psHandleData;
PVRSRV_ERROR eError = GetHandleData(psBase, &psHandleData, hHandle,
PVRSRV_HANDLE_TYPE_NONE);
PVR_RETURN_IF_ERROR(eError);
return HandleUnrefAndMaybeMarkForFree(psBase, psHandleData, hHandle, PVRSRV_HANDLE_TYPE_NONE);
}
static PVRSRV_ERROR HandleUnrefAndMaybeMarkForFree(PVRSRV_HANDLE_BASE *psBase,
HANDLE_DATA *psHandleData,
IMG_HANDLE hHandle,
PVRSRV_HANDLE_TYPE eType)
{
HANDLE_DATA *psHandleData = NULL;
PVRSRV_ERROR eError;
eError = GetHandleData(psBase, &psHandleData, hHandle, eType);
PVR_RETURN_IF_ERROR(eError);
if (psHandleData->ui32RefCount == 0)
/* If bCanLookup is false it means that the destructor was called more than
* once on this handle. */
if (!psHandleData->bCanLookup)
{
/* the handle is already in the destruction phase
* i.e. its refcount has already reached 0
*/
return PVRSRV_OK;
PVR_DPF((PVR_DBG_ERROR, "%s: Handle %p of type %s already freed.",
__func__, psHandleData->hHandle,
HandleTypeToString(psHandleData->eType)));
return PVRSRV_ERROR_HANDLE_NOT_FOUND;
}
if (_HandleUnref(psHandleData) > 0)
if (psHandleData->iLookupCount > 0)
{
/* this handle still has references so do not destroy it
* or the underlying object yet
*/
return PVRSRV_ERROR_OBJECT_STILL_REFERENCED;
}
/* Mark this handle as freed only if it's no longer referenced by any
* lookup. The user space should retry freeing this handle once there are
* no outstanding lookups. */
psHandleData->bCanLookup = IMG_FALSE;
#ifdef DEBUG_REFCNT
PVR_DPF((PVR_DBG_ERROR, "%s: bCanLookup = false, iLookupCount = %d", __func__,
psHandleData->iLookupCount));
#endif /* DEBUG_REFCNT */
/* Prepare children for destruction */
eError = IterateOverChildren(psBase, psHandleData,
HandleUnrefAndMaybeMarkForFreeWrapper);
PVR_LOG_RETURN_IF_ERROR(eError, "IterateOverChildren->HandleUnrefAndMaybeMarkForFree");
PVR_LOG_RETURN_IF_ERROR(eError, "HandleUnrefAndMaybeMarkForFreeWrapper");
return PVRSRV_OK;
}
static PVRSRV_ERROR HandleFreePrivData(PVRSRV_HANDLE_BASE *psBase,
IMG_HANDLE hHandle,
PVRSRV_HANDLE_TYPE eType);
static PVRSRV_ERROR HandleFreePrivDataWrapper(PVRSRV_HANDLE_BASE *psBase,
IMG_HANDLE hHandle)
{
return HandleFreePrivData(psBase, hHandle, PVRSRV_HANDLE_TYPE_NONE);
HANDLE_DATA *psHandleData;
PVRSRV_ERROR eError = GetHandleData(psBase, &psHandleData, hHandle,
PVRSRV_HANDLE_TYPE_NONE);
PVR_RETURN_IF_ERROR(eError);
return HandleFreePrivData(psBase, psHandleData, hHandle, PVRSRV_HANDLE_TYPE_NONE);
}
static PVRSRV_ERROR HandleFreePrivData(PVRSRV_HANDLE_BASE *psBase,
HANDLE_DATA *psHandleData,
IMG_HANDLE hHandle,
PVRSRV_HANDLE_TYPE eType)
{
HANDLE_DATA *psHandleData = NULL;
PVRSRV_ERROR eError;
eError = GetHandleData(psBase, &psHandleData, hHandle, eType);
PVR_RETURN_IF_ERROR(eError);
/* Call the release data callback for each reference on the handle */
if (psHandleData->pfnReleaseData != NULL)
{
eError = psHandleData->pfnReleaseData(psHandleData->pvData);
if (eError == PVRSRV_ERROR_RETRY)
if (eError != PVRSRV_OK)
{
PVR_DPF((PVR_DBG_MESSAGE,
"FreeHandle: "
"Got retry while calling release data callback for %p (type = %d)",
hHandle,
(IMG_UINT32)psHandleData->eType));
if (IsRetryError(eError))
{
PVR_DPF((PVR_DBG_MESSAGE, "%s: Got retry while calling release "
"data callback for handle %p of type = %s", __func__,
hHandle, HandleTypeToString(psHandleData->eType)));
}
else
{
PVR_LOG_ERROR(eError, "pfnReleaseData");
}
return eError;
}
else if (eError != PVRSRV_OK)
{
return eError;
}
/* we don't need this so make sure it's not called on
* the pvData for the second time
@@ -1580,27 +1555,25 @@ static PVRSRV_ERROR HandleFreePrivData(PVRSRV_HANDLE_BASE *psBase,
return PVRSRV_OK;
}
static PVRSRV_ERROR HandleFreeDestroy(PVRSRV_HANDLE_BASE *psBase,
IMG_HANDLE hHandle,
PVRSRV_HANDLE_TYPE eType);
static PVRSRV_ERROR HandleFreeDestroyWrapper(PVRSRV_HANDLE_BASE *psBase,
IMG_HANDLE hHandle)
IMG_HANDLE hHandle)
{
return HandleFreeDestroy(psBase, hHandle, PVRSRV_HANDLE_TYPE_NONE);
HANDLE_DATA *psHandleData;
PVRSRV_ERROR eError = GetHandleData(psBase, &psHandleData, hHandle,
PVRSRV_HANDLE_TYPE_NONE);
PVR_RETURN_IF_ERROR(eError);
return HandleFreeDestroy(psBase, psHandleData, hHandle, PVRSRV_HANDLE_TYPE_NONE);
}
static PVRSRV_ERROR HandleFreeDestroy(PVRSRV_HANDLE_BASE *psBase,
HANDLE_DATA *psHandleData,
IMG_HANDLE hHandle,
PVRSRV_HANDLE_TYPE eType)
{
HANDLE_DATA *psHandleData = NULL;
HANDLE_DATA *psReleasedHandleData;
PVRSRV_ERROR eError;
eError = GetHandleData(psBase, &psHandleData, hHandle, eType);
PVR_RETURN_IF_ERROR(eError);
eError = UnlinkFromParent(psBase, psHandleData);
PVR_LOG_RETURN_IF_ERROR(eError, "UnlinkFromParent");
@@ -1633,40 +1606,122 @@ static PVRSRV_ERROR HandleFreeDestroy(PVRSRV_HANDLE_BASE *psBase,
return PVRSRV_OK;
}
PVRSRV_ERROR PVRSRVReleaseHandleStagedUnlock(PVRSRV_HANDLE_BASE *psBase,
IMG_HANDLE hHandle,
PVRSRV_HANDLE_TYPE eType)
static PVRSRV_ERROR DestroyHandle(PVRSRV_HANDLE_BASE *psBase,
IMG_HANDLE hHandle,
PVRSRV_HANDLE_TYPE eType,
IMG_BOOL bReleaseLock)
{
PVRSRV_ERROR eError;
HANDLE_DATA *psHandleData = NULL;
PVR_ASSERT(eType != PVRSRV_HANDLE_TYPE_NONE);
PVR_ASSERT(gpsHandleFuncs);
PVR_LOG_RETURN_IF_FALSE(psBase != NULL, "psBase invalid",
PVRSRV_ERROR_INVALID_PARAMS);
PVR_LOG_RETURN_IF_INVALID_PARAM(psBase != NULL, "psBase");
eError = HandleUnrefAndMaybeMarkForFree(psBase, hHandle, eType);
if (eError == PVRSRV_ERROR_OBJECT_STILL_REFERENCED)
eError = GetHandleData(psBase, &psHandleData, hHandle, eType);
PVR_RETURN_IF_ERROR(eError);
eError = HandleUnrefAndMaybeMarkForFree(psBase, psHandleData, hHandle, eType);
PVR_RETURN_IF_ERROR(eError);
if (bReleaseLock)
{
return PVRSRV_OK;
}
else if (eError != PVRSRV_OK)
{
return eError;
UnlockHandle(psBase);
}
UnlockHandle(psBase);
eError = HandleFreePrivData(psBase, hHandle, eType);
eError = HandleFreePrivData(psBase, psHandleData, hHandle, eType);
if (eError != PVRSRV_OK)
{
LockHandle(psBase);
if (bReleaseLock)
{
LockHandle(psBase);
}
/* If the data could not be freed due to a temporary condition the
* handle must be kept alive so that the next destroy call can try again */
if (IsRetryError(eError))
{
psHandleData->bCanLookup = IMG_TRUE;
}
return eError;
}
LockHandle(psBase);
if (bReleaseLock)
{
LockHandle(psBase);
}
return HandleFreeDestroy(psBase, hHandle, eType);
return HandleFreeDestroy(psBase, psHandleData, hHandle, eType);
}
/*!
*******************************************************************************
@Function PVRSRVDestroyHandle
@Description Destroys a handle that is no longer needed. Will
acquiring the handle lock for duration of the call.
Can return RETRY or KERNEL_CCB_FULL if resource could not be
destroyed, caller should retry sometime later.
@Input psBase - pointer to handle base structure
hHandle - handle from client
eType - handle type
@Return Error code or PVRSRV_OK
******************************************************************************/
PVRSRV_ERROR PVRSRVDestroyHandle(PVRSRV_HANDLE_BASE *psBase,
IMG_HANDLE hHandle,
PVRSRV_HANDLE_TYPE eType)
{
PVRSRV_ERROR eError;
LockHandle(psBase);
eError = DestroyHandle(psBase, hHandle, eType, IMG_FALSE);
UnlockHandle(psBase);
return eError;
}
/*!
*******************************************************************************
@Function PVRSRVDestroyHandleUnlocked
@Description Destroys a handle that is no longer needed without
acquiring/releasing the handle lock. The function assumes you
hold the lock when called.
Can return RETRY or KERNEL_CCB_FULL if resource could not be
destroyed, caller should retry sometime later.
@Input psBase - pointer to handle base structure
hHandle - handle from client
eType - handle type
@Return Error code or PVRSRV_OK
******************************************************************************/
PVRSRV_ERROR PVRSRVDestroyHandleUnlocked(PVRSRV_HANDLE_BASE *psBase,
IMG_HANDLE hHandle,
PVRSRV_HANDLE_TYPE eType)
{
return DestroyHandle(psBase, hHandle, eType, IMG_FALSE);
}
/*!
*******************************************************************************
@Function PVRSRVDestroyHandleStagedUnlocked
@Description Destroys a handle that is no longer needed without
acquiring/releasing the handle lock. The function assumes you
hold the lock when called. This function, unlike
PVRSRVDestroyHandleUnlocked(), releases the handle lock while
destroying handle private data. This is done to open the
bridge for other bridge calls.
Can return RETRY or KERNEL_CCB_FULL if resource could not be
destroyed, caller should retry sometime later.
@Input psBase - pointer to handle base structure
hHandle - handle from client
eType - handle type
@Return Error code or PVRSRV_OK
******************************************************************************/
PVRSRV_ERROR PVRSRVDestroyHandleStagedUnlocked(PVRSRV_HANDLE_BASE *psBase,
IMG_HANDLE hHandle,
PVRSRV_HANDLE_TYPE eType)
{
return DestroyHandle(psBase, hHandle, eType, IMG_TRUE);
}
/*!
@@ -1778,12 +1833,11 @@ static PVRSRV_ERROR ListHandlesInBase(IMG_HANDLE hHandle, void *pvData)
if (psHandleData != NULL)
{
PVR_DPF((PVR_DBG_WARNING, " Handle: %6u, Refs: %3u, Type: %s (%u), pvData<%p>",
(IMG_UINT32) (uintptr_t) psHandleData->hHandle,
psHandleData->ui32RefCount,
HandleTypeToString(psHandleData->eType),
psHandleData->eType,
psHandleData->pvData));
PVR_DPF((PVR_DBG_WARNING,
" Handle: %6u, CanLookup: %u, LookupCount: %3u, Type: %s (%u), pvData<%p>",
(IMG_UINT32) (uintptr_t) psHandleData->hHandle, psHandleData->bCanLookup,
psHandleData->iLookupCount, HandleTypeToString(psHandleData->eType),
psHandleData->eType, psHandleData->pvData));
}
return PVRSRV_OK;
@@ -1794,7 +1848,7 @@ static PVRSRV_ERROR ListHandlesInBase(IMG_HANDLE hHandle, void *pvData)
static INLINE IMG_BOOL _CheckIfMaxTimeExpired(IMG_UINT64 ui64TimeStart, IMG_UINT64 ui64MaxBridgeTime)
{
/* unsigned arithmetic is well defined so this will wrap around correctly */
return (OSClockns64() - ui64TimeStart) >= ui64MaxBridgeTime;
return (IMG_BOOL)((OSClockns64() - ui64TimeStart) >= ui64MaxBridgeTime);
}
static PVRSRV_ERROR FreeKernelHandlesWrapperIterKernel(IMG_HANDLE hHandle, void *pvData)
@@ -1888,21 +1942,18 @@ static PVRSRV_ERROR FreeHandleDataWrapper(IMG_HANDLE hHandle, void *pvData)
return PVRSRV_OK;
}
PVR_ASSERT(psHandleData->ui32RefCount > 0);
PVR_ASSERT(psHandleData->bCanLookup && psHandleData->iLookupCount == 0);
while (psHandleData->ui32RefCount != 0)
if (psHandleData->bCanLookup)
{
if (psHandleData->pfnReleaseData != NULL)
{
eError = psHandleData->pfnReleaseData(psHandleData->pvData);
if (eError == PVRSRV_ERROR_RETRY)
{
PVR_DPF((PVR_DBG_MESSAGE,
"%s: "
"Got retry while calling release data callback for %p (type = %d)",
__func__,
hHandle,
(IMG_UINT32)psHandleData->eType));
PVR_DPF((PVR_DBG_MESSAGE, "%s: Got retry while calling release "
"data callback for handle %p of type = %s", __func__,
hHandle, HandleTypeToString(psHandleData->eType)));
return eError;
}
@@ -1912,7 +1963,7 @@ static PVRSRV_ERROR FreeHandleDataWrapper(IMG_HANDLE hHandle, void *pvData)
}
}
_HandleUnref(psHandleData);
psHandleData->bCanLookup = IMG_FALSE;
}
if (!TEST_ALLOC_FLAG(psHandleData, PVRSRV_HANDLE_ALLOC_FLAG_MULTI))
@@ -1946,10 +1997,10 @@ static PVRSRV_ERROR FreeHandleDataWrapper(IMG_HANDLE hHandle, void *pvData)
"%s: Lock timeout (timeout: %" IMG_UINT64_FMTSPEC")",
__func__,
psData->ui64MaxBridgeTime));
/* UnlockHandle(psData->psBase); - func only run in single thread ctx */
UnlockHandle(psData->psBase);
/* Invoke the scheduler to check if other processes are waiting for the lock */
OSReleaseThreadQuanta();
/* LockHandle(psData->psBase); - func only run in single thread ctx */
LockHandle(psData->psBase);
/* Set again lock timeout and reset the counter */
psData->ui64TimeStart = OSClockns64();
PVR_DPF((PVR_DBG_MESSAGE, "%s: Lock acquired again", __func__));
@@ -1998,6 +2049,9 @@ static const PVRSRV_HANDLE_TYPE g_aeOrderedFreeList[] =
PVRSRV_HANDLE_TYPE_RGX_SERVER_COMPUTE_CONTEXT,
PVRSRV_HANDLE_TYPE_RGX_SERVER_RAY_CONTEXT,
PVRSRV_HANDLE_TYPE_RGX_SERVER_KICKSYNC_CONTEXT,
#if defined(PVR_TESTING_UTILS) && defined(SUPPORT_VALIDATION)
PVRSRV_HANDLE_TYPE_RGX_SERVER_GPUMAP_CONTEXT,
#endif
PVRSRV_HANDLE_TYPE_RI_HANDLE,
PVRSRV_HANDLE_TYPE_SYNC_RECORD_HANDLE,
PVRSRV_HANDLE_TYPE_SYNC_PRIMITIVE_BLOCK,
@@ -2069,19 +2123,21 @@ PVRSRV_HANDLE_BASE *PVRSRVRetrieveProcessHandleBase(void)
{
PVRSRV_HANDLE_BASE *psHandleBase = NULL;
PROCESS_HANDLE_BASE *psProcHandleBase = NULL;
PVRSRV_DATA *psPvrData = PVRSRVGetPVRSRVData();
IMG_PID ui32PurgePid = PVRSRVGetPurgeConnectionPid();
IMG_PID uiCleanupPid = PVRSRVCleanupThreadGetPid();
uintptr_t uiCleanupTid = PVRSRVCleanupThreadGetTid();
OSLockAcquire(psPvrData->hProcessHandleBase_Lock);
OSLockAcquire(g_hProcessHandleBaseLock);
/* Check to see if we're being called from the cleanup thread... */
if ((OSGetCurrentClientProcessIDKM() == psPvrData->cleanupThreadPid) &&
(ui32PurgePid > 0))
if ((OSGetCurrentProcessID() == uiCleanupPid) &&
(OSGetCurrentThreadID() == uiCleanupTid) &&
(ui32PurgePid > 0))
{
/* Check to see if the cleanup thread has already removed the
* process handle base from the HASH table.
*/
psHandleBase = psPvrData->psProcessHandleBaseBeingFreed;
psHandleBase = g_psProcessHandleBaseBeingFreed;
/* psHandleBase shouldn't be null, as cleanup thread
* should be removing this from the HASH table before
* we get here, so assert if not.
@@ -2093,10 +2149,11 @@ PVRSRV_HANDLE_BASE *PVRSRVRetrieveProcessHandleBase(void)
/* Not being called from the cleanup thread, so return the process
* handle base for the current process.
*/
psProcHandleBase = (PROCESS_HANDLE_BASE*) HASH_Retrieve(psPvrData->psProcessHandleBase_Table,
OSGetCurrentClientProcessIDKM());
psProcHandleBase = (PROCESS_HANDLE_BASE *)
HASH_Retrieve(g_psProcessHandleBaseTable, OSGetCurrentClientProcessIDKM());
}
OSLockRelease(psPvrData->hProcessHandleBase_Lock);
OSLockRelease(g_hProcessHandleBaseLock);
if (psHandleBase == NULL && psProcHandleBase != NULL)
{
@@ -2105,6 +2162,112 @@ PVRSRV_HANDLE_BASE *PVRSRVRetrieveProcessHandleBase(void)
return psHandleBase;
}
/*!
*******************************************************************************
@Function PVRSRVAcquireProcessHandleBase
@Description Increments reference count on a process handle base identified
by uiPid and returns pointer to the base. If the handle base
does not exist it will be allocated.
@Inout uiPid - PID of a process
@Output ppsBase - pointer to a handle base for the process identified by
uiPid
@Return Error code or PVRSRV_OK
******************************************************************************/
PVRSRV_ERROR PVRSRVAcquireProcessHandleBase(IMG_PID uiPid, PROCESS_HANDLE_BASE **ppsBase)
{
PROCESS_HANDLE_BASE *psBase;
PVRSRV_ERROR eError;
OSLockAcquire(g_hProcessHandleBaseLock);
psBase = (PROCESS_HANDLE_BASE*) HASH_Retrieve(g_psProcessHandleBaseTable, uiPid);
/* In case there is none we are going to allocate one */
if (psBase == NULL)
{
IMG_BOOL bSuccess;
psBase = OSAllocZMem(sizeof(*psBase));
PVR_LOG_GOTO_IF_NOMEM(psBase, eError, ErrorUnlock);
/* Allocate handle base for this process */
eError = PVRSRVAllocHandleBase(&psBase->psHandleBase, PVRSRV_HANDLE_BASE_TYPE_PROCESS);
PVR_LOG_GOTO_IF_ERROR(eError, "PVRSRVAllocHandleBase", ErrorFreeProcessHandleBase);
/* Insert the handle base into the global hash table */
bSuccess = HASH_Insert(g_psProcessHandleBaseTable, uiPid, (uintptr_t) psBase);
PVR_LOG_GOTO_IF_FALSE(bSuccess, "HASH_Insert failed", ErrorFreeHandleBase);
}
OSAtomicIncrement(&psBase->iRefCount);
OSLockRelease(g_hProcessHandleBaseLock);
*ppsBase = psBase;
return PVRSRV_OK;
ErrorFreeHandleBase:
PVRSRVFreeHandleBase(psBase->psHandleBase, 0);
ErrorFreeProcessHandleBase:
OSFreeMem(psBase);
ErrorUnlock:
OSLockRelease(g_hProcessHandleBaseLock);
return eError;
}
/*!
*******************************************************************************
@Function PVRSRVReleaseProcessHandleBase
@Description Decrements reference count on a process handle base psBase
for a process identified by uiPid. If the reference count
reaches 0 the handle base will be freed..
@Input psBase - pointer to a process handle base
@Inout uiPid - PID of a process
@Inout ui64MaxBridgeTime - maximum time a handle destroy operation
can hold the handle base lock (after that
time a lock will be release and reacquired
for another time slice)
@Return Error code or PVRSRV_OK
******************************************************************************/
PVRSRV_ERROR PVRSRVReleaseProcessHandleBase(PROCESS_HANDLE_BASE *psBase, IMG_PID uiPid,
IMG_UINT64 ui64MaxBridgeTime)
{
PVRSRV_ERROR eError;
IMG_INT iRefCount;
uintptr_t uiHashValue;
OSLockAcquire(g_hProcessHandleBaseLock);
iRefCount = OSAtomicDecrement(&psBase->iRefCount);
if (iRefCount != 0)
{
OSLockRelease(g_hProcessHandleBaseLock);
return PVRSRV_OK;
}
/* in case the refcount becomes 0 we can remove the process handle base
* and all related objects */
uiHashValue = HASH_Remove(g_psProcessHandleBaseTable, uiPid);
OSLockRelease(g_hProcessHandleBaseLock);
PVR_LOG_RETURN_IF_FALSE(uiHashValue != 0, "HASH_Remove failed",
PVRSRV_ERROR_UNABLE_TO_REMOVE_HASH_VALUE);
eError = PVRSRVFreeKernelHandles(psBase->psHandleBase);
PVR_LOG_RETURN_IF_ERROR(eError, "PVRSRVFreeKernelHandles");
eError = PVRSRVFreeHandleBase(psBase->psHandleBase, ui64MaxBridgeTime);
PVR_LOG_RETURN_IF_ERROR(eError, "PVRSRVFreeHandleBase");
OSFreeMem(psBase);
return PVRSRV_OK;
}
/*!
*******************************************************************************
@Function PVRSRVFreeHandleBase
@@ -2120,20 +2283,21 @@ PVRSRV_ERROR PVRSRVFreeHandleBase(PVRSRV_HANDLE_BASE *psBase, IMG_UINT64 ui64Max
FREE_HANDLE_DATA sHandleData = {NULL};
IMG_UINT32 i;
PVRSRV_ERROR eError;
PVRSRV_DATA *psPVRSRVData = PVRSRVGetPVRSRVData();
IMG_PID uiCleanupPid = psPVRSRVData->cleanupThreadPid;
IMG_PID uiCleanupPid = PVRSRVCleanupThreadGetPid();
uintptr_t uiCleanupTid = PVRSRVCleanupThreadGetTid();
PVR_ASSERT(gpsHandleFuncs);
/* LockHandle(psBase); - func only run in single thread ctx */
LockHandle(psBase);
/* If this is a process handle base being freed by the cleanup
* thread, store this in psPVRSRVData->psProcessHandleBaseBeingFreed
* thread, store this in g_psProcessHandleBaseBeingFreed
*/
if ((OSGetCurrentClientProcessIDKM() == uiCleanupPid) &&
if ((OSGetCurrentProcessID() == uiCleanupPid) &&
(OSGetCurrentThreadID() == uiCleanupTid) &&
(psBase->eType == PVRSRV_HANDLE_BASE_TYPE_PROCESS))
{
psPVRSRVData->psProcessHandleBaseBeingFreed = psBase;
g_psProcessHandleBaseBeingFreed = psBase;
}
sHandleData.psBase = psBase;
@@ -2152,7 +2316,7 @@ PVRSRV_ERROR PVRSRVFreeHandleBase(PVRSRV_HANDLE_BASE *psBase, IMG_UINT64 ui64Max
if (sCountData.uiHandleDataCount != 0)
{
IMG_BOOL bList = sCountData.uiHandleDataCount < HANDLE_DEBUG_LISTING_MAX_NUM;
IMG_BOOL bList = (IMG_BOOL)(sCountData.uiHandleDataCount < HANDLE_DEBUG_LISTING_MAX_NUM);
PVR_DPF((PVR_DBG_WARNING,
"%s: %u remaining handles in handle base 0x%p "
@@ -2200,18 +2364,19 @@ PVRSRV_ERROR PVRSRVFreeHandleBase(PVRSRV_HANDLE_BASE *psBase, IMG_UINT64 ui64Max
eError = gpsHandleFuncs->pfnDestroyHandleBase(psBase->psImplBase);
PVR_GOTO_IF_ERROR(eError, ExitUnlock);
/* UnlockHandle(psBase); - func only run in single thread ctx */
UnlockHandle(psBase);
OSLockDestroy(psBase->hLock);
OSFreeMem(psBase);
return eError;
ExitUnlock:
if (OSGetCurrentClientProcessIDKM() == uiCleanupPid)
if ((OSGetCurrentProcessID() == uiCleanupPid) &&
(OSGetCurrentThreadID() == uiCleanupTid))
{
psPVRSRVData->psProcessHandleBaseBeingFreed = NULL;
g_psProcessHandleBaseBeingFreed = NULL;
}
/* UnlockHandle(psBase); - func only run in single thread ctx */
UnlockHandle(psBase);
return eError;
}
@@ -2228,10 +2393,15 @@ PVRSRV_ERROR PVRSRVHandleInit(void)
PVR_ASSERT(gpsKernelHandleBase == NULL);
PVR_ASSERT(gpsHandleFuncs == NULL);
PVR_ASSERT(g_hProcessHandleBaseLock == NULL);
PVR_ASSERT(g_psProcessHandleBaseTable == NULL);
PVR_ASSERT(!gbLockInitialised);
eError = OSLockCreate(&gKernelHandleLock);
PVR_LOG_RETURN_IF_ERROR(eError, "OSLockCreate");
PVR_LOG_RETURN_IF_ERROR(eError, "OSLockCreate:1");
eError = OSLockCreate(&g_hProcessHandleBaseLock);
PVR_LOG_GOTO_IF_ERROR(eError, "OSLockCreate:2", ErrorHandleDeinit);
gbLockInitialised = IMG_TRUE;
@@ -2242,9 +2412,11 @@ PVRSRV_ERROR PVRSRVHandleInit(void)
PVRSRV_HANDLE_BASE_TYPE_GLOBAL);
PVR_LOG_GOTO_IF_ERROR(eError, "PVRSRVAllocHandleBase", ErrorHandleDeinit);
g_psProcessHandleBaseTable = HASH_Create(HANDLE_PROC_HANDLE_HASH_INIT_SIZE);
PVR_LOG_GOTO_IF_NOMEM(g_psProcessHandleBaseTable, eError, ErrorHandleDeinit);
eError = gpsHandleFuncs->pfnEnableHandlePurging(gpsKernelHandleBase->psImplBase);
PVR_LOG_GOTO_IF_ERROR(eError, "pfnEnableHandlePurging",
ErrorHandleDeinit);
PVR_LOG_GOTO_IF_ERROR(eError, "pfnEnableHandlePurging", ErrorHandleDeinit);
return PVRSRV_OK;
@@ -2290,7 +2462,19 @@ PVRSRV_ERROR PVRSRVHandleDeInit(void)
PVR_ASSERT(gpsKernelHandleBase == NULL);
}
if (gbLockInitialised)
if (g_psProcessHandleBaseTable != NULL)
{
HASH_Delete(g_psProcessHandleBaseTable);
g_psProcessHandleBaseTable = NULL;
}
if (g_hProcessHandleBaseLock != NULL)
{
OSLockDestroy(g_hProcessHandleBaseLock);
g_hProcessHandleBaseLock = NULL;
}
if (gKernelHandleLock != NULL)
{
OSLockDestroy(gKernelHandleLock);
gbLockInitialised = IMG_FALSE;

15
drivers/gpu/drm/img-rogue/handle.h
View File

@@ -99,7 +99,7 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
* Given a handle for a resource of type eType, return the pointer to the
* resource.
*
* PVRSRV_ERROR PVRSRVLookuSubHandle(PVRSRV_HANDLE_BASE *psBase,
* PVRSRV_ERROR PVRSRVLookupSubHandle(PVRSRV_HANDLE_BASE *psBase,
* void **ppvData, IMG_HANDLE hHandle, PVRSRV_HANDLE_TYPE eType,
* IMH_HANDLE hAncestor);
*
@@ -152,7 +152,6 @@ typedef struct _PROCESS_HANDLE_BASE_
{
PVRSRV_HANDLE_BASE *psHandleBase;
ATOMIC_T iRefCount;
} PROCESS_HANDLE_BASE;
extern PVRSRV_HANDLE_BASE *gpsKernelHandleBase;
@@ -176,9 +175,12 @@ PVRSRV_ERROR PVRSRVLookupHandleUnlocked(PVRSRV_HANDLE_BASE *psBase, void **ppvDa
PVRSRV_ERROR PVRSRVLookupSubHandle(PVRSRV_HANDLE_BASE *psBase, void **ppvData, IMG_HANDLE hHandle, PVRSRV_HANDLE_TYPE eType, IMG_HANDLE hAncestor);
PVRSRV_ERROR PVRSRVReleaseHandle(PVRSRV_HANDLE_BASE *psBase, IMG_HANDLE hHandle, PVRSRV_HANDLE_TYPE eType);
PVRSRV_ERROR PVRSRVReleaseHandleUnlocked(PVRSRV_HANDLE_BASE *psBase, IMG_HANDLE hHandle, PVRSRV_HANDLE_TYPE eType);
PVRSRV_ERROR PVRSRVReleaseHandleStagedUnlock(PVRSRV_HANDLE_BASE *psBase, IMG_HANDLE hHandle, PVRSRV_HANDLE_TYPE eType);
void PVRSRVReleaseHandle(PVRSRV_HANDLE_BASE *psBase, IMG_HANDLE hHandle, PVRSRV_HANDLE_TYPE eType);
void PVRSRVReleaseHandleUnlocked(PVRSRV_HANDLE_BASE *psBase, IMG_HANDLE hHandle, PVRSRV_HANDLE_TYPE eType);
PVRSRV_ERROR PVRSRVDestroyHandle(PVRSRV_HANDLE_BASE *psBase, IMG_HANDLE hHandle, PVRSRV_HANDLE_TYPE eType);
PVRSRV_ERROR PVRSRVDestroyHandleUnlocked(PVRSRV_HANDLE_BASE *psBase, IMG_HANDLE hHandle, PVRSRV_HANDLE_TYPE eType);
PVRSRV_ERROR PVRSRVDestroyHandleStagedUnlocked(PVRSRV_HANDLE_BASE *psBase, IMG_HANDLE hHandle, PVRSRV_HANDLE_TYPE eType);
PVRSRV_ERROR PVRSRVPurgeHandles(PVRSRV_HANDLE_BASE *psBase);
@@ -195,6 +197,9 @@ PVRSRV_ERROR PVRSRVHandleDeInit(void);
PVRSRV_HANDLE_BASE *PVRSRVRetrieveProcessHandleBase(void);
PVRSRV_ERROR PVRSRVAcquireProcessHandleBase(IMG_PID uiPid, PROCESS_HANDLE_BASE **ppsBase);
PVRSRV_ERROR PVRSRVReleaseProcessHandleBase(PROCESS_HANDLE_BASE *psBase, IMG_PID uiPid, IMG_UINT64 ui64MaxBridgeTime);
void LockHandle(PVRSRV_HANDLE_BASE *psBase);
void UnlockHandle(PVRSRV_HANDLE_BASE *psBase);

3
drivers/gpu/drm/img-rogue/handle_types.h
View File

@@ -63,6 +63,9 @@ HANDLETYPE(RGX_SERVER_TQ_TDM_CONTEXT)
HANDLETYPE(RGX_SERVER_COMPUTE_CONTEXT)
HANDLETYPE(RGX_SERVER_RAY_CONTEXT)
HANDLETYPE(RGX_SERVER_KICKSYNC_CONTEXT)
#if defined(PVR_TESTING_UTILS) && defined(SUPPORT_VALIDATION)
HANDLETYPE(RGX_SERVER_GPUMAP_CONTEXT)
#endif
HANDLETYPE(SYNC_PRIMITIVE_BLOCK)
HANDLETYPE(SYNC_RECORD_HANDLE)
HANDLETYPE(PVRSRV_TIMELINE_SERVER)

13
drivers/gpu/drm/img-rogue/htbuffer.c
View File

@@ -45,7 +45,18 @@ IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/ /**************************************************************************/
#include <stdarg.h>
#if defined(__linux__)
#include <linux/version.h>
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 15, 0))
#include <linux/stdarg.h>
#else
#include <stdarg.h>
#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(5, 15, 0) */
#else
#include <stdarg.h>
#endif /* __linux__ */
#include "htbuffer.h"
#include "osfunc.h"
#include "client_htbuffer_bridge.h"

20
drivers/gpu/drm/img-rogue/img_defs.h
View File

@@ -150,19 +150,19 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
do { \
assert(!(msg)); \
__builtin_unreachable(); \
} while (0)
} while (false)
#elif defined(_MSC_VER)
#define unreachable(msg) \
do { \
assert(!(msg)); \
__assume(0); \
} while (0)
} while (false)
#else
#define unreachable(msg) \
do { \
assert(!(msg)); \
while (1); \
} while (0)
} while (false)
#endif
/*
@@ -175,13 +175,13 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
do { \
assert(expr); \
__builtin_assume(expr); \
} while (0)
} while (false)
#elif defined(_MSC_VER)
#define assume(expr) \
do { \
assert(expr); \
__assume(expr); \
} while (0)
} while (false)
#elif defined(__linux__) && defined(__KERNEL__)
#define assume(expr) ((void)(expr))
#elif GCC_VERSION_AT_LEAST(4, 5) || has_clang_builtin(__builtin_unreachable)
@@ -189,7 +189,7 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
do { \
if (unlikely(!(expr))) \
unreachable("Assumption isn't true: " # expr); \
} while (0)
} while (false)
#else
#define assume(expr) assert(expr)
#endif
@@ -506,6 +506,7 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define VG_MARK_INITIALIZED(pvData,ui32Size) VALGRIND_MAKE_MEM_DEFINED(pvData,ui32Size)
#define VG_MARK_NOACCESS(pvData,ui32Size) VALGRIND_MAKE_MEM_NOACCESS(pvData,ui32Size)
#define VG_MARK_ACCESS(pvData,ui32Size) VALGRIND_MAKE_MEM_UNDEFINED(pvData,ui32Size)
#define VG_ASSERT_DEFINED(pvData,ui32Size) VALGRIND_CHECK_MEM_IS_DEFINED(pvData,ui32Size)
#else
#if defined(_MSC_VER)
# define PVR_MSC_SUPPRESS_4127 __pragma(warning(suppress:4127))
@@ -513,9 +514,10 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
# define PVR_MSC_SUPPRESS_4127
#endif
#define VG_MARK_INITIALIZED(pvData,ui32Size) PVR_MSC_SUPPRESS_4127 do { } while (0)
#define VG_MARK_NOACCESS(pvData,ui32Size) PVR_MSC_SUPPRESS_4127 do { } while (0)
#define VG_MARK_ACCESS(pvData,ui32Size) PVR_MSC_SUPPRESS_4127 do { } while (0)
#define VG_MARK_INITIALIZED(pvData,ui32Size) PVR_MSC_SUPPRESS_4127 do { } while (false)
#define VG_MARK_NOACCESS(pvData,ui32Size) PVR_MSC_SUPPRESS_4127 do { } while (false)
#define VG_MARK_ACCESS(pvData,ui32Size) PVR_MSC_SUPPRESS_4127 do { } while (false)
#define VG_ASSERT_DEFINED(pvData,ui32Size) PVR_MSC_SUPPRESS_4127 do { } while (false)
#endif
#define IMG_STRINGIFY_IMPL(x) # x

12
drivers/gpu/drm/img-rogue/img_types.h
View File

@@ -254,13 +254,19 @@ typedef struct
{
#if defined(UNDER_WDDM) || defined(WINDOWS_WDF)
uintptr_t uiAddr;
#define IMG_CAST_TO_CPUPHYADDR_UINT(var) (uintptr_t)(var)
#define IMG_CAST_TO_CPUPHYADDR_UINT(var) (uintptr_t)(var)
#define CPUPHYADDR_FMTARG(var) (IMG_UINT64)(var)
#define CPUPHYADDR_UINT_FMTSPEC "0x%016" IMG_UINT64_FMTSPECx
#elif defined(__linux__) && defined(__KERNEL__)
phys_addr_t uiAddr;
#define IMG_CAST_TO_CPUPHYADDR_UINT(var) (phys_addr_t)(var)
#define IMG_CAST_TO_CPUPHYADDR_UINT(var) (phys_addr_t)(var)
#define CPUPHYADDR_FMTARG(var) (&var)
#define CPUPHYADDR_UINT_FMTSPEC "%pa"
#else
IMG_UINT64 uiAddr;
#define IMG_CAST_TO_CPUPHYADDR_UINT(var) (IMG_UINT64)(var)
#define IMG_CAST_TO_CPUPHYADDR_UINT(var) (IMG_UINT64)(var)
#define CPUPHYADDR_FMTARG(var) (var)
#define CPUPHYADDR_UINT_FMTSPEC "0x%016" IMG_UINT64_FMTSPECx
#endif
} IMG_CPU_PHYADDR;

2
drivers/gpu/drm/img-rogue/include/devicemem_typedefs.h
View File

@@ -137,6 +137,6 @@ typedef IMG_UINT32 SPARSE_MEM_RESIZE_FLAGS;
/* Defines the max length for PMR, MemDesc, Device memory History and RI debug
* annotations stored in memory, including the null terminator.
*/
#define DEVMEM_ANNOTATION_MAX_LEN (PVR_ANNOTATION_MAX_LEN + 1U)
#define DEVMEM_ANNOTATION_MAX_LEN ((IMG_UINT32)PVR_ANNOTATION_MAX_LEN + 1U)
#endif /* #ifndef DEVICEMEM_TYPEDEFS_H */

18
drivers/gpu/drm/img-rogue/include/drm/pvr_drm.h
View File

@@ -89,6 +89,17 @@ struct pvr_sw_timeline_advance_data {
__u64 sync_pt_idx;
};
#define PVR_SRVKM_SERVICES_INIT 1
#define PVR_SRVKM_SYNC_INIT 2
struct drm_pvr_srvkm_init_data {
__u32 init_module;
};
/* Values used to configure the PVRSRV_DEVICE_INIT_MODE tunable (Linux-only) */
#define PVRSRV_LINUX_DEV_INIT_ON_PROBE 1
#define PVRSRV_LINUX_DEV_INIT_ON_OPEN 2
#define PVRSRV_LINUX_DEV_INIT_ON_CONNECT 3
/*
* DRM command numbers, relative to DRM_COMMAND_BASE.
* These defines must be prefixed with "DRM_".
@@ -105,6 +116,9 @@ struct pvr_sw_timeline_advance_data {
#define DRM_PVR_SW_SYNC_CREATE_FENCE_CMD 3
#define DRM_PVR_SW_SYNC_INC_CMD 4
/* PVR Services Render Device Init command */
#define DRM_PVR_SRVKM_INIT 5
/* These defines must be prefixed with "DRM_IOCTL_". */
#define DRM_IOCTL_PVR_SRVKM_CMD \
DRM_IOWR(DRM_COMMAND_BASE + DRM_PVR_SRVKM_CMD, \
@@ -125,4 +139,8 @@ struct pvr_sw_timeline_advance_data {
DRM_IOR(DRM_COMMAND_BASE + DRM_PVR_SW_SYNC_INC_CMD, \
struct pvr_sw_timeline_advance_data)
#define DRM_IOCTL_PVR_SRVKM_INIT \
DRM_IOW(DRM_COMMAND_BASE + DRM_PVR_SRVKM_INIT, \
struct drm_pvr_srvkm_init_data)
#endif /* defined(__PVR_DRM_H__) */

20
drivers/gpu/drm/img-rogue/include/img_defs.h
View File

@@ -150,19 +150,19 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
do { \
assert(!(msg)); \
__builtin_unreachable(); \
} while (0)
} while (false)
#elif defined(_MSC_VER)
#define unreachable(msg) \
do { \
assert(!(msg)); \
__assume(0); \
} while (0)
} while (false)
#else
#define unreachable(msg) \
do { \
assert(!(msg)); \
while (1); \
} while (0)
} while (false)
#endif
/*
@@ -175,13 +175,13 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
do { \
assert(expr); \
__builtin_assume(expr); \
} while (0)
} while (false)
#elif defined(_MSC_VER)
#define assume(expr) \
do { \
assert(expr); \
__assume(expr); \
} while (0)
} while (false)
#elif defined(__linux__) && defined(__KERNEL__)
#define assume(expr) ((void)(expr))
#elif GCC_VERSION_AT_LEAST(4, 5) || has_clang_builtin(__builtin_unreachable)
@@ -189,7 +189,7 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
do { \
if (unlikely(!(expr))) \
unreachable("Assumption isn't true: " # expr); \
} while (0)
} while (false)
#else
#define assume(expr) assert(expr)
#endif
@@ -506,6 +506,7 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define VG_MARK_INITIALIZED(pvData,ui32Size) VALGRIND_MAKE_MEM_DEFINED(pvData,ui32Size)
#define VG_MARK_NOACCESS(pvData,ui32Size) VALGRIND_MAKE_MEM_NOACCESS(pvData,ui32Size)
#define VG_MARK_ACCESS(pvData,ui32Size) VALGRIND_MAKE_MEM_UNDEFINED(pvData,ui32Size)
#define VG_ASSERT_DEFINED(pvData,ui32Size) VALGRIND_CHECK_MEM_IS_DEFINED(pvData,ui32Size)
#else
#if defined(_MSC_VER)
# define PVR_MSC_SUPPRESS_4127 __pragma(warning(suppress:4127))
@@ -513,9 +514,10 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
# define PVR_MSC_SUPPRESS_4127
#endif
#define VG_MARK_INITIALIZED(pvData,ui32Size) PVR_MSC_SUPPRESS_4127 do { } while (0)
#define VG_MARK_NOACCESS(pvData,ui32Size) PVR_MSC_SUPPRESS_4127 do { } while (0)
#define VG_MARK_ACCESS(pvData,ui32Size) PVR_MSC_SUPPRESS_4127 do { } while (0)
#define VG_MARK_INITIALIZED(pvData,ui32Size) PVR_MSC_SUPPRESS_4127 do { } while (false)
#define VG_MARK_NOACCESS(pvData,ui32Size) PVR_MSC_SUPPRESS_4127 do { } while (false)
#define VG_MARK_ACCESS(pvData,ui32Size) PVR_MSC_SUPPRESS_4127 do { } while (false)
#define VG_ASSERT_DEFINED(pvData,ui32Size) PVR_MSC_SUPPRESS_4127 do { } while (false)
#endif
#define IMG_STRINGIFY_IMPL(x) # x

4
drivers/gpu/drm/img-rogue/include/img_drm_fourcc_internal.h
View File

@@ -61,7 +61,7 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#define DRM_FORMAT_MOD_PVR_FBCDC_8x8_V0 fourcc_mod_code(PVR, 1)
#define DRM_FORMAT_MOD_PVR_FBCDC_8x8_V0_FIX fourcc_mod_code(PVR, 2) /* Fix for HW_BRN_37464 */
#define DRM_FORMAT_MOD_PVR_FBCDC_8x8_V1 fourcc_mod_code(PVR, 3)
/* DRM_FORMAT_MOD_PVR_FBCDC_8x8_V1 - moved to the public header */
#define DRM_FORMAT_MOD_PVR_FBCDC_8x8_V2 fourcc_mod_code(PVR, 4)
#define DRM_FORMAT_MOD_PVR_FBCDC_8x8_V3 fourcc_mod_code(PVR, 5)
/* DRM_FORMAT_MOD_PVR_FBCDC_8x8_V7 - moved to the public header */
@@ -74,7 +74,7 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
/* DRM_FORMAT_MOD_PVR_FBCDC_8x8_LOSSY75_V13 - moved to the public header */
#define DRM_FORMAT_MOD_PVR_FBCDC_16x4_V0 fourcc_mod_code(PVR, 7)
#define DRM_FORMAT_MOD_PVR_FBCDC_16x4_V0_FIX fourcc_mod_code(PVR, 8) /* Fix for HW_BRN_37464 */
#define DRM_FORMAT_MOD_PVR_FBCDC_16x4_V1 fourcc_mod_code(PVR, 9)
/* DRM_FORMAT_MOD_PVR_FBCDC_16x4_V1 - moved to the public header */
#define DRM_FORMAT_MOD_PVR_FBCDC_16x4_V2 fourcc_mod_code(PVR, 10)
#define DRM_FORMAT_MOD_PVR_FBCDC_16x4_V3 fourcc_mod_code(PVR, 11)
/* DRM_FORMAT_MOD_PVR_FBCDC_16x4_V7 - moved to the public header */

12
drivers/gpu/drm/img-rogue/include/img_types.h
View File

@@ -254,13 +254,19 @@ typedef struct
{
#if defined(UNDER_WDDM) || defined(WINDOWS_WDF)
uintptr_t uiAddr;
#define IMG_CAST_TO_CPUPHYADDR_UINT(var) (uintptr_t)(var)
#define IMG_CAST_TO_CPUPHYADDR_UINT(var) (uintptr_t)(var)
#define CPUPHYADDR_FMTARG(var) (IMG_UINT64)(var)
#define CPUPHYADDR_UINT_FMTSPEC "0x%016" IMG_UINT64_FMTSPECx
#elif defined(__linux__) && defined(__KERNEL__)
phys_addr_t uiAddr;
#define IMG_CAST_TO_CPUPHYADDR_UINT(var) (phys_addr_t)(var)
#define IMG_CAST_TO_CPUPHYADDR_UINT(var) (phys_addr_t)(var)
#define CPUPHYADDR_FMTARG(var) (&var)
#define CPUPHYADDR_UINT_FMTSPEC "%pa"
#else
IMG_UINT64 uiAddr;
#define IMG_CAST_TO_CPUPHYADDR_UINT(var) (IMG_UINT64)(var)
#define IMG_CAST_TO_CPUPHYADDR_UINT(var) (IMG_UINT64)(var)
#define CPUPHYADDR_FMTARG(var) (var)
#define CPUPHYADDR_UINT_FMTSPEC "0x%016" IMG_UINT64_FMTSPECx
#endif
} IMG_CPU_PHYADDR;

14
drivers/gpu/drm/img-rogue/include/lock_types.h
View File

@@ -60,29 +60,29 @@ typedef atomic_t ATOMIC_T;
#else /* defined(__linux__) && defined(__KERNEL__) */
#include "img_types.h" /* needed for IMG_INT */
typedef struct _OS_LOCK_ *POS_LOCK;
typedef struct OS_LOCK_TAG *POS_LOCK;
#if defined(__linux__) || defined(__QNXNTO__) || defined(INTEGRITY_OS)
typedef struct _OSWR_LOCK_ *POSWR_LOCK;
typedef struct OSWR_LOCK_TAG *POSWR_LOCK;
#else /* defined(__linux__) || defined(__QNXNTO__) || defined(INTEGRITY_OS) */
typedef struct _OSWR_LOCK_ {
typedef struct OSWR_LOCK_TAG {
IMG_UINT32 ui32Dummy;
} *POSWR_LOCK;
#endif /* defined(__linux__) || defined(__QNXNTO__) || defined(INTEGRITY_OS) */
#if defined(__linux__)
typedef struct _OS_ATOMIC {IMG_INT32 counter;} ATOMIC_T;
typedef struct OS_ATOMIC_TAG {IMG_INT32 counter;} ATOMIC_T;
#elif defined(__QNXNTO__)
typedef struct _OS_ATOMIC {IMG_INT32 counter;} ATOMIC_T;
typedef struct OS_ATOMIC_TAG {IMG_INT32 counter;} ATOMIC_T;
#elif defined(_WIN32)
/*
* Dummy definition. WDDM doesn't use Services, but some headers
* still have to be shared. This is one such case.
*/
typedef struct _OS_ATOMIC {IMG_INT32 counter;} ATOMIC_T;
typedef struct OS_ATOMIC_TAG {IMG_INT32 counter;} ATOMIC_T;
#elif defined(INTEGRITY_OS)
/* Only lower 32bits are used in OS ATOMIC APIs to have consistent behaviour across all OS */
typedef struct _OS_ATOMIC {IMG_INT64 counter;} ATOMIC_T;
typedef struct OS_ATOMIC_TAG {IMG_INT64 counter;} ATOMIC_T;
#else
#error "Please type-define an atomic lock for this environment"
#endif

8
drivers/gpu/drm/img-rogue/include/log2.h
View File

@@ -270,7 +270,7 @@ static INLINE uint32_t __const_function FloorLog2(uint32_t n)
{
uint32_t ui32log2 = 0;
while (n >>= 1)
while ((n >>= 1) != 0U)
{
ui32log2++;
}
@@ -287,7 +287,7 @@ static INLINE uint32_t __const_function FloorLog2_64(uint64_t n)
{
uint32_t ui32log2 = 0;
while (n >>= 1)
while ((n >>= 1) != 0U)
{
ui32log2++;
}
@@ -311,7 +311,7 @@ static INLINE uint32_t __const_function CeilLog2(uint32_t n)
n--; /* Handle powers of 2 */
while (n)
while (n != 0U)
{
ui32log2++;
n >>= 1;
@@ -336,7 +336,7 @@ static INLINE uint32_t __const_function CeilLog2_64(uint64_t n)
n--; /* Handle powers of 2 */
while (n)
while (n != 0U)
{
ui32log2++;
n >>= 1;

48
drivers/gpu/drm/img-rogue/include/osfunc_common.h
View File

@@ -154,7 +154,14 @@ size_t StringLCopy(IMG_CHAR *pszDest, const IMG_CHAR *pszSrc, size_t uDataSize);
@Input c the number of bytes to be set to the given value
@Return Pointer to the destination memory.
*/ /**************************************************************************/
#define OSDeviceMemSet(a,b,c) memset((a), (b), (c))
#define OSDeviceMemSet(a,b,c) \
do { \
if ((c) != 0) \
{ \
(void) memset((a), (b), (c)); \
(void) *(volatile IMG_UINT32*)((void*)(a)); \
} \
} while (false)
/**************************************************************************/ /*!
@Function OSDeviceMemCopy
@@ -167,7 +174,14 @@ size_t StringLCopy(IMG_CHAR *pszDest, const IMG_CHAR *pszSrc, size_t uDataSize);
@Input c the number of bytes to be copied
@Return Pointer to the destination memory.
*/ /**************************************************************************/
#define OSDeviceMemCopy(a,b,c) memcpy((a), (b), (c))
#define OSDeviceMemCopy(a,b,c) \
do { \
if ((c) != 0) \
{ \
memcpy((a), (b), (c)); \
(void) *(volatile IMG_UINT32*)((void*)(a)); \
} \
} while (false)
#endif /* (defined(__arm64__) || defined(__aarch64__) || defined(PVRSRV_DEVMEM_TEST_SAFE_MEMSETCPY)) */
@@ -181,7 +195,7 @@ size_t StringLCopy(IMG_CHAR *pszDest, const IMG_CHAR *pszSrc, size_t uDataSize);
@Input c the number of bytes to be set to the given value
@Return Pointer to the destination memory.
*/ /**************************************************************************/
#define OSCachedMemSet(a,b,c) memset((a), (b), (c))
#define OSCachedMemSet(a,b,c) (void) memset((a), (b), (c))
/**************************************************************************/ /*!
@Function OSCachedMemCopy
@@ -210,12 +224,22 @@ size_t StringLCopy(IMG_CHAR *pszDest, const IMG_CHAR *pszSrc, size_t uDataSize);
@Input c the number of bytes to be set to the given value
@Return Pointer to the destination memory.
*/ /**************************************************************************/
#if !defined(SERVICES_SC)
#define OSCachedMemSetWMB(a,b,c) \
do { \
if ((c) != 0) \
{ \
(void) memset((a), (b), (c)); \
OSWriteMemoryBarrier(a); \
} \
} while (false)
#else
#define OSCachedMemSetWMB(a,b,c) \
do { \
(void) memset((a), (b), (c)); \
OSWriteMemoryBarrier(); \
} while (0)
} while (false)
#endif /* !defined(SERVICES_SC) */
/**************************************************************************/ /*!
@Function OSCachedMemCopy
@Description Copy values from one area of memory, to another, when both
@@ -228,12 +252,22 @@ size_t StringLCopy(IMG_CHAR *pszDest, const IMG_CHAR *pszSrc, size_t uDataSize);
@Input c the number of bytes to be copied
@Return Pointer to the destination memory.
*/ /**************************************************************************/
#if !defined(SERVICES_SC)
#define OSCachedMemCopyWMB(a,b,c) \
do { \
if ((c) != 0) \
{ \
(void) memcpy((a), (b), (c)); \
OSWriteMemoryBarrier(a); \
} \
} while (false)
#else
#define OSCachedMemCopyWMB(a,b,c) \
do { \
(void) memcpy((a), (b), (c)); \
OSWriteMemoryBarrier(); \
} while (0)
} while (false)
#endif /* !defined(SERVICES_SC) */
#endif /* defined(__KERNEL__) */
/**************************************************************************/ /*!

3
drivers/gpu/drm/img-rogue/include/public/powervr/img_drm_fourcc.h
View File

@@ -114,6 +114,9 @@ THE SOFTWARE.
#define DRM_FORMAT_MOD_LINEAR fourcc_mod_code(NONE, 0)
#endif
#define DRM_FORMAT_MOD_PVR_FBCDC_8x8_V1 fourcc_mod_code(PVR, 3)
#define DRM_FORMAT_MOD_PVR_FBCDC_16x4_V1 fourcc_mod_code(PVR, 9)
#define DRM_FORMAT_MOD_PVR_FBCDC_8x8_V7 fourcc_mod_code(PVR, 6)
#define DRM_FORMAT_MOD_PVR_FBCDC_16x4_V7 fourcc_mod_code(PVR, 12)

141
drivers/gpu/drm/img-rogue/include/pvr_debug.h
View File

@@ -119,7 +119,7 @@ __noreturn void klocwork_abort(void);
* them.
*/
#if defined(__KLOCWORK__)
#define PVR_ASSERT(x) do { if (!(x)) {klocwork_abort();} } while (0)
#define PVR_ASSERT(x) do { if (!(x)) {klocwork_abort();} } while (false)
#else /* ! __KLOCWORKS__ */
#if defined(_WIN32)
@@ -133,7 +133,7 @@ __noreturn void klocwork_abort(void);
__debugbreak(); \
} \
MSC_SUPPRESS_4127 \
} while (0)
} while (false)
#else
@@ -152,7 +152,7 @@ __noreturn void klocwork_abort(void);
"Debug assertion failed!"); \
WARN_ON(1); \
} \
} while (0)
} while (false)
#else /* defined(__linux__) && defined(__KERNEL__) */
@@ -177,14 +177,14 @@ PVRSRVDebugAssertFail(const IMG_CHAR *pszFile,
{ \
PVRSRVDebugAssertFail(__FILE__, __LINE__, #EXPR); \
} \
} while (0)
} while (false)
#endif /* defined(__linux__) && defined(__KERNEL__) */
#endif /* defined(_WIN32) */
#endif /* defined(__KLOCWORK__) */
#if defined(__KLOCWORK__)
#define PVR_DBG_BREAK do { klocwork_abort(); } while (0)
#define PVR_DBG_BREAK do { klocwork_abort(); } while (false)
#else
#if defined(WIN32)
#define PVR_DBG_BREAK __debugbreak() /*!< Implementation of PVR_DBG_BREAK for (non-WinCE) Win32 */
@@ -214,8 +214,8 @@ PVRSRVDebugAssertFail(const IMG_CHAR *pszFile,
* macros in a special way when the code is analysed by Klocwork avoids
* them.
*/
#if defined(__KLOCWORK__)
#define PVR_ASSERT(EXPR) do { if (!(EXPR)) {klocwork_abort();} } while (0)
#if defined(__KLOCWORK__) && !defined(SERVICES_SC)
#define PVR_ASSERT(EXPR) do { if (!(EXPR)) {klocwork_abort();} } while (false)
#else
#define PVR_ASSERT(EXPR) (void)(EXPR) /*!< Null Implementation of PVR_ASSERT (does nothing) */
#endif
@@ -294,21 +294,21 @@ PVRSRVDebugAssertFail(const IMG_CHAR *pszFile,
PVR_DPF((PVR_DBG_ERROR, "%s() failed (%s) in %s()", _call, PVRSRVGETERRORSTRING(_rc), __func__)); \
} \
MSC_SUPPRESS_4127\
} while (0)
} while (false)
#define PVR_WARN_IF_ERROR(_rc, _call) do \
{ if (unlikely(_rc != PVRSRV_OK)) { \
PVR_DPF((PVR_DBG_WARNING, "%s() failed (%s) in %s()", _call, PVRSRVGETERRORSTRING(_rc), __func__)); \
} \
MSC_SUPPRESS_4127\
} while (0)
} while (false)
#define PVR_LOG_RETURN_IF_NOMEM(_expr, _call) do \
{ if (unlikely(_expr == NULL)) { \
PVR_DPF((PVR_DBG_ERROR, "%s failed (PVRSRV_ERROR_OUT_OF_MEMORY) in %s()", _call, __func__)); \
return PVRSRV_ERROR_OUT_OF_MEMORY; } \
MSC_SUPPRESS_4127\
} while (0)
} while (false)
#define PVR_LOG_GOTO_IF_NOMEM(_expr, _err, _go) do \
{ if (unlikely(_expr == NULL)) { \
@@ -316,70 +316,70 @@ PVRSRVDebugAssertFail(const IMG_CHAR *pszFile,
_err = PVRSRV_ERROR_OUT_OF_MEMORY; \
goto _go; } \
MSC_SUPPRESS_4127\
} while (0)
} while (false)
#define PVR_LOG_RETURN_IF_ERROR(_rc, _call) do \
{ if (unlikely(_rc != PVRSRV_OK)) { \
PVR_DPF((PVR_DBG_ERROR, "%s() failed (%s) in %s()", _call, PVRSRVGETERRORSTRING(_rc), __func__)); \
return _rc; } \
MSC_SUPPRESS_4127\
} while (0)
} while (false)
#define PVR_LOG_RETURN_VOID_IF_ERROR(_rc, _call) do \
{ if (unlikely(_rc != PVRSRV_OK)) { \
PVR_DPF((PVR_DBG_ERROR, "%s() failed (%s) in %s()", _call, PVRSRVGETERRORSTRING(_rc), __func__)); \
return; } \
MSC_SUPPRESS_4127\
} while (0)
} while (false)
#define PVR_LOG_GOTO_IF_ERROR(_rc, _call, _go) do \
{ if (unlikely(_rc != PVRSRV_OK)) { \
PVR_DPF((PVR_DBG_ERROR, "%s() failed (%s) in %s()", _call, PVRSRVGETERRORSTRING(_rc), __func__)); \
goto _go; } \
MSC_SUPPRESS_4127\
} while (0)
} while (false)
#define PVR_LOG_GOTO_WITH_ERROR(_call, _err, _rc, _go) do \
{ PVR_DPF((PVR_DBG_ERROR, "%s() failed (%s) in %s()", _call, PVRSRVGETERRORSTRING(_rc), __func__)); \
_err = _rc; \
goto _go; \
MSC_SUPPRESS_4127\
} while (0)
} while (false)
#define PVR_LOG_IF_FALSE(_expr, _msg) do \
{ if (unlikely(!(_expr))) { \
PVR_DPF((PVR_DBG_ERROR, "%s in %s()", _msg, __func__)); \
} \
MSC_SUPPRESS_4127\
} while (0)
} while (false)
#define PVR_LOG_RETURN_IF_FALSE(_expr, _msg, _rc) do \
{ if (unlikely(!(_expr))) { \
PVR_DPF((PVR_DBG_ERROR, "%s in %s()", _msg, __func__)); \
return _rc; } \
MSC_SUPPRESS_4127\
} while (0)
} while (false)
#define PVR_LOG_RETURN_VOID_IF_FALSE(_expr, _msg) do \
{ if (unlikely(!(_expr))) { \
PVR_DPF((PVR_DBG_ERROR, "%s in %s()", _msg, __func__)); \
return; } \
MSC_SUPPRESS_4127\
} while (0)
} while (false)
#define PVR_LOG_GOTO_IF_FALSE(_expr, _msg, _go) do \
{ if (unlikely(!(_expr))) { \
PVR_DPF((PVR_DBG_ERROR, "%s in %s()", _msg, __func__)); \
goto _go; } \
MSC_SUPPRESS_4127\
} while (0)
} while (false)
#define PVR_LOG_RETURN_IF_INVALID_PARAM(_expr, _param) do \
{ if (unlikely(!(_expr))) { \
PVR_DPF((PVR_DBG_ERROR, "%s invalid in %s()", _param, __func__)); \
return PVRSRV_ERROR_INVALID_PARAMS; } \
MSC_SUPPRESS_4127\
} while (0)
} while (false)
#define PVR_LOG_GOTO_IF_INVALID_PARAM(_expr, _err, _go) do \
{ if (unlikely(!(_expr))) { \
@@ -387,7 +387,7 @@ PVRSRVDebugAssertFail(const IMG_CHAR *pszFile,
_err = PVRSRV_ERROR_INVALID_PARAMS; \
goto _go; } \
MSC_SUPPRESS_4127\
} while (0)
} while (false)
#define PVR_LOG_MSG(_lvl, _msg) \
PVR_DPF((_lvl, ("In %s() "_msg), __func__))
@@ -400,42 +400,42 @@ PVRSRVDebugAssertFail(const IMG_CHAR *pszFile,
PVR_DPF((_lvl, ("In %s() "_msg), __func__, __VA_ARGS__)); \
} \
MSC_SUPPRESS_4127\
} while (0)
} while (false)
#define PVR_LOG_IF_FALSE_VA(_lvl, _expr, _msg, ...) do \
{ if (unlikely(!(_expr))) { \
PVR_DPF((_lvl, ("In %s() "_msg), __func__, __VA_ARGS__)); \
} \
MSC_SUPPRESS_4127\
} while (0)
} while (false)
#define PVR_LOG_RETURN_IF_ERROR_VA(_rc, _msg, ...) do \
{ if (unlikely(_rc != PVRSRV_OK)) { \
PVR_DPF((PVR_DBG_ERROR, ("In %s() "_msg), __func__, __VA_ARGS__)); \
return _rc; \
} MSC_SUPPRESS_4127\
} while (0)
} while (false)
#define PVR_LOG_GOTO_IF_ERROR_VA(_rc, _go, _msg, ...) do \
{ if (unlikely(_rc != PVRSRV_OK)) { \
PVR_DPF((PVR_DBG_ERROR, ("In %s() "_msg), __func__, __VA_ARGS__)); \
goto _go; \
} MSC_SUPPRESS_4127\
} while (0)
} while (false)
#define PVR_LOG_RETURN_IF_FALSE_VA(_expr, _rc, _msg, ...) do \
{ if (unlikely(!(_expr))) { \
PVR_DPF((PVR_DBG_ERROR, ("At %s: "_msg), __func__, __VA_ARGS__)); \
return _rc; \
} MSC_SUPPRESS_4127\
} while (0)
} while (false)
#define PVR_LOG_GOTO_IF_FALSE_VA(_expr, _go, _msg, ...) do \
{ if (unlikely(!(_expr))) { \
PVR_DPF((PVR_DBG_ERROR, ("In %s() "_msg), __func__, __VA_ARGS__)); \
goto _go; \
} MSC_SUPPRESS_4127\
} while (0)
} while (false)
#else /* defined(PVRSRV_NEED_PVR_DPF) */
@@ -450,27 +450,27 @@ PVRSRVDebugAssertFail(const IMG_CHAR *pszFile,
#define PVR_LOG_IF_ERROR_VA(_lvl, _rc, _msg, ...) (void)(_rc)
#define PVR_LOG_IF_FALSE_VA(_lvl, _expr, _msg, ...) (void)(_expr)
#define PVR_LOG_RETURN_IF_NOMEM(_expr, _call) do { if (unlikely(_expr == NULL)) { return PVRSRV_ERROR_OUT_OF_MEMORY; } MSC_SUPPRESS_4127 } while (0)
#define PVR_LOG_GOTO_IF_NOMEM(_expr, _err, _go) do { if (unlikely(_expr == NULL)) { _err = PVRSRV_ERROR_OUT_OF_MEMORY; goto _go; } MSC_SUPPRESS_4127 } while (0)
#define PVR_LOG_RETURN_IF_NOMEM(_expr, _call) do { if (unlikely(_expr == NULL)) { return PVRSRV_ERROR_OUT_OF_MEMORY; } MSC_SUPPRESS_4127 } while (false)
#define PVR_LOG_GOTO_IF_NOMEM(_expr, _err, _go) do { if (unlikely(_expr == NULL)) { _err = PVRSRV_ERROR_OUT_OF_MEMORY; goto _go; } MSC_SUPPRESS_4127 } while (false)
#define PVR_LOG_RETURN_IF_ERROR(_rc, _call) do { if (unlikely(_rc != PVRSRV_OK)) { return (_rc); } MSC_SUPPRESS_4127 } while (0)
#define PVR_LOG_RETURN_IF_ERROR_VA(_rc, _msg, ...) do { if (unlikely(_rc != PVRSRV_OK)) { return (_rc); } MSC_SUPPRESS_4127 } while (0)
#define PVR_LOG_RETURN_VOID_IF_ERROR(_rc, _call) do { if (unlikely(_rc != PVRSRV_OK)) { return; } MSC_SUPPRESS_4127 } while (0)
#define PVR_LOG_RETURN_IF_ERROR(_rc, _call) do { if (unlikely(_rc != PVRSRV_OK)) { return (_rc); } MSC_SUPPRESS_4127 } while (false)
#define PVR_LOG_RETURN_IF_ERROR_VA(_rc, _msg, ...) do { if (unlikely(_rc != PVRSRV_OK)) { return (_rc); } MSC_SUPPRESS_4127 } while (false)
#define PVR_LOG_RETURN_VOID_IF_ERROR(_rc, _call) do { if (unlikely(_rc != PVRSRV_OK)) { return; } MSC_SUPPRESS_4127 } while (false)
#define PVR_LOG_GOTO_IF_ERROR(_rc, _call, _go) do { if (unlikely(_rc != PVRSRV_OK)) { goto _go; } MSC_SUPPRESS_4127 } while (0)
#define PVR_LOG_GOTO_IF_ERROR_VA(_rc, _go, _msg, ...) do { if (unlikely(_rc != PVRSRV_OK)) { goto _go; } MSC_SUPPRESS_4127 } while (0)
#define PVR_LOG_GOTO_WITH_ERROR(_call, _err, _rc, _go) do { _err = _rc; goto _go; MSC_SUPPRESS_4127 } while (0)
#define PVR_LOG_GOTO_IF_ERROR(_rc, _call, _go) do { if (unlikely(_rc != PVRSRV_OK)) { goto _go; } MSC_SUPPRESS_4127 } while (false)
#define PVR_LOG_GOTO_IF_ERROR_VA(_rc, _go, _msg, ...) do { if (unlikely(_rc != PVRSRV_OK)) { goto _go; } MSC_SUPPRESS_4127 } while (false)
#define PVR_LOG_GOTO_WITH_ERROR(_call, _err, _rc, _go) do { _err = _rc; goto _go; MSC_SUPPRESS_4127 } while (false)
#define PVR_LOG_IF_FALSE(_expr, _msg) (void)(_expr)
#define PVR_LOG_RETURN_IF_FALSE(_expr, _msg, _rc) do { if (unlikely(!(_expr))) { return (_rc); } MSC_SUPPRESS_4127 } while (0)
#define PVR_LOG_RETURN_IF_FALSE_VA(_expr, _rc, _msg, ...) do { if (unlikely(!(_expr))) { return (_rc); } MSC_SUPPRESS_4127 } while (0)
#define PVR_LOG_RETURN_IF_FALSE(_expr, _msg, _rc) do { if (unlikely(!(_expr))) { return (_rc); } MSC_SUPPRESS_4127 } while (false)
#define PVR_LOG_RETURN_IF_FALSE_VA(_expr, _rc, _msg, ...) do { if (unlikely(!(_expr))) { return (_rc); } MSC_SUPPRESS_4127 } while (false)
#define PVR_LOG_RETURN_VOID_IF_FALSE(_expr, _msg) do { if (unlikely(!(_expr))) { return; } MSC_SUPPRESS_4127 } while (0)
#define PVR_LOG_GOTO_IF_FALSE(_expr, _msg, _go) do { if (unlikely(!(_expr))) { goto _go; } MSC_SUPPRESS_4127 } while (0)
#define PVR_LOG_GOTO_IF_FALSE_VA(_expr, _go, _msg, ...) do { if (unlikely(!(_expr))) { goto _go; } MSC_SUPPRESS_4127 } while (0)
#define PVR_LOG_RETURN_VOID_IF_FALSE(_expr, _msg) do { if (unlikely(!(_expr))) { return; } MSC_SUPPRESS_4127 } while (false)
#define PVR_LOG_GOTO_IF_FALSE(_expr, _msg, _go) do { if (unlikely(!(_expr))) { goto _go; } MSC_SUPPRESS_4127 } while (false)
#define PVR_LOG_GOTO_IF_FALSE_VA(_expr, _go, _msg, ...) do { if (unlikely(!(_expr))) { goto _go; } MSC_SUPPRESS_4127 } while (false)
#define PVR_LOG_RETURN_IF_INVALID_PARAM(_expr, _param) do { if (unlikely(!(_expr))) { return PVRSRV_ERROR_INVALID_PARAMS; } MSC_SUPPRESS_4127 } while (0)
#define PVR_LOG_GOTO_IF_INVALID_PARAM(_expr, _err, _go) do { if (unlikely(!(_expr))) { _err = PVRSRV_ERROR_INVALID_PARAMS; goto _go; } MSC_SUPPRESS_4127 } while (0)
#define PVR_LOG_RETURN_IF_INVALID_PARAM(_expr, _param) do { if (unlikely(!(_expr))) { return PVRSRV_ERROR_INVALID_PARAMS; } MSC_SUPPRESS_4127 } while (false)
#define PVR_LOG_GOTO_IF_INVALID_PARAM(_expr, _err, _go) do { if (unlikely(!(_expr))) { _err = PVRSRV_ERROR_INVALID_PARAMS; goto _go; } MSC_SUPPRESS_4127 } while (false)
#undef PVR_DPF_FUNCTION_TRACE_ON
@@ -520,8 +520,10 @@ IMG_EXPORT void IMG_CALLCONV PVRSRVDebugPrintf(IMG_UINT32 ui32DebugLevel,
*/ /**************************************************************************/
IMG_EXPORT void IMG_CALLCONV PVRSRVDebugPrintfDumpCCB(void);
#if !defined(DOXYGEN)
#define PVR_DPF_FUNC__(lvl, message, ...) PVR_DPF((lvl, "%s: " message, __func__, ##__VA_ARGS__))
#define PVR_DPF_FUNC(x) PVR_DPF_FUNC__ x
#endif /*!defined(DOXYGEN) */
/* Note: Use only when a log message due to the error absolutely should not
* be printed. Otherwise use PVR_LOG_RETURN_IF_ERROR macro.
@@ -530,7 +532,7 @@ IMG_EXPORT void IMG_CALLCONV PVRSRVDebugPrintfDumpCCB(void);
{ if (unlikely(_rc != PVRSRV_OK)) { \
return _rc; } \
MSC_SUPPRESS_4127 \
} while (0)
} while (false)
/* Note: Use only when a log message due to the error absolutely should not
* be printed. Otherwise use PVR_LOG_RETURN_IF_FALSE macro.
@@ -539,7 +541,7 @@ IMG_EXPORT void IMG_CALLCONV PVRSRVDebugPrintfDumpCCB(void);
{ if (unlikely(!(_expr))) { \
return _rc; } \
MSC_SUPPRESS_4127 \
} while (0)
} while (false)
/* Note: Use only when a log message due to the error absolutely should not
* be printed. Otherwise use PVR_LOG_RETURN_IF_INVALID_PARAM macro.
@@ -548,7 +550,7 @@ IMG_EXPORT void IMG_CALLCONV PVRSRVDebugPrintfDumpCCB(void);
{ if (unlikely(!(_expr))) { \
return PVRSRV_ERROR_INVALID_PARAMS; } \
MSC_SUPPRESS_4127 \
} while (0)
} while (false)
/* Note: Use only when a log message due to the error absolutely should not
* be printed. Otherwise use PVR_LOG_RETURN_IF_NOMEM macro.
@@ -557,7 +559,7 @@ IMG_EXPORT void IMG_CALLCONV PVRSRVDebugPrintfDumpCCB(void);
{ if (unlikely(!(_expr))) { \
return PVRSRV_ERROR_OUT_OF_MEMORY; } \
MSC_SUPPRESS_4127 \
} while (0)
} while (false)
/* Note: Use only when a log message due to the error absolutely should not
* be printed. Otherwise use PVR_LOG_GOTO_IF_NOMEM macro.
@@ -567,7 +569,7 @@ IMG_EXPORT void IMG_CALLCONV PVRSRVDebugPrintfDumpCCB(void);
_err = PVRSRV_ERROR_OUT_OF_MEMORY; \
goto _go; } \
MSC_SUPPRESS_4127 \
} while (0)
} while (false)
/* Note: Use only when a log message due to the error absolutely should not
* be printed. Otherwise use PVR_LOG_GOTO_IF_INVALID_PARAM macro.
@@ -577,7 +579,7 @@ IMG_EXPORT void IMG_CALLCONV PVRSRVDebugPrintfDumpCCB(void);
_err = PVRSRV_ERROR_INVALID_PARAMS; \
goto _go; } \
MSC_SUPPRESS_4127 \
} while (0)
} while (false)
/* Note: Use only when a log message due to the error absolutely should not
* be printed. Otherwise use PVR_LOG_GOTO_IF_FALSE macro.
@@ -586,7 +588,7 @@ IMG_EXPORT void IMG_CALLCONV PVRSRVDebugPrintfDumpCCB(void);
{ if (unlikely(!(_expr))) { \
goto _go; } \
MSC_SUPPRESS_4127 \
} while (0)
} while (false)
/* Note: Use only when a log message due to the error absolutely should not
* be printed. Otherwise use PVR_LOG_GOTO_IF_ERROR macro.
@@ -595,7 +597,7 @@ IMG_EXPORT void IMG_CALLCONV PVRSRVDebugPrintfDumpCCB(void);
{ if (unlikely(_rc != PVRSRV_OK)) { \
goto _go; } \
MSC_SUPPRESS_4127\
} while (0)
} while (false)
/* Note: Use only when a log message due to the error absolutely should not
* be printed. Otherwise use PVR_LOG_GOTO_WITH_ERROR macro.
@@ -603,7 +605,7 @@ IMG_EXPORT void IMG_CALLCONV PVRSRVDebugPrintfDumpCCB(void);
#define PVR_GOTO_WITH_ERROR(_err, _rc, _go) do \
{ _err = _rc; goto _go; \
MSC_SUPPRESS_4127 \
} while (0)
} while (false)
/*! @cond Doxygen_Suppress */
#if defined(PVR_DPF_FUNCTION_TRACE_ON)
@@ -615,19 +617,19 @@ IMG_EXPORT void IMG_CALLCONV PVRSRVDebugPrintfDumpCCB(void);
PVR_DPF((PVR_DBG_CALLTRACE, "|-> %s:%d entered (0x%lx)", __func__, __LINE__, ((unsigned long)p1)))
#define PVR_DPF_RETURN_RC(a) \
do { int _r = (a); PVR_DPF((PVR_DBG_CALLTRACE, "<-| %s:%d returned %d", __func__, __LINE__, (_r))); return (_r); MSC_SUPPRESS_4127 } while (0)
do { int _r = (a); PVR_DPF((PVR_DBG_CALLTRACE, "<-| %s:%d returned %d", __func__, __LINE__, (_r))); return (_r); MSC_SUPPRESS_4127 } while (false)
#define PVR_DPF_RETURN_RC1(a,p1) \
do { int _r = (a); PVR_DPF((PVR_DBG_CALLTRACE, "<-| %s:%d returned %d (0x%lx)", __func__, __LINE__, (_r), ((unsigned long)p1))); return (_r); MSC_SUPPRESS_4127 } while (0)
do { int _r = (a); PVR_DPF((PVR_DBG_CALLTRACE, "<-| %s:%d returned %d (0x%lx)", __func__, __LINE__, (_r), ((unsigned long)p1))); return (_r); MSC_SUPPRESS_4127 } while (false)
#define PVR_DPF_RETURN_VAL(a) \
do { PVR_DPF((PVR_DBG_CALLTRACE, "<-| %s:%d returned with value", __func__, __LINE__)); return (a); MSC_SUPPRESS_4127 } while (0)
do { PVR_DPF((PVR_DBG_CALLTRACE, "<-| %s:%d returned with value", __func__, __LINE__)); return (a); MSC_SUPPRESS_4127 } while (false)
#define PVR_DPF_RETURN_OK \
do { PVR_DPF((PVR_DBG_CALLTRACE, "<-| %s:%d returned ok", __func__, __LINE__)); return PVRSRV_OK; MSC_SUPPRESS_4127 } while (0)
do { PVR_DPF((PVR_DBG_CALLTRACE, "<-| %s:%d returned ok", __func__, __LINE__)); return PVRSRV_OK; MSC_SUPPRESS_4127 } while (false)
#define PVR_DPF_RETURN \
do { PVR_DPF((PVR_DBG_CALLTRACE, "<-| %s:%d returned", __func__, __LINE__)); return; MSC_SUPPRESS_4127 } while (0)
do { PVR_DPF((PVR_DBG_CALLTRACE, "<-| %s:%d returned", __func__, __LINE__)); return; MSC_SUPPRESS_4127 } while (false)
#if !defined(DEBUG)
#error PVR DPF Function trace enabled in release build, rectify
@@ -742,7 +744,7 @@ IMG_EXPORT void IMG_CALLCONV PVRSRVTrace(const IMG_CHAR* pszFormat, ... )
#define PVR_DBG_FILELINE_ARG , pszaFile, ui32Line
#define PVR_DBG_FILELINE_FMT " %s:%u"
#define PVR_DBG_FILELINE_UNREF() do { PVR_UNREFERENCED_PARAMETER(pszaFile); \
PVR_UNREFERENCED_PARAMETER(ui32Line); } while (0)
PVR_UNREFERENCED_PARAMETER(ui32Line); } while (false)
#else
#define PVR_DBG_FILELINE
#define PVR_DBG_FILELINE_PARAM
@@ -840,7 +842,7 @@ IMG_EXPORT void IMG_CALLCONV PVRSRVTrace(const IMG_CHAR* pszFormat, ... )
@brief Goes to a label if expression is false.
@def PVR_GOTO_IF_FALSE
@def Goes to a label if expression is false.
@brief Goes to a label if expression is false.
@def PVR_GOTO_IF_ERROR
@brief Goes to a label if the error code is different than PVRSRV_OK;
@@ -852,6 +854,29 @@ IMG_EXPORT void IMG_CALLCONV PVRSRVTrace(const IMG_CHAR* pszFormat, ... )
@brief Prints message to a log unconditionally.
This macro will print messages only if PVRSRV_NEED_PVR_LOG macro is defined.
@def PVR_LOG_MSG
@brief Prints message to a log with the given log-level.
@def PVR_LOG_VA
@brief Prints message with var-args to a log with the given log-level.
@def PVR_LOG_IF_ERROR_VA
@brief Prints message with var-args to a log if the error code is different than PVRSRV_OK.
@def PVR_LOG_IF_FALSE_VA
@brief Prints message with var-args if expression is false.
@def PVR_LOG_RETURN_IF_ERROR_VA
@brief Prints message with var-args to a log and returns the error code.
@def PVR_LOG_GOTO_IF_ERROR_VA
@brief Prints message with var-args to a log and goes to a label if the error code is different than PVRSRV_OK.
@def PVR_LOG_RETURN_IF_FALSE_VA
@brief Logs the error message with var-args if the expression is false and returns the error code.
@def PVR_LOG_GOTO_IF_FALSE_VA
@brief Logs the error message with var-args and goes to a label if the expression is false.
@def PVR_TRACE_EMPTY_LINE
@brief Prints empty line to a log (PVRSRV_NEED_PVR_LOG must be defined).

2
drivers/gpu/drm/img-rogue/include/pvrsrv_errors.h
View File

@@ -406,3 +406,5 @@ PVRE(PVRSRV_ERROR_TOO_MANY_SYNCS)
PVRE(PVRSRV_ERROR_ION_NO_CLIENT)
PVRE(PVRSRV_ERROR_ION_FAILED_TO_ALLOC)
PVRE(PVRSRV_ERROR_PDUMP_CAPTURE_BOUND_TO_ANOTHER_DEVICE)
PVRE(PVRSRV_ERROR_REFCOUNT_OVERFLOW)
PVRE(PVRSRV_ERROR_OUT_OF_RANGE)

128
drivers/gpu/drm/img-rogue/include/pvrsrv_memalloc_physheap.h
View File

@@ -56,41 +56,115 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* NOTE: Enum order important, table in physheap.c must change if order changed.
*/
typedef enum
{
/* Services client accessible heaps */
PVRSRV_PHYS_HEAP_DEFAULT = 0, /* default phys heap for device memory allocations */
PVRSRV_PHYS_HEAP_GPU_LOCAL = 1, /* used for buffers with more GPU access than CPU */
PVRSRV_PHYS_HEAP_CPU_LOCAL = 2, /* used for buffers with more CPU access than GPU */
PVRSRV_PHYS_HEAP_GPU_PRIVATE = 3, /* used for buffers that only required GPU read/write access, not visible to the CPU. */
typedef IMG_UINT32 PVRSRV_PHYS_HEAP;
/* Services client accessible heaps */
#define PVRSRV_PHYS_HEAP_DEFAULT 0U /* default phys heap for device memory allocations */
#define PVRSRV_PHYS_HEAP_GPU_LOCAL 1U /* used for buffers with more GPU access than CPU */
#define PVRSRV_PHYS_HEAP_CPU_LOCAL 2U /* used for buffers with more CPU access than GPU */
#define PVRSRV_PHYS_HEAP_GPU_PRIVATE 3U /* used for buffers that only required GPU read/write access, not visible to the CPU. */
/* Services internal heaps */
PVRSRV_PHYS_HEAP_FW_MAIN = 4, /* runtime data, e.g. CCBs, sync objects */
PVRSRV_PHYS_HEAP_EXTERNAL = 5, /* used by some PMR import/export factories where the physical memory heap is not managed by the pvrsrv driver */
PVRSRV_PHYS_HEAP_GPU_COHERENT = 6, /* used for a cache coherent region */
PVRSRV_PHYS_HEAP_GPU_SECURE = 7, /* used by security validation */
PVRSRV_PHYS_HEAP_FW_CONFIG = 8, /* subheap of FW_MAIN, configuration data for FW init */
PVRSRV_PHYS_HEAP_FW_CODE = 9, /* used by security validation or dedicated fw */
PVRSRV_PHYS_HEAP_FW_PRIV_DATA = 10, /* internal FW data (like the stack, FW control data structures, etc.) */
PVRSRV_PHYS_HEAP_FW_PREMAP0 = 11, /* Host OS premap fw heap */
PVRSRV_PHYS_HEAP_FW_PREMAP1 = 12, /* Guest OS 1 premap fw heap */
PVRSRV_PHYS_HEAP_FW_PREMAP2 = 13, /* Guest OS 2 premap fw heap */
PVRSRV_PHYS_HEAP_FW_PREMAP3 = 14, /* Guest OS 3 premap fw heap */
PVRSRV_PHYS_HEAP_FW_PREMAP4 = 15, /* Guest OS 4 premap fw heap */
PVRSRV_PHYS_HEAP_FW_PREMAP5 = 16, /* Guest OS 5 premap fw heap */
PVRSRV_PHYS_HEAP_FW_PREMAP6 = 17, /* Guest OS 6 premap fw heap */
PVRSRV_PHYS_HEAP_FW_PREMAP7 = 18, /* Guest OS 7 premap fw heap */
PVRSRV_PHYS_HEAP_LAST
} PVRSRV_PHYS_HEAP;
#define HEAPSTR(x) #x
static inline const IMG_CHAR *PVRSRVGetClientPhysHeapName(PVRSRV_PHYS_HEAP ePhysHeapID)
{
switch (ePhysHeapID)
{
case PVRSRV_PHYS_HEAP_DEFAULT:
return HEAPSTR(PVRSRV_PHYS_HEAP_DEFAULT);
case PVRSRV_PHYS_HEAP_GPU_LOCAL:
return HEAPSTR(PVRSRV_PHYS_HEAP_GPU_LOCAL);
case PVRSRV_PHYS_HEAP_CPU_LOCAL:
return HEAPSTR(PVRSRV_PHYS_HEAP_CPU_LOCAL);
case PVRSRV_PHYS_HEAP_GPU_PRIVATE:
return HEAPSTR(PVRSRV_PHYS_HEAP_GPU_PRIVATE);
default:
return "Unknown Heap";
}
}
/* Services internal heaps */
#define PVRSRV_PHYS_HEAP_FW_MAIN 4U /* runtime data, e.g. CCBs, sync objects */
#define PVRSRV_PHYS_HEAP_EXTERNAL 5U /* used by some PMR import/export factories where the physical memory heap is not managed by the pvrsrv driver */
#define PVRSRV_PHYS_HEAP_GPU_COHERENT 6U /* used for a cache coherent region */
#define PVRSRV_PHYS_HEAP_GPU_SECURE 7U /* used by security validation */
#define PVRSRV_PHYS_HEAP_FW_CONFIG 8U /* subheap of FW_MAIN, configuration data for FW init */
#define PVRSRV_PHYS_HEAP_FW_CODE 9U /* used by security validation or dedicated fw */
#define PVRSRV_PHYS_HEAP_FW_PRIV_DATA 10U /* internal FW data (like the stack, FW control data structures, etc.) */
#define PVRSRV_PHYS_HEAP_FW_PREMAP0 11U /* Host OS premap fw heap */
#define PVRSRV_PHYS_HEAP_FW_PREMAP1 12U /* Guest OS 1 premap fw heap */
#define PVRSRV_PHYS_HEAP_FW_PREMAP2 13U /* Guest OS 2 premap fw heap */
#define PVRSRV_PHYS_HEAP_FW_PREMAP3 14U /* Guest OS 3 premap fw heap */
#define PVRSRV_PHYS_HEAP_FW_PREMAP4 15U /* Guest OS 4 premap fw heap */
#define PVRSRV_PHYS_HEAP_FW_PREMAP5 16U /* Guest OS 5 premap fw heap */
#define PVRSRV_PHYS_HEAP_FW_PREMAP6 17U /* Guest OS 6 premap fw heap */
#define PVRSRV_PHYS_HEAP_FW_PREMAP7 18U /* Guest OS 7 premap fw heap */
#define PVRSRV_PHYS_HEAP_LAST 19U
static_assert(PVRSRV_PHYS_HEAP_LAST <= (0x1FU + 1U), "Ensure enum fits in memalloc flags bitfield.");
typedef struct _PHYS_HEAP_MEM_STATS_
/*! Type conveys the class of physical heap to instantiate within Services
* for the physical pool of memory. */
typedef enum _PHYS_HEAP_TYPE_
{
PHYS_HEAP_TYPE_UNKNOWN = 0, /*!< Not a valid value for any config */
PHYS_HEAP_TYPE_UMA, /*!< Heap represents OS managed physical memory heap
i.e. system RAM. Unified Memory Architecture
physmem_osmem PMR factory */
PHYS_HEAP_TYPE_LMA, /*!< Heap represents physical memory pool managed by
Services i.e. carve out from system RAM or local
card memory. Local Memory Architecture
physmem_lma PMR factory */
#if defined(__KERNEL__)
PHYS_HEAP_TYPE_DMA, /*!< Heap represents a physical memory pool managed by
Services, alias of LMA and is only used on
VZ non-native system configurations for
a heap used for PHYS_HEAP_USAGE_FW_MAIN tagged
buffers */
#if defined(SUPPORT_WRAP_EXTMEMOBJECT)
PHYS_HEAP_TYPE_WRAP, /*!< Heap used to group UM buffers given
to Services. Integrity OS port only. */
#endif
#endif
} PHYS_HEAP_TYPE;
/* Defines used when interpreting the ui32PhysHeapFlags in PHYS_HEAP_MEM_STATS
0x000000000000dttt
d = is this the default heap? (1=yes, 0=no)
ttt = heap type (000 = PHYS_HEAP_TYPE_UNKNOWN,
001 = PHYS_HEAP_TYPE_UMA,
010 = PHYS_HEAP_TYPE_LMA,
011 = PHYS_HEAP_TYPE_DMA)
*/
#define PVRSRV_PHYS_HEAP_FLAGS_TYPE_MASK (0x7U << 0)
#define PVRSRV_PHYS_HEAP_FLAGS_IS_DEFAULT (0x1U << 7)
typedef struct PHYS_HEAP_MEM_STATS_TAG
{
IMG_UINT64 ePhysHeapID;
IMG_UINT64 ui64TotalSize;
IMG_UINT64 ui64FreeSize;
IMG_UINT32 ui32PhysHeapFlags;
}PHYS_HEAP_MEM_STATS, *PHYS_HEAP_MEM_STATS_PTR;
typedef struct PHYS_HEAP_MEM_STATS_PKD_TAG
{
IMG_UINT64 ui64TotalSize;
IMG_UINT64 ui64FreeSize;
IMG_UINT32 ui32PhysHeapFlags;
IMG_UINT32 ui32Dummy;
}PHYS_HEAP_MEM_STATS_PKD, *PHYS_HEAP_MEM_STATS_PKD_PTR;
static inline const IMG_CHAR *PVRSRVGetClientPhysHeapTypeName(PHYS_HEAP_TYPE ePhysHeapType)
{
switch (ePhysHeapType)
{
case PHYS_HEAP_TYPE_UMA:
return HEAPSTR(PHYS_HEAP_TYPE_UMA);
case PHYS_HEAP_TYPE_LMA:
return HEAPSTR(PHYS_HEAP_TYPE_LMA);
default:
return "Unknown Heap Type";
}
}
#undef HEAPSTR
#endif /* PVRSRV_MEMALLOC_PHYSHEAP_H */

70
drivers/gpu/drm/img-rogue/include/pvrsrv_memallocflags.h
View File

@@ -58,7 +58,7 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
typedef IMG_UINT64 PVRSRV_MEMALLOCFLAGS_T;
#define PVRSRV_MEMALLOCFLAGS_FMTSPEC IMG_UINT64_FMTSPECx
#if defined(__KERNEL__) || defined(SERVICES_SC)
#if defined(__KERNEL__)
#include "pvrsrv_memallocflags_internal.h"
#endif /* __KERNEL__ */
@@ -538,7 +538,7 @@ typedef IMG_UINT64 PVRSRV_MEMALLOCFLAGS_T;
/*!
Indicates the particular memory that's being allocated is sparse and the
sparse regions should not be backed by dummy page
*/
*/
#define PVRSRV_MEMALLOCFLAG_SPARSE_NO_DUMMY_BACKING (1ULL << 18)
/*!
@@ -549,9 +549,12 @@ typedef IMG_UINT64 PVRSRV_MEMALLOCFLAGS_T;
#define PVRSRV_IS_SPARSE_DUMMY_BACKING_REQUIRED(uiFlags) (((uiFlags) & PVRSRV_MEMALLOCFLAG_SPARSE_NO_DUMMY_BACKING) == 0U)
/*!
Services is going to clean the cache for the allocated memory.
For performance reasons avoid usage if allocation is written to by the
CPU anyway before the next GPU kick.
Used to force Services to carry out at least one CPU cache invalidate on a
CPU cached buffer during allocation of the memory. Applicable to incoherent
systems, it must be used for buffers which are CPU cached and which will not
be 100% written to by the CPU before the GPU accesses it. For performance
reasons, avoid usage if the whole buffer that is allocated is written to by
the CPU anyway before the next GPU kick, or if the system is coherent.
*/
#define PVRSRV_MEMALLOCFLAG_CPU_CACHE_CLEAN (1ULL<<19)
@@ -570,7 +573,7 @@ typedef IMG_UINT64 PVRSRV_MEMALLOCFLAGS_T;
by zero page at the time of mapping.
The zero backed page is always with read only attribute irrespective of its
original attributes.
*/
*/
#define PVRSRV_MEMALLOCFLAG_SPARSE_ZERO_BACKING (1ULL << 20)
#define PVRSRV_IS_SPARSE_ZERO_BACKING_REQUIRED(uiFlags) (((uiFlags) & \
PVRSRV_MEMALLOCFLAG_SPARSE_ZERO_BACKING) == PVRSRV_MEMALLOCFLAG_SPARSE_ZERO_BACKING)
@@ -650,8 +653,10 @@ typedef IMG_UINT64 PVRSRV_MEMALLOCFLAGS_T;
*/
#define PVRSRV_CHECK_POISON_ON_ALLOC(uiFlags) (((uiFlags) & PVRSRV_MEMALLOCFLAG_POISON_ON_ALLOC) != 0U)
#if defined(DEBUG) || defined(SERVICES_SC)
/*!
Causes memory to be trashed when freed, as a lazy man's security measure.
Causes memory to be trashed when freed, used when debugging only, not to be used
as a security measure.
*/
#define PVRSRV_MEMALLOCFLAG_POISON_ON_FREE (1ULL<<29)
@@ -661,6 +666,7 @@ typedef IMG_UINT64 PVRSRV_MEMALLOCFLAGS_T;
@Return True if the flag is set, false otherwise
*/
#define PVRSRV_CHECK_POISON_ON_FREE(uiFlags) (((uiFlags) & PVRSRV_MEMALLOCFLAG_POISON_ON_FREE) != 0U)
#endif /* DEBUG */
/*!
Avoid address alignment to a CPU or GPU cache line size.
@@ -822,20 +828,27 @@ typedef IMG_UINT64 PVRSRV_MEMALLOCFLAGS_T;
* Trusted device mask -- Flags in the mask are allowed for trusted device
* because the driver cannot access the memory
*/
#if defined(DEBUG) || defined(SERVICES_SC)
#define PVRSRV_MEMALLOCFLAGS_TDFWMASK ~(PVRSRV_MEMALLOCFLAG_KERNEL_CPU_MAPPABLE | \
PVRSRV_MEMALLOCFLAG_ZERO_ON_ALLOC | \
PVRSRV_MEMALLOCFLAG_POISON_ON_ALLOC | \
PVRSRV_MEMALLOCFLAG_POISON_ON_FREE | \
PVRSRV_MEMALLOCFLAG_POISON_ON_FREE | \
PVRSRV_MEMALLOCFLAGS_CPU_MMUFLAGSMASK | \
PVRSRV_MEMALLOCFLAG_SPARSE_NO_DUMMY_BACKING)
#else
#define PVRSRV_MEMALLOCFLAGS_TDFWMASK ~(PVRSRV_MEMALLOCFLAG_KERNEL_CPU_MAPPABLE | \
PVRSRV_MEMALLOCFLAG_ZERO_ON_ALLOC | \
PVRSRV_MEMALLOCFLAG_POISON_ON_ALLOC | \
PVRSRV_MEMALLOCFLAGS_CPU_MMUFLAGSMASK | \
PVRSRV_MEMALLOCFLAG_SPARSE_NO_DUMMY_BACKING)
#endif
/*!
PMR flags mask -- for internal services use only. This is the set of flags
that will be passed down and stored with the PMR, this also includes the
MMU flags which the PMR has to pass down to mm_common.c at PMRMap time.
*/
#if defined(DEBUG) || defined(SERVICES_SC)
#define PVRSRV_MEMALLOCFLAGS_PMRFLAGSMASK (PVRSRV_MEMALLOCFLAG_DEVICE_FLAGS_MASK | \
PVRSRV_MEMALLOCFLAG_CPU_CACHE_CLEAN | \
PVRSRV_MEMALLOCFLAG_KERNEL_CPU_MAPPABLE | \
@@ -848,8 +861,23 @@ typedef IMG_UINT64 PVRSRV_MEMALLOCFLAGS_T;
PVRSRV_MEMALLOCFLAG_NO_OSPAGES_ON_ALLOC | \
PVRSRV_MEMALLOCFLAG_SPARSE_NO_DUMMY_BACKING | \
PVRSRV_MEMALLOCFLAG_SPARSE_ZERO_BACKING | \
PVRSRV_MEMALLOCFLAG_VAL_SHARED_BUFFER | \
PVRSRV_MEMALLOCFLAG_VAL_SHARED_BUFFER | \
PVRSRV_PHYS_HEAP_HINT_MASK)
#else
#define PVRSRV_MEMALLOCFLAGS_PMRFLAGSMASK (PVRSRV_MEMALLOCFLAG_DEVICE_FLAGS_MASK | \
PVRSRV_MEMALLOCFLAG_CPU_CACHE_CLEAN | \
PVRSRV_MEMALLOCFLAG_KERNEL_CPU_MAPPABLE | \
PVRSRV_MEMALLOCFLAG_ZERO_ON_ALLOC | \
PVRSRV_MEMALLOCFLAG_SVM_ALLOC | \
PVRSRV_MEMALLOCFLAG_POISON_ON_ALLOC | \
PVRSRV_MEMALLOCFLAGS_GPU_MMUFLAGSMASK | \
PVRSRV_MEMALLOCFLAGS_CPU_MMUFLAGSMASK | \
PVRSRV_MEMALLOCFLAG_NO_OSPAGES_ON_ALLOC | \
PVRSRV_MEMALLOCFLAG_SPARSE_NO_DUMMY_BACKING | \
PVRSRV_MEMALLOCFLAG_SPARSE_ZERO_BACKING | \
PVRSRV_MEMALLOCFLAG_VAL_SHARED_BUFFER | \
PVRSRV_PHYS_HEAP_HINT_MASK)
#endif
/*!
* CPU mappable mask -- Any flag set in the mask requires memory to be CPU mappable
@@ -874,11 +902,18 @@ typedef IMG_UINT64 PVRSRV_MEMALLOCFLAGS_T;
memory might be reused.
*/
#if defined(DEBUG) || defined(SERVICES_SC)
#define PVRSRV_MEMALLOCFLAGS_RA_DIFFERENTIATION_MASK (PVRSRV_MEMALLOCFLAGS_PMRFLAGSMASK \
& \
~(PVRSRV_MEMALLOCFLAG_ZERO_ON_ALLOC | \
PVRSRV_MEMALLOCFLAG_POISON_ON_ALLOC | \
PVRSRV_MEMALLOCFLAG_POISON_ON_FREE))
#else
#define PVRSRV_MEMALLOCFLAGS_RA_DIFFERENTIATION_MASK (PVRSRV_MEMALLOCFLAGS_PMRFLAGSMASK \
& \
~(PVRSRV_MEMALLOCFLAG_ZERO_ON_ALLOC | \
PVRSRV_MEMALLOCFLAG_POISON_ON_ALLOC))
#endif
/*!
Flags that affect _allocation_
*/
@@ -903,6 +938,7 @@ typedef IMG_UINT64 PVRSRV_MEMALLOCFLAGS_T;
/*!
Flags that affect _physical allocations_ in the DevMemX API
*/
#if defined(DEBUG) || defined(SERVICES_SC)
#define PVRSRV_MEMALLOCFLAGS_DEVMEMX_PHYSICAL_MASK (PVRSRV_MEMALLOCFLAGS_CPU_MMUFLAGSMASK | \
PVRSRV_MEMALLOCFLAG_GPU_CACHE_MODE_MASK | \
PVRSRV_MEMALLOCFLAG_CPU_READ_PERMITTED | \
@@ -912,6 +948,16 @@ typedef IMG_UINT64 PVRSRV_MEMALLOCFLAGS_T;
PVRSRV_MEMALLOCFLAG_POISON_ON_ALLOC | \
PVRSRV_MEMALLOCFLAG_POISON_ON_FREE | \
PVRSRV_PHYS_HEAP_HINT_MASK)
#else
#define PVRSRV_MEMALLOCFLAGS_DEVMEMX_PHYSICAL_MASK (PVRSRV_MEMALLOCFLAGS_CPU_MMUFLAGSMASK | \
PVRSRV_MEMALLOCFLAG_GPU_CACHE_MODE_MASK | \
PVRSRV_MEMALLOCFLAG_CPU_READ_PERMITTED | \
PVRSRV_MEMALLOCFLAG_CPU_WRITE_PERMITTED | \
PVRSRV_MEMALLOCFLAG_CPU_CACHE_CLEAN | \
PVRSRV_MEMALLOCFLAG_ZERO_ON_ALLOC | \
PVRSRV_MEMALLOCFLAG_POISON_ON_ALLOC | \
PVRSRV_PHYS_HEAP_HINT_MASK)
#endif
/*!
Flags that affect _virtual allocations_ in the DevMemX API

2
drivers/gpu/drm/img-rogue/include/pvrsrv_tlcommon.h
View File

@@ -170,7 +170,7 @@ typedef IMG_UINT32 PVRSRVTL_PACKETTYPE;
*/
#define PVRSRVTL_SET_PACKET_DATA(len) (len) | (PVRSRVTL_PACKETTYPE_DATA << PVRSRVTL_PACKETHDR_TYPE_OFFSET)
#define PVRSRVTL_SET_PACKET_PADDING(len) (len) | (PVRSRVTL_PACKETTYPE_PADDING << PVRSRVTL_PACKETHDR_TYPE_OFFSET)
#define PVRSRVTL_SET_PACKET_WRITE_FAILED (0) | (PVRSRVTL_PACKETTYPE_MOST_RECENT_WRITE_FAILED << PVRSRVTL_PACKETHDR_TYPE_OFFSET)
#define PVRSRVTL_SET_PACKET_WRITE_FAILED (0U) | (PVRSRVTL_PACKETTYPE_MOST_RECENT_WRITE_FAILED << PVRSRVTL_PACKETHDR_TYPE_OFFSET)
#define PVRSRVTL_SET_PACKET_HDR(len, type) (len) | ((type) << PVRSRVTL_PACKETHDR_TYPE_OFFSET)
/*! Returns the number of bytes of data in the packet.

16
drivers/gpu/drm/img-rogue/include/pvrversion.h
View File

@@ -45,21 +45,21 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define PVRVERSION_H
#define PVRVERSION_MAJ 1U
#define PVRVERSION_MIN 16U
#define PVRVERSION_MIN 17U
#define PVRVERSION_FAMILY "rogueddk"
#define PVRVERSION_BRANCHNAME "1.16"
#define PVRVERSION_BUILD 6099580
#define PVRVERSION_BRANCHNAME "1.17"
#define PVRVERSION_BUILD 6210866
#define PVRVERSION_BSCONTROL "Rogue_DDK_Linux_WS"
#define PVRVERSION_STRING "Rogue_DDK_Linux_WS rogueddk 1.16@6099580"
#define PVRVERSION_STRING_SHORT "1.16@6099580"
#define PVRVERSION_STRING "Rogue_DDK_Linux_WS rogueddk 1.17@6210866"
#define PVRVERSION_STRING_SHORT "1.17@6210866"
#define COPYRIGHT_TXT "Copyright (c) Imagination Technologies Ltd. All Rights Reserved."
#define PVRVERSION_BUILD_HI 609
#define PVRVERSION_BUILD_LO 9580
#define PVRVERSION_STRING_NUMERIC "1.16.609.9580"
#define PVRVERSION_BUILD_HI 621
#define PVRVERSION_BUILD_LO 866
#define PVRVERSION_STRING_NUMERIC "1.17.621.866"
#define PVRVERSION_PACK(MAJOR,MINOR) (((IMG_UINT32)((IMG_UINT32)(MAJOR) & 0xFFFFU) << 16U) | (((MINOR) & 0xFFFFU) << 0U))
#define PVRVERSION_UNPACK_MAJ(VERSION) (((VERSION) >> 16U) & 0xFFFFU)

66
drivers/gpu/drm/img-rogue/include/rgx_common.h
View File

@@ -52,20 +52,7 @@ extern "C" {
/* Included to get the BVNC_KM_N defined and other feature defs */
#include "km/rgxdefs_km.h"
/*! This macro represents a mask of LSBs that must be zero on data structure
* sizes and offsets to ensure they are 8-byte granular on types shared between
* the FW and host driver */
#define RGX_FW_ALIGNMENT_LSB (7U)
/*! Macro to test structure size alignment */
#define RGX_FW_STRUCT_SIZE_ASSERT(_a) \
static_assert((sizeof(_a) & RGX_FW_ALIGNMENT_LSB) == 0U, \
"Size of " #_a " is not properly aligned")
/*! Macro to test structure member alignment */
#define RGX_FW_STRUCT_OFFSET_ASSERT(_a, _b) \
static_assert((offsetof(_a, _b) & RGX_FW_ALIGNMENT_LSB) == 0U, \
"Offset of " #_a "." #_b " is not properly aligned")
#include "rgx_common_asserts.h"
/* Virtualisation validation builds are meant to test the VZ-related hardware without a fully virtualised platform.
@@ -99,25 +86,25 @@ typedef IMG_UINT32 RGXFWIF_DM;
#define RGXFWIF_DM_CDM IMG_UINT32_C(4)
#define RGXFWIF_DM_RAY IMG_UINT32_C(5)
#define RGXFWIF_DM_GEOM2 IMG_UINT32_C(6)
#define RGXFWIF_DM_GEOM3 IMG_UINT32_C(7)
#define RGXFWIF_DM_GEOM4 IMG_UINT32_C(8)
#define RGXFWIF_DM_LAST RGXFWIF_DM_GEOM2
#define RGXFWIF_DM_LAST RGXFWIF_DM_GEOM4
typedef enum _RGX_KICK_TYPE_DM_
{
RGX_KICK_TYPE_DM_GP = 0x001,
RGX_KICK_TYPE_DM_TDM_2D = 0x002,
RGX_KICK_TYPE_DM_TA = 0x004,
RGX_KICK_TYPE_DM_3D = 0x008,
RGX_KICK_TYPE_DM_CDM = 0x010,
RGX_KICK_TYPE_DM_RTU = 0x020,
RGX_KICK_TYPE_DM_SHG = 0x040,
RGX_KICK_TYPE_DM_TQ2D = 0x080,
RGX_KICK_TYPE_DM_TQ3D = 0x100,
RGX_KICK_TYPE_DM_RAY = 0x200,
RGX_KICK_TYPE_DM_LAST = 0x400
} RGX_KICK_TYPE_DM;
typedef IMG_UINT32 RGX_KICK_TYPE_DM;
#define RGX_KICK_TYPE_DM_GP IMG_UINT32_C(0x001)
#define RGX_KICK_TYPE_DM_TDM_2D IMG_UINT32_C(0x002)
#define RGX_KICK_TYPE_DM_TA IMG_UINT32_C(0x004)
#define RGX_KICK_TYPE_DM_3D IMG_UINT32_C(0x008)
#define RGX_KICK_TYPE_DM_CDM IMG_UINT32_C(0x010)
#define RGX_KICK_TYPE_DM_RTU IMG_UINT32_C(0x020)
#define RGX_KICK_TYPE_DM_SHG IMG_UINT32_C(0x040)
#define RGX_KICK_TYPE_DM_TQ2D IMG_UINT32_C(0x080)
#define RGX_KICK_TYPE_DM_TQ3D IMG_UINT32_C(0x100)
#define RGX_KICK_TYPE_DM_RAY IMG_UINT32_C(0x200)
#define RGX_KICK_TYPE_DM_LAST IMG_UINT32_C(0x400)
/* Maximum number of DM in use: GP, 2D/TDM, GEOM, 3D, CDM, RDM, GEOM2 */
/* Maximum number of DM in use: GP, 2D/TDM, GEOM, 3D, CDM, RDM, GEOM2, GEOM3, GEOM4 */
#define RGXFWIF_DM_MAX (RGXFWIF_DM_LAST + 1U)
/*
@@ -201,10 +188,18 @@ typedef enum _RGX_KICK_TYPE_DM_
#define RGX_MAX_NUM_REGISTER_PROGRAMMER_WRITES (128U)
/* FW common context priority. */
#define RGX_CTX_PRIORITY_REALTIME (UINT32_MAX)
#define RGX_CTX_PRIORITY_HIGH (2U)
#define RGX_CTX_PRIORITY_MEDIUM (1U)
#define RGX_CTX_PRIORITY_LOW (0)
/*!
* @AddToGroup WorkloadContexts
* @{
*/
#define RGX_CTX_PRIORITY_REALTIME (INT32_MAX)
#define RGX_CTX_PRIORITY_HIGH (2U) /*!< HIGH priority */
#define RGX_CTX_PRIORITY_MEDIUM (1U) /*!< MEDIUM priority */
#define RGX_CTX_PRIORITY_LOW (0) /*!< LOW priority */
/*!
* @} End of AddToGroup WorkloadContexts
*/
/*
* Use of the 32-bit context property flags mask
@@ -220,6 +215,9 @@ typedef enum _RGX_KICK_TYPE_DM_
*/
#define RGX_CONTEXT_FLAG_DISABLESLR (1UL << 0) /*!< Disable SLR */
/* Bitmask of context flags allowed to be modified after context create. */
#define RGX_CONTEXT_FLAGS_WRITEABLE_MASK (RGX_CONTEXT_FLAG_DISABLESLR)
/* List of attributes that may be set for a context */
typedef enum _RGX_CONTEXT_PROPERTY_
{

73
drivers/gpu/drm/img-rogue/include/rgx_common_asserts.h Normal file
View File

@@ -0,0 +1,73 @@
/*************************************************************************/ /*!
@File
@Title RGX Common Types and Defines Header
@Copyright Copyright (c) Imagination Technologies Ltd. All Rights Reserved
@Description Common types and definitions for RGX software
@License Dual MIT/GPLv2
The contents of this file are subject to the MIT license as set out below.
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
Alternatively, the contents of this file may be used under the terms of
the GNU General Public License Version 2 ("GPL") in which case the provisions
of GPL are applicable instead of those above.
If you wish to allow use of your version of this file only under the terms of
GPL, and not to allow others to use your version of this file under the terms
of the MIT license, indicate your decision by deleting the provisions above
and replace them with the notice and other provisions required by GPL as set
out in the file called "GPL-COPYING" included in this distribution. If you do
not delete the provisions above, a recipient may use your version of this file
under the terms of either the MIT license or GPL.
This License is also included in this distribution in the file called
"MIT-COPYING".
EXCEPT AS OTHERWISE STATED IN A NEGOTIATED AGREEMENT: (A) THE SOFTWARE IS
PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
PURPOSE AND NONINFRINGEMENT; AND (B) IN NO EVENT SHALL THE AUTHORS OR
COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/ /**************************************************************************/
#ifndef RGX_COMMON_ASSERTS_H
#define RGX_COMMON_ASSERTS_H
#if defined(__cplusplus)
extern "C" {
#endif
/*! This macro represents a mask of LSBs that must be zero on data structure
* sizes and offsets to ensure they are 8-byte granular on types shared between
* the FW and host driver */
#define RGX_FW_ALIGNMENT_LSB (7U)
/*! Macro to test structure size alignment */
#define RGX_FW_STRUCT_SIZE_ASSERT(_a) \
static_assert((sizeof(_a) & RGX_FW_ALIGNMENT_LSB) == 0U, \
"Size of " #_a " is not properly aligned")
/*! Macro to test structure member alignment */
#define RGX_FW_STRUCT_OFFSET_ASSERT(_a, _b) \
static_assert((offsetof(_a, _b) & RGX_FW_ALIGNMENT_LSB) == 0U, \
"Offset of " #_a "." #_b " is not properly aligned")
#if defined(__cplusplus)
}
#endif
#endif /* RGX_COMMON_ASSERTS_H */
/******************************************************************************
End of file
******************************************************************************/

2
drivers/gpu/drm/img-rogue/include/rgx_compat_bvnc.h
View File

@@ -110,7 +110,7 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
(bvnc) = ((L).ui64BVNC == (R).ui64BVNC); \
} \
(all) = (version) && (bvnc); \
} while (0)
} while (false)
/**************************************************************************//**

18
drivers/gpu/drm/img-rogue/include/rgx_fwif_resetframework.h
View File

@@ -48,21 +48,17 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
typedef struct
{
#if defined(RGX_FEATURE_CDM_USER_MODE_QUEUE)
IMG_UINT64 uCDMReg_CDM_CB_QUEUE;
IMG_UINT64 uCDMReg_CDM_CB_BASE;
IMG_UINT64 uCDMReg_CDM_CB;
#else
IMG_UINT64 uCDMReg_CDM_CTRL_STREAM_BASE;
#endif
union
{
IMG_UINT64 uCDMReg_CDM_CB_BASE; // defined(RGX_FEATURE_CDM_USER_MODE_QUEUE)
IMG_UINT64 uCDMReg_CDM_CTRL_STREAM_BASE; // !defined(RGX_FEATURE_CDM_USER_MODE_QUEUE)
};
IMG_UINT64 uCDMReg_CDM_CB_QUEUE; // !defined(RGX_FEATURE_CDM_USER_MODE_QUEUE)
IMG_UINT64 uCDMReg_CDM_CB; // !defined(RGX_FEATURE_CDM_USER_MODE_QUEUE)
} RGXFWIF_RF_REGISTERS;
#define RGXFWIF_RF_FLAG_ENABLE 0x00000001U /*!< enables the reset framework in the firmware */
typedef struct
{
IMG_UINT32 ui32Flags;
/* THIS MUST BE THE LAST MEMBER OF THE CONTAINING STRUCTURE */
RGXFWIF_RF_REGISTERS RGXFW_ALIGN sFWRegisters;

54
drivers/gpu/drm/img-rogue/include/rgx_fwif_sf.h
View File

@@ -71,6 +71,10 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
X(RGXFW_GROUP_DMA,DMA) \
X(RGXFW_GROUP_DBG,DBG)
/*!
* @InGroup SRVAndFWTracing
* @Brief FW Trace log groups(GID) list
*/
enum RGXFW_LOG_SFGROUPS {
#define X(A,B) A,
RGXFW_LOG_SFGROUPLIST
@@ -284,7 +288,7 @@ X(181, RGXFW_GROUP_MAIN, RGXFW_SF_MAIN_SIGNAL_UPDATE, "Signal update, Snoop Filt
X(182, RGXFW_GROUP_MAIN, RGXFW_SF_MAIN_DEV_SERIES8_DEPRECATED, "WARNING: Skipping FW KCCB Cmd type %d which is not yet supported on Series8.", 1) \
X(183, RGXFW_GROUP_MAIN, RGXFW_SF_MAIN_INCONSISTENT_MMU_FLAGS, "MMU context cache data NULL, but cache flags=0x%x (sync counter=%u, update value=%u) OSId=%u", 4) \
X(184, RGXFW_GROUP_MAIN, RGXFW_SF_MAIN_SLC_FLUSH, "SLC range based flush: Context=%u VAddr=0x%02x%08x, Size=0x%08x, Invalidate=%d", 5) \
X(185, RGXFW_GROUP_MAIN, RGXFW_SF_MAIN_FBSC_INVAL, "FBSC invalidate for Context [0x%08x]: Entry mask 0x%08x%08x.", 3) \
X(185, RGXFW_GROUP_MAIN, RGXFW_SF_MAIN_FBSC_INVAL, "FBSC invalidate for Context Set [0x%08x]: Entry mask 0x%08x%08x.", 3) \
X(186, RGXFW_GROUP_MAIN, RGXFW_SF_MAIN_TDM_BRN66284_UPDATE, "TDM context switch check: Roff %u was not valid for kick starting at %u, moving back to %u", 3) \
X(187, RGXFW_GROUP_MAIN, RGXFW_SF_MAIN_SPFILTER_UPDATES, "Signal updates: FIFO: %u, Signals: 0x%08x", 2) \
X(188, RGXFW_GROUP_MAIN, RGXFW_SF_MAIN_INVALID_FBSC_CMD, "Invalid FBSC cmd: FWCtx 0x%08x, MemCtx 0x%08x", 2) \
@@ -318,8 +322,8 @@ X(215, RGXFW_GROUP_MAIN, RGXFW_SF_MAIN_USC_TASKS_RANGE, "DM%d USC tasks range li
X(216, RGXFW_GROUP_MAIN, RGXFW_SF_MAIN_GPU_ECC_FAULT, "ECC fault GPU=0x%08x", 1) \
X(217, RGXFW_GROUP_MAIN, RGXFW_SF_MAIN_GPU_SAFETY_RESET, "GPU Hardware units reset to prevent transient faults.", 0) \
X(218, RGXFW_GROUP_MAIN, RGXFW_SF_MAIN_ABORTCMD, "Kick Abort cmd: FWCtx 0x%08.8x @ %d", 2) \
X(219, RGXFW_GROUP_MAIN, RGXFW_SF_MAIN_KICK_RAY, "Kick Ray: FWCtx 0x%08.8x @ %d. (PID:%d, prio:%d, frame:%d, ext:0x%08x, int:0x%08x)", 7)\
X(220, RGXFW_GROUP_MAIN, RGXFW_SF_MAIN_RAY_FINISHED, "Ray finished", 0) \
X(219, RGXFW_GROUP_MAIN, RGXFW_SF_MAIN_KICK_RAY_DEPRECATED, "Kick Ray: FWCtx 0x%08.8x @ %d. (PID:%d, prio:%d, frame:%d, ext:0x%08x, int:0x%08x)", 7)\
X(220, RGXFW_GROUP_MAIN, RGXFW_SF_MAIN_RAY_FINISHED_DEPRECATED, "Ray finished", 0) \
X(221, RGXFW_GROUP_MAIN, RGXFW_SF_MAIN_FWDATA_INIT_STATUS, "State of firmware's private data at boot time: %d (0 = uninitialised, 1 = initialised); Fw State Flags = 0x%08X", 2) \
X(222, RGXFW_GROUP_MAIN, RGXFW_SF_MAIN_CFI_TIMEOUT, "CFI Timeout detected (%d increasing to %d)", 2) \
X(223, RGXFW_GROUP_MAIN, RGXFW_SF_MAIN_CFI_TIMEOUT_FBM, "CFI Timeout detected for FBM (%d increasing to %d)", 2) \
@@ -327,6 +331,17 @@ X(224, RGXFW_GROUP_MAIN, RGXFW_SF_MAIN_GEOM_OOM_DISALLOWED, "Geom OOM event not
X(225, RGXFW_GROUP_MAIN, RGXFW_SF_MAIN_OS_PRIORITY_CHANGE, "Changing OSid %d's priority from %u to %u; Isolation = %u (0 = off; 1 = on)", 4) \
X(226, RGXFW_GROUP_MAIN, RGXFW_SF_MAIN_SKIP_ALREADY_RUN_GEOM, "Skipping already executed TA FWCtx 0x%08.8x @ %d", 2) \
X(227, RGXFW_GROUP_MAIN, RGXFW_SF_MAIN_ATTEMPT_TO_RUN_AHEAD_GEOM, "Attempt to execute TA FWCtx 0x%08.8x @ %d ahead of time on other GEOM", 2) \
X(228, RGXFW_GROUP_MAIN, RGXFW_SF_MAIN_KICK_TDM_DEPRECATED2, "Kick TDM: Kick ID %u FWCtx 0x%08.8x @ %d. (PID:%d, prio:%d, frame:%d, ext:0x%08x, int:0x%08x)", 8) \
X(229, RGXFW_GROUP_MAIN, RGXFW_SF_MAIN_KICK_TA_PIPELINE, "Kick TA: Kick ID %u FWCtx 0x%08.8x @ %d, RTD 0x%08x, First kick:%d, Last kick:%d, CSW resume:%d. (PID:%d, prio:%d, frame:%d, ext:0x%08x, int:0x%08x)", 12) \
X(230, RGXFW_GROUP_MAIN, RGXFW_SF_MAIN_KICK_3D_PIPELINE, "Kick 3D: Kick ID %u FWCtx 0x%08.8x @ %d, RTD 0x%08x, Partial render:%d, CSW resume:%d. (PID:%d, prio:%d, frame:%d, ext:0x%08x, int:0x%08x)", 11) \
X(231, RGXFW_GROUP_MAIN, RGXFW_SF_MAIN_KICK_COMPUTE_PIPELINE, "Kick Compute: Kick ID %u FWCtx 0x%08.8x @ %d. (PID:%d, prio:%d, ext:0x%08x, int:0x%08x)", 7) \
X(232, RGXFW_GROUP_MAIN, RGXFW_SF_MAIN_TDM_FINISHED_PIPELINE, "TDM finished: Kick ID %u ", 1) \
X(233, RGXFW_GROUP_MAIN, RGXFW_SF_MAIN_TA_FINISHED_PIPELINE, "TA finished: Kick ID %u ", 1) \
X(234, RGXFW_GROUP_MAIN, RGXFW_SF_MAIN_3D_FINISHED_PIPELINE, "3D finished: Kick ID %u , HWRTData0State=%x, HWRTData1State=%x", 3) \
X(235, RGXFW_GROUP_MAIN, RGXFW_SF_MAIN_COMPUTE_FINISHED_PIPELINE, "Compute finished: Kick ID %u ", 1) \
X(236, RGXFW_GROUP_MAIN, RGXFW_SF_MAIN_KICK_TDM_PIPELINE, "Kick TDM: Kick ID %u FWCtx 0x%08.8x @ %d, Base 0x%08x%08x. (PID:%d, prio:%d, frame:%d, ext:0x%08x, int:0x%08x)", 10) \
X(237, RGXFW_GROUP_MAIN, RGXFW_SF_MAIN_KICK_RAY_PIPELINE, "Kick Ray: Kick ID %u FWCtx 0x%08.8x @ %d. (PID:%d, prio:%d, frame:%d, ext:0x%08x, int:0x%08x)", 8)\
X(238, RGXFW_GROUP_MAIN, RGXFW_SF_MAIN_RAY_FINISHED_PIPELINE, "Ray finished: Kick ID %u ", 1) \
\
X( 1, RGXFW_GROUP_MTS, RGXFW_SF_MTS_BG_KICK_DEPRECATED, "Bg Task DM = %u, counted = %d", 2) \
X( 2, RGXFW_GROUP_MTS, RGXFW_SF_MTS_BG_COMPLETE_DEPRECATED, "Bg Task complete DM = %u", 1) \
@@ -348,6 +363,7 @@ X( 17, RGXFW_GROUP_MTS, RGXFW_SF_MTS_KCCBCMD_RTN_VALUE, "KCCB Slot %u: Return va
X( 18, RGXFW_GROUP_MTS, RGXFW_SF_MTS_BG_KICK, "Bg Task OSid = %u", 1) \
X( 19, RGXFW_GROUP_MTS, RGXFW_SF_MTS_KCCBCMD_EXEC, "KCCB Slot %u: Cmd=0x%08x, OSid=%u", 3) \
X( 20, RGXFW_GROUP_MTS, RGXFW_SF_MTS_IRQ_KICK, "Irq Task (EVENT_STATUS=0x%08x)", 1) \
X( 21, RGXFW_GROUP_MTS, RGXFW_SF_MTS_VZ_SIDEBAND, "VZ sideband test, kicked with OSid=%u from MTS, OSid for test=%u", 2) \
\
X( 1, RGXFW_GROUP_CLEANUP, RGXFW_SF_CLEANUP_FWCTX_CLEANUP, "FwCommonContext [0x%08x] cleaned", 1) \
X( 2, RGXFW_GROUP_CLEANUP, RGXFW_SF_CLEANUP_FWCTX_BUSY, "FwCommonContext [0x%08x] is busy: ReadOffset = %d, WriteOffset = %d", 3) \
@@ -425,9 +441,9 @@ X( 54, RGXFW_GROUP_CSW, RGXFW_SF_CSW_RDM_RESUME, "RDM FWCtx 0x%08.8x resume", 1)
\
X( 1, RGXFW_GROUP_BIF, RGXFW_SF_BIF_ACTIVATE_BIFREQ_DEPRECATED, "Activate MemCtx=0x%08x BIFreq=%d secure=%d", 3) \
X( 2, RGXFW_GROUP_BIF, RGXFW_SF_BIF_DEACTIVATE, "Deactivate MemCtx=0x%08x", 1) \
X( 3, RGXFW_GROUP_BIF, RGXFW_SF_BIF_PCREG_ALLOC, "Alloc PC reg %d", 1) \
X( 4, RGXFW_GROUP_BIF, RGXFW_SF_BIF_PCREG_GRAB, "Grab reg %d refcount now %d", 2) \
X( 5, RGXFW_GROUP_BIF, RGXFW_SF_BIF_PCREG_UNGRAB, "Ungrab reg %d refcount now %d", 2) \
X( 3, RGXFW_GROUP_BIF, RGXFW_SF_BIF_PCREG_ALLOC_DEPRECATED, "Alloc PC reg %d", 1) \
X( 4, RGXFW_GROUP_BIF, RGXFW_SF_BIF_PCSET_GRAB, "Grab reg set %d refcount now %d", 2) \
X( 5, RGXFW_GROUP_BIF, RGXFW_SF_BIF_PCSET_UNGRAB, "Ungrab reg set %d refcount now %d", 2) \
X( 6, RGXFW_GROUP_BIF, RGXFW_SF_BIF_SETUP_REG_BIFREQ_DEPRECATED, "Setup reg=%d BIFreq=%d, expect=0x%08x%08x, actual=0x%08x%08x", 6) \
X( 7, RGXFW_GROUP_BIF, RGXFW_SF_BIF_TRUST_DEPRECATED, "Trust enabled:%d, for BIFreq=%d", 2) \
X( 8, RGXFW_GROUP_BIF, RGXFW_SF_BIF_TILECFG_DEPRECATED, "BIF Tiling Cfg %d base 0x%08x%08x len 0x%08x%08x enable %d stride %d --> 0x%08x%08x", 9) \
@@ -437,10 +453,12 @@ X( 11, RGXFW_GROUP_BIF, RGXFW_SF_BIF_OSIDx, "ui32OSid = %u, Catbase = %u, Reg Ad
X( 12, RGXFW_GROUP_BIF, RGXFW_SF_BIF_MAP_GPU_MEMORY_BIFREQ_DEPRECATED, "Map GPU memory DevVAddr 0x%x%08x, Size %u, Context ID %u, BIFREQ %u", 5) \
X( 13, RGXFW_GROUP_BIF, RGXFW_SF_BIF_UNMAP_GPU_MEMORY, "Unmap GPU memory (event status 0x%x)", 1) \
X( 14, RGXFW_GROUP_BIF, RGXFW_SF_BIF_ACTIVATE_DM, "Activate MemCtx=0x%08x DM=%d secure=%d", 3) \
X( 15, RGXFW_GROUP_BIF, RGXFW_SF_BIF_SETUP_REG_DM, "Setup reg=%d DM=%d, expect=0x%08x%08x, actual=0x%08x%08x", 6) \
X( 15, RGXFW_GROUP_BIF, RGXFW_SF_BIF_SETUP_REG_DM_DEPRECATED, "Setup reg=%d DM=%d, expect=0x%08x%08x, actual=0x%08x%08x", 6) \
X( 16, RGXFW_GROUP_BIF, RGXFW_SF_BIF_MAP_GPU_MEMORY, "Map GPU memory DevVAddr 0x%x%08x, Size %u, Context ID %u", 4) \
X( 17, RGXFW_GROUP_BIF, RGXFW_SF_BIF_TRUST_DM, "Trust enabled:%d, for DM=%d", 2) \
X( 18, RGXFW_GROUP_BIF, RGXFW_SF_BIF_MAP_GPU_MEMORY_DM, "Map GPU memory DevVAddr 0x%x%08x, Size %u, Context ID %u, DM %u", 5) \
X( 19, RGXFW_GROUP_BIF, RGXFW_SF_BIF_SETUP_REG_DM, "Setup register set=%d DM=%d, PC address=0x%08x%08x, OSid=%u, NewPCRegRequired=%d", 6) \
X( 20, RGXFW_GROUP_BIF, RGXFW_SF_BIF_PCSET_ALLOC, "Alloc PC set %d as register range [%u - %u]", 3) \
\
X( 1, RGXFW_GROUP_MISC, RGXFW_SF_MISC_GPIO_WRITE, "GPIO write 0x%02x", 1) \
X( 2, RGXFW_GROUP_MISC, RGXFW_SF_MISC_GPIO_READ, "GPIO read 0x%02x", 1) \
@@ -505,6 +523,8 @@ X( 28, RGXFW_GROUP_PM, RGXFW_SF_PM_3D_TIMEOUT, "3D Timeout Now for FWCtx 0x%08.8
X( 29, RGXFW_GROUP_PM, RGXFW_SF_PM_RECYCLE, "GEOM PM Recycle for FWCtx 0x%08.8x", 1) \
X( 30, RGXFW_GROUP_PM, RGXFW_SF_PM_PRIMARY_CONFIG, "PM running primary config (Core %d)", 1) \
X( 31, RGXFW_GROUP_PM, RGXFW_SF_PM_SECONDARY_CONFIG, "PM running secondary config (Core %d)", 1) \
X( 32, RGXFW_GROUP_PM, RGXFW_SF_PM_TERTIARY_CONFIG, "PM running tertiary config (Core %d)", 1) \
X( 33, RGXFW_GROUP_PM, RGXFW_SF_PM_QUATERNARY_CONFIG, "PM running quaternary config (Core %d)", 1) \
\
X( 1, RGXFW_GROUP_RPM, RGXFW_SF_RPM_GLL_DYNAMIC_STATUS_DEPRECATED, "Global link list dynamic page count: vertex 0x%x, varying 0x%x, node 0x%x", 3) \
X( 2, RGXFW_GROUP_RPM, RGXFW_SF_RPM_GLL_STATIC_STATUS_DEPRECATED, "Global link list static page count: vertex 0x%x, varying 0x%x, node 0x%x", 3) \
@@ -628,6 +648,7 @@ X( 54, RGXFW_GROUP_SPM, RGXFW_SF_SPM_ACK_GROW_UPDATE, "Received grow update, FL
X( 66, RGXFW_GROUP_SPM, RGXFW_SF_SPM_OOM_TACMD, "OOM TA/3D PR Check: [0x%08.8x] is 0x%08.8x requires 0x%08.8x", 3) \
X( 67, RGXFW_GROUP_SPM, RGXFW_SF_SPM_RESUMED_TA, "OOM: Resumed TA with ready pages, FL addr: 0x%02x%08x, current pages: %u", 3) \
X( 68, RGXFW_GROUP_SPM, RGXFW_SF_SPM_PR_DEADLOCK_UNBLOCKED, "OOM TA/3D PR deadlock unblocked reordering DM%d runlist head from Context 0x%08x to 0x%08x", 3) \
X( 69, RGXFW_GROUP_SPM, RGXFW_SF_SPM_STATE_PR_FORCEFREE, "SPM State = PR force free", 0) \
\
X( 1, RGXFW_GROUP_POW, RGXFW_SF_POW_CHECK_DEPRECATED, "Check Pow state DM%d int: 0x%x, ext: 0x%x, pow flags: 0x%x", 4) \
X( 2, RGXFW_GROUP_POW, RGXFW_SF_POW_GPU_IDLE, "GPU idle (might be powered down). Pow state int: 0x%x, ext: 0x%x, flags: 0x%x", 3) \
@@ -697,6 +718,10 @@ X( 66, RGXFW_GROUP_POW, RGXFW_SF_POW_POWMON_PERF_MODE, "PPA block started in per
X( 67, RGXFW_GROUP_POW, RGXFW_SF_POW_POWMON_RESET, "Reset PPA block state %u (1=reset, 0=recalculate).", 1) \
X( 68, RGXFW_GROUP_POW, RGXFW_SF_POW_POWCTRL_ABORT_WITH_CORE, "Power controller returned ABORT for Core-%d last request so retrying.", 1) \
X( 69, RGXFW_GROUP_POW, RGXFW_SF_POW_HWREQ64BIT, "HW Request On(1)/Off(0): %d, Units: 0x%08x%08x", 3) \
X( 70, RGXFW_GROUP_POW, RGXFW_SF_POW_SPU_RAC_POW_STATE_CHANGE_REQ, "Request to change SPU power state mask from 0x%x to 0x%x and RAC from 0x%x to 0x%x. Pow flags: 0x%x", 5) \
X( 71, RGXFW_GROUP_POW, RGXFW_SF_POW_SPU_RAC_POW_STATE_CHANGE, "Changing SPU power state mask from 0x%x to 0x%x and RAC from 0x%x to 0x%x", 4) \
X( 72, RGXFW_GROUP_POW, RGXFW_SF_POW_REQUESTEDOFF_RAC, "RAC pending? %d, RAC Active? %d", 2) \
X( 73, RGXFW_GROUP_POW, RGXFW_SF_POW_INIOFF_RAC, "Initiate powoff query for RAC.", 0) \
\
X( 1, RGXFW_GROUP_HWR, RGXFW_SF_HWR_LOCKUP_DEPRECATED, "Lockup detected on DM%d, FWCtx: 0x%08.8x", 2) \
X( 2, RGXFW_GROUP_HWR, RGXFW_SF_HWR_RESET_FW_DEPRECATED, "Reset fw state for DM%d, FWCtx: 0x%08.8x, MemCtx: 0x%08.8x", 3) \
@@ -786,14 +811,15 @@ X( 85, RGXFW_GROUP_HWR, RGXFW_SF_HWR_FULL_CHECK, "Full Signature Check result fo
X( 86, RGXFW_GROUP_HWR, RGXFW_SF_HWR_USC_SLOTS_CHECK, "USC Slots result for Core%u, DM%u is HWRNeeded=%u USCSlotsUsedByDM=%d", 4) \
X( 87, RGXFW_GROUP_HWR, RGXFW_SF_HWR_WATCHDOG_CHECK, "USC Watchdog result for Core%u DM%u is HWRNeeded=%u Status=%u USCs={0x%x} with HWRChecksToGo=%u", 6) \
X( 88, RGXFW_GROUP_HWR, RGXFW_SF_HWR_MMU_RISCV_FAULT, "RISC-V MMU page fault detected (FWCORE MMU Status 0x%08x Req Status 0x%08x%08x)", 3) \
X( 89, RGXFW_GROUP_HWR, RGXFW_SF_HWR_HWR_FAULT_POLL_BIF_TEXAS1_PFS_DEPRECATED, "After FW fault was raised, TEXAS1_PFS poll failed on core %d with value 0x%08x", 2) \
X( 90, RGXFW_GROUP_HWR, RGXFW_SF_HWR_HWR_FAULT_POLL_BIF_PFS, "After FW fault was raised, BIF_PFS poll failed on core %d with value 0x%08x", 2) \
X( 91, RGXFW_GROUP_HWR, RGXFW_SF_HWR_HWR_FAULT_POLL_SET_ABORT_PM_STATUS, "After FW fault was raised, MMU_ABORT_PM_STATUS set poll failed on core %d with value 0x%08x", 2) \
X( 92, RGXFW_GROUP_HWR, RGXFW_SF_HWR_HWR_FAULT_POLL_UNSET_ABORT_PM_STATUS, "After FW fault was raised, MMU_ABORT_PM_STATUS unset poll failed on core %d with value 0x%08x", 2) \
X( 93, RGXFW_GROUP_HWR, RGXFW_SF_HWR_HWR_FAULT_POLL_SLC_INVAL, "After FW fault was raised, MMU_CTRL_INVAL poll (all but fw) failed on core %d with value 0x%08x", 2) \
X( 94, RGXFW_GROUP_HWR, RGXFW_SF_HWR_HWR_FAULT_POLL_SLCMMU_INVAL, "After FW fault was raised, MMU_CTRL_INVAL poll (all) failed on core %d with value 0x%08x", 2) \
X( 95, RGXFW_GROUP_HWR, RGXFW_SF_HWR_HWR_FAULT_POLL_BIF_TEXAS_PFS, "After FW fault was raised, TEXAS%d_PFS poll failed on core %d with value 0x%08x", 3) \
X( 89, RGXFW_GROUP_HWR, RGXFW_SF_HWR_HWR_FAULT_POLL_BIF_TEXAS1_PFS_DEPRECATED, "TEXAS1_PFS poll failed on core %d with value 0x%08x", 2) \
X( 90, RGXFW_GROUP_HWR, RGXFW_SF_HWR_HWR_FAULT_POLL_BIF_PFS, "BIF_PFS poll failed on core %d with value 0x%08x", 2) \
X( 91, RGXFW_GROUP_HWR, RGXFW_SF_HWR_HWR_FAULT_POLL_SET_ABORT_PM_STATUS, "MMU_ABORT_PM_STATUS set poll failed on core %d with value 0x%08x", 2) \
X( 92, RGXFW_GROUP_HWR, RGXFW_SF_HWR_HWR_FAULT_POLL_UNSET_ABORT_PM_STATUS, "MMU_ABORT_PM_STATUS unset poll failed on core %d with value 0x%08x", 2) \
X( 93, RGXFW_GROUP_HWR, RGXFW_SF_HWR_HWR_FAULT_POLL_SLC_INVAL, "MMU_CTRL_INVAL poll (all but fw) failed on core %d with value 0x%08x", 2) \
X( 94, RGXFW_GROUP_HWR, RGXFW_SF_HWR_HWR_FAULT_POLL_SLCMMU_INVAL, "MMU_CTRL_INVAL poll (all) failed on core %d with value 0x%08x", 2) \
X( 95, RGXFW_GROUP_HWR, RGXFW_SF_HWR_HWR_FAULT_POLL_BIF_TEXAS_PFS, "TEXAS%d_PFS poll failed on core %d with value 0x%08x", 3) \
X( 96, RGXFW_GROUP_HWR, RGXFW_SF_HWR_EXTRA_CHECK, "Extra Registers Check result for Core%u, DM%u is HWRNeeded=%u", 3) \
X( 97, RGXFW_GROUP_HWR, RGXFW_SF_HWR_WRITE_TO_GPU_READONLY_ADDR, "FW attempted to write to read-only GPU address 0x%08x", 1) \
\
X( 1, RGXFW_GROUP_HWP, RGXFW_SF_HWP_I_CFGBLK, "Block 0x%x mapped to Config Idx %u", 2) \
X( 2, RGXFW_GROUP_HWP, RGXFW_SF_HWP_I_OMTBLK, "Block 0x%x omitted from event - not enabled in HW", 1) \

32
drivers/gpu/drm/img-rogue/include/rgx_heap_firmware.h
View File

@@ -57,7 +57,7 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
* of the map / unmap functions must take into consideration
* the entire range (i.e. main and config heap).
*/
#define RGX_FIRMWARE_NUMBER_OF_FW_HEAPS (2)
#define RGX_FIRMWARE_NUMBER_OF_FW_HEAPS (IMG_UINT32_C(2))
#define RGX_FIRMWARE_HEAP_SHIFT RGX_FW_HEAP_SHIFT
#define RGX_FIRMWARE_RAW_HEAP_BASE (0xE1C0000000ULL)
#define RGX_FIRMWARE_RAW_HEAP_SIZE (IMG_UINT32_C(1) << RGX_FIRMWARE_HEAP_SHIFT)
@@ -73,9 +73,9 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
* 1st PMR: RGXFWIF_CONNECTION_CTL
* 2nd PMR: RGXFWIF_OSINIT
* 3rd PMR: RGXFWIF_SYSINIT */
#define RGX_FIRMWARE_CONFIG_HEAP_SIZE (3*RGX_FIRMWARE_CONFIG_HEAP_ALLOC_GRANULARITY)
#define RGX_FIRMWARE_CONFIG_HEAP_SIZE (IMG_UINT32_C(3)*RGX_FIRMWARE_CONFIG_HEAP_ALLOC_GRANULARITY)
#define RGX_FIRMWARE_META_MAIN_HEAP_SIZE (RGX_FIRMWARE_RAW_HEAP_SIZE - RGX_FIRMWARE_CONFIG_HEAP_SIZE)
#define RGX_FIRMWARE_DEFAULT_MAIN_HEAP_SIZE (RGX_FIRMWARE_RAW_HEAP_SIZE - RGX_FIRMWARE_CONFIG_HEAP_SIZE)
/*
* MIPS FW needs space in the Main heap to map GPU memory.
* This space is taken from the MAIN heap, to avoid creating a new heap.
@@ -83,36 +83,30 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define RGX_FIRMWARE_MIPS_GPU_MAP_RESERVED_SIZE_NORMAL (IMG_UINT32_C(0x100000)) /* 1MB */
#define RGX_FIRMWARE_MIPS_GPU_MAP_RESERVED_SIZE_BRN65101 (IMG_UINT32_C(0x400000)) /* 4MB */
#define RGX_FIRMWARE_MIPS_MAIN_HEAP_SIZE_NORMAL (RGX_FIRMWARE_RAW_HEAP_SIZE - RGX_FIRMWARE_CONFIG_HEAP_SIZE - \
RGX_FIRMWARE_MIPS_GPU_MAP_RESERVED_SIZE_NORMAL)
#define RGX_FIRMWARE_HOST_MIPS_MAIN_HEAP_SIZE_NORMAL (RGX_FIRMWARE_RAW_HEAP_SIZE - RGX_FIRMWARE_CONFIG_HEAP_SIZE - \
RGX_FIRMWARE_MIPS_GPU_MAP_RESERVED_SIZE_NORMAL)
#define RGX_FIRMWARE_MIPS_MAIN_HEAP_SIZE_BRN65101 (RGX_FIRMWARE_RAW_HEAP_SIZE - RGX_FIRMWARE_CONFIG_HEAP_SIZE - \
RGX_FIRMWARE_MIPS_GPU_MAP_RESERVED_SIZE_BRN65101)
#define RGX_FIRMWARE_HOST_MIPS_MAIN_HEAP_SIZE_BRN65101 (RGX_FIRMWARE_RAW_HEAP_SIZE - RGX_FIRMWARE_CONFIG_HEAP_SIZE - \
RGX_FIRMWARE_MIPS_GPU_MAP_RESERVED_SIZE_BRN65101)
#if !defined(__KERNEL__)
#if defined(FIX_HW_BRN_65101)
#define RGX_FIRMWARE_MIPS_GPU_MAP_RESERVED_SIZE RGX_FIRMWARE_MIPS_GPU_MAP_RESERVED_SIZE_BRN65101
#define RGX_FIRMWARE_MIPS_MAIN_HEAP_SIZE RGX_FIRMWARE_MIPS_MAIN_HEAP_SIZE_BRN65101
#define RGX_FIRMWARE_HOST_MIPS_MAIN_HEAP_SIZE RGX_FIRMWARE_HOST_MIPS_MAIN_HEAP_SIZE_BRN65101
#include "img_defs.h"
static_assert((RGX_FIRMWARE_RAW_HEAP_SIZE) >= IMG_UINT32_C(0x800000), "MIPS GPU map size cannot be increased due to BRN65101 with a small FW heap");
#else
#define RGX_FIRMWARE_MIPS_GPU_MAP_RESERVED_SIZE RGX_FIRMWARE_MIPS_GPU_MAP_RESERVED_SIZE_NORMAL
#define RGX_FIRMWARE_MIPS_MAIN_HEAP_SIZE RGX_FIRMWARE_MIPS_MAIN_HEAP_SIZE_NORMAL
#define RGX_FIRMWARE_HOST_MIPS_MAIN_HEAP_SIZE RGX_FIRMWARE_HOST_MIPS_MAIN_HEAP_SIZE_NORMAL
#endif
#endif /* !defined(__KERNEL__) */
/* Host sub-heap order: MAIN + CONFIG */
#define RGX_FIRMWARE_HOST_MAIN_HEAP_BASE RGX_FIRMWARE_RAW_HEAP_BASE
#define RGX_FIRMWARE_HOST_CONFIG_HEAP_BASE (RGX_FIRMWARE_HOST_MAIN_HEAP_BASE + \
RGX_FIRMWARE_RAW_HEAP_SIZE - \
RGX_FIRMWARE_CONFIG_HEAP_SIZE)
/* Guest sub-heap order: CONFIG + MAIN */
#define RGX_FIRMWARE_GUEST_CONFIG_HEAP_BASE RGX_FIRMWARE_RAW_HEAP_BASE
#define RGX_FIRMWARE_GUEST_MAIN_HEAP_BASE (RGX_FIRMWARE_GUEST_CONFIG_HEAP_BASE + \
RGX_FIRMWARE_CONFIG_HEAP_SIZE)
#define RGX_FIRMWARE_MAIN_HEAP_BASE RGX_FIRMWARE_RAW_HEAP_BASE
#define RGX_FIRMWARE_CONFIG_HEAP_BASE (RGX_FIRMWARE_MAIN_HEAP_BASE + \
RGX_FIRMWARE_RAW_HEAP_SIZE - \
RGX_FIRMWARE_CONFIG_HEAP_SIZE)
/*
* The maximum configurable size via RGX_FW_HEAP_SHIFT is 32MiB (1<<25) and

482
drivers/gpu/drm/img-rogue/include/rgx_hwperf_common.h Normal file
View File

@@ -0,0 +1,482 @@
/*************************************************************************/ /*!
@File
@Title RGX HWPerf and Debug Types and Defines Header
@Copyright Copyright (c) Imagination Technologies Ltd. All Rights Reserved
@Description Common data types definitions for hardware performance API
@License Dual MIT/GPLv2
The contents of this file are subject to the MIT license as set out below.
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
Alternatively, the contents of this file may be used under the terms of
the GNU General Public License Version 2 ("GPL") in which case the provisions
of GPL are applicable instead of those above.
If you wish to allow use of your version of this file only under the terms of
GPL, and not to allow others to use your version of this file under the terms
of the MIT license, indicate your decision by deleting the provisions above
and replace them with the notice and other provisions required by GPL as set
out in the file called "GPL-COPYING" included in this distribution. If you do
not delete the provisions above, a recipient may use your version of this file
under the terms of either the MIT license or GPL.
This License is also included in this distribution in the file called
"MIT-COPYING".
EXCEPT AS OTHERWISE STATED IN A NEGOTIATED AGREEMENT: (A) THE SOFTWARE IS
PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
PURPOSE AND NONINFRINGEMENT; AND (B) IN NO EVENT SHALL THE AUTHORS OR
COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/ /**************************************************************************/
#ifndef RGX_HWPERF_COMMON_H_
#define RGX_HWPERF_COMMON_H_
#if defined(__cplusplus)
extern "C" {
#endif
/* These structures are used on both GPU and CPU and must be a size that is a
* multiple of 64 bits, 8 bytes to allow the FW to write 8 byte quantities at
* 8 byte aligned addresses. RGX_FW_STRUCT_*_ASSERT() is used to check this.
*/
/******************************************************************************
* Includes and Defines
*****************************************************************************/
#include "img_types.h"
#include "img_defs.h"
#include "rgx_common_asserts.h"
#include "pvrsrv_tlcommon.h"
/******************************************************************************
* Packet Event Type Enumerations
*****************************************************************************/
/*! Type used to encode the event that generated the packet.
* NOTE: When this type is updated the corresponding hwperfbin2json tool
* source needs to be updated as well. The RGX_HWPERF_EVENT_MASK_* macros will
* also need updating when adding new types.
*
* @par
* The event type values are incrementing integers for use as a shift ordinal
* in the event filtering process at the point events are generated.
* This scheme thus implies a limit of 63 event types.
*/
typedef IMG_UINT32 RGX_HWPERF_EVENT_TYPE;
#define RGX_HWPERF_INVALID 0x00U /*!< Invalid. Reserved value. */
/*! FW types 0x01..0x06 */
#define RGX_HWPERF_FW_EVENT_RANGE_FIRST_TYPE 0x01U
#define RGX_HWPERF_FW_BGSTART 0x01U /*!< Background task processing start */
#define RGX_HWPERF_FW_BGEND 0x02U /*!< Background task end */
#define RGX_HWPERF_FW_IRQSTART 0x03U /*!< IRQ task processing start */
#define RGX_HWPERF_FW_IRQEND 0x04U /*!< IRQ task end */
#define RGX_HWPERF_FW_DBGSTART 0x05U /*!< Debug event start */
#define RGX_HWPERF_FW_DBGEND 0x06U /*!< Debug event end */
#define RGX_HWPERF_FW_EVENT_RANGE_LAST_TYPE 0x06U
/*! HW types 0x07..0x19 */
#define RGX_HWPERF_HW_EVENT_RANGE0_FIRST_TYPE 0x07U
#define RGX_HWPERF_HW_PMOOM_TAPAUSE 0x07U /*!< TA Pause at PM Out of Memory */
#define RGX_HWPERF_HW_TAKICK 0x08U /*!< TA task started */
#define RGX_HWPERF_HW_TAFINISHED 0x09U /*!< TA task finished */
#define RGX_HWPERF_HW_3DTQKICK 0x0AU /*!< 3D TQ started */
#define RGX_HWPERF_HW_3DKICK 0x0BU /*!< 3D task started */
#define RGX_HWPERF_HW_3DFINISHED 0x0CU /*!< 3D task finished */
#define RGX_HWPERF_HW_CDMKICK 0x0DU /*!< CDM task started */
#define RGX_HWPERF_HW_CDMFINISHED 0x0EU /*!< CDM task finished */
#define RGX_HWPERF_HW_TLAKICK 0x0FU /*!< TLA task started */
#define RGX_HWPERF_HW_TLAFINISHED 0x10U /*!< TLS task finished */
#define RGX_HWPERF_HW_3DSPMKICK 0x11U /*!< 3D SPM task started */
#define RGX_HWPERF_HW_PERIODIC 0x12U /*!< Periodic event with updated HW counters */
#define RGX_HWPERF_HW_RTUKICK 0x13U /*!< Reserved, future use */
#define RGX_HWPERF_HW_RTUFINISHED 0x14U /*!< Reserved, future use */
#define RGX_HWPERF_HW_SHGKICK 0x15U /*!< Reserved, future use */
#define RGX_HWPERF_HW_SHGFINISHED 0x16U /*!< Reserved, future use */
#define RGX_HWPERF_HW_3DTQFINISHED 0x17U /*!< 3D TQ finished */
#define RGX_HWPERF_HW_3DSPMFINISHED 0x18U /*!< 3D SPM task finished */
#define RGX_HWPERF_HW_PMOOM_TARESUME 0x19U /*!< TA Resume after PM Out of Memory */
/*! HW_EVENT_RANGE0 used up. Use next empty range below to add new hardware events */
#define RGX_HWPERF_HW_EVENT_RANGE0_LAST_TYPE 0x19U
/*! other types 0x1A..0x1F */
#define RGX_HWPERF_CLKS_CHG 0x1AU /*!< Clock speed change in GPU */
#define RGX_HWPERF_GPU_STATE_CHG 0x1BU /*!< GPU work state change */
/*! power types 0x20..0x27 */
#define RGX_HWPERF_PWR_EST_RANGE_FIRST_TYPE 0x20U
#define RGX_HWPERF_PWR_EST_REQUEST 0x20U /*!< Power estimate requested (via GPIO) */
#define RGX_HWPERF_PWR_EST_READY 0x21U /*!< Power estimate inputs ready */
#define RGX_HWPERF_PWR_EST_RESULT 0x22U /*!< Power estimate result calculated */
#define RGX_HWPERF_PWR_EST_RANGE_LAST_TYPE 0x22U
#define RGX_HWPERF_PWR_CHG 0x23U /*!< Power state change */
/*! HW_EVENT_RANGE1 0x28..0x2F, for accommodating new hardware events */
#define RGX_HWPERF_HW_EVENT_RANGE1_FIRST_TYPE 0x28U
#define RGX_HWPERF_HW_TDMKICK 0x28U /*!< TDM task started */
#define RGX_HWPERF_HW_TDMFINISHED 0x29U /*!< TDM task finished */
#define RGX_HWPERF_HW_NULLKICK 0x2AU /*!< NULL event */
#define RGX_HWPERF_HW_EVENT_RANGE1_LAST_TYPE 0x2AU
/*! context switch types 0x30..0x31 */
#define RGX_HWPERF_CSW_START 0x30U /*!< HW context store started */
#define RGX_HWPERF_CSW_FINISHED 0x31U /*!< HW context store finished */
/*! DVFS events */
#define RGX_HWPERF_DVFS 0x32U /*!< Dynamic voltage/frequency scaling events */
/*! firmware misc 0x38..0x39 */
#define RGX_HWPERF_UFO 0x38U /*!< FW UFO Check / Update */
#define RGX_HWPERF_FWACT 0x39U /*!< FW Activity notification */
/*! last */
#define RGX_HWPERF_LAST_TYPE 0x3BU
/*! This enumeration must have a value that is a power of two as it is
* used in masks and a filter bit field (currently 64 bits long).
*/
#define RGX_HWPERF_MAX_TYPE 0x40U
static_assert(RGX_HWPERF_LAST_TYPE < RGX_HWPERF_MAX_TYPE, "Too many HWPerf event types");
/*! Macro used to check if an event type ID is present in the known set of hardware type events */
#define HWPERF_PACKET_IS_HW_TYPE(_etype) (((_etype) >= RGX_HWPERF_HW_EVENT_RANGE0_FIRST_TYPE && (_etype) <= RGX_HWPERF_HW_EVENT_RANGE0_LAST_TYPE) || \
((_etype) >= RGX_HWPERF_HW_EVENT_RANGE1_FIRST_TYPE && (_etype) <= RGX_HWPERF_HW_EVENT_RANGE1_LAST_TYPE))
/*! Macro used to check if an event type ID is present in the known set of firmware type events */
#define HWPERF_PACKET_IS_FW_TYPE(_etype) \
((_etype) >= RGX_HWPERF_FW_EVENT_RANGE_FIRST_TYPE && \
(_etype) <= RGX_HWPERF_FW_EVENT_RANGE_LAST_TYPE)
typedef enum {
RGX_HWPERF_HOST_INVALID = 0x00, /*!< Invalid, do not use. */
RGX_HWPERF_HOST_ENQ = 0x01, /*!< ``0x01`` Kernel driver has queued GPU work.
See RGX_HWPERF_HOST_ENQ_DATA */
RGX_HWPERF_HOST_UFO = 0x02, /*!< ``0x02`` UFO updated by the driver.
See RGX_HWPERF_HOST_UFO_DATA */
RGX_HWPERF_HOST_ALLOC = 0x03, /*!< ``0x03`` Resource allocated.
See RGX_HWPERF_HOST_ALLOC_DATA */
RGX_HWPERF_HOST_CLK_SYNC = 0x04, /*!< ``0x04`` GPU / Host clocks correlation data.
See RGX_HWPERF_HOST_CLK_SYNC_DATA */
RGX_HWPERF_HOST_FREE = 0x05, /*!< ``0x05`` Resource freed,
See RGX_HWPERF_HOST_FREE_DATA */
RGX_HWPERF_HOST_MODIFY = 0x06, /*!< ``0x06`` Resource modified / updated.
See RGX_HWPERF_HOST_MODIFY_DATA */
RGX_HWPERF_HOST_DEV_INFO = 0x07, /*!< ``0x07`` Device Health status.
See RGX_HWPERF_HOST_DEV_INFO_DATA */
RGX_HWPERF_HOST_INFO = 0x08, /*!< ``0x08`` Device memory usage information.
See RGX_HWPERF_HOST_INFO_DATA */
RGX_HWPERF_HOST_SYNC_FENCE_WAIT = 0x09, /*!< ``0x09`` Wait for sync event.
See RGX_HWPERF_HOST_SYNC_FENCE_WAIT_DATA */
RGX_HWPERF_HOST_SYNC_SW_TL_ADVANCE = 0x0A, /*!< ``0x0A`` Software timeline advanced.
See RGX_HWPERF_HOST_SYNC_SW_TL_ADV_DATA */
RGX_HWPERF_HOST_CLIENT_INFO = 0x0B, /*!< ``0x0B`` Additional client info.
See RGX_HWPERF_HOST_CLIENT_INFO_DATA */
/*! last */
RGX_HWPERF_HOST_LAST_TYPE,
/*! This enumeration must have a value that is a power of two as it is
* used in masks and a filter bit field (currently 32 bits long).
*/
RGX_HWPERF_HOST_MAX_TYPE = 0x20
} RGX_HWPERF_HOST_EVENT_TYPE;
/*!< The event type values are incrementing integers for use as a shift ordinal
* in the event filtering process at the point events are generated.
* This scheme thus implies a limit of 31 event types.
*/
static_assert(RGX_HWPERF_HOST_LAST_TYPE < RGX_HWPERF_HOST_MAX_TYPE, "Too many HWPerf host event types");
/******************************************************************************
* Packet Header Format Version 2 Types
*****************************************************************************/
/*! Major version number of the protocol in operation
*/
#define RGX_HWPERF_V2_FORMAT 2
/*! Signature ASCII pattern 'HWP2' found in the first word of a HWPerfV2 packet
*/
#define HWPERF_PACKET_V2_SIG 0x48575032
/*! Signature ASCII pattern 'HWPA' found in the first word of a HWPerfV2a packet
*/
#define HWPERF_PACKET_V2A_SIG 0x48575041
/*! Signature ASCII pattern 'HWPB' found in the first word of a HWPerfV2b packet
*/
#define HWPERF_PACKET_V2B_SIG 0x48575042
/*! Signature ASCII pattern 'HWPC' found in the first word of a HWPerfV2c packet
*/
#define HWPERF_PACKET_V2C_SIG 0x48575043
#define HWPERF_PACKET_ISVALID(_val) (((_val) == HWPERF_PACKET_V2_SIG) || ((_val) == HWPERF_PACKET_V2A_SIG) || ((_val) == HWPERF_PACKET_V2B_SIG) || ((_val) == HWPERF_PACKET_V2C_SIG))
/*!< Checks that the packet signature is one of the supported versions */
/*! Type defines the HWPerf packet header common to all events. */
typedef struct
{
IMG_UINT32 ui32Sig; /*!< Always the value HWPERF_PACKET_SIG */
IMG_UINT32 ui32Size; /*!< Overall packet size in bytes */
IMG_UINT32 eTypeId; /*!< Event type information field */
IMG_UINT32 ui32Ordinal; /*!< Sequential number of the packet */
IMG_UINT64 ui64Timestamp; /*!< Event timestamp */
} RGX_HWPERF_V2_PACKET_HDR, *RGX_PHWPERF_V2_PACKET_HDR;
RGX_FW_STRUCT_OFFSET_ASSERT(RGX_HWPERF_V2_PACKET_HDR, ui64Timestamp);
RGX_FW_STRUCT_SIZE_ASSERT(RGX_HWPERF_V2_PACKET_HDR);
/*! Mask for use with the IMG_UINT32 ui32Size header field */
#define RGX_HWPERF_SIZE_MASK 0xFFFFU
/*! This macro defines an upper limit to which the size of the largest variable
* length HWPerf packet must fall within, currently 3KB. This constant may be
* used to allocate a buffer to hold one packet.
* This upper limit is policed by packet producing code.
*/
#define RGX_HWPERF_MAX_PACKET_SIZE 0xC00U
/*! Defines an upper limit to the size of a variable length packet payload.
*/
#define RGX_HWPERF_MAX_PAYLOAD_SIZE ((IMG_UINT32)(RGX_HWPERF_MAX_PACKET_SIZE-\
sizeof(RGX_HWPERF_V2_PACKET_HDR)))
/*! Macro which takes a structure name and provides the packet size for
* a fixed size payload packet, rounded up to 8 bytes to align packets
* for 64 bit architectures. */
#define RGX_HWPERF_MAKE_SIZE_FIXED(_struct) ((IMG_UINT32)(RGX_HWPERF_SIZE_MASK&(sizeof(RGX_HWPERF_V2_PACKET_HDR)+PVR_ALIGN(sizeof(_struct), PVRSRVTL_PACKET_ALIGNMENT))))
/*! Macro which takes the number of bytes written in the data payload of a
* packet for a variable size payload packet, rounded up to 8 bytes to
* align packets for 64 bit architectures. */
#define RGX_HWPERF_MAKE_SIZE_VARIABLE(_size) ((IMG_UINT32)(RGX_HWPERF_SIZE_MASK&((IMG_UINT32)sizeof(RGX_HWPERF_V2_PACKET_HDR)+PVR_ALIGN((_size), PVRSRVTL_PACKET_ALIGNMENT))))
/*! Macro to obtain the size of the packet */
#define RGX_HWPERF_GET_SIZE(_packet_addr) ((IMG_UINT16)(((_packet_addr)->ui32Size) & RGX_HWPERF_SIZE_MASK))
/*! Macro to obtain the size of the packet data */
#define RGX_HWPERF_GET_DATA_SIZE(_packet_addr) (RGX_HWPERF_GET_SIZE(_packet_addr) - sizeof(RGX_HWPERF_V2_PACKET_HDR))
/*! Masks for use with the IMG_UINT32 eTypeId header field */
#define RGX_HWPERF_TYPEID_MASK 0x0007FFFFU
#define RGX_HWPERF_TYPEID_EVENT_MASK 0x00007FFFU
#define RGX_HWPERF_TYPEID_THREAD_MASK 0x00008000U
#define RGX_HWPERF_TYPEID_STREAM_MASK 0x00070000U
#define RGX_HWPERF_TYPEID_META_DMA_MASK 0x00080000U
#define RGX_HWPERF_TYPEID_M_CORE_MASK 0x00100000U
#define RGX_HWPERF_TYPEID_OSID_MASK 0x07000000U
/*! Meta thread macros for encoding the ID into the type field of a packet */
#define RGX_HWPERF_META_THREAD_SHIFT 15U
#define RGX_HWPERF_META_THREAD_ID0 0x0U /*!< Meta Thread 0 ID */
#define RGX_HWPERF_META_THREAD_ID1 0x1U /*!< Meta Thread 1 ID */
/*! Obsolete, kept for source compatibility */
#define RGX_HWPERF_META_THREAD_MASK 0x1U
/*! Stream ID macros for encoding the ID into the type field of a packet */
#define RGX_HWPERF_STREAM_SHIFT 16U
/*! Meta DMA macro for encoding how the packet was generated into the type field of a packet */
#define RGX_HWPERF_META_DMA_SHIFT 19U
/*! Bit-shift macro used for encoding multi-core data into the type field of a packet */
#define RGX_HWPERF_M_CORE_SHIFT 20U
/*! OSID bit-shift macro used for encoding OSID into type field of a packet */
#define RGX_HWPERF_OSID_SHIFT 24U
typedef enum {
RGX_HWPERF_STREAM_ID0_FW, /*!< Events from the Firmware/GPU */
RGX_HWPERF_STREAM_ID1_HOST, /*!< Events from the Server host driver component */
RGX_HWPERF_STREAM_ID2_CLIENT, /*!< Events from the Client host driver component */
RGX_HWPERF_STREAM_ID_LAST,
} RGX_HWPERF_STREAM_ID;
/* Checks if all stream IDs can fit under RGX_HWPERF_TYPEID_STREAM_MASK. */
static_assert(((IMG_UINT32)RGX_HWPERF_STREAM_ID_LAST - 1U) < (RGX_HWPERF_TYPEID_STREAM_MASK >> RGX_HWPERF_STREAM_SHIFT),
"Too many HWPerf stream IDs.");
/*! Compile-time value used to seed the Multi-Core (MC) bit in the typeID field.
* Only set by RGX_FIRMWARE builds.
*/
#if defined(RGX_FIRMWARE)
# if defined(RGX_FEATURE_GPU_MULTICORE_SUPPORT)
#define RGX_HWPERF_M_CORE_VALUE 1U /*!< 1 => Multi-core supported */
# else
#define RGX_HWPERF_M_CORE_VALUE 0U /*!< 0 => Multi-core not supported */
# endif
#else
#define RGX_HWPERF_M_CORE_VALUE 0U /*!< 0 => Multi-core not supported */
#endif
/*! Macros used to set the packet type and encode meta thread ID (0|1),
* HWPerf stream ID, multi-core capability and OSID within the typeID */
#define RGX_HWPERF_MAKE_TYPEID(_stream, _type, _thread, _metadma, _osid)\
((IMG_UINT32) ((RGX_HWPERF_TYPEID_STREAM_MASK&((IMG_UINT32)(_stream) << RGX_HWPERF_STREAM_SHIFT)) | \
(RGX_HWPERF_TYPEID_THREAD_MASK & ((IMG_UINT32)(_thread) << RGX_HWPERF_META_THREAD_SHIFT)) | \
(RGX_HWPERF_TYPEID_EVENT_MASK & (IMG_UINT32)(_type)) | \
(RGX_HWPERF_TYPEID_META_DMA_MASK & ((IMG_UINT32)(_metadma) << RGX_HWPERF_META_DMA_SHIFT)) | \
(RGX_HWPERF_TYPEID_OSID_MASK & ((IMG_UINT32)(_osid) << RGX_HWPERF_OSID_SHIFT)) | \
(RGX_HWPERF_TYPEID_M_CORE_MASK & ((IMG_UINT32)(RGX_HWPERF_M_CORE_VALUE) << RGX_HWPERF_M_CORE_SHIFT))))
/*! Obtains the event type that generated the packet */
#define RGX_HWPERF_GET_TYPE(_packet_addr) (((_packet_addr)->eTypeId) & RGX_HWPERF_TYPEID_EVENT_MASK)
/*! Obtains the META Thread number that generated the packet */
#define RGX_HWPERF_GET_THREAD_ID(_packet_addr) (((((_packet_addr)->eTypeId) & RGX_HWPERF_TYPEID_THREAD_MASK) >> RGX_HWPERF_META_THREAD_SHIFT))
/*! Determines if the packet generated contains multi-core data */
#define RGX_HWPERF_GET_M_CORE(_packet_addr) (((_packet_addr)->eTypeId & RGX_HWPERF_TYPEID_M_CORE_MASK) >> RGX_HWPERF_M_CORE_SHIFT)
/*! Obtains the guest OSID which resulted in packet generation */
#define RGX_HWPERF_GET_OSID(_packet_addr) (((_packet_addr)->eTypeId & RGX_HWPERF_TYPEID_OSID_MASK) >> RGX_HWPERF_OSID_SHIFT)
/*! Obtain stream id */
#define RGX_HWPERF_GET_STREAM_ID(_packet_addr) (((((_packet_addr)->eTypeId) & RGX_HWPERF_TYPEID_STREAM_MASK) >> RGX_HWPERF_STREAM_SHIFT))
/*! Obtain information about how the packet was generated, which might affect payload total size */
#define RGX_HWPERF_GET_META_DMA_INFO(_packet_addr) (((((_packet_addr)->eTypeId) & RGX_HWPERF_TYPEID_META_DMA_MASK) >> RGX_HWPERF_META_DMA_SHIFT))
/*! Obtains a typed pointer to a packet given a buffer address */
#define RGX_HWPERF_GET_PACKET(_buffer_addr) ((RGX_HWPERF_V2_PACKET_HDR *)(void *) (_buffer_addr))
/*! Obtains a typed pointer to a data structure given a packet address */
#define RGX_HWPERF_GET_PACKET_DATA_BYTES(_packet_addr) (IMG_OFFSET_ADDR((_packet_addr), sizeof(RGX_HWPERF_V2_PACKET_HDR)))
/*! Obtains a typed pointer to the next packet given a packet address */
#define RGX_HWPERF_GET_NEXT_PACKET(_packet_addr) ((RGX_HWPERF_V2_PACKET_HDR *) (IMG_OFFSET_ADDR((_packet_addr), RGX_HWPERF_SIZE_MASK&((_packet_addr)->ui32Size))))
/*! Obtains a typed pointer to a packet header given the packet data address */
#define RGX_HWPERF_GET_PACKET_HEADER(_packet_addr) ((RGX_HWPERF_V2_PACKET_HDR *) (IMG_OFFSET_ADDR((_packet_addr), -(IMG_INT32)sizeof(RGX_HWPERF_V2_PACKET_HDR))))
/******************************************************************************
* Other Common Defines
*****************************************************************************/
/*! This macro is not a real array size, but indicates the array has a variable
* length only known at run-time but always contains at least 1 element. The
* final size of the array is deduced from the size field of a packet header.
*/
#define RGX_HWPERF_ONE_OR_MORE_ELEMENTS 1U
/*! This macro is not a real array size, but indicates the array is optional
* and if present has a variable length only known at run-time. The final
* size of the array is deduced from the size field of a packet header. */
#define RGX_HWPERF_ZERO_OR_MORE_ELEMENTS 1U
/*! Masks for use with the IMG_UINT32 ui32BlkInfo field */
#define RGX_HWPERF_BLKINFO_BLKCOUNT_MASK 0xFFFF0000U
#define RGX_HWPERF_BLKINFO_BLKOFFSET_MASK 0x0000FFFFU
/*! Shift for the NumBlocks and counter block offset field in ui32BlkInfo */
#define RGX_HWPERF_BLKINFO_BLKCOUNT_SHIFT 16U
#define RGX_HWPERF_BLKINFO_BLKOFFSET_SHIFT 0U
/*! Macro used to set the block info word as a combination of two 16-bit integers */
#define RGX_HWPERF_MAKE_BLKINFO(_numblks, _blkoffset) ((IMG_UINT32) ((RGX_HWPERF_BLKINFO_BLKCOUNT_MASK&((_numblks) << RGX_HWPERF_BLKINFO_BLKCOUNT_SHIFT)) | (RGX_HWPERF_BLKINFO_BLKOFFSET_MASK&((_blkoffset) << RGX_HWPERF_BLKINFO_BLKOFFSET_SHIFT))))
/*! Macro used to obtain the number of counter blocks present in the packet */
#define RGX_HWPERF_GET_BLKCOUNT(_blkinfo) (((_blkinfo) & RGX_HWPERF_BLKINFO_BLKCOUNT_MASK) >> RGX_HWPERF_BLKINFO_BLKCOUNT_SHIFT)
/*! Obtains the offset of the counter block stream in the packet */
#define RGX_HWPERF_GET_BLKOFFSET(_blkinfo) (((_blkinfo) & RGX_HWPERF_BLKINFO_BLKOFFSET_MASK) >> RGX_HWPERF_BLKINFO_BLKOFFSET_SHIFT)
/*! This macro gets the number of blocks depending on the packet version */
#define RGX_HWPERF_GET_NUMBLKS(_sig, _packet_data, _numblocks) \
do { \
if (HWPERF_PACKET_V2B_SIG == (_sig) || HWPERF_PACKET_V2C_SIG == (_sig)) \
{ \
(_numblocks) = RGX_HWPERF_GET_BLKCOUNT((_packet_data)->ui32BlkInfo);\
} \
else \
{ \
IMG_UINT32 ui32VersionOffset = (((_sig) == HWPERF_PACKET_V2_SIG) ? 1 : 3);\
(_numblocks) = *(IMG_UINT16 *)(IMG_OFFSET_ADDR(&(_packet_data)->ui32WorkTarget, ui32VersionOffset)); \
} \
} while (0)
/*! This macro gets the counter stream pointer depending on the packet version */
#define RGX_HWPERF_GET_CNTSTRM(_sig, _hw_packet_data, _cntstream_ptr) \
{ \
if (HWPERF_PACKET_V2B_SIG == (_sig) || HWPERF_PACKET_V2C_SIG == (_sig)) \
{ \
(_cntstream_ptr) = (IMG_UINT32 *)(IMG_OFFSET_ADDR((_hw_packet_data), RGX_HWPERF_GET_BLKOFFSET((_hw_packet_data)->ui32BlkInfo))); \
} \
else \
{ \
IMG_UINT32 ui32BlkStreamOffsetInWords = (((_sig) == HWPERF_PACKET_V2_SIG) ? 6 : 8); \
(_cntstream_ptr) = (IMG_UINT32 *)(IMG_OFFSET_ADDR_DW((_hw_packet_data), ui32BlkStreamOffsetInWords)); \
} \
}
/*! Masks for use with the IMG_UINT32 ui32KickInfo field */
#define RGX_HWPERF_KICKINFO_KICKID_MASK 0x000000FFU
/*! Shift for the Kick ID field in ui32KickInfo */
#define RGX_HWPERF_KICKINFO_KICKID_SHIFT 0U
/*! Macro used to set the kick info field. */
#define RGX_HWPERF_MAKE_KICKINFO(_kickid) ((IMG_UINT32) (RGX_HWPERF_KICKINFO_KICKID_MASK&((_kickid) << RGX_HWPERF_KICKINFO_KICKID_SHIFT)))
/*! Macro used to obtain the Kick ID if present in the packet */
#define RGX_HWPERF_GET_KICKID(_kickinfo) (((_kickinfo) & RGX_HWPERF_KICKINFO_KICKID_MASK) >> RGX_HWPERF_KICKINFO_KICKID_SHIFT)
/*! Masks for use with the RGX_HWPERF_UFO_EV eEvType field */
#define RGX_HWPERF_UFO_STREAMSIZE_MASK 0xFFFF0000U
#define RGX_HWPERF_UFO_STREAMOFFSET_MASK 0x0000FFFFU
/*! Shift for the UFO count and data stream fields */
#define RGX_HWPERF_UFO_STREAMSIZE_SHIFT 16U
#define RGX_HWPERF_UFO_STREAMOFFSET_SHIFT 0U
/*! Macro used to set UFO stream info word as a combination of two 16-bit integers */
#define RGX_HWPERF_MAKE_UFOPKTINFO(_ssize, _soff) \
((IMG_UINT32) ((RGX_HWPERF_UFO_STREAMSIZE_MASK&((_ssize) << RGX_HWPERF_UFO_STREAMSIZE_SHIFT)) | \
(RGX_HWPERF_UFO_STREAMOFFSET_MASK&((_soff) << RGX_HWPERF_UFO_STREAMOFFSET_SHIFT))))
/*! Macro used to obtain UFO count*/
#define RGX_HWPERF_GET_UFO_STREAMSIZE(_streaminfo) \
(((_streaminfo) & RGX_HWPERF_UFO_STREAMSIZE_MASK) >> RGX_HWPERF_UFO_STREAMSIZE_SHIFT)
/*! Obtains the offset of the UFO stream in the packet */
#define RGX_HWPERF_GET_UFO_STREAMOFFSET(_streaminfo) \
(((_streaminfo) & RGX_HWPERF_UFO_STREAMOFFSET_MASK) >> RGX_HWPERF_UFO_STREAMOFFSET_SHIFT)
#if defined(__cplusplus)
}
#endif
#endif /* RGX_HWPERF_COMMON_H_ */
/******************************************************************************
End of file
******************************************************************************/

12
drivers/gpu/drm/img-rogue/include/rgx_meta.h
View File

@@ -74,7 +74,7 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define META_CR_PERF_COUNT_THR_SHIFT (24)
#define META_CR_PERF_COUNT_THR_MASK (0x0F000000)
#define META_CR_PERF_COUNT_THR_0 (IMG_UINT32_C(0x1) << META_CR_PERF_COUNT_THR_SHIFT)
#define META_CR_PERF_COUNT_THR_1 (IMG_UINT32_C(0x2) << META_CR_PERF_COUNT_THR_1)
#define META_CR_PERF_COUNT_THR_1 (IMG_UINT32_C(0x2) << META_CR_PERF_COUNT_THR_SHIFT)
#define META_CR_TxVECINT_BHALT (0x04820500)
#define META_CR_PERF_ICORE0 (0x0480FFD0)
@@ -248,11 +248,11 @@ typedef struct
* The interface has been kept the same to simplify the code changes.
* The bifdm argument is ignored (no longer relevant) in S7 and volcanic.
*/
#define RGXFW_SEGMMU_OUTADDR_TOP_VIVT_SLC(pers, slc_policy, mmu_ctx) ((((IMG_UINT64) ((pers) & 0x3)) << 52) | \
(((IMG_UINT64) ((mmu_ctx) & 0xFF)) << 44) | \
(((IMG_UINT64) ((slc_policy) & 0x1)) << 40))
#define RGXFW_SEGMMU_OUTADDR_TOP_VIVT_SLC_CACHED(mmu_ctx) RGXFW_SEGMMU_OUTADDR_TOP_VIVT_SLC(0x3, 0x0, mmu_ctx)
#define RGXFW_SEGMMU_OUTADDR_TOP_VIVT_SLC_UNCACHED(mmu_ctx) RGXFW_SEGMMU_OUTADDR_TOP_VIVT_SLC(0x0, 0x1, mmu_ctx)
#define RGXFW_SEGMMU_OUTADDR_TOP_VIVT_SLC(pers, slc_policy, mmu_ctx) ((((IMG_UINT64) ((pers) & 0x3U)) << 52) | \
(((IMG_UINT64) ((mmu_ctx) & 0xFFU)) << 44) | \
(((IMG_UINT64) ((slc_policy) & 0x1U)) << 40))
#define RGXFW_SEGMMU_OUTADDR_TOP_VIVT_SLC_CACHED(mmu_ctx) RGXFW_SEGMMU_OUTADDR_TOP_VIVT_SLC(0x3U, 0x0U, mmu_ctx)
#define RGXFW_SEGMMU_OUTADDR_TOP_VIVT_SLC_UNCACHED(mmu_ctx) RGXFW_SEGMMU_OUTADDR_TOP_VIVT_SLC(0x0U, 0x1U, mmu_ctx)
/* To configure the Page Catalog and BIF-DM fed into the BIF for Garten
* accesses through this segment

36
drivers/gpu/drm/img-rogue/include/rgx_mips.h
View File

@@ -72,7 +72,7 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
/* Total number of TLB entries */
#define RGXMIPSFW_NUMBER_OF_TLB_ENTRIES (16)
/* "Uncached" caching policy */
#define RGXMIPSFW_UNCACHED_CACHE_POLICY (0X00000002)
#define RGXMIPSFW_UNCACHED_CACHE_POLICY (0X00000002U)
/* "Write-back write-allocate" caching policy */
#define RGXMIPSFW_WRITEBACK_CACHE_POLICY (0X00000003)
/* "Write-through no write-allocate" caching policy */
@@ -91,11 +91,11 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define RGXMIPSFW_ENTRYLO_READ_INHIBIT_SHIFT (31U)
#define RGXMIPSFW_ENTRYLO_READ_INHIBIT_CLRMSK (0X7FFFFFFF)
#define RGXMIPSFW_ENTRYLO_READ_INHIBIT_EN (0X80000000)
#define RGXMIPSFW_ENTRYLO_READ_INHIBIT_EN (0X80000000U)
#define RGXMIPSFW_ENTRYLO_EXEC_INHIBIT_SHIFT (30U)
#define RGXMIPSFW_ENTRYLO_EXEC_INHIBIT_CLRMSK (0XBFFFFFFF)
#define RGXMIPSFW_ENTRYLO_EXEC_INHIBIT_EN (0X40000000)
#define RGXMIPSFW_ENTRYLO_EXEC_INHIBIT_EN (0X40000000U)
/* Page Frame Number */
#define RGXMIPSFW_ENTRYLO_PFN_SHIFT (6)
@@ -104,25 +104,25 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define RGXMIPSFW_ENTRYLO_PFN_MASK (0x03FFFFC0)
#define RGXMIPSFW_ENTRYLO_PFN_SIZE (20)
/* Mask used for the MIPS Page Table in case of physical bus on more than 32 bit */
#define RGXMIPSFW_ENTRYLO_PFN_MASK_ABOVE_32BIT (0x3FFFFFC0)
#define RGXMIPSFW_ENTRYLO_PFN_MASK_ABOVE_32BIT (0x3FFFFFC0U)
#define RGXMIPSFW_ENTRYLO_PFN_SIZE_ABOVE_32BIT (24)
#define RGXMIPSFW_ADDR_TO_ENTRYLO_PFN_RSHIFT (RGXMIPSFW_ENTRYLO_PFN_ALIGNSHIFT - \
RGXMIPSFW_ENTRYLO_PFN_SHIFT)
#define RGXMIPSFW_ENTRYLO_CACHE_POLICY_SHIFT (3U)
#define RGXMIPSFW_ENTRYLO_CACHE_POLICY_CLRMSK (0XFFFFFFC7)
#define RGXMIPSFW_ENTRYLO_CACHE_POLICY_CLRMSK (0XFFFFFFC7U)
#define RGXMIPSFW_ENTRYLO_DIRTY_SHIFT (2U)
#define RGXMIPSFW_ENTRYLO_DIRTY_CLRMSK (0XFFFFFFFB)
#define RGXMIPSFW_ENTRYLO_DIRTY_EN (0X00000004)
#define RGXMIPSFW_ENTRYLO_DIRTY_EN (0X00000004U)
#define RGXMIPSFW_ENTRYLO_VALID_SHIFT (1U)
#define RGXMIPSFW_ENTRYLO_VALID_CLRMSK (0XFFFFFFFD)
#define RGXMIPSFW_ENTRYLO_VALID_EN (0X00000002)
#define RGXMIPSFW_ENTRYLO_VALID_EN (0X00000002U)
#define RGXMIPSFW_ENTRYLO_GLOBAL_SHIFT (0U)
#define RGXMIPSFW_ENTRYLO_GLOBAL_CLRMSK (0XFFFFFFFE)
#define RGXMIPSFW_ENTRYLO_GLOBAL_EN (0X00000001)
#define RGXMIPSFW_ENTRYLO_GLOBAL_EN (0X00000001U)
#define RGXMIPSFW_ENTRYLO_DVG (RGXMIPSFW_ENTRYLO_DIRTY_EN | \
RGXMIPSFW_ENTRYLO_VALID_EN | \
@@ -158,14 +158,14 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#define RGXMIPSFW_TRAMPOLINE_LOG2_NUMPAGES (2)
#define RGXMIPSFW_TRAMPOLINE_NUMPAGES (1 << RGXMIPSFW_TRAMPOLINE_LOG2_NUMPAGES)
#define RGXMIPSFW_TRAMPOLINE_NUMPAGES (1U << RGXMIPSFW_TRAMPOLINE_LOG2_NUMPAGES)
#define RGXMIPSFW_TRAMPOLINE_SIZE (RGXMIPSFW_TRAMPOLINE_NUMPAGES << RGXMIPSFW_LOG2_PAGE_SIZE_4K)
#define RGXMIPSFW_TRAMPOLINE_LOG2_SEGMENT_SIZE (RGXMIPSFW_TRAMPOLINE_LOG2_NUMPAGES + RGXMIPSFW_LOG2_PAGE_SIZE_4K)
#define RGXMIPSFW_TRAMPOLINE_TARGET_PHYS_ADDR (RGXMIPSFW_BOOT_REMAP_PHYS_ADDR_IN)
#define RGXMIPSFW_TRAMPOLINE_OFFSET(a) (a - RGXMIPSFW_BOOT_REMAP_PHYS_ADDR_IN)
#define RGXMIPSFW_SENSITIVE_ADDR(a) (RGXMIPSFW_BOOT_REMAP_PHYS_ADDR_IN == (~((1UL << RGXMIPSFW_TRAMPOLINE_LOG2_SEGMENT_SIZE)-1) & a))
#define RGXMIPSFW_SENSITIVE_ADDR(a) (RGXMIPSFW_BOOT_REMAP_PHYS_ADDR_IN == (~((1UL << RGXMIPSFW_TRAMPOLINE_LOG2_SEGMENT_SIZE)-1U) & a))
/*
* Firmware virtual layout and remap configuration
@@ -183,20 +183,20 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
/* Boot remap setup */
#define RGXMIPSFW_BOOT_REMAP_VIRTUAL_BASE (0xBFC00000)
#define RGXMIPSFW_BOOT_REMAP_PHYS_ADDR_IN (0x1FC00000)
#define RGXMIPSFW_BOOT_REMAP_PHYS_ADDR_IN (0x1FC00000U)
#define RGXMIPSFW_BOOT_REMAP_LOG2_SEGMENT_SIZE (12)
#define RGXMIPSFW_BOOT_NMI_CODE_VIRTUAL_BASE (RGXMIPSFW_BOOT_REMAP_VIRTUAL_BASE)
/* Data remap setup */
#define RGXMIPSFW_DATA_REMAP_VIRTUAL_BASE (0xBFC01000)
#define RGXMIPSFW_DATA_CACHED_REMAP_VIRTUAL_BASE (0x9FC01000)
#define RGXMIPSFW_DATA_REMAP_PHYS_ADDR_IN (0x1FC01000)
#define RGXMIPSFW_DATA_REMAP_PHYS_ADDR_IN (0x1FC01000U)
#define RGXMIPSFW_DATA_REMAP_LOG2_SEGMENT_SIZE (12)
#define RGXMIPSFW_BOOT_NMI_DATA_VIRTUAL_BASE (RGXMIPSFW_DATA_REMAP_VIRTUAL_BASE)
/* Code remap setup */
#define RGXMIPSFW_CODE_REMAP_VIRTUAL_BASE (0x9FC02000)
#define RGXMIPSFW_CODE_REMAP_PHYS_ADDR_IN (0x1FC02000)
#define RGXMIPSFW_CODE_REMAP_PHYS_ADDR_IN (0x1FC02000U)
#define RGXMIPSFW_CODE_REMAP_LOG2_SEGMENT_SIZE (12)
#define RGXMIPSFW_EXCEPTIONS_VIRTUAL_BASE (RGXMIPSFW_CODE_REMAP_VIRTUAL_BASE)
@@ -211,7 +211,7 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
/* Bootloader configuration offset (where RGXMIPSFW_BOOT_DATA lives)
* within the bootloader/NMI data page */
#define RGXMIPSFW_BOOTLDR_CONF_OFFSET (0x0)
#define RGXMIPSFW_BOOTLDR_CONF_OFFSET (0x0U)
/*
@@ -292,10 +292,10 @@ typedef struct
#define RGXMIPSFW_C0_NBHWIRQ 8
/* Macros to decode C0_Cause register */
#define RGXMIPSFW_C0_CAUSE_EXCCODE(CAUSE) (((CAUSE) & 0x7c) >> 2)
#define RGXMIPSFW_C0_CAUSE_EXCCODE(CAUSE) (((CAUSE) & 0x7cU) >> 2U)
#define RGXMIPSFW_C0_CAUSE_EXCCODE_FWERROR 9
/* Use only when Coprocessor Unusable exception */
#define RGXMIPSFW_C0_CAUSE_UNUSABLE_UNIT(CAUSE) (((CAUSE) >> 28) & 0x3)
#define RGXMIPSFW_C0_CAUSE_UNUSABLE_UNIT(CAUSE) (((CAUSE) >> 28U) & 0x3U)
#define RGXMIPSFW_C0_CAUSE_PENDING_HWIRQ(CAUSE) (((CAUSE) & 0x3fc00) >> 10)
#define RGXMIPSFW_C0_CAUSE_FDCIPENDING (1UL << 21)
#define RGXMIPSFW_C0_CAUSE_IV (1UL << 23)
@@ -305,7 +305,7 @@ typedef struct
#define RGXMIPSFW_C0_CAUSE_BRANCH_DELAY (1UL << 31)
/* Macros to decode C0_Debug register */
#define RGXMIPSFW_C0_DEBUG_EXCCODE(DEBUG) (((DEBUG) >> 10) & 0x1f)
#define RGXMIPSFW_C0_DEBUG_EXCCODE(DEBUG) (((DEBUG) >> 10U) & 0x1fU)
#define RGXMIPSFW_C0_DEBUG_DSS (1UL << 0)
#define RGXMIPSFW_C0_DEBUG_DBP (1UL << 1)
#define RGXMIPSFW_C0_DEBUG_DDBL (1UL << 2)
@@ -325,7 +325,7 @@ typedef struct
/* Macros to decode TLB entries */
#define RGXMIPSFW_TLB_GET_MASK(PAGE_MASK) (((PAGE_MASK) >> 13) & 0XFFFFU)
#define RGXMIPSFW_TLB_GET_PAGE_SIZE(PAGE_MASK) ((((PAGE_MASK) | 0x1FFF) + 1) >> 11) /* page size in KB */
#define RGXMIPSFW_TLB_GET_PAGE_SIZE(PAGE_MASK) ((((PAGE_MASK) | 0x1FFFU) + 1U) >> 11U) /* page size in KB */
#define RGXMIPSFW_TLB_GET_PAGE_MASK(PAGE_SIZE) ((((PAGE_SIZE) << 11) - 1) & ~0x7FF) /* page size in KB */
#define RGXMIPSFW_TLB_GET_VPN2(ENTRY_HI) ((ENTRY_HI) >> 13)
#define RGXMIPSFW_TLB_GET_COHERENCY(ENTRY_LO) (((ENTRY_LO) >> 3) & 0x7U)

2
drivers/gpu/drm/img-rogue/include/rgx_riscv.h
View File

@@ -76,7 +76,7 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define RGXRISCVFW_COREMEM_REGION IMG_UINT32_C(0x8)
#define RGXRISCVFW_COREMEM_MAX_SIZE IMG_UINT32_C(0x10000000) /* 256 MB */
#define RGXRISCVFW_COREMEM_BASE (RGXRISCVFW_GET_REGION_BASE(RGXRISCVFW_COREMEM_REGION))
#define RGXRISCVFW_COREMEM_END (RGXRISCVFW_COREMEM_BASE + RGXRISCVFW_COREMEM_MAX_SIZE - 1)
#define RGXRISCVFW_COREMEM_END (RGXRISCVFW_COREMEM_BASE + RGXRISCVFW_COREMEM_MAX_SIZE - 1U)
/*

34
drivers/gpu/drm/img-rogue/include/rogue/rgx_fwif_hwperf.h
View File

@@ -68,6 +68,20 @@ typedef struct
IMG_UINT32 aui32SelectedCountersIDs[RGX_HWPERF_MAX_CUSTOM_CNTRS];
} RGXFW_HWPERF_SELECT;
/* Structure used to hold a Direct-Addressable block's parameters for passing
* between the BG context and the IRQ context when applying a configuration
* request. RGX_FEATURE_HWPERF_OCEANIC use only.
*/
typedef struct
{
IMG_UINT32 uiEnabled;
IMG_UINT32 uiNumCounters;
IMG_UINT32 eBlockID;
RGXFWIF_DEV_VIRTADDR psModel;
IMG_UINT32 aui32Counters[RGX_CNTBLK_COUNTERS_MAX];
} RGXFWIF_HWPERF_DA_BLK;
/* Structure to hold the whole configuration request details for all blocks
* The block masks and counts are used to optimise reading of this data. */
typedef struct
@@ -77,8 +91,8 @@ typedef struct
IMG_UINT32 ui32SelectedCountersBlockMask;
RGXFW_HWPERF_SELECT RGXFW_ALIGN SelCntr[RGX_HWPERF_MAX_CUSTOM_BLKS];
IMG_UINT32 ui32EnabledBlksCount;
RGXFWIF_HWPERF_CTL_BLK RGXFW_ALIGN sBlkCfg[RGX_HWPERF_MAX_DEFINED_BLKS];
IMG_UINT32 ui32EnabledMUXBlksCount;
RGXFWIF_HWPERF_CTL_BLK RGXFW_ALIGN sBlkCfg[RGX_HWPERF_MAX_MUX_BLKS];
} UNCACHED_ALIGN RGXFWIF_HWPERF_CTL;
/* NOTE: The switch statement in this function must be kept in alignment with
@@ -90,7 +104,7 @@ typedef struct
#ifdef INLINE_IS_PRAGMA
#pragma inline(rgxfw_hwperf_get_block_ctl)
#endif
static INLINE RGXFWIF_HWPERF_CTL_BLK* rgxfw_hwperf_get_block_ctl(
static INLINE RGXFWIF_HWPERF_CTL_BLK *rgxfw_hwperf_get_block_ctl(
RGX_HWPERF_CNTBLK_ID eBlockID, RGXFWIF_HWPERF_CTL *psHWPerfInitData)
{
IMG_UINT32 ui32Idx;
@@ -221,4 +235,18 @@ static INLINE RGXFWIF_HWPERF_CTL_BLK* rgxfw_hwperf_get_block_ctl(
return &psHWPerfInitData->sBlkCfg[ui32Idx];
}
/* Stub routine for rgxfw_hwperf_get_da_block_ctl() for non
* RGX_FEATURE_HWPERF_OCEANIC systems. Just return a NULL.
*/
#ifdef INLINE_IS_PRAGMA
#pragma inline(rgxfw_hwperf_get_da_block_ctl)
#endif
static INLINE RGXFWIF_HWPERF_DA_BLK* rgxfw_hwperf_get_da_block_ctl(
RGX_HWPERF_CNTBLK_ID eBlockID, RGXFWIF_HWPERF_CTL *psHWPerfInitData)
{
PVR_UNREFERENCED_PARAMETER(eBlockID);
PVR_UNREFERENCED_PARAMETER(psHWPerfInitData);
return NULL;
}
#endif

340
drivers/gpu/drm/img-rogue/include/rogue/rgx_fwif_km.h
View File

@@ -109,21 +109,21 @@ typedef struct {
#define RGXFWIF_LOG_ENABLED_GROUPS_LIST_PFSPEC "%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s"
/* Used in a print statement to display log group state, one per group */
#define RGXFWIF_LOG_ENABLED_GROUPS_LIST(types) (((types) & RGXFWIF_LOG_TYPE_GROUP_MAIN) ?("main ") :("")), \
(((types) & RGXFWIF_LOG_TYPE_GROUP_MTS) ?("mts ") :("")), \
(((types) & RGXFWIF_LOG_TYPE_GROUP_CLEANUP) ?("cleanup ") :("")), \
(((types) & RGXFWIF_LOG_TYPE_GROUP_CSW) ?("csw ") :("")), \
(((types) & RGXFWIF_LOG_TYPE_GROUP_BIF) ?("bif ") :("")), \
(((types) & RGXFWIF_LOG_TYPE_GROUP_PM) ?("pm ") :("")), \
(((types) & RGXFWIF_LOG_TYPE_GROUP_RTD) ?("rtd ") :("")), \
(((types) & RGXFWIF_LOG_TYPE_GROUP_SPM) ?("spm ") :("")), \
(((types) & RGXFWIF_LOG_TYPE_GROUP_POW) ?("pow ") :("")), \
(((types) & RGXFWIF_LOG_TYPE_GROUP_HWR) ?("hwr ") :("")), \
(((types) & RGXFWIF_LOG_TYPE_GROUP_HWP) ?("hwp ") :("")), \
(((types) & RGXFWIF_LOG_TYPE_GROUP_RPM) ?("rpm ") :("")), \
(((types) & RGXFWIF_LOG_TYPE_GROUP_DMA) ?("dma ") :("")), \
(((types) & RGXFWIF_LOG_TYPE_GROUP_MISC) ?("misc ") :("")), \
(((types) & RGXFWIF_LOG_TYPE_GROUP_DEBUG) ?("debug ") :(""))
#define RGXFWIF_LOG_ENABLED_GROUPS_LIST(types) ((((types) & RGXFWIF_LOG_TYPE_GROUP_MAIN) != 0U) ?("main ") :("")), \
((((types) & RGXFWIF_LOG_TYPE_GROUP_MTS) != 0U) ?("mts ") :("")), \
((((types) & RGXFWIF_LOG_TYPE_GROUP_CLEANUP) != 0U) ?("cleanup ") :("")), \
((((types) & RGXFWIF_LOG_TYPE_GROUP_CSW) != 0U) ?("csw ") :("")), \
((((types) & RGXFWIF_LOG_TYPE_GROUP_BIF) != 0U) ?("bif ") :("")), \
((((types) & RGXFWIF_LOG_TYPE_GROUP_PM) != 0U) ?("pm ") :("")), \
((((types) & RGXFWIF_LOG_TYPE_GROUP_RTD) != 0U) ?("rtd ") :("")), \
((((types) & RGXFWIF_LOG_TYPE_GROUP_SPM) != 0U) ?("spm ") :("")), \
((((types) & RGXFWIF_LOG_TYPE_GROUP_POW) != 0U) ?("pow ") :("")), \
((((types) & RGXFWIF_LOG_TYPE_GROUP_HWR) != 0U) ?("hwr ") :("")), \
((((types) & RGXFWIF_LOG_TYPE_GROUP_HWP) != 0U) ?("hwp ") :("")), \
((((types) & RGXFWIF_LOG_TYPE_GROUP_RPM) != 0U) ?("rpm ") :("")), \
((((types) & RGXFWIF_LOG_TYPE_GROUP_DMA) != 0U) ?("dma ") :("")), \
((((types) & RGXFWIF_LOG_TYPE_GROUP_MISC) != 0U) ?("misc ") :("")), \
((((types) & RGXFWIF_LOG_TYPE_GROUP_DEBUG) != 0U) ?("debug ") :(""))
/************************************************************************
@@ -156,20 +156,31 @@ typedef struct
IMG_UINT32 ui32LineNum;
} UNCACHED_ALIGN RGXFWIF_FILE_INFO_BUF;
/*!
* @Defgroup SRVAndFWTracing Services and Firmware Tracing data interface
* @Brief The document groups/lists the data structures and the interfaces related to Services and Firmware Tracing
* @{
*/
/*!
* @Brief Firmware trace buffer details
*/
typedef struct
{
IMG_UINT32 ui32TracePointer;
IMG_UINT32 ui32TracePointer; /*!< Trace pointer (write index into Trace Buffer)*/
#if defined(RGX_FIRMWARE)
IMG_UINT32 *pui32RGXFWIfTraceBuffer; /* To be used by firmware for writing into trace buffer */
IMG_UINT32 *pui32RGXFWIfTraceBuffer; /*!< Trace buffer address (FW address), to be used by firmware for writing into trace buffer */
#else
RGXFWIF_DEV_VIRTADDR pui32RGXFWIfTraceBuffer;
RGXFWIF_DEV_VIRTADDR pui32RGXFWIfTraceBuffer; /*!< Trace buffer address (FW address)*/
#endif
IMG_PUINT32 pui32TraceBuffer; /* To be used by host when reading from trace buffer */
IMG_PUINT32 pui32TraceBuffer; /*!< Trace buffer address (Host address), to be used by host when reading from trace buffer */
RGXFWIF_FILE_INFO_BUF sAssertBuf;
RGXFWIF_FILE_INFO_BUF sAssertBuf;
} UNCACHED_ALIGN RGXFWIF_TRACEBUF_SPACE;
/*! @} End of Defgroup SRVAndFWTracing */
#define RGXFWIF_FWFAULTINFO_MAX (8U) /* Total number of FW fault logs stored */
typedef struct
@@ -229,14 +240,12 @@ typedef IMG_UINT32 RGXFWIF_HWR_STATEFLAGS;
#define RGXFWIF_DM_STATE_GPU_ECC_HWR (IMG_UINT32_C(0x1) << 10) /*!< DM was forced into HWR due to an uncorrected GPU ECC error */
/* Firmware's connection state */
typedef enum
{
RGXFW_CONNECTION_FW_OFFLINE = 0, /*!< Firmware is offline */
RGXFW_CONNECTION_FW_READY, /*!< Firmware is initialised */
RGXFW_CONNECTION_FW_ACTIVE, /*!< Firmware connection is fully established */
RGXFW_CONNECTION_FW_OFFLOADING, /*!< Firmware is clearing up connection data */
RGXFW_CONNECTION_FW_STATE_COUNT
} RGXFWIF_CONNECTION_FW_STATE;
typedef IMG_UINT32 RGXFWIF_CONNECTION_FW_STATE;
#define RGXFW_CONNECTION_FW_OFFLINE 0U /*!< Firmware is offline */
#define RGXFW_CONNECTION_FW_READY 1U /*!< Firmware is initialised */
#define RGXFW_CONNECTION_FW_ACTIVE 2U /*!< Firmware connection is fully established */
#define RGXFW_CONNECTION_FW_OFFLOADING 3U /*!< Firmware is clearing up connection data */
#define RGXFW_CONNECTION_FW_STATE_COUNT 4U
/* OS' connection state */
typedef enum
@@ -259,7 +268,7 @@ typedef struct
typedef IMG_UINT32 RGXFWIF_HWR_RECOVERYFLAGS;
#if defined(PVRSRV_STALLED_CCB_ACTION)
#define PVR_SLR_LOG_ENTRIES 10
#define PVR_SLR_LOG_ENTRIES 10U
#define PVR_SLR_LOG_STRLEN 30 /*!< MAX_CLIENT_CCB_NAME not visible to this header */
typedef struct
@@ -271,14 +280,17 @@ typedef struct
} UNCACHED_ALIGN RGXFWIF_SLR_ENTRY;
#endif
/* firmware trace control data */
/*!
* @InGroup SRVAndFWTracing
* @Brief Firmware trace control data
*/
typedef struct
{
IMG_UINT32 ui32LogType;
RGXFWIF_TRACEBUF_SPACE sTraceBuf[RGXFW_THREAD_NUM];
IMG_UINT32 ui32TraceBufSizeInDWords; /*!< Member initialised only when sTraceBuf is actually allocated
* (in RGXTraceBufferInitOnDemandResources) */
IMG_UINT32 ui32TracebufFlags; /*!< Compatibility and other flags */
IMG_UINT32 ui32LogType; /*!< FW trace log group configuration */
RGXFWIF_TRACEBUF_SPACE sTraceBuf[RGXFW_THREAD_NUM]; /*!< FW Trace buffer */
IMG_UINT32 ui32TraceBufSizeInDWords; /*!< FW Trace buffer size in dwords, Member initialised only when sTraceBuf is actually allocated
(in RGXTraceBufferInitOnDemandResources) */
IMG_UINT32 ui32TracebufFlags; /*!< Compatibility and other flags */
} UNCACHED_ALIGN RGXFWIF_TRACEBUF;
/*! @Brief Firmware system data shared with the Host driver */
@@ -320,6 +332,7 @@ typedef struct
RGXFWIF_HWR_STATEFLAGS ui32HWRStateFlags; /*!< Firmware's Current HWR state */
RGXFWIF_HWR_RECOVERYFLAGS aui32HWRRecoveryFlags[RGXFWIF_DM_MAX]; /*!< Each DM's HWR state */
IMG_UINT32 ui32FwSysDataFlags; /*!< Compatibility and other flags */
IMG_UINT32 ui32McConfig; /*!< Identify whether MC config is P-P or P-S */
} UNCACHED_ALIGN RGXFWIF_SYSDATA;
/*!
@@ -533,18 +546,13 @@ typedef struct
#define RGXFWIF_INICFG_FBCDC_V3_1_EN (IMG_UINT32_C(0x1) << 6)
#define RGXFWIF_INICFG_CHECK_MLIST_EN (IMG_UINT32_C(0x1) << 7)
#define RGXFWIF_INICFG_DISABLE_CLKGATING_EN (IMG_UINT32_C(0x1) << 8)
#define RGXFWIF_INICFG_POLL_COUNTERS_EN (IMG_UINT32_C(0x1) << 9)
#define RGXFWIF_INICFG_VDM_CTX_STORE_MODE_SHIFT (10)
#define RGXFWIF_INICFG_VDM_CTX_STORE_MODE_INDEX ((IMG_UINT32)RGX_CR_VDM_CONTEXT_STORE_MODE_MODE_INDEX << RGXFWIF_INICFG_VDM_CTX_STORE_MODE_SHIFT)
#define RGXFWIF_INICFG_VDM_CTX_STORE_MODE_INSTANCE ((IMG_UINT32)RGX_CR_VDM_CONTEXT_STORE_MODE_MODE_INSTANCE << RGXFWIF_INICFG_VDM_CTX_STORE_MODE_SHIFT)
#define RGXFWIF_INICFG_VDM_CTX_STORE_MODE_LIST ((IMG_UINT32)RGX_CR_VDM_CONTEXT_STORE_MODE_MODE_LIST << RGXFWIF_INICFG_VDM_CTX_STORE_MODE_SHIFT)
#define RGXFWIF_INICFG_VDM_CTX_STORE_MODE_MASK (RGXFWIF_INICFG_VDM_CTX_STORE_MODE_INDEX |\
RGXFWIF_INICFG_VDM_CTX_STORE_MODE_INSTANCE |\
RGXFWIF_INICFG_VDM_CTX_STORE_MODE_LIST)
/* 9 unused */
/* 10 unused */
/* 11 unused */
#define RGXFWIF_INICFG_REGCONFIG_EN (IMG_UINT32_C(0x1) << 12)
#define RGXFWIF_INICFG_ASSERT_ON_OUTOFMEMORY (IMG_UINT32_C(0x1) << 13)
#define RGXFWIF_INICFG_HWP_DISABLE_FILTER (IMG_UINT32_C(0x1) << 14)
#define RGXFWIF_INICFG_CUSTOM_PERF_TIMER_EN (IMG_UINT32_C(0x1) << 15)
/* 15 unused */
#define RGXFWIF_INICFG_CTXSWITCH_PROFILE_SHIFT (16)
#define RGXFWIF_INICFG_CTXSWITCH_PROFILE_FAST (RGXFWIF_CTXSWITCH_PROFILE_FAST_EN << RGXFWIF_INICFG_CTXSWITCH_PROFILE_SHIFT)
#define RGXFWIF_INICFG_CTXSWITCH_PROFILE_MEDIUM (RGXFWIF_CTXSWITCH_PROFILE_MEDIUM_EN << RGXFWIF_INICFG_CTXSWITCH_PROFILE_SHIFT)
@@ -575,7 +583,12 @@ typedef struct
/* Extended Flag definitions affecting the firmware globally */
#define RGXFWIF_INICFG_EXT_TFBC_CONTROL_SHIFT (0)
#define RGXFWIF_INICFG_EXT_TFBC_CONTROL_MASK (IMG_UINT32_C(0x7F)) /* RGX_CR_TFBC_COMPRESSION_CONTROL_MASKFULL */
/* [7] YUV10 override
* [6:4] Quality
* [3] Quality enable
* [2:1] Compression scheme
* [0] Lossy group */
#define RGXFWIF_INICFG_EXT_TFBC_CONTROL_MASK (IMG_UINT32_C(0xFF)) /* RGX_CR_TFBC_COMPRESSION_CONTROL_MASKFULL */
#define RGXFWIF_INICFG_EXT_ALL (RGXFWIF_INICFG_EXT_TFBC_CONTROL_MASK)
#define RGXFWIF_INICFG_SYS_CTXSWITCH_CLRMSK ~(RGXFWIF_INICFG_CTXSWITCH_MODE_RAND | \
@@ -599,7 +612,7 @@ typedef struct
#define RGXFWIF_INICFG_OS_LOW_PRIO_CS_3D (IMG_UINT32_C(0x1) << 6)
#define RGXFWIF_INICFG_OS_LOW_PRIO_CS_CDM (IMG_UINT32_C(0x1) << 7)
#define RGXFWIF_INICFG_OS_ALL (0xFF)
#define RGXFWIF_INICFG_OS_ALL (0xFFU)
#define RGXFWIF_INICFG_OS_CTXSWITCH_DM_ALL (RGXFWIF_INICFG_OS_CTXSWITCH_GEOM_EN | \
RGXFWIF_INICFG_OS_CTXSWITCH_3D_EN | \
@@ -617,12 +630,10 @@ typedef struct
#define RGXFWIF_FILTCFG_TRUNCATE_INT (IMG_UINT32_C(0x1) << 2)
#define RGXFWIF_FILTCFG_NEW_FILTER_MODE (IMG_UINT32_C(0x1) << 1)
typedef enum
{
RGX_ACTIVEPM_FORCE_OFF = 0,
RGX_ACTIVEPM_FORCE_ON = 1,
RGX_ACTIVEPM_DEFAULT = 2
} RGX_ACTIVEPM_CONF;
typedef IMG_UINT32 RGX_ACTIVEPM_CONF;
#define RGX_ACTIVEPM_FORCE_OFF 0U
#define RGX_ACTIVEPM_FORCE_ON 1U
#define RGX_ACTIVEPM_DEFAULT 2U
typedef enum
{
@@ -675,6 +686,7 @@ typedef RGXFWIF_DEV_VIRTADDR PRGXFWIF_GPU_UTIL_FWCB;
typedef RGXFWIF_DEV_VIRTADDR PRGXFWIF_REG_CFG;
typedef RGXFWIF_DEV_VIRTADDR PRGXFWIF_HWPERF_CTL;
typedef RGXFWIF_DEV_VIRTADDR PRGX_HWPERF_CONFIG_MUX_CNTBLK;
typedef RGXFWIF_DEV_VIRTADDR PRGX_HWPERF_CONFIG_CNTBLK;
typedef RGXFWIF_DEV_VIRTADDR PRGX_HWPERF_SELECT_CUSTOM_CNTRS;
typedef RGXFWIF_DEV_VIRTADDR PRGXFWIF_CCB_CTL;
typedef RGXFWIF_DEV_VIRTADDR PRGXFWIF_CCB;
@@ -701,7 +713,7 @@ typedef RGXFWIF_DEV_VIRTADDR PRGXFWIF_RF_CMD;
/*!
* This number is used to represent unallocated page catalog base register
*/
#define RGXFW_BIF_INVALID_PCREG 0xFFFFFFFFU
#define RGXFW_BIF_INVALID_PCSET 0xFFFFFFFFU
/*!
Firmware memory context.
@@ -709,7 +721,7 @@ typedef RGXFWIF_DEV_VIRTADDR PRGXFWIF_RF_CMD;
typedef struct
{
IMG_DEV_PHYADDR RGXFW_ALIGN sPCDevPAddr; /*!< device physical address of context's page catalogue */
IMG_UINT32 uiPageCatBaseRegID; /*!< associated page catalog base register (RGXFW_BIF_INVALID_PCREG == unallocated) */
IMG_UINT32 uiPageCatBaseRegSet; /*!< associated page catalog base register (RGXFW_BIF_INVALID_PCSET == unallocated) */
IMG_UINT32 uiBreakpointAddr; /*!< breakpoint address */
IMG_UINT32 uiBPHandlerAddr; /*!< breakpoint handler address */
IMG_UINT32 uiBreakpointCtl; /*!< DM and enable control for BP */
@@ -728,6 +740,7 @@ typedef struct
#define RGXFWIF_CONTEXT_FLAGS_NEED_RESUME (0x00000001U)
#define RGXFWIF_CONTEXT_FLAGS_MC_NEED_RESUME_MASKFULL (0x000000FFU)
#define RGXFWIF_CONTEXT_FLAGS_TDM_HEADER_STALE (0x00000100U)
#define RGXFWIF_CONTEXT_FLAGS_LAST_KICK_SECURE (0x00000200U)
/*!
* @InGroup ContextSwitching
@@ -738,11 +751,14 @@ typedef struct
/* FW-accessible TA state which must be written out to memory on context store */
IMG_UINT64 RGXFW_ALIGN uTAReg_VDM_CALL_STACK_POINTER; /*!< VDM control stream stack pointer, to store in mid-TA */
IMG_UINT64 RGXFW_ALIGN uTAReg_VDM_CALL_STACK_POINTER_Init; /*!< Initial value of VDM control stream stack pointer (in case is 'lost' due to a lock-up) */
IMG_UINT64 RGXFW_ALIGN uTAReg_VBS_SO_PRIM0;
IMG_UINT64 RGXFW_ALIGN uTAReg_VBS_SO_PRIM1;
IMG_UINT64 RGXFW_ALIGN uTAReg_VBS_SO_PRIM2;
IMG_UINT64 RGXFW_ALIGN uTAReg_VBS_SO_PRIM3;
IMG_UINT32 uTAReg_VBS_SO_PRIM[4];
IMG_UINT16 ui16TACurrentIdx;
} UNCACHED_ALIGN RGXFWIF_TACTX_STATE_PER_GEOM;
typedef struct
{
/* FW-accessible TA state which must be written out to memory on context store */
RGXFWIF_TACTX_STATE_PER_GEOM asGeomCore[RGX_NUM_GEOM_CORES];
} UNCACHED_ALIGN RGXFWIF_TACTX_STATE;
/*!
@@ -761,7 +777,7 @@ typedef struct
IMG_UINT32 au3DReg_ISP_STORE[]; /*!< ISP state (per-pipe) */
} UNCACHED_ALIGN RGXFWIF_3DCTX_STATE;
static_assert(sizeof(RGXFWIF_3DCTX_STATE) <= 16,
static_assert(sizeof(RGXFWIF_3DCTX_STATE) <= 16U,
"Size of structure RGXFWIF_3DCTX_STATE exceeds maximum expected size.");
#define RGXFWIF_CTX_USING_BUFFER_A (0)
@@ -788,7 +804,7 @@ typedef struct RGXFWIF_FWCOMMONCONTEXT_
/* Flags e.g. for context switching */
IMG_UINT32 ui32FWComCtxFlags;
IMG_UINT32 ui32Priority; /*!< Priority level */
IMG_INT32 i32Priority; /*!< Priority level */
IMG_UINT32 ui32PrioritySeqNum;
/* Framework state */
@@ -823,7 +839,7 @@ typedef struct RGXFWIF_FWCOMMONCONTEXT_
} UNCACHED_ALIGN RGXFWIF_FWCOMMONCONTEXT;
static_assert(sizeof(RGXFWIF_FWCOMMONCONTEXT) <= 256,
static_assert(sizeof(RGXFWIF_FWCOMMONCONTEXT) <= 256U,
"Size of structure RGXFWIF_FWCOMMONCONTEXT exceeds maximum expected size.");
typedef IMG_UINT64 RGXFWIF_TRP_CHECKSUM_TQ[RGX_TRP_MAX_NUM_CORES][1];
@@ -846,6 +862,10 @@ typedef struct
IMG_UINT32 ui32FwRenderCtxFlags; /*!< Compatibility and other flags */
#if defined(SUPPORT_TRP)
RGXFWIF_TRP_CHECKSUM_3D aui64TRPChecksums3D;
RGXFWIF_TRP_CHECKSUM_GEOM aui64TRPChecksumsGeom;
#endif
} UNCACHED_ALIGN RGXFWIF_FWRENDERCONTEXT;
/*!
@@ -935,7 +955,11 @@ typedef struct
#if !defined(RGX_FEATURE_SLC_VIVT)
#define RGXFWIF_MMUCACHEDATA_FLAGS_PMTLB (0x10U) /* can't use PM_TLB0 bit from BIFPM_CTRL reg because it collides with PT bit from BIF_CTRL reg */
#if !defined(RGX_FEATURE_XE_ARCHITECTURE) || (RGX_FEATURE_XE_ARCHITECTURE < 2)
#define RGXFWIF_MMUCACHEDATA_FLAGS_TLB (RGXFWIF_MMUCACHEDATA_FLAGS_PMTLB | 0x8U) /* BIF_CTRL_INVAL_TLB1_EN */
#else
#define RGXFWIF_MMUCACHEDATA_FLAGS_TLB (RGXFWIF_MMUCACHEDATA_FLAGS_PMTLB)
#endif
#define RGXFWIF_MMUCACHEDATA_FLAGS_CTX_ALL (0x0U) /* not used */
#else /* RGX_FEATURE_SLC_VIVT */
@@ -1106,6 +1130,12 @@ typedef struct
PRGX_HWPERF_CONFIG_MUX_CNTBLK sBlockConfigs; /*!< Address of the RGX_HWPERF_CONFIG_MUX_CNTBLK array */
} RGXFWIF_HWPERF_CONFIG_ENABLE_BLKS;
typedef struct
{
IMG_UINT32 ui32NumBlocks; /*!< Number of RGX_HWPERF_CONFIG_CNTBLK in the array */
PRGX_HWPERF_CONFIG_CNTBLK sBlockConfigs; /*!< Address of the RGX_HWPERF_CONFIG_CNTBLK array */
} RGXFWIF_HWPERF_CONFIG_DA_BLKS;
/*!
* @Brief Command data for \ref RGXFWIF_KCCB_CMD_CORECLKSPEEDCHANGE type command
*/
@@ -1151,6 +1181,13 @@ typedef struct
IMG_UINT32 ui32RegAddr;
IMG_UINT64 RGXFW_ALIGN ui64RegVal;
} RGXFWIF_RGXREG_DATA;
typedef struct
{
IMG_UINT64 ui64BaseAddress;
PRGXFWIF_FWCOMMONCONTEXT psContext;
IMG_UINT32 ui32Size;
} RGXFWIF_GPUMAP_DATA;
#endif
/*!
@@ -1340,6 +1377,10 @@ typedef enum
RGXFWIF_KCCB_CMD_COUNTER_DUMP = 216U | RGX_CMD_MAGIC_DWORD_SHIFTED, /*!< Controls counter dumping in the FW */
RGXFWIF_KCCB_CMD_HWPERF_CONFIG_ENABLE_BLKS = 217U | RGX_CMD_MAGIC_DWORD_SHIFTED, /*!< Configure, clear and enable multiple HWPerf blocks */
RGXFWIF_KCCB_CMD_HWPERF_SELECT_CUSTOM_CNTRS = 218U | RGX_CMD_MAGIC_DWORD_SHIFTED, /*!< Configure the custom counters for HWPerf */
#if defined(SUPPORT_VALIDATION)
RGXFWIF_KCCB_CMD_GPUMAP = 219U | RGX_CMD_MAGIC_DWORD_SHIFTED, /*!< Request a FW GPU mapping which is written into by the FW with a pattern */
#endif
RGXFWIF_KCCB_CMD_HWPERF_CONFIG_BLKS = 220U | RGX_CMD_MAGIC_DWORD_SHIFTED, /*!< Configure directly addressable counters for HWPerf */
} RGXFWIF_KCCB_CMD_TYPE;
#define RGXFWIF_LAST_ALLOWED_GUEST_KCCB_CMD (RGXFWIF_KCCB_CMD_REGCONFIG - 1)
@@ -1366,7 +1407,8 @@ typedef struct
RGXFWIF_HWPERF_CTRL sHWPerfCtrl; /*!< Data for HWPerf control command */
RGXFWIF_HWPERF_CONFIG_ENABLE_BLKS sHWPerfCfgEnableBlks; /*!< Data for HWPerf configure, clear and enable performance counter block command */
RGXFWIF_HWPERF_CTRL_BLKS sHWPerfCtrlBlks; /*!< Data for HWPerf enable or disable performance counter block commands */
RGXFWIF_HWPERF_SELECT_CUSTOM_CNTRS sHWPerfSelectCstmCntrs; /*!< Data for HWPerf configure the custom counters to read */
RGXFWIF_HWPERF_SELECT_CUSTOM_CNTRS sHWPerfSelectCstmCntrs; /*!< Data for HWPerf configure the custom counters to read */
RGXFWIF_HWPERF_CONFIG_DA_BLKS sHWPerfCfgDABlks; /*!< Data for HWPerf configure Directly Addressable blocks */
RGXFWIF_CORECLKSPEEDCHANGE_DATA sCoreClkSpeedChangeData;/*!< Data for core clock speed change */
RGXFWIF_ZSBUFFER_BACKING_DATA sZSBufferBackingData; /*!< Feedback for Z/S Buffer backing/unbacking */
RGXFWIF_FREELIST_GS_DATA sFreeListGSData; /*!< Feedback for Freelist grow/shrink */
@@ -1381,6 +1423,7 @@ typedef struct
RGXFWIF_KCCB_CMD_FORCE_UPDATE_DATA sForceUpdateData; /*!< Data for signalling all unmet fences for a given CCB */
#if defined(SUPPORT_VALIDATION)
RGXFWIF_RGXREG_DATA sFwRgxData; /*!< Data for reading off an RGX register */
RGXFWIF_GPUMAP_DATA sGPUMapData; /*!< Data for requesting a FW GPU mapping which is written into by the FW with a pattern */
#endif
} UNCACHED_ALIGN uCmdData;
} UNCACHED_ALIGN RGXFWIF_KCCB_CMD;
@@ -1664,7 +1707,7 @@ typedef struct
/*! @Brief Command data for \ref RGXFWIF_CCB_CMD_TYPE_PRIORITY type client CCB command */
typedef struct
{
IMG_UINT32 ui32Priority; /*!< Priority level */
IMG_INT32 i32Priority; /*!< Priority level */
} RGXFWIF_CMD_PRIORITY;
/*! @} End of ClientCCBTypes */
@@ -1721,7 +1764,7 @@ typedef struct
do { \
(name).ui32LayoutVersion = RGXFWIF_COMPCHECKS_LAYOUT_VERSION; \
(name).ui64BVNC = 0; \
} while (0)
} while (false)
typedef struct
{
@@ -1831,8 +1874,6 @@ typedef enum
FW_PERF_CONF_NONE = 0,
FW_PERF_CONF_ICACHE = 1,
FW_PERF_CONF_DCACHE = 2,
FW_PERF_CONF_POLLS = 3,
FW_PERF_CONF_CUSTOM_TIMER = 4,
FW_PERF_CONF_JTLB_INSTR = 5,
FW_PERF_CONF_INSTRUCTIONS = 6
} FW_PERF_CONF;
@@ -1915,6 +1956,9 @@ typedef struct
IMG_DEV_VIRTADDR RGXFW_ALIGN sPDSExecBase; /*!< PDS execution base */
IMG_DEV_VIRTADDR RGXFW_ALIGN sUSCExecBase; /*!< USC execution base */
IMG_DEV_VIRTADDR RGXFW_ALIGN sFBCDCStateTableBase; /*!< FBCDC bindless texture state table base */
IMG_DEV_VIRTADDR RGXFW_ALIGN sFBCDCLargeStateTableBase;
IMG_DEV_VIRTADDR RGXFW_ALIGN sTextureHeapBase; /*!< Texture state base */
IMG_UINT64 RGXFW_ALIGN ui64HWPerfFilter; /*! Event filter for Firmware events */
@@ -2002,10 +2046,11 @@ typedef struct
/* Value to write into RGX_CR_TFBC_COMPRESSION_CONTROL */
IMG_UINT32 ui32TFBCCompressionControl;
} UNCACHED_ALIGN RGXFWIF_SYSINIT;
#if defined(SUPPORT_AUTOVZ)
IMG_UINT32 ui32VzWdgPeriod;
#endif
static_assert(sizeof(RGXFWIF_SYSINIT) <= 792,
"Size of structure RGXFW_SYSINIT exceeds maximum expected size.");
} UNCACHED_ALIGN RGXFWIF_SYSINIT;
#if defined(SUPPORT_GPUVIRT_VALIDATION)
#define RGXFWIF_KICK_TEST_ENABLED_BIT 0x1
@@ -2134,67 +2179,33 @@ typedef struct
IMG_UINT32 ui32RTACtlFlags; /* Compatibility and other flags */
} UNCACHED_ALIGN RGXFWIF_RTA_CTL;
/*! @Brief Firmware Freelist holding usage state of the Parameter Buffers */
/*!
* @InGroup RenderTarget
* @Brief Firmware Freelist holding usage state of the Parameter Buffers
*/
typedef struct
{
IMG_DEV_VIRTADDR RGXFW_ALIGN psFreeListDevVAddr;
IMG_UINT64 RGXFW_ALIGN ui64CurrentDevVAddr;
IMG_UINT32 ui32CurrentStackTop;
IMG_UINT32 ui32MaxPages;
IMG_UINT32 ui32GrowPages;
IMG_UINT32 ui32CurrentPages; /* HW pages */
IMG_UINT32 ui32AllocatedPageCount;
IMG_UINT32 ui32AllocatedMMUPageCount;
IMG_DEV_VIRTADDR RGXFW_ALIGN psFreeListDevVAddr; /*!< Freelist page table base */
IMG_UINT64 RGXFW_ALIGN ui64CurrentDevVAddr;/*!< Freelist page table entry for current free page */
IMG_UINT32 ui32CurrentStackTop; /*!< Freelist current free page */
IMG_UINT32 ui32MaxPages; /*!< Max no. of pages can be added to the freelist */
IMG_UINT32 ui32GrowPages; /*!< No pages to add in each freelist grow */
IMG_UINT32 ui32CurrentPages; /*!< Total no. of pages made available to the PM HW */
IMG_UINT32 ui32AllocatedPageCount; /*!< No. of pages allocated by PM HW */
IMG_UINT32 ui32AllocatedMMUPageCount; /*!< No. of pages allocated for GPU MMU for PM*/
#if defined(SUPPORT_SHADOW_FREELISTS)
IMG_UINT32 ui32HWRCounter;
IMG_UINT32 ui32HWRCounter;
PRGXFWIF_FWMEMCONTEXT psFWMemContext;
#endif
IMG_UINT32 ui32FreeListID;
IMG_BOOL bGrowPending;
IMG_UINT32 ui32ReadyPages; /* Pages that should be used only when OOM is reached */
IMG_UINT32 ui32FreelistFlags; /* Compatibility and other flags */
IMG_UINT32 ui32FreeListID; /*!< Unique Freelist ID */
IMG_BOOL bGrowPending; /*!< Freelist grow is pending */
IMG_UINT32 ui32ReadyPages; /*!< Reserved pages to be used only on PM OOM event */
IMG_UINT32 ui32FreelistFlags; /*!< Compatibility and other flags */
#if defined(SUPPORT_AGP)
IMG_UINT32 ui32PmGlobalPb; /*!< PM Global PB on which Freelist is loaded */
#endif
} UNCACHED_ALIGN RGXFWIF_FREELIST;
/*!
******************************************************************************
* Parameter Management (PM) control data for RGX
*****************************************************************************/
/* Used only by Firmware but defined here for similarity with Volcanic where it's required for SW TRP */
typedef enum
{
RGXFW_SPM_STATE_NONE = 0,
RGXFW_SPM_STATE_PR_BLOCKED,
RGXFW_SPM_STATE_WAIT_FOR_GROW,
RGXFW_SPM_STATE_WAIT_FOR_HW,
RGXFW_SPM_STATE_PR_RUNNING,
RGXFW_SPM_STATE_PR_AVOIDED,
RGXFW_SPM_STATE_PR_EXECUTED,
} RGXFW_SPM_STATE;
/*!
******************************************************************************
* @Brief RGX firmware SPM Control Data:
* This structure holds all the internal SPM control Data of the firmware.
*****************************************************************************/
typedef struct
{
RGXFW_SPM_STATE eSPMState; /*!< Current state of TA OOM event */
RGXFWIF_UFO sPartialRenderTA3DFence; /*!< TA/3D fence object holding the value to let through the 3D partial command */
#if defined(RGX_FIRMWARE)
RGXFWIF_FWCOMMONCONTEXT *ps3dContext; /*!< Pointer to the 3D Context holding the partial render */
RGXFWIF_PRBUFFER *apsPRBuffer[RGXFWIF_PRBUFFER_MAXSUPPORTED]; /*!< Array of pointers to PR Buffers which may be used if partial render is needed */
#else
RGXFWIF_DEV_VIRTADDR ps3dContext; /*!< Pointer to the 3D Context holding the partial render */
RGXFWIF_DEV_VIRTADDR apsPRBuffer[RGXFWIF_PRBUFFER_MAXSUPPORTED]; /*!< Array of pointers to PR Buffers which may be used if partial render is needed */
#endif
IMG_UINT32 ui32CmdOffset; /*!< CCCB offset of the command holding the partial render */
bool b3DMemFreeDetected; /*!< Indicates if a 3D Memory Free has been detected, which resolves OOM */
} RGXFW_ALIGN_DCACHEL RGXFW_SPMCTL;
static_assert(sizeof(RGXFW_SPMCTL) <= 64,
"Size of structure RGXFW_SPMCTL exceeds maximum expected size.");
/*!
******************************************************************************
* HWRTData
@@ -2202,12 +2213,19 @@ static_assert(sizeof(RGXFW_SPMCTL) <= 64,
/* HWRTData flags */
/* Deprecated flags 1:0 */
#define HWRTDATA_HAS_LAST_TA (1U << 2)
#define HWRTDATA_PARTIAL_RENDERED (1U << 3)
#define HWRTDATA_DISABLE_TILE_REORDERING (1U << 4)
#define HWRTDATA_NEED_BRN65101_BLIT (1U << 5)
#define HWRTDATA_FIRST_BRN65101_STRIP (1U << 6)
#define HWRTDATA_NEED_BRN67182_2ND_RENDER (1U << 7)
#define HWRTDATA_HAS_LAST_TA (1UL << 2)
#define HWRTDATA_PARTIAL_RENDERED (1UL << 3)
#define HWRTDATA_DISABLE_TILE_REORDERING (1UL << 4)
#define HWRTDATA_NEED_BRN65101_BLIT (1UL << 5)
#define HWRTDATA_FIRST_BRN65101_STRIP (1UL << 6)
#define HWRTDATA_NEED_BRN67182_2ND_RENDER (1UL << 7)
#if defined(SUPPORT_AGP)
#define HWRTDATA_GLOBAL_PB_NUMBER_BIT0 (1UL << 8)
#if defined(SUPPORT_AGP4)
#define HWRTDATA_GLOBAL_PB_NUMBER_BIT1 (1UL << 9)
#endif
#define HWRTDATA_GEOM_NEEDS_RESUME (1UL << 10)
#endif
typedef enum
{
@@ -2251,51 +2269,55 @@ typedef struct
IMG_UINT32 ui32ISPMtileSize;
} UNCACHED_ALIGN RGXFWIF_HWRTDATA_COMMON;
/*! @Brief Firmware Render Target data i.e. HWRTDATA used to hold the PM context */
/*!
* @InGroup RenderTarget
* @Brief Firmware Render Target data i.e. HWRTDATA used to hold the PM context
*/
typedef struct
{
IMG_DEV_VIRTADDR RGXFW_ALIGN psPMMListDevVAddr; /*!< MList Data Store */
IMG_DEV_VIRTADDR RGXFW_ALIGN psPMMListDevVAddr; /*!< MList Data Store */
IMG_UINT64 RGXFW_ALIGN ui64VCECatBase[4];
IMG_UINT64 RGXFW_ALIGN ui64VCELastCatBase[4];
IMG_UINT64 RGXFW_ALIGN ui64TECatBase[4];
IMG_UINT64 RGXFW_ALIGN ui64TELastCatBase[4];
IMG_UINT64 RGXFW_ALIGN ui64AlistCatBase;
IMG_UINT64 RGXFW_ALIGN ui64AlistLastCatBase;
IMG_UINT64 RGXFW_ALIGN ui64VCECatBase[4]; /*!< VCE Page Catalogue base */
IMG_UINT64 RGXFW_ALIGN ui64VCELastCatBase[4];
IMG_UINT64 RGXFW_ALIGN ui64TECatBase[4]; /*!< TE Page Catalogue base */
IMG_UINT64 RGXFW_ALIGN ui64TELastCatBase[4];
IMG_UINT64 RGXFW_ALIGN ui64AlistCatBase; /*!< Alist Page Catalogue base */
IMG_UINT64 RGXFW_ALIGN ui64AlistLastCatBase;
IMG_UINT64 RGXFW_ALIGN ui64PMAListStackPointer;
IMG_UINT32 ui32PMMListStackPointer;
IMG_UINT64 RGXFW_ALIGN ui64PMAListStackPointer; /*!< Freelist page table entry for current Mlist page */
IMG_UINT32 ui32PMMListStackPointer; /*!< Current Mlist page */
RGXFWIF_DEV_VIRTADDR sHWRTDataCommonFwAddr;
RGXFWIF_DEV_VIRTADDR sHWRTDataCommonFwAddr; /*!< Render target dimension dependent data */
IMG_UINT32 ui32HWRTDataFlags;
RGXFWIF_RTDATA_STATE eState;
IMG_UINT32 ui32HWRTDataFlags;
RGXFWIF_RTDATA_STATE eState; /*!< Current workload processing state of HWRTDATA */
PRGXFWIF_FREELIST RGXFW_ALIGN apsFreeLists[RGXFW_MAX_FREELISTS];
IMG_UINT32 aui32FreeListHWRSnapshot[RGXFW_MAX_FREELISTS];
PRGXFWIF_FREELIST RGXFW_ALIGN apsFreeLists[RGXFW_MAX_FREELISTS]; /*!< Freelist to use */
IMG_UINT32 aui32FreeListHWRSnapshot[RGXFW_MAX_FREELISTS];
IMG_DEV_VIRTADDR RGXFW_ALIGN psVHeapTableDevVAddr;
IMG_DEV_VIRTADDR RGXFW_ALIGN psVHeapTableDevVAddr; /*!< VHeap table base */
RGXFWIF_CLEANUP_CTL sCleanupState;
RGXFWIF_CLEANUP_CTL sCleanupState; /*!< Render target clean up state */
RGXFWIF_RTA_CTL sRTACtl;
RGXFWIF_RTA_CTL sRTACtl; /*!< Render target array data */
IMG_DEV_VIRTADDR RGXFW_ALIGN sTailPtrsDevVAddr;
IMG_DEV_VIRTADDR RGXFW_ALIGN sMacrotileArrayDevVAddr;
IMG_DEV_VIRTADDR RGXFW_ALIGN sRgnHeaderDevVAddr;
IMG_DEV_VIRTADDR RGXFW_ALIGN sRTCDevVAddr;
IMG_DEV_VIRTADDR RGXFW_ALIGN sTailPtrsDevVAddr; /*!< Tail pointers base */
IMG_DEV_VIRTADDR RGXFW_ALIGN sMacrotileArrayDevVAddr; /*!< Macrotiling array base */
IMG_DEV_VIRTADDR RGXFW_ALIGN sRgnHeaderDevVAddr; /*!< Region headers base */
IMG_DEV_VIRTADDR RGXFW_ALIGN sRTCDevVAddr; /*!< Render target cache base */
#if defined(RGX_FIRMWARE)
struct RGXFWIF_FWCOMMONCONTEXT_* RGXFW_ALIGN psOwnerGeom;
struct RGXFWIF_FWCOMMONCONTEXT_* RGXFW_ALIGN psOwnerGeom;
#else
RGXFWIF_DEV_VIRTADDR RGXFW_ALIGN pui32OwnerGeomNotUsedByHost;
RGXFWIF_DEV_VIRTADDR RGXFW_ALIGN pui32OwnerGeomNotUsedByHost;
#endif
#if defined(SUPPORT_TRP)
IMG_UINT32 ui32KickFlagsCopy;
IMG_UINT32 ui32TRPState;
RGXFWIF_TRP_CHECKSUM_3D aui64TRPChecksums3D;
RGXFWIF_TRP_CHECKSUM_GEOM aui64TRPChecksumsGeom;
IMG_UINT32 ui32TEPageCopy;
IMG_UINT32 ui32VCEPageCopy;
IMG_UINT32 ui32KickFlagsCopy;
IMG_UINT32 ui32TRPState;
IMG_UINT32 ui32TEPageCopy;
IMG_UINT32 ui32VCEPageCopy;
#endif
#if defined(SUPPORT_AGP)
IMG_BOOL bTACachesNeedZeroing;
#endif
} UNCACHED_ALIGN RGXFWIF_HWRTDATA;

44
drivers/gpu/drm/img-rogue/include/rogue/rgx_fwif_shared.h
View File

@@ -51,7 +51,17 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#include "powervr/mem_types.h"
/* Indicates the number of RTDATAs per RTDATASET */
#define RGXMKIF_NUM_RTDATAS 2U
#if defined(SUPPORT_AGP)
#define RGXMKIF_NUM_RTDATAS 4U
#define RGXMKIF_NUM_GEOMDATAS 4U
#define RGXMKIF_NUM_RTDATA_FREELISTS 12U /* RGXMKIF_NUM_RTDATAS * RGXFW_MAX_FREELISTS */
#define RGX_NUM_GEOM_CORES (2U)
#else
#define RGXMKIF_NUM_RTDATAS 2U
#define RGXMKIF_NUM_GEOMDATAS 1U
#define RGXMKIF_NUM_RTDATA_FREELISTS 2U /* RGXMKIF_NUM_RTDATAS * RGXFW_MAX_FREELISTS */
#define RGX_NUM_GEOM_CORES (1U)
#endif
/* Maximum number of UFOs in a CCB command.
* The number is based on having 32 sync prims (as originally), plus 32 sync
@@ -121,13 +131,17 @@ typedef enum
RGXFWIF_PRBUFFER_UNBACKING_PENDING,
}RGXFWIF_PRBUFFER_STATE;
/*!
* @InGroup RenderTarget
* @Brief OnDemand Z/S/MSAA Buffers
*/
typedef struct
{
IMG_UINT32 ui32BufferID; /*!< Buffer ID*/
IMG_BOOL bOnDemand; /*!< Needs On-demand Z/S/MSAA Buffer allocation */
RGXFWIF_PRBUFFER_STATE eState; /*!< Z/S/MSAA -Buffer state */
RGXFWIF_CLEANUP_CTL sCleanupState; /*!< Cleanup state */
IMG_UINT32 ui32PRBufferFlags; /*!< Compatibility and other flags */
IMG_UINT32 ui32BufferID; /*!< Buffer ID*/
IMG_BOOL bOnDemand; /*!< Needs On-demand Z/S/MSAA Buffer allocation */
RGXFWIF_PRBUFFER_STATE eState; /*!< Z/S/MSAA -Buffer state */
RGXFWIF_CLEANUP_CTL sCleanupState; /*!< Cleanup state */
IMG_UINT32 ui32PRBufferFlags; /*!< Compatibility and other flags */
} UNCACHED_ALIGN RGXFWIF_PRBUFFER;
/*
@@ -188,7 +202,15 @@ typedef struct
* Points to commands not ready, i.e.
* fence dependencies are not met. */
IMG_UINT32 ui32WrapMask; /*!< Offset wrapping mask, total capacity
* in bytes of the CCB-1 */
in bytes of the CCB-1 */
#if defined(SUPPORT_AGP)
IMG_UINT32 ui32ReadOffset2;
#if defined(SUPPORT_AGP4)
IMG_UINT32 ui32ReadOffset3;
IMG_UINT32 ui32ReadOffset4;
#endif
#endif
} UNCACHED_ALIGN RGXFWIF_CCCB_CTL;
@@ -196,7 +218,13 @@ typedef IMG_UINT32 RGXFW_FREELIST_TYPE;
#define RGXFW_LOCAL_FREELIST IMG_UINT32_C(0)
#define RGXFW_GLOBAL_FREELIST IMG_UINT32_C(1)
#if defined(SUPPORT_AGP)
#define RGXFW_GLOBAL2_FREELIST IMG_UINT32_C(2)
#define RGXFW_MAX_FREELISTS (RGXFW_GLOBAL2_FREELIST + 1U)
#else
#define RGXFW_MAX_FREELISTS (RGXFW_GLOBAL_FREELIST + 1U)
#endif
#define RGXFW_MAX_HWFREELISTS (2U)
/*!
* @Defgroup ContextSwitching Context switching data interface
@@ -256,7 +284,7 @@ typedef struct
*/
typedef struct
{
RGXFWIF_TAREGISTERS_CSWITCH RGXFW_ALIGN sCtxSwitch_Regs; /*!< Geom registers for ctx switch */
RGXFWIF_TAREGISTERS_CSWITCH RGXFW_ALIGN asCtxSwitch_GeomRegs[RGX_NUM_GEOM_CORES]; /*!< Geom registers for ctx switch */
} RGXFWIF_STATIC_RENDERCONTEXT_STATE;
#define RGXFWIF_STATIC_RENDERCONTEXT_SIZE sizeof(RGXFWIF_STATIC_RENDERCONTEXT_STATE)

1
drivers/gpu/drm/img-rogue/include/rogue/rgx_heaps.h
View File

@@ -54,6 +54,7 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define RGX_VK_CAPT_REPLAY_HEAP_IDENT "Vulkan Capture Replay" /*!< RGX Vulkan capture replay buffer Heap Identifier */
#define RGX_SIGNALS_HEAP_IDENT "Signals" /*!< Signals Heap Identifier */
#define RGX_FBCDC_HEAP_IDENT "FBCDC" /*!< RGX FBCDC State Table Heap Identifier */
#define RGX_FBCDC_LARGE_HEAP_IDENT "Large FBCDC" /*!< RGX Large FBCDC State Table Heap Identifier */
#define RGX_CMP_MISSION_RMW_HEAP_IDENT "Compute Mission RMW" /*!< Compute Mission RMW Heap Identifier */
#define RGX_CMP_SAFETY_RMW_HEAP_IDENT "Compute Safety RMW" /*!< Compute Safety RMW Heap Identifier */
#define RGX_TEXTURE_STATE_HEAP_IDENT "Texture State" /*!< Texture State Heap Identifier */

524
drivers/gpu/drm/img-rogue/include/rogue/rgx_hwperf.h
View File

@@ -60,6 +60,7 @@ extern "C" {
#include "img_defs.h"
#include "rgx_common.h"
#include "rgx_hwperf_common.h"
#include "pvrsrv_tlcommon.h"
#include "pvrsrv_sync_km.h"
@@ -141,404 +142,8 @@ static_assert(RGX_FEATURE_NUM_CLUSTERS <= 16U, "Cluster count too large for HWPe
/*! The number of counters supported in each non-mux counter block */
#define RGX_HWPERF_MAX_CUSTOM_CNTRS 8U
/*! The number of non-mux counter blocks supported */
#if defined(SUPPORT_VALIDATION)
#define RGX_CNTBLK_COUNTERS_MAX 64U
#else
#define RGX_CNTBLK_COUNTERS_MAX 12U
#endif
/******************************************************************************
* Packet Event Type Enumerations
*****************************************************************************/
/*! Type used to encode the event that generated the packet.
* NOTE: When this type is updated the corresponding hwperfbin2json tool
* source needs to be updated as well. The RGX_HWPERF_EVENT_MASK_* macros will
* also need updating when adding new types.
*
* @par
* The event type values are incrementing integers for use as a shift ordinal
* in the event filtering process at the point events are generated.
* This scheme thus implies a limit of 63 event types.
*/
typedef IMG_UINT32 RGX_HWPERF_EVENT_TYPE;
#define RGX_HWPERF_INVALID 0x00U /*!< Invalid. Reserved value. */
/*! FW types 0x01..0x06 */
#define RGX_HWPERF_FW_EVENT_RANGE_FIRST_TYPE 0x01U
#define RGX_HWPERF_FW_BGSTART 0x01U /*!< Background task processing start */
#define RGX_HWPERF_FW_BGEND 0x02U /*!< Background task end */
#define RGX_HWPERF_FW_IRQSTART 0x03U /*!< IRQ task processing start */
#define RGX_HWPERF_FW_IRQEND 0x04U /*!< IRQ task end */
#define RGX_HWPERF_FW_DBGSTART 0x05U /*!< Debug event start */
#define RGX_HWPERF_FW_DBGEND 0x06U /*!< Debug event end */
#define RGX_HWPERF_FW_EVENT_RANGE_LAST_TYPE 0x06U
/*! HW types 0x07..0x19 */
#define RGX_HWPERF_HW_EVENT_RANGE0_FIRST_TYPE 0x07U
#define RGX_HWPERF_HW_PMOOM_TAPAUSE 0x07U /*!< TA Pause at PM Out of Memory */
#define RGX_HWPERF_HW_TAKICK 0x08U /*!< TA task started */
#define RGX_HWPERF_HW_TAFINISHED 0x09U /*!< TA task finished */
#define RGX_HWPERF_HW_3DTQKICK 0x0AU /*!< 3D TQ started */
#define RGX_HWPERF_HW_3DKICK 0x0BU /*!< 3D task started */
#define RGX_HWPERF_HW_3DFINISHED 0x0CU /*!< 3D task finished */
#define RGX_HWPERF_HW_CDMKICK 0x0DU /*!< CDM task started */
#define RGX_HWPERF_HW_CDMFINISHED 0x0EU /*!< CDM task finished */
#define RGX_HWPERF_HW_TLAKICK 0x0FU /*!< TLA task started */
#define RGX_HWPERF_HW_TLAFINISHED 0x10U /*!< TLS task finished */
#define RGX_HWPERF_HW_3DSPMKICK 0x11U /*!< 3D SPM task started */
#define RGX_HWPERF_HW_PERIODIC 0x12U /*!< Periodic event with updated HW counters */
#define RGX_HWPERF_HW_RTUKICK 0x13U /*!< Reserved, future use */
#define RGX_HWPERF_HW_RTUFINISHED 0x14U /*!< Reserved, future use */
#define RGX_HWPERF_HW_SHGKICK 0x15U /*!< Reserved, future use */
#define RGX_HWPERF_HW_SHGFINISHED 0x16U /*!< Reserved, future use */
#define RGX_HWPERF_HW_3DTQFINISHED 0x17U /*!< 3D TQ finished */
#define RGX_HWPERF_HW_3DSPMFINISHED 0x18U /*!< 3D SPM task finished */
#define RGX_HWPERF_HW_PMOOM_TARESUME 0x19U /*!< TA Resume after PM Out of Memory */
/*! HW_EVENT_RANGE0 used up. Use next empty range below to add new hardware events */
#define RGX_HWPERF_HW_EVENT_RANGE0_LAST_TYPE 0x19U
/*! other types 0x1A..0x1F */
#define RGX_HWPERF_CLKS_CHG 0x1AU /*!< Clock speed change in GPU */
#define RGX_HWPERF_GPU_STATE_CHG 0x1BU /*!< GPU work state change */
/*! power types 0x20..0x27 */
#define RGX_HWPERF_PWR_EST_RANGE_FIRST_TYPE 0x20U
#define RGX_HWPERF_PWR_EST_REQUEST 0x20U /*!< Power estimate requested (via GPIO) */
#define RGX_HWPERF_PWR_EST_READY 0x21U /*!< Power estimate inputs ready */
#define RGX_HWPERF_PWR_EST_RESULT 0x22U /*!< Power estimate result calculated */
#define RGX_HWPERF_PWR_EST_RANGE_LAST_TYPE 0x22U
#define RGX_HWPERF_PWR_CHG 0x23U /*!< Power state change */
/*! HW_EVENT_RANGE1 0x28..0x2F, for accommodating new hardware events */
#define RGX_HWPERF_HW_EVENT_RANGE1_FIRST_TYPE 0x28U
#define RGX_HWPERF_HW_TDMKICK 0x28U /*!< TDM task started */
#define RGX_HWPERF_HW_TDMFINISHED 0x29U /*!< TDM task finished */
#define RGX_HWPERF_HW_NULLKICK 0x2AU /*!< NULL event */
#define RGX_HWPERF_HW_EVENT_RANGE1_LAST_TYPE 0x2AU
/*! context switch types 0x30..0x31 */
#define RGX_HWPERF_CSW_START 0x30U /*!< HW context store started */
#define RGX_HWPERF_CSW_FINISHED 0x31U /*!< HW context store finished */
/*! DVFS events */
#define RGX_HWPERF_DVFS 0x32U /*!< Dynamic voltage/frequency scaling events */
/*! firmware misc 0x38..0x39 */
#define RGX_HWPERF_UFO 0x38U /*!< FW UFO Check / Update */
#define RGX_HWPERF_FWACT 0x39U /*!< FW Activity notification */
/*! last */
#define RGX_HWPERF_LAST_TYPE 0x3BU
/*! This enumeration must have a value that is a power of two as it is
* used in masks and a filter bit field (currently 64 bits long).
*/
#define RGX_HWPERF_MAX_TYPE 0x40U
static_assert(RGX_HWPERF_LAST_TYPE < RGX_HWPERF_MAX_TYPE, "Too many HWPerf event types");
/*! Macro used to check if an event type ID is present in the known set of hardware type events */
#define HWPERF_PACKET_IS_HW_TYPE(_etype) (((_etype) >= RGX_HWPERF_HW_EVENT_RANGE0_FIRST_TYPE && (_etype) <= RGX_HWPERF_HW_EVENT_RANGE0_LAST_TYPE) || \
((_etype) >= RGX_HWPERF_HW_EVENT_RANGE1_FIRST_TYPE && (_etype) <= RGX_HWPERF_HW_EVENT_RANGE1_LAST_TYPE))
/*! Macro used to check if an event type ID is present in the known set of firmware type events */
#define HWPERF_PACKET_IS_FW_TYPE(_etype) \
((_etype) >= RGX_HWPERF_FW_EVENT_RANGE_FIRST_TYPE && \
(_etype) <= RGX_HWPERF_FW_EVENT_RANGE_LAST_TYPE)
typedef enum {
RGX_HWPERF_HOST_INVALID = 0x00, /*!< Invalid, do not use. */
RGX_HWPERF_HOST_ENQ = 0x01, /*!< ``0x01`` Kernel driver has queued GPU work.
See RGX_HWPERF_HOST_ENQ_DATA */
RGX_HWPERF_HOST_UFO = 0x02, /*!< ``0x02`` UFO updated by the driver.
See RGX_HWPERF_HOST_UFO_DATA */
RGX_HWPERF_HOST_ALLOC = 0x03, /*!< ``0x03`` Resource allocated.
See RGX_HWPERF_HOST_ALLOC_DATA */
RGX_HWPERF_HOST_CLK_SYNC = 0x04, /*!< ``0x04`` GPU / Host clocks correlation data.
See RGX_HWPERF_HOST_CLK_SYNC_DATA */
RGX_HWPERF_HOST_FREE = 0x05, /*!< ``0x05`` Resource freed,
See RGX_HWPERF_HOST_FREE_DATA */
RGX_HWPERF_HOST_MODIFY = 0x06, /*!< ``0x06`` Resource modified / updated.
See RGX_HWPERF_HOST_MODIFY_DATA */
RGX_HWPERF_HOST_DEV_INFO = 0x07, /*!< ``0x07`` Device Health status.
See RGX_HWPERF_HOST_DEV_INFO_DATA */
RGX_HWPERF_HOST_INFO = 0x08, /*!< ``0x08`` Device memory usage information.
See RGX_HWPERF_HOST_INFO_DATA */
RGX_HWPERF_HOST_SYNC_FENCE_WAIT = 0x09, /*!< ``0x09`` Wait for sync event.
See RGX_HWPERF_HOST_SYNC_FENCE_WAIT_DATA */
RGX_HWPERF_HOST_SYNC_SW_TL_ADVANCE = 0x0A, /*!< ``0x0A`` Software timeline advanced.
See RGX_HWPERF_HOST_SYNC_SW_TL_ADV_DATA */
/*! last */
RGX_HWPERF_HOST_LAST_TYPE,
/*! This enumeration must have a value that is a power of two as it is
* used in masks and a filter bit field (currently 32 bits long).
*/
RGX_HWPERF_HOST_MAX_TYPE = 0x20
} RGX_HWPERF_HOST_EVENT_TYPE;
/*!< The event type values are incrementing integers for use as a shift ordinal
* in the event filtering process at the point events are generated.
* This scheme thus implies a limit of 31 event types.
*/
static_assert(RGX_HWPERF_HOST_LAST_TYPE < RGX_HWPERF_HOST_MAX_TYPE, "Too many HWPerf host event types");
/******************************************************************************
* Packet Header Format Version 2 Types
*****************************************************************************/
/*! Major version number of the protocol in operation
*/
#define RGX_HWPERF_V2_FORMAT 2
/*! Signature ASCII pattern 'HWP2' found in the first word of a HWPerfV2 packet
*/
#define HWPERF_PACKET_V2_SIG 0x48575032
/*! Signature ASCII pattern 'HWPA' found in the first word of a HWPerfV2a packet
*/
#define HWPERF_PACKET_V2A_SIG 0x48575041
/*! Signature ASCII pattern 'HWPB' found in the first word of a HWPerfV2b packet
*/
#define HWPERF_PACKET_V2B_SIG 0x48575042
#define HWPERF_PACKET_ISVALID(_ptr) (((_ptr) == HWPERF_PACKET_V2_SIG) || ((_ptr) == HWPERF_PACKET_V2A_SIG)|| ((_ptr) == HWPERF_PACKET_V2B_SIG))
/*!< Checks that the packet signature is one of the supported versions */
/*! Type defines the HWPerf packet header common to all events. */
typedef struct
{
IMG_UINT32 ui32Sig; /*!< Always the value HWPERF_PACKET_SIG */
IMG_UINT32 ui32Size; /*!< Overall packet size in bytes */
IMG_UINT32 eTypeId; /*!< Event type information field */
IMG_UINT32 ui32Ordinal; /*!< Sequential number of the packet */
IMG_UINT64 ui64Timestamp; /*!< Event timestamp */
} RGX_HWPERF_V2_PACKET_HDR, *RGX_PHWPERF_V2_PACKET_HDR;
#ifndef __CHECKER__
RGX_FW_STRUCT_OFFSET_ASSERT(RGX_HWPERF_V2_PACKET_HDR, ui64Timestamp);
RGX_FW_STRUCT_SIZE_ASSERT(RGX_HWPERF_V2_PACKET_HDR);
#endif
/*! Mask for use with the IMG_UINT32 ui32Size header field */
#define RGX_HWPERF_SIZE_MASK 0xFFFFU
/*! This macro defines an upper limit to which the size of the largest variable
* length HWPerf packet must fall within, currently 3KB. This constant may be
* used to allocate a buffer to hold one packet.
* This upper limit is policed by packet producing code.
*/
#define RGX_HWPERF_MAX_PACKET_SIZE 0xC00U
/*! Defines an upper limit to the size of a variable length packet payload.
*/
#define RGX_HWPERF_MAX_PAYLOAD_SIZE ((IMG_UINT32)(RGX_HWPERF_MAX_PACKET_SIZE-\
sizeof(RGX_HWPERF_V2_PACKET_HDR)))
/*! Macro which takes a structure name and provides the packet size for
* a fixed size payload packet, rounded up to 8 bytes to align packets
* for 64 bit architectures. */
#define RGX_HWPERF_MAKE_SIZE_FIXED(_struct) ((IMG_UINT32)(RGX_HWPERF_SIZE_MASK&(sizeof(RGX_HWPERF_V2_PACKET_HDR)+PVR_ALIGN(sizeof(_struct), PVRSRVTL_PACKET_ALIGNMENT))))
/*! Macro which takes the number of bytes written in the data payload of a
* packet for a variable size payload packet, rounded up to 8 bytes to
* align packets for 64 bit architectures. */
#define RGX_HWPERF_MAKE_SIZE_VARIABLE(_size) ((IMG_UINT32)(RGX_HWPERF_SIZE_MASK&(sizeof(RGX_HWPERF_V2_PACKET_HDR)+PVR_ALIGN((_size), PVRSRVTL_PACKET_ALIGNMENT))))
/*! Macro to obtain the size of the packet */
#define RGX_HWPERF_GET_SIZE(_packet_addr) ((IMG_UINT16)(((_packet_addr)->ui32Size) & RGX_HWPERF_SIZE_MASK))
/*! Macro to obtain the size of the packet data */
#define RGX_HWPERF_GET_DATA_SIZE(_packet_addr) (RGX_HWPERF_GET_SIZE(_packet_addr) - sizeof(RGX_HWPERF_V2_PACKET_HDR))
/*! Masks for use with the IMG_UINT32 eTypeId header field */
#define RGX_HWPERF_TYPEID_MASK 0x0007FFFFU
#define RGX_HWPERF_TYPEID_EVENT_MASK 0x00007FFFU
#define RGX_HWPERF_TYPEID_THREAD_MASK 0x00008000U
#define RGX_HWPERF_TYPEID_STREAM_MASK 0x00070000U
#define RGX_HWPERF_TYPEID_META_DMA_MASK 0x00080000U
#define RGX_HWPERF_TYPEID_M_CORE_MASK 0x00100000U
#define RGX_HWPERF_TYPEID_OSID_MASK 0x07000000U
/*! Meta thread macros for encoding the ID into the type field of a packet */
#define RGX_HWPERF_META_THREAD_SHIFT 15U
#define RGX_HWPERF_META_THREAD_ID0 0x0U /*!< Meta Thread 0 ID */
#define RGX_HWPERF_META_THREAD_ID1 0x1U /*!< Meta Thread 1 ID */
/*! Obsolete, kept for source compatibility */
#define RGX_HWPERF_META_THREAD_MASK 0x1U
/*! Stream ID macros for encoding the ID into the type field of a packet */
#define RGX_HWPERF_STREAM_SHIFT 16U
/*! Meta DMA macro for encoding how the packet was generated into the type field of a packet */
#define RGX_HWPERF_META_DMA_SHIFT 19U
/*! Bit-shift macro used for encoding multi-core data into the type field of a packet */
#define RGX_HWPERF_M_CORE_SHIFT 20U
/*! OSID bit-shift macro used for encoding OSID into type field of a packet */
#define RGX_HWPERF_OSID_SHIFT 24U
typedef enum {
RGX_HWPERF_STREAM_ID0_FW, /*!< Events from the Firmware/GPU */
RGX_HWPERF_STREAM_ID1_HOST, /*!< Events from the Server host driver component */
RGX_HWPERF_STREAM_ID2_CLIENT, /*!< Events from the Client host driver component */
RGX_HWPERF_STREAM_ID_LAST,
} RGX_HWPERF_STREAM_ID;
/* Checks if all stream IDs can fit under RGX_HWPERF_TYPEID_STREAM_MASK. */
static_assert(((IMG_UINT32)RGX_HWPERF_STREAM_ID_LAST - 1U) < (RGX_HWPERF_TYPEID_STREAM_MASK >> RGX_HWPERF_STREAM_SHIFT),
"Too many HWPerf stream IDs.");
/*! Compile-time value used to seed the Multi-Core (MC) bit in the typeID field.
* Only set by RGX_FIRMWARE builds.
*/
#if defined(RGX_FIRMWARE)
# if defined(RGX_FEATURE_GPU_MULTICORE_SUPPORT)
#define RGX_HWPERF_M_CORE_VALUE 1U /*!< 1 => Multi-core supported */
# else
#define RGX_HWPERF_M_CORE_VALUE 0U /*!< 0 => Multi-core not supported */
# endif
#else
#define RGX_HWPERF_M_CORE_VALUE 0U /*!< 0 => Multi-core not supported */
#endif
/*! Macros used to set the packet type and encode meta thread ID (0|1),
* HWPerf stream ID, multi-core capability and OSID within the typeID */
#define RGX_HWPERF_MAKE_TYPEID(_stream, _type, _thread, _metadma, _osid)\
((IMG_UINT32) ((RGX_HWPERF_TYPEID_STREAM_MASK&((IMG_UINT32)(_stream) << RGX_HWPERF_STREAM_SHIFT)) | \
(RGX_HWPERF_TYPEID_THREAD_MASK & ((IMG_UINT32)(_thread) << RGX_HWPERF_META_THREAD_SHIFT)) | \
(RGX_HWPERF_TYPEID_EVENT_MASK & (IMG_UINT32)(_type)) | \
(RGX_HWPERF_TYPEID_META_DMA_MASK & ((IMG_UINT32)(_metadma) << RGX_HWPERF_META_DMA_SHIFT)) | \
(RGX_HWPERF_TYPEID_OSID_MASK & ((IMG_UINT32)(_osid) << RGX_HWPERF_OSID_SHIFT)) | \
(RGX_HWPERF_TYPEID_M_CORE_MASK & ((IMG_UINT32)(RGX_HWPERF_M_CORE_VALUE) << RGX_HWPERF_M_CORE_SHIFT))))
/*! Obtains the event type that generated the packet */
#define RGX_HWPERF_GET_TYPE(_packet_addr) (((_packet_addr)->eTypeId) & RGX_HWPERF_TYPEID_EVENT_MASK)
/*! Obtains the META Thread number that generated the packet */
#define RGX_HWPERF_GET_THREAD_ID(_packet_addr) (((((_packet_addr)->eTypeId) & RGX_HWPERF_TYPEID_THREAD_MASK) >> RGX_HWPERF_META_THREAD_SHIFT))
/*! Determines if the packet generated contains multi-core data */
#define RGX_HWPERF_GET_M_CORE(_packet_addr) (((_packet_addr)->eTypeId & RGX_HWPERF_TYPEID_M_CORE_MASK) >> RGX_HWPERF_M_CORE_SHIFT)
/*! Obtains the guest OSID which resulted in packet generation */
#define RGX_HWPERF_GET_OSID(_packet_addr) (((_packet_addr)->eTypeId & RGX_HWPERF_TYPEID_OSID_MASK) >> RGX_HWPERF_OSID_SHIFT)
/*! Obtain stream id */
#define RGX_HWPERF_GET_STREAM_ID(_packet_addr) (((((_packet_addr)->eTypeId) & RGX_HWPERF_TYPEID_STREAM_MASK) >> RGX_HWPERF_STREAM_SHIFT))
/*! Obtain information about how the packet was generated, which might affect payload total size */
#define RGX_HWPERF_GET_META_DMA_INFO(_packet_addr) (((((_packet_addr)->eTypeId) & RGX_HWPERF_TYPEID_META_DMA_MASK) >> RGX_HWPERF_META_DMA_SHIFT))
/*! Obtains a typed pointer to a packet given a buffer address */
#define RGX_HWPERF_GET_PACKET(_buffer_addr) ((RGX_HWPERF_V2_PACKET_HDR *)(void *) (_buffer_addr))
/*! Obtains a typed pointer to a data structure given a packet address */
#define RGX_HWPERF_GET_PACKET_DATA_BYTES(_packet_addr) (IMG_OFFSET_ADDR((_packet_addr), sizeof(RGX_HWPERF_V2_PACKET_HDR)))
/*! Obtains a typed pointer to the next packet given a packet address */
#define RGX_HWPERF_GET_NEXT_PACKET(_packet_addr) ((RGX_HWPERF_V2_PACKET_HDR *) (IMG_OFFSET_ADDR((_packet_addr), RGX_HWPERF_SIZE_MASK&((_packet_addr)->ui32Size))))
/*! Obtains a typed pointer to a packet header given the packet data address */
#define RGX_HWPERF_GET_PACKET_HEADER(_packet_addr) ((RGX_HWPERF_V2_PACKET_HDR *) (IMG_OFFSET_ADDR((_packet_addr), -(IMG_INT32)sizeof(RGX_HWPERF_V2_PACKET_HDR))))
/******************************************************************************
* Other Common Defines
*****************************************************************************/
/*! This macro is not a real array size, but indicates the array has a variable
* length only known at run-time but always contains at least 1 element. The
* final size of the array is deduced from the size field of a packet header.
*/
#define RGX_HWPERF_ONE_OR_MORE_ELEMENTS 1U
/*! This macro is not a real array size, but indicates the array is optional
* and if present has a variable length only known at run-time. The final
* size of the array is deduced from the size field of a packet header. */
#define RGX_HWPERF_ZERO_OR_MORE_ELEMENTS 1U
/*! Masks for use with the IMG_UINT32 ui32BlkInfo field */
#define RGX_HWPERF_BLKINFO_BLKCOUNT_MASK 0xFFFF0000U
#define RGX_HWPERF_BLKINFO_BLKOFFSET_MASK 0x0000FFFFU
/*! Shift for the NumBlocks and counter block offset field in ui32BlkInfo */
#define RGX_HWPERF_BLKINFO_BLKCOUNT_SHIFT 16U
#define RGX_HWPERF_BLKINFO_BLKOFFSET_SHIFT 0U
/*! Macro used to set the block info word as a combination of two 16-bit integers */
#define RGX_HWPERF_MAKE_BLKINFO(_numblks, _blkoffset) ((IMG_UINT32) ((RGX_HWPERF_BLKINFO_BLKCOUNT_MASK&((_numblks) << RGX_HWPERF_BLKINFO_BLKCOUNT_SHIFT)) | (RGX_HWPERF_BLKINFO_BLKOFFSET_MASK&((_blkoffset) << RGX_HWPERF_BLKINFO_BLKOFFSET_SHIFT))))
/*! Macro used to obtain the number of counter blocks present in the packet */
#define RGX_HWPERF_GET_BLKCOUNT(_blkinfo) (((_blkinfo) & RGX_HWPERF_BLKINFO_BLKCOUNT_MASK) >> RGX_HWPERF_BLKINFO_BLKCOUNT_SHIFT)
/*! Obtains the offset of the counter block stream in the packet */
#define RGX_HWPERF_GET_BLKOFFSET(_blkinfo) (((_blkinfo) & RGX_HWPERF_BLKINFO_BLKOFFSET_MASK) >> RGX_HWPERF_BLKINFO_BLKOFFSET_SHIFT)
/*! This macro gets the number of blocks depending on the packet version */
#define RGX_HWPERF_GET_NUMBLKS(_sig, _packet_data, _numblocks) \
do { \
if (HWPERF_PACKET_V2B_SIG == (_sig)) \
{ \
(_numblocks) = RGX_HWPERF_GET_BLKCOUNT((_packet_data)->ui32BlkInfo);\
} \
else \
{ \
IMG_UINT32 ui32VersionOffset = (((_sig) == HWPERF_PACKET_V2_SIG) ? 1 : 3);\
(_numblocks) = *(IMG_UINT16 *)(IMG_OFFSET_ADDR(&(_packet_data)->ui32WorkTarget, ui32VersionOffset)); \
} \
} while (0)
/*! This macro gets the counter stream pointer depending on the packet version */
#define RGX_HWPERF_GET_CNTSTRM(_sig, _hw_packet_data, _cntstream_ptr) \
{ \
if (HWPERF_PACKET_V2B_SIG == (_sig)) \
{ \
(_cntstream_ptr) = (IMG_UINT32 *)(IMG_OFFSET_ADDR((_hw_packet_data), RGX_HWPERF_GET_BLKOFFSET((_hw_packet_data)->ui32BlkInfo))); \
} \
else \
{ \
IMG_UINT32 ui32BlkStreamOffsetInWords = (((_sig) == HWPERF_PACKET_V2_SIG) ? 6 : 8); \
(_cntstream_ptr) = (IMG_UINT32 *)(IMG_OFFSET_ADDR_DW((_hw_packet_data), ui32BlkStreamOffsetInWords)); \
} \
}
/*! Masks for use with the RGX_HWPERF_UFO_EV eEvType field */
#define RGX_HWPERF_UFO_STREAMSIZE_MASK 0xFFFF0000U
#define RGX_HWPERF_UFO_STREAMOFFSET_MASK 0x0000FFFFU
/*! Shift for the UFO count and data stream fields */
#define RGX_HWPERF_UFO_STREAMSIZE_SHIFT 16U
#define RGX_HWPERF_UFO_STREAMOFFSET_SHIFT 0U
/*! Macro used to set UFO stream info word as a combination of two 16-bit integers */
#define RGX_HWPERF_MAKE_UFOPKTINFO(_ssize, _soff) \
((IMG_UINT32) ((RGX_HWPERF_UFO_STREAMSIZE_MASK&((_ssize) << RGX_HWPERF_UFO_STREAMSIZE_SHIFT)) | \
(RGX_HWPERF_UFO_STREAMOFFSET_MASK&((_soff) << RGX_HWPERF_UFO_STREAMOFFSET_SHIFT))))
/*! Macro used to obtain UFO count*/
#define RGX_HWPERF_GET_UFO_STREAMSIZE(_streaminfo) \
(((_streaminfo) & RGX_HWPERF_UFO_STREAMSIZE_MASK) >> RGX_HWPERF_UFO_STREAMSIZE_SHIFT)
/*! Obtains the offset of the UFO stream in the packet */
#define RGX_HWPERF_GET_UFO_STREAMOFFSET(_streaminfo) \
(((_streaminfo) & RGX_HWPERF_UFO_STREAMOFFSET_MASK) >> RGX_HWPERF_UFO_STREAMOFFSET_SHIFT)
/*! The number of directly-addressable counters allowed in non-mux counter blocks */
#define RGX_CNTBLK_COUNTERS_MAX ((IMG_UINT32)PVRSRV_HWPERF_COUNTERS_PERBLK + 0U)
/******************************************************************************
@@ -565,18 +170,20 @@ typedef enum {
RGX_HWPERF_DM_INVALID = 0x1FFFFFFF
} RGX_HWPERF_DM;
/*! Enum containing bit position for 32bit feature flags used in hwperf and api */
typedef enum {
RGX_HWPERF_FEATURE_PERFBUS_FLAG = 0x001,
RGX_HWPERF_FEATURE_S7_TOP_INFRASTRUCTURE_FLAG = 0x002,
RGX_HWPERF_FEATURE_XT_TOP_INFRASTRUCTURE_FLAG = 0x004,
RGX_HWPERF_FEATURE_PERF_COUNTER_BATCH_FLAG = 0x008,
RGX_HWPERF_FEATURE_ROGUEXE_FLAG = 0x010,
RGX_HWPERF_FEATURE_DUST_POWER_ISLAND_S7_FLAG = 0x020,
RGX_HWPERF_FEATURE_PBE2_IN_XE_FLAG = 0x040,
RGX_HWPERF_FEATURE_WORKLOAD_ESTIMATION = 0x080,
RGX_HWPERF_FEATURE_MULTICORE_FLAG = 0x100
} RGX_HWPERF_FEATURE_FLAGS;
/*! Define containing bit position for 32bit feature flags used in hwperf and api */
typedef IMG_UINT32 RGX_HWPERF_FEATURE_FLAGS;
#define RGX_HWPERF_FEATURE_PERFBUS_FLAG 0x0001U
#define RGX_HWPERF_FEATURE_S7_TOP_INFRASTRUCTURE_FLAG 0x0002U
#define RGX_HWPERF_FEATURE_XT_TOP_INFRASTRUCTURE_FLAG 0x0004U
#define RGX_HWPERF_FEATURE_PERF_COUNTER_BATCH_FLAG 0x0008U
#define RGX_HWPERF_FEATURE_ROGUEXE_FLAG 0x0010U
#define RGX_HWPERF_FEATURE_DUST_POWER_ISLAND_S7_FLAG 0x0020U
#define RGX_HWPERF_FEATURE_PBE2_IN_XE_FLAG 0x0040U
#define RGX_HWPERF_FEATURE_WORKLOAD_ESTIMATION 0x0080U
#define RGX_HWPERF_FEATURE_MULTICORE_FLAG 0x0100U
#define RGX_HWPERF_FEATURE_VOLCANIC_FLAG 0x0800U
#define RGX_HWPERF_FEATURE_ROGUE_FLAG 0x1000U
#define RGX_HWPERF_FEATURE_OCEANIC_FLAG 0x2000U
/*! This structure holds the data of a firmware packet. */
typedef struct
@@ -606,11 +213,14 @@ typedef struct
IMG_UINT32 ui32WorkCtx; /*!< Work context: Render Context for TA/3D; RayTracing Context for RTU/SHG; 0x0 otherwise */
IMG_UINT32 ui32CtxPriority; /*!< Context priority */
IMG_UINT32 ui32GPUIdMask; /*!< GPU IDs active within this event */
IMG_UINT32 aui32CountBlksStream[RGX_HWPERF_ZERO_OR_MORE_ELEMENTS]; /*!< Counter data */
IMG_UINT32 ui32Padding2; /*!< Reserved. To ensure correct alignment */
IMG_UINT32 ui32KickInfo; /*!< <31..8> Reserved <7..0> GPU Pipeline DM kick ID, 0 if not using Pipeline DMs */
IMG_UINT32 ui32Padding; /*!< Reserved. To ensure correct alignment */
IMG_UINT32 aui32CountBlksStream[RGX_HWPERF_ZERO_OR_MORE_ELEMENTS]; /*!< Optional variable length Counter data */
IMG_UINT32 ui32Padding2; /*!< Reserved. To ensure correct alignment (not written in the packet) */
} RGX_HWPERF_HW_DATA;
RGX_FW_STRUCT_SIZE_ASSERT(RGX_HWPERF_HW_DATA);
RGX_FW_STRUCT_OFFSET_ASSERT(RGX_HWPERF_HW_DATA, aui32CountBlksStream);
typedef struct
{
@@ -914,6 +524,26 @@ typedef struct
RGX_FW_STRUCT_SIZE_ASSERT(RGX_HWPERF_BVNC);
/*! Performance Counter Configuration data element. */
typedef struct
{
IMG_UINT32 ui32BlockID; /*!< Counter Block ID. See RGX_HWPERF_CNTBLK_ID */
IMG_UINT32 ui32NumCounters; /*!< Number of counters configured */
IMG_UINT32 ui32CounterVals[RGX_CNTBLK_COUNTERS_MAX]; /*!< Counters configured (ui32NumCounters worth of entries) */
} RGX_HWPERF_COUNTER_CFG_DATA_EL;
RGX_FW_STRUCT_SIZE_ASSERT(RGX_HWPERF_COUNTER_CFG_DATA_EL);
/*! Performance Counter Configuration data. */
typedef struct
{
IMG_UINT32 ui32EnabledBlocks; /*!< Number of Enabled Blocks. */
RGX_HWPERF_COUNTER_CFG_DATA_EL uData; /*!< Start of variable length data. See RGX_HWPERF_COUNTER_CFG_DATA_EL */
IMG_UINT32 ui32Padding; /*!< reserved */
} RGX_HWPERF_COUNTER_CFG;
RGX_FW_STRUCT_SIZE_ASSERT(RGX_HWPERF_COUNTER_CFG);
/*! Sub-event's data. */
typedef union
{
@@ -930,7 +560,7 @@ typedef union
IMG_UINT32 ui32EvMaskLo; /*!< Low order 32 bits of Filter Mask */
IMG_UINT32 ui32EvMaskHi; /*!< High order 32 bits of Filter Mask */
} sEvMsk; /*!< HW Filter Mask */
RGX_HWPERF_COUNTER_CFG sPCC; /*!< Performance Counter Config. See RGX_HWPERF_COUNTER_CFG */
} RGX_HWPERF_FWACT_DETAIL;
RGX_FW_STRUCT_SIZE_ASSERT(RGX_HWPERF_FWACT_DETAIL);
@@ -1456,6 +1086,49 @@ typedef struct
static_assert((sizeof(RGX_HWPERF_HOST_SYNC_SW_TL_ADV_DATA) & (PVRSRVTL_PACKET_ALIGNMENT-1U)) == 0U,
"sizeof(RGX_HWPERF_HOST_SYNC_SW_TL_ADV_DATA) must be a multiple PVRSRVTL_PACKET_ALIGNMENT");
typedef enum
{
RGX_HWPERF_HOST_CLIENT_INFO_TYPE_INVALID = 0, /*!< Invalid */
RGX_HWPERF_HOST_CLIENT_INFO_TYPE_PROCESS_NAME, /*!< Process Name */
RGX_HWPERF_HOST_CLIENT_INFO_TYPE_LAST, /*!< Do not use */
} RGX_HWPERF_HOST_CLIENT_INFO_TYPE;
typedef struct
{
IMG_PID uiClientPID; /*!< Client process identifier */
IMG_UINT32 ui32Length; /*!< Number of bytes present in ``acName`` */
IMG_CHAR acName[RGX_HWPERF_ONE_OR_MORE_ELEMENTS]; /*!< Process name string, null terminated */
} RGX_HWPERF_HOST_CLIENT_PROC_NAME;
#define RGX_HWPERF_HOST_CLIENT_PROC_NAME_SIZE(ui32NameLen) \
((IMG_UINT32)(offsetof(RGX_HWPERF_HOST_CLIENT_PROC_NAME, acName) + (ui32NameLen)))
typedef union
{
struct
{
IMG_UINT32 ui32Count; /*!< Number of elements in ``asProcNames`` */
RGX_HWPERF_HOST_CLIENT_PROC_NAME asProcNames[RGX_HWPERF_ONE_OR_MORE_ELEMENTS];
} sProcName;
} RGX_HWPERF_HOST_CLIENT_INFO_DETAIL;
typedef struct
{
IMG_UINT32 uiReserved1; /*!< Reserved. Align structure size to 8 bytes */
RGX_HWPERF_HOST_CLIENT_INFO_TYPE eType;
/*!< Type of the subevent, see
RGX_HWPERF_HOST_CLIENT_INFO_TYPE */
RGX_HWPERF_HOST_CLIENT_INFO_DETAIL uDetail;
/*!< Union of structures. Size of data
varies with union member that is present,
check ``eType`` value to decode */
} RGX_HWPERF_HOST_CLIENT_INFO_DATA;
static_assert((sizeof(RGX_HWPERF_HOST_CLIENT_INFO_DATA) & (PVRSRVTL_PACKET_ALIGNMENT-1U)) == 0U,
"sizeof(RGX_HWPERF_HOST_CLIENT_INFO_DATA) must be a multiple PVRSRVTL_PACKET_ALIGNMENT");
typedef enum
{
RGX_HWPERF_RESOURCE_CAPTURE_TYPE_NONE,
@@ -1581,6 +1254,9 @@ typedef union
events ``0x09`` (Host) */
RGX_HWPERF_HOST_SYNC_SW_TL_ADV_DATA sSWTLADV; /*!< Host SW-timeline advance
data, events ``0x0A`` (Host) */
RGX_HWPERF_HOST_CLIENT_INFO_DATA sHClientInfo; /*!< Host client info,
events ``0x0B`` (Host) */
} RGX_HWPERF_V2_PACKET_DATA, *RGX_PHWPERF_V2_PACKET_DATA;
RGX_FW_STRUCT_SIZE_ASSERT(RGX_HWPERF_V2_PACKET_DATA);
@@ -1612,7 +1288,11 @@ typedef IMG_UINT32 RGX_HWPERF_CNTBLK_ID;
#define RGX_CNTBLK_ID_HUB 0x0002U /*!< Non-cluster grouping cores */
#define RGX_CNTBLK_ID_TORNADO 0x0003U /*!< XT cores */
#define RGX_CNTBLK_ID_JONES 0x0004U /*!< S7 cores */
#if defined(RGX_FEATURE_HWPERF_OCEANIC)
#define RGX_CNTBLK_ID_DIRECT_LAST 0x0003U /*!< Indirect blocks start from here */
#else
#define RGX_CNTBLK_ID_DIRECT_LAST 0x0005U /*!< Indirect blocks start from here */
#endif /* defined(RGX_FEATURE_HWPERF_OCEANIC) */
#define RGX_CNTBLK_ID_BF_DEPRECATED 0x0005U /*!< Doppler unit (DEPRECATED) */
#define RGX_CNTBLK_ID_BT_DEPRECATED 0x0006U /*!< Doppler unit (DEPRECATED) */
@@ -1747,6 +1427,19 @@ typedef IMG_UINT32 RGX_HWPERF_CNTBLK_ID;
/*! The number of layout blocks defined with configurable multiplexed
* performance counters, hence excludes custom counter blocks.
*/
#if defined(RGX_FEATURE_HWPERF_OCEANIC)
#define RGX_HWPERF_MAX_MUX_BLKS (\
(IMG_UINT32)RGX_CNTBLK_ID_DIRECT_LAST +\
RGX_CNTBLK_INDIRECT_COUNT(PBE, 0) )
#define RGX_HWPERF_MAX_DA_BLKS (\
(IMG_UINT32)RGX_CNTBLK_INDIRECT_COUNT(TPU_MCU, 0)+\
RGX_CNTBLK_INDIRECT_COUNT(USC, 0) )
#define RGX_HWPERF_MAX_DEFINED_BLKS (\
(IMG_UINT32)RGX_HWPERF_MAX_MUX_BLKS +\
RGX_HWPERF_MAX_DA_BLKS )
#else
#define RGX_HWPERF_MAX_DEFINED_BLKS (\
(IMG_UINT32)RGX_CNTBLK_ID_DIRECT_LAST +\
RGX_CNTBLK_INDIRECT_COUNT(TPU_MCU, 7)+\
@@ -1755,12 +1448,15 @@ typedef IMG_UINT32 RGX_HWPERF_CNTBLK_ID;
RGX_CNTBLK_INDIRECT_COUNT(RASTER, 3)+\
RGX_CNTBLK_INDIRECT_COUNT(BLACKPEARL, 3)+\
RGX_CNTBLK_INDIRECT_COUNT(PBE, 15) )
#define RGX_HWPERF_MAX_MUX_BLKS (\
RGX_HWPERF_MAX_DEFINED_BLKS )
#endif
static_assert(
((RGX_CNTBLK_ID_DIRECT_LAST + ((RGX_CNTBLK_ID_LAST & RGX_CNTBLK_ID_GROUP_MASK) >> RGX_CNTBLK_ID_GROUP_SHIFT)) <= RGX_HWPERF_MAX_BVNC_BLOCK_LEN),
"RGX_HWPERF_MAX_BVNC_BLOCK_LEN insufficient");
#define RGX_HWPERF_EVENT_MASK_VALUE(e) (IMG_UINT64_C(1) << (e))
#define RGX_HWPERF_EVENT_MASK_VALUE(e) (IMG_UINT64_C(1) << (IMG_UINT32)(e))
#define RGX_CUSTOM_FW_CNTRS \
X(TA_LOCAL_FL_SIZE, 0x0, RGX_HWPERF_EVENT_MASK_VALUE(RGX_HWPERF_HW_TAKICK) | \

9
drivers/gpu/drm/img-rogue/include/rogue/rgxheapconfig.h
View File

@@ -231,8 +231,13 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define RGX_FBCDC_HEAP_BASE IMG_UINT64_C(0xEC00000000)
#define RGX_FBCDC_HEAP_SIZE RGX_HEAP_SIZE_2MiB
/* 0xEC_0020_0000 - 0xED_FFFF_FFFF **/
/* 945 GiB to 952 GiB, size of 7 GiB : RESERVED VOLCANIC **/
/* 0xEC_4000_0000 - 0xEC_401F_FFFF **/
/* 945 GiB to 946 GiB, size 2 MiB : FBCDC_LARGE_HEAP **/
#define RGX_FBCDC_LARGE_HEAP_BASE IMG_UINT64_C(0xEC40000000)
#define RGX_FBCDC_LARGE_HEAP_SIZE RGX_HEAP_SIZE_2MiB
/* 0xEC_8000_0000 - 0xED_FFFF_FFFF **/
/* 946 GiB to 952 GiB, size of 6 GiB : RESERVED VOLCANIC **/
/* 0xEE_0000_0000 - 0xEE_3FFF_FFFF **/
/* 952 GiB to 953 GiB, size of 1 GiB : CMP_MISSION_RMW_HEAP **/

24
drivers/gpu/drm/img-rogue/include/servicesext.h
View File

@@ -88,25 +88,19 @@ typedef enum _PVRSRV_SYS_POWER_STATE_
/*!
Device Power State Enum
*/
typedef enum _PVRSRV_DEV_POWER_STATE_
{
PVRSRV_DEV_POWER_STATE_DEFAULT = -1, /*!< Default state for the device */
PVRSRV_DEV_POWER_STATE_OFF = 0, /*!< Unpowered */
PVRSRV_DEV_POWER_STATE_ON = 1, /*!< Running */
PVRSRV_DEV_POWER_STATE_FORCE_I32 = 0x7fffffff /*!< Force enum to be at least 32-bits wide */
} PVRSRV_DEV_POWER_STATE, *PPVRSRV_DEV_POWER_STATE; /*!< Typedef for ptr to PVRSRV_DEV_POWER_STATE */ /* PRQA S 3205 */
typedef IMG_INT32 PVRSRV_DEV_POWER_STATE;
typedef IMG_INT32 *PPVRSRV_DEV_POWER_STATE; /*!< Typedef for ptr to PVRSRV_DEV_POWER_STATE */ /* PRQA S 3205 */
#define PVRSRV_DEV_POWER_STATE_DEFAULT -1 /*!< Default state for the device */
#define PVRSRV_DEV_POWER_STATE_OFF 0 /*!< Unpowered */
#define PVRSRV_DEV_POWER_STATE_ON 1 /*!< Running */
/*!
Power Flags Enum
*/
typedef enum _PVRSRV_POWER_FLAGS_
{
PVRSRV_POWER_FLAGS_NONE = 0, /*!< No flags */
PVRSRV_POWER_FLAGS_FORCED = 1 << 0, /*!< Power the transition should not fail */
PVRSRV_POWER_FLAGS_SUSPEND = 1 << 1, /*!< Power transition is due to OS suspend request */
} PVRSRV_POWER_FLAGS;
typedef IMG_UINT32 PVRSRV_POWER_FLAGS;
#define PVRSRV_POWER_FLAGS_NONE 0U /*!< No flags */
#define PVRSRV_POWER_FLAGS_FORCED 1U << 0 /*!< Power the transition should not fail */
#define PVRSRV_POWER_FLAGS_SUSPEND 1U << 1 /*!< Power transition is due to OS suspend request */
/* Clock speed handler prototypes */

6
drivers/gpu/drm/img-rogue/include/sync_checkpoint_external.h
View File

@@ -49,9 +49,9 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#ifndef CHECKPOINT_TYPES
#define CHECKPOINT_TYPES
typedef struct _SYNC_CHECKPOINT_CONTEXT *PSYNC_CHECKPOINT_CONTEXT;
typedef struct SYNC_CHECKPOINT_CONTEXT_TAG *PSYNC_CHECKPOINT_CONTEXT;
typedef struct _SYNC_CHECKPOINT *PSYNC_CHECKPOINT;
typedef struct SYNC_CHECKPOINT_TAG *PSYNC_CHECKPOINT;
#endif
/* PVRSRV_SYNC_CHECKPOINT states.
@@ -68,7 +68,7 @@ typedef IMG_UINT32 PVRSRV_SYNC_CHECKPOINT_STATE;
#define PVRSRV_SYNC_CHECKPOINT_ERRORED 0xeffU /*!< checkpoint has been errored */
#define PVRSRV_UFO_IS_SYNC_CHECKPOINT_FWADDR(fwaddr) ((fwaddr) & 0x1U)
#define PVRSRV_UFO_IS_SYNC_CHECKPOINT_FWADDR(fwaddr) (((fwaddr) & 0x1U) != 0U)
#define PVRSRV_UFO_IS_SYNC_CHECKPOINT(ufoptr) (PVRSRV_UFO_IS_SYNC_CHECKPOINT_FWADDR((ufoptr)->puiAddrUFO.ui32Addr))
/* Maximum number of sync checkpoints the firmware supports in one fence */

63
drivers/gpu/drm/img-rogue/include/virt_validation_defs.h Normal file
View File

@@ -0,0 +1,63 @@
/*************************************************************************/ /*!
@File
@Title Definitions for virtualization
@Copyright Copyright (c) Imagination Technologies Ltd. All Rights Reserved
@Description Services shared header for virtualization definitions
@License Dual MIT/GPLv2
The contents of this file are subject to the MIT license as set out below.
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
Alternatively, the contents of this file may be used under the terms of
the GNU General Public License Version 2 ("GPL") in which case the provisions
of GPL are applicable instead of those above.
If you wish to allow use of your version of this file only under the terms of
GPL, and not to allow others to use your version of this file under the terms
of the MIT license, indicate your decision by deleting the provisions above
and replace them with the notice and other provisions required by GPL as set
out in the file called "GPL-COPYING" included in this distribution. If you do
not delete the provisions above, a recipient may use your version of this file
under the terms of either the MIT license or GPL.
This License is also included in this distribution in the file called
"MIT-COPYING".
EXCEPT AS OTHERWISE STATED IN A NEGOTIATED AGREEMENT: (A) THE SOFTWARE IS
PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
PURPOSE AND NONINFRINGEMENT; AND (B) IN NO EVENT SHALL THE AUTHORS OR
COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/ /**************************************************************************/
#ifndef SRV_VIRT_DEFS_H
#define SRV_VIRT_DEFS_H
#if !defined(GPUVIRT_VALIDATION_MAX_STRING_LENGTH)
#define GPUVIRT_VALIDATION_MAX_STRING_LENGTH 512
#endif
#define GPUVIRT_VALIDATION_MAX_OS 8
#define GPUVIRT_VALIDATION_NUM_REGIONS 2
#define GPUVIRT_VAL_REGION_SECURE 0
#define GPUVIRT_VAL_REGION_SHARED 1
/* Shared region 1MB */
#define GPUVIRT_SIZEOF_SHARED 0x100000
/* Min region size 64MB */
#define GPUVIRT_MIN_SIZE 0x4000000
#endif /* SRV_VIRT_DEFS_H */

268
drivers/gpu/drm/img-rogue/include/volcanic/rgx_fwif_km.h
View File

@@ -156,20 +156,31 @@ typedef struct
IMG_UINT32 ui32LineNum;
} UNCACHED_ALIGN RGXFWIF_FILE_INFO_BUF;
/*!
* @Defgroup SRVAndFWTracing Services and Firmware Tracing data interface
* @Brief The document groups/lists the data structures and the interfaces related to Services and Firmware Tracing
* @{
*/
/*!
* @Brief Firmware trace buffer details
*/
typedef struct
{
IMG_UINT32 ui32TracePointer;
IMG_UINT32 ui32TracePointer; /*!< Trace pointer (write index into Trace Buffer)*/
#if defined(RGX_FIRMWARE)
IMG_UINT32 *pui32RGXFWIfTraceBuffer; /* To be used by firmware for writing into trace buffer */
IMG_UINT32 *pui32RGXFWIfTraceBuffer; /*!< Trace buffer address (FW address), to be used by firmware for writing into trace buffer */
#else
RGXFWIF_DEV_VIRTADDR pui32RGXFWIfTraceBuffer;
RGXFWIF_DEV_VIRTADDR pui32RGXFWIfTraceBuffer; /*!< Trace buffer address (FW address)*/
#endif
IMG_PUINT32 pui32TraceBuffer; /* To be used by host when reading from trace buffer */
IMG_PUINT32 pui32TraceBuffer; /*!< Trace buffer address (Host address), to be used by host when reading from trace buffer */
RGXFWIF_FILE_INFO_BUF sAssertBuf;
RGXFWIF_FILE_INFO_BUF sAssertBuf;
} UNCACHED_ALIGN RGXFWIF_TRACEBUF_SPACE;
/*! @} End of Defgroup SRVAndFWTracing */
#define RGXFWIF_FWFAULTINFO_MAX (8U) /* Total number of FW fault logs stored */
typedef struct
@@ -271,14 +282,17 @@ typedef struct
} UNCACHED_ALIGN RGXFWIF_SLR_ENTRY;
#endif
/* firmware trace control data */
/*!
* @InGroup SRVAndFWTracing
* @Brief Firmware trace control data
*/
typedef struct
{
IMG_UINT32 ui32LogType;
RGXFWIF_TRACEBUF_SPACE sTraceBuf[RGXFW_THREAD_NUM];
IMG_UINT32 ui32TraceBufSizeInDWords; /*!< Member initialised only when sTraceBuf is actually allocated
* (in RGXTraceBufferInitOnDemandResources) */
IMG_UINT32 ui32TracebufFlags; /*!< Compatibility and other flags */
IMG_UINT32 ui32LogType; /*!< FW trace log group configuration */
RGXFWIF_TRACEBUF_SPACE sTraceBuf[RGXFW_THREAD_NUM]; /*!< FW Trace buffer */
IMG_UINT32 ui32TraceBufSizeInDWords; /*!< FW Trace buffer size in dwords, Member initialised only when sTraceBuf is actually allocated
(in RGXTraceBufferInitOnDemandResources) */
IMG_UINT32 ui32TracebufFlags; /*!< Compatibility and other flags */
} UNCACHED_ALIGN RGXFWIF_TRACEBUF;
/*! @Brief Firmware system data shared with the Host driver */
@@ -547,13 +561,13 @@ typedef struct
#define RGXFWIF_INICFG_FBCDC_V3_1_EN (IMG_UINT32_C(0x1) << 6)
#define RGXFWIF_INICFG_CHECK_MLIST_EN (IMG_UINT32_C(0x1) << 7)
#define RGXFWIF_INICFG_DISABLE_CLKGATING_EN (IMG_UINT32_C(0x1) << 8)
#define RGXFWIF_INICFG_POLL_COUNTERS_EN (IMG_UINT32_C(0x1) << 9)
/* 9 unused */
/* 10 unused */
/* 11 unused */
#define RGXFWIF_INICFG_REGCONFIG_EN (IMG_UINT32_C(0x1) << 12)
#define RGXFWIF_INICFG_ASSERT_ON_OUTOFMEMORY (IMG_UINT32_C(0x1) << 13)
#define RGXFWIF_INICFG_HWP_DISABLE_FILTER (IMG_UINT32_C(0x1) << 14)
#define RGXFWIF_INICFG_CUSTOM_PERF_TIMER_EN (IMG_UINT32_C(0x1) << 15)
/* 15 unused */
#define RGXFWIF_INICFG_CTXSWITCH_PROFILE_SHIFT (16)
#define RGXFWIF_INICFG_CTXSWITCH_PROFILE_FAST (RGXFWIF_CTXSWITCH_PROFILE_FAST_EN << RGXFWIF_INICFG_CTXSWITCH_PROFILE_SHIFT)
#define RGXFWIF_INICFG_CTXSWITCH_PROFILE_MEDIUM (RGXFWIF_CTXSWITCH_PROFILE_MEDIUM_EN << RGXFWIF_INICFG_CTXSWITCH_PROFILE_SHIFT)
@@ -691,9 +705,9 @@ typedef RGXFWIF_DEV_VIRTADDR PRGXFWIF_RF_CMD;
#define RGXFWIF_INVALID_PC_PHYADDR 0xFFFFFFFFFFFFFFFFLLU
/*!
* This number is used to represent unallocated page catalog base register
* This number is used to represent an unallocated set of page catalog base registers
*/
#define RGXFW_BIF_INVALID_PCREG 0xFFFFFFFFU
#define RGXFW_BIF_INVALID_PCSET 0xFFFFFFFFU
/*!
Firmware memory context.
@@ -701,7 +715,7 @@ typedef RGXFWIF_DEV_VIRTADDR PRGXFWIF_RF_CMD;
typedef struct
{
IMG_DEV_PHYADDR RGXFW_ALIGN sPCDevPAddr; /*!< device physical address of context's page catalogue */
IMG_UINT32 uiPageCatBaseRegID; /*!< associated page catalog base register (RGXFW_BIF_INVALID_PCREG == unallocated) */
IMG_UINT32 uiPageCatBaseRegSet; /*!< index of the associated set of page catalog base registers (RGXFW_BIF_INVALID_PCSET == unallocated) */
IMG_UINT32 uiBreakpointAddr; /*!< breakpoint address */
IMG_UINT32 uiBPHandlerAddr; /*!< breakpoint handler address */
IMG_UINT32 uiBreakpointCtl; /*!< DM and enable control for BP */
@@ -720,6 +734,7 @@ typedef struct
*/
#define RGXFWIF_CONTEXT_FLAGS_NEED_RESUME (0x00000001U)
#define RGXFWIF_CONTEXT_FLAGS_TDM_HEADER_STALE (0x00000002U)
#define RGXFWIF_CONTEXT_FLAGS_LAST_KICK_SECURE (0x00000200U)
/*!
* @InGroup ContextSwitching
@@ -798,7 +813,7 @@ typedef struct RGXFWIF_FWCOMMONCONTEXT_
/* Flags e.g. for context switching */
IMG_UINT32 ui32FWComCtxFlags;
IMG_UINT32 ui32Priority; /*!< Priority level */
IMG_INT32 i32Priority; /*!< Priority level */
IMG_UINT32 ui32PrioritySeqNum;
/* Framework state */
@@ -831,6 +846,7 @@ typedef struct RGXFWIF_FWCOMMONCONTEXT_
IMG_BOOL bGeomOOMDisabled; /*!< True when Geom DM OOM is not allowed */
IMG_UINT32 ui32PipelinedKicks; /*!< Number of kick from this CCB currently submitted to the DM pipeline */
} UNCACHED_ALIGN RGXFWIF_FWCOMMONCONTEXT;
static_assert(sizeof(RGXFWIF_FWCOMMONCONTEXT) <= 256,
@@ -851,10 +867,13 @@ typedef struct
RGXFWIF_STATIC_RENDERCONTEXT_STATE sStaticRenderContextState;
IMG_UINT32 ui32TotalNumPartialRenders; /*!< Total number of partial renders */
IMG_UINT32 ui32TotalNumOutOfMemory; /*!< Total number of OOMs */
IMG_UINT32 ui32WorkEstCCBSubmitted; /*!< Number of commands submitted to the WorkEst FW CCB */
IMG_UINT32 ui32FwRenderCtxFlags; /*!< Compatibility and other flags */
#if defined(SUPPORT_TRP)
RGXFWIF_TRP_CHECKSUM_3D aui64TRPChecksums3D;
RGXFWIF_TRP_CHECKSUM_GEOM aui64TRPChecksumsGeom;
#endif
} UNCACHED_ALIGN RGXFWIF_FWRENDERCONTEXT;
/*!
@@ -1058,7 +1077,11 @@ typedef struct
RGXFWIF_POWER_TYPE ePowType; /*!< Type of power request */
union
{
IMG_UINT32 ui32PowUnitsStateMask; /*!< New power units state mask */
struct
{
IMG_UINT32 ui32PowUnitsStateMask; /*!< New power units state mask */
IMG_UINT32 ui32RACStateMask; /*!< New RAC state mask */
};
IMG_BOOL bForced; /*!< If the operation is mandatory */
RGXFWIF_POWER_FORCE_IDLE_TYPE ePowRequestType; /*!< Type of Request. Consolidating Force Idle, Cancel Forced Idle, Host Timeout */
} uPowerReqData;
@@ -1146,6 +1169,13 @@ typedef struct
IMG_UINT32 ui32RegAddr;
IMG_UINT64 RGXFW_ALIGN ui64RegVal;
} RGXFWIF_RGXREG_DATA;
typedef struct
{
IMG_UINT64 ui64BaseAddress;
PRGXFWIF_FWCOMMONCONTEXT psContext;
IMG_UINT32 ui32Size;
} RGXFWIF_GPUMAP_DATA;
#endif
/*!
@@ -1317,6 +1347,9 @@ typedef enum
RGXFWIF_KCCB_CMD_RGXREG = 214U | RGX_CMD_MAGIC_DWORD_SHIFTED, /*!< Read RGX Register from FW */
#endif
RGXFWIF_KCCB_CMD_WDG_CFG = 215U | RGX_CMD_MAGIC_DWORD_SHIFTED, /*!< Configure Safety Firmware Watchdog */
#if defined(SUPPORT_VALIDATION)
RGXFWIF_KCCB_CMD_GPUMAP = 219U | RGX_CMD_MAGIC_DWORD_SHIFTED, /*!< Request a FW GPU mapping which is written into by the FW with a pattern */
#endif
} RGXFWIF_KCCB_CMD_TYPE;
#define RGXFWIF_LAST_ALLOWED_GUEST_KCCB_CMD (RGXFWIF_KCCB_CMD_REGCONFIG - 1)
@@ -1358,6 +1391,7 @@ typedef struct
RGXFWIF_KCCB_CMD_FORCE_UPDATE_DATA sForceUpdateData; /*!< Data for signalling all unmet fences for a given CCB */
#if defined(SUPPORT_VALIDATION)
RGXFWIF_RGXREG_DATA sFwRgxData; /*!< Data for reading off an RGX register */
RGXFWIF_GPUMAP_DATA sGPUMapData; /*!< Data for requesting a FW GPU mapping which is written into by the FW with a pattern */
#endif
} UNCACHED_ALIGN uCmdData;
} UNCACHED_ALIGN RGXFWIF_KCCB_CMD;
@@ -1643,7 +1677,7 @@ typedef struct
/*! @Brief Command data for \ref RGXFWIF_CCB_CMD_TYPE_PRIORITY type client CCB command */
typedef struct
{
IMG_UINT32 ui32Priority; /*!< Priority level */
IMG_INT32 i32Priority; /*!< Priority level */
} RGXFWIF_CMD_PRIORITY;
/*! @} End of ClientCCBTypes */
@@ -1719,6 +1753,7 @@ typedef struct
IMG_BOOL bActivePMLatencyPersistant; /* If set, APM latency does not reset to system default each GPU power transition */
IMG_UINT32 ui32CoreClockSpeed; /* Core clock speed, currently only used to calculate timer ticks */
IMG_UINT32 ui32PowUnitsStateMask; /* Power Unit state mask set by the host */
IMG_UINT32 ui32RACStateMask; /* RAC state mask set by the host */
IMG_UINT32 ui32PHRMode; /* Periodic Hardware Reset configuration values */
IMG_UINT32 ui32HCSDeadlineMS; /* New number of milliseconds C/S is allowed to last */
IMG_UINT32 ui32WdgPeriodUs; /* The watchdog period in microseconds */
@@ -1822,8 +1857,6 @@ typedef enum
FW_PERF_CONF_NONE = 0,
FW_PERF_CONF_ICACHE = 1,
FW_PERF_CONF_DCACHE = 2,
FW_PERF_CONF_POLLS = 3,
FW_PERF_CONF_CUSTOM_TIMER = 4,
FW_PERF_CONF_JTLB_INSTR = 5,
FW_PERF_CONF_INSTRUCTIONS = 6
} FW_PERF_CONF;
@@ -2000,9 +2033,13 @@ typedef struct
IMG_UINT32 ui32OSKickTest;
#endif
#if defined(SUPPORT_AUTOVZ)
IMG_UINT32 ui32VzWdgPeriod;
#endif
} UNCACHED_ALIGN RGXFWIF_SYSINIT;
static_assert(sizeof(RGXFWIF_SYSINIT) <= 952,
static_assert(sizeof(RGXFWIF_SYSINIT) <= 968,
"Size of structure RGXFWIF_SYSINIT exceeds maximum expected size.");
#if defined(SUPPORT_GPUVIRT_VALIDATION)
@@ -2131,95 +2168,42 @@ typedef struct
IMG_UINT32 ui32RTACtlFlags; /* Compatibility and other flags */
} UNCACHED_ALIGN RGXFWIF_RTA_CTL;
/*! @Brief Firmware Freelist holding usage state of the Parameter Buffers */
/*!
* @InGroup RenderTarget
* @Brief Firmware Freelist holding usage state of the Parameter Buffers
*/
typedef struct
{
IMG_DEV_VIRTADDR RGXFW_ALIGN sFreeListBaseDevVAddr; /*!< Free list device base address */
IMG_DEV_VIRTADDR RGXFW_ALIGN sFreeListStateDevVAddr; /*!< Free list state buffer */
IMG_DEV_VIRTADDR RGXFW_ALIGN sFreeListLastGrowDevVAddr; /*!< Free list base address at last grow */
IMG_DEV_VIRTADDR RGXFW_ALIGN sFreeListBaseDevVAddr; /*!< Freelist page table base address */
IMG_DEV_VIRTADDR RGXFW_ALIGN sFreeListStateDevVAddr; /*!< Freelist state buffer base address */
IMG_DEV_VIRTADDR RGXFW_ALIGN sFreeListLastGrowDevVAddr; /*!< Freelist base address at last grow */
#if defined(PM_INTERACTIVE_MODE)
IMG_UINT64 RGXFW_ALIGN ui64CurrentDevVAddr;
IMG_UINT32 ui32CurrentStackTop;
IMG_UINT64 RGXFW_ALIGN ui64CurrentDevVAddr;/*!< Freelist page table entry for current free page */
IMG_UINT32 ui32CurrentStackTop; /*!< Freelist current free page */
#endif
IMG_UINT32 ui32MaxPages;
IMG_UINT32 ui32GrowPages;
IMG_UINT32 ui32CurrentPages; /* HW pages */
IMG_UINT32 ui32MaxPages; /*!< Max no. of pages can be added to the freelist */
IMG_UINT32 ui32GrowPages; /*!< No pages to add in each freelist grow */
IMG_UINT32 ui32CurrentPages; /*!< Total no. of pages made available to the PM HW */
#if defined(PM_INTERACTIVE_MODE)
IMG_UINT32 ui32AllocatedPageCount;
IMG_UINT32 ui32AllocatedMMUPageCount;
IMG_UINT32 ui32AllocatedPageCount; /*!< No. of pages allocated by PM HW */
IMG_UINT32 ui32AllocatedMMUPageCount; /*!< No. of pages allocated for GPU MMU for PM*/
#endif
#if defined(SUPPORT_SHADOW_FREELISTS)
IMG_UINT32 ui32HWRCounter;
IMG_UINT32 ui32HWRCounter;
PRGXFWIF_FWMEMCONTEXT psFWMemContext;
#endif
IMG_UINT32 ui32FreeListID;
IMG_BOOL bGrowPending;
IMG_UINT32 ui32ReadyPages; /* Pages that should be used only when OOM is reached */
IMG_UINT32 ui32FreelistFlags; /* Compatibility and other flags */
IMG_UINT32 ui32FreeListID; /*!< Unique Freelist ID */
IMG_BOOL bGrowPending; /*!< Freelist grow is pending */
IMG_UINT32 ui32ReadyPages; /*!< Reserved pages to be used only on PM OOM event */
IMG_UINT32 ui32FreelistFlags; /*!< Compatibility and other flags */
IMG_BOOL bUpdatePending;
IMG_UINT32 ui32UpdateNewPages;
IMG_UINT32 ui32UpdateNewReadyPages;
IMG_BOOL bUpdatePending;
IMG_UINT32 ui32UpdateNewPages;
IMG_UINT32 ui32UpdateNewReadyPages;
} UNCACHED_ALIGN RGXFWIF_FREELIST;
#if defined(SUPPORT_SW_TRP)
#define SW_TRP_SIGNATURE_FIRST_KICK 0U
#define SW_TRP_SIGNATURE_SECOND_KICK 1U
#define SW_TRP_SIGNATURE_COUNT 2U
#define SW_TRP_GEOMETRY_SIGNATURE_SIZE 8U
#define SW_TRP_FRAGMENT_SIGNATURE_SIZE 8U
/* Space for tile usage bitmap, one bit per tile on screen */
#define RGX_FEATURE_TILE_SIZE_X (32U)
#define RGX_FEATURE_TILE_SIZE_Y (32U)
#define SW_TRP_TILE_USED_SIZE ((ROGUE_RENDERSIZE_MAXX / RGX_FEATURE_TILE_SIZE_X + ROGUE_RENDERSIZE_MAXY / RGX_FEATURE_TILE_SIZE_Y) / (8U * sizeof(IMG_UINT32)))
#endif
/*!
******************************************************************************
* Parameter Management (PM) control data for RGX
*****************************************************************************/
typedef enum
{
RGXFW_SPM_STATE_NONE = 0,
RGXFW_SPM_STATE_PR_BLOCKED,
RGXFW_SPM_STATE_WAIT_FOR_GROW,
RGXFW_SPM_STATE_WAIT_FOR_HW,
RGXFW_SPM_STATE_PR_RUNNING,
RGXFW_SPM_STATE_PR_AVOIDED,
RGXFW_SPM_STATE_PR_EXECUTED,
RGXFW_SPM_STATE_PR_FORCEFREE,
} RGXFW_SPM_STATE;
/*!
******************************************************************************
* @Brief RGX firmware SPM Control Data:
* This structure holds all the internal SPM control Data of the firmware.
*****************************************************************************/
typedef struct
{
RGXFW_SPM_STATE eSPMState; /*!< Current state of TA OOM event */
RGXFWIF_UFO sPartialRenderTA3DFence; /*!< TA/3D fence object holding the value to let through the 3D partial command */
#if defined(RGX_FIRMWARE)
RGXFWIF_FWCOMMONCONTEXT *ps3dContext; /*!< Pointer to the 3D Context holding the partial render */
RGXFWIF_PRBUFFER *apsPRBuffer[RGXFWIF_PRBUFFER_MAXSUPPORTED]; /*!< Array of pointers to PR Buffers which may be used if partial render is needed */
#else
RGXFWIF_DEV_VIRTADDR ps3dContext; /*!< Pointer to the 3D Context holding the partial render */
RGXFWIF_DEV_VIRTADDR apsPRBuffer[RGXFWIF_PRBUFFER_MAXSUPPORTED]; /*!< Array of pointers to PR Buffers which may be used if partial render is needed */
#endif
IMG_UINT32 ui32CmdOffset; /*!< CCCB offset of the command holding the partial render */
bool b3DMemFreeDetected; /*!< Indicates if a 3D Memory Free has been detected, which resolves OOM */
#if defined(SUPPORT_AGP)
IMG_UINT32 ui32OOMCoreMask; /*!< Mask of all the cores that are OOM */
RGXFWIF_DM eCurrentDM; /*!< Current DM that is in SPM */
#endif
} RGXFW_ALIGN_DCACHEL RGXFW_SPMCTL;
static_assert(sizeof(RGXFW_SPMCTL) <= 64,
"Size of structure RGXFW_SPMCTL exceeds maximum expected size.");
/*!
******************************************************************************
* HWRTData
@@ -2227,13 +2211,16 @@ static_assert(sizeof(RGXFW_SPMCTL) <= 64,
/* HWRTData flags */
/* Deprecated flags 1:0 */
#define HWRTDATA_HAS_LAST_TA (1U << 2)
#define HWRTDATA_PARTIAL_RENDERED (1U << 3)
#define HWRTDATA_KILLED (1U << 4)
#define HWRTDATA_KILL_AFTER_TARESTART (1U << 5)
#define HWRTDATA_HAS_LAST_TA (1UL << 2)
#define HWRTDATA_PARTIAL_RENDERED (1UL << 3)
#define HWRTDATA_KILLED (1UL << 4)
#define HWRTDATA_KILL_AFTER_TARESTART (1UL << 5)
#if defined(SUPPORT_AGP)
#define HWRTDATA_USE_SECONDARY_GLOBAL_PB (1U << 6)
#define HWRTDATA_GEOM_NEEDS_RESUME (1U << 7)
#define HWRTDATA_GLOBAL_PB_NUMBER_BIT0 (1UL << 6)
#if defined(SUPPORT_AGP4)
#define HWRTDATA_GLOBAL_PB_NUMBER_BIT1 (1UL << 7)
#endif
#define HWRTDATA_GEOM_NEEDS_RESUME (1UL << 8)
#endif
typedef enum
@@ -2273,67 +2260,54 @@ typedef struct
IMG_UINT32 ui32ISPMergeScaleY;
} UNCACHED_ALIGN RGXFWIF_HWRTDATA_COMMON;
/*! @Brief Firmware Render Target data i.e. HWRTDATA used to hold the PM context */
/*!
* @InGroup RenderTarget
* @Brief Firmware Render Target data i.e. HWRTDATA used to hold the PM context
*/
typedef struct
{
IMG_UINT64 RGXFW_ALIGN ui64VCECatBase[4];
IMG_UINT64 RGXFW_ALIGN ui64VCELastCatBase[4];
IMG_UINT64 RGXFW_ALIGN ui64TECatBase[4];
IMG_UINT64 RGXFW_ALIGN ui64TELastCatBase[4];
IMG_UINT64 RGXFW_ALIGN ui64AlistCatBase;
IMG_UINT64 RGXFW_ALIGN ui64AlistLastCatBase;
IMG_UINT64 RGXFW_ALIGN ui64VCECatBase[4]; /*!< VCE Page Catalogue base */
IMG_UINT64 RGXFW_ALIGN ui64VCELastCatBase[4];
IMG_UINT64 RGXFW_ALIGN ui64TECatBase[4]; /*!< TE Page Catalogue base */
IMG_UINT64 RGXFW_ALIGN ui64TELastCatBase[4];
IMG_UINT64 RGXFW_ALIGN ui64AlistCatBase; /*!< Alist Page Catalogue base */
IMG_UINT64 RGXFW_ALIGN ui64AlistLastCatBase;
#if defined(PM_INTERACTIVE_MODE)
IMG_DEV_VIRTADDR RGXFW_ALIGN psVHeapTableDevVAddr;
IMG_DEV_VIRTADDR RGXFW_ALIGN sPMMListDevVAddr;
IMG_DEV_VIRTADDR RGXFW_ALIGN psVHeapTableDevVAddr; /*!< VHeap table base */
IMG_DEV_VIRTADDR RGXFW_ALIGN sPMMListDevVAddr; /*!< Mlist table base */
#else
/* Series8 PM State buffers */
IMG_DEV_VIRTADDR RGXFW_ALIGN sPMRenderStateDevVAddr;
IMG_DEV_VIRTADDR RGXFW_ALIGN sPMSecureRenderStateDevVAddr;
IMG_DEV_VIRTADDR RGXFW_ALIGN sPMRenderStateDevVAddr; /*!< Series8 PM State buffers */
IMG_DEV_VIRTADDR RGXFW_ALIGN sPMSecureRenderStateDevVAddr;
#endif
PRGXFWIF_FREELIST RGXFW_ALIGN apsFreeLists[RGXFW_MAX_FREELISTS];
IMG_UINT32 aui32FreeListHWRSnapshot[RGXFW_MAX_FREELISTS];
IMG_BOOL bRenderStateNeedsReset;
PRGXFWIF_FREELIST RGXFW_ALIGN apsFreeLists[RGXFW_MAX_FREELISTS]; /*!< Freelist to use */
IMG_UINT32 aui32FreeListHWRSnapshot[RGXFW_MAX_FREELISTS];
IMG_BOOL bRenderStateNeedsReset;
RGXFWIF_DEV_VIRTADDR sHWRTDataCommonFwAddr;
RGXFWIF_DEV_VIRTADDR sHWRTDataCommonFwAddr; /*!< Render target dimension dependent data */
IMG_UINT32 ui32HWRTDataFlags;
RGXFWIF_RTDATA_STATE eState;
IMG_UINT32 ui32HWRTDataFlags;
RGXFWIF_RTDATA_STATE eState; /*!< Current workload processing state of HWRTDATA */
RGXFWIF_CLEANUP_CTL sCleanupState;
RGXFWIF_CLEANUP_CTL sCleanupState; /*!< Render target clean up state */
RGXFWIF_RTA_CTL sRTACtl;
RGXFWIF_RTA_CTL sRTACtl; /*!< Render target array data */
IMG_DEV_VIRTADDR RGXFW_ALIGN sTailPtrsDevVAddr;
IMG_DEV_VIRTADDR RGXFW_ALIGN sTailPtrsDevVAddr; /*!< Tail pointers base */
#if defined(RGX_FIRMWARE)
struct RGXFWIF_FWCOMMONCONTEXT_* psOwnerGeom;
struct RGXFWIF_FWCOMMONCONTEXT_* psOwnerGeom;
#else
RGXFWIF_DEV_VIRTADDR pui32OwnerGeomNotUsedByHost;
RGXFWIF_DEV_VIRTADDR pui32OwnerGeomNotUsedByHost;
#endif
#if defined(PM_INTERACTIVE_MODE)
IMG_UINT64 RGXFW_ALIGN ui64PMAListStackPointer;
IMG_UINT32 ui32PMMListStackPointer;
#endif
#if defined(SUPPORT_SW_TRP)
/* SW-TRP state and signature data
*
* Stored state is used to kick the same geometry or 3D twice,
* State is stored before first kick and restored before second to rerun the same data.
* Signatures from both kicks are stored and compared */
IMG_UINT32 aaui32GeometrySignature[SW_TRP_SIGNATURE_COUNT][SW_TRP_GEOMETRY_SIGNATURE_SIZE];
IMG_UINT32 aaui32FragmentSignature[SW_TRP_SIGNATURE_COUNT][SW_TRP_FRAGMENT_SIGNATURE_SIZE];
IMG_UINT32 ui32KickFlagsCopy;
IMG_UINT32 ui32SW_TRPState;
IMG_UINT32 aui32TileUsed[SW_TRP_TILE_USED_SIZE];
RGXFW_SPMCTL sSPMCtlCopy;
IMG_UINT64 RGXFW_ALIGN ui64PMAListStackPointer; /*!< Freelist page table entry for current Mlist page */
IMG_UINT32 ui32PMMListStackPointer; /*!< Current Mlist page */
#endif
#if defined(SUPPORT_TRP)
IMG_UINT32 ui32KickFlagsCopy;
IMG_UINT32 ui32TRPState;
RGXFWIF_TRP_CHECKSUM_3D aui64TRPChecksums3D;
RGXFWIF_TRP_CHECKSUM_GEOM aui64TRPChecksumsGeom;
IMG_UINT32 ui32KickFlagsCopy;
IMG_UINT32 ui32TRPState;
#endif
} UNCACHED_ALIGN RGXFWIF_HWRTDATA;

32
drivers/gpu/drm/img-rogue/include/volcanic/rgx_fwif_shared.h
View File

@@ -52,10 +52,17 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
/* Indicates the number of RTDATAs per RTDATASET */
#if defined(SUPPORT_AGP)
#if defined(SUPPORT_AGP4)
#define RGXMKIF_NUM_RTDATAS 4U
#define RGXMKIF_NUM_GEOMDATAS 4U
#define RGXMKIF_NUM_RTDATA_FREELISTS 20U /* RGXMKIF_NUM_RTDATAS * RGXFW_MAX_FREELISTS */
#define RGX_NUM_GEOM_CORES (4U)
#else
#define RGXMKIF_NUM_RTDATAS 4U
#define RGXMKIF_NUM_GEOMDATAS 4U
#define RGXMKIF_NUM_RTDATA_FREELISTS 12U /* RGXMKIF_NUM_RTDATAS * RGXFW_MAX_FREELISTS */
#define RGX_NUM_GEOM_CORES (2U)
#endif
#else
#define RGXMKIF_NUM_RTDATAS 2U
#define RGXMKIF_NUM_GEOMDATAS 1U
@@ -131,13 +138,17 @@ typedef enum
RGXFWIF_PRBUFFER_UNBACKING_PENDING,
}RGXFWIF_PRBUFFER_STATE;
/*!
* @InGroup RenderTarget
* @Brief OnDemand Z/S/MSAA Buffers
*/
typedef struct
{
IMG_UINT32 ui32BufferID; /*!< Buffer ID*/
IMG_BOOL bOnDemand; /*!< Needs On-demand Z/S/MSAA Buffer allocation */
RGXFWIF_PRBUFFER_STATE eState; /*!< Z/S/MSAA -Buffer state */
RGXFWIF_CLEANUP_CTL sCleanupState; /*!< Cleanup state */
IMG_UINT32 ui32PRBufferFlags; /*!< Compatibility and other flags */
IMG_UINT32 ui32BufferID; /*!< Buffer ID*/
IMG_BOOL bOnDemand; /*!< Needs On-demand Z/S/MSAA Buffer allocation */
RGXFWIF_PRBUFFER_STATE eState; /*!< Z/S/MSAA -Buffer state */
RGXFWIF_CLEANUP_CTL sCleanupState; /*!< Cleanup state */
IMG_UINT32 ui32PRBufferFlags; /*!< Compatibility and other flags */
} UNCACHED_ALIGN RGXFWIF_PRBUFFER;
/*
@@ -201,6 +212,10 @@ typedef struct
in bytes of the CCB-1 */
#if defined(SUPPORT_AGP)
IMG_UINT32 ui32ReadOffset2;
#if defined(SUPPORT_AGP4)
IMG_UINT32 ui32ReadOffset3;
IMG_UINT32 ui32ReadOffset4;
#endif
#endif
} UNCACHED_ALIGN RGXFWIF_CCCB_CTL;
@@ -209,7 +224,12 @@ typedef IMG_UINT32 RGXFW_FREELIST_TYPE;
#define RGXFW_LOCAL_FREELIST IMG_UINT32_C(0)
#define RGXFW_GLOBAL_FREELIST IMG_UINT32_C(1)
#if defined(SUPPORT_AGP)
#if defined(SUPPORT_AGP4)
#define RGXFW_GLOBAL2_FREELIST IMG_UINT32_C(2)
#define RGXFW_GLOBAL3_FREELIST IMG_UINT32_C(3)
#define RGXFW_GLOBAL4_FREELIST IMG_UINT32_C(4)
#define RGXFW_MAX_FREELISTS (RGXFW_GLOBAL4_FREELIST + 1U)
#elif defined(SUPPORT_AGP)
#define RGXFW_GLOBAL2_FREELIST IMG_UINT32_C(2)
#define RGXFW_MAX_FREELISTS (RGXFW_GLOBAL2_FREELIST + 1U)
#else

485
drivers/gpu/drm/img-rogue/include/volcanic/rgx_hwperf.h
View File

@@ -60,6 +60,7 @@ extern "C" {
#include "img_defs.h"
#include "rgx_common.h"
#include "rgx_hwperf_common.h"
#include "pvrsrv_tlcommon.h"
#include "pvrsrv_sync_km.h"
@@ -77,400 +78,6 @@ static_assert(RGX_FEATURE_NUM_CLUSTERS <= 16U,
#define RGX_HWPERF_CTRL_COMP_FULLRANGE (2U) /*!< selectable compute counters are full range */
#define RGX_HWPERF_CTRL_TDM_FULLRANGE (4U) /*!< selectable TDM counters are full range */
/******************************************************************************
* Packet Event Type Enumerations
*****************************************************************************/
/*! Type used to encode the event that generated the packet.
* NOTE: When this type is updated the corresponding hwperfbin2json tool
* source needs to be updated as well. The RGX_HWPERF_EVENT_MASK_* macros will
* also need updating when adding new types.
*
* @par
* The event type values are incrementing integers for use as a shift ordinal
* in the event filtering process at the point events are generated.
* This scheme thus implies a limit of 63 event types.
*/
typedef IMG_UINT32 RGX_HWPERF_EVENT_TYPE;
#define RGX_HWPERF_INVALID 0x00U /*!< Invalid. Reserved value. */
/*! FW types 0x01..0x06 */
#define RGX_HWPERF_FW_EVENT_RANGE_FIRST_TYPE 0x01U
#define RGX_HWPERF_FW_BGSTART 0x01U /*!< Background task processing start */
#define RGX_HWPERF_FW_BGEND 0x02U /*!< Background task end */
#define RGX_HWPERF_FW_IRQSTART 0x03U /*!< IRQ task processing start */
#define RGX_HWPERF_FW_IRQEND 0x04U /*!< IRQ task end */
#define RGX_HWPERF_FW_DBGSTART 0x05U /*!< Debug event start */
#define RGX_HWPERF_FW_DBGEND 0x06U /*!< Debug event end */
#define RGX_HWPERF_FW_EVENT_RANGE_LAST_TYPE 0x06U
/*! HW types 0x07..0x19 */
#define RGX_HWPERF_HW_EVENT_RANGE0_FIRST_TYPE 0x07U
#define RGX_HWPERF_HW_PMOOM_TAPAUSE 0x07U /*!< TA Pause at PM Out of Memory */
#define RGX_HWPERF_HW_TAKICK 0x08U /*!< TA task started */
#define RGX_HWPERF_HW_TAFINISHED 0x09U /*!< TA task finished */
#define RGX_HWPERF_HW_3DTQKICK 0x0AU /*!< 3D TQ started */
#define RGX_HWPERF_HW_3DKICK 0x0BU /*!< 3D task started */
#define RGX_HWPERF_HW_3DFINISHED 0x0CU /*!< 3D task finished */
#define RGX_HWPERF_HW_CDMKICK 0x0DU /*!< CDM task started */
#define RGX_HWPERF_HW_CDMFINISHED 0x0EU /*!< CDM task finished */
#define RGX_HWPERF_HW_TLAKICK 0x0FU /*!< TLA task started */
#define RGX_HWPERF_HW_TLAFINISHED 0x10U /*!< TLS task finished */
#define RGX_HWPERF_HW_3DSPMKICK 0x11U /*!< 3D SPM task started */
#define RGX_HWPERF_HW_PERIODIC 0x12U /*!< Periodic event with updated HW counters */
#define RGX_HWPERF_HW_RTUKICK 0x13U /*!< Reserved, future use */
#define RGX_HWPERF_HW_RTUFINISHED 0x14U /*!< Reserved, future use */
#define RGX_HWPERF_HW_SHGKICK 0x15U /*!< Reserved, future use */
#define RGX_HWPERF_HW_SHGFINISHED 0x16U /*!< Reserved, future use */
#define RGX_HWPERF_HW_3DTQFINISHED 0x17U /*!< 3D TQ finished */
#define RGX_HWPERF_HW_3DSPMFINISHED 0x18U /*!< 3D SPM task finished */
#define RGX_HWPERF_HW_PMOOM_TARESUME 0x19U /*!< TA Resume after PM Out of Memory */
/*! HW_EVENT_RANGE0 used up. Use next empty range below to add new hardware events */
#define RGX_HWPERF_HW_EVENT_RANGE0_LAST_TYPE 0x19U
/*! other types 0x1A..0x1F */
#define RGX_HWPERF_CLKS_CHG 0x1AU /*!< Clock speed change in GPU */
#define RGX_HWPERF_GPU_STATE_CHG 0x1BU /*!< GPU work state change */
/*! power types 0x20..0x27 */
#define RGX_HWPERF_PWR_EST_RANGE_FIRST_TYPE 0x20U
#define RGX_HWPERF_PWR_EST_REQUEST 0x20U /*!< Power estimate requested (via GPIO) */
#define RGX_HWPERF_PWR_EST_READY 0x21U /*!< Power estimate inputs ready */
#define RGX_HWPERF_PWR_EST_RESULT 0x22U /*!< Power estimate result calculated */
#define RGX_HWPERF_PWR_EST_RANGE_LAST_TYPE 0x22U
#define RGX_HWPERF_PWR_CHG 0x23U /*!< Power state change */
/*! HW_EVENT_RANGE1 0x28..0x2F, for accommodating new hardware events */
#define RGX_HWPERF_HW_EVENT_RANGE1_FIRST_TYPE 0x28U
#define RGX_HWPERF_HW_TDMKICK 0x28U /*!< TDM task started */
#define RGX_HWPERF_HW_TDMFINISHED 0x29U /*!< TDM task finished */
#define RGX_HWPERF_HW_NULLKICK 0x2AU /*!< NULL event */
#define RGX_HWPERF_HW_EVENT_RANGE1_LAST_TYPE 0x2AU
/*! context switch types 0x30..0x31 */
#define RGX_HWPERF_CSW_START 0x30U /*!< HW context store started */
#define RGX_HWPERF_CSW_FINISHED 0x31U /*!< HW context store finished */
/*! DVFS events */
#define RGX_HWPERF_DVFS 0x32U /*!< Dynamic voltage/frequency scaling events */
/*! firmware misc 0x38..0x39 */
#define RGX_HWPERF_UFO 0x38U /*!< FW UFO Check / Update */
#define RGX_HWPERF_FWACT 0x39U /*!< FW Activity notification */
/*! last */
#define RGX_HWPERF_LAST_TYPE 0x3BU
/*! This enumeration must have a value that is a power of two as it is
* used in masks and a filter bit field (currently 64 bits long).
*/
#define RGX_HWPERF_MAX_TYPE 0x40U
static_assert(RGX_HWPERF_LAST_TYPE < RGX_HWPERF_MAX_TYPE, "Too many HWPerf event types");
/*! Macro used to check if an event type ID is present in the known set of hardware type events */
#define HWPERF_PACKET_IS_HW_TYPE(_etype) (((_etype) >= RGX_HWPERF_HW_EVENT_RANGE0_FIRST_TYPE && (_etype) <= RGX_HWPERF_HW_EVENT_RANGE0_LAST_TYPE) || \
((_etype) >= RGX_HWPERF_HW_EVENT_RANGE1_FIRST_TYPE && (_etype) <= RGX_HWPERF_HW_EVENT_RANGE1_LAST_TYPE))
/*! Macro used to check if an event type ID is present in the known set of firmware type events */
#define HWPERF_PACKET_IS_FW_TYPE(_etype) \
((_etype) >= RGX_HWPERF_FW_EVENT_RANGE_FIRST_TYPE && \
(_etype) <= RGX_HWPERF_FW_EVENT_RANGE_LAST_TYPE)
typedef enum {
RGX_HWPERF_HOST_INVALID = 0x00, /*!< Invalid, do not use. */
RGX_HWPERF_HOST_ENQ = 0x01, /*!< ``0x01`` Kernel driver has queued GPU work.
See RGX_HWPERF_HOST_ENQ_DATA */
RGX_HWPERF_HOST_UFO = 0x02, /*!< ``0x02`` UFO updated by the driver.
See RGX_HWPERF_HOST_UFO_DATA */
RGX_HWPERF_HOST_ALLOC = 0x03, /*!< ``0x03`` Resource allocated.
See RGX_HWPERF_HOST_ALLOC_DATA */
RGX_HWPERF_HOST_CLK_SYNC = 0x04, /*!< ``0x04`` GPU / Host clocks correlation data.
See RGX_HWPERF_HOST_CLK_SYNC_DATA */
RGX_HWPERF_HOST_FREE = 0x05, /*!< ``0x05`` Resource freed,
See RGX_HWPERF_HOST_FREE_DATA */
RGX_HWPERF_HOST_MODIFY = 0x06, /*!< ``0x06`` Resource modified / updated.
See RGX_HWPERF_HOST_MODIFY_DATA */
RGX_HWPERF_HOST_DEV_INFO = 0x07, /*!< ``0x07`` Device Health status.
See RGX_HWPERF_HOST_DEV_INFO_DATA */
RGX_HWPERF_HOST_INFO = 0x08, /*!< ``0x08`` Device memory usage information.
See RGX_HWPERF_HOST_INFO_DATA */
RGX_HWPERF_HOST_SYNC_FENCE_WAIT = 0x09, /*!< ``0x09`` Wait for sync event.
See RGX_HWPERF_HOST_SYNC_FENCE_WAIT_DATA */
RGX_HWPERF_HOST_SYNC_SW_TL_ADVANCE = 0x0A, /*!< ``0x0A`` Software timeline advanced.
See RGX_HWPERF_HOST_SYNC_SW_TL_ADV_DATA */
/*! last */
RGX_HWPERF_HOST_LAST_TYPE,
/*! This enumeration must have a value that is a power of two as it is
* used in masks and a filter bit field (currently 32 bits long).
*/
RGX_HWPERF_HOST_MAX_TYPE = 0x20
} RGX_HWPERF_HOST_EVENT_TYPE;
/*!< The event type values are incrementing integers for use as a shift ordinal
* in the event filtering process at the point events are generated.
* This scheme thus implies a limit of 31 event types.
*/
static_assert(RGX_HWPERF_HOST_LAST_TYPE < RGX_HWPERF_HOST_MAX_TYPE, "Too many HWPerf host event types");
/******************************************************************************
* Packet Header Format Version 2 Types
*****************************************************************************/
/*! Major version number of the protocol in operation
*/
#define RGX_HWPERF_V2_FORMAT 2
/*! Signature ASCII pattern 'HWP2' found in the first word of a HWPerfV2 packet
*/
#define HWPERF_PACKET_V2_SIG 0x48575032
/*! Signature ASCII pattern 'HWPA' found in the first word of a HWPerfV2a packet
*/
#define HWPERF_PACKET_V2A_SIG 0x48575041
/*! Signature ASCII pattern 'HWPB' found in the first word of a HWPerfV2b packet
*/
#define HWPERF_PACKET_V2B_SIG 0x48575042
/*! Signature ASCII pattern 'HWPC' found in the first word of a HWPerfV2c packet
*/
#define HWPERF_PACKET_V2C_SIG 0x48575043
#define HWPERF_PACKET_ISVALID(_val) (((_val) == HWPERF_PACKET_V2_SIG) || ((_val) == HWPERF_PACKET_V2A_SIG) || ((_val) == HWPERF_PACKET_V2B_SIG) || ((_val) == HWPERF_PACKET_V2C_SIG))
/*!< Checks that the packet signature is one of the supported versions */
/*! Type defines the HWPerf packet header common to all events. */
typedef struct
{
IMG_UINT32 ui32Sig; /*!< Always the value HWPERF_PACKET_SIG */
IMG_UINT32 ui32Size; /*!< Overall packet size in bytes */
IMG_UINT32 eTypeId; /*!< Event type information field */
IMG_UINT32 ui32Ordinal; /*!< Sequential number of the packet */
IMG_UINT64 ui64Timestamp; /*!< Event timestamp */
} RGX_HWPERF_V2_PACKET_HDR, *RGX_PHWPERF_V2_PACKET_HDR;
RGX_FW_STRUCT_OFFSET_ASSERT(RGX_HWPERF_V2_PACKET_HDR, ui64Timestamp);
RGX_FW_STRUCT_SIZE_ASSERT(RGX_HWPERF_V2_PACKET_HDR);
/*! Mask for use with the IMG_UINT32 ui32Size header field */
#define RGX_HWPERF_SIZE_MASK 0xFFFFU
/*! This macro defines an upper limit to which the size of the largest variable
* length HWPerf packet must fall within, currently 3KB. This constant may be
* used to allocate a buffer to hold one packet.
* This upper limit is policed by packet producing code.
*/
#define RGX_HWPERF_MAX_PACKET_SIZE 0xC00U
/*! Defines an upper limit to the size of a variable length packet payload.
*/
#define RGX_HWPERF_MAX_PAYLOAD_SIZE ((IMG_UINT32)(RGX_HWPERF_MAX_PACKET_SIZE-\
sizeof(RGX_HWPERF_V2_PACKET_HDR)))
/*! Macro which takes a structure name and provides the packet size for
* a fixed size payload packet, rounded up to 8 bytes to align packets
* for 64 bit architectures. */
#define RGX_HWPERF_MAKE_SIZE_FIXED(_struct) ((IMG_UINT32)(RGX_HWPERF_SIZE_MASK&(sizeof(RGX_HWPERF_V2_PACKET_HDR)+PVR_ALIGN(sizeof(_struct), PVRSRVTL_PACKET_ALIGNMENT))))
/*! Macro which takes the number of bytes written in the data payload of a
* packet for a variable size payload packet, rounded up to 8 bytes to
* align packets for 64 bit architectures. */
#define RGX_HWPERF_MAKE_SIZE_VARIABLE(_size) ((IMG_UINT32)(RGX_HWPERF_SIZE_MASK&(sizeof(RGX_HWPERF_V2_PACKET_HDR)+PVR_ALIGN((_size), PVRSRVTL_PACKET_ALIGNMENT))))
/*! Macro to obtain the size of the packet */
#define RGX_HWPERF_GET_SIZE(_packet_addr) ((IMG_UINT16)(((_packet_addr)->ui32Size) & RGX_HWPERF_SIZE_MASK))
/*! Macro to obtain the size of the packet data */
#define RGX_HWPERF_GET_DATA_SIZE(_packet_addr) (RGX_HWPERF_GET_SIZE(_packet_addr) - sizeof(RGX_HWPERF_V2_PACKET_HDR))
/*! Masks for use with the IMG_UINT32 eTypeId header field */
#define RGX_HWPERF_TYPEID_MASK 0x0007FFFFU
#define RGX_HWPERF_TYPEID_EVENT_MASK 0x00007FFFU
#define RGX_HWPERF_TYPEID_THREAD_MASK 0x00008000U
#define RGX_HWPERF_TYPEID_STREAM_MASK 0x00070000U
#define RGX_HWPERF_TYPEID_META_DMA_MASK 0x00080000U
#define RGX_HWPERF_TYPEID_M_CORE_MASK 0x00100000U
#define RGX_HWPERF_TYPEID_OSID_MASK 0x07000000U
/*! Meta thread macros for encoding the ID into the type field of a packet */
#define RGX_HWPERF_META_THREAD_SHIFT 15U
#define RGX_HWPERF_META_THREAD_ID0 0x0U /*!< Meta Thread 0 ID */
#define RGX_HWPERF_META_THREAD_ID1 0x1U /*!< Meta Thread 1 ID */
/*! Obsolete, kept for source compatibility */
#define RGX_HWPERF_META_THREAD_MASK 0x1U
/*! Stream ID macros for encoding the ID into the type field of a packet */
#define RGX_HWPERF_STREAM_SHIFT 16U
/*! Meta DMA macro for encoding how the packet was generated into the type field of a packet */
#define RGX_HWPERF_META_DMA_SHIFT 19U
/*! Bit-shift macro used for encoding multi-core data into the type field of a packet */
#define RGX_HWPERF_M_CORE_SHIFT 20U
/*! OSID bit-shift macro used for encoding OSID into type field of a packet */
#define RGX_HWPERF_OSID_SHIFT 24U
typedef enum {
RGX_HWPERF_STREAM_ID0_FW, /*!< Events from the Firmware/GPU */
RGX_HWPERF_STREAM_ID1_HOST, /*!< Events from the Server host driver component */
RGX_HWPERF_STREAM_ID2_CLIENT, /*!< Events from the Client host driver component */
RGX_HWPERF_STREAM_ID_LAST,
} RGX_HWPERF_STREAM_ID;
/* Checks if all stream IDs can fit under RGX_HWPERF_TYPEID_STREAM_MASK. */
static_assert(((IMG_UINT32)RGX_HWPERF_STREAM_ID_LAST - 1U) < (RGX_HWPERF_TYPEID_STREAM_MASK >> RGX_HWPERF_STREAM_SHIFT),
"Too many HWPerf stream IDs.");
/*! Compile-time value used to seed the Multi-Core (MC) bit in the typeID field.
* Only set by RGX_FIRMWARE builds.
*/
#if defined(RGX_FIRMWARE)
# if defined(RGX_FEATURE_GPU_MULTICORE_SUPPORT)
#define RGX_HWPERF_M_CORE_VALUE 1U /*!< 1 => Multi-core supported */
# else
#define RGX_HWPERF_M_CORE_VALUE 0U /*!< 0 => Multi-core not supported */
# endif
#else
#define RGX_HWPERF_M_CORE_VALUE 0U /*!< 0 => Multi-core not supported */
#endif
/*! Macros used to set the packet type and encode meta thread ID (0|1),
* HWPerf stream ID, multi-core capability and OSID within the typeID */
#define RGX_HWPERF_MAKE_TYPEID(_stream, _type, _thread, _metadma, _osid)\
((IMG_UINT32) ((RGX_HWPERF_TYPEID_STREAM_MASK&((IMG_UINT32)(_stream) << RGX_HWPERF_STREAM_SHIFT)) | \
(RGX_HWPERF_TYPEID_THREAD_MASK & ((IMG_UINT32)(_thread) << RGX_HWPERF_META_THREAD_SHIFT)) | \
(RGX_HWPERF_TYPEID_EVENT_MASK & (IMG_UINT32)(_type)) | \
(RGX_HWPERF_TYPEID_META_DMA_MASK & ((IMG_UINT32)(_metadma) << RGX_HWPERF_META_DMA_SHIFT)) | \
(RGX_HWPERF_TYPEID_OSID_MASK & ((IMG_UINT32)(_osid) << RGX_HWPERF_OSID_SHIFT)) | \
(RGX_HWPERF_TYPEID_M_CORE_MASK & ((IMG_UINT32)(RGX_HWPERF_M_CORE_VALUE) << RGX_HWPERF_M_CORE_SHIFT))))
/*! Obtains the event type that generated the packet */
#define RGX_HWPERF_GET_TYPE(_packet_addr) (((_packet_addr)->eTypeId) & RGX_HWPERF_TYPEID_EVENT_MASK)
/*! Obtains the META Thread number that generated the packet */
#define RGX_HWPERF_GET_THREAD_ID(_packet_addr) (((((_packet_addr)->eTypeId) & RGX_HWPERF_TYPEID_THREAD_MASK) >> RGX_HWPERF_META_THREAD_SHIFT))
/*! Determines if the packet generated contains multi-core data */
#define RGX_HWPERF_GET_M_CORE(_packet_addr) (((_packet_addr)->eTypeId & RGX_HWPERF_TYPEID_M_CORE_MASK) >> RGX_HWPERF_M_CORE_SHIFT)
/*! Obtains the guest OSID which resulted in packet generation */
#define RGX_HWPERF_GET_OSID(_packet_addr) (((_packet_addr)->eTypeId & RGX_HWPERF_TYPEID_OSID_MASK) >> RGX_HWPERF_OSID_SHIFT)
/*! Obtain stream id */
#define RGX_HWPERF_GET_STREAM_ID(_packet_addr) (((((_packet_addr)->eTypeId) & RGX_HWPERF_TYPEID_STREAM_MASK) >> RGX_HWPERF_STREAM_SHIFT))
/*! Obtain information about how the packet was generated, which might affect payload total size */
#define RGX_HWPERF_GET_META_DMA_INFO(_packet_addr) (((((_packet_addr)->eTypeId) & RGX_HWPERF_TYPEID_META_DMA_MASK) >> RGX_HWPERF_META_DMA_SHIFT))
/*! Obtains a typed pointer to a packet given a buffer address */
#define RGX_HWPERF_GET_PACKET(_buffer_addr) ((RGX_HWPERF_V2_PACKET_HDR *)(void *) (_buffer_addr))
/*! Obtains a typed pointer to a data structure given a packet address */
#define RGX_HWPERF_GET_PACKET_DATA_BYTES(_packet_addr) (IMG_OFFSET_ADDR((_packet_addr), sizeof(RGX_HWPERF_V2_PACKET_HDR)))
/*! Obtains a typed pointer to the next packet given a packet address */
#define RGX_HWPERF_GET_NEXT_PACKET(_packet_addr) ((RGX_HWPERF_V2_PACKET_HDR *) (IMG_OFFSET_ADDR((_packet_addr), RGX_HWPERF_SIZE_MASK&((_packet_addr)->ui32Size))))
/*! Obtains a typed pointer to a packet header given the packet data address */
#define RGX_HWPERF_GET_PACKET_HEADER(_packet_addr) ((RGX_HWPERF_V2_PACKET_HDR *) (IMG_OFFSET_ADDR((_packet_addr), -(IMG_INT32)sizeof(RGX_HWPERF_V2_PACKET_HDR))))
/******************************************************************************
* Other Common Defines
*****************************************************************************/
/*! This macro is not a real array size, but indicates the array has a variable
* length only known at run-time but always contains at least 1 element. The
* final size of the array is deduced from the size field of a packet header.
*/
#define RGX_HWPERF_ONE_OR_MORE_ELEMENTS 1U
/*! This macro is not a real array size, but indicates the array is optional
* and if present has a variable length only known at run-time. The final
* size of the array is deduced from the size field of a packet header. */
#define RGX_HWPERF_ZERO_OR_MORE_ELEMENTS 1U
/*! Masks for use with the IMG_UINT32 ui32BlkInfo field */
#define RGX_HWPERF_BLKINFO_BLKCOUNT_MASK 0xFFFF0000U
#define RGX_HWPERF_BLKINFO_BLKOFFSET_MASK 0x0000FFFFU
/*! Shift for the NumBlocks and counter block offset field in ui32BlkInfo */
#define RGX_HWPERF_BLKINFO_BLKCOUNT_SHIFT 16U
#define RGX_HWPERF_BLKINFO_BLKOFFSET_SHIFT 0U
/*! Macro used to set the block info word as a combination of two 16-bit integers */
#define RGX_HWPERF_MAKE_BLKINFO(_numblks, _blkoffset) ((IMG_UINT32) ((RGX_HWPERF_BLKINFO_BLKCOUNT_MASK&((_numblks) << RGX_HWPERF_BLKINFO_BLKCOUNT_SHIFT)) | (RGX_HWPERF_BLKINFO_BLKOFFSET_MASK&((_blkoffset) << RGX_HWPERF_BLKINFO_BLKOFFSET_SHIFT))))
/*! Macro used to obtain the number of counter blocks present in the packet */
#define RGX_HWPERF_GET_BLKCOUNT(_blkinfo) (((_blkinfo) & RGX_HWPERF_BLKINFO_BLKCOUNT_MASK) >> RGX_HWPERF_BLKINFO_BLKCOUNT_SHIFT)
/*! Obtains the offset of the counter block stream in the packet */
#define RGX_HWPERF_GET_BLKOFFSET(_blkinfo) (((_blkinfo) & RGX_HWPERF_BLKINFO_BLKOFFSET_MASK) >> RGX_HWPERF_BLKINFO_BLKOFFSET_SHIFT)
/*! This macro gets the number of blocks depending on the packet version */
#define RGX_HWPERF_GET_NUMBLKS(_sig, _packet_data, _numblocks) \
do { \
if (HWPERF_PACKET_V2B_SIG == _sig || HWPERF_PACKET_V2C_SIG == _sig) \
{ \
(_numblocks) = RGX_HWPERF_GET_BLKCOUNT((_packet_data)->ui32BlkInfo);\
} \
else \
{ \
IMG_UINT32 ui32VersionOffset = (((_sig) == HWPERF_PACKET_V2_SIG) ? 1 : 3);\
(_numblocks) = *(IMG_UINT16 *)(IMG_OFFSET_ADDR(&(_packet_data)->ui32WorkTarget, ui32VersionOffset)); \
} \
} while (0)
/*! This macro gets the counter stream pointer depending on the packet version */
#define RGX_HWPERF_GET_CNTSTRM(_sig, _hw_packet_data, _cntstream_ptr) \
{ \
if (HWPERF_PACKET_V2B_SIG == _sig || HWPERF_PACKET_V2C_SIG == _sig) \
{ \
(_cntstream_ptr) = (IMG_UINT32 *)(IMG_OFFSET_ADDR((_hw_packet_data), RGX_HWPERF_GET_BLKOFFSET((_hw_packet_data)->ui32BlkInfo))); \
} \
else \
{ \
IMG_UINT32 ui32BlkStreamOffsetInWords = ((_sig == HWPERF_PACKET_V2_SIG) ? 6 : 8); \
(_cntstream_ptr) = (IMG_UINT32 *)(IMG_OFFSET_ADDR((_hw_packet_data), ui32BlkStreamOffsetInWords)); \
} \
}
/*! Masks for use with the RGX_HWPERF_UFO_EV eEvType field */
#define RGX_HWPERF_UFO_STREAMSIZE_MASK 0xFFFF0000U
#define RGX_HWPERF_UFO_STREAMOFFSET_MASK 0x0000FFFFU
/*! Shift for the UFO count and data stream fields */
#define RGX_HWPERF_UFO_STREAMSIZE_SHIFT 16U
#define RGX_HWPERF_UFO_STREAMOFFSET_SHIFT 0U
/*! Macro used to set UFO stream info word as a combination of two 16-bit integers */
#define RGX_HWPERF_MAKE_UFOPKTINFO(_ssize, _soff) \
((IMG_UINT32) ((RGX_HWPERF_UFO_STREAMSIZE_MASK&((_ssize) << RGX_HWPERF_UFO_STREAMSIZE_SHIFT)) | \
(RGX_HWPERF_UFO_STREAMOFFSET_MASK&((_soff) << RGX_HWPERF_UFO_STREAMOFFSET_SHIFT))))
/*! Macro used to obtain UFO count*/
#define RGX_HWPERF_GET_UFO_STREAMSIZE(_streaminfo) \
(((_streaminfo) & RGX_HWPERF_UFO_STREAMSIZE_MASK) >> RGX_HWPERF_UFO_STREAMSIZE_SHIFT)
/*! Obtains the offset of the UFO stream in the packet */
#define RGX_HWPERF_GET_UFO_STREAMOFFSET(_streaminfo) \
(((_streaminfo) & RGX_HWPERF_UFO_STREAMOFFSET_MASK) >> RGX_HWPERF_UFO_STREAMOFFSET_SHIFT)
/******************************************************************************
* Data Stream Common Types
@@ -496,17 +103,20 @@ typedef enum {
/*! Enum containing bit position for 32bit feature flags used in hwperf and api */
typedef enum {
RGX_HWPERF_FEATURE_PERFBUS_FLAG = 0x001,
RGX_HWPERF_FEATURE_S7_TOP_INFRASTRUCTURE_FLAG = 0x002,
RGX_HWPERF_FEATURE_XT_TOP_INFRASTRUCTURE_FLAG = 0x004,
RGX_HWPERF_FEATURE_PERF_COUNTER_BATCH_FLAG = 0x008,
RGX_HWPERF_FEATURE_ROGUEXE_FLAG = 0x010,
RGX_HWPERF_FEATURE_DUST_POWER_ISLAND_S7_FLAG = 0x020,
RGX_HWPERF_FEATURE_PBE2_IN_XE_FLAG = 0x040,
RGX_HWPERF_FEATURE_WORKLOAD_ESTIMATION = 0x080,
RGX_HWPERF_FEATURE_MULTICORE_FLAG = 0x100,
RGX_HWPERF_FEATURE_RAYTRACING_FLAG = 0x200,
RGX_HWPERF_FEATURE_CXT_TOP_INFRASTRUCTURE_FLAG = 0x400
RGX_HWPERF_FEATURE_PERFBUS_FLAG = 0x0001,
RGX_HWPERF_FEATURE_S7_TOP_INFRASTRUCTURE_FLAG = 0x0002,
RGX_HWPERF_FEATURE_XT_TOP_INFRASTRUCTURE_FLAG = 0x0004,
RGX_HWPERF_FEATURE_PERF_COUNTER_BATCH_FLAG = 0x0008,
RGX_HWPERF_FEATURE_ROGUEXE_FLAG = 0x0010,
RGX_HWPERF_FEATURE_DUST_POWER_ISLAND_S7_FLAG = 0x0020,
RGX_HWPERF_FEATURE_PBE2_IN_XE_FLAG = 0x0040,
RGX_HWPERF_FEATURE_WORKLOAD_ESTIMATION = 0x0080,
RGX_HWPERF_FEATURE_MULTICORE_FLAG = 0x0100,
RGX_HWPERF_FEATURE_RAYTRACING_FLAG = 0x0200,
RGX_HWPERF_FEATURE_CXT_TOP_INFRASTRUCTURE_FLAG = 0x0400,
RGX_HWPERF_FEATURE_VOLCANIC_FLAG = 0x0800,
RGX_HWPERF_FEATURE_ROGUE_FLAG = 0x1000,
RGX_HWPERF_FEATURE_OCEANIC_FLAG = 0x2000
} RGX_HWPERF_FEATURE_FLAGS;
/*! This structure holds the data of a firmware packet. */
@@ -537,11 +147,14 @@ typedef struct
IMG_UINT32 ui32WorkCtx; /*!< Work context: Render Context for TA/3D; RayTracing Context for RTU/SHG; 0x0 otherwise */
IMG_UINT32 ui32CtxPriority; /*!< Context priority */
IMG_UINT32 ui32GPUIdMask; /*!< GPU IDs active within this event */
IMG_UINT32 aui32CountBlksStream[RGX_HWPERF_ZERO_OR_MORE_ELEMENTS]; /*!< Counter data */
IMG_UINT32 ui32Padding2; /*!< Reserved. To ensure correct alignment */
IMG_UINT32 ui32KickInfo; /*!< <31..8> Reserved <7..0> GPU Pipeline DM kick ID, 0 if not using Pipeline DMs */
IMG_UINT32 ui32Padding; /*!< Reserved. To ensure correct alignment */
IMG_UINT32 aui32CountBlksStream[RGX_HWPERF_ZERO_OR_MORE_ELEMENTS]; /*!< Optional variable length Counter data */
IMG_UINT32 ui32Padding2; /*!< Reserved. To ensure correct alignment (not written in the packet) */
} RGX_HWPERF_HW_DATA;
RGX_FW_STRUCT_SIZE_ASSERT(RGX_HWPERF_HW_DATA);
RGX_FW_STRUCT_OFFSET_ASSERT(RGX_HWPERF_HW_DATA, aui32CountBlksStream);
/*! Mask for use with the aui32CountBlksStream field when decoding the
* counter block ID and mask word. */
@@ -549,11 +162,7 @@ RGX_FW_STRUCT_SIZE_ASSERT(RGX_HWPERF_HW_DATA);
#define RGX_HWPERF_CNTBLK_ID_SHIFT 16U
/*! MAX value used in server handling of counter config arrays */
#if defined(SUPPORT_VALIDATION)
#define RGX_CNTBLK_COUNTERS_MAX 64
#else
#define RGX_CNTBLK_COUNTERS_MAX 12
#endif
#define RGX_CNTBLK_COUNTERS_MAX PVRSRV_HWPERF_COUNTERS_PERBLK
/*! Obtains the counter block ID word from an aui32CountBlksStream field.
@@ -957,12 +566,14 @@ RGX_FW_STRUCT_SIZE_ASSERT(RGX_HWPERF_UFO_DATA);
*/
typedef enum
{
RGX_HWPERF_KICK_TYPE_TA3D, /*!< TA 3D Kick */
RGX_HWPERF_KICK_TYPE_TA3D, /*!< Replaced by separate TA and 3D types */
RGX_HWPERF_KICK_TYPE_CDM, /*!< Compute Data Master Kick */
RGX_HWPERF_KICK_TYPE_RS, /*!< Ray Store Kick */
RGX_HWPERF_KICK_TYPE_SHG, /*!< Scene Hierarchy Generator Kick */
RGX_HWPERF_KICK_TYPE_TQTDM, /*!< TQ 2D Data Master Kick */
RGX_HWPERF_KICK_TYPE_SYNC, /*!< Sync Kick */
RGX_HWPERF_KICK_TYPE_TA, /*!< TA Kick */
RGX_HWPERF_KICK_TYPE_3D, /*!< 3D Kick */
RGX_HWPERF_KICK_TYPE_LAST,
RGX_HWPERF_KICK_TYPE_FORCE_32BIT = 0x7fffffff
@@ -1395,6 +1006,49 @@ typedef struct
static_assert((sizeof(RGX_HWPERF_HOST_SYNC_SW_TL_ADV_DATA) & (PVRSRVTL_PACKET_ALIGNMENT-1U)) == 0U,
"sizeof(RGX_HWPERF_HOST_SYNC_SW_TL_ADV_DATA) must be a multiple PVRSRVTL_PACKET_ALIGNMENT");
typedef enum
{
RGX_HWPERF_HOST_CLIENT_INFO_TYPE_INVALID = 0, /*!< Invalid */
RGX_HWPERF_HOST_CLIENT_INFO_TYPE_PROCESS_NAME, /*!< Process Name */
RGX_HWPERF_HOST_CLIENT_INFO_TYPE_LAST, /*!< Do not use */
} RGX_HWPERF_HOST_CLIENT_INFO_TYPE;
typedef struct
{
IMG_PID uiClientPID; /*!< Client process identifier */
IMG_UINT32 ui32Length; /*!< Number of bytes present in ``acName`` */
IMG_CHAR acName[RGX_HWPERF_ONE_OR_MORE_ELEMENTS]; /*!< Process name string, null terminated */
} RGX_HWPERF_HOST_CLIENT_PROC_NAME;
#define RGX_HWPERF_HOST_CLIENT_PROC_NAME_SIZE(ui32NameLen) \
((IMG_UINT32)(offsetof(RGX_HWPERF_HOST_CLIENT_PROC_NAME, acName) + (ui32NameLen)))
typedef union
{
struct
{
IMG_UINT32 ui32Count; /*!< Number of elements in ``asProcNames`` */
RGX_HWPERF_HOST_CLIENT_PROC_NAME asProcNames[RGX_HWPERF_ONE_OR_MORE_ELEMENTS];
} sProcName;
} RGX_HWPERF_HOST_CLIENT_INFO_DETAIL;
typedef struct
{
IMG_UINT32 uiReserved1; /*!< Reserved. Align structure size to 8 bytes */
RGX_HWPERF_HOST_CLIENT_INFO_TYPE eType;
/*!< Type of the subevent, see
RGX_HWPERF_HOST_CLIENT_INFO_TYPE */
RGX_HWPERF_HOST_CLIENT_INFO_DETAIL uDetail;
/*!< Union of structures. Size of data
varies with union member that is present,
check ``eType`` value to decode */
} RGX_HWPERF_HOST_CLIENT_INFO_DATA;
static_assert((sizeof(RGX_HWPERF_HOST_CLIENT_INFO_DATA) & (PVRSRVTL_PACKET_ALIGNMENT-1U)) == 0U,
"sizeof(RGX_HWPERF_HOST_CLIENT_INFO_DATA) must be a multiple PVRSRVTL_PACKET_ALIGNMENT");
typedef enum
{
RGX_HWPERF_RESOURCE_CAPTURE_TYPE_NONE,
@@ -1480,7 +1134,8 @@ typedef union
RGX_HWPERF_FW_DATA sFW; /*!< Firmware event packet data,
events ``0x01-0x06`` */
RGX_HWPERF_HW_DATA sHW; /*!< Hardware event packet data,
events ``0x07-0x19``, ``0x28-0x29`` */
events ``0x07-0x19``, ``0x28-0x29``
See RGX_HWPERF_HW_DATA */
RGX_HWPERF_CLKS_CHG_DATA sCLKSCHG; /*!< Clock change event packet
data, events ``0x1A`` */
RGX_HWPERF_GPU_STATE_CHG_DATA sGPUSTATECHG; /*!< GPU utilisation state
@@ -1520,6 +1175,8 @@ typedef union
events ``0x09`` (Host) */
RGX_HWPERF_HOST_SYNC_SW_TL_ADV_DATA sSWTLADV; /*!< Host SW-timeline advance
data, events ``0x0A`` (Host) */
RGX_HWPERF_HOST_CLIENT_INFO_DATA sHClientInfo; /*!< Host client info,
events ``0x0B`` (Host) */
} RGX_HWPERF_V2_PACKET_DATA, *RGX_PHWPERF_V2_PACKET_DATA;
RGX_FW_STRUCT_SIZE_ASSERT(RGX_HWPERF_V2_PACKET_DATA);

11
drivers/gpu/drm/img-rogue/kernel_compatibility.h
View File

@@ -507,4 +507,15 @@ struct dma_buf_map {
#endif /* (LINUX_VERSION_CODE < KERNEL_VERSION(5, 13, 0)) */
/*
* Linux 5.11 renames the privileged uaccess routines for arm64 and Android
* kernel v5.10 merges the change as well. These routines are only used for
* arm64 so CONFIG_ARM64 testing can be ignored.
*/
#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 10, 0)) || \
((LINUX_VERSION_CODE < KERNEL_VERSION(5, 11, 0)) && !defined(ANDROID))
#define uaccess_enable_privileged() uaccess_enable()
#define uaccess_disable_privileged() uaccess_disable()
#endif
#endif /* __KERNEL_COMPATIBILITY_H__ */

76
drivers/gpu/drm/img-rogue/km/rgx_bvnc_defs_km.h
View File

@@ -177,53 +177,59 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define RGX_FEATURE_SLC_VIVT_POS (37U)
#define RGX_FEATURE_SLC_VIVT_BIT_MASK (IMG_UINT64_C(0x0000002000000000))
#define RGX_FEATURE_SYS_BUS_SECURE_RESET_POS (38U)
#define RGX_FEATURE_SYS_BUS_SECURE_RESET_BIT_MASK (IMG_UINT64_C(0x0000004000000000))
#define RGX_FEATURE_SOC_TIMER_POS (38U)
#define RGX_FEATURE_SOC_TIMER_BIT_MASK (IMG_UINT64_C(0x0000004000000000))
#define RGX_FEATURE_TDM_PDS_CHECKSUM_POS (39U)
#define RGX_FEATURE_TDM_PDS_CHECKSUM_BIT_MASK (IMG_UINT64_C(0x0000008000000000))
#define RGX_FEATURE_SYS_BUS_SECURE_RESET_POS (39U)
#define RGX_FEATURE_SYS_BUS_SECURE_RESET_BIT_MASK (IMG_UINT64_C(0x0000008000000000))
#define RGX_FEATURE_TESSELLATION_POS (40U)
#define RGX_FEATURE_TESSELLATION_BIT_MASK (IMG_UINT64_C(0x0000010000000000))
#define RGX_FEATURE_TDM_PDS_CHECKSUM_POS (40U)
#define RGX_FEATURE_TDM_PDS_CHECKSUM_BIT_MASK (IMG_UINT64_C(0x0000010000000000))
#define RGX_FEATURE_TFBC_DELTA_CORRELATION_POS (41U)
#define RGX_FEATURE_TFBC_DELTA_CORRELATION_BIT_MASK (IMG_UINT64_C(0x0000020000000000))
#define RGX_FEATURE_TESSELLATION_POS (41U)
#define RGX_FEATURE_TESSELLATION_BIT_MASK (IMG_UINT64_C(0x0000020000000000))
#define RGX_FEATURE_TFBC_LOSSY_37_PERCENT_POS (42U)
#define RGX_FEATURE_TFBC_LOSSY_37_PERCENT_BIT_MASK (IMG_UINT64_C(0x0000040000000000))
#define RGX_FEATURE_TFBC_DELTA_CORRELATION_POS (42U)
#define RGX_FEATURE_TFBC_DELTA_CORRELATION_BIT_MASK (IMG_UINT64_C(0x0000040000000000))
#define RGX_FEATURE_TFBC_NATIVE_YUV10_POS (43U)
#define RGX_FEATURE_TFBC_NATIVE_YUV10_BIT_MASK (IMG_UINT64_C(0x0000080000000000))
#define RGX_FEATURE_TFBC_LOSSY_37_PERCENT_POS (43U)
#define RGX_FEATURE_TFBC_LOSSY_37_PERCENT_BIT_MASK (IMG_UINT64_C(0x0000080000000000))
#define RGX_FEATURE_TILE_REGION_PROTECTION_POS (44U)
#define RGX_FEATURE_TILE_REGION_PROTECTION_BIT_MASK (IMG_UINT64_C(0x0000100000000000))
#define RGX_FEATURE_TFBC_NATIVE_YUV10_POS (44U)
#define RGX_FEATURE_TFBC_NATIVE_YUV10_BIT_MASK (IMG_UINT64_C(0x0000100000000000))
#define RGX_FEATURE_TLA_POS (45U)
#define RGX_FEATURE_TLA_BIT_MASK (IMG_UINT64_C(0x0000200000000000))
#define RGX_FEATURE_TILE_REGION_PROTECTION_POS (45U)
#define RGX_FEATURE_TILE_REGION_PROTECTION_BIT_MASK (IMG_UINT64_C(0x0000200000000000))
#define RGX_FEATURE_TPU_CEM_DATAMASTER_GLOBAL_REGISTERS_POS (46U)
#define RGX_FEATURE_TPU_CEM_DATAMASTER_GLOBAL_REGISTERS_BIT_MASK (IMG_UINT64_C(0x0000400000000000))
#define RGX_FEATURE_TLA_POS (46U)
#define RGX_FEATURE_TLA_BIT_MASK (IMG_UINT64_C(0x0000400000000000))
#define RGX_FEATURE_TPU_DM_GLOBAL_REGISTERS_POS (47U)
#define RGX_FEATURE_TPU_DM_GLOBAL_REGISTERS_BIT_MASK (IMG_UINT64_C(0x0000800000000000))
#define RGX_FEATURE_TPU_CEM_DATAMASTER_GLOBAL_REGISTERS_POS (47U)
#define RGX_FEATURE_TPU_CEM_DATAMASTER_GLOBAL_REGISTERS_BIT_MASK (IMG_UINT64_C(0x0000800000000000))
#define RGX_FEATURE_TPU_FILTERING_MODE_CONTROL_POS (48U)
#define RGX_FEATURE_TPU_FILTERING_MODE_CONTROL_BIT_MASK (IMG_UINT64_C(0x0001000000000000))
#define RGX_FEATURE_TPU_DM_GLOBAL_REGISTERS_POS (48U)
#define RGX_FEATURE_TPU_DM_GLOBAL_REGISTERS_BIT_MASK (IMG_UINT64_C(0x0001000000000000))
#define RGX_FEATURE_VDM_DRAWINDIRECT_POS (49U)
#define RGX_FEATURE_VDM_DRAWINDIRECT_BIT_MASK (IMG_UINT64_C(0x0002000000000000))
#define RGX_FEATURE_TPU_FILTERING_MODE_CONTROL_POS (49U)
#define RGX_FEATURE_TPU_FILTERING_MODE_CONTROL_BIT_MASK (IMG_UINT64_C(0x0002000000000000))
#define RGX_FEATURE_VDM_OBJECT_LEVEL_LLS_POS (50U)
#define RGX_FEATURE_VDM_OBJECT_LEVEL_LLS_BIT_MASK (IMG_UINT64_C(0x0004000000000000))
#define RGX_FEATURE_VDM_DRAWINDIRECT_POS (50U)
#define RGX_FEATURE_VDM_DRAWINDIRECT_BIT_MASK (IMG_UINT64_C(0x0004000000000000))
#define RGX_FEATURE_WATCHDOG_TIMER_POS (51U)
#define RGX_FEATURE_WATCHDOG_TIMER_BIT_MASK (IMG_UINT64_C(0x0008000000000000))
#define RGX_FEATURE_VDM_OBJECT_LEVEL_LLS_POS (51U)
#define RGX_FEATURE_VDM_OBJECT_LEVEL_LLS_BIT_MASK (IMG_UINT64_C(0x0008000000000000))
#define RGX_FEATURE_XE_MEMORY_HIERARCHY_POS (52U)
#define RGX_FEATURE_XE_MEMORY_HIERARCHY_BIT_MASK (IMG_UINT64_C(0x0010000000000000))
#define RGX_FEATURE_WATCHDOG_TIMER_POS (52U)
#define RGX_FEATURE_WATCHDOG_TIMER_BIT_MASK (IMG_UINT64_C(0x0010000000000000))
#define RGX_FEATURE_XT_TOP_INFRASTRUCTURE_POS (53U)
#define RGX_FEATURE_XT_TOP_INFRASTRUCTURE_BIT_MASK (IMG_UINT64_C(0x0020000000000000))
#define RGX_FEATURE_WORKGROUP_PROTECTION_POS (53U)
#define RGX_FEATURE_WORKGROUP_PROTECTION_BIT_MASK (IMG_UINT64_C(0x0020000000000000))
#define RGX_FEATURE_XE_MEMORY_HIERARCHY_POS (54U)
#define RGX_FEATURE_XE_MEMORY_HIERARCHY_BIT_MASK (IMG_UINT64_C(0x0040000000000000))
#define RGX_FEATURE_XT_TOP_INFRASTRUCTURE_POS (55U)
#define RGX_FEATURE_XT_TOP_INFRASTRUCTURE_BIT_MASK (IMG_UINT64_C(0x0080000000000000))
/******************************************************************************
@@ -236,6 +242,8 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define RGX_FEATURE_FBCDC_MAX_VALUE_IDX (4)
#define RGX_FEATURE_FBCDC_ALGORITHM_MAX_VALUE_IDX (6)
#define RGX_FEATURE_FBCDC_ARCHITECTURE_MAX_VALUE_IDX (4)
#define RGX_FEATURE_FBC_MAX_DEFAULT_DESCRIPTORS_MAX_VALUE_IDX (2)
#define RGX_FEATURE_FBC_MAX_LARGE_DESCRIPTORS_MAX_VALUE_IDX (2)
#define RGX_FEATURE_LAYOUT_MARS_MAX_VALUE_IDX (3)
#define RGX_FEATURE_META_MAX_VALUE_IDX (4)
#define RGX_FEATURE_META_COREMEM_BANKS_MAX_VALUE_IDX (1)
@@ -255,6 +263,7 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define RGX_FEATURE_TILE_SIZE_X_MAX_VALUE_IDX (3)
#define RGX_FEATURE_TILE_SIZE_Y_MAX_VALUE_IDX (3)
#define RGX_FEATURE_VIRTUAL_ADDRESS_SPACE_BITS_MAX_VALUE_IDX (2)
#define RGX_FEATURE_XE_ARCHITECTURE_MAX_VALUE_IDX (2)
#define RGX_FEATURE_XPU_MAX_REGBANKS_ADDR_WIDTH_MAX_VALUE_IDX (2)
#define RGX_FEATURE_XPU_MAX_SLAVES_MAX_VALUE_IDX (2)
#define RGX_FEATURE_XPU_REGISTER_BROADCAST_MAX_VALUE_IDX (2)
@@ -269,6 +278,8 @@ typedef enum _RGX_FEATURE_WITH_VALUE_INDEX_ {
RGX_FEATURE_FBCDC_IDX,
RGX_FEATURE_FBCDC_ALGORITHM_IDX,
RGX_FEATURE_FBCDC_ARCHITECTURE_IDX,
RGX_FEATURE_FBC_MAX_DEFAULT_DESCRIPTORS_IDX,
RGX_FEATURE_FBC_MAX_LARGE_DESCRIPTORS_IDX,
RGX_FEATURE_LAYOUT_MARS_IDX,
RGX_FEATURE_META_IDX,
RGX_FEATURE_META_COREMEM_BANKS_IDX,
@@ -288,6 +299,7 @@ typedef enum _RGX_FEATURE_WITH_VALUE_INDEX_ {
RGX_FEATURE_TILE_SIZE_X_IDX,
RGX_FEATURE_TILE_SIZE_Y_IDX,
RGX_FEATURE_VIRTUAL_ADDRESS_SPACE_BITS_IDX,
RGX_FEATURE_XE_ARCHITECTURE_IDX,
RGX_FEATURE_XPU_MAX_REGBANKS_ADDR_WIDTH_IDX,
RGX_FEATURE_XPU_MAX_SLAVES_IDX,
RGX_FEATURE_XPU_REGISTER_BROADCAST_IDX,

179
drivers/gpu/drm/img-rogue/km/rgx_bvnc_table_km.h
View File

@@ -76,6 +76,10 @@ static const IMG_UINT16 aui16_RGX_FEATURE_FBCDC_ALGORITHM_values[RGX_FEATURE_FBC
static const IMG_UINT16 aui16_RGX_FEATURE_FBCDC_ARCHITECTURE_values[RGX_FEATURE_FBCDC_ARCHITECTURE_MAX_VALUE_IDX] = {(IMG_UINT16)RGX_FEATURE_VALUE_DISABLED, 1, 2, 7, };
static const IMG_UINT16 aui16_RGX_FEATURE_FBC_MAX_DEFAULT_DESCRIPTORS_values[RGX_FEATURE_FBC_MAX_DEFAULT_DESCRIPTORS_MAX_VALUE_IDX] = {(IMG_UINT16)RGX_FEATURE_VALUE_DISABLED, 0, };
static const IMG_UINT16 aui16_RGX_FEATURE_FBC_MAX_LARGE_DESCRIPTORS_values[RGX_FEATURE_FBC_MAX_LARGE_DESCRIPTORS_MAX_VALUE_IDX] = {(IMG_UINT16)RGX_FEATURE_VALUE_DISABLED, 0, };
static const IMG_UINT16 aui16_RGX_FEATURE_LAYOUT_MARS_values[RGX_FEATURE_LAYOUT_MARS_MAX_VALUE_IDX] = {(IMG_UINT16)RGX_FEATURE_VALUE_DISABLED, 0, 1, };
static const IMG_UINT16 aui16_RGX_FEATURE_META_values[RGX_FEATURE_META_MAX_VALUE_IDX] = {(IMG_UINT16)RGX_FEATURE_VALUE_DISABLED, LTP217, LTP218, MTP218, };
@@ -114,6 +118,8 @@ static const IMG_UINT16 aui16_RGX_FEATURE_TILE_SIZE_Y_values[RGX_FEATURE_TILE_SI
static const IMG_UINT16 aui16_RGX_FEATURE_VIRTUAL_ADDRESS_SPACE_BITS_values[RGX_FEATURE_VIRTUAL_ADDRESS_SPACE_BITS_MAX_VALUE_IDX] = {(IMG_UINT16)RGX_FEATURE_VALUE_DISABLED, 40, };
static const IMG_UINT16 aui16_RGX_FEATURE_XE_ARCHITECTURE_values[RGX_FEATURE_XE_ARCHITECTURE_MAX_VALUE_IDX] = {(IMG_UINT16)RGX_FEATURE_VALUE_DISABLED, 1, };
static const IMG_UINT16 aui16_RGX_FEATURE_XPU_MAX_REGBANKS_ADDR_WIDTH_values[RGX_FEATURE_XPU_MAX_REGBANKS_ADDR_WIDTH_MAX_VALUE_IDX] = {(IMG_UINT16)RGX_FEATURE_VALUE_DISABLED, 19, };
static const IMG_UINT16 aui16_RGX_FEATURE_XPU_MAX_SLAVES_values[RGX_FEATURE_XPU_MAX_SLAVES_MAX_VALUE_IDX] = {(IMG_UINT16)RGX_FEATURE_VALUE_DISABLED, 3, };
@@ -133,6 +139,8 @@ static const IMG_UINT16 * const gaFeaturesValues[RGX_FEATURE_WITH_VALUES_MAX_IDX
aui16_RGX_FEATURE_FBCDC_values,
aui16_RGX_FEATURE_FBCDC_ALGORITHM_values,
aui16_RGX_FEATURE_FBCDC_ARCHITECTURE_values,
aui16_RGX_FEATURE_FBC_MAX_DEFAULT_DESCRIPTORS_values,
aui16_RGX_FEATURE_FBC_MAX_LARGE_DESCRIPTORS_values,
aui16_RGX_FEATURE_LAYOUT_MARS_values,
aui16_RGX_FEATURE_META_values,
aui16_RGX_FEATURE_META_COREMEM_BANKS_values,
@@ -152,6 +160,7 @@ static const IMG_UINT16 * const gaFeaturesValues[RGX_FEATURE_WITH_VALUES_MAX_IDX
aui16_RGX_FEATURE_TILE_SIZE_X_values,
aui16_RGX_FEATURE_TILE_SIZE_Y_values,
aui16_RGX_FEATURE_VIRTUAL_ADDRESS_SPACE_BITS_values,
aui16_RGX_FEATURE_XE_ARCHITECTURE_values,
aui16_RGX_FEATURE_XPU_MAX_REGBANKS_ADDR_WIDTH_values,
aui16_RGX_FEATURE_XPU_MAX_SLAVES_values,
aui16_RGX_FEATURE_XPU_REGISTER_BROADCAST_values,
@@ -170,6 +179,8 @@ static const IMG_UINT16 gaFeaturesValuesMaxIndexes[] = {
RGX_FEATURE_FBCDC_MAX_VALUE_IDX,
RGX_FEATURE_FBCDC_ALGORITHM_MAX_VALUE_IDX,
RGX_FEATURE_FBCDC_ARCHITECTURE_MAX_VALUE_IDX,
RGX_FEATURE_FBC_MAX_DEFAULT_DESCRIPTORS_MAX_VALUE_IDX,
RGX_FEATURE_FBC_MAX_LARGE_DESCRIPTORS_MAX_VALUE_IDX,
RGX_FEATURE_LAYOUT_MARS_MAX_VALUE_IDX,
RGX_FEATURE_META_MAX_VALUE_IDX,
RGX_FEATURE_META_COREMEM_BANKS_MAX_VALUE_IDX,
@@ -189,6 +200,7 @@ static const IMG_UINT16 gaFeaturesValuesMaxIndexes[] = {
RGX_FEATURE_TILE_SIZE_X_MAX_VALUE_IDX,
RGX_FEATURE_TILE_SIZE_Y_MAX_VALUE_IDX,
RGX_FEATURE_VIRTUAL_ADDRESS_SPACE_BITS_MAX_VALUE_IDX,
RGX_FEATURE_XE_ARCHITECTURE_MAX_VALUE_IDX,
RGX_FEATURE_XPU_MAX_REGBANKS_ADDR_WIDTH_MAX_VALUE_IDX,
RGX_FEATURE_XPU_MAX_SLAVES_MAX_VALUE_IDX,
RGX_FEATURE_XPU_REGISTER_BROADCAST_MAX_VALUE_IDX,
@@ -205,28 +217,31 @@ static const IMG_UINT16 aui16FeaturesWithValuesBitPositions[] = {
(4U), /* RGX_FEATURE_FBCDC_POS */
(7U), /* RGX_FEATURE_FBCDC_ALGORITHM_POS */
(10U), /* RGX_FEATURE_FBCDC_ARCHITECTURE_POS */
(13U), /* RGX_FEATURE_LAYOUT_MARS_POS */
(15U), /* RGX_FEATURE_META_POS */
(18U), /* RGX_FEATURE_META_COREMEM_BANKS_POS */
(19U), /* RGX_FEATURE_META_COREMEM_SIZE_POS */
(21U), /* RGX_FEATURE_META_DMA_CHANNEL_COUNT_POS */
(22U), /* RGX_FEATURE_NUM_CLUSTERS_POS */
(25U), /* RGX_FEATURE_NUM_ISP_IPP_PIPES_POS */
(29U), /* RGX_FEATURE_NUM_OSIDS_POS */
(31U), /* RGX_FEATURE_NUM_RASTER_PIPES_POS */
(33U), /* RGX_FEATURE_PHYS_BUS_WIDTH_POS */
(36U), /* RGX_FEATURE_SCALABLE_TE_ARCH_POS */
(37U), /* RGX_FEATURE_SCALABLE_VCE_POS */
(38U), /* RGX_FEATURE_SIMPLE_PARAMETER_FORMAT_VERSION_POS */
(40U), /* RGX_FEATURE_SLC_BANKS_POS */
(43U), /* RGX_FEATURE_SLC_CACHE_LINE_SIZE_BITS_POS */
(45U), /* RGX_FEATURE_SLC_SIZE_IN_KILOBYTES_POS */
(48U), /* RGX_FEATURE_TILE_SIZE_X_POS */
(50U), /* RGX_FEATURE_TILE_SIZE_Y_POS */
(52U), /* RGX_FEATURE_VIRTUAL_ADDRESS_SPACE_BITS_POS */
(54U), /* RGX_FEATURE_XPU_MAX_REGBANKS_ADDR_WIDTH_POS */
(56U), /* RGX_FEATURE_XPU_MAX_SLAVES_POS */
(58U), /* RGX_FEATURE_XPU_REGISTER_BROADCAST_POS */
(13U), /* RGX_FEATURE_FBC_MAX_DEFAULT_DESCRIPTORS_POS */
(15U), /* RGX_FEATURE_FBC_MAX_LARGE_DESCRIPTORS_POS */
(17U), /* RGX_FEATURE_LAYOUT_MARS_POS */
(19U), /* RGX_FEATURE_META_POS */
(22U), /* RGX_FEATURE_META_COREMEM_BANKS_POS */
(23U), /* RGX_FEATURE_META_COREMEM_SIZE_POS */
(25U), /* RGX_FEATURE_META_DMA_CHANNEL_COUNT_POS */
(26U), /* RGX_FEATURE_NUM_CLUSTERS_POS */
(29U), /* RGX_FEATURE_NUM_ISP_IPP_PIPES_POS */
(33U), /* RGX_FEATURE_NUM_OSIDS_POS */
(35U), /* RGX_FEATURE_NUM_RASTER_PIPES_POS */
(37U), /* RGX_FEATURE_PHYS_BUS_WIDTH_POS */
(40U), /* RGX_FEATURE_SCALABLE_TE_ARCH_POS */
(41U), /* RGX_FEATURE_SCALABLE_VCE_POS */
(42U), /* RGX_FEATURE_SIMPLE_PARAMETER_FORMAT_VERSION_POS */
(44U), /* RGX_FEATURE_SLC_BANKS_POS */
(47U), /* RGX_FEATURE_SLC_CACHE_LINE_SIZE_BITS_POS */
(49U), /* RGX_FEATURE_SLC_SIZE_IN_KILOBYTES_POS */
(52U), /* RGX_FEATURE_TILE_SIZE_X_POS */
(54U), /* RGX_FEATURE_TILE_SIZE_Y_POS */
(56U), /* RGX_FEATURE_VIRTUAL_ADDRESS_SPACE_BITS_POS */
(58U), /* RGX_FEATURE_XE_ARCHITECTURE_POS */
(60U), /* RGX_FEATURE_XPU_MAX_REGBANKS_ADDR_WIDTH_POS */
(62U), /* RGX_FEATURE_XPU_MAX_SLAVES_POS */
(64U), /* RGX_FEATURE_XPU_REGISTER_BROADCAST_POS */
};
@@ -240,28 +255,31 @@ static const IMG_UINT64 aui64FeaturesWithValuesBitMasks[] = {
(IMG_UINT64_C(0x0000000000000070)), /* RGX_FEATURE_FBCDC_BIT_MASK */
(IMG_UINT64_C(0x0000000000000380)), /* RGX_FEATURE_FBCDC_ALGORITHM_BIT_MASK */
(IMG_UINT64_C(0x0000000000001C00)), /* RGX_FEATURE_FBCDC_ARCHITECTURE_BIT_MASK */
(IMG_UINT64_C(0x0000000000006000)), /* RGX_FEATURE_LAYOUT_MARS_BIT_MASK */
(IMG_UINT64_C(0x0000000000038000)), /* RGX_FEATURE_META_BIT_MASK */
(IMG_UINT64_C(0x0000000000040000)), /* RGX_FEATURE_META_COREMEM_BANKS_BIT_MASK */
(IMG_UINT64_C(0x0000000000180000)), /* RGX_FEATURE_META_COREMEM_SIZE_BIT_MASK */
(IMG_UINT64_C(0x0000000000200000)), /* RGX_FEATURE_META_DMA_CHANNEL_COUNT_BIT_MASK */
(IMG_UINT64_C(0x0000000001C00000)), /* RGX_FEATURE_NUM_CLUSTERS_BIT_MASK */
(IMG_UINT64_C(0x000000001E000000)), /* RGX_FEATURE_NUM_ISP_IPP_PIPES_BIT_MASK */
(IMG_UINT64_C(0x0000000060000000)), /* RGX_FEATURE_NUM_OSIDS_BIT_MASK */
(IMG_UINT64_C(0x0000000180000000)), /* RGX_FEATURE_NUM_RASTER_PIPES_BIT_MASK */
(IMG_UINT64_C(0x0000000E00000000)), /* RGX_FEATURE_PHYS_BUS_WIDTH_BIT_MASK */
(IMG_UINT64_C(0x0000001000000000)), /* RGX_FEATURE_SCALABLE_TE_ARCH_BIT_MASK */
(IMG_UINT64_C(0x0000002000000000)), /* RGX_FEATURE_SCALABLE_VCE_BIT_MASK */
(IMG_UINT64_C(0x000000C000000000)), /* RGX_FEATURE_SIMPLE_PARAMETER_FORMAT_VERSION_BIT_MASK */
(IMG_UINT64_C(0x0000070000000000)), /* RGX_FEATURE_SLC_BANKS_BIT_MASK */
(IMG_UINT64_C(0x0000180000000000)), /* RGX_FEATURE_SLC_CACHE_LINE_SIZE_BITS_BIT_MASK */
(IMG_UINT64_C(0x0000E00000000000)), /* RGX_FEATURE_SLC_SIZE_IN_KILOBYTES_BIT_MASK */
(IMG_UINT64_C(0x0003000000000000)), /* RGX_FEATURE_TILE_SIZE_X_BIT_MASK */
(IMG_UINT64_C(0x000C000000000000)), /* RGX_FEATURE_TILE_SIZE_Y_BIT_MASK */
(IMG_UINT64_C(0x0030000000000000)), /* RGX_FEATURE_VIRTUAL_ADDRESS_SPACE_BITS_BIT_MASK */
(IMG_UINT64_C(0x00C0000000000000)), /* RGX_FEATURE_XPU_MAX_REGBANKS_ADDR_WIDTH_BIT_MASK */
(IMG_UINT64_C(0x0300000000000000)), /* RGX_FEATURE_XPU_MAX_SLAVES_BIT_MASK */
(IMG_UINT64_C(0x0C00000000000000)), /* RGX_FEATURE_XPU_REGISTER_BROADCAST_BIT_MASK */
(IMG_UINT64_C(0x0000000000006000)), /* RGX_FEATURE_FBC_MAX_DEFAULT_DESCRIPTORS_BIT_MASK */
(IMG_UINT64_C(0x0000000000018000)), /* RGX_FEATURE_FBC_MAX_LARGE_DESCRIPTORS_BIT_MASK */
(IMG_UINT64_C(0x0000000000060000)), /* RGX_FEATURE_LAYOUT_MARS_BIT_MASK */
(IMG_UINT64_C(0x0000000000380000)), /* RGX_FEATURE_META_BIT_MASK */
(IMG_UINT64_C(0x0000000000400000)), /* RGX_FEATURE_META_COREMEM_BANKS_BIT_MASK */
(IMG_UINT64_C(0x0000000001800000)), /* RGX_FEATURE_META_COREMEM_SIZE_BIT_MASK */
(IMG_UINT64_C(0x0000000002000000)), /* RGX_FEATURE_META_DMA_CHANNEL_COUNT_BIT_MASK */
(IMG_UINT64_C(0x000000001C000000)), /* RGX_FEATURE_NUM_CLUSTERS_BIT_MASK */
(IMG_UINT64_C(0x00000001E0000000)), /* RGX_FEATURE_NUM_ISP_IPP_PIPES_BIT_MASK */
(IMG_UINT64_C(0x0000000600000000)), /* RGX_FEATURE_NUM_OSIDS_BIT_MASK */
(IMG_UINT64_C(0x0000001800000000)), /* RGX_FEATURE_NUM_RASTER_PIPES_BIT_MASK */
(IMG_UINT64_C(0x000000E000000000)), /* RGX_FEATURE_PHYS_BUS_WIDTH_BIT_MASK */
(IMG_UINT64_C(0x0000010000000000)), /* RGX_FEATURE_SCALABLE_TE_ARCH_BIT_MASK */
(IMG_UINT64_C(0x0000020000000000)), /* RGX_FEATURE_SCALABLE_VCE_BIT_MASK */
(IMG_UINT64_C(0x00000C0000000000)), /* RGX_FEATURE_SIMPLE_PARAMETER_FORMAT_VERSION_BIT_MASK */
(IMG_UINT64_C(0x0000700000000000)), /* RGX_FEATURE_SLC_BANKS_BIT_MASK */
(IMG_UINT64_C(0x0001800000000000)), /* RGX_FEATURE_SLC_CACHE_LINE_SIZE_BITS_BIT_MASK */
(IMG_UINT64_C(0x000E000000000000)), /* RGX_FEATURE_SLC_SIZE_IN_KILOBYTES_BIT_MASK */
(IMG_UINT64_C(0x0030000000000000)), /* RGX_FEATURE_TILE_SIZE_X_BIT_MASK */
(IMG_UINT64_C(0x00C0000000000000)), /* RGX_FEATURE_TILE_SIZE_Y_BIT_MASK */
(IMG_UINT64_C(0x0300000000000000)), /* RGX_FEATURE_VIRTUAL_ADDRESS_SPACE_BITS_BIT_MASK */
(IMG_UINT64_C(0x0C00000000000000)), /* RGX_FEATURE_XE_ARCHITECTURE_BIT_MASK */
(IMG_UINT64_C(0x3000000000000000)), /* RGX_FEATURE_XPU_MAX_REGBANKS_ADDR_WIDTH_BIT_MASK */
(IMG_UINT64_C(0xC000000000000000)), /* RGX_FEATURE_XPU_MAX_SLAVES_BIT_MASK */
(IMG_UINT64_C(0x0000000000000003)), /* RGX_FEATURE_XPU_REGISTER_BROADCAST_BIT_MASK */
};
@@ -270,41 +288,40 @@ static const IMG_UINT64 aui64FeaturesWithValuesBitMasks[] = {
*****************************************************************************/
static const IMG_UINT64 gaFeatures[][3]=
static const IMG_UINT64 gaFeatures[][4]=
{
{ IMG_UINT64_C(0x000100000002001e), IMG_UINT64_C(0x0000200000402025), IMG_UINT64_C(0x001aa8068689a481) }, /* 1.0.2.30 */
{ IMG_UINT64_C(0x0001000000040005), IMG_UINT64_C(0x0000200000402024), IMG_UINT64_C(0x001aa80686c9a481) }, /* 1.0.4.5 */
{ IMG_UINT64_C(0x0001000000040013), IMG_UINT64_C(0x0000200000402025), IMG_UINT64_C(0x001aa80686c9a481) }, /* 1.0.4.19 */
{ IMG_UINT64_C(0x0004000000020033), IMG_UINT64_C(0x0021600000c0222f), IMG_UINT64_C(0x001aa8068e912901) }, /* 4.0.2.51 */
{ IMG_UINT64_C(0x000400000002003a), IMG_UINT64_C(0x0021600000c0322f), IMG_UINT64_C(0x001aa806ce912901) }, /* 4.0.2.58 */
{ IMG_UINT64_C(0x0004000000040037), IMG_UINT64_C(0x0021600000c0222e), IMG_UINT64_C(0x001aa8068ed12901) }, /* 4.0.4.55 */
{ IMG_UINT64_C(0x000400000006003e), IMG_UINT64_C(0x0021600000c0322f), IMG_UINT64_C(0x001aab074f112901) }, /* 4.0.6.62 */
{ IMG_UINT64_C(0x000500000001002e), IMG_UINT64_C(0x0000000004402205), IMG_UINT64_C(0x001a69068248a501) }, /* 5.0.1.46 */
{ IMG_UINT64_C(0x0006000000040023), IMG_UINT64_C(0x0021600000c0222f), IMG_UINT64_C(0x001aa8068ed12901) }, /* 6.0.4.35 */
{ IMG_UINT64_C(0x000f000000010040), IMG_UINT64_C(0x0000000004403205), IMG_UINT64_C(0x001a8906c448a501) }, /* 15.0.1.64 */
{ IMG_UINT64_C(0x0016000000150010), IMG_UINT64_C(0x00000045844b3025), IMG_UINT64_C(0x00154942c4402001) }, /* 22.0.21.16 */
{ IMG_UINT64_C(0x0016000000360019), IMG_UINT64_C(0x00000045844b3025), IMG_UINT64_C(0x00158942c6402001) }, /* 22.0.54.25 */
{ IMG_UINT64_C(0x001600000036001e), IMG_UINT64_C(0x00000045844b3025), IMG_UINT64_C(0x00158942c8402001) }, /* 22.0.54.30 */
{ IMG_UINT64_C(0x0016000000360026), IMG_UINT64_C(0x00000045844b3025), IMG_UINT64_C(0x00158944c8402001) }, /* 22.0.54.38 */
{ IMG_UINT64_C(0x001600000036014a), IMG_UINT64_C(0x00000045844b3025), IMG_UINT64_C(0x00158942c8402591) }, /* 22.0.54.330 */
{ IMG_UINT64_C(0x0016000000680012), IMG_UINT64_C(0x00000045844b3025), IMG_UINT64_C(0x00158944cc402001) }, /* 22.0.104.18 */
{ IMG_UINT64_C(0x00160000006800da), IMG_UINT64_C(0x00000045844b3025), IMG_UINT64_C(0x00158944cc402591) }, /* 22.0.104.218 */
{ IMG_UINT64_C(0x0016000000d0013e), IMG_UINT64_C(0x00000045844b3025), IMG_UINT64_C(0x00158a4550802591) }, /* 22.0.208.318 */
{ IMG_UINT64_C(0x00180000003600cc), IMG_UINT64_C(0x001000c2844f7425), IMG_UINT64_C(0x00158984c8402591) }, /* 24.0.54.204 */
{ IMG_UINT64_C(0x00180000006801f8), IMG_UINT64_C(0x001000c2844f7425), IMG_UINT64_C(0x00158984ca402591) }, /* 24.0.104.504 */
{ IMG_UINT64_C(0x0018000000d001f8), IMG_UINT64_C(0x001000c2844f7425), IMG_UINT64_C(0x0015aa8550802591) }, /* 24.0.208.504 */
{ IMG_UINT64_C(0x0018000000d001f9), IMG_UINT64_C(0x001000c2844f7425), IMG_UINT64_C(0x0015aa8550802591) }, /* 24.0.208.505 */
{ IMG_UINT64_C(0x001d0000003400ca), IMG_UINT64_C(0x0010c0c2844f74a5), IMG_UINT64_C(0x00156984c4402621) }, /* 29.0.52.202 */
{ IMG_UINT64_C(0x001d0000006c00d0), IMG_UINT64_C(0x0010c0c2844f74a5), IMG_UINT64_C(0x0015aa854e802621) }, /* 29.0.108.208 */
{ IMG_UINT64_C(0x00210000000b0003), IMG_UINT64_C(0x00100052844b5085), IMG_UINT64_C(0x00152984a2402001) }, /* 33.0.11.3 */
{ IMG_UINT64_C(0x0021000000160001), IMG_UINT64_C(0x0010c042854b70a5), IMG_UINT64_C(0x00156984c4402001) }, /* 33.0.22.1 */
{ IMG_UINT64_C(0x0024000000360067), IMG_UINT64_C(0x0010c052844b38a5), IMG_UINT64_C(0x00156984c8402eb1) }, /* 36.0.54.103 */
{ IMG_UINT64_C(0x00240000003600b6), IMG_UINT64_C(0x0010c052844b78a5), IMG_UINT64_C(0x05556984c8404eb1) }, /* 36.0.54.182 */
{ IMG_UINT64_C(0x00240000003600b7), IMG_UINT64_C(0x0010c052844b78a5), IMG_UINT64_C(0x05556984c8404eb1) }, /* 36.0.54.183 */
{ IMG_UINT64_C(0x0024000000360118), IMG_UINT64_C(0x0010ce52844b78a5), IMG_UINT64_C(0x05556984c8404eb1) }, /* 36.0.54.280 */
{ IMG_UINT64_C(0x00240000006800b6), IMG_UINT64_C(0x0010c052844b78a5), IMG_UINT64_C(0x05556984ca404eb1) }, /* 36.0.104.182 */
{ IMG_UINT64_C(0x00240000006800b7), IMG_UINT64_C(0x0010c052844b78a5), IMG_UINT64_C(0x05556984ca404eb1) }, /* 36.0.104.183 */
{ IMG_UINT64_C(0x002400000068031c), IMG_UINT64_C(0x0018d052864a78a5), IMG_UINT64_C(0x05556984ca404eb5) }, /* 36.0.104.796 */
{ IMG_UINT64_C(0x000100000002001e), IMG_UINT64_C(0x0000400000402025), IMG_UINT64_C(0x01aa8068689aa481), IMG_UINT64_C(0x0000000000000000) }, /* 1.0.2.30 */
{ IMG_UINT64_C(0x0001000000040005), IMG_UINT64_C(0x0000400000402024), IMG_UINT64_C(0x01aa80686c9aa481), IMG_UINT64_C(0x0000000000000000) }, /* 1.0.4.5 */
{ IMG_UINT64_C(0x0001000000040013), IMG_UINT64_C(0x0000400000402025), IMG_UINT64_C(0x01aa80686c9aa481), IMG_UINT64_C(0x0000000000000000) }, /* 1.0.4.19 */
{ IMG_UINT64_C(0x0004000000020033), IMG_UINT64_C(0x0082c04000c0222f), IMG_UINT64_C(0x01aa8068e912a901), IMG_UINT64_C(0x0000000000000000) }, /* 4.0.2.51 */
{ IMG_UINT64_C(0x000400000002003a), IMG_UINT64_C(0x0082c04000c0322f), IMG_UINT64_C(0x01aa806ce912a901), IMG_UINT64_C(0x0000000000000000) }, /* 4.0.2.58 */
{ IMG_UINT64_C(0x0004000000040037), IMG_UINT64_C(0x0082c04000c0222e), IMG_UINT64_C(0x01aa8068ed12a901), IMG_UINT64_C(0x0000000000000000) }, /* 4.0.4.55 */
{ IMG_UINT64_C(0x000400000006003e), IMG_UINT64_C(0x0082c04000c0322f), IMG_UINT64_C(0x01aab074f112a901), IMG_UINT64_C(0x0000000000000000) }, /* 4.0.6.62 */
{ IMG_UINT64_C(0x000500000001002e), IMG_UINT64_C(0x0000004004402205), IMG_UINT64_C(0x05a69068248aa501), IMG_UINT64_C(0x0000000000000000) }, /* 5.0.1.46 */
{ IMG_UINT64_C(0x0006000000040023), IMG_UINT64_C(0x0082c04000c0222f), IMG_UINT64_C(0x01aa8068ed12a901), IMG_UINT64_C(0x0000000000000000) }, /* 6.0.4.35 */
{ IMG_UINT64_C(0x000f000000010040), IMG_UINT64_C(0x0000004004403205), IMG_UINT64_C(0x05a8906c448aa501), IMG_UINT64_C(0x0000000000000000) }, /* 15.0.1.64 */
{ IMG_UINT64_C(0x0016000000150010), IMG_UINT64_C(0x000000c5844b3025), IMG_UINT64_C(0x0554942c44020001), IMG_UINT64_C(0x0000000000000000) }, /* 22.0.21.16 */
{ IMG_UINT64_C(0x0016000000360019), IMG_UINT64_C(0x000000c5844b3025), IMG_UINT64_C(0x0558942c64020001), IMG_UINT64_C(0x0000000000000000) }, /* 22.0.54.25 */
{ IMG_UINT64_C(0x001600000036001e), IMG_UINT64_C(0x000000c5844b3025), IMG_UINT64_C(0x0558942c84020001), IMG_UINT64_C(0x0000000000000000) }, /* 22.0.54.30 */
{ IMG_UINT64_C(0x0016000000360026), IMG_UINT64_C(0x000000c5844b3025), IMG_UINT64_C(0x0558944c84020001), IMG_UINT64_C(0x0000000000000000) }, /* 22.0.54.38 */
{ IMG_UINT64_C(0x001600000036014a), IMG_UINT64_C(0x000000c5844b3025), IMG_UINT64_C(0x0558942c8402a591), IMG_UINT64_C(0x0000000000000000) }, /* 22.0.54.330 */
{ IMG_UINT64_C(0x0016000000680012), IMG_UINT64_C(0x000000c5844b3025), IMG_UINT64_C(0x0558944cc4020001), IMG_UINT64_C(0x0000000000000000) }, /* 22.0.104.18 */
{ IMG_UINT64_C(0x00160000006800da), IMG_UINT64_C(0x000000c5844b3025), IMG_UINT64_C(0x0558944cc402a591), IMG_UINT64_C(0x0000000000000000) }, /* 22.0.104.218 */
{ IMG_UINT64_C(0x0016000000d0013e), IMG_UINT64_C(0x000000c5844b3025), IMG_UINT64_C(0x0558a4550802a591), IMG_UINT64_C(0x0000000000000000) }, /* 22.0.208.318 */
{ IMG_UINT64_C(0x00180000003600cc), IMG_UINT64_C(0x004001c2844f7425), IMG_UINT64_C(0x0558984c8402a591), IMG_UINT64_C(0x0000000000000000) }, /* 24.0.54.204 */
{ IMG_UINT64_C(0x00180000006801f8), IMG_UINT64_C(0x004001c2844f7425), IMG_UINT64_C(0x0558984ca402a591), IMG_UINT64_C(0x0000000000000000) }, /* 24.0.104.504 */
{ IMG_UINT64_C(0x0018000000d001f8), IMG_UINT64_C(0x004001c2844f7425), IMG_UINT64_C(0x055aa8550802a591), IMG_UINT64_C(0x0000000000000000) }, /* 24.0.208.504 */
{ IMG_UINT64_C(0x0018000000d001f9), IMG_UINT64_C(0x004001c2844f7425), IMG_UINT64_C(0x055aa8550802a591), IMG_UINT64_C(0x0000000000000000) }, /* 24.0.208.505 */
{ IMG_UINT64_C(0x001d0000003400ca), IMG_UINT64_C(0x004181c2844f74a5), IMG_UINT64_C(0x0556984c4402a621), IMG_UINT64_C(0x0000000000000000) }, /* 29.0.52.202 */
{ IMG_UINT64_C(0x001d0000006c00d0), IMG_UINT64_C(0x004181c2844f74a5), IMG_UINT64_C(0x055aa854e802a621), IMG_UINT64_C(0x0000000000000000) }, /* 29.0.108.208 */
{ IMG_UINT64_C(0x00210000000b0003), IMG_UINT64_C(0x00400092844b5085), IMG_UINT64_C(0x0552984a24020001), IMG_UINT64_C(0x0000000000000000) }, /* 33.0.11.3 */
{ IMG_UINT64_C(0x0021000000160001), IMG_UINT64_C(0x004180c2854b70a5), IMG_UINT64_C(0x0556984c44020001), IMG_UINT64_C(0x0000000000000000) }, /* 33.0.22.1 */
{ IMG_UINT64_C(0x0024000000360067), IMG_UINT64_C(0x004180d2844b38a5), IMG_UINT64_C(0x0556984c8402aeb1), IMG_UINT64_C(0x0000000000000000) }, /* 36.0.54.103 */
{ IMG_UINT64_C(0x00240000003600b6), IMG_UINT64_C(0x004180d2844b78a5), IMG_UINT64_C(0x5556984c8404aeb1), IMG_UINT64_C(0x0000000000000001) }, /* 36.0.54.182 */
{ IMG_UINT64_C(0x00240000003600b7), IMG_UINT64_C(0x004180d2844b78a5), IMG_UINT64_C(0x5556984c8404aeb1), IMG_UINT64_C(0x0000000000000001) }, /* 36.0.54.183 */
{ IMG_UINT64_C(0x00240000006800b6), IMG_UINT64_C(0x004180d2844b78a5), IMG_UINT64_C(0x5556984ca404aeb1), IMG_UINT64_C(0x0000000000000001) }, /* 36.0.104.182 */
{ IMG_UINT64_C(0x00240000006800b7), IMG_UINT64_C(0x004180d2844b78a5), IMG_UINT64_C(0x5556984ca404aeb1), IMG_UINT64_C(0x0000000000000001) }, /* 36.0.104.183 */
{ IMG_UINT64_C(0x002400000068031c), IMG_UINT64_C(0x0071a0d2864a78a5), IMG_UINT64_C(0x5556984ca404aeb5), IMG_UINT64_C(0x0000000000000001) }, /* 36.0.104.796 */
};
/******************************************************************************
@@ -344,19 +361,17 @@ static const IMG_UINT64 gaErnsBrns[][2]=
{ IMG_UINT64_C(0x001d0013003400ca), IMG_UINT64_C(0x000000000006212a) }, /* 29.19.52.202 */
{ IMG_UINT64_C(0x0021000800160001), IMG_UINT64_C(0x000000000000212a) }, /* 33.8.22.1 */
{ IMG_UINT64_C(0x0021000f000b0003), IMG_UINT64_C(0x000000000000212a) }, /* 33.15.11.3 */
{ IMG_UINT64_C(0x0024001e003600b6), IMG_UINT64_C(0x000000000000212a) }, /* 36.30.54.182 */
{ IMG_UINT64_C(0x00240032003600b6), IMG_UINT64_C(0x000000000000212a) }, /* 36.50.54.182 */
{ IMG_UINT64_C(0x00240034006800b6), IMG_UINT64_C(0x000000000000212a) }, /* 36.52.104.182 */
{ IMG_UINT64_C(0x002400350068031c), IMG_UINT64_C(0x000000000000012a) }, /* 36.53.104.796 */
{ IMG_UINT64_C(0x00240036003600b7), IMG_UINT64_C(0x000000000000212a) }, /* 36.54.54.183 */
{ IMG_UINT64_C(0x0024003700360067), IMG_UINT64_C(0x000000000000212a) }, /* 36.55.54.103 */
{ IMG_UINT64_C(0x00240038006800b7), IMG_UINT64_C(0x000000000000212a) }, /* 36.56.104.183 */
{ IMG_UINT64_C(0x0024003c00360118), IMG_UINT64_C(0x000000000000212a) }, /* 36.60.54.280 */
};
#if defined(DEBUG)
#define FEATURE_NO_VALUES_NAMES_MAX_IDX (54)
#define FEATURE_NO_VALUES_NAMES_MAX_IDX (56)
static const IMG_CHAR * const gaszFeaturesNoValuesNames[FEATURE_NO_VALUES_NAMES_MAX_IDX] =
{
@@ -398,6 +413,7 @@ static const IMG_CHAR * const gaszFeaturesNoValuesNames[FEATURE_NO_VALUES_NAMES_
"SLC_HYBRID_CACHELINE_64_128",
"SLC_SIZE_CONFIGURABLE",
"SLC_VIVT",
"SOC_TIMER",
"SYS_BUS_SECURE_RESET",
"TDM_PDS_CHECKSUM",
"TESSELLATION",
@@ -412,6 +428,7 @@ static const IMG_CHAR * const gaszFeaturesNoValuesNames[FEATURE_NO_VALUES_NAMES_
"VDM_DRAWINDIRECT",
"VDM_OBJECT_LEVEL_LLS",
"WATCHDOG_TIMER",
"WORKGROUP_PROTECTION",
"XE_MEMORY_HIERARCHY",
"XT_TOP_INFRASTRUCTURE",
};

46
drivers/gpu/drm/img-rogue/km/rgx_cr_defs_km.h
View File

@@ -69,6 +69,15 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define RGX_CR_RASTERISATION_INDIRECT_ADDRESS_CLRMSK (0xFFFFFFF0U)
/*
Register RGX_CR_USC_INDIRECT
*/
#define RGX_CR_USC_INDIRECT (0x8000U)
#define RGX_CR_USC_INDIRECT_MASKFULL (IMG_UINT64_C(0x000000000000000F))
#define RGX_CR_USC_INDIRECT_ADDRESS_SHIFT (0U)
#define RGX_CR_USC_INDIRECT_ADDRESS_CLRMSK (0xFFFFFFF0U)
/*
Register RGX_CR_PBE_INDIRECT
*/
@@ -492,6 +501,24 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define RGX_CR_CHANGESET_NUMBER_CHANGESET_NUMBER_CLRMSK (IMG_UINT64_C(0x0000000000000000))
/*
Register RGX_CR_SOC_TIMER_GRAY
*/
#define RGX_CR_SOC_TIMER_GRAY (0x00E0U)
#define RGX_CR_SOC_TIMER_GRAY_MASKFULL (IMG_UINT64_C(0xFFFFFFFFFFFFFFFF))
#define RGX_CR_SOC_TIMER_GRAY_VALUE_SHIFT (0U)
#define RGX_CR_SOC_TIMER_GRAY_VALUE_CLRMSK (IMG_UINT64_C(0x0000000000000000))
/*
Register RGX_CR_SOC_TIMER_BINARY
*/
#define RGX_CR_SOC_TIMER_BINARY (0x00E8U)
#define RGX_CR_SOC_TIMER_BINARY_MASKFULL (IMG_UINT64_C(0xFFFFFFFFFFFFFFFF))
#define RGX_CR_SOC_TIMER_BINARY_VALUE_SHIFT (0U)
#define RGX_CR_SOC_TIMER_BINARY_VALUE_CLRMSK (IMG_UINT64_C(0x0000000000000000))
/*
Register RGX_CR_CLK_XTPLUS_CTRL
*/
@@ -5462,6 +5489,25 @@ Fast scale render */
#define RGX_CR_SLC_SIZE_IN_KB_SIZE_CLRMSK (0xFFFF0000U)
/*
Register RGX_CR_USC_TIMER
*/
#define RGX_CR_USC_TIMER (0x46C8U)
#define RGX_CR_USC_TIMER_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
#define RGX_CR_USC_TIMER_CNT_SHIFT (0U)
#define RGX_CR_USC_TIMER_CNT_CLRMSK (0x00000000U)
/*
Register RGX_CR_USC_TIMER_CNT
*/
#define RGX_CR_USC_TIMER_CNT (0x46D0U)
#define RGX_CR_USC_TIMER_CNT_MASKFULL (IMG_UINT64_C(0x0000000000000001))
#define RGX_CR_USC_TIMER_CNT_RESET_SHIFT (0U)
#define RGX_CR_USC_TIMER_CNT_RESET_CLRMSK (0xFFFFFFFEU)
#define RGX_CR_USC_TIMER_CNT_RESET_EN (0x00000001U)
/*
Register RGX_CR_USC_UVS0_CHECKSUM
*/

24
drivers/gpu/drm/img-rogue/km/rgxdefs_km.h
View File

@@ -81,7 +81,7 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define RGX_BVNC_KM_V_ST RGX_BVNC_KM_ST(RGX_BVNC_KM_V)
/* Maximum string size is [bb.vvvp.nnnn.cccc\0], includes null char */
#define RGX_BVNC_STR_SIZE_MAX (2+1+4+1+4+1+4+1)
#define RGX_BVNC_STR_SIZE_MAX (2U+1U+4U+1U+4U+1U+4U+1U)
#define RGX_BVNC_STR_FMTSPEC "%u.%u.%u.%u"
#define RGX_BVNC_STRP_FMTSPEC "%u.%up.%u.%u"
@@ -126,10 +126,10 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define RGXFW_THREAD_1 (1U)
/* META cores (required for the RGX_FEATURE_META) */
#define MTP218 (1)
#define MTP219 (2)
#define LTP218 (3)
#define LTP217 (4)
#define MTP218 (1U)
#define MTP219 (2U)
#define LTP218 (3U)
#define LTP217 (4U)
/* META Core memory feature depending on META variants */
#define RGX_META_COREMEM_32K (32*1024)
@@ -157,10 +157,14 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#endif
#endif
#define GET_ROGUE_CACHE_LINE_SIZE(x) ((((IMG_INT32)(x)) > 0) ? ((x)/8) : (0))
#define GET_ROGUE_CACHE_LINE_SIZE(x) ((((IMG_UINT32)(x)) > 0U) ? ((IMG_UINT32)(x)/8U) : (0U))
#if defined(SUPPORT_AGP)
#define MAX_HW_TA3DCONTEXTS 3U
#else
#define MAX_HW_TA3DCONTEXTS 2U
#endif
#define RGX_CR_CLK_CTRL_ALL_ON (IMG_UINT64_C(0x5555555555555555)&RGX_CR_CLK_CTRL_MASKFULL)
#define RGX_CR_CLK_CTRL_ALL_AUTO (IMG_UINT64_C(0xaaaaaaaaaaaaaaaa)&RGX_CR_CLK_CTRL_MASKFULL)
@@ -243,11 +247,11 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
* FW MMU contexts
*/
#if defined(SUPPORT_TRUSTED_DEVICE) && defined(RGX_FEATURE_META)
#define MMU_CONTEXT_MAPPING_FWPRIV (0x0) /* FW code/private data */
#define MMU_CONTEXT_MAPPING_FWIF (0x7) /* Host/FW data */
#define MMU_CONTEXT_MAPPING_FWPRIV (0x0U) /* FW code/private data */
#define MMU_CONTEXT_MAPPING_FWIF (0x7U) /* Host/FW data */
#else
#define MMU_CONTEXT_MAPPING_FWPRIV (0x0)
#define MMU_CONTEXT_MAPPING_FWIF (0x0)
#define MMU_CONTEXT_MAPPING_FWPRIV (0x0U)
#define MMU_CONTEXT_MAPPING_FWIF (0x0U)
#endif

8
drivers/gpu/drm/img-rogue/km/rgxmhdefs_km.h
View File

@@ -222,10 +222,10 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define RGX_MH_TAG_SB_MMU_ENCODING_MMU_TAG_PM_PC_WREQUEST (0x00000007U)
#define RGX_MH_TAG_ENCODING_MH_TAG_MMU_PT (0x00000000U)
#define RGX_MH_TAG_ENCODING_MH_TAG_MMU_PD (0x00000001U)
#define RGX_MH_TAG_ENCODING_MH_TAG_MMU_PC (0x00000002U)
#define RGX_MH_TAG_ENCODING_MH_TAG_MMU_PM (0x00000003U)
#define RGX_MH_TAG_ENCODING_MH_TAG_MMU (0x00000000U)
#define RGX_MH_TAG_ENCODING_MH_TAG_CPU_MMU (0x00000001U)
#define RGX_MH_TAG_ENCODING_MH_TAG_CPU_IFU (0x00000002U)
#define RGX_MH_TAG_ENCODING_MH_TAG_CPU_LSU (0x00000003U)
#define RGX_MH_TAG_ENCODING_MH_TAG_MIPS (0x00000004U)
#define RGX_MH_TAG_ENCODING_MH_TAG_CDM_STG0 (0x00000005U)
#define RGX_MH_TAG_ENCODING_MH_TAG_CDM_STG1 (0x00000006U)

8
drivers/gpu/drm/img-rogue/km_apphint.c
View File

@@ -436,7 +436,8 @@ static void apphint_action_worker(struct work_struct *work)
__func__, param_lookup[id].data_type, id));
}
if (PVRSRV_OK != result) {
/* Do not log errors if running in GUEST mode */
if ((PVRSRV_OK != result) && !PVRSRV_VZ_MODE_IS(GUEST)) {
PVR_DPF((PVR_DBG_ERROR,
"%s: failed (%s)",
__func__, PVRSRVGetErrorString(result)));
@@ -1008,7 +1009,7 @@ static int apphint_debuginfo_init(const char *sub_dir,
const DI_ITERATOR_CB iterator = {
.pfnStart = apphint_di_start, .pfnStop = apphint_di_stop,
.pfnNext = apphint_di_next, .pfnShow = apphint_di_show,
.pfnWrite = apphint_set
.pfnWrite = apphint_set, .ui32WriteLenMax = APPHINT_BUFFER_SIZE
};
if (*rootdir) {
@@ -1085,7 +1086,8 @@ static void apphint_pdump_values(void *pvDeviceNode,
(void)vsnprintf(km_buffer, APPHINT_BUFFER_SIZE, format, ap);
va_end(ap);
PDumpCommentKM(NULL, (PVRSRV_DEVICE_NODE*)pvDeviceNode, km_buffer, ui32Flags);
/* ui32CommentSize set to 0 here as function does not make use of the value. */
PDumpCommentKM(NULL, (PVRSRV_DEVICE_NODE*)pvDeviceNode, 0, km_buffer, ui32Flags);
}
#endif

3
drivers/gpu/drm/img-rogue/km_apphint_defs.h
View File

@@ -73,13 +73,14 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define APPHINT_LIST_MODPARAM \
/* name, type, class, default, helper, */ \
X(EnableCDMKillingRandMode, BOOL, VALIDATION, PVRSRV_APPHINT_ENABLECDMKILLINGRANDMODE, NO_PARAM_TABLE ) \
X(VDMContextSwitchMode, UINT32, VALIDATION, PVRSRV_APPHINT_VDMCONTEXTSWITCHMODE, NO_PARAM_TABLE ) \
\
X(HWPerfDisableCustomCounterFilter, BOOL, VALIDATION, PVRSRV_APPHINT_HWPERFDISABLECUSTOMCOUNTERFILTER, NO_PARAM_TABLE ) \
X(ValidateSOCUSCTimer, BOOL, VALIDATION, PVRSRV_APPHINT_VALIDATESOCUSCTIMERS, NO_PARAM_TABLE ) \
X(ECCRAMErrInj, UINT32, VALIDATION, 0, NO_PARAM_TABLE ) \
\
X(TFBCCompressionControlGroup, UINT32, VALIDATION, PVRSRV_APPHINT_TFBCCOMPRESSIONCONTROLGROUP, NO_PARAM_TABLE ) \
X(TFBCCompressionControlScheme, UINT32, VALIDATION, PVRSRV_APPHINT_TFBCCOMPRESSIONCONTROLSCHEME, NO_PARAM_TABLE ) \
X(TFBCCompressionControlYUVFormat, BOOL, VALIDATION, 0, NO_PARAM_TABLE ) \
/*
*******************************************************************************

3
drivers/gpu/drm/img-rogue/km_apphint_defs_common.h
View File

@@ -54,7 +54,6 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
/* name, type, class, default, helper, */ \
X(EnableTrustedDeviceAceConfig, BOOL, GPUVIRT_VAL, PVRSRV_APPHINT_ENABLETRUSTEDDEVICEACECONFIG, NO_PARAM_TABLE ) \
X(CleanupThreadPriority, UINT32, NEVER, PVRSRV_APPHINT_CLEANUPTHREADPRIORITY, NO_PARAM_TABLE ) \
X(CacheOpThreadPriority, UINT32, NEVER, PVRSRV_APPHINT_CACHEOPTHREADPRIORITY, NO_PARAM_TABLE ) \
X(WatchdogThreadPriority, UINT32, NEVER, PVRSRV_APPHINT_WATCHDOGTHREADPRIORITY, NO_PARAM_TABLE ) \
X(HWPerfClientBufferSize, UINT32, ALWAYS, PVRSRV_APPHINT_HWPERFCLIENTBUFFERSIZE, NO_PARAM_TABLE ) \
@@ -157,7 +156,7 @@ X(EnableAPM, UINT32, ALWAYS, PVRSRV_APPHINT_
X(DisableFEDLogging, BOOL, ALWAYS, PVRSRV_APPHINT_DISABLEFEDLOGGING, NO_PARAM_TABLE ) \
X(ZeroFreelist, BOOL, ALWAYS, PVRSRV_APPHINT_ZEROFREELIST, NO_PARAM_TABLE ) \
X(DisablePDumpPanic, BOOL, PDUMP, PVRSRV_APPHINT_DISABLEPDUMPPANIC, NO_PARAM_TABLE ) \
X(EnableFWPoisonOnFree, BOOL, ALWAYS, PVRSRV_APPHINT_ENABLEFWPOISONONFREE, NO_PARAM_TABLE ) \
X(EnableFWPoisonOnFree, BOOL, DEBUG, PVRSRV_APPHINT_ENABLEFWPOISONONFREE, NO_PARAM_TABLE ) \
X(GPUUnitsPowerChange, BOOL, VALIDATION, PVRSRV_APPHINT_GPUUNITSPOWERCHANGE, NO_PARAM_TABLE ) \
X(HWPerfHostFilter, UINT32, ALWAYS, PVRSRV_APPHINT_HWPERFHOSTFILTER, NO_PARAM_TABLE )

14
drivers/gpu/drm/img-rogue/lists.h
View File

@@ -46,7 +46,19 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
/* instruct QAC to ignore warnings about the following custom formatted macros */
/* PRQA S 0881,3410 ++ */
#include <stdarg.h>
#if defined(__linux__)
#include <linux/version.h>
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 15, 0))
#include <linux/stdarg.h>
#else
#include <stdarg.h>
#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(5, 15, 0) */
#else
#include <stdarg.h>
#endif /* __linux__ */
#include "img_types.h"
#include "device.h"
#include "power.h"

22
drivers/gpu/drm/img-rogue/lock.h
View File

@@ -64,12 +64,12 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*(phLock) = OSAllocMem(sizeof(struct mutex)); \
if (*(phLock)) { mutex_init(*(phLock)); e = PVRSRV_OK; }; \
e;})
#define OSLockDestroy(hLock) ({mutex_destroy((hLock)); OSFreeMem((hLock)); PVRSRV_OK;})
#define OSLockDestroyNoStats(hLock) ({mutex_destroy((hLock)); OSFreeMemNoStats((hLock)); PVRSRV_OK;})
#define OSLockDestroy(hLock) ({mutex_destroy((hLock)); OSFreeMem((hLock));})
#define OSLockDestroyNoStats(hLock) ({mutex_destroy((hLock)); OSFreeMemNoStats((hLock));})
#define OSLockAcquire(hLock) ({mutex_lock((hLock)); PVRSRV_OK;})
#define OSLockAcquireNested(hLock, subclass) ({mutex_lock_nested((hLock), (subclass)); PVRSRV_OK;})
#define OSLockRelease(hLock) ({mutex_unlock((hLock)); PVRSRV_OK;})
#define OSLockAcquire(hLock) ({mutex_lock((hLock));})
#define OSLockAcquireNested(hLock, subclass) ({mutex_lock_nested((hLock), (subclass));})
#define OSLockRelease(hLock) ({mutex_unlock((hLock));})
#define OSLockIsLocked(hLock) ((mutex_is_locked((hLock)) == 1) ? IMG_TRUE : IMG_FALSE)
#define OSTryLockAcquire(hLock) ((mutex_trylock(hLock) == 1) ? IMG_TRUE : IMG_FALSE)
@@ -114,10 +114,10 @@ static inline IMG_INT OSAtomicOr(ATOMIC_T *pCounter, IMG_INT iVal)
}
#define OSAtomicAdd(pCounter, incr) atomic_add_return(incr,pCounter)
#define OSAtomicAddUnless(pCounter, incr, test) __atomic_add_unless(pCounter,incr,test)
#define OSAtomicAddUnless(pCounter, incr, test) atomic_add_unless(pCounter, (incr), (test))
#define OSAtomicSubtract(pCounter, incr) atomic_add_return(-(incr),pCounter)
#define OSAtomicSubtractUnless(pCounter, incr, test) OSAtomicAddUnless(pCounter, -(incr), test)
#define OSAtomicSubtractUnless(pCounter, incr, test) OSAtomicAddUnless(pCounter, -(incr), (test))
#else /* defined(__linux__) && defined(__KERNEL__) */
@@ -147,7 +147,7 @@ PVRSRV_ERROR OSLockCreate(POS_LOCK *phLock);
@Return None.
*/ /**************************************************************************/
IMG_INTERNAL
PVRSRV_ERROR OSLockDestroy(POS_LOCK hLock);
void OSLockDestroy(POS_LOCK hLock);
#if defined(INTEGRITY_OS)
#define OSLockDestroyNoStats OSLockDestroy
@@ -412,11 +412,17 @@ IMG_INT32 OSAtomicOr(ATOMIC_T *pCounter, IMG_INT32 iVal);
/* For now, spin-locks are required on Linux only, so other platforms fake
* spinlocks with normal mutex locks */
/*! Type definitions for OS_SPINLOCK accessor and creation / deletion */
typedef unsigned long OS_SPINLOCK_FLAGS;
/*! Pointer to an OS Spinlock */
#define POS_SPINLOCK POS_LOCK
/*! Wrapper for OSLockCreate() */
#define OSSpinLockCreate(ppLock) OSLockCreate(ppLock)
/*! Wrapper for OSLockDestroy() */
#define OSSpinLockDestroy(pLock) OSLockDestroy(pLock)
/*! Wrapper for OSLockAcquire() */
#define OSSpinLockAcquire(pLock, flags) {flags = 0; OSLockAcquire(pLock);}
/*! Wrapper for OSLockRelease() */
#define OSSpinLockRelease(pLock, flags) {flags = 0; OSLockRelease(pLock);}
#endif /* defined(__linux__) */

14
drivers/gpu/drm/img-rogue/lock_types.h
View File

@@ -60,29 +60,29 @@ typedef atomic_t ATOMIC_T;
#else /* defined(__linux__) && defined(__KERNEL__) */
#include "img_types.h" /* needed for IMG_INT */
typedef struct _OS_LOCK_ *POS_LOCK;
typedef struct OS_LOCK_TAG *POS_LOCK;
#if defined(__linux__) || defined(__QNXNTO__) || defined(INTEGRITY_OS)
typedef struct _OSWR_LOCK_ *POSWR_LOCK;
typedef struct OSWR_LOCK_TAG *POSWR_LOCK;
#else /* defined(__linux__) || defined(__QNXNTO__) || defined(INTEGRITY_OS) */
typedef struct _OSWR_LOCK_ {
typedef struct OSWR_LOCK_TAG {
IMG_UINT32 ui32Dummy;
} *POSWR_LOCK;
#endif /* defined(__linux__) || defined(__QNXNTO__) || defined(INTEGRITY_OS) */
#if defined(__linux__)
typedef struct _OS_ATOMIC {IMG_INT32 counter;} ATOMIC_T;
typedef struct OS_ATOMIC_TAG {IMG_INT32 counter;} ATOMIC_T;
#elif defined(__QNXNTO__)
typedef struct _OS_ATOMIC {IMG_INT32 counter;} ATOMIC_T;
typedef struct OS_ATOMIC_TAG {IMG_INT32 counter;} ATOMIC_T;
#elif defined(_WIN32)
/*
* Dummy definition. WDDM doesn't use Services, but some headers
* still have to be shared. This is one such case.
*/
typedef struct _OS_ATOMIC {IMG_INT32 counter;} ATOMIC_T;
typedef struct OS_ATOMIC_TAG {IMG_INT32 counter;} ATOMIC_T;
#elif defined(INTEGRITY_OS)
/* Only lower 32bits are used in OS ATOMIC APIs to have consistent behaviour across all OS */
typedef struct _OS_ATOMIC {IMG_INT64 counter;} ATOMIC_T;
typedef struct OS_ATOMIC_TAG {IMG_INT64 counter;} ATOMIC_T;
#else
#error "Please type-define an atomic lock for this environment"
#endif

8
drivers/gpu/drm/img-rogue/log2.h
View File

@@ -270,7 +270,7 @@ static INLINE uint32_t __const_function FloorLog2(uint32_t n)
{
uint32_t ui32log2 = 0;
while (n >>= 1)
while ((n >>= 1) != 0U)
{
ui32log2++;
}
@@ -287,7 +287,7 @@ static INLINE uint32_t __const_function FloorLog2_64(uint64_t n)
{
uint32_t ui32log2 = 0;
while (n >>= 1)
while ((n >>= 1) != 0U)
{
ui32log2++;
}
@@ -311,7 +311,7 @@ static INLINE uint32_t __const_function CeilLog2(uint32_t n)
n--; /* Handle powers of 2 */
while (n)
while (n != 0U)
{
ui32log2++;
n >>= 1;
@@ -336,7 +336,7 @@ static INLINE uint32_t __const_function CeilLog2_64(uint64_t n)
n--; /* Handle powers of 2 */
while (n)
while (n != 0U)
{
ui32log2++;
n >>= 1;

201
drivers/gpu/drm/img-rogue/mmu_common.c
View File

@@ -337,7 +337,7 @@ _FreeMMUMapping(PVRSRV_DEVICE_NODE *psDevNode,
MMU_MEMORY_MAPPING,
sMMUMappingItem);
psDevNode->sDevMMUPxSetup.pfnDevPxFree(psDevNode, &psMapping->sMemHandle);
PhysHeapPagesFree(psDevNode->psMMUPhysHeap, &psMapping->sMemHandle);
dllist_remove_node(psNode);
OSFreeMem(psMapping);
}
@@ -722,10 +722,10 @@ void RGXMapBRN71422TargetPhysicalAddress(MMU_CONTEXT *psMMUContext)
{
PVRSRV_ERROR eError;
PVRSRV_DEVICE_NODE *psDevNode = (PVRSRV_DEVICE_NODE *)psMMUContext->psPhysMemCtx->psDevNode;
eError = psDevNode->sDevMMUPxSetup.pfnDevPxClean(psDevNode,
&psMemDesc->psMapping->sMemHandle,
psMemDesc->uiOffset,
psMemDesc->uiSize);
eError = PhysHeapPagesClean(psDevNode->psMMUPhysHeap,
&psMemDesc->psMapping->sMemHandle,
psMemDesc->uiOffset,
psMemDesc->uiSize);
PVR_LOG_IF_ERROR(eError, "pfnDevPxClean");
}
@@ -795,18 +795,18 @@ static PVRSRV_ERROR _MMU_PhysMem_RAImportAlloc(RA_PERARENA_HANDLE hArenaHandle,
* pfnDevPxFree() routine.
*/
psMapping->sMemHandle.uiOSid = psPhysMemCtx->ui32OSid;
eError = psDevNode->sDevMMUPxSetup.pfnDevPxAllocGPV(psDevNode,
TRUNCATE_64BITS_TO_SIZE_T(uiSize),
&psMapping->sMemHandle,
&psMapping->sDevPAddr,
psPhysMemCtx->ui32OSid,
uiPid);
eError = PhysHeapPagesAllocGPV(psDevNode->psMMUPhysHeap,
TRUNCATE_64BITS_TO_SIZE_T(uiSize),
&psMapping->sMemHandle,
&psMapping->sDevPAddr,
psPhysMemCtx->ui32OSid,
uiPid);
#else
eError = psDevNode->sDevMMUPxSetup.pfnDevPxAlloc(psDevNode,
TRUNCATE_64BITS_TO_SIZE_T(uiSize),
&psMapping->sMemHandle,
&psMapping->sDevPAddr,
uiPid);
eError = PhysHeapPagesAlloc(psDevNode->psMMUPhysHeap,
TRUNCATE_64BITS_TO_SIZE_T(uiSize),
&psMapping->sMemHandle,
&psMapping->sDevPAddr,
uiPid);
#endif
if (eError != PVRSRV_OK)
{
@@ -915,11 +915,11 @@ static PVRSRV_ERROR _MMU_PhysMemAlloc(MMU_PHYSMEM_CONTEXT *psPhysMemCtx,
if (psMemDesc->psMapping->uiCpuVAddrRefCount == 0)
{
eError = psPhysMemCtx->psDevNode->sDevMMUPxSetup.pfnDevPxMap(psPhysMemCtx->psDevNode,
&psMemDesc->psMapping->sMemHandle,
psMemDesc->psMapping->uiSize,
&psMemDesc->psMapping->sDevPAddr,
&psMemDesc->psMapping->pvCpuVAddr);
eError = PhysHeapPagesMap(psPhysMemCtx->psDevNode->psMMUPhysHeap,
&psMemDesc->psMapping->sMemHandle,
psMemDesc->psMapping->uiSize,
&psMemDesc->psMapping->sDevPAddr,
&psMemDesc->psMapping->pvCpuVAddr);
if (eError != PVRSRV_OK)
{
RA_Free(psPhysMemCtx->psPhysMemRA, psMemDesc->sDevPAddr.uiAddr);
@@ -957,9 +957,9 @@ static void _MMU_PhysMemFree(MMU_PHYSMEM_CONTEXT *psPhysMemCtx,
if (--psMemDesc->psMapping->uiCpuVAddrRefCount == 0)
{
psPhysMemCtx->psDevNode->sDevMMUPxSetup.pfnDevPxUnMap(psPhysMemCtx->psDevNode,
&psMemDesc->psMapping->sMemHandle,
psMemDesc->psMapping->pvCpuVAddr);
PhysHeapPagesUnMap(psPhysMemCtx->psDevNode->psMMUPhysHeap,
&psMemDesc->psMapping->sMemHandle,
psMemDesc->psMapping->pvCpuVAddr);
}
psMemDesc->pvCpuVAddr = NULL;
@@ -1125,10 +1125,10 @@ static PVRSRV_ERROR _PxMemAlloc(MMU_CONTEXT *psMMUContext,
*/
OSCachedMemSet(psMemDesc->pvCpuVAddr, 0, uiBytes);
eError = psDevNode->sDevMMUPxSetup.pfnDevPxClean(psDevNode,
&psMemDesc->psMapping->sMemHandle,
psMemDesc->uiOffset,
psMemDesc->uiSize);
eError = PhysHeapPagesClean(psDevNode->psMMUPhysHeap,
&psMemDesc->psMapping->sMemHandle,
psMemDesc->uiOffset,
psMemDesc->uiSize);
PVR_GOTO_IF_ERROR(eError, e1);
#if defined(PDUMP)
@@ -1654,10 +1654,10 @@ static IMG_BOOL _MMU_FreeLevel(MMU_CONTEXT *psMMUContext,
/* Level one flushing is done when we actually write the table entries */
if ((aeMMULevel[uiThisLevel] != MMU_LEVEL_1) && (psLevel != NULL))
{
psDevNode->sDevMMUPxSetup.pfnDevPxClean(psDevNode,
&psLevel->sMemDesc.psMapping->sMemHandle,
uiStartIndex * psConfig->uiBytesPerEntry + psLevel->sMemDesc.uiOffset,
(uiEndIndex - uiStartIndex) * psConfig->uiBytesPerEntry);
PhysHeapPagesClean(psDevNode->psMMUPhysHeap,
&psLevel->sMemDesc.psMapping->sMemHandle,
uiStartIndex * psConfig->uiBytesPerEntry + psLevel->sMemDesc.uiOffset,
(uiEndIndex - uiStartIndex) * psConfig->uiBytesPerEntry);
}
MMU_OBJ_DBG((PVR_DBG_ERROR, "_MMU_FreeLevel end: level = %d, refcount = %d",
@@ -1872,10 +1872,10 @@ static PVRSRV_ERROR _MMU_AllocLevel(MMU_CONTEXT *psMMUContext,
/* Level one flushing is done when we actually write the table entries */
if (aeMMULevel[uiThisLevel] != MMU_LEVEL_1)
{
eError = psDevNode->sDevMMUPxSetup.pfnDevPxClean(psDevNode,
&psLevel->sMemDesc.psMapping->sMemHandle,
uiStartIndex * psConfig->uiBytesPerEntry + psLevel->sMemDesc.uiOffset,
(uiEndIndex - uiStartIndex) * psConfig->uiBytesPerEntry);
eError = PhysHeapPagesClean(psDevNode->psMMUPhysHeap,
&psLevel->sMemDesc.psMapping->sMemHandle,
uiStartIndex * psConfig->uiBytesPerEntry + psLevel->sMemDesc.uiOffset,
(uiEndIndex - uiStartIndex) * psConfig->uiBytesPerEntry);
PVR_GOTO_IF_ERROR(eError, e0);
}
@@ -2267,7 +2267,7 @@ static void _FreePageTables(MMU_CONTEXT *psMMUContext,
static INLINE void _MMU_GetPTInfo(MMU_CONTEXT *psMMUContext,
IMG_DEV_VIRTADDR sDevVAddr,
const MMU_DEVVADDR_CONFIG *psDevVAddrConfig,
MMU_Levelx_INFO **psLevel,
MMU_Levelx_INFO **ppsLevel,
IMG_UINT32 *pui32PTEIndex)
{
MMU_Levelx_INFO *psLocalLevel = NULL;
@@ -2278,8 +2278,7 @@ static INLINE void _MMU_GetPTInfo(MMU_CONTEXT *psMMUContext,
if ((eMMULevel <= MMU_LEVEL_0) || (eMMULevel >= MMU_LEVEL_LAST))
{
PVR_DPF((PVR_DBG_ERROR, "_MMU_GetPTEInfo: Invalid MMU level"));
psLevel = NULL;
return;
PVR_ASSERT(0);
}
for (; eMMULevel > MMU_LEVEL_0; eMMULevel--)
@@ -2319,7 +2318,7 @@ static INLINE void _MMU_GetPTInfo(MMU_CONTEXT *psMMUContext,
}
}
}
*psLevel = psLocalLevel;
*ppsLevel = psLocalLevel;
}
/*************************************************************************/ /*!
@@ -2499,7 +2498,7 @@ MMU_ContextCreate(CONNECTION_DATA *psConnection,
psPhysMemCtx->psPhysMemRA = RA_Create(psPhysMemCtx->pszPhysMemRAName,
/* subsequent import */
psDevNode->sDevMMUPxSetup.uiMMUPxLog2AllocGran,
PhysHeapGetPageShift(psDevNode->psMMUPhysHeap),
RA_LOCKCLASS_1,
_MMU_PhysMem_RAImportAlloc,
_MMU_PhysMem_RAImportFree,
@@ -2843,17 +2842,6 @@ MMU_MapPages(MMU_CONTEXT *psMMUContext,
(IMG_UINT64)(ui32MapPageCount * uiPageSize));
#endif /*PDUMP*/
#if defined(TC_MEMORY_CONFIG) || defined(PLATO_MEMORY_CONFIG)
/* We're aware that on TC based platforms, accesses from GPU to CPU_LOCAL
* allocated DevMem fail, so we forbid mapping such a PMR into device mmu */
if (PVRSRV_CHECK_PHYS_HEAP(CPU_LOCAL, PMR_Flags(psPMR)))
{
PVR_DPF((PVR_DBG_ERROR,
"%s: Mapping a CPU_LOCAL PMR to device is forbidden on this platform", __func__));
return PVRSRV_ERROR_PMR_NOT_PERMITTED;
}
#endif
/* Validate the most essential parameters */
PVR_LOG_GOTO_IF_INVALID_PARAM(psMMUContext, eError, e0);
PVR_LOG_GOTO_IF_INVALID_PARAM(psPMR, eError, e0);
@@ -2952,17 +2940,11 @@ MMU_MapPages(MMU_CONTEXT *psMMUContext,
{
uiDummyProtFlags = psMMUContext->psDevAttrs->pfnDerivePTEProt8(uiMMUProtFlags , uiLog2HeapPageSize);
}
else if (psConfig->uiBytesPerEntry == 4)
{
uiDummyProtFlags = psMMUContext->psDevAttrs->pfnDerivePTEProt4(uiMMUProtFlags);
}
else
{
PVR_DPF((PVR_DBG_ERROR,
"%s: The page table entry byte length is not supported",
__func__));
eError = PVRSRV_ERROR_INVALID_PARAMS;
goto e2;
/* We've already validated possible values of uiBytesPerEntry at the start of this function */
PVR_ASSERT(psConfig->uiBytesPerEntry == 4);
uiDummyProtFlags = psMMUContext->psDevAttrs->pfnDerivePTEProt4(uiMMUProtFlags);
}
}
}
@@ -3086,10 +3068,10 @@ MMU_MapPages(MMU_CONTEXT *psMMUContext,
/* Flush if we moved to another psLevel, i.e. page table */
if (psPrevLevel != NULL)
{
eError = psDevNode->sDevMMUPxSetup.pfnDevPxClean(psDevNode,
&psPrevLevel->sMemDesc.psMapping->sMemHandle,
uiFlushStart * psConfig->uiBytesPerEntry + psPrevLevel->sMemDesc.uiOffset,
(uiFlushEnd+1 - uiFlushStart) * psConfig->uiBytesPerEntry);
eError = PhysHeapPagesClean(psDevNode->psMMUPhysHeap,
&psPrevLevel->sMemDesc.psMapping->sMemHandle,
uiFlushStart * psConfig->uiBytesPerEntry + psPrevLevel->sMemDesc.uiOffset,
(uiFlushEnd+1 - uiFlushStart) * psConfig->uiBytesPerEntry);
PVR_GOTO_IF_ERROR(eError, e3);
}
@@ -3136,10 +3118,10 @@ MMU_MapPages(MMU_CONTEXT *psMMUContext,
/* Flush the last level we touched */
if (psLevel != NULL)
{
eError = psDevNode->sDevMMUPxSetup.pfnDevPxClean(psDevNode,
&psLevel->sMemDesc.psMapping->sMemHandle,
uiFlushStart * psConfig->uiBytesPerEntry + psLevel->sMemDesc.uiOffset,
(uiFlushEnd+1 - uiFlushStart) * psConfig->uiBytesPerEntry);
eError = PhysHeapPagesClean(psDevNode->psMMUPhysHeap,
&psLevel->sMemDesc.psMapping->sMemHandle,
uiFlushStart * psConfig->uiBytesPerEntry + psLevel->sMemDesc.uiOffset,
(uiFlushEnd+1 - uiFlushStart) * psConfig->uiBytesPerEntry);
PVR_GOTO_IF_ERROR(eError, e3);
}
@@ -3303,10 +3285,10 @@ MMU_UnmapPages(MMU_CONTEXT *psMMUContext,
/* Flush if we moved to another psLevel, i.e. page table */
if (psPrevLevel != NULL)
{
psDevNode->sDevMMUPxSetup.pfnDevPxClean(psDevNode,
&psPrevLevel->sMemDesc.psMapping->sMemHandle,
uiFlushStart * psConfig->uiBytesPerEntry + psPrevLevel->sMemDesc.uiOffset,
(uiFlushEnd+1 - uiFlushStart) * psConfig->uiBytesPerEntry);
PhysHeapPagesClean(psDevNode->psMMUPhysHeap,
&psPrevLevel->sMemDesc.psMapping->sMemHandle,
uiFlushStart * psConfig->uiBytesPerEntry + psPrevLevel->sMemDesc.uiOffset,
(uiFlushEnd+1 - uiFlushStart) * psConfig->uiBytesPerEntry);
}
uiFlushStart = uiPTEIndex;
@@ -3342,10 +3324,10 @@ MMU_UnmapPages(MMU_CONTEXT *psMMUContext,
/* Flush the last level we touched */
if (psLevel != NULL)
{
psDevNode->sDevMMUPxSetup.pfnDevPxClean(psDevNode,
&psLevel->sMemDesc.psMapping->sMemHandle,
uiFlushStart * psConfig->uiBytesPerEntry + psLevel->sMemDesc.uiOffset,
(uiFlushEnd+1 - uiFlushStart) * psConfig->uiBytesPerEntry);
PhysHeapPagesClean(psDevNode->psMMUPhysHeap,
&psLevel->sMemDesc.psMapping->sMemHandle,
uiFlushStart * psConfig->uiBytesPerEntry + psLevel->sMemDesc.uiOffset,
(uiFlushEnd+1 - uiFlushStart) * psConfig->uiBytesPerEntry);
}
OSLockRelease(psMMUContext->hLock);
@@ -3407,17 +3389,6 @@ MMU_MapPMRFast (MMU_CONTEXT *psMMUContext,
PVR_ASSERT (psMMUContext != NULL);
PVR_ASSERT (psPMR != NULL);
#if defined(TC_MEMORY_CONFIG) || defined(PLATO_MEMORY_CONFIG)
/* We're aware that on TC based platforms, accesses from GPU to CPU_LOCAL
* allocated DevMem fail, so we forbid mapping such a PMR into device mmu */
if (PVRSRV_CHECK_PHYS_HEAP(CPU_LOCAL, PMR_Flags(psPMR)))
{
PVR_DPF((PVR_DBG_ERROR,
"%s: Mapping a CPU_LOCAL PMR to device is forbidden on this platform", __func__));
return PVRSRV_ERROR_PMR_NOT_PERMITTED;
}
#endif
/* Allocate memory for page-frame-numbers and validity states,
N.B. assert could be triggered by an illegal uiSizeBytes */
uiCount = uiSizeBytes >> uiLog2HeapPageSize;
@@ -3551,10 +3522,10 @@ MMU_MapPMRFast (MMU_CONTEXT *psMMUContext,
}
else
{
eError = psDevNode->sDevMMUPxSetup.pfnDevPxClean(psDevNode,
&psLevel->sMemDesc.psMapping->sMemHandle,
uiFlushStart * psConfig->uiBytesPerEntry + psLevel->sMemDesc.uiOffset,
(uiPTEIndex+1 - uiFlushStart) * psConfig->uiBytesPerEntry);
eError = PhysHeapPagesClean(psDevNode->psMMUPhysHeap,
&psLevel->sMemDesc.psMapping->sMemHandle,
uiFlushStart * psConfig->uiBytesPerEntry + psLevel->sMemDesc.uiOffset,
(uiPTEIndex+1 - uiFlushStart) * psConfig->uiBytesPerEntry);
PVR_GOTO_IF_ERROR(eError, unlock_mmu_context);
@@ -3695,16 +3666,10 @@ MMU_UnmapPMRFast(MMU_CONTEXT *psMMUContext,
{
((IMG_UINT64*)psLevel->sMemDesc.pvCpuVAddr)[uiPTEIndex] = uiEntry;
}
else if (psConfig->uiBytesPerEntry == 4)
{
((IMG_UINT32*)psLevel->sMemDesc.pvCpuVAddr)[uiPTEIndex] = (IMG_UINT32) uiEntry;
}
else
{
PVR_DPF((PVR_DBG_ERROR,
"%s: The page table entry byte length is not supported",
__func__));
goto e1;
PVR_ASSERT(psConfig->uiBytesPerEntry == 4);
((IMG_UINT32*)psLevel->sMemDesc.pvCpuVAddr)[uiPTEIndex] = (IMG_UINT32) uiEntry;
}
/* Log modifications */
@@ -3748,10 +3713,10 @@ MMU_UnmapPMRFast(MMU_CONTEXT *psMMUContext,
}
else
{
psDevNode->sDevMMUPxSetup.pfnDevPxClean(psDevNode,
&psLevel->sMemDesc.psMapping->sMemHandle,
uiFlushStart * psConfig->uiBytesPerEntry + psLevel->sMemDesc.uiOffset,
(uiPTEIndex+1 - uiFlushStart) * psConfig->uiBytesPerEntry);
PhysHeapPagesClean(psDevNode->psMMUPhysHeap,
&psLevel->sMemDesc.psMapping->sMemHandle,
uiFlushStart * psConfig->uiBytesPerEntry + psLevel->sMemDesc.uiOffset,
(uiPTEIndex+1 - uiFlushStart) * psConfig->uiBytesPerEntry);
_MMU_GetPTInfo(psMMUContext, sDevVAddr, psDevVAddrConfig,
&psLevel, &uiPTEIndex);
@@ -3771,9 +3736,6 @@ MMU_UnmapPMRFast(MMU_CONTEXT *psMMUContext,
return;
e1:
OSLockRelease(psMMUContext->hLock);
_MMU_PutPTConfig(psMMUContext, hPriv);
e0:
PVR_DPF((PVR_DBG_ERROR, "%s: Failed to map/unmap page table", __func__));
PVR_ASSERT(0);
@@ -3911,10 +3873,10 @@ MMU_ChangeValidity(MMU_CONTEXT *psMMUContext,
else
{
eError = psDevNode->sDevMMUPxSetup.pfnDevPxClean(psDevNode,
&psLevel->sMemDesc.psMapping->sMemHandle,
uiFlushStart * psConfig->uiBytesPerEntry + psLevel->sMemDesc.uiOffset,
(uiPTIndex+1 - uiFlushStart) * psConfig->uiBytesPerEntry);
eError = PhysHeapPagesClean(psDevNode->psMMUPhysHeap,
&psLevel->sMemDesc.psMapping->sMemHandle,
uiFlushStart * psConfig->uiBytesPerEntry + psLevel->sMemDesc.uiOffset,
(uiPTIndex+1 - uiFlushStart) * psConfig->uiBytesPerEntry);
PVR_GOTO_IF_ERROR(eError, e_exit);
_MMU_GetPTInfo(psMMUContext, sDevVAddr, psDevVAddrConfig,
@@ -3955,6 +3917,23 @@ MMU_AcquireBaseAddr(MMU_CONTEXT *psMMUContext, IMG_DEV_PHYADDR *psPhysAddr)
return PVRSRV_OK;
}
/*
MMU_AcquireCPUBaseAddr
*/
PVRSRV_ERROR
MMU_AcquireCPUBaseAddr(MMU_CONTEXT *psMMUContext, void **ppvCPUVAddr)
{
if (!psMMUContext)
{
*ppvCPUVAddr = NULL;
return PVRSRV_ERROR_INVALID_PARAMS;
}
*ppvCPUVAddr = psMMUContext->sBaseLevelInfo.sMemDesc.pvCpuVAddr;
return PVRSRV_OK;
}
/*
MMU_ReleaseBaseAddr
*/

16
drivers/gpu/drm/img-rogue/mmu_common.h
View File

@@ -554,6 +554,22 @@ MMU_ChangeValidity(MMU_CONTEXT *psMMUContext,
PVRSRV_ERROR
MMU_AcquireBaseAddr(MMU_CONTEXT *psMMUContext, IMG_DEV_PHYADDR *psPhysAddr);
/*************************************************************************/ /*!
@Function MMU_AcquireCPUBaseAddr
@Description Acquire the CPU Virtual Address of the base level MMU object
@Input psMMUContext MMU context to operate on
@Output ppvCPUVAddr CPU Virtual Address of the base level
MMU object
@Return PVRSRV_OK if successful
*/
/*****************************************************************************/
PVRSRV_ERROR
MMU_AcquireCPUBaseAddr(MMU_CONTEXT *psMMUContext, void **ppvCPUVAddr);
/*************************************************************************/ /*!
@Function MMU_ReleaseBaseAddr

242
drivers/gpu/drm/img-rogue/module_common.c
View File

@@ -119,7 +119,7 @@ EXPORT_SYMBOL(RGXInitSLC);
EXPORT_SYMBOL(RGXHWPerfConnect);
EXPORT_SYMBOL(RGXHWPerfDisconnect);
EXPORT_SYMBOL(RGXHWPerfControl);
#if defined(HWPERF_PACKET_V2C_SIG)
#if defined(RGX_FEATURE_HWPERF_VOLCANIC)
EXPORT_SYMBOL(RGXHWPerfConfigureCounters);
#else
EXPORT_SYMBOL(RGXHWPerfConfigMuxCounters);
@@ -137,13 +137,34 @@ EXPORT_SYMBOL(OSRemoveTimer);
#endif
#endif
CONNECTION_DATA *LinuxConnectionFromFile(struct file *pFile)
static int PVRSRVDeviceSyncOpen(struct _PVRSRV_DEVICE_NODE_ *psDeviceNode,
struct drm_file *psDRMFile);
CONNECTION_DATA *LinuxServicesConnectionFromFile(struct file *pFile)
{
if (pFile)
{
struct drm_file *psDRMFile = pFile->private_data;
PVRSRV_CONNECTION_PRIV *psConnectionPriv = (PVRSRV_CONNECTION_PRIV*)psDRMFile->driver_priv;
return psDRMFile->driver_priv;
return (CONNECTION_DATA*)psConnectionPriv->pvConnectionData;
}
return NULL;
}
CONNECTION_DATA *LinuxSyncConnectionFromFile(struct file *pFile)
{
if (pFile)
{
struct drm_file *psDRMFile = pFile->private_data;
PVRSRV_CONNECTION_PRIV *psConnectionPriv = (PVRSRV_CONNECTION_PRIV*)psDRMFile->driver_priv;
#if (PVRSRV_DEVICE_INIT_MODE == PVRSRV_LINUX_DEV_INIT_ON_CONNECT)
return (CONNECTION_DATA*)psConnectionPriv->pvConnectionData;
#else
return (CONNECTION_DATA*)psConnectionPriv->pvSyncConnectionData;
#endif
}
return NULL;
@@ -200,6 +221,21 @@ int PVRSRVDriverInit(void)
}
#endif
#if defined(ANDROID)
#if defined(CONFIG_PROC_FS)
error = PVRProcFsRegister();
if (error != PVRSRV_OK)
{
return -ENOMEM;
}
#elif defined(CONFIG_DEBUG_FS)
error = PVRDebugFsRegister();
if (error != PVRSRV_OK)
{
return -ENOMEM;
}
#endif /* defined(CONFIG_PROC_FS) || defined(CONFIG_DEBUG_FS) */
#else
#if defined(CONFIG_DEBUG_FS)
error = PVRDebugFsRegister();
if (error != PVRSRV_OK)
@@ -213,6 +249,7 @@ int PVRSRVDriverInit(void)
return -ENOMEM;
}
#endif /* defined(CONFIG_DEBUG_FS) || defined(CONFIG_PROC_FS) */
#endif /* defined(ANDROID) */
error = PVRSRVIonStatsInitialise();
if (error != PVRSRV_OK)
@@ -410,21 +447,21 @@ int PVRSRVDeviceResume(PVRSRV_DEVICE_NODE *psDeviceNode)
}
/**************************************************************************/ /*!
@Function PVRSRVDeviceOpen
@Description Common device open.
@Function PVRSRVDeviceServicesOpen
@Description Services device open.
@Input psDeviceNode The device node representing the device being
opened by a user mode process
@Input psDRMFile The DRM file data that backs the file handle
returned to the user mode process
@Return int 0 on success and a Linux error code otherwise
*/ /***************************************************************************/
int PVRSRVDeviceOpen(PVRSRV_DEVICE_NODE *psDeviceNode,
struct drm_file *psDRMFile)
int PVRSRVDeviceServicesOpen(PVRSRV_DEVICE_NODE *psDeviceNode,
struct drm_file *psDRMFile)
{
static DEFINE_MUTEX(sDeviceInitMutex);
PVRSRV_DATA *psPVRSRVData = PVRSRVGetPVRSRVData();
ENV_CONNECTION_PRIVATE_DATA sPrivData;
void *pvConnectionData;
PVRSRV_CONNECTION_PRIV *psConnectionPriv;
PVRSRV_ERROR eError;
int iErr = 0;
@@ -449,6 +486,23 @@ int PVRSRVDeviceOpen(PVRSRV_DEVICE_NODE *psDeviceNode,
goto out;
}
if (psDRMFile->driver_priv == NULL)
{
/* Allocate psConnectionPriv (stores private data and release pfn under driver_priv) */
psConnectionPriv = kzalloc(sizeof(*psConnectionPriv), GFP_KERNEL);
if (!psConnectionPriv)
{
PVR_DPF((PVR_DBG_ERROR, "%s: No memory to allocate driver_priv data", __func__));
iErr = -ENOMEM;
mutex_unlock(&sDeviceInitMutex);
goto fail_alloc_connection_priv;
}
}
else
{
psConnectionPriv = (PVRSRV_CONNECTION_PRIV*)psDRMFile->driver_priv;
}
if (psDeviceNode->eDevState == PVRSRV_DEVICE_STATE_INIT)
{
eError = PVRSRVCommonDeviceInitialise(psDeviceNode);
@@ -458,7 +512,7 @@ int PVRSRVDeviceOpen(PVRSRV_DEVICE_NODE *psDeviceNode,
__func__, PVRSRVGetErrorString(eError)));
iErr = -ENODEV;
mutex_unlock(&sDeviceInitMutex);
goto out;
goto fail_device_init;
}
#if defined(SUPPORT_RGX)
@@ -474,24 +528,125 @@ int PVRSRVDeviceOpen(PVRSRV_DEVICE_NODE *psDeviceNode,
* OSConnectionPrivateDataInit function where we can save it so
* we can back reference the file structure from its connection
*/
eError = PVRSRVCommonConnectionConnect(&pvConnectionData, (void *) &sPrivData);
eError = PVRSRVCommonConnectionConnect(&psConnectionPriv->pvConnectionData,
(void *)&sPrivData);
if (eError != PVRSRV_OK)
{
iErr = -ENOMEM;
goto fail_connect;
}
#if (PVRSRV_DEVICE_INIT_MODE == PVRSRV_LINUX_DEV_INIT_ON_CONNECT)
psConnectionPriv->pfDeviceRelease = PVRSRVCommonConnectionDisconnect;
#endif
psDRMFile->driver_priv = (void*)psConnectionPriv;
goto out;
fail_connect:
fail_device_init:
kfree(psConnectionPriv);
fail_alloc_connection_priv:
out:
return iErr;
}
/**************************************************************************/ /*!
@Function PVRSRVDeviceSyncOpen
@Description Sync device open.
@Input psDeviceNode The device node representing the device being
opened by a user mode process
@Input psDRMFile The DRM file data that backs the file handle
returned to the user mode process
@Return int 0 on success and a Linux error code otherwise
*/ /***************************************************************************/
static int PVRSRVDeviceSyncOpen(PVRSRV_DEVICE_NODE *psDeviceNode,
struct drm_file *psDRMFile)
{
PVRSRV_DATA *psPVRSRVData = PVRSRVGetPVRSRVData();
CONNECTION_DATA *psConnection = NULL;
ENV_CONNECTION_PRIVATE_DATA sPrivData;
PVRSRV_CONNECTION_PRIV *psConnectionPriv;
PVRSRV_ERROR eError;
int iErr = 0;
if (!psPVRSRVData)
{
PVR_DPF((PVR_DBG_ERROR, "%s: No device data", __func__));
iErr = -ENODEV;
goto out;
}
if (psDRMFile->driver_priv == NULL)
{
/* Allocate psConnectionPriv (stores private data and release pfn under driver_priv) */
psConnectionPriv = kzalloc(sizeof(*psConnectionPriv), GFP_KERNEL);
if (!psConnectionPriv)
{
PVR_DPF((PVR_DBG_ERROR, "%s: No memory to allocate driver_priv data", __func__));
iErr = -ENOMEM;
goto out;
}
}
else
{
psConnectionPriv = (PVRSRV_CONNECTION_PRIV*)psDRMFile->driver_priv;
}
/* Allocate connection data area, no stats since process not registered yet */
psConnection = kzalloc(sizeof(*psConnection), GFP_KERNEL);
if (!psConnection)
{
PVR_DPF((PVR_DBG_ERROR, "%s: No memory to allocate connection data", __func__));
iErr = -ENOMEM;
goto fail_alloc_connection;
}
#if (PVRSRV_DEVICE_INIT_MODE == PVRSRV_LINUX_DEV_INIT_ON_CONNECT)
psConnectionPriv->pvConnectionData = (void*)psConnection;
#else
psConnectionPriv->pvSyncConnectionData = (void*)psConnection;
#endif
sPrivData.psDevNode = psDeviceNode;
/* Call environment specific connection data init function */
eError = OSConnectionPrivateDataInit(&psConnection->hOsPrivateData, &sPrivData);
if (eError != PVRSRV_OK)
{
PVR_DPF((PVR_DBG_ERROR, "%s: OSConnectionPrivateDataInit() failed (%s)",
__func__, PVRSRVGetErrorString(eError)));
goto fail_private_data_init;
}
#if defined(SUPPORT_NATIVE_FENCE_SYNC) && !defined(USE_PVRSYNC_DEVNODE)
iErr = pvr_sync_open(pvConnectionData, psDRMFile);
#if (PVRSRV_DEVICE_INIT_MODE == PVRSRV_LINUX_DEV_INIT_ON_CONNECT)
iErr = pvr_sync_open(psConnectionPriv->pvConnectionData, psDRMFile);
#else
iErr = pvr_sync_open(psConnectionPriv->pvSyncConnectionData, psDRMFile);
#endif
if (iErr)
{
PVRSRVCommonConnectionDisconnect(pvConnectionData);
goto out;
PVR_DPF((PVR_DBG_ERROR, "%s: pvr_sync_open() failed(%d)",
__func__, iErr));
goto fail_pvr_sync_open;
}
#endif
psDRMFile->driver_priv = pvConnectionData;
#if defined(SUPPORT_NATIVE_FENCE_SYNC) && !defined(USE_PVRSYNC_DEVNODE)
#if (PVRSRV_DEVICE_INIT_MODE == PVRSRV_LINUX_DEV_INIT_ON_CONNECT)
psConnectionPriv->pfDeviceRelease = pvr_sync_close;
#endif
#endif
psDRMFile->driver_priv = psConnectionPriv;
goto out;
#if defined(SUPPORT_NATIVE_FENCE_SYNC) && !defined(USE_PVRSYNC_DEVNODE)
fail_pvr_sync_open:
OSConnectionPrivateDataDeInit(psConnection->hOsPrivateData);
#endif
fail_private_data_init:
kfree(psConnection);
fail_alloc_connection:
kfree(psConnectionPriv);
out:
return iErr;
}
@@ -505,18 +660,63 @@ out:
@Return void
*/ /***************************************************************************/
void PVRSRVDeviceRelease(PVRSRV_DEVICE_NODE *psDeviceNode,
struct drm_file *psDRMFile)
struct drm_file *psDRMFile)
{
void *pvConnectionData = psDRMFile->driver_priv;
PVR_UNREFERENCED_PARAMETER(psDeviceNode);
psDRMFile->driver_priv = NULL;
if (pvConnectionData)
if (psDRMFile->driver_priv)
{
PVRSRV_CONNECTION_PRIV *psConnectionPriv = (PVRSRV_CONNECTION_PRIV*)psDRMFile->driver_priv;
if (psConnectionPriv->pvConnectionData)
{
#if (PVRSRV_DEVICE_INIT_MODE == PVRSRV_LINUX_DEV_INIT_ON_CONNECT)
if (psConnectionPriv->pfDeviceRelease)
{
psConnectionPriv->pfDeviceRelease(psConnectionPriv->pvConnectionData);
}
#else
if (psConnectionPriv->pvConnectionData)
PVRSRVCommonConnectionDisconnect(psConnectionPriv->pvConnectionData);
#if defined(SUPPORT_NATIVE_FENCE_SYNC) && !defined(USE_PVRSYNC_DEVNODE)
pvr_sync_close(pvConnectionData);
if (psConnectionPriv->pvSyncConnectionData)
pvr_sync_close(psConnectionPriv->pvSyncConnectionData);
#endif
PVRSRVCommonConnectionDisconnect(pvConnectionData);
#endif
}
kfree(psDRMFile->driver_priv);
psDRMFile->driver_priv = NULL;
}
}
int
drm_pvr_srvkm_init(struct drm_device *dev, void *arg, struct drm_file *psDRMFile)
{
struct drm_pvr_srvkm_init_data *data = arg;
struct pvr_drm_private *priv = dev->dev_private;
int iErr = 0;
switch (data->init_module)
{
case PVR_SRVKM_SYNC_INIT:
{
iErr = PVRSRVDeviceSyncOpen(priv->dev_node, psDRMFile);
break;
}
case PVR_SRVKM_SERVICES_INIT:
{
iErr = PVRSRVDeviceServicesOpen(priv->dev_node, psDRMFile);
break;
}
default:
{
PVR_DPF((PVR_DBG_ERROR, "%s: invalid init_module (%d)",
__func__, data->init_module));
iErr = -EINVAL;
}
}
return iErr;
}

40
drivers/gpu/drm/img-rogue/module_common.h
View File

@@ -43,11 +43,43 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#ifndef MODULE_COMMON_H
#define MODULE_COMMON_H
#include "pvr_drm.h"
/* DRVNAME is the name we use to register our driver. */
#define DRVNAME PVR_LDM_DRIVER_REGISTRATION_NAME
struct _PVRSRV_DEVICE_NODE_;
struct drm_file;
struct drm_device;
/* psDRMFile->driver_priv will point to a PVRSV_CONNECTION_PRIV
* struct, which will contain a ptr to the CONNECTION_DATA and
* a pfn to the release function (which will differ depending
* on whether the connection is to Sync or Services).
*/
typedef void (*PFN_PVRSRV_DEV_RELEASE)(void *pvData);
typedef struct
{
/* pvConnectionData is used to hold Services connection data
* for all PVRSRV_DEVICE_INIT_MODE options.
*/
void *pvConnectionData;
/* pfDeviceRelease is used to indicate the release function
* to be called when PVRSRV_DEVICE_INIT_MODE is PVRSRV_LINUX_DEV_INIT_ON_CONNECT,
* as we can then have one connections made (either for Services or Sync) per
* psDRMFile, and need to know which type of connection is being released
* (as the ioctl release call is common for both).
*/
PFN_PVRSRV_DEV_RELEASE pfDeviceRelease;
/* pvSyncConnectionData is used to hold Sync connection data
* when PVRSRV_DEVICE_INIT_MODE is not PVRSRV_LINUX_DEV_INIT_ON_CONNECT,
* as we can then have two connections made (for Services and Sync) to
* the same psDRMFile.
*/
void *pvSyncConnectionData;
} PVRSRV_CONNECTION_PRIV;
int PVRSRVDriverInit(void);
void PVRSRVDriverDeinit(void);
@@ -59,9 +91,11 @@ void PVRSRVDeviceShutdown(struct _PVRSRV_DEVICE_NODE_ *psDeviceNode);
int PVRSRVDeviceSuspend(struct _PVRSRV_DEVICE_NODE_ *psDeviceNode);
int PVRSRVDeviceResume(struct _PVRSRV_DEVICE_NODE_ *psDeviceNode);
int PVRSRVDeviceOpen(struct _PVRSRV_DEVICE_NODE_ *psDeviceNode,
struct drm_file *psDRMFile);
int PVRSRVDeviceServicesOpen(struct _PVRSRV_DEVICE_NODE_ *psDeviceNode,
struct drm_file *psDRMFile);
void PVRSRVDeviceRelease(struct _PVRSRV_DEVICE_NODE_ *psDeviceNode,
struct drm_file *psDRMFile);
struct drm_file *psDRMFile);
int drm_pvr_srvkm_init(struct drm_device *dev,
void *arg, struct drm_file *psDRMFile);
#endif /* MODULE_COMMON_H */

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