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f72e7cd077
This version update involves a lot of content, so the previous version has been deleted and the new version has been re-merged into the kernel. The configuration file for the GPU driver originates from a previous version. Signed-off-by: Mingzheng Xing <xingmingzheng@iscas.ac.cn>
829 lines
32 KiB
C
829 lines
32 KiB
C
/*************************************************************************/ /*!
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@File
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@Title RGX device node header file
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@Copyright Copyright (c) Imagination Technologies Ltd. All Rights Reserved
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@Description Header for the RGX device node
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@License Dual MIT/GPLv2
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The contents of this file are subject to the MIT license as set out below.
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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Alternatively, the contents of this file may be used under the terms of
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the GNU General Public License Version 2 ("GPL") in which case the provisions
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of GPL are applicable instead of those above.
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If you wish to allow use of your version of this file only under the terms of
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GPL, and not to allow others to use your version of this file under the terms
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of the MIT license, indicate your decision by deleting the provisions above
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and replace them with the notice and other provisions required by GPL as set
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out in the file called "GPL-COPYING" included in this distribution. If you do
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not delete the provisions above, a recipient may use your version of this file
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under the terms of either the MIT license or GPL.
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This License is also included in this distribution in the file called
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"MIT-COPYING".
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EXCEPT AS OTHERWISE STATED IN A NEGOTIATED AGREEMENT: (A) THE SOFTWARE IS
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PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
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BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
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PURPOSE AND NONINFRINGEMENT; AND (B) IN NO EVENT SHALL THE AUTHORS OR
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COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/ /**************************************************************************/
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#if !defined(RGXDEVICE_H)
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#define RGXDEVICE_H
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#include "img_types.h"
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#include "img_defs.h"
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#include "pvrsrv_device_types.h"
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#include "mmu_common.h"
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#include "rgx_fwif_km.h"
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#include "cache_ops.h"
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#include "device.h"
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#include "osfunc.h"
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#include "rgxlayer_impl.h"
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#if defined(SUPPORT_WORKLOAD_ESTIMATION)
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#include "hash.h"
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#endif
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typedef struct _RGX_SERVER_COMMON_CONTEXT_ RGX_SERVER_COMMON_CONTEXT;
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typedef struct {
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DEVMEM_MEMDESC *psFWFrameworkMemDesc;
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} RGX_COMMON_CONTEXT_INFO;
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/*!
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******************************************************************************
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* Device state flags
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*****************************************************************************/
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#define RGXKM_DEVICE_STATE_ZERO_FREELIST (0x1) /*!< Zeroing the physical pages of reconstructed free lists */
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#define RGXKM_DEVICE_STATE_DISABLE_DW_LOGGING_EN (0x2) /*!< Used to disable the Devices Watchdog logging */
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#define RGXKM_DEVICE_STATE_GPU_UNITS_POWER_CHANGE_EN (0x4) /*!< Used for validation to inject dust requests every TA/3D kick */
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#define RGXKM_DEVICE_STATE_CCB_GROW_EN (0x8) /*!< Used to indicate CCB grow is permitted */
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#define RGXKM_DEVICE_STATE_ENABLE_SPU_UNITS_POWER_MASK_CHANGE_EN (0x10) /*!< Used for validation to enable SPU power state mask change */
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#define RGXKM_DEVICE_STATE_MASK (0x1F)
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/*!
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******************************************************************************
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* ECC RAM Fault Validation
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*****************************************************************************/
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#define RGXKM_ECC_ERR_INJ_DISABLE 0
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#define RGXKM_ECC_ERR_INJ_SLC 1
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#define RGXKM_ECC_ERR_INJ_USC 2
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#define RGXKM_ECC_ERR_INJ_TPU 3
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#define RGXKM_ECC_ERR_INJ_RASCAL 4
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#define RGXKM_ECC_ERR_INJ_MARS 5
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#define RGXKM_ECC_ERR_INJ_INTERVAL 10U
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/*!
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******************************************************************************
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* GPU DVFS Table
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*****************************************************************************/
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#define RGX_GPU_DVFS_TABLE_SIZE 32
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#define RGX_GPU_DVFS_FIRST_CALIBRATION_TIME_US 25000 /* Time required to calibrate a clock frequency the first time */
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#define RGX_GPU_DVFS_TRANSITION_CALIBRATION_TIME_US 150000 /* Time required for a recalibration after a DVFS transition */
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#define RGX_GPU_DVFS_PERIODIC_CALIBRATION_TIME_US 10000000 /* Time before the next periodic calibration and correlation */
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/*!
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******************************************************************************
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* Global flags for driver validation
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*****************************************************************************/
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#define RGX_VAL_KZ_SIG_CHECK_NOERR_EN (0x10U) /*!< Enable KZ signature check. Signatures must match */
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#define RGX_VAL_KZ_SIG_CHECK_ERR_EN (0x20U) /*!< Enable KZ signature check. Signatures must not match */
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#define RGX_VAL_SIG_CHECK_ERR_EN (0U) /*!< Not supported on Rogue cores */
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typedef struct _GPU_FREQ_TRACKING_DATA_
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{
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/* Core clock speed estimated by the driver */
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IMG_UINT32 ui32EstCoreClockSpeed;
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/* Amount of successful calculations of the estimated core clock speed */
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IMG_UINT32 ui32CalibrationCount;
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} GPU_FREQ_TRACKING_DATA;
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#if defined(PVRSRV_TIMER_CORRELATION_HISTORY)
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#define RGX_GPU_FREQ_TRACKING_SIZE 16
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typedef struct
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{
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IMG_UINT64 ui64BeginCRTimestamp;
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IMG_UINT64 ui64BeginOSTimestamp;
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IMG_UINT64 ui64EndCRTimestamp;
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IMG_UINT64 ui64EndOSTimestamp;
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IMG_UINT32 ui32EstCoreClockSpeed;
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IMG_UINT32 ui32CoreClockSpeed;
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} GPU_FREQ_TRACKING_HISTORY;
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#endif
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typedef struct _RGX_GPU_DVFS_TABLE_
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{
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/* Beginning of current calibration period (in us) */
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IMG_UINT64 ui64CalibrationCRTimestamp;
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IMG_UINT64 ui64CalibrationOSTimestamp;
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/* Calculated calibration period (in us) */
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IMG_UINT64 ui64CalibrationCRTimediff;
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IMG_UINT64 ui64CalibrationOSTimediff;
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/* Current calibration period (in us) */
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IMG_UINT32 ui32CalibrationPeriod;
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/* System layer frequency table and frequency tracking data */
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IMG_UINT32 ui32FreqIndex;
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IMG_UINT32 aui32GPUFrequency[RGX_GPU_DVFS_TABLE_SIZE];
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GPU_FREQ_TRACKING_DATA asTrackingData[RGX_GPU_DVFS_TABLE_SIZE];
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#if defined(PVRSRV_TIMER_CORRELATION_HISTORY)
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IMG_UINT32 ui32HistoryIndex;
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GPU_FREQ_TRACKING_HISTORY asTrackingHistory[RGX_GPU_FREQ_TRACKING_SIZE];
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#endif
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} RGX_GPU_DVFS_TABLE;
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/*!
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******************************************************************************
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* GPU utilisation statistics
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*****************************************************************************/
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typedef struct _RGXFWIF_GPU_UTIL_STATS_
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{
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IMG_BOOL bValid; /* If TRUE, statistics are valid.
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FALSE if the driver couldn't get reliable stats. */
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IMG_UINT64 ui64GpuStatActive; /* GPU active statistic */
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IMG_UINT64 ui64GpuStatBlocked; /* GPU blocked statistic */
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IMG_UINT64 ui64GpuStatIdle; /* GPU idle statistic */
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IMG_UINT64 ui64GpuStatCumulative; /* Sum of active/blocked/idle stats */
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IMG_UINT64 ui64TimeStamp; /* Timestamp of the most recent sample of the GPU stats */
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} RGXFWIF_GPU_UTIL_STATS;
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typedef struct _RGX_REG_CONFIG_
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{
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IMG_BOOL bEnabled;
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RGXFWIF_REG_CFG_TYPE eRegCfgTypeToPush;
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IMG_UINT32 ui32NumRegRecords;
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POS_LOCK hLock;
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} RGX_REG_CONFIG;
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typedef struct _PVRSRV_STUB_PBDESC_ PVRSRV_STUB_PBDESC;
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typedef struct
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{
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IMG_UINT32 ui32DustCount1;
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IMG_UINT32 ui32DustCount2;
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IMG_BOOL bToggle;
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} RGX_DUST_STATE;
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typedef struct _PVRSRV_DEVICE_FEATURE_CONFIG_
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{
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IMG_UINT64 ui64ErnsBrns;
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IMG_UINT64 ui64Features;
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IMG_UINT32 ui32B;
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IMG_UINT32 ui32V;
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IMG_UINT32 ui32N;
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IMG_UINT32 ui32C;
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IMG_UINT32 ui32FeaturesValues[RGX_FEATURE_WITH_VALUES_MAX_IDX];
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IMG_UINT32 ui32MAXDMCount;
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IMG_UINT32 ui32MAXDustCount;
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IMG_UINT32 ui32SLCSizeInBytes;
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IMG_PCHAR pszBVNCString;
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}PVRSRV_DEVICE_FEATURE_CONFIG;
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/* This is used to get the value of a specific feature.
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* Note that it will assert if the feature is disabled or value is invalid. */
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#define RGX_GET_FEATURE_VALUE(psDevInfo, Feature) \
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( psDevInfo->sDevFeatureCfg.ui32FeaturesValues[RGX_FEATURE_##Feature##_IDX] )
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/* This is used to check if the feature value (e.g. with an integer value) is available for the currently running BVNC or not */
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#define RGX_IS_FEATURE_VALUE_SUPPORTED(psDevInfo, Feature) \
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( psDevInfo->sDevFeatureCfg.ui32FeaturesValues[RGX_FEATURE_##Feature##_IDX] < RGX_FEATURE_VALUE_DISABLED )
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/* This is used to check if the Boolean feature (e.g. WITHOUT an integer value) is available for the currently running BVNC or not */
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#define RGX_IS_FEATURE_SUPPORTED(psDevInfo, Feature) \
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BITMASK_HAS(psDevInfo->sDevFeatureCfg.ui64Features, RGX_FEATURE_##Feature##_BIT_MASK)
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/* This is used to check if the ERN is available for the currently running BVNC or not */
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#define RGX_IS_ERN_SUPPORTED(psDevInfo, ERN) \
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BITMASK_HAS(psDevInfo->sDevFeatureCfg.ui64ErnsBrns, HW_ERN_##ERN##_BIT_MASK)
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/* This is used to check if the BRN is available for the currently running BVNC or not */
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#define RGX_IS_BRN_SUPPORTED(psDevInfo, BRN) \
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BITMASK_HAS(psDevInfo->sDevFeatureCfg.ui64ErnsBrns, FIX_HW_BRN_##BRN##_BIT_MASK)
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/* there is a corresponding define in rgxapi.h */
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#define RGX_MAX_TIMER_QUERIES 16U
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#if defined(SUPPORT_WORKLOAD_ESTIMATION)
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/*!
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* The host maintains a 512-deep cache of submitted workloads per device,
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* i.e. a global look-up table for TA, 3D and compute (depending on the RGX
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* hardware support present)
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*/
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/*
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* For the workload estimation return data array, the max amount of commands the
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* MTS can have is 255, therefore 512 (LOG2 = 9) is large enough to account for
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* all corner cases
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*/
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#define RETURN_DATA_ARRAY_SIZE_LOG2 (9)
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#define RETURN_DATA_ARRAY_SIZE ((1U) << RETURN_DATA_ARRAY_SIZE_LOG2)
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#define RETURN_DATA_ARRAY_WRAP_MASK (RETURN_DATA_ARRAY_SIZE - 1)
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#define WORKLOAD_HASH_SIZE_LOG2 6
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#define WORKLOAD_HASH_SIZE ((1U) << WORKLOAD_HASH_SIZE_LOG2)
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#define WORKLOAD_HASH_WRAP_MASK (WORKLOAD_HASH_SIZE - 1)
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/*!
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* Workload characteristics for supported data masters.
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* All characteristics must match for the workload estimate to be used/updated.
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*/
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typedef union _RGX_WORKLOAD_
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{
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struct
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{
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IMG_UINT32 ui32RenderTargetSize;
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IMG_UINT32 ui32NumberOfDrawCalls;
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IMG_UINT32 ui32NumberOfIndices;
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IMG_UINT32 ui32NumberOfMRTs;
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} sTA3D;
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struct
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{
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IMG_UINT32 ui32NumberOfWorkgroups;
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IMG_UINT32 ui32NumberOfWorkitems;
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} sCompute;
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struct
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{
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IMG_UINT32 ui32Characteristic1;
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IMG_UINT32 ui32Characteristic2;
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} sTransfer;
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} RGX_WORKLOAD;
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/*!
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* Host data used to match the return data (actual cycles count) to the
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* submitted command packet.
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* The hash table is a per-DM circular buffer containing a key based on the
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* workload characteristics. On job completion, the oldest workload data
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* is evicted if the CB is full and the driver matches the characteristics
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* to the matching data.
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*
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* o If the driver finds a match the existing cycle estimate is averaged with
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* the actual cycles used.
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* o Otherwise a new hash entry is created with the actual cycles for this
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* workload.
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*
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* Subsequently if a match is found during command submission, the estimate
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* is passed to the scheduler, e.g. adjust the GPU frequency if PDVFS is enabled.
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*/
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typedef struct _WORKLOAD_MATCHING_DATA_
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{
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POS_LOCK psHashLock;
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HASH_TABLE *psHashTable; /*! existing workload cycle estimates for this DM */
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RGX_WORKLOAD asHashKeys[WORKLOAD_HASH_SIZE];
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IMG_UINT64 aui64HashData[WORKLOAD_HASH_SIZE];
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IMG_UINT32 ui32HashArrayWO; /*! track the most recent workload estimates */
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} WORKLOAD_MATCHING_DATA;
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/*!
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* A generic container for the workload matching data for GPU contexts:
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* rendering (TA, 3D), compute, etc.
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*/
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typedef struct _WORKEST_HOST_DATA_
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{
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union
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{
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struct
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{
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WORKLOAD_MATCHING_DATA sDataTA; /*!< matching data for TA commands */
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WORKLOAD_MATCHING_DATA sData3D; /*!< matching data for 3D commands */
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} sTA3D;
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struct
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{
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WORKLOAD_MATCHING_DATA sDataCDM; /*!< matching data for CDM commands */
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} sCompute;
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struct
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{
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WORKLOAD_MATCHING_DATA sDataTDM; /*!< matching data for TDM-TQ commands */
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} sTransfer;
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} uWorkloadMatchingData;
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/*
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* This is a per-context property, hence the TA and 3D share the same
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* per render context counter.
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*/
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IMG_UINT32 ui32WorkEstCCBReceived; /*!< Used to ensure all submitted work
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estimation commands are received
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by the host before clean up. */
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} WORKEST_HOST_DATA;
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/*!
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* Entries in the list of submitted workloads, used when the completed command
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* returns data to the host.
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*
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* - the matching data is needed as it holds the hash data
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* - the host data is needed for completion updates, ensuring memory is not
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* freed while workload estimates are in-flight.
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* - the workload characteristic is used in the hash table look-up.
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*/
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typedef struct _WORKEST_RETURN_DATA_
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{
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WORKEST_HOST_DATA *psWorkEstHostData;
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WORKLOAD_MATCHING_DATA *psWorkloadMatchingData;
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RGX_WORKLOAD sWorkloadCharacteristics;
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} WORKEST_RETURN_DATA;
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#endif
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typedef struct
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{
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#if defined(PDUMP)
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IMG_HANDLE hPdumpPages;
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#endif
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PG_HANDLE sPages;
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IMG_DEV_PHYADDR sPhysAddr;
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} RGX_MIPS_ADDRESS_TRAMPOLINE;
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/*!
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******************************************************************************
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* RGX Device error counts
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*****************************************************************************/
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typedef struct _PVRSRV_RGXDEV_ERROR_COUNTS_
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{
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IMG_UINT32 ui32WGPErrorCount; /*!< count of the number of WGP checksum errors */
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IMG_UINT32 ui32TRPErrorCount; /*!< count of the number of TRP checksum errors */
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} PVRSRV_RGXDEV_ERROR_COUNTS;
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/*!
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******************************************************************************
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* RGX Device info
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*****************************************************************************/
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typedef struct _PVRSRV_RGXDEV_INFO_
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{
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PVRSRV_DEVICE_NODE *psDeviceNode;
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PVRSRV_DEVICE_FEATURE_CONFIG sDevFeatureCfg;
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IMG_BOOL bDevInit2Done;
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IMG_BOOL bFirmwareInitialised;
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IMG_BOOL bPDPEnabled;
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IMG_HANDLE hDbgReqNotify;
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/* Kernel mode linear address of device registers */
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void __iomem *pvRegsBaseKM;
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IMG_HANDLE hRegMapping;
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/* System physical address of device registers */
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IMG_CPU_PHYADDR sRegsPhysBase;
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/* Register region size in bytes */
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IMG_UINT32 ui32RegSize;
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PVRSRV_STUB_PBDESC *psStubPBDescListKM;
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/* Firmware memory context info */
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DEVMEM_CONTEXT *psKernelDevmemCtx;
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DEVMEM_HEAP *psFirmwareMainHeap;
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DEVMEM_HEAP *psFirmwareConfigHeap;
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MMU_CONTEXT *psKernelMMUCtx;
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void *pvDeviceMemoryHeap;
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/* Kernel CCB */
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DEVMEM_MEMDESC *psKernelCCBCtlMemDesc; /*!< memdesc for Kernel CCB control */
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RGXFWIF_CCB_CTL *psKernelCCBCtl; /*!< kernel mapping for Kernel CCB control */
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DEVMEM_MEMDESC *psKernelCCBMemDesc; /*!< memdesc for Kernel CCB */
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IMG_UINT8 *psKernelCCB; /*!< kernel mapping for Kernel CCB */
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DEVMEM_MEMDESC *psKernelCCBRtnSlotsMemDesc; /*!< Return slot array for Kernel CCB commands */
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IMG_UINT32 *pui32KernelCCBRtnSlots; /*!< kernel mapping for return slot array */
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/* Firmware CCB */
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DEVMEM_MEMDESC *psFirmwareCCBCtlMemDesc; /*!< memdesc for Firmware CCB control */
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RGXFWIF_CCB_CTL *psFirmwareCCBCtl; /*!< kernel mapping for Firmware CCB control */
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DEVMEM_MEMDESC *psFirmwareCCBMemDesc; /*!< memdesc for Firmware CCB */
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IMG_UINT8 *psFirmwareCCB; /*!< kernel mapping for Firmware CCB */
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/* Workload Estimation Firmware CCB */
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DEVMEM_MEMDESC *psWorkEstFirmwareCCBCtlMemDesc; /*!< memdesc for Workload Estimation Firmware CCB control */
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RGXFWIF_CCB_CTL *psWorkEstFirmwareCCBCtl; /*!< kernel mapping for Workload Estimation Firmware CCB control */
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DEVMEM_MEMDESC *psWorkEstFirmwareCCBMemDesc; /*!< memdesc for Workload Estimation Firmware CCB */
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IMG_UINT8 *psWorkEstFirmwareCCB; /*!< kernel mapping for Workload Estimation Firmware CCB */
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#if defined(SUPPORT_POWER_SAMPLING_VIA_DEBUGFS)
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/* Counter dumping */
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DEVMEM_MEMDESC *psCounterBufferMemDesc; /*!< mem desc for counter dumping buffer */
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POS_LOCK hCounterDumpingLock; /*!< Lock for guarding access to counter dumping buffer */
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#endif
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PVRSRV_MEMALLOCFLAGS_T uiFWPoisonOnFreeFlag; /*!< Flag for poisoning FW allocations when freed */
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IMG_BOOL bIgnoreHWReportedBVNC; /*!< Ignore BVNC reported by HW */
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/*
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if we don't preallocate the pagetables we must
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insert newly allocated page tables dynamically
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*/
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void *pvMMUContextList;
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IMG_UINT32 ui32ClkGateStatusReg;
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IMG_UINT32 ui32ClkGateStatusMask;
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DEVMEM_MEMDESC *psRGXFWCodeMemDesc;
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IMG_DEV_VIRTADDR sFWCodeDevVAddrBase;
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IMG_UINT32 ui32FWCodeSizeInBytes;
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DEVMEM_MEMDESC *psRGXFWDataMemDesc;
|
|
IMG_DEV_VIRTADDR sFWDataDevVAddrBase;
|
|
RGX_MIPS_ADDRESS_TRAMPOLINE *psTrampoline;
|
|
|
|
DEVMEM_MEMDESC *psRGXFWCorememCodeMemDesc;
|
|
IMG_DEV_VIRTADDR sFWCorememCodeDevVAddrBase;
|
|
RGXFWIF_DEV_VIRTADDR sFWCorememCodeFWAddr;
|
|
IMG_UINT32 ui32FWCorememCodeSizeInBytes;
|
|
|
|
DEVMEM_MEMDESC *psRGXFWIfCorememDataStoreMemDesc;
|
|
IMG_DEV_VIRTADDR sFWCorememDataStoreDevVAddrBase;
|
|
RGXFWIF_DEV_VIRTADDR sFWCorememDataStoreFWAddr;
|
|
|
|
DEVMEM_MEMDESC *psRGXFWAlignChecksMemDesc;
|
|
|
|
#if defined(PDUMP)
|
|
DEVMEM_MEMDESC *psRGXFWSigTAChecksMemDesc;
|
|
IMG_UINT32 ui32SigTAChecksSize;
|
|
|
|
DEVMEM_MEMDESC *psRGXFWSig3DChecksMemDesc;
|
|
IMG_UINT32 ui32Sig3DChecksSize;
|
|
|
|
DEVMEM_MEMDESC *psRGXFWSigTDM2DChecksMemDesc;
|
|
IMG_UINT32 ui32SigTDM2DChecksSize;
|
|
|
|
IMG_BOOL bDumpedKCCBCtlAlready;
|
|
|
|
POS_SPINLOCK hSyncCheckpointSignalSpinLock; /*!< Guards data shared between an atomic & sleepable-context */
|
|
#endif
|
|
|
|
POS_LOCK hRGXFWIfBufInitLock; /*!< trace buffer lock for initialisation phase */
|
|
|
|
DEVMEM_MEMDESC *psRGXFWIfTraceBufCtlMemDesc; /*!< memdesc of trace buffer control structure */
|
|
DEVMEM_MEMDESC *psRGXFWIfTraceBufferMemDesc[RGXFW_THREAD_NUM]; /*!< memdesc of actual FW trace (log) buffer(s) */
|
|
RGXFWIF_TRACEBUF *psRGXFWIfTraceBufCtl; /*!< structure containing trace control data and actual trace buffer */
|
|
|
|
DEVMEM_MEMDESC *psRGXFWIfFwSysDataMemDesc; /*!< memdesc of the firmware-shared system data structure */
|
|
RGXFWIF_SYSDATA *psRGXFWIfFwSysData; /*!< structure containing trace control data and actual trace buffer */
|
|
|
|
DEVMEM_MEMDESC *psRGXFWIfFwOsDataMemDesc; /*!< memdesc of the firmware-shared os structure */
|
|
RGXFWIF_OSDATA *psRGXFWIfFwOsData; /*!< structure containing trace control data and actual trace buffer */
|
|
|
|
#if defined(SUPPORT_TBI_INTERFACE)
|
|
DEVMEM_MEMDESC *psRGXFWIfTBIBufferMemDesc; /*!< memdesc of actual FW TBI buffer */
|
|
RGXFWIF_DEV_VIRTADDR sRGXFWIfTBIBuffer; /*!< TBI buffer data */
|
|
IMG_UINT32 ui32FWIfTBIBufferSize;
|
|
#endif
|
|
|
|
DEVMEM_MEMDESC *psRGXFWIfHWRInfoBufCtlMemDesc;
|
|
RGXFWIF_HWRINFOBUF *psRGXFWIfHWRInfoBufCtl;
|
|
IMG_UINT32 ui32ClockSource;
|
|
IMG_UINT32 ui32LastClockSource;
|
|
|
|
DEVMEM_MEMDESC *psRGXFWIfGpuUtilFWCbCtlMemDesc;
|
|
RGXFWIF_GPU_UTIL_FWCB *psRGXFWIfGpuUtilFWCb;
|
|
|
|
DEVMEM_MEMDESC *psRGXFWIfHWPerfBufMemDesc;
|
|
IMG_BYTE *psRGXFWIfHWPerfBuf;
|
|
IMG_UINT32 ui32RGXFWIfHWPerfBufSize; /* in bytes */
|
|
|
|
DEVMEM_MEMDESC *psRGXFWIfRegCfgMemDesc;
|
|
|
|
DEVMEM_MEMDESC *psRGXFWIfHWPerfCountersMemDesc;
|
|
|
|
DEVMEM_MEMDESC *psRGXFWIfConnectionCtlMemDesc;
|
|
RGXFWIF_CONNECTION_CTL *psRGXFWIfConnectionCtl;
|
|
|
|
DEVMEM_MEMDESC *psRGXFWHeapGuardPageReserveMemDesc;
|
|
DEVMEM_MEMDESC *psRGXFWIfSysInitMemDesc;
|
|
RGXFWIF_SYSINIT *psRGXFWIfSysInit;
|
|
|
|
DEVMEM_MEMDESC *psRGXFWIfOsInitMemDesc;
|
|
RGXFWIF_OSINIT *psRGXFWIfOsInit;
|
|
|
|
DEVMEM_MEMDESC *psRGXFWIfRuntimeCfgMemDesc;
|
|
RGXFWIF_RUNTIME_CFG *psRGXFWIfRuntimeCfg;
|
|
|
|
/* Additional guest firmware memory context info */
|
|
DEVMEM_HEAP *psGuestFirmwareRawHeap[RGX_NUM_OS_SUPPORTED];
|
|
DEVMEM_MEMDESC *psGuestFirmwareRawMemDesc[RGX_NUM_OS_SUPPORTED];
|
|
|
|
#if defined(SUPPORT_WORKLOAD_ESTIMATION)
|
|
/* Array to store data needed for workload estimation when a workload
|
|
has finished and its cycle time is returned to the host. */
|
|
WORKEST_RETURN_DATA asReturnData[RETURN_DATA_ARRAY_SIZE];
|
|
IMG_UINT32 ui32ReturnDataWO;
|
|
POS_LOCK hWorkEstLock;
|
|
#endif
|
|
|
|
#if defined(SUPPORT_PDVFS)
|
|
/**
|
|
* Host memdesc and pointer to memory containing core clock rate in Hz.
|
|
* Firmware updates the memory on changing the core clock rate over GPIO.
|
|
* Note: Shared memory needs atomic access from Host driver and firmware,
|
|
* hence size should not be greater than memory transaction granularity.
|
|
* Currently it is chosen to be 32 bits.
|
|
*/
|
|
DEVMEM_MEMDESC *psRGXFWIFCoreClkRateMemDesc;
|
|
volatile IMG_UINT32 *pui32RGXFWIFCoreClkRate;
|
|
/**
|
|
* Last sampled core clk rate.
|
|
*/
|
|
volatile IMG_UINT32 ui32CoreClkRateSnapshot;
|
|
#endif
|
|
|
|
/*
|
|
HWPerf data for the RGX device
|
|
*/
|
|
|
|
POS_LOCK hHWPerfLock; /*! Critical section lock that protects HWPerf code
|
|
* from multiple thread duplicate init/deinit
|
|
* and loss/freeing of FW & Host resources while in
|
|
* use in another thread e.g. MSIR. */
|
|
|
|
IMG_UINT64 ui64HWPerfFilter; /*! Event filter for FW events (settable by AppHint) */
|
|
IMG_HANDLE hHWPerfStream; /*! TL Stream buffer (L2) for firmware event stream */
|
|
IMG_UINT32 ui32L2BufMaxPacketSize;/*!< Max allowed packet size in FW HWPerf TL (L2) buffer */
|
|
IMG_BOOL bSuspendHWPerfL2DataCopy; /*! Flag to indicate if copying HWPerf data is suspended */
|
|
|
|
IMG_UINT32 ui32HWPerfHostFilter; /*! Event filter for HWPerfHost stream (settable by AppHint) */
|
|
POS_LOCK hLockHWPerfHostStream; /*! Lock guarding access to HWPerfHost stream from multiple threads */
|
|
IMG_HANDLE hHWPerfHostStream; /*! TL Stream buffer for host only event stream */
|
|
IMG_UINT32 ui32HWPerfHostBufSize; /*! Host side buffer size in bytes */
|
|
IMG_UINT32 ui32HWPerfHostLastOrdinal; /*! Ordinal of the last packet emitted in HWPerfHost TL stream.
|
|
* Guarded by hLockHWPerfHostStream */
|
|
IMG_UINT32 ui32HWPerfHostNextOrdinal; /*! Ordinal number for HWPerfHost events. Guarded by hHWPerfHostSpinLock */
|
|
IMG_UINT8 *pui8DeferredEvents; /*! List of HWPerfHost events yet to be emitted in the TL stream.
|
|
* Events generated from atomic context are deferred "emitted"
|
|
* as the "emission" code can sleep */
|
|
IMG_UINT16 ui16DEReadIdx; /*! Read index in the above deferred events buffer */
|
|
IMG_UINT16 ui16DEWriteIdx; /*! Write index in the above deferred events buffer */
|
|
void *pvHostHWPerfMISR; /*! MISR to emit pending/deferred events in HWPerfHost TL stream */
|
|
POS_SPINLOCK hHWPerfHostSpinLock; /*! Guards data shared between an atomic & sleepable-context */
|
|
#if defined(PVRSRV_HWPERF_HOST_DEBUG_DEFERRED_EVENTS)
|
|
IMG_UINT32 ui32DEHighWatermark; /*! High watermark of deferred events buffer usage. Protected by
|
|
*! hHWPerfHostSpinLock */
|
|
/* Max number of times DeferredEmission waited for an atomic-context to "finish" packet write */
|
|
IMG_UINT32 ui32WaitForAtomicCtxPktHighWatermark; /*! Protected by hLockHWPerfHostStream */
|
|
/* Whether warning has been logged about an atomic-context packet loss (due to too long wait for "write" finish) */
|
|
IMG_BOOL bWarnedAtomicCtxPktLost;
|
|
/* Max number of times DeferredEmission scheduled-out to give a chance to the right-ordinal packet to be emitted */
|
|
IMG_UINT32 ui32WaitForRightOrdPktHighWatermark; /*! Protected by hLockHWPerfHostStream */
|
|
/* Whether warning has been logged about an packet loss (due to too long wait for right ordinal to emit) */
|
|
IMG_BOOL bWarnedPktOrdinalBroke;
|
|
#endif
|
|
|
|
void *pvGpuFtraceData;
|
|
|
|
/* Poll data for detecting firmware fatal errors */
|
|
IMG_UINT32 aui32CrLastPollCount[RGXFW_THREAD_NUM];
|
|
IMG_UINT32 ui32KCCBCmdsExecutedLastTime;
|
|
IMG_BOOL bKCCBCmdsWaitingLastTime;
|
|
IMG_UINT32 ui32GEOTimeoutsLastTime;
|
|
IMG_UINT32 ui32InterruptCountLastTime;
|
|
IMG_UINT32 ui32MissingInterruptsLastTime;
|
|
|
|
/* Client stall detection */
|
|
IMG_UINT32 ui32StalledClientMask;
|
|
|
|
IMG_BOOL bWorkEstEnabled;
|
|
IMG_BOOL bPDVFSEnabled;
|
|
|
|
void *pvLISRData;
|
|
void *pvMISRData;
|
|
void *pvAPMISRData;
|
|
RGX_ACTIVEPM_CONF eActivePMConf;
|
|
|
|
volatile IMG_UINT32 aui32SampleIRQCount[RGXFW_THREAD_NUM];
|
|
|
|
DEVMEM_MEMDESC *psRGXFaultAddressMemDesc;
|
|
|
|
DEVMEM_MEMDESC *psSLC3FenceMemDesc;
|
|
|
|
/* If we do 10 deferred memory allocations per second, then the ID would wrap around after 13 years */
|
|
IMG_UINT32 ui32ZSBufferCurrID; /*!< ID assigned to the next deferred devmem allocation */
|
|
IMG_UINT32 ui32FreelistCurrID; /*!< ID assigned to the next freelist */
|
|
|
|
POS_LOCK hLockZSBuffer; /*!< Lock to protect simultaneous access to ZSBuffers */
|
|
DLLIST_NODE sZSBufferHead; /*!< List of on-demand ZSBuffers */
|
|
POS_LOCK hLockFreeList; /*!< Lock to protect simultaneous access to Freelists */
|
|
DLLIST_NODE sFreeListHead; /*!< List of growable Freelists */
|
|
PSYNC_PRIM_CONTEXT hSyncPrimContext;
|
|
PVRSRV_CLIENT_SYNC_PRIM *psPowSyncPrim;
|
|
|
|
IMG_UINT32 ui32ActivePMReqOk;
|
|
IMG_UINT32 ui32ActivePMReqDenied;
|
|
IMG_UINT32 ui32ActivePMReqNonIdle;
|
|
IMG_UINT32 ui32ActivePMReqRetry;
|
|
IMG_UINT32 ui32ActivePMReqTotal;
|
|
|
|
IMG_HANDLE hProcessQueuesMISR;
|
|
|
|
IMG_UINT32 ui32DeviceFlags; /*!< Flags to track general device state */
|
|
|
|
/* GPU DVFS Table */
|
|
RGX_GPU_DVFS_TABLE *psGpuDVFSTable;
|
|
|
|
/* Pointer to function returning the GPU utilisation statistics since the last
|
|
* time the function was called. Supports different users at the same time.
|
|
*
|
|
* psReturnStats [out]: GPU utilisation statistics (active high/active low/idle/blocked)
|
|
* in microseconds since the last time the function was called
|
|
* by a specific user (identified by hGpuUtilUser)
|
|
*
|
|
* Returns PVRSRV_OK in case the call completed without errors,
|
|
* some other value otherwise.
|
|
*/
|
|
PVRSRV_ERROR (*pfnGetGpuUtilStats) (PVRSRV_DEVICE_NODE *psDeviceNode,
|
|
IMG_HANDLE hGpuUtilUser,
|
|
RGXFWIF_GPU_UTIL_STATS *psReturnStats);
|
|
|
|
/* Pointer to function that checks if the physical GPU IRQ
|
|
* line has been asserted and clears it if so */
|
|
IMG_BOOL (*pfnRGXAckIrq) (struct _PVRSRV_RGXDEV_INFO_ *psDevInfo);
|
|
|
|
POS_LOCK hGPUUtilLock;
|
|
|
|
/* Register configuration */
|
|
RGX_REG_CONFIG sRegCongfig;
|
|
|
|
IMG_BOOL bRGXPowered;
|
|
DLLIST_NODE sMemoryContextList;
|
|
|
|
POSWR_LOCK hRenderCtxListLock;
|
|
POSWR_LOCK hComputeCtxListLock;
|
|
POSWR_LOCK hTransferCtxListLock;
|
|
POSWR_LOCK hTDMCtxListLock;
|
|
POSWR_LOCK hMemoryCtxListLock;
|
|
POSWR_LOCK hKickSyncCtxListLock;
|
|
|
|
/* Linked list of deferred KCCB commands due to a full KCCB.
|
|
* Access to members sKCCBDeferredCommandsListHead and ui32KCCBDeferredCommandsCount
|
|
* are protected by the hLockKCCBDeferredCommandsList spin lock. */
|
|
POS_SPINLOCK hLockKCCBDeferredCommandsList; /*!< Protects deferred KCCB commands list */
|
|
DLLIST_NODE sKCCBDeferredCommandsListHead;
|
|
IMG_UINT32 ui32KCCBDeferredCommandsCount; /*!< No of commands in the deferred list */
|
|
|
|
/* Linked lists of contexts on this device */
|
|
DLLIST_NODE sRenderCtxtListHead;
|
|
DLLIST_NODE sComputeCtxtListHead;
|
|
DLLIST_NODE sTransferCtxtListHead;
|
|
DLLIST_NODE sTDMCtxtListHead;
|
|
DLLIST_NODE sKickSyncCtxtListHead;
|
|
|
|
DLLIST_NODE sCommonCtxtListHead;
|
|
POSWR_LOCK hCommonCtxtListLock;
|
|
IMG_UINT32 ui32CommonCtxtCurrentID; /*!< ID assigned to the next common context */
|
|
|
|
POS_LOCK hDebugFaultInfoLock; /*!< Lock to protect the debug fault info list */
|
|
POS_LOCK hMMUCtxUnregLock; /*!< Lock to protect list of unregistered MMU contexts */
|
|
|
|
POS_LOCK hNMILock; /*!< Lock to protect NMI operations */
|
|
|
|
#if defined(SUPPORT_VALIDATION)
|
|
IMG_UINT32 ui32ValidationFlags; /*!< Validation flags for host driver */
|
|
#endif
|
|
RGX_DUST_STATE sDustReqState;
|
|
|
|
RGX_LAYER_PARAMS sLayerParams;
|
|
|
|
RGXFWIF_DM eBPDM; /*!< Current breakpoint data master */
|
|
IMG_BOOL bBPSet; /*!< A Breakpoint has been set */
|
|
POS_LOCK hBPLock; /*!< Lock for break point operations */
|
|
|
|
IMG_UINT32 ui32CoherencyTestsDone;
|
|
|
|
ATOMIC_T iCCBSubmissionOrdinal; /* Rolling count used to indicate CCB submission order (all CCBs) */
|
|
POS_LOCK hCCBRecoveryLock; /* Lock to protect pvEarliestStalledClientCCB and ui32OldestSubmissionOrdinal variables */
|
|
void *pvEarliestStalledClientCCB; /* Will point to cCCB command to unblock in the event of a stall */
|
|
IMG_UINT32 ui32OldestSubmissionOrdinal; /* Earliest submission ordinal of CCB entry found so far */
|
|
IMG_UINT32 ui32SLRHoldoffCounter; /* Decremented each time health check is called until zero. SLR only happen when zero. */
|
|
|
|
POS_LOCK hCCBStallCheckLock; /* Lock used to guard against multiple threads simultaneously checking for stalled CCBs */
|
|
|
|
#if defined(SUPPORT_FIRMWARE_GCOV)
|
|
/* Firmware gcov buffer */
|
|
DEVMEM_MEMDESC *psFirmwareGcovBufferMemDesc; /*!< mem desc for Firmware gcov dumping buffer */
|
|
IMG_UINT32 ui32FirmwareGcovSize;
|
|
#endif
|
|
|
|
#if defined(SUPPORT_VALIDATION) && defined(SUPPORT_SOC_TIMER)
|
|
struct
|
|
{
|
|
IMG_UINT64 ui64timerGray;
|
|
IMG_UINT64 ui64timerBinary;
|
|
IMG_UINT64 *pui64uscTimers;
|
|
} sRGXTimerValues;
|
|
#endif
|
|
|
|
#if defined(SUPPORT_VALIDATION)
|
|
struct
|
|
{
|
|
IMG_UINT64 ui64RegVal;
|
|
struct completion sRegComp;
|
|
} sFwRegs;
|
|
#endif
|
|
|
|
IMG_HANDLE hTQCLISharedMem; /*!< TQ Client Shared Mem PMR */
|
|
IMG_HANDLE hTQUSCSharedMem; /*!< TQ USC Shared Mem PMR */
|
|
|
|
#if defined(SUPPORT_VALIDATION)
|
|
IMG_UINT32 ui32TestSLRInterval; /* Don't enqueue an update sync checkpoint every nth kick */
|
|
IMG_UINT32 ui32TestSLRCount; /* (used to test SLR operation) */
|
|
IMG_UINT32 ui32SLRSkipFWAddr;
|
|
#endif
|
|
|
|
#if defined(SUPPORT_SECURITY_VALIDATION)
|
|
DEVMEM_MEMDESC *psRGXFWIfSecureBufMemDesc;
|
|
DEVMEM_MEMDESC *psRGXFWIfNonSecureBufMemDesc;
|
|
#endif
|
|
|
|
/* Timer Queries */
|
|
IMG_UINT32 ui32ActiveQueryId; /*!< id of the active line */
|
|
IMG_BOOL bSaveStart; /*!< save the start time of the next kick on the device*/
|
|
IMG_BOOL bSaveEnd; /*!< save the end time of the next kick on the device*/
|
|
|
|
DEVMEM_MEMDESC *psStartTimeMemDesc; /*!< memdesc for Start Times */
|
|
IMG_UINT64 *pui64StartTimeById; /*!< CPU mapping of the above */
|
|
|
|
DEVMEM_MEMDESC *psEndTimeMemDesc; /*!< memdesc for End Timer */
|
|
IMG_UINT64 *pui64EndTimeById; /*!< CPU mapping of the above */
|
|
|
|
IMG_UINT32 aui32ScheduledOnId[RGX_MAX_TIMER_QUERIES]; /*!< kicks Scheduled on QueryId */
|
|
DEVMEM_MEMDESC *psCompletedMemDesc; /*!< kicks Completed on QueryId */
|
|
IMG_UINT32 *pui32CompletedById; /*!< CPU mapping of the above */
|
|
|
|
#if !defined(PVRSRV_USE_BRIDGE_LOCK)
|
|
POS_LOCK hTimerQueryLock; /*!< lock to protect simultaneous access to timer query members */
|
|
#endif
|
|
|
|
PVRSRV_RGXDEV_ERROR_COUNTS sErrorCounts; /*!< struct containing device error counts */
|
|
|
|
IMG_UINT32 ui32HostSafetyEventMask;/*!< mask of the safety events handled by the driver */
|
|
|
|
RGX_CONTEXT_RESET_REASON eLastDeviceError; /*!< device error reported to client */
|
|
#if defined(SUPPORT_VALIDATION)
|
|
IMG_UINT32 ui32ECCRAMErrInjModule;
|
|
IMG_UINT32 ui32ECCRAMErrInjInterval;
|
|
#endif
|
|
|
|
IMG_UINT32 ui32Log2Non4KPgSize; /* Page size of Non4k heap in log2 form */
|
|
} PVRSRV_RGXDEV_INFO;
|
|
|
|
|
|
|
|
typedef struct _RGX_TIMING_INFORMATION_
|
|
{
|
|
/*! GPU default core clock speed in Hz */
|
|
IMG_UINT32 ui32CoreClockSpeed;
|
|
|
|
/*! Active Power Management: GPU actively requests the host driver to be powered off */
|
|
IMG_BOOL bEnableActivePM;
|
|
|
|
/*! Enable the GPU to power off internal Power Islands independently from the host driver */
|
|
IMG_BOOL bEnableRDPowIsland;
|
|
|
|
/*! Active Power Management: Delay between the GPU idle and the request to the host */
|
|
IMG_UINT32 ui32ActivePMLatencyms;
|
|
|
|
} RGX_TIMING_INFORMATION;
|
|
|
|
typedef struct _RGX_DATA_
|
|
{
|
|
/*! Timing information */
|
|
RGX_TIMING_INFORMATION *psRGXTimingInfo;
|
|
} RGX_DATA;
|
|
|
|
|
|
/*
|
|
RGX PDUMP register bank name (prefix)
|
|
*/
|
|
#define RGX_PDUMPREG_NAME "RGXREG"
|
|
#define RGX_TB_PDUMPREG_NAME "EMUREG"
|
|
|
|
#endif /* RGXDEVICE_H */
|