ci: update toolchains

Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
Linux_SDK_V1.4.2
2026-06-21 09:12:28 +02:00 · 2024-01-12 21:53:40 +08:00 · 2024-01-12 21:53:40 +08:00 · 2024-01-12 21:53:40 +08:00 · 2023-09-26 21:55:29 +08:00 · 2023-09-26 21:55:29 +08:00
29 changed files with 906 additions and 42 deletions
--- a/.github/workflows/build.yml
+++ b/.github/workflows/build.yml
@@ -0,0 +1,64 @@
+name: thead-opensbi
+
+on:
+  push:
+  pull_request:
+  workflow_dispatch:
+  schedule:
+    - cron: "0 2 * * *"
+
+env:
+  xuantie_toolchain: https://occ-oss-prod.oss-cn-hangzhou.aliyuncs.com/resource//1698113812618
+  toolchain_file_name: Xuantie-900-gcc-linux-5.10.4-glibc-x86_64-V2.8.0-20231018.tar.gz
+  mainline_toolchain: https://github.com/riscv-collab/riscv-gnu-toolchain/releases/download/2023.10.18
+  mainline_toolchain_file_name: riscv64-glibc-ubuntu-22.04-gcc-nightly-2023.10.18-nightly.tar.gz
+  wget_alias: 'wget --retry-connrefused --waitretry=1 --read-timeout=20 --timeout=15 -t 0'
+  ARCH: riscv
+  CROSS_COMPILE: riscv64-unknown-linux-gnu-
+
+jobs:
+  build:
+    runs-on: ubuntu-22.04
+    strategy:
+      fail-fast: false
+      matrix:
+        name: [thead-gcc, gcc-13]
+
+    steps:
+      - name: Install software
+        run: |
+              sudo apt update && \
+              sudo apt install -y gdisk dosfstools g++-12-riscv64-linux-gnu cpp-12-riscv64-linux-gnu build-essential \
+                                  libncurses-dev gawk flex bison openssl libssl-dev tree \
+                                  dkms libelf-dev libudev-dev libpci-dev libiberty-dev autoconf device-tree-compiler
+
+      - name: Checkout opensbi
+        uses: actions/checkout@v4
+
+      - name: opensbi compile
+        run: |
+              mkdir output
+              if [[ ${{ matrix.name }} = "thead-gcc" ]]; then
+                ${wget_alias} ${xuantie_toolchain}/${toolchain_file_name}
+                tar -xvf ${toolchain_file_name} -C /opt
+                export PATH="/opt/Xuantie-900-gcc-linux-5.10.4-glibc-x86_64-V2.8.0/bin:$PATH"
+              else
+                ${wget_alias} ${mainline_toolchain}/${mainline_toolchain_file_name}
+                tar -xvf ${mainline_toolchain_file_name} -C /opt
+                export PATH="/opt/riscv/bin:$PATH"
+              fi
+              ${CROSS_COMPILE}gcc -v
+
+              pushd $PWD
+                make PLATFORM=generic FW_PIC=y
+                cp -v build/platform/generic/firmware/fw_dynamic.bin output/
+              popd
+              tree ${GITHUB_WORKSPACE}/output
+
+
+      - name: 'Upload Artifact'
+        uses: actions/upload-artifact@v3
+        with:
+          name: thead-opensbi-${{ matrix.name }}
+          path: output/fw_dynamic.bin
+          retention-days: 30
--- a/11
+++ b/11
@@ -106,6 +106,9 @@ ifndef PLATFORM_RISCV_XLEN
  endif
 endif

+# Check whether the assembler and the compiler support the Zicsr and Zifencei extensions
+CC_SUPPORT_ZICSR_ZIFENCEI := $(shell $(CC) $(CLANG_TARGET) $(RELAX_FLAG) -nostdlib -march=rv$(OPENSBI_CC_XLEN)imafd_zicsr_zifencei -x c /dev/null -o /dev/null 2>&1 | grep "zicsr\|zifencei" > /dev/null && echo n || echo y)
+
 # Setup list of objects.mk files
 ifdef PLATFORM
 platform-object-mks=$(shell if [ -d $(platform_src_dir)/ ]; then find $(platform_src_dir) -iname "objects.mk" | sort -r; fi)
@@ -157,7 +160,11 @@ ifndef PLATFORM_RISCV_ABI
 endif
 ifndef PLATFORM_RISCV_ISA
  ifneq ($(PLATFORM_RISCV_TOOLCHAIN_DEFAULT), 1)
-    PLATFORM_RISCV_ISA = rv$(PLATFORM_RISCV_XLEN)imafdc
+    ifeq ($(CC_SUPPORT_ZICSR_ZIFENCEI), y)
+      PLATFORM_RISCV_ISA = rv$(PLATFORM_RISCV_XLEN)imafdc_zicsr_zifencei
+    else
+      PLATFORM_RISCV_ISA = rv$(PLATFORM_RISCV_XLEN)imafdc
+    endif
  else
    PLATFORM_RISCV_ISA = $(OPENSBI_CC_ISA)
  endif
@@ -203,7 +210,7 @@ GENFLAGS	+=	$(libsbiutils-genflags-y)
 GENFLAGS	+=	$(platform-genflags-y)
 GENFLAGS	+=	$(firmware-genflags-y)

-CFLAGS		=	-g -Wall -Werror -ffreestanding -nostdlib -fno-strict-aliasing -O2
+CFLAGS		=	-g -Wall -Werror -ffreestanding -nostdlib -fno-stack-protector -fno-strict-aliasing -O2
 CFLAGS		+=	-fno-omit-frame-pointer -fno-optimize-sibling-calls
 CFLAGS		+=	-mno-save-restore -mstrict-align
 CFLAGS		+=	-mabi=$(PLATFORM_RISCV_ABI) -march=$(PLATFORM_RISCV_ISA)
--- a/docs/platform/thead-c9xx.md
+++ b/docs/platform/thead-c9xx.md
@@ -51,11 +51,6 @@ DTS Example1: (Single core, eg: Allwinner D1 - c906)
 		compatible = "simple-bus";
 		ranges;

-		reset: reset-sample {
-			compatible = "thead,reset-sample";
-			plic-delegate = <0x0 0x101ffffc>;
-		};
-
 		clint0: clint@14000000 {
 			compatible = "riscv,clint0";
 			interrupts-extended = <
@@ -67,7 +62,8 @@ DTS Example1: (Single core, eg: Allwinner D1 - c906)

 		intc: interrupt-controller@10000000 {
 			#interrupt-cells = <1>;
-			compatible = "riscv,plic0";
+			compatible = "allwinner,sun20i-d1-plic",
+				     "thead,c900-plic";
 			interrupt-controller;
 			interrupts-extended = <
 				&cpu0_intc  0xffffffff &cpu0_intc  9
@@ -150,7 +146,6 @@ DTS Example2: (Multi cores with soc reset-regs)

 		reset: reset-sample {
 			compatible = "thead,reset-sample";
-			plic-delegate = <0xff 0xd81ffffc>;
 			entry-reg = <0xff 0xff019050>;
 			entry-cnt = <4>;
 			control-reg = <0xff 0xff015004>;
@@ -173,7 +168,7 @@ DTS Example2: (Multi cores with soc reset-regs)

 		intc: interrupt-controller@ffd8000000 {
 			#interrupt-cells = <1>;
-			compatible = "riscv,plic0";
+			compatible = "thead,c900-plic";
 			interrupt-controller;
 			interrupts-extended = <
 				&cpu0_intc  0xffffffff &cpu0_intc  9
@@ -194,7 +189,6 @@ DTS Example2: (Multi cores with old reset csrs)
 ```
 	reset: reset-sample {
 		compatible = "thead,reset-sample";
-		plic-delegate = <0xff 0xd81ffffc>;
 		using-csr-reset;
 		csr-copy = <0x7c0 0x7c1 0x7c2 0x7c3 0x7c5 0x7cc
 			    0x3b0 0x3b1 0x3b2 0x3b3
--- a/firmware/fw_base.S
+++ b/firmware/fw_base.S
@@ -713,6 +713,7 @@ fw_platform_init:
 	.globl _trap_handler
 	.globl _trap_exit
 _trap_handler:
+	sfence.vma zero, t0
 	TRAP_SAVE_AND_SETUP_SP_T0

 	TRAP_SAVE_MEPC_MSTATUS 0
--- a/include/sbi/riscv_asm.h
+++ b/include/sbi/riscv_asm.h
@@ -162,6 +162,19 @@ void csr_write_num(int csr_num, unsigned long val);
 		__asm__ __volatile__("ebreak" ::: "memory"); \
 	} while (0)

+
+#define dcache_call()                                             \
+	do {                                              \
+		asm volatile(".long 0x0010000b\n"); \
+	} while (0)
+
+#define dcache_ciall()                                             \
+	do {                                              \
+		asm volatile(".long 0x0030000b\n"); \
+	} while (0)
+
+#define sync_is()   asm volatile (".long 0x01b0000b")
+
 /* Get current HART id */
 #define current_hartid()	((unsigned int)csr_read(CSR_MHARTID))

--- a/include/sbi/riscv_encoding.h
+++ b/include/sbi/riscv_encoding.h
@@ -625,6 +625,9 @@
 #define INSN_MASK_WFI			0xffffff00
 #define INSN_MATCH_WFI			0x10500000

+#define INSN_MASK_FENCE_TSO		0xffffffff
+#define INSN_MATCH_FENCE_TSO		0x8330000f
+
 #define INSN_16BIT_MASK			0x3
 #define INSN_32BIT_MASK			0x1c

--- a/include/sbi/sbi_platform.h
+++ b/include/sbi/sbi_platform.h
@@ -45,6 +45,10 @@
 #include <sbi/sbi_scratch.h>
 #include <sbi/sbi_version.h>

+#define SBI_EXT_VENDOR_SMC      (SBI_EXT_VENDOR_START + 0)
+#define SBI_EXT_VENDOR_PMU      (SBI_EXT_VENDOR_START + 1)
+#define SBI_EXT_VENDOR_PMP      (SBI_EXT_VENDOR_START + 2)
+
 struct sbi_domain_memregion;
 struct sbi_trap_info;
 struct sbi_trap_regs;
--- a/include/sbi/sbi_scratch.h
+++ b/include/sbi/sbi_scratch.h
@@ -98,7 +98,7 @@ int sbi_scratch_init(struct sbi_scratch *scratch);
 * @return zero on failure and non-zero (>= SBI_SCRATCH_EXTRA_SPACE_OFFSET)
 * on success
 */
-unsigned long sbi_scratch_alloc_offset(unsigned long size, const char *owner);
+unsigned long sbi_scratch_alloc_offset(unsigned long size);

 /** Free-up extra space in sbi_scratch */
 void sbi_scratch_free_offset(unsigned long offset);
--- a/lib/sbi/sbi_hart.c
+++ b/lib/sbi/sbi_hart.c
@@ -451,8 +451,7 @@ int sbi_hart_init(struct sbi_scratch *scratch, bool cold_boot)
 			sbi_hart_expected_trap = &__sbi_expected_trap_hext;

 		hart_features_offset = sbi_scratch_alloc_offset(
-						sizeof(struct hart_features),
-						"HART_FEATURES");
+						sizeof(struct hart_features));
 		if (!hart_features_offset)
 			return SBI_ENOMEM;
 	}
--- a/lib/sbi/sbi_hsm.c
+++ b/lib/sbi/sbi_hsm.c
@@ -185,8 +185,7 @@ int sbi_hsm_init(struct sbi_scratch *scratch, u32 hartid, bool cold_boot)
 	struct sbi_hsm_data *hdata;

 	if (cold_boot) {
-		hart_data_offset = sbi_scratch_alloc_offset(sizeof(*hdata),
-							    "HART_DATA");
+		hart_data_offset = sbi_scratch_alloc_offset(sizeof(*hdata));
 		if (!hart_data_offset)
 			return SBI_ENOMEM;

@@ -359,12 +358,6 @@ static int __sbi_hsm_suspend_non_ret_default(struct sbi_scratch *scratch,
 {
 	void (*jump_warmboot)(void) = (void (*)(void))scratch->warmboot_addr;

-	/*
-	 * Save some of the M-mode CSRs which should be restored after
-	 * resuming from suspend state
-	 */
-	__sbi_hsm_suspend_non_ret_save(scratch);
-
 	/* Wait for interrupt */
 	wfi();

@@ -464,6 +457,13 @@ int sbi_hsm_hart_suspend(struct sbi_scratch *scratch, u32 suspend_type,
 	/* Save the suspend type */
 	hdata->suspend_type = suspend_type;

+	/*
+	 * Save context which will be restored after resuming from
+	 * non-retentive suspend.
+	 */
+	if (suspend_type & SBI_HSM_SUSP_NON_RET_BIT)
+		__sbi_hsm_suspend_non_ret_save(scratch);
+
 	/* Try platform specific suspend */
 	ret = hsm_device_hart_suspend(suspend_type, scratch->warmboot_addr);
 	if (ret == SBI_ENOTSUPP) {
--- a/lib/sbi/sbi_illegal_insn.c
+++ b/lib/sbi/sbi_illegal_insn.c
@@ -8,6 +8,7 @@
 */

 #include <sbi/riscv_asm.h>
+#include <sbi/riscv_barrier.h>
 #include <sbi/riscv_encoding.h>
 #include <sbi/sbi_bitops.h>
 #include <sbi/sbi_emulate_csr.h>
@@ -31,6 +32,18 @@ static int truly_illegal_insn(ulong insn, struct sbi_trap_regs *regs)
 	return sbi_trap_redirect(regs, &trap);
 }

+static int misc_mem_opcode_insn(ulong insn, struct sbi_trap_regs *regs)
+{
+	/* Errata workaround: emulate `fence.tso` as `fence rw, rw`. */
+	if ((insn & INSN_MASK_FENCE_TSO) == INSN_MATCH_FENCE_TSO) {
+		smp_mb();
+		regs->mepc += 4;
+		return 0;
+	}
+
+	return truly_illegal_insn(insn, regs);
+}
+
 static int system_opcode_insn(ulong insn, struct sbi_trap_regs *regs)
 {
 	int do_write, rs1_num = (insn >> 15) & 0x1f;
@@ -83,7 +96,7 @@ static illegal_insn_func illegal_insn_table[32] = {
 	truly_illegal_insn, /* 0 */
 	truly_illegal_insn, /* 1 */
 	truly_illegal_insn, /* 2 */
-	truly_illegal_insn, /* 3 */
+	misc_mem_opcode_insn, /* 3 */
 	truly_illegal_insn, /* 4 */
 	truly_illegal_insn, /* 5 */
 	truly_illegal_insn, /* 6 */
--- a/lib/sbi/sbi_init.c
+++ b/lib/sbi/sbi_init.c
@@ -233,8 +233,7 @@ static void __noreturn init_coldboot(struct sbi_scratch *scratch, u32 hartid)
 	if (rc)
 		sbi_hart_hang();

-	init_count_offset = sbi_scratch_alloc_offset(__SIZEOF_POINTER__,
-						     "INIT_COUNT");
+	init_count_offset = sbi_scratch_alloc_offset(__SIZEOF_POINTER__);
 	if (!init_count_offset)
 		sbi_hart_hang();

--- a/lib/sbi/sbi_ipi.c
+++ b/lib/sbi/sbi_ipi.c
@@ -227,8 +227,7 @@ int sbi_ipi_init(struct sbi_scratch *scratch, bool cold_boot)
 	struct sbi_ipi_data *ipi_data;

 	if (cold_boot) {
-		ipi_data_off = sbi_scratch_alloc_offset(sizeof(*ipi_data),
-							"IPI_DATA");
+		ipi_data_off = sbi_scratch_alloc_offset(sizeof(*ipi_data));
 		if (!ipi_data_off)
 			return SBI_ENOMEM;
 		ret = sbi_ipi_event_create(&ipi_smode_ops);
--- a/lib/sbi/sbi_scratch.c
+++ b/lib/sbi/sbi_scratch.c
@@ -40,7 +40,7 @@ int sbi_scratch_init(struct sbi_scratch *scratch)
 	return 0;
 }

-unsigned long sbi_scratch_alloc_offset(unsigned long size, const char *owner)
+unsigned long sbi_scratch_alloc_offset(unsigned long size)
 {
 	u32 i;
 	void *ptr;
--- a/lib/sbi/sbi_timer.c
+++ b/lib/sbi/sbi_timer.c
@@ -121,8 +121,7 @@ int sbi_timer_init(struct sbi_scratch *scratch, bool cold_boot)
 	const struct sbi_platform *plat = sbi_platform_ptr(scratch);

 	if (cold_boot) {
-		time_delta_off = sbi_scratch_alloc_offset(sizeof(*time_delta),
-							  "TIME_DELTA");
+		time_delta_off = sbi_scratch_alloc_offset(sizeof(*time_delta));
 		if (!time_delta_off)
 			return SBI_ENOMEM;

--- a/lib/sbi/sbi_tlb.c
+++ b/lib/sbi/sbi_tlb.c
@@ -392,19 +392,16 @@ int sbi_tlb_init(struct sbi_scratch *scratch, bool cold_boot)
 	const struct sbi_platform *plat = sbi_platform_ptr(scratch);

 	if (cold_boot) {
-		tlb_sync_off = sbi_scratch_alloc_offset(sizeof(*tlb_sync),
-							"IPI_TLB_SYNC");
+		tlb_sync_off = sbi_scratch_alloc_offset(sizeof(*tlb_sync));
 		if (!tlb_sync_off)
 			return SBI_ENOMEM;
-		tlb_fifo_off = sbi_scratch_alloc_offset(sizeof(*tlb_q),
-							"IPI_TLB_FIFO");
+		tlb_fifo_off = sbi_scratch_alloc_offset(sizeof(*tlb_q));
 		if (!tlb_fifo_off) {
 			sbi_scratch_free_offset(tlb_sync_off);
 			return SBI_ENOMEM;
 		}
 		tlb_fifo_mem_off = sbi_scratch_alloc_offset(
-				SBI_TLB_FIFO_NUM_ENTRIES * SBI_TLB_INFO_SIZE,
-				"IPI_TLB_FIFO_MEM");
+				SBI_TLB_FIFO_NUM_ENTRIES * SBI_TLB_INFO_SIZE);
 		if (!tlb_fifo_mem_off) {
 			sbi_scratch_free_offset(tlb_fifo_off);
 			sbi_scratch_free_offset(tlb_sync_off);
--- a/lib/sbi/sbi_trap.c
+++ b/lib/sbi/sbi_trap.c
@@ -225,6 +225,15 @@ struct sbi_trap_regs *sbi_trap_handler(struct sbi_trap_regs *regs)

 	if (mcause & (1UL << (__riscv_xlen - 1))) {
 		mcause &= ~(1UL << (__riscv_xlen - 1));
+
+		/*
+		 * DCACHE.CALL:
+		 * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 |
+		 *   0000000    00001     00000      000      00000  0001011
+		 */
+		if ((regs->mepc & 0x7f) == 4)
+			asm volatile(".long 0x0010000b\n");
+
 		switch (mcause) {
 		case IRQ_M_TIMER:
 			sbi_timer_process();
--- a/lib/utils/ipi/fdt_ipi_clint.c
+++ b/lib/utils/ipi/fdt_ipi_clint.c
@@ -37,6 +37,7 @@ static int ipi_clint_cold_init(void *fdt, int nodeoff,
 static const struct fdt_match ipi_clint_match[] = {
 	{ .compatible = "riscv,clint0" },
 	{ .compatible = "sifive,clint0" },
+	{ .compatible = "thead,c900-clint" },
 	{ },
 };

--- a/lib/utils/irqchip/fdt_irqchip_plic.c
+++ b/lib/utils/irqchip/fdt_irqchip_plic.c
@@ -9,6 +9,7 @@

 #include <libfdt.h>
 #include <sbi/riscv_asm.h>
+#include <sbi/riscv_io.h>
 #include <sbi/sbi_error.h>
 #include <sbi/sbi_hartmask.h>
 #include <sbi_utils/fdt/fdt_helper.h>
@@ -91,6 +92,11 @@ static int irqchip_plic_cold_init(void *fdt, int nodeoff,
 	if (rc)
 		return rc;

+	if (match->data) {
+		void (*plic_plat_init)(struct plic_data *) = match->data;
+		plic_plat_init(pd);
+	}
+
 	rc = plic_cold_irqchip_init(pd);
 	if (rc)
 		return rc;
@@ -106,9 +112,18 @@ static int irqchip_plic_cold_init(void *fdt, int nodeoff,
 	return irqchip_plic_update_hartid_table(fdt, nodeoff, pd);
 }

+#define THEAD_PLIC_CTRL_REG 0x1ffffc
+
+static void thead_plic_plat_init(struct plic_data *pd)
+{
+	writel_relaxed(BIT(0), (void *)pd->addr + THEAD_PLIC_CTRL_REG);
+}
+
 static const struct fdt_match irqchip_plic_match[] = {
 	{ .compatible = "riscv,plic0" },
 	{ .compatible = "sifive,plic-1.0.0" },
+	{ .compatible = "thead,c900-plic",
+	  .data = thead_plic_plat_init },
 	{ },
 };

--- a/lib/utils/reset/fdt_reset_thead.c
+++ b/lib/utils/reset/fdt_reset_thead.c
@@ -62,24 +62,25 @@ static int thead_reset_init(void *fdt, int nodeoff,
 	void *p;
 	const fdt64_t *val;
 	const fdt32_t *val_w;
-	int len, i, cnt;
+	int len, i;
 	u32 t, tmp = 0;

 	/* Prepare clone csrs */
 	val_w = fdt_getprop(fdt, nodeoff, "csr-copy", &len);
 	if (len > 0 && val_w) {
-		cnt = len / sizeof(fdt32_t);
+		int cnt;

+		cnt = len / sizeof(fdt32_t);
 		if (cnt > MAX_CUSTOM_CSR)
 			sbi_hart_hang();

 		for (i = 0; i < cnt; i++) {
 			custom_csr[i].index = fdt32_to_cpu(val_w[i]);
 		}
-	}

-	if (cnt)
-		clone_csrs(cnt);
+		if (cnt)
+			clone_csrs(cnt);
+	}

 	/* Delegate plic enable regs for S-mode */
 	val = fdt_getprop(fdt, nodeoff, "plic-delegate", &len);
--- a/lib/utils/serial/fdt_serial_uart8250.c
+++ b/lib/utils/serial/fdt_serial_uart8250.c
@@ -28,6 +28,7 @@ static int serial_uart8250_init(void *fdt, int nodeoff,
 static const struct fdt_match serial_uart8250_match[] = {
 	{ .compatible = "ns16550" },
 	{ .compatible = "ns16550a" },
+	{ .compatible = "snps,dw-apb-uart" },
 	{ },
 };

--- a/lib/utils/timer/fdt_timer_clint.c
+++ b/lib/utils/timer/fdt_timer_clint.c
@@ -7,6 +7,7 @@
 *   Anup Patel <anup.patel@wdc.com>
 */

+#include <libfdt.h>
 #include <sbi/sbi_error.h>
 #include <sbi_utils/fdt/fdt_helper.h>
 #include <sbi_utils/timer/fdt_timer.h>
@@ -33,12 +34,16 @@ static int timer_clint_cold_init(void *fdt, int nodeoff,
 	if (rc)
 		return rc;

+	if (fdt_node_check_compatible(fdt, nodeoff, "thead,c900-clint") >= 0)
+		ct->has_64bit_mmio = FALSE;
+
 	return clint_cold_timer_init(ct, ctmaster);
 }

 static const struct fdt_match timer_clint_match[] = {
 	{ .compatible = "riscv,clint0" },
 	{ .compatible = "sifive,clint0" },
+	{ .compatible = "thead,c900-clint" },
 	{ },
 };

--- a/platform/generic/include/aonsys_reg_define.h
+++ b/platform/generic/include/aonsys_reg_define.h
@@ -0,0 +1,218 @@
+//------------------------------------------------------------
+// DONOT MODIFY THIS FILE
+// generated by JISHENGJU automatically
+//------------------------------------------------------------
+
+#ifndef AONSYS_SYSREG_REG_OFFSET_DEFINE_H
+#define AONSYS_SYSREG_REG_OFFSET_DEFINE_H
+
+#define AONSYS_REG_BASE			0xFFFFF48000
+
+#define REG_AON_CPU_LP_MODE         (AONSYS_REG_BASE + 0x0  )
+#define REG_AON_CHIP_LP_MODE        (AONSYS_REG_BASE + 0x4  )
+#define REG_AON_AO_SERAM_TRN        (AONSYS_REG_BASE + 0x10 )
+#define REG_AON_AO_SERAM_INT        (AONSYS_REG_BASE + 0x14 )
+#define REG_AON_STR_SERAM_TRN       (AONSYS_REG_BASE + 0x18 )
+#define REG_AON_STR_SERAM_INT       (AONSYS_REG_BASE + 0x1c )
+#define REG_AON_STR_INDICATOR_0     (AONSYS_REG_BASE + 0x20 )
+#define REG_AON_STR_INDICATOR_1     (AONSYS_REG_BASE + 0x24 )
+#define REG_AON_STR_INDICATOR_2     (AONSYS_REG_BASE + 0x28 )
+#define REG_AON_STR_INDICATOR_3     (AONSYS_REG_BASE + 0x2c )
+#define REG_AON_PVTC_WR_LOCK        (AONSYS_REG_BASE + 0x30 )
+#define REG_AON_PVTC_TS_ALARM       (AONSYS_REG_BASE + 0x34 )
+#define REG_AON_PVTC_VM_ALARM       (AONSYS_REG_BASE + 0x38 )
+#define REG_AON_PVTC_PD_ALARM       (AONSYS_REG_BASE + 0x3c )
+#define REG_AON_E902_CNT_CLR        (AONSYS_REG_BASE + 0x40 )
+#define REG_AON_E902_RST_ADDR       (AONSYS_REG_BASE + 0x44 )
+#define REG_AON_C906_RST_ADDR_L     (AONSYS_REG_BASE + 0x48 )
+#define REG_AON_C906_RST_ADDR_H     (AONSYS_REG_BASE + 0x4c )
+#define REG_AON_RESERVED_REG_0      (AONSYS_REG_BASE + 0x50 )
+#define REG_AON_RESERVED_REG_1      (AONSYS_REG_BASE + 0x54 )
+#define REG_AON_RESERVED_REG_2      (AONSYS_REG_BASE + 0x58 )
+#define REG_AON_RESERVED_REG_3      (AONSYS_REG_BASE + 0x5c )
+#define REG_AON_AON_AHB_ADEXT       (AONSYS_REG_BASE + 0x60 )
+#define REG_AON_RC_EN               (AONSYS_REG_BASE + 0x70 )
+#define REG_AON_RC_FCAL             (AONSYS_REG_BASE + 0x74 )
+#define REG_AON_RC_MODE             (AONSYS_REG_BASE + 0x78 )
+#define REG_AON_RC_READY            (AONSYS_REG_BASE + 0x7c )
+#define REG_AON_ISO_CFG             (AONSYS_REG_BASE + 0x80 )
+#define REG_AON_OCRAM_ERR           (AONSYS_REG_BASE + 0x90 )
+#define REG_AON_TIMER_LINK          (AONSYS_REG_BASE + 0x100)
+#define REG_AON_PD_REQ              (AONSYS_REG_BASE + 0x110)
+#define REG_AON_PD_ISO_EN_SET       (AONSYS_REG_BASE + 0x114)
+#define REG_AON_PD_ISO_EN_CLR       (AONSYS_REG_BASE + 0x118)
+#define REG_AON_PD_SW_EN_SET        (AONSYS_REG_BASE + 0x11c)
+#define REG_AON_PD_SW_EN_CLR        (AONSYS_REG_BASE + 0x120)
+#define REG_AON_PD_SW_ACK           (AONSYS_REG_BASE + 0x124)
+#define REG_AON_PD_SW_CNT_EN        (AONSYS_REG_BASE + 0x128)
+#define REG_AON_PD_FSM_RST          (AONSYS_REG_BASE + 0x12c)
+#define REG_AON_PD_INT_MASK         (AONSYS_REG_BASE + 0x130)
+#define REG_AON_PD_FSM_STS_L        (AONSYS_REG_BASE + 0x134)
+#define REG_AON_PD_FSM_STS_H        (AONSYS_REG_BASE + 0x138)
+#define REG_AON_PD_INT_STS          (AONSYS_REG_BASE + 0x13c)
+#define REG_AON_PD_INT_CLR          (AONSYS_REG_BASE + 0x140)
+#define REG_AON_PD_BLK0_SW_CNT      (AONSYS_REG_BASE + 0x144)
+#define REG_AON_PD_BLK1_SW_CNT      (AONSYS_REG_BASE + 0x148)
+#define REG_AON_PD_BLK2_SW_CNT      (AONSYS_REG_BASE + 0x14c)
+#define REG_AON_PD_BLK3_SW_CNT      (AONSYS_REG_BASE + 0x150)
+#define REG_AON_PD_BLK4_SW_CNT      (AONSYS_REG_BASE + 0x154)
+#define REG_AON_PD_BLK5_SW_CNT      (AONSYS_REG_BASE + 0x158)
+#define REG_AON_PD_BLK6_SW_CNT      (AONSYS_REG_BASE + 0x15c)
+#define REG_AON_PD_BLK7_SW_CNT      (AONSYS_REG_BASE + 0x160)
+#define REG_AON_PD_BLK8_SW_CNT      (AONSYS_REG_BASE + 0x164)
+#define REG_AON_PD_BLK9_SW_CNT      (AONSYS_REG_BASE + 0x168)
+#define REG_AON_PD_BLK10_SW_CNT     (AONSYS_REG_BASE + 0x16c)
+#define REG_AON_PD_BLK0_INTV_CNT    (AONSYS_REG_BASE + 0x180)
+#define REG_AON_PD_BLK1_INTV_CNT    (AONSYS_REG_BASE + 0x184)
+#define REG_AON_PD_BLK2_INTV_CNT    (AONSYS_REG_BASE + 0x188)
+#define REG_AON_PD_BLK3_INTV_CNT    (AONSYS_REG_BASE + 0x18c)
+#define REG_AON_PD_BLK4_INTV_CNT    (AONSYS_REG_BASE + 0x190)
+#define REG_AON_PD_BLK5_INTV_CNT    (AONSYS_REG_BASE + 0x194)
+#define REG_AON_PD_BLK6_INTV_CNT    (AONSYS_REG_BASE + 0x198)
+#define REG_AON_PD_BLK7_INTV_CNT    (AONSYS_REG_BASE + 0x19c)
+#define REG_AON_PD_BLK8_INTV_CNT    (AONSYS_REG_BASE + 0x1a0)
+#define REG_AON_PD_BLK9_INTV_CNT    (AONSYS_REG_BASE + 0x1a4)
+#define REG_AON_PD_BLK10_INTV_CNT   (AONSYS_REG_BASE + 0x1a8)
+#define REG_AON_AUDIO_PMU_REQ       (AONSYS_REG_BASE + 0x1f8)
+#define REG_AON_AUDIO_PMU_STS       (AONSYS_REG_BASE + 0x1fc)
+#define REG_AON_AUDIO_PMU_INTR      (AONSYS_REG_BASE + 0x204)
+#define REG_AON_PMU_AUDIO_REQ       (AONSYS_REG_BASE + 0x208)
+#define REG_AON_PMU_AUDIO_STS       (AONSYS_REG_BASE + 0x20c)
+#define REG_AON_MEM_LP_MODE         (AONSYS_REG_BASE + 0x210)
+#define REG_AON_C910_DBG_MASK       (AONSYS_REG_BASE + 0x214)
+#define REG_AON_C910_L2CACHE        (AONSYS_REG_BASE + 0x218)
+#define REG_AON_BISR_CTRL           (AONSYS_REG_BASE + 0x220)
+#define REG_AON_EFUSE_PRELOAD_DONE  (AONSYS_REG_BASE + 0x224)
+#define REG_AON_GPIO_RTE            (AONSYS_REG_BASE + 0x228)
+#define REG_AON_PLL_DSKEW_LOCK      (AONSYS_REG_BASE + 0x22c)
+#define REG_AON_SRAM_AXI_CFG        (AONSYS_REG_BASE + 0x230)
+#define REG_AON_SRAM_AXI_ST         (AONSYS_REG_BASE + 0x234)
+#define REG_AON_SRAM_AXI_ERR_STS_0  (AONSYS_REG_BASE + 0x238)
+#define REG_AON_SRAM_AXI_ERR_STS_1  (AONSYS_REG_BASE + 0x23c)
+#define REG_AON_SRAM_AXI_ERR_STS_2  (AONSYS_REG_BASE + 0x240)
+#define REG_AON_SRAM_AXI_ERR_STS_3  (AONSYS_REG_BASE + 0x244)
+#define REG_AON_SRAM_AXI_ERR_STS_4  (AONSYS_REG_BASE + 0x248)
+#define REG_AON_SE_MUX_LOCK         (AONSYS_REG_BASE + 0x24c)
+#define REG_AON_CPU_DBG_DIS_LOCK    (AONSYS_REG_BASE + 0x270)
+#define REG_AON_RESERVED_REG_4      (AONSYS_REG_BASE + 0x300)
+#define REG_AON_RESERVED_REG_5      (AONSYS_REG_BASE + 0x304)
+#define REG_AON_RESERVED_REG_6      (AONSYS_REG_BASE + 0x308)
+#define REG_AON_RESERVED_REG_7      (AONSYS_REG_BASE + 0x30c)
+#define REG_AON_RESERVED_REG_8      (AONSYS_REG_BASE + 0x400)
+#define REG_AON_RESERVED_REG_9      (AONSYS_REG_BASE + 0x404)
+#define REG_AON_RESERVED_REG_10     (AONSYS_REG_BASE + 0x408)
+#define REG_AON_RESERVED_REG_11     (AONSYS_REG_BASE + 0x40c)
+#define REG_AON_RESERVED_REG_12     (AONSYS_REG_BASE + 0x500)
+#define REG_AON_RESERVED_REG_13     (AONSYS_REG_BASE + 0x504)
+#define REG_AON_RESERVED_REG_14     (AONSYS_REG_BASE + 0x508)
+#define REG_AON_RESERVED_REG_15     (AONSYS_REG_BASE + 0x50c)
+#define REG_AON_RESERVED_REG_16     (AONSYS_REG_BASE + 0x600)
+#define REG_AON_RESERVED_REG_17     (AONSYS_REG_BASE + 0x604)
+#define REG_AON_RESERVED_REG_18     (AONSYS_REG_BASE + 0x608)
+#define REG_AON_RESERVED_REG_19     (AONSYS_REG_BASE + 0x60c)
+
+#define CPU_LP_MODE_DFLT_VAL          0x3ff
+#define CHIP_LP_MODE_DFLT_VAL         0x0
+#define AO_SERAM_TRN_DFLT_VAL         0x0
+#define AO_SERAM_INT_DFLT_VAL         0x0
+#define STR_SERAM_TRN_DFLT_VAL        0x0
+#define STR_SERAM_INT_DFLT_VAL        0x0
+#define STR_INDICATOR_0_DFLT_VAL      0x0
+#define STR_INDICATOR_1_DFLT_VAL      0x0
+#define STR_INDICATOR_2_DFLT_VAL      0x0
+#define STR_INDICATOR_3_DFLT_VAL      0x0
+#define PVTC_WR_LOCK_DFLT_VAL         0x0
+#define PVTC_TS_ALARM_DFLT_VAL        0x0
+#define PVTC_VM_ALARM_DFLT_VAL        0x0
+#define PVTC_PD_ALARM_DFLT_VAL        0x0
+#define E902_CNT_CLR_DFLT_VAL         0x0
+#define E902_RST_ADDR_DFLT_VAL        0xffef8000
+#define C906_RST_ADDR_L_DFLT_VAL      0xc0000000
+#define C906_RST_ADDR_H_DFLT_VAL      0xff
+#define RESERVED_REG_0_DFLT_VAL       0x0
+#define RESERVED_REG_1_DFLT_VAL       0x0
+#define RESERVED_REG_2_DFLT_VAL       0x0
+#define RESERVED_REG_3_DFLT_VAL       0x0
+#define AON_AHB_ADEXT_DFLT_VAL        0x0
+#define RC_EN_DFLT_VAL                0x1
+#define RC_FCAL_DFLT_VAL              0x77f
+#define RC_MODE_DFLT_VAL              0x1
+#define RC_READY_DFLT_VAL             0x0
+#define ISO_CFG_DFLT_VAL              0x0
+#define OCRAM_ERR_DFLT_VAL            0x0
+#define TIMER_LINK_DFLT_VAL           0x0
+#define PD_REQ_DFLT_VAL               0x0
+#define PD_ISO_EN_SET_DFLT_VAL        0x0
+#define PD_ISO_EN_CLR_DFLT_VAL        0x0
+#define PD_SW_EN_SET_DFLT_VAL         0x0
+#define PD_SW_EN_CLR_DFLT_VAL         0x0
+#define PD_SW_ACK_DFLT_VAL            0x3fffff
+#define PD_SW_CNT_EN_DFLT_VAL         0x0
+#define PD_FSM_RST_DFLT_VAL           0x0
+#define PD_INT_MASK_DFLT_VAL          0x3fffff
+#define PD_FSM_STS_L_DFLT_VAL         0x0
+#define PD_FSM_STS_H_DFLT_VAL         0x0
+#define PD_INT_STS_DFLT_VAL           0x0
+#define PD_INT_CLR_DFLT_VAL           0x0
+#define PD_BLK0_SW_CNT_DFLT_VAL       0xff00ff
+#define PD_BLK1_SW_CNT_DFLT_VAL       0xff00ff
+#define PD_BLK2_SW_CNT_DFLT_VAL       0xff00ff
+#define PD_BLK3_SW_CNT_DFLT_VAL       0xff00ff
+#define PD_BLK4_SW_CNT_DFLT_VAL       0xff00ff
+#define PD_BLK5_SW_CNT_DFLT_VAL       0xff00ff
+#define PD_BLK6_SW_CNT_DFLT_VAL       0xff00ff
+#define PD_BLK7_SW_CNT_DFLT_VAL       0xff00ff
+#define PD_BLK8_SW_CNT_DFLT_VAL       0xff00ff
+#define PD_BLK9_SW_CNT_DFLT_VAL       0xff00ff
+#define PD_BLK10_SW_CNT_DFLT_VAL      0xff00ff
+#define PD_BLK0_INTV_CNT_DFLT_VAL     0xff0ffff
+#define PD_BLK1_INTV_CNT_DFLT_VAL     0xff0ffff
+#define PD_BLK2_INTV_CNT_DFLT_VAL     0xff0ffff
+#define PD_BLK3_INTV_CNT_DFLT_VAL     0xff0ffff
+#define PD_BLK4_INTV_CNT_DFLT_VAL     0xff0ffff
+#define PD_BLK5_INTV_CNT_DFLT_VAL     0xff0ffff
+#define PD_BLK6_INTV_CNT_DFLT_VAL     0xff0ffff
+#define PD_BLK7_INTV_CNT_DFLT_VAL     0xff0ffff
+#define PD_BLK8_INTV_CNT_DFLT_VAL     0xff0ffff
+#define PD_BLK9_INTV_CNT_DFLT_VAL     0xff0ffff
+#define PD_BLK10_INTV_CNT_DFLT_VAL    0xff0ffff
+#define AUDIO_PMU_REQ_DFLT_VAL        0x0
+#define AUDIO_PMU_STS_DFLT_VAL        0x0
+#define AUDIO_PMU_INTR_DFLT_VAL       0x0
+#define PMU_AUDIO_REQ_DFLT_VAL        0x0
+#define PMU_AUDIO_STS_DFLT_VAL        0x0
+#define MEM_LP_MODE_DFLT_VAL          0x0
+#define C910_DBG_MASK_DFLT_VAL        0x0
+#define C910_L2CACHE_DFLT_VAL         0x0
+#define BISR_CTRL_DFLT_VAL            0x0
+#define EFUSE_PRELOAD_DONE_DFLT_VAL   0x0
+#define GPIO_RTE_DFLT_VAL             0x0
+#define PLL_DSKEW_LOCK_DFLT_VAL       0x0
+#define SRAM_AXI_CFG_DFLT_VAL         0x0
+#define SRAM_AXI_ST_DFLT_VAL          0x0
+#define SRAM_AXI_ERR_STS_0_DFLT_VAL   0x0
+#define SRAM_AXI_ERR_STS_1_DFLT_VAL   0x0
+#define SRAM_AXI_ERR_STS_2_DFLT_VAL   0x0
+#define SRAM_AXI_ERR_STS_3_DFLT_VAL   0x0
+#define SRAM_AXI_ERR_STS_4_DFLT_VAL   0x0
+#define SE_MUX_LOCK_DFLT_VAL          0x0
+#define CPU_DBG_DIS_LOCK_DFLT_VAL     0x0
+#define RESERVED_REG_4_DFLT_VAL       0x0
+#define RESERVED_REG_5_DFLT_VAL       0x0
+#define RESERVED_REG_6_DFLT_VAL       0x0
+#define RESERVED_REG_7_DFLT_VAL       0x0
+#define RESERVED_REG_8_DFLT_VAL       0x0
+#define RESERVED_REG_9_DFLT_VAL       0x0
+#define RESERVED_REG_10_DFLT_VAL      0x0
+#define RESERVED_REG_11_DFLT_VAL      0x0
+#define RESERVED_REG_12_DFLT_VAL      0x0
+#define RESERVED_REG_13_DFLT_VAL      0x0
+#define RESERVED_REG_14_DFLT_VAL      0x0
+#define RESERVED_REG_15_DFLT_VAL      0x0
+#define RESERVED_REG_16_DFLT_VAL      0x0
+#define RESERVED_REG_17_DFLT_VAL      0x0
+#define RESERVED_REG_18_DFLT_VAL      0x0
+#define RESERVED_REG_19_DFLT_VAL      0x0
+
+
+#endif
--- a/platform/generic/include/aprst_reg_define.h
+++ b/platform/generic/include/aprst_reg_define.h
@@ -0,0 +1,9 @@
+
+#ifndef APSYS_RSTGEN_REG_OFFSET_DEFINE_H
+#define APSYS_RSTGEN_REG_OFFSET_DEFINE_H
+
+#define APSYS_RSTGEN_BASE		0xFFFF014000
+
+#define REG_C910_SWRST      (APSYS_RSTGEN_BASE + 0x1004)
+
+#endif
--- a/platform/generic/include/apsys_reg_define.h
+++ b/platform/generic/include/apsys_reg_define.h
@@ -0,0 +1,17 @@
+
+#ifndef APSYS_SYSREG_REG_OFFSET_DEFINE_H
+#define APSYS_SYSREG_REG_OFFSET_DEFINE_H
+
+#define APSYS_REG_BASE		0xFFFF019000
+
+#define REG_C910_CORE0_RVBA_L	(APSYS_REG_BASE + 0x50)
+#define REG_C910_CORE0_RVBA_H	(APSYS_REG_BASE + 0x54)
+#define REG_C910_CORE1_RVBA_L	(APSYS_REG_BASE + 0x58)
+#define REG_C910_CORE1_RVBA_H	(APSYS_REG_BASE + 0x5C)
+#define REG_C910_CORE2_RVBA_L	(APSYS_REG_BASE + 0x60)
+#define REG_C910_CORE2_RVBA_H	(APSYS_REG_BASE + 0x64)
+#define REG_C910_CORE3_RVBA_L	(APSYS_REG_BASE + 0x68)
+#define REG_C910_CORE3_RVBA_H	(APSYS_REG_BASE + 0x6C)
+
+
+#endif
--- a/platform/generic/include/thead_c9xx.h
+++ b/platform/generic/include/thead_c9xx.h
@@ -0,0 +1,128 @@
+#ifndef __RISCV_THEAD_C9XX_H____
+#define __RISCV_THEAD_C9XX_H____
+
+/* T-HEAD C9xx M mode CSR.  */
+#define THEAD_C9XX_CSR_MXSTATUS		0x7c0
+#define THEAD_C9XX_CSR_MHCR		0x7c1
+#define THEAD_C9XX_CSR_MCOR		0x7c2
+#define THEAD_C9XX_CSR_MCCR2		0x7c3
+#define THEAD_C9XX_CSR_MCER2		0x7c4
+#define THEAD_C9XX_CSR_MHINT		0x7c5
+#define THEAD_C9XX_CSR_MRMR		0x7c6
+#define THEAD_C9XX_CSR_MRVBR		0x7c7
+#define THEAD_C9XX_CSR_MCER		0x7c8
+#define THEAD_C9XX_CSR_MCOUNTERWEN	0x7c9
+#define THEAD_C9XX_CSR_MCOUNTERINTEN	0x7ca
+#define THEAD_C9XX_CSR_MCOUNTEROF	0x7cb
+#define THEAD_C9XX_CSR_MHINT2		0x7cc
+#define THEAD_C9XX_CSR_MHINT3		0x7cd
+#define THEAD_C9XX_CSR_MHINT4		0x7ce
+#define THEAD_C9XX_CSR_MRADDR		0x7e0
+#define THEAD_C9XX_CSR_MEXSTATUS	0x7e1
+#define THEAD_C9XX_CSR_MNMICAUSE	0x7e2
+#define THEAD_C9XX_CSR_MNMIPC		0x7e3
+#define THEAD_C9XX_CSR_MHPMCR		0x7f0
+#define THEAD_C9XX_CSR_MHPMSR		0x7f1
+#define THEAD_C9XX_CSR_MHPMER		0x7f2
+#define THEAD_C9XX_CSR_MSMPR		0x7f3
+#define THEAD_C9XX_CSR_MTEECFG		0x7f4
+#define THEAD_C9XX_CSR_MZONEID		0x7f5
+#define THEAD_C9XX_CSR_ML2CPID		0x7f6
+#define THEAD_C9XX_CSR_ML2WP		0x7f7
+#define THEAD_C9XX_CSR_MDTCMCR		0x7f8
+#define THEAD_C9XX_CSR_USP		0x7d1
+#define THEAD_C9XX_CSR_MCINS		0x7d2
+#define THEAD_C9XX_CSR_MCINDEX		0x7d3
+#define THEAD_C9XX_CSR_MCDATA0		0x7d4
+#define THEAD_C9XX_CSR_MCDATA1		0x7d5
+#define THEAD_C9XX_CSR_MEICR		0x7d6
+#define THEAD_C9XX_CSR_MEICR2		0x7d7
+#define THEAD_C9XX_CSR_MBEADDR		0x7d8
+#define THEAD_C9XX_CSR_MCPUID		0xfc0
+#define THEAD_C9XX_CSR_MAPBADDR		0xfc1
+#define THEAD_C9XX_CSR_MWMSR		0xfc2
+#define THEAD_C9XX_CSR_MHALTCAUSE	0xfe0
+#define THEAD_C9XX_CSR_MDBGINFO		0xfe1
+#define THEAD_C9XX_CSR_MPCFIFO		0xfe2
+
+/* T-HEAD C9xx S mode CSR.  */
+#define THEAD_C9XX_CSR_SXSTATUS		0x5c0
+#define THEAD_C9XX_CSR_SHCR		0x5c1
+#define THEAD_C9XX_CSR_SCER2		0x5c2
+#define THEAD_C9XX_CSR_SCER		0x5c3
+#define THEAD_C9XX_CSR_SCOUNTERINTEN	0x5c4
+#define THEAD_C9XX_CSR_SCOUNTEROF	0x5c5
+#define THEAD_C9XX_CSR_SHINT		0x5c6
+#define THEAD_C9XX_CSR_SHINT2		0x5c7
+#define THEAD_C9XX_CSR_SHPMINHIBIT	0x5c8
+#define THEAD_C9XX_CSR_SHPMCR		0x5c9
+#define THEAD_C9XX_CSR_SHPMSR		0x5ca
+#define THEAD_C9XX_CSR_SHPMER		0x5cb
+#define THEAD_C9XX_CSR_SL2CPID		0x5cc
+#define THEAD_C9XX_CSR_SL2WP		0x5cd
+#define THEAD_C9XX_CSR_SBEADDR		0x5d0
+#define THEAD_C9XX_CSR_SCYCLE		0x5e0
+#define THEAD_C9XX_CSR_SHPMCOUNTER1	0x5e1
+#define THEAD_C9XX_CSR_SHPMCOUNTER2	0x5e2
+#define THEAD_C9XX_CSR_SHPMCOUNTER3	0x5e3
+#define THEAD_C9XX_CSR_SHPMCOUNTER4	0x5e4
+#define THEAD_C9XX_CSR_SHPMCOUNTER5	0x5e5
+#define THEAD_C9XX_CSR_SHPMCOUNTER6	0x5e6
+#define THEAD_C9XX_CSR_SHPMCOUNTER7	0x5e7
+#define THEAD_C9XX_CSR_SHPMCOUNTER8	0x5e8
+#define THEAD_C9XX_CSR_SHPMCOUNTER9	0x5e9
+#define THEAD_C9XX_CSR_SHPMCOUNTER10	0x5ea
+#define THEAD_C9XX_CSR_SHPMCOUNTER11	0x5eb
+#define THEAD_C9XX_CSR_SHPMCOUNTER12	0x5ec
+#define THEAD_C9XX_CSR_SHPMCOUNTER13	0x5ed
+#define THEAD_C9XX_CSR_SHPMCOUNTER14	0x5ee
+#define THEAD_C9XX_CSR_SHPMCOUNTER15	0x5ef
+#define THEAD_C9XX_CSR_SHPMCOUNTER16	0x5f0
+#define THEAD_C9XX_CSR_SHPMCOUNTER17	0x5f1
+#define THEAD_C9XX_CSR_SHPMCOUNTER18	0x5f2
+#define THEAD_C9XX_CSR_SHPMCOUNTER19	0x5f3
+#define THEAD_C9XX_CSR_SHPMCOUNTER20	0x5f4
+#define THEAD_C9XX_CSR_SHPMCOUNTER21	0x5f5
+#define THEAD_C9XX_CSR_SHPMCOUNTER22	0x5f6
+#define THEAD_C9XX_CSR_SHPMCOUNTER23	0x5f7
+#define THEAD_C9XX_CSR_SHPMCOUNTER24	0x5f8
+#define THEAD_C9XX_CSR_SHPMCOUNTER25	0x5f9
+#define THEAD_C9XX_CSR_SHPMCOUNTER26	0x5fa
+#define THEAD_C9XX_CSR_SHPMCOUNTER27	0x5fb
+#define THEAD_C9XX_CSR_SHPMCOUNTER28	0x5fc
+#define THEAD_C9XX_CSR_SHPMCOUNTER29	0x5fd
+#define THEAD_C9XX_CSR_SHPMCOUNTER30	0x5fe
+#define THEAD_C9XX_CSR_SHPMCOUNTER31	0x5ff
+
+/* T-HEAD C9xx U mode CSR.  */
+#define THEAD_C9XX_CSR_FXCR		0x800
+
+/* T-HEAD C9xx MMU extentions.  */
+#define THEAD_C9XX_CSR_SMIR		0x9c0
+#define THEAD_C9XX_CSR_SMEL		0x9c1
+#define THEAD_C9XX_CSR_SMEH		0x9c2
+#define THEAD_C9XX_CSR_SMCIR		0x9c3
+
+/* T-HEAD C9xx Security CSR(May be droped).  */
+#define THEAD_C9XX_CSR_MEBR		0xbe0
+#define THEAD_C9XX_CSR_NT_MSTATUS	0xbe1
+#define THEAD_C9XX_CSR_NT_MIE		0xbe2
+#define THEAD_C9XX_CSR_NT_MTVEC		0xbe3
+#define THEAD_C9XX_CSR_NT_MTVT		0xbe4
+#define THEAD_C9XX_CSR_NT_MEPC		0xbe5
+#define THEAD_C9XX_CSR_NT_MCAUSE	0xbe6
+#define THEAD_C9XX_CSR_NT_MIP		0xbe7
+#define THEAD_C9XX_CSR_NT_MINTSTATE	0xbe8
+#define THEAD_C9XX_CSR_NT_MXSTATUS	0xbe9
+#define THEAD_C9XX_CSR_NT_MEBR		0xbea
+#define THEAD_C9XX_CSR_NT_MSP		0xbeb
+#define THEAD_C9XX_CSR_T_USP		0xbec
+#define THEAD_C9XX_CSR_T_MDCR		0xbed
+#define THEAD_C9XX_CSR_T_MPCR		0xbee
+#define THEAD_C9XX_CSR_PMPTEECFG	0xbef
+
+/* T-HEAD C9xx MIP CSR extension */
+#define THEAD_C9XX_IRQ_PMU_OVF		17
+#define THEAD_C9XX_MIP_MOIP		(_UL(1) << THEAD_C9XX_IRQ_PMU_OVF)
+
+#endif
--- a/platform/generic/light_c910.c
+++ b/platform/generic/light_c910.c
@@ -0,0 +1,255 @@
+/*
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Copyright (c) 2023 <ben.lh@alibaba-inc.com>
+ */
+
+#include <platform_override.h>
+#include <thead_c9xx.h>
+#include <aonsys_reg_define.h>
+#include <apsys_reg_define.h>
+#include <aprst_reg_define.h>
+#include <sbi/riscv_asm.h>
+#include <sbi/riscv_io.h>
+#include <sbi/sbi_bitops.h>
+#include <sbi/sbi_console.h>
+#include <sbi/sbi_ecall_interface.h>
+#include <sbi/sbi_error.h>
+#include <sbi/sbi_hsm.h>
+#include <sbi/sbi_ipi.h>
+#include <sbi/sbi_scratch.h>
+#include <sbi_utils/fdt/fdt_fixup.h>
+#include <sbi_utils/fdt/fdt_helper.h>
+
+#define INDICATOR_0_MAGIC_NUM           0x5a5a5a5a
+#define INDICATOR_1_MAGIC_NUM           0x12345678
+#define INDICATOR_2_MAGIC_NUM           0x32fde438
+#define INDICATOR_3_MAGIC_NUM           0x8ab4c52c
+
+
+/* system lowpoer mode */
+#define LP_HW_VAD			(1 << 16)
+#define LP_STANDBY			(2 << 16)
+
+/* redefine CSR register */
+#define CSR_MXSTATUS	THEAD_C9XX_CSR_MXSTATUS
+#define CSR_MHCR		THEAD_C9XX_CSR_MHCR
+#define CSR_MCCR2		THEAD_C9XX_CSR_MCCR2
+#define CSR_MHINT		THEAD_C9XX_CSR_MHINT
+#define CSR_MHINT2_E	THEAD_C9XX_CSR_MHINT2
+#define CSR_MHINT4		THEAD_C9XX_CSR_MHINT4
+#define CSR_MSMPR		THEAD_C9XX_CSR_MSMPR
+#define CSR_SMPEN		CSR_MSMPR
+
+/* CSR_MHCR */
+#define MHCR_IE			_UL(0x00000001)
+#define MHCR_DE			_UL(0x00000002)
+
+/* CSR_MHINT */
+#define MHINT_DPLD		_UL(0x00000004)
+#define MHINT_IPLD		_UL(0x00000100)
+#define MHINT_L2PLD		_UL(0x00008000)
+
+/* CSR_MSMPR */
+#define MSMPR_MSPEN		_UL(0x00000001)
+
+#define CONFIG_SYS_CACHELINE_SIZE   64
+
+static unsigned long csr_mstatus;
+static unsigned long csr_mie;
+static unsigned long csr_mhcr;
+static unsigned long csr_mhint;
+static unsigned long csr_msmpen;
+static int hotplug_flag = 0;
+
+extern void __thead_pre_start_warm(void);
+extern void *_data_start, *_data_end, *_bss_start, *_bss_end, *_fw_end;
+
+static void light_set_lpmode(int mode)
+{
+	writel(mode, (volatile void *)REG_AON_CHIP_LP_MODE);
+}
+
+static void light_mastercore_entryboot_set()
+{
+	u32 t;
+
+	writel(INDICATOR_0_MAGIC_NUM, (volatile void *)REG_AON_STR_INDICATOR_0);
+	writel(INDICATOR_1_MAGIC_NUM, (volatile void *)REG_AON_STR_INDICATOR_1);
+	writel(INDICATOR_2_MAGIC_NUM, (volatile void *)REG_AON_STR_INDICATOR_2);
+	writel(INDICATOR_3_MAGIC_NUM, (volatile void *)REG_AON_STR_INDICATOR_3);
+
+	/* brom->spl entry addr */
+	writel(0xFF, (volatile void *)REG_AON_RESERVED_REG_0);
+	writel(0xE0000000, (volatile void *)REG_AON_RESERVED_REG_1);
+
+	/* spl->opensbi entry addr */
+	t = (ulong)&__thead_pre_start_warm;
+	writel(t, (volatile void *)REG_AON_RESERVED_REG_2);
+	t = (u64)(ulong)&__thead_pre_start_warm >> 32;
+	writel(t, (volatile void *)REG_AON_RESERVED_REG_3);
+}
+
+static void light_auxcore_entryboot_set()
+{
+	u32 t;
+
+	/* spl->opensbi entry addr */
+	t = (ulong)&__thead_pre_start_warm;
+	writel(t, (volatile void *)REG_C910_CORE0_RVBA_L);
+	writel(t, (volatile void *)REG_C910_CORE1_RVBA_L);
+	writel(t, (volatile void *)REG_C910_CORE2_RVBA_L);
+	writel(t, (volatile void *)REG_C910_CORE3_RVBA_L);
+	t = (u64)(ulong)&__thead_pre_start_warm >> 32;
+	writel(t, (volatile void *)REG_C910_CORE0_RVBA_H);
+	writel(t, (volatile void *)REG_C910_CORE1_RVBA_H);
+	writel(t, (volatile void *)REG_C910_CORE2_RVBA_H);
+	writel(t, (volatile void *)REG_C910_CORE3_RVBA_H);
+}
+
+void cpu_performance_disable(void)
+{
+	csr_write(CSR_SMPEN, 0x0);
+	csr_write(CSR_MHINT2_E, 0x0);
+	csr_write(CSR_MHINT4, 0x0);
+	csr_write(CSR_MCCR2, 0x02490009);
+	csr_write(CSR_MHCR, 0x11ff);
+	csr_write(CSR_MXSTATUS, 0xc0638000);
+	csr_write(CSR_MHINT, 0x24000);
+}
+
+static void light_mastercore_save(void)
+{
+	/* a) disable all irq */
+	csr_mstatus = csr_read_clear(CSR_MSTATUS, MSTATUS_MIE | MSTATUS_SIE);
+	csr_mie = csr_read_clear(CSR_MIE, MIP_MSIP | MIP_MTIP | MIP_MEIP | \
+				MIP_SSIP | MIP_STIP | MIP_SEIP );
+	hotplug_flag = 1;
+	/* b) close prefetch */
+	csr_mhint = csr_read_clear(CSR_MHINT, MHINT_L2PLD | MHINT_IPLD | MHINT_DPLD);
+	/* c) inv&clr d-call all */
+	dcache_ciall();
+	sync_is();
+	/* d) close dcache */
+	csr_mhcr = csr_read_clear(CSR_MHCR, MHCR_DE);
+	/* e) close smpen */
+	csr_msmpen = csr_read_clear(CSR_MSMPR, MSMPR_MSPEN);
+	/* f) fence iorw,iorw*/
+	mb();
+	/* g) sleepmode reg */
+	light_set_lpmode(LP_STANDBY);
+
+	/* set mastercore bootrom jump entry */
+	light_mastercore_entryboot_set();
+
+	cpu_performance_disable();
+
+	/* h) wfi */
+	wfi();
+	__thead_pre_start_warm();
+}
+
+static void light_auxcore_save(void)
+{
+	/* a) disable all irq */
+	csr_mstatus = csr_read_clear(CSR_MSTATUS, MSTATUS_MIE | MSTATUS_SIE);
+	csr_mie = csr_read_clear(CSR_MIE, MIP_MSIP | MIP_MTIP | MIP_MEIP | \
+				MIP_SSIP | MIP_STIP | MIP_SEIP );
+
+	hotplug_flag = 1;
+	/* b) close prefetch */
+	csr_mhint = csr_read_clear(CSR_MHINT, MHINT_L2PLD | MHINT_IPLD | MHINT_DPLD);
+	/* c) inv&clr d-call all */
+	dcache_ciall();
+	sync_is();
+	/* d) close dcache */
+	csr_mhcr = csr_read_clear(CSR_MHCR, MHCR_DE);
+	/* e) close smpen */
+	csr_msmpen = csr_read_clear(CSR_MSMPR, MSMPR_MSPEN);
+	/* f) fence iorw,iorw*/
+	mb();
+	/* g) sleepmode reg */
+
+	/* h) wfi : when test hotplug just comment wfi to continue run */
+	wfi();
+}
+
+static void light_auxcore_restore(u32 hartid)
+{
+	u32 val;
+
+	/* set auxcore bootrom jump entry after warm reset*/
+	light_auxcore_entryboot_set();
+
+	if (hotplug_flag) {
+		val = readl((volatile void *)REG_C910_SWRST);
+		val &= ~(1 << (hartid + 1));
+		writel(val, (volatile void *)REG_C910_SWRST);
+
+		val |= (1 << (hartid + 1));
+		writel(val, (volatile void *)REG_C910_SWRST);
+	}
+}
+
+static int light_hart_start(u32 hartid, ulong saddr)
+{
+	sbi_printf("core:%d %s: line:%d enter\n",current_hartid(), __func__, __LINE__);
+
+	/* send ipi to triger already plugout core which will be waiting in sbi_hsm_hart_wait
+	 * after reset.
+	 */
+	light_auxcore_restore(hartid);
+
+	sbi_printf("core:%d %s: line:%d exit\n", current_hartid(), __func__, __LINE__);
+
+	return 0;
+}
+
+static int light_hart_stop(void)
+{
+	sbi_printf("core:%d %s: line:%d enter\n",current_hartid(),  __func__, __LINE__);
+
+	light_auxcore_save();
+
+	sbi_printf("core:%d %s: line:%d exit\n", current_hartid(), __func__, __LINE__);
+
+	return 0;
+}
+
+static int light_hart_suspend(u32 suspend_type, ulong raddr)
+{
+	sbi_printf("core:%d %s: line:%d enter\n",current_hartid(),  __func__, __LINE__);
+	/* Use the generic code for retentive suspend. */
+	if (!(suspend_type & SBI_HSM_SUSP_NON_RET_BIT))
+		return SBI_ENOTSUPP;
+
+	light_mastercore_save();
+
+	sbi_printf("core:%d %s: line:%d exit\n", current_hartid(), __func__, __LINE__);
+	return 0;
+}
+
+static const struct sbi_hsm_device light_ppu = {
+	.name		= "light-ppu",
+	.hart_start	= light_hart_start,
+	.hart_stop	= light_hart_stop,
+	.hart_suspend	= light_hart_suspend,
+};
+
+static int light_final_init(bool cold_boot, const struct fdt_match *match)
+{
+	sbi_printf("core:%d %s: line:%d enter. cold_boot:%d\n",current_hartid(), __func__, __LINE__, cold_boot);
+	sbi_hsm_set_device(&light_ppu);
+
+	return 0;
+}
+
+static const struct fdt_match ligth_match[] = {
+	{ .compatible = "thead,light" },
+	{ },
+};
+
+const struct platform_override light = {
+	.match_table	= ligth_match,
+	.final_init	= light_final_init,
+};
--- a/platform/generic/objects.mk
+++ b/platform/generic/objects.mk
@@ -9,3 +9,4 @@

 platform-objs-y += platform.o
 platform-objs-y += sifive_fu540.o
+platform-objs-y += light_c910.o
--- a/platform/generic/platform.c
+++ b/platform/generic/platform.c
@@ -21,11 +21,28 @@
 #include <sbi_utils/timer/fdt_timer.h>
 #include <sbi_utils/ipi/fdt_ipi.h>
 #include <sbi_utils/reset/fdt_reset.h>
+#include <sbi/sbi_console.h>
+#include <sbi/riscv_io.h>
+
+#define PMP_BASE_ADDR			0xffdc020000UL
+#define PMP_SIZE_PER_CORE		0x4000UL
+#define TCM0_START_ADDR			0xffe0180000UL
+#define TCM0_END_ADDR			0xffe01c0000UL
+#define TCM1_START_ADDR			0xffe01c0000UL
+#define TCM1_END_ADDR			0xffe0200000UL
+#define RESERVED_START_ADDR		0xffe0200000UL
+#define RESERVED_END_ADDR		0xffe1000000UL
+#define PMP_ENTRY_BASE_ADDR		0x100UL
+#define PMP_ENTRY_START_ADDR(n)	(PMP_BASE_ADDR + PMP_ENTRY_BASE_ADDR + (n * 8))
+#define PMP_ENTRY_END_ADDR(n)	(PMP_ENTRY_START_ADDR(n) + 4)
+#define PMP_ENTRY_CFG_ADDR(n)	(PMP_BASE_ADDR + ((n / 4) * 4))

 extern const struct platform_override sifive_fu540;
+extern const struct platform_override light;

 static const struct platform_override *special_platforms[] = {
 	&sifive_fu540,
+	&light,
 };

 static const struct platform_override *generic_plat = NULL;
@@ -328,14 +345,109 @@ static void sbi_thead_pmu_set(unsigned long type, unsigned long idx, unsigned lo
 	}
 }

+static void sbi_thead_reserved_pmp_set(void)
+{
+	unsigned int num, reg_val;
+
+	for (num = 0; num < 4; num++) {
+		/*	pmp entry 28 for reserved memory	*/
+		writel(RESERVED_START_ADDR >> 12, (void *)(PMP_ENTRY_START_ADDR(28) + num*PMP_SIZE_PER_CORE));
+		writel(RESERVED_END_ADDR >> 12, (void *)(PMP_ENTRY_END_ADDR(28) + num*PMP_SIZE_PER_CORE));
+
+		/*	pmp entry 28 config	*/
+		reg_val = readl((void *)(PMP_ENTRY_CFG_ADDR(28) + num*PMP_SIZE_PER_CORE));
+		reg_val = (reg_val & 0xffffff00) | 0x040;
+		writel(reg_val, (void *)((PMP_ENTRY_CFG_ADDR(28) + num*PMP_SIZE_PER_CORE)));
+	}
+
+	sync_is();
+}
+
+static void sbi_thead_tcm0_pmp_set(unsigned long auth)
+{
+	sbi_printf("%s: auth:%lx \n", __func__, auth);
+	unsigned int num, reg_val;
+
+	reg_val = readl((void *)PMP_ENTRY_START_ADDR(26));
+
+	if (reg_val != TCM0_START_ADDR >> 12)
+		for(num = 0; num < 4; num++) {
+			/*	pmp entry 26 for dsp tcm0	*/
+			writel(TCM0_START_ADDR >> 12, (void *)(PMP_ENTRY_START_ADDR(26) + num*PMP_SIZE_PER_CORE));
+			writel(TCM0_END_ADDR >> 12, (void *)(PMP_ENTRY_END_ADDR(26) + num*PMP_SIZE_PER_CORE));
+		}
+
+	for(num = 0; num < 4; num++) {
+		/*	pmp entry 26 config	*/
+		reg_val = readl((void *)(PMP_ENTRY_CFG_ADDR(26) + num*PMP_SIZE_PER_CORE));
+		reg_val = (reg_val & 0xff00ffff) | (auth << 16);
+		writel(reg_val, (void *)(PMP_ENTRY_CFG_ADDR(26) + num*PMP_SIZE_PER_CORE));
+	}
+
+	sync_is();
+}
+
+static void sbi_thead_tcm1_pmp_set(unsigned long auth)
+{
+	sbi_printf("%s: auth:%lx \n", __func__, auth);
+	unsigned int num, reg_val;
+
+	reg_val = readl((void *)PMP_ENTRY_START_ADDR(27));
+	if (reg_val != TCM1_START_ADDR >> 12)
+		for (num = 0; num < 4; num++) {
+			/*	pmp entry 27 for dsp tcm1	*/
+			writel(TCM1_START_ADDR >> 12, (void *)(PMP_ENTRY_START_ADDR(27) + num*PMP_SIZE_PER_CORE));
+			writel(TCM1_END_ADDR >> 12, (void *)(PMP_ENTRY_END_ADDR(27) + num*PMP_SIZE_PER_CORE));
+		}
+
+	for (num = 0; num < 4; num++) {
+		/*	pmp entry 27 config	*/
+		reg_val = readl((void *)(PMP_ENTRY_CFG_ADDR(27) + num*PMP_SIZE_PER_CORE));
+		reg_val = (reg_val & 0x00ffffff) | (auth << 24);
+		writel(reg_val, (void *)(PMP_ENTRY_CFG_ADDR(27) + num*PMP_SIZE_PER_CORE));
+	}
+
+	sync_is();
+}
+
+static void sbi_thead_pmp_set(unsigned long idx, unsigned long auth)
+{
+	unsigned int reg_val;
+
+	if (idx !=0 && idx != 1)
+		return;
+
+	/*	read pmp entry 28	*/
+	reg_val = readl((void *)PMP_ENTRY_START_ADDR(28));
+
+	if (reg_val != RESERVED_START_ADDR >> 12)
+		sbi_thead_reserved_pmp_set();
+
+	switch (idx) {
+	case 0:
+		sbi_thead_tcm0_pmp_set(auth);
+		break;
+	case 1:
+		sbi_thead_tcm1_pmp_set(auth);
+		break;
+	default:
+		break;
+	}
+}
+
 static int thead_vendor_ext_provider(long extid, long funcid,
 	const struct sbi_trap_regs *regs, unsigned long *out_value,
 	struct sbi_trap_info *out_trap)
 {
+	sbi_printf("%s: extid:%lx funcid:%lx \n", __func__,
+				   extid, funcid);
 	switch (extid) {
-	case 0x09000001:
+	case SBI_EXT_VENDOR_PMU:
 		sbi_thead_pmu_set(regs->a0, regs->a1, regs->a2);
 		break;
+	case SBI_EXT_VENDOR_PMP:
+		sbi_thead_pmp_set(funcid, regs->a0);
+		break;
 	default:
 		while(1);
 	}
Author	SHA1	Message	Date
Han Gao	61d7484c75	ci: update toolchains Signed-off-by: Han Gao <gaohan@iscas.ac.cn>	2024-01-12 21:53:40 +08:00
thead_admin	00ce75ee41	Linux_SDK_V1.4.2 Signed-off-by: thead_admin <occ_thead@service.alibaba.com>	2024-01-12 21:53:40 +08:00
thead_admin	d35408efb1	Linux_SDK_V1.3.3 Signed-off-by: thead_admin <occ_thead@service.alibaba.com>	2024-01-12 21:53:40 +08:00
Jisheng Zhang	d16b0e0a00	lib: utils: reset: thead: add back "plic-delegate" handling When backporting commit 78c2b19218bd ("lib: utils/irqchip: Automatically delegate T-HEAD PLIC access"), we removed the delegate property handling as upstream does, but it will break sdk linux kernel which still relies on "plic-delegate" property, add back it.	2023-09-26 21:55:29 +08:00
Jisheng Zhang	58bc661d74	lib: utils/timer: add T-HEAD C9xx plic support For upstream linux kernel usage	2023-09-26 21:55:29 +08:00
Icenowy Zheng	2a01b611c9	lib: utils/ipi: add T-Head C9xx CLINT compatible backport commit a8ee82cd8c008f09c91b5c307de4c9b37660ff71 upstream Althoug the MTIMER part of a C9xx CLINT differs from a SiFive one, the MSWI part is compliant. Add T-Head C9xx CLINT compatible string to fdt_ipi_mswi code, sharing the same codepath with SiFive CLINT. Signed-off-by: Icenowy Zheng <uwu@icenowy.me> Reviewed-by: Anup Patel <anup@brainfault.org>	2023-09-26 21:55:29 +08:00
Samuel Holland	400de74755	lib: utils/irqchip: Automatically delegate T-HEAD PLIC access commit 78c2b19218bd62653b9fb31623a42ced45f38ea6 upstream The T-HEAD PLIC implementation requires setting a delegation bit to allow access from S-mode. Now that the T-HEAD PLIC has its own compatible string, set this bit automatically from the PLIC driver, instead of reaching into the PLIC's MMIO space from another driver. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Anup Patel <anup.patel@wdc.com>	2023-09-26 21:55:29 +08:00
Heinrich Schuchardt	ab383936e1	lib: utils: missing initialization in thead_reset_init commit 360ab88569201f8d282cf98546b86b8576b6f2ad upstream If property csr-copy does not exist, fdt_getprop() will return NULL and cnt will have a random value from the stack. Call clone_csrs() only if cnt is initialized to a non-zero value. Fixes: 49e422c5ad7a ("lib: utils: reset: Add T-HEAD sample platform reset driver") Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Anup Patel <anup.patel@wdc.com>	2023-09-26 21:55:29 +08:00
Fabrice Fontaine	f6e8831ac4	Makefile: unconditionally disable SSP Though -nostdlib is passed in CFLAGS, -fno-stack-protector must also be passed to avoid linking errors related to undefined references to '__stack_chk_guard' and '__stack_chk_fail' if toolchain enforces -fstack-protector. Fixes: - https://gitlab.com/kubu93/buildroot/-/jobs/1247043359 Signed-off-by: Fabrice Fontaine <fontaine.fabrice@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Xiang W <wxjstz@126.com>	2023-08-06 19:44:41 +08:00
Robert Nelson	44fe1cd431	fdt_serial_uart8250.c: add .compatible = "snps,dw-apb-uart", from Drew and Fu Wei Signed-off-by: Robert Nelson <robertcnelson@gmail.com>	2023-08-01 23:56:19 +08:00
Han Gao	24b6b1d418	feat: update SDK1.2.0 Signed-off-by: Han Gao <gaohan@iscas.ac.cn>	2023-07-30 03:23:20 +08:00
Han Gao	e042f21ecc	feat: add gcc-12 build Signed-off-by: Han Gao <gaohan@iscas.ac.cn>	2023-07-24 06:12:36 +08:00
Han Gao	574b950215	fix: maybe-uninitialized resovled Signed-off-by: Han Gao <gaohan@iscas.ac.cn>	2023-07-24 06:12:36 +08:00
Aurelien Jarno	0c27ac7f5d	Makefile: fix build with binutils 2.38 From version 2.38, binutils default to ISA spec version 20191213. This means that the csr read/write (csrr/csrw) instructions and fence.i instruction has separated from the `I` extension, become two standalone extensions: Zicsr and Zifencei. As the kernel uses those instruction, this causes the following build failure: CC lib/sbi/sbi_tlb.o <<BUILDDIR>>/lib/sbi/sbi_tlb.c: Assembler messages: <<BUILDDIR>>/lib/sbi/sbi_tlb.c:190: Error: unrecognized opcode `fence.i' make: *** [Makefile:431: <<BUILDDIR>>/build/lib/sbi/sbi_tlb.o] Error 1 The fix is to specify those extensions explicitly in -march. However as older binutils version do not support this, we first need to detect that. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Alexandre Ghiti <alexandre.ghiti@canonical.com> Reviewed-by: Anup Patel <anup@brainfault.org>	2023-07-24 06:12:36 +08:00
Rahul Pathak	d98da90a19	lib: sbi_illegal_insn: Fix FENCE.TSO emulation infinite trap loop In case of missing "FENCE.TSO" instruction implementation, opensbi can emulate the "FENCE.TSO" with "FENCE RW,RW", but mepc was not incremented to continue from the next instruction causing infinite trap. Fixes: cb8271c8 ("lib: sbi_illegal_insn: Add emulation for fence.tso") Signed-off-by: Rahul Pathak <rpathak@ventanamicro.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: Xiang W <wxjstz@126.com> Reviewed-by: Samuel Holland <samuel@sholland.org>	2023-04-12 09:21:26 +00:00
Samuel Holland	39d1e698c9	lib: sbi_illegal_insn: Add emulation for fence.tso While OpenC906 appears to properly decode `fence.tso` as a fence instruction[1], the version of the C906 taped out in the Allwinner D1 does not, and raises illegal instruction. Handle this errata by emulating `fence.tso` as `fence rw, rw`. [1]: https://github.com/T-head-Semi/openc906/blob/30827e7f/C906_RTL_FACTORY/gen_rtl/idu/rtl/aq_idu_id_decd.v#L2097 Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Anup Patel <anup@brainfault.org>	2023-04-12 09:21:16 +00:00
thead_admin	513f62819b	Linux_SDK_V1.1.2	2023-03-05 22:36:27 +08:00