ci: update toolchains

Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
Linux_SDK_V1.4.2
2026-06-21 17:22:26 +02:00 · 2024-01-12 21:53:40 +08:00 · 2024-01-12 21:53:40 +08:00 · 2024-01-12 21:53:40 +08:00 · 2023-09-26 21:55:29 +08:00 · 2023-09-26 21:55:29 +08:00
8 changed files with 104 additions and 16 deletions
--- a/.github/workflows/build.yml
+++ b/.github/workflows/build.yml
@@ -0,0 +1,64 @@
+name: thead-opensbi
+
+on:
+  push:
+  pull_request:
+  workflow_dispatch:
+  schedule:
+    - cron: "0 2 * * *"
+
+env:
+  xuantie_toolchain: https://occ-oss-prod.oss-cn-hangzhou.aliyuncs.com/resource//1698113812618
+  toolchain_file_name: Xuantie-900-gcc-linux-5.10.4-glibc-x86_64-V2.8.0-20231018.tar.gz
+  mainline_toolchain: https://github.com/riscv-collab/riscv-gnu-toolchain/releases/download/2023.10.18
+  mainline_toolchain_file_name: riscv64-glibc-ubuntu-22.04-gcc-nightly-2023.10.18-nightly.tar.gz
+  wget_alias: 'wget --retry-connrefused --waitretry=1 --read-timeout=20 --timeout=15 -t 0'
+  ARCH: riscv
+  CROSS_COMPILE: riscv64-unknown-linux-gnu-
+
+jobs:
+  build:
+    runs-on: ubuntu-22.04
+    strategy:
+      fail-fast: false
+      matrix:
+        name: [thead-gcc, gcc-13]
+
+    steps:
+      - name: Install software
+        run: |
+              sudo apt update && \
+              sudo apt install -y gdisk dosfstools g++-12-riscv64-linux-gnu cpp-12-riscv64-linux-gnu build-essential \
+                                  libncurses-dev gawk flex bison openssl libssl-dev tree \
+                                  dkms libelf-dev libudev-dev libpci-dev libiberty-dev autoconf device-tree-compiler
+
+      - name: Checkout opensbi
+        uses: actions/checkout@v4
+
+      - name: opensbi compile
+        run: |
+              mkdir output
+              if [[ ${{ matrix.name }} = "thead-gcc" ]]; then
+                ${wget_alias} ${xuantie_toolchain}/${toolchain_file_name}
+                tar -xvf ${toolchain_file_name} -C /opt
+                export PATH="/opt/Xuantie-900-gcc-linux-5.10.4-glibc-x86_64-V2.8.0/bin:$PATH"
+              else
+                ${wget_alias} ${mainline_toolchain}/${mainline_toolchain_file_name}
+                tar -xvf ${mainline_toolchain_file_name} -C /opt
+                export PATH="/opt/riscv/bin:$PATH"
+              fi
+              ${CROSS_COMPILE}gcc -v
+
+              pushd $PWD
+                make PLATFORM=generic FW_PIC=y
+                cp -v build/platform/generic/firmware/fw_dynamic.bin output/
+              popd
+              tree ${GITHUB_WORKSPACE}/output
+
+
+      - name: 'Upload Artifact'
+        uses: actions/upload-artifact@v3
+        with:
+          name: thead-opensbi-${{ matrix.name }}
+          path: output/fw_dynamic.bin
+          retention-days: 30
--- a/11
+++ b/11
@@ -106,6 +106,9 @@ ifndef PLATFORM_RISCV_XLEN
  endif
 endif

+# Check whether the assembler and the compiler support the Zicsr and Zifencei extensions
+CC_SUPPORT_ZICSR_ZIFENCEI := $(shell $(CC) $(CLANG_TARGET) $(RELAX_FLAG) -nostdlib -march=rv$(OPENSBI_CC_XLEN)imafd_zicsr_zifencei -x c /dev/null -o /dev/null 2>&1 | grep "zicsr\|zifencei" > /dev/null && echo n || echo y)
+
 # Setup list of objects.mk files
 ifdef PLATFORM
 platform-object-mks=$(shell if [ -d $(platform_src_dir)/ ]; then find $(platform_src_dir) -iname "objects.mk" | sort -r; fi)
@@ -157,7 +160,11 @@ ifndef PLATFORM_RISCV_ABI
 endif
 ifndef PLATFORM_RISCV_ISA
  ifneq ($(PLATFORM_RISCV_TOOLCHAIN_DEFAULT), 1)
-    PLATFORM_RISCV_ISA = rv$(PLATFORM_RISCV_XLEN)imafdc
+    ifeq ($(CC_SUPPORT_ZICSR_ZIFENCEI), y)
+      PLATFORM_RISCV_ISA = rv$(PLATFORM_RISCV_XLEN)imafdc_zicsr_zifencei
+    else
+      PLATFORM_RISCV_ISA = rv$(PLATFORM_RISCV_XLEN)imafdc
+    endif
  else
    PLATFORM_RISCV_ISA = $(OPENSBI_CC_ISA)
  endif
@@ -203,7 +210,7 @@ GENFLAGS	+=	$(libsbiutils-genflags-y)
 GENFLAGS	+=	$(platform-genflags-y)
 GENFLAGS	+=	$(firmware-genflags-y)

-CFLAGS		=	-g -Wall -Werror -ffreestanding -nostdlib -fno-strict-aliasing -O2
+CFLAGS		=	-g -Wall -Werror -ffreestanding -nostdlib -fno-stack-protector -fno-strict-aliasing -O2
 CFLAGS		+=	-fno-omit-frame-pointer -fno-optimize-sibling-calls
 CFLAGS		+=	-mno-save-restore -mstrict-align
 CFLAGS		+=	-mabi=$(PLATFORM_RISCV_ABI) -march=$(PLATFORM_RISCV_ISA)
--- a/docs/platform/thead-c9xx.md
+++ b/docs/platform/thead-c9xx.md
@@ -51,11 +51,6 @@ DTS Example1: (Single core, eg: Allwinner D1 - c906)
 		compatible = "simple-bus";
 		ranges;

-		reset: reset-sample {
-			compatible = "thead,reset-sample";
-			plic-delegate = <0x0 0x101ffffc>;
-		};
-
 		clint0: clint@14000000 {
 			compatible = "riscv,clint0";
 			interrupts-extended = <
@@ -67,7 +62,8 @@ DTS Example1: (Single core, eg: Allwinner D1 - c906)

 		intc: interrupt-controller@10000000 {
 			#interrupt-cells = <1>;
-			compatible = "riscv,plic0";
+			compatible = "allwinner,sun20i-d1-plic",
+				     "thead,c900-plic";
 			interrupt-controller;
 			interrupts-extended = <
 				&cpu0_intc  0xffffffff &cpu0_intc  9
@@ -150,7 +146,6 @@ DTS Example2: (Multi cores with soc reset-regs)

 		reset: reset-sample {
 			compatible = "thead,reset-sample";
-			plic-delegate = <0xff 0xd81ffffc>;
 			entry-reg = <0xff 0xff019050>;
 			entry-cnt = <4>;
 			control-reg = <0xff 0xff015004>;
@@ -173,7 +168,7 @@ DTS Example2: (Multi cores with soc reset-regs)

 		intc: interrupt-controller@ffd8000000 {
 			#interrupt-cells = <1>;
-			compatible = "riscv,plic0";
+			compatible = "thead,c900-plic";
 			interrupt-controller;
 			interrupts-extended = <
 				&cpu0_intc  0xffffffff &cpu0_intc  9
@@ -194,7 +189,6 @@ DTS Example2: (Multi cores with old reset csrs)
 ```
 	reset: reset-sample {
 		compatible = "thead,reset-sample";
-		plic-delegate = <0xff 0xd81ffffc>;
 		using-csr-reset;
 		csr-copy = <0x7c0 0x7c1 0x7c2 0x7c3 0x7c5 0x7cc
 			    0x3b0 0x3b1 0x3b2 0x3b3
--- a/lib/utils/ipi/fdt_ipi_clint.c
+++ b/lib/utils/ipi/fdt_ipi_clint.c
@@ -37,6 +37,7 @@ static int ipi_clint_cold_init(void *fdt, int nodeoff,
 static const struct fdt_match ipi_clint_match[] = {
 	{ .compatible = "riscv,clint0" },
 	{ .compatible = "sifive,clint0" },
+	{ .compatible = "thead,c900-clint" },
 	{ },
 };

--- a/lib/utils/irqchip/fdt_irqchip_plic.c
+++ b/lib/utils/irqchip/fdt_irqchip_plic.c
@@ -9,6 +9,7 @@

 #include <libfdt.h>
 #include <sbi/riscv_asm.h>
+#include <sbi/riscv_io.h>
 #include <sbi/sbi_error.h>
 #include <sbi/sbi_hartmask.h>
 #include <sbi_utils/fdt/fdt_helper.h>
@@ -91,6 +92,11 @@ static int irqchip_plic_cold_init(void *fdt, int nodeoff,
 	if (rc)
 		return rc;

+	if (match->data) {
+		void (*plic_plat_init)(struct plic_data *) = match->data;
+		plic_plat_init(pd);
+	}
+
 	rc = plic_cold_irqchip_init(pd);
 	if (rc)
 		return rc;
@@ -106,9 +112,18 @@ static int irqchip_plic_cold_init(void *fdt, int nodeoff,
 	return irqchip_plic_update_hartid_table(fdt, nodeoff, pd);
 }

+#define THEAD_PLIC_CTRL_REG 0x1ffffc
+
+static void thead_plic_plat_init(struct plic_data *pd)
+{
+	writel_relaxed(BIT(0), (void *)pd->addr + THEAD_PLIC_CTRL_REG);
+}
+
 static const struct fdt_match irqchip_plic_match[] = {
 	{ .compatible = "riscv,plic0" },
 	{ .compatible = "sifive,plic-1.0.0" },
+	{ .compatible = "thead,c900-plic",
+	  .data = thead_plic_plat_init },
 	{ },
 };

--- a/lib/utils/reset/fdt_reset_thead.c
+++ b/lib/utils/reset/fdt_reset_thead.c
@@ -62,24 +62,25 @@ static int thead_reset_init(void *fdt, int nodeoff,
 	void *p;
 	const fdt64_t *val;
 	const fdt32_t *val_w;
-	int len, i, cnt = 0;
+	int len, i;
 	u32 t, tmp = 0;

 	/* Prepare clone csrs */
 	val_w = fdt_getprop(fdt, nodeoff, "csr-copy", &len);
 	if (len > 0 && val_w) {
-		cnt = len / sizeof(fdt32_t);
+		int cnt;

+		cnt = len / sizeof(fdt32_t);
 		if (cnt > MAX_CUSTOM_CSR)
 			sbi_hart_hang();

 		for (i = 0; i < cnt; i++) {
 			custom_csr[i].index = fdt32_to_cpu(val_w[i]);
 		}
-	}

-	if (cnt)
-		clone_csrs(cnt);
+		if (cnt)
+			clone_csrs(cnt);
+	}

 	/* Delegate plic enable regs for S-mode */
 	val = fdt_getprop(fdt, nodeoff, "plic-delegate", &len);
--- a/lib/utils/serial/fdt_serial_uart8250.c
+++ b/lib/utils/serial/fdt_serial_uart8250.c
@@ -28,6 +28,7 @@ static int serial_uart8250_init(void *fdt, int nodeoff,
 static const struct fdt_match serial_uart8250_match[] = {
 	{ .compatible = "ns16550" },
 	{ .compatible = "ns16550a" },
+	{ .compatible = "snps,dw-apb-uart" },
 	{ },
 };

--- a/lib/utils/timer/fdt_timer_clint.c
+++ b/lib/utils/timer/fdt_timer_clint.c
@@ -7,6 +7,7 @@
 *   Anup Patel <anup.patel@wdc.com>
 */

+#include <libfdt.h>
 #include <sbi/sbi_error.h>
 #include <sbi_utils/fdt/fdt_helper.h>
 #include <sbi_utils/timer/fdt_timer.h>
@@ -33,12 +34,16 @@ static int timer_clint_cold_init(void *fdt, int nodeoff,
 	if (rc)
 		return rc;

+	if (fdt_node_check_compatible(fdt, nodeoff, "thead,c900-clint") >= 0)
+		ct->has_64bit_mmio = FALSE;
+
 	return clint_cold_timer_init(ct, ctmaster);
 }

 static const struct fdt_match timer_clint_match[] = {
 	{ .compatible = "riscv,clint0" },
 	{ .compatible = "sifive,clint0" },
+	{ .compatible = "thead,c900-clint" },
 	{ },
 };
Author	SHA1	Message	Date
Han Gao	61d7484c75	ci: update toolchains Signed-off-by: Han Gao <gaohan@iscas.ac.cn>	2024-01-12 21:53:40 +08:00
thead_admin	00ce75ee41	Linux_SDK_V1.4.2 Signed-off-by: thead_admin <occ_thead@service.alibaba.com>	2024-01-12 21:53:40 +08:00
thead_admin	d35408efb1	Linux_SDK_V1.3.3 Signed-off-by: thead_admin <occ_thead@service.alibaba.com>	2024-01-12 21:53:40 +08:00
Jisheng Zhang	d16b0e0a00	lib: utils: reset: thead: add back "plic-delegate" handling When backporting commit 78c2b19218bd ("lib: utils/irqchip: Automatically delegate T-HEAD PLIC access"), we removed the delegate property handling as upstream does, but it will break sdk linux kernel which still relies on "plic-delegate" property, add back it.	2023-09-26 21:55:29 +08:00
Jisheng Zhang	58bc661d74	lib: utils/timer: add T-HEAD C9xx plic support For upstream linux kernel usage	2023-09-26 21:55:29 +08:00
Icenowy Zheng	2a01b611c9	lib: utils/ipi: add T-Head C9xx CLINT compatible backport commit a8ee82cd8c008f09c91b5c307de4c9b37660ff71 upstream Althoug the MTIMER part of a C9xx CLINT differs from a SiFive one, the MSWI part is compliant. Add T-Head C9xx CLINT compatible string to fdt_ipi_mswi code, sharing the same codepath with SiFive CLINT. Signed-off-by: Icenowy Zheng <uwu@icenowy.me> Reviewed-by: Anup Patel <anup@brainfault.org>	2023-09-26 21:55:29 +08:00
Samuel Holland	400de74755	lib: utils/irqchip: Automatically delegate T-HEAD PLIC access commit 78c2b19218bd62653b9fb31623a42ced45f38ea6 upstream The T-HEAD PLIC implementation requires setting a delegation bit to allow access from S-mode. Now that the T-HEAD PLIC has its own compatible string, set this bit automatically from the PLIC driver, instead of reaching into the PLIC's MMIO space from another driver. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Anup Patel <anup.patel@wdc.com>	2023-09-26 21:55:29 +08:00
Heinrich Schuchardt	ab383936e1	lib: utils: missing initialization in thead_reset_init commit 360ab88569201f8d282cf98546b86b8576b6f2ad upstream If property csr-copy does not exist, fdt_getprop() will return NULL and cnt will have a random value from the stack. Call clone_csrs() only if cnt is initialized to a non-zero value. Fixes: 49e422c5ad7a ("lib: utils: reset: Add T-HEAD sample platform reset driver") Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Anup Patel <anup.patel@wdc.com>	2023-09-26 21:55:29 +08:00
Fabrice Fontaine	f6e8831ac4	Makefile: unconditionally disable SSP Though -nostdlib is passed in CFLAGS, -fno-stack-protector must also be passed to avoid linking errors related to undefined references to '__stack_chk_guard' and '__stack_chk_fail' if toolchain enforces -fstack-protector. Fixes: - https://gitlab.com/kubu93/buildroot/-/jobs/1247043359 Signed-off-by: Fabrice Fontaine <fontaine.fabrice@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Xiang W <wxjstz@126.com>	2023-08-06 19:44:41 +08:00
Robert Nelson	44fe1cd431	fdt_serial_uart8250.c: add .compatible = "snps,dw-apb-uart", from Drew and Fu Wei Signed-off-by: Robert Nelson <robertcnelson@gmail.com>	2023-08-01 23:56:19 +08:00
Han Gao	24b6b1d418	feat: update SDK1.2.0 Signed-off-by: Han Gao <gaohan@iscas.ac.cn>	2023-07-30 03:23:20 +08:00
Han Gao	e042f21ecc	feat: add gcc-12 build Signed-off-by: Han Gao <gaohan@iscas.ac.cn>	2023-07-24 06:12:36 +08:00
Han Gao	574b950215	fix: maybe-uninitialized resovled Signed-off-by: Han Gao <gaohan@iscas.ac.cn>	2023-07-24 06:12:36 +08:00
Aurelien Jarno	0c27ac7f5d	Makefile: fix build with binutils 2.38 From version 2.38, binutils default to ISA spec version 20191213. This means that the csr read/write (csrr/csrw) instructions and fence.i instruction has separated from the `I` extension, become two standalone extensions: Zicsr and Zifencei. As the kernel uses those instruction, this causes the following build failure: CC lib/sbi/sbi_tlb.o <<BUILDDIR>>/lib/sbi/sbi_tlb.c: Assembler messages: <<BUILDDIR>>/lib/sbi/sbi_tlb.c:190: Error: unrecognized opcode `fence.i' make: *** [Makefile:431: <<BUILDDIR>>/build/lib/sbi/sbi_tlb.o] Error 1 The fix is to specify those extensions explicitly in -march. However as older binutils version do not support this, we first need to detect that. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Alexandre Ghiti <alexandre.ghiti@canonical.com> Reviewed-by: Anup Patel <anup@brainfault.org>	2023-07-24 06:12:36 +08:00
Rahul Pathak	d98da90a19	lib: sbi_illegal_insn: Fix FENCE.TSO emulation infinite trap loop In case of missing "FENCE.TSO" instruction implementation, opensbi can emulate the "FENCE.TSO" with "FENCE RW,RW", but mepc was not incremented to continue from the next instruction causing infinite trap. Fixes: cb8271c8 ("lib: sbi_illegal_insn: Add emulation for fence.tso") Signed-off-by: Rahul Pathak <rpathak@ventanamicro.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: Xiang W <wxjstz@126.com> Reviewed-by: Samuel Holland <samuel@sholland.org>	2023-04-12 09:21:26 +00:00
Samuel Holland	39d1e698c9	lib: sbi_illegal_insn: Add emulation for fence.tso While OpenC906 appears to properly decode `fence.tso` as a fence instruction[1], the version of the C906 taped out in the Allwinner D1 does not, and raises illegal instruction. Handle this errata by emulating `fence.tso` as `fence rw, rw`. [1]: https://github.com/T-head-Semi/openc906/blob/30827e7f/C906_RTL_FACTORY/gen_rtl/idu/rtl/aq_idu_id_decd.v#L2097 Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Anup Patel <anup@brainfault.org>	2023-04-12 09:21:16 +00:00