Linux_SDK_V1.3.3

Signed-off-by: thead_admin <occ_thead@service.alibaba.com>
lib/sbi/illegal_insn.c: add emulation for fence.tso
2026-06-21 17:22:26 +02:00 · 2023-12-24 19:25:47 +08:00 · 2023-07-30 04:24:52 +08:00 · 2023-07-30 04:24:38 +08:00
10 changed files with 17 additions and 219 deletions
--- a/.github/workflows/build.yml
+++ b/.github/workflows/build.yml
@@ -1,64 +0,0 @@
-name: thead-opensbi
-
-on:
-  push:
-  pull_request:
-  workflow_dispatch:
-  schedule:
-    - cron: "0 2 * * *"
-
-env:
-  xuantie_toolchain: https://occ-oss-prod.oss-cn-hangzhou.aliyuncs.com/resource//1698113812618
-  toolchain_file_name: Xuantie-900-gcc-linux-5.10.4-glibc-x86_64-V2.8.0-20231018.tar.gz
-  mainline_toolchain: https://github.com/riscv-collab/riscv-gnu-toolchain/releases/download/2023.10.18
-  mainline_toolchain_file_name: riscv64-glibc-ubuntu-22.04-gcc-nightly-2023.10.18-nightly.tar.gz
-  wget_alias: 'wget --retry-connrefused --waitretry=1 --read-timeout=20 --timeout=15 -t 0'
-  ARCH: riscv
-  CROSS_COMPILE: riscv64-unknown-linux-gnu-
-
-jobs:
-  build:
-    runs-on: ubuntu-22.04
-    strategy:
-      fail-fast: false
-      matrix:
-        name: [thead-gcc, gcc-13]
-
-    steps:
-      - name: Install software
-        run: |
-              sudo apt update && \
-              sudo apt install -y gdisk dosfstools g++-12-riscv64-linux-gnu cpp-12-riscv64-linux-gnu build-essential \
-                                  libncurses-dev gawk flex bison openssl libssl-dev tree \
-                                  dkms libelf-dev libudev-dev libpci-dev libiberty-dev autoconf device-tree-compiler
-
-      - name: Checkout opensbi
-        uses: actions/checkout@v4
-
-      - name: opensbi compile
-        run: |
-              mkdir output
-              if [[ ${{ matrix.name }} = "thead-gcc" ]]; then
-                ${wget_alias} ${xuantie_toolchain}/${toolchain_file_name}
-                tar -xvf ${toolchain_file_name} -C /opt
-                export PATH="/opt/Xuantie-900-gcc-linux-5.10.4-glibc-x86_64-V2.8.0/bin:$PATH"
-              else
-                ${wget_alias} ${mainline_toolchain}/${mainline_toolchain_file_name}
-                tar -xvf ${mainline_toolchain_file_name} -C /opt
-                export PATH="/opt/riscv/bin:$PATH"
-              fi
-              ${CROSS_COMPILE}gcc -v
-
-              pushd $PWD
-                make PLATFORM=generic FW_PIC=y
-                cp -v build/platform/generic/firmware/fw_dynamic.bin output/
-              popd
-              tree ${GITHUB_WORKSPACE}/output
-
-
-      - name: 'Upload Artifact'
-        uses: actions/upload-artifact@v3
-        with:
-          name: thead-opensbi-${{ matrix.name }}
-          path: output/fw_dynamic.bin
-          retention-days: 30
--- a/11
+++ b/11
@@ -106,9 +106,6 @@ ifndef PLATFORM_RISCV_XLEN
  endif
 endif

-# Check whether the assembler and the compiler support the Zicsr and Zifencei extensions
-CC_SUPPORT_ZICSR_ZIFENCEI := $(shell $(CC) $(CLANG_TARGET) $(RELAX_FLAG) -nostdlib -march=rv$(OPENSBI_CC_XLEN)imafd_zicsr_zifencei -x c /dev/null -o /dev/null 2>&1 | grep "zicsr\|zifencei" > /dev/null && echo n || echo y)
-
 # Setup list of objects.mk files
 ifdef PLATFORM
 platform-object-mks=$(shell if [ -d $(platform_src_dir)/ ]; then find $(platform_src_dir) -iname "objects.mk" | sort -r; fi)
@@ -160,11 +157,7 @@ ifndef PLATFORM_RISCV_ABI
 endif
 ifndef PLATFORM_RISCV_ISA
  ifneq ($(PLATFORM_RISCV_TOOLCHAIN_DEFAULT), 1)
-    ifeq ($(CC_SUPPORT_ZICSR_ZIFENCEI), y)
-      PLATFORM_RISCV_ISA = rv$(PLATFORM_RISCV_XLEN)imafdc_zicsr_zifencei
-    else
-      PLATFORM_RISCV_ISA = rv$(PLATFORM_RISCV_XLEN)imafdc
-    endif
+    PLATFORM_RISCV_ISA = rv$(PLATFORM_RISCV_XLEN)imafdc
  else
    PLATFORM_RISCV_ISA = $(OPENSBI_CC_ISA)
  endif
@@ -210,7 +203,7 @@ GENFLAGS	+=	$(libsbiutils-genflags-y)
 GENFLAGS	+=	$(platform-genflags-y)
 GENFLAGS	+=	$(firmware-genflags-y)

-CFLAGS		=	-g -Wall -Werror -ffreestanding -nostdlib -fno-stack-protector -fno-strict-aliasing -O2
+CFLAGS		=	-g -Wall -Werror -ffreestanding -nostdlib -fno-strict-aliasing -O2
 CFLAGS		+=	-fno-omit-frame-pointer -fno-optimize-sibling-calls
 CFLAGS		+=	-mno-save-restore -mstrict-align
 CFLAGS		+=	-mabi=$(PLATFORM_RISCV_ABI) -march=$(PLATFORM_RISCV_ISA)
--- a/docs/platform/thead-c9xx.md
+++ b/docs/platform/thead-c9xx.md
@@ -51,6 +51,11 @@ DTS Example1: (Single core, eg: Allwinner D1 - c906)
 		compatible = "simple-bus";
 		ranges;

+		reset: reset-sample {
+			compatible = "thead,reset-sample";
+			plic-delegate = <0x0 0x101ffffc>;
+		};
+
 		clint0: clint@14000000 {
 			compatible = "riscv,clint0";
 			interrupts-extended = <
@@ -62,8 +67,7 @@ DTS Example1: (Single core, eg: Allwinner D1 - c906)

 		intc: interrupt-controller@10000000 {
 			#interrupt-cells = <1>;
-			compatible = "allwinner,sun20i-d1-plic",
-				     "thead,c900-plic";
+			compatible = "riscv,plic0";
 			interrupt-controller;
 			interrupts-extended = <
 				&cpu0_intc  0xffffffff &cpu0_intc  9
@@ -146,6 +150,7 @@ DTS Example2: (Multi cores with soc reset-regs)

 		reset: reset-sample {
 			compatible = "thead,reset-sample";
+			plic-delegate = <0xff 0xd81ffffc>;
 			entry-reg = <0xff 0xff019050>;
 			entry-cnt = <4>;
 			control-reg = <0xff 0xff015004>;
@@ -168,7 +173,7 @@ DTS Example2: (Multi cores with soc reset-regs)

 		intc: interrupt-controller@ffd8000000 {
 			#interrupt-cells = <1>;
-			compatible = "thead,c900-plic";
+			compatible = "riscv,plic0";
 			interrupt-controller;
 			interrupts-extended = <
 				&cpu0_intc  0xffffffff &cpu0_intc  9
@@ -189,6 +194,7 @@ DTS Example2: (Multi cores with old reset csrs)
 ```
 	reset: reset-sample {
 		compatible = "thead,reset-sample";
+		plic-delegate = <0xff 0xd81ffffc>;
 		using-csr-reset;
 		csr-copy = <0x7c0 0x7c1 0x7c2 0x7c3 0x7c5 0x7cc
 			    0x3b0 0x3b1 0x3b2 0x3b3
--- a/include/sbi/sbi_platform.h
+++ b/include/sbi/sbi_platform.h
@@ -45,10 +45,6 @@
 #include <sbi/sbi_scratch.h>
 #include <sbi/sbi_version.h>

-#define SBI_EXT_VENDOR_SMC      (SBI_EXT_VENDOR_START + 0)
-#define SBI_EXT_VENDOR_PMU      (SBI_EXT_VENDOR_START + 1)
-#define SBI_EXT_VENDOR_PMP      (SBI_EXT_VENDOR_START + 2)
-
 struct sbi_domain_memregion;
 struct sbi_trap_info;
 struct sbi_trap_regs;
--- a/lib/utils/ipi/fdt_ipi_clint.c
+++ b/lib/utils/ipi/fdt_ipi_clint.c
@@ -37,7 +37,6 @@ static int ipi_clint_cold_init(void *fdt, int nodeoff,
 static const struct fdt_match ipi_clint_match[] = {
 	{ .compatible = "riscv,clint0" },
 	{ .compatible = "sifive,clint0" },
-	{ .compatible = "thead,c900-clint" },
 	{ },
 };

--- a/lib/utils/irqchip/fdt_irqchip_plic.c
+++ b/lib/utils/irqchip/fdt_irqchip_plic.c
@@ -9,7 +9,6 @@

 #include <libfdt.h>
 #include <sbi/riscv_asm.h>
-#include <sbi/riscv_io.h>
 #include <sbi/sbi_error.h>
 #include <sbi/sbi_hartmask.h>
 #include <sbi_utils/fdt/fdt_helper.h>
@@ -92,11 +91,6 @@ static int irqchip_plic_cold_init(void *fdt, int nodeoff,
 	if (rc)
 		return rc;

-	if (match->data) {
-		void (*plic_plat_init)(struct plic_data *) = match->data;
-		plic_plat_init(pd);
-	}
-
 	rc = plic_cold_irqchip_init(pd);
 	if (rc)
 		return rc;
@@ -112,18 +106,9 @@ static int irqchip_plic_cold_init(void *fdt, int nodeoff,
 	return irqchip_plic_update_hartid_table(fdt, nodeoff, pd);
 }

-#define THEAD_PLIC_CTRL_REG 0x1ffffc
-
-static void thead_plic_plat_init(struct plic_data *pd)
-{
-	writel_relaxed(BIT(0), (void *)pd->addr + THEAD_PLIC_CTRL_REG);
-}
-
 static const struct fdt_match irqchip_plic_match[] = {
 	{ .compatible = "riscv,plic0" },
 	{ .compatible = "sifive,plic-1.0.0" },
-	{ .compatible = "thead,c900-plic",
-	  .data = thead_plic_plat_init },
 	{ },
 };

--- a/lib/utils/reset/fdt_reset_thead.c
+++ b/lib/utils/reset/fdt_reset_thead.c
@@ -62,26 +62,25 @@ static int thead_reset_init(void *fdt, int nodeoff,
 	void *p;
 	const fdt64_t *val;
 	const fdt32_t *val_w;
-	int len, i;
+	int len, i, cnt = 0;
 	u32 t, tmp = 0;

 	/* Prepare clone csrs */
 	val_w = fdt_getprop(fdt, nodeoff, "csr-copy", &len);
 	if (len > 0 && val_w) {
-		int cnt;
-
 		cnt = len / sizeof(fdt32_t);
+
 		if (cnt > MAX_CUSTOM_CSR)
 			sbi_hart_hang();

 		for (i = 0; i < cnt; i++) {
 			custom_csr[i].index = fdt32_to_cpu(val_w[i]);
 		}
-
-		if (cnt)
-			clone_csrs(cnt);
 	}

+	if (cnt)
+		clone_csrs(cnt);
+
 	/* Delegate plic enable regs for S-mode */
 	val = fdt_getprop(fdt, nodeoff, "plic-delegate", &len);
 	if (len > 0 && val) {
--- a/lib/utils/serial/fdt_serial_uart8250.c
+++ b/lib/utils/serial/fdt_serial_uart8250.c
@@ -28,7 +28,6 @@ static int serial_uart8250_init(void *fdt, int nodeoff,
 static const struct fdt_match serial_uart8250_match[] = {
 	{ .compatible = "ns16550" },
 	{ .compatible = "ns16550a" },
-	{ .compatible = "snps,dw-apb-uart" },
 	{ },
 };

--- a/lib/utils/timer/fdt_timer_clint.c
+++ b/lib/utils/timer/fdt_timer_clint.c
@@ -7,7 +7,6 @@
 *   Anup Patel <anup.patel@wdc.com>
 */

-#include <libfdt.h>
 #include <sbi/sbi_error.h>
 #include <sbi_utils/fdt/fdt_helper.h>
 #include <sbi_utils/timer/fdt_timer.h>
@@ -34,16 +33,12 @@ static int timer_clint_cold_init(void *fdt, int nodeoff,
 	if (rc)
 		return rc;

-	if (fdt_node_check_compatible(fdt, nodeoff, "thead,c900-clint") >= 0)
-		ct->has_64bit_mmio = FALSE;
-
 	return clint_cold_timer_init(ct, ctmaster);
 }

 static const struct fdt_match timer_clint_match[] = {
 	{ .compatible = "riscv,clint0" },
 	{ .compatible = "sifive,clint0" },
-	{ .compatible = "thead,c900-clint" },
 	{ },
 };

--- a/platform/generic/platform.c
+++ b/platform/generic/platform.c
@@ -21,21 +21,6 @@
 #include <sbi_utils/timer/fdt_timer.h>
 #include <sbi_utils/ipi/fdt_ipi.h>
 #include <sbi_utils/reset/fdt_reset.h>
-#include <sbi/sbi_console.h>
-#include <sbi/riscv_io.h>
-
-#define PMP_BASE_ADDR			0xffdc020000UL
-#define PMP_SIZE_PER_CORE		0x4000UL
-#define TCM0_START_ADDR			0xffe0180000UL
-#define TCM0_END_ADDR			0xffe01c0000UL
-#define TCM1_START_ADDR			0xffe01c0000UL
-#define TCM1_END_ADDR			0xffe0200000UL
-#define RESERVED_START_ADDR		0xffe0200000UL
-#define RESERVED_END_ADDR		0xffe1000000UL
-#define PMP_ENTRY_BASE_ADDR		0x100UL
-#define PMP_ENTRY_START_ADDR(n)	(PMP_BASE_ADDR + PMP_ENTRY_BASE_ADDR + (n * 8))
-#define PMP_ENTRY_END_ADDR(n)	(PMP_ENTRY_START_ADDR(n) + 4)
-#define PMP_ENTRY_CFG_ADDR(n)	(PMP_BASE_ADDR + ((n / 4) * 4))

 extern const struct platform_override sifive_fu540;
 extern const struct platform_override light;
@@ -345,109 +330,14 @@ static void sbi_thead_pmu_set(unsigned long type, unsigned long idx, unsigned lo
 	}
 }

-static void sbi_thead_reserved_pmp_set(void)
-{
-	unsigned int num, reg_val;
-
-	for (num = 0; num < 4; num++) {
-		/*	pmp entry 28 for reserved memory	*/
-		writel(RESERVED_START_ADDR >> 12, (void *)(PMP_ENTRY_START_ADDR(28) + num*PMP_SIZE_PER_CORE));
-		writel(RESERVED_END_ADDR >> 12, (void *)(PMP_ENTRY_END_ADDR(28) + num*PMP_SIZE_PER_CORE));
-
-		/*	pmp entry 28 config	*/
-		reg_val = readl((void *)(PMP_ENTRY_CFG_ADDR(28) + num*PMP_SIZE_PER_CORE));
-		reg_val = (reg_val & 0xffffff00) | 0x040;
-		writel(reg_val, (void *)((PMP_ENTRY_CFG_ADDR(28) + num*PMP_SIZE_PER_CORE)));
-	}
-
-	sync_is();
-}
-
-static void sbi_thead_tcm0_pmp_set(unsigned long auth)
-{
-	sbi_printf("%s: auth:%lx \n", __func__, auth);
-	unsigned int num, reg_val;
-
-	reg_val = readl((void *)PMP_ENTRY_START_ADDR(26));
-
-	if (reg_val != TCM0_START_ADDR >> 12)
-		for(num = 0; num < 4; num++) {
-			/*	pmp entry 26 for dsp tcm0	*/
-			writel(TCM0_START_ADDR >> 12, (void *)(PMP_ENTRY_START_ADDR(26) + num*PMP_SIZE_PER_CORE));
-			writel(TCM0_END_ADDR >> 12, (void *)(PMP_ENTRY_END_ADDR(26) + num*PMP_SIZE_PER_CORE));
-		}
-
-	for(num = 0; num < 4; num++) {
-		/*	pmp entry 26 config	*/
-		reg_val = readl((void *)(PMP_ENTRY_CFG_ADDR(26) + num*PMP_SIZE_PER_CORE));
-		reg_val = (reg_val & 0xff00ffff) | (auth << 16);
-		writel(reg_val, (void *)(PMP_ENTRY_CFG_ADDR(26) + num*PMP_SIZE_PER_CORE));
-	}
-
-	sync_is();
-}
-
-static void sbi_thead_tcm1_pmp_set(unsigned long auth)
-{
-	sbi_printf("%s: auth:%lx \n", __func__, auth);
-	unsigned int num, reg_val;
-
-	reg_val = readl((void *)PMP_ENTRY_START_ADDR(27));
-	if (reg_val != TCM1_START_ADDR >> 12)
-		for (num = 0; num < 4; num++) {
-			/*	pmp entry 27 for dsp tcm1	*/
-			writel(TCM1_START_ADDR >> 12, (void *)(PMP_ENTRY_START_ADDR(27) + num*PMP_SIZE_PER_CORE));
-			writel(TCM1_END_ADDR >> 12, (void *)(PMP_ENTRY_END_ADDR(27) + num*PMP_SIZE_PER_CORE));
-		}
-
-	for (num = 0; num < 4; num++) {
-		/*	pmp entry 27 config	*/
-		reg_val = readl((void *)(PMP_ENTRY_CFG_ADDR(27) + num*PMP_SIZE_PER_CORE));
-		reg_val = (reg_val & 0x00ffffff) | (auth << 24);
-		writel(reg_val, (void *)(PMP_ENTRY_CFG_ADDR(27) + num*PMP_SIZE_PER_CORE));
-	}
-
-	sync_is();
-}
-
-static void sbi_thead_pmp_set(unsigned long idx, unsigned long auth)
-{
-	unsigned int reg_val;
-
-	if (idx !=0 && idx != 1)
-		return;
-
-	/*	read pmp entry 28	*/
-	reg_val = readl((void *)PMP_ENTRY_START_ADDR(28));
-
-	if (reg_val != RESERVED_START_ADDR >> 12)
-		sbi_thead_reserved_pmp_set();
-
-	switch (idx) {
-	case 0:
-		sbi_thead_tcm0_pmp_set(auth);
-		break;
-	case 1:
-		sbi_thead_tcm1_pmp_set(auth);
-		break;
-	default:
-		break;
-	}
-}
-
 static int thead_vendor_ext_provider(long extid, long funcid,
 	const struct sbi_trap_regs *regs, unsigned long *out_value,
 	struct sbi_trap_info *out_trap)
 {
-	sbi_printf("%s: extid:%lx funcid:%lx \n", __func__,
-				   extid, funcid);
 	switch (extid) {
-	case SBI_EXT_VENDOR_PMU:
+	case 0x09000001:
 		sbi_thead_pmu_set(regs->a0, regs->a1, regs->a2);
 		break;
-	case SBI_EXT_VENDOR_PMP:
-		sbi_thead_pmp_set(funcid, regs->a0);
-		break;
 	default:
 		while(1);
 	}
Author	SHA1	Message	Date
thead_admin	4b124c86c2	Linux_SDK_V1.3.3 Signed-off-by: thead_admin <occ_thead@service.alibaba.com>	2023-12-24 19:25:47 +08:00
thead_admin	d5d8cd2e5c	lib/sbi/illegal_insn.c: add emulation for fence.tso	2023-07-30 04:24:52 +08:00
Han Gao	69a3baddbe	Linux_SDK_V1.2.0	2023-07-30 04:24:38 +08:00