mirror of
https://github.com/revyos/thead-opensbi.git
synced 2026-06-21 09:12:28 +02:00
484 lines
12 KiB
C
484 lines
12 KiB
C
/*
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2020 Western Digital Corporation or its affiliates.
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*
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* Authors:
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* Anup Patel <anup.patel@wdc.com>
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*/
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#include <libfdt.h>
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#include <platform_override.h>
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#include <sbi/riscv_asm.h>
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#include <sbi/sbi_hartmask.h>
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#include <sbi/sbi_platform.h>
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#include <sbi/sbi_string.h>
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#include <sbi_utils/fdt/fdt_domain.h>
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#include <sbi_utils/fdt/fdt_fixup.h>
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#include <sbi_utils/fdt/fdt_helper.h>
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#include <sbi_utils/irqchip/fdt_irqchip.h>
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#include <sbi_utils/serial/fdt_serial.h>
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#include <sbi_utils/timer/fdt_timer.h>
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#include <sbi_utils/ipi/fdt_ipi.h>
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#include <sbi_utils/reset/fdt_reset.h>
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#include <sbi/sbi_console.h>
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#include <sbi/riscv_io.h>
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#define PMP_BASE_ADDR 0xffdc020000UL
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#define PMP_SIZE_PER_CORE 0x4000UL
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#define TCM0_START_ADDR 0xffe0180000UL
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#define TCM0_END_ADDR 0xffe01c0000UL
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#define TCM1_START_ADDR 0xffe01c0000UL
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#define TCM1_END_ADDR 0xffe0200000UL
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#define RESERVED_START_ADDR 0xffe0200000UL
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#define RESERVED_END_ADDR 0xffe1000000UL
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#define PMP_ENTRY_BASE_ADDR 0x100UL
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#define PMP_ENTRY_START_ADDR(n) (PMP_BASE_ADDR + PMP_ENTRY_BASE_ADDR + (n * 8))
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#define PMP_ENTRY_END_ADDR(n) (PMP_ENTRY_START_ADDR(n) + 4)
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#define PMP_ENTRY_CFG_ADDR(n) (PMP_BASE_ADDR + ((n / 4) * 4))
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extern const struct platform_override sifive_fu540;
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extern const struct platform_override light;
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static const struct platform_override *special_platforms[] = {
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&sifive_fu540,
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&light,
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};
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static const struct platform_override *generic_plat = NULL;
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static const struct fdt_match *generic_plat_match = NULL;
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static void fw_platform_lookup_special(void *fdt, int root_offset)
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{
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int pos, noff;
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const struct platform_override *plat;
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const struct fdt_match *match;
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for (pos = 0; pos < array_size(special_platforms); pos++) {
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plat = special_platforms[pos];
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if (!plat->match_table)
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continue;
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noff = fdt_find_match(fdt, -1, plat->match_table, &match);
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if (noff < 0)
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continue;
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generic_plat = plat;
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generic_plat_match = match;
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break;
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}
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}
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extern struct sbi_platform platform;
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static u32 generic_hart_index2id[SBI_HARTMASK_MAX_BITS] = { 0 };
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/*
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* The fw_platform_init() function is called very early on the boot HART
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* OpenSBI reference firmwares so that platform specific code get chance
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* to update "platform" instance before it is used.
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*
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* The arguments passed to fw_platform_init() function are boot time state
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* of A0 to A4 register. The "arg0" will be boot HART id and "arg1" will
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* be address of FDT passed by previous booting stage.
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*
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* The return value of fw_platform_init() function is the FDT location. If
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* FDT is unchanged (or FDT is modified in-place) then fw_platform_init()
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* can always return the original FDT location (i.e. 'arg1') unmodified.
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*/
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unsigned long fw_platform_init(unsigned long arg0, unsigned long arg1,
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unsigned long arg2, unsigned long arg3,
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unsigned long arg4)
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{
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const char *model;
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void *fdt = (void *)arg1;
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u32 hartid, hart_count = 0;
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int rc, root_offset, cpus_offset, cpu_offset, len;
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root_offset = fdt_path_offset(fdt, "/");
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if (root_offset < 0)
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goto fail;
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fw_platform_lookup_special(fdt, root_offset);
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model = fdt_getprop(fdt, root_offset, "model", &len);
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if (model)
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sbi_strncpy(platform.name, model, sizeof(platform.name));
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if (generic_plat && generic_plat->features)
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platform.features = generic_plat->features(generic_plat_match);
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cpus_offset = fdt_path_offset(fdt, "/cpus");
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if (cpus_offset < 0)
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goto fail;
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fdt_for_each_subnode(cpu_offset, fdt, cpus_offset) {
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rc = fdt_parse_hart_id(fdt, cpu_offset, &hartid);
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if (rc)
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continue;
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if (SBI_HARTMASK_MAX_BITS <= hartid)
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continue;
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generic_hart_index2id[hart_count++] = hartid;
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}
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platform.hart_count = hart_count;
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/* Return original FDT pointer */
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return arg1;
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fail:
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while (1)
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wfi();
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}
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static int generic_early_init(bool cold_boot)
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{
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int rc;
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if (generic_plat && generic_plat->early_init) {
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rc = generic_plat->early_init(cold_boot, generic_plat_match);
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if (rc)
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return rc;
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}
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if (!cold_boot)
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return 0;
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return fdt_reset_init();
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}
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static int generic_final_init(bool cold_boot)
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{
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void *fdt;
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int rc;
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if (generic_plat && generic_plat->final_init) {
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rc = generic_plat->final_init(cold_boot, generic_plat_match);
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if (rc)
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return rc;
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}
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if (!cold_boot)
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return 0;
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fdt = sbi_scratch_thishart_arg1_ptr();
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fdt_cpu_fixup(fdt);
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fdt_fixups(fdt);
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fdt_domain_fixup(fdt);
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if (generic_plat && generic_plat->fdt_fixup) {
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rc = generic_plat->fdt_fixup(fdt, generic_plat_match);
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if (rc)
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return rc;
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}
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return 0;
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}
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static void generic_early_exit(void)
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{
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if (generic_plat && generic_plat->early_exit)
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generic_plat->early_exit(generic_plat_match);
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}
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static void generic_final_exit(void)
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{
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if (generic_plat && generic_plat->final_exit)
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generic_plat->final_exit(generic_plat_match);
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}
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static int generic_domains_init(void)
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{
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return fdt_domains_populate(sbi_scratch_thishart_arg1_ptr());
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}
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static u64 generic_tlbr_flush_limit(void)
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{
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if (generic_plat && generic_plat->tlbr_flush_limit)
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return generic_plat->tlbr_flush_limit(generic_plat_match);
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return SBI_PLATFORM_TLB_RANGE_FLUSH_LIMIT_DEFAULT;
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}
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#include <sbi/sbi_trap.h>
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#define CSR_MCOUNTERWEN 0x7c9
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static void sbi_thead_pmu_init(void)
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{
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unsigned long interrupts;
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interrupts = csr_read(CSR_MIDELEG) | (1 << 17);
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csr_write(CSR_MIDELEG, interrupts);
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/* CSR_MCOUNTEREN has already been set in mstatus_init() */
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csr_write(CSR_MCOUNTERWEN, 0xffffffff);
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csr_write(CSR_MHPMEVENT3, 1);
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csr_write(CSR_MHPMEVENT4, 2);
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csr_write(CSR_MHPMEVENT5, 3);
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csr_write(CSR_MHPMEVENT6, 4);
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csr_write(CSR_MHPMEVENT7, 5);
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csr_write(CSR_MHPMEVENT8, 6);
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csr_write(CSR_MHPMEVENT9, 7);
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csr_write(CSR_MHPMEVENT10, 8);
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csr_write(CSR_MHPMEVENT11, 9);
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csr_write(CSR_MHPMEVENT12, 10);
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csr_write(CSR_MHPMEVENT13, 11);
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csr_write(CSR_MHPMEVENT14, 12);
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csr_write(CSR_MHPMEVENT15, 13);
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csr_write(CSR_MHPMEVENT16, 14);
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csr_write(CSR_MHPMEVENT17, 15);
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csr_write(CSR_MHPMEVENT18, 16);
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csr_write(CSR_MHPMEVENT19, 17);
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csr_write(CSR_MHPMEVENT20, 18);
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csr_write(CSR_MHPMEVENT21, 19);
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csr_write(CSR_MHPMEVENT22, 20);
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csr_write(CSR_MHPMEVENT23, 21);
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csr_write(CSR_MHPMEVENT24, 22);
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csr_write(CSR_MHPMEVENT25, 23);
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csr_write(CSR_MHPMEVENT26, 24);
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csr_write(CSR_MHPMEVENT27, 25);
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csr_write(CSR_MHPMEVENT28, 26);
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}
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static void sbi_thead_pmu_map(unsigned long idx, unsigned long event_id)
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{
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switch (idx) {
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case 3:
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csr_write(CSR_MHPMEVENT3, event_id);
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break;
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case 4:
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csr_write(CSR_MHPMEVENT4, event_id);
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break;
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case 5:
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csr_write(CSR_MHPMEVENT5, event_id);
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break;
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case 6:
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csr_write(CSR_MHPMEVENT6, event_id);
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break;
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case 7:
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csr_write(CSR_MHPMEVENT7, event_id);
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break;
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case 8:
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csr_write(CSR_MHPMEVENT8, event_id);
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break;
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case 9:
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csr_write(CSR_MHPMEVENT9, event_id);
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break;
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case 10:
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csr_write(CSR_MHPMEVENT10, event_id);
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break;
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case 11:
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csr_write(CSR_MHPMEVENT11, event_id);
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break;
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case 12:
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csr_write(CSR_MHPMEVENT12, event_id);
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break;
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case 13:
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csr_write(CSR_MHPMEVENT13, event_id);
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break;
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case 14:
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csr_write(CSR_MHPMEVENT14, event_id);
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break;
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case 15:
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csr_write(CSR_MHPMEVENT15, event_id);
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break;
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case 16:
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csr_write(CSR_MHPMEVENT16, event_id);
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break;
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case 17:
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csr_write(CSR_MHPMEVENT17, event_id);
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break;
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case 18:
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csr_write(CSR_MHPMEVENT18, event_id);
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break;
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case 19:
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csr_write(CSR_MHPMEVENT19, event_id);
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break;
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case 20:
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csr_write(CSR_MHPMEVENT20, event_id);
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break;
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case 21:
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csr_write(CSR_MHPMEVENT21, event_id);
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break;
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case 22:
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csr_write(CSR_MHPMEVENT22, event_id);
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break;
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case 23:
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csr_write(CSR_MHPMEVENT23, event_id);
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break;
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case 24:
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csr_write(CSR_MHPMEVENT24, event_id);
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break;
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case 25:
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csr_write(CSR_MHPMEVENT25, event_id);
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break;
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case 26:
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csr_write(CSR_MHPMEVENT26, event_id);
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break;
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case 27:
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csr_write(CSR_MHPMEVENT27, event_id);
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break;
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case 28:
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csr_write(CSR_MHPMEVENT28, event_id);
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break;
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case 29:
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csr_write(CSR_MHPMEVENT29, event_id);
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break;
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case 30:
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csr_write(CSR_MHPMEVENT30, event_id);
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break;
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case 31:
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csr_write(CSR_MHPMEVENT31, event_id);
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break;
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}
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}
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static void sbi_thead_pmu_set(unsigned long type, unsigned long idx, unsigned long event_id)
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{
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switch (type) {
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case 2:
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sbi_thead_pmu_map(idx, event_id);
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break;
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default:
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sbi_thead_pmu_init();
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break;
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}
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}
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static void sbi_thead_reserved_pmp_set(void)
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{
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unsigned int num, reg_val;
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for (num = 0; num < 4; num++) {
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/* pmp entry 28 for reserved memory */
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writel(RESERVED_START_ADDR >> 12, (void *)(PMP_ENTRY_START_ADDR(28) + num*PMP_SIZE_PER_CORE));
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writel(RESERVED_END_ADDR >> 12, (void *)(PMP_ENTRY_END_ADDR(28) + num*PMP_SIZE_PER_CORE));
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/* pmp entry 28 config */
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reg_val = readl((void *)(PMP_ENTRY_CFG_ADDR(28) + num*PMP_SIZE_PER_CORE));
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reg_val = (reg_val & 0xffffff00) | 0x040;
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writel(reg_val, (void *)((PMP_ENTRY_CFG_ADDR(28) + num*PMP_SIZE_PER_CORE)));
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}
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sync_is();
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}
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static void sbi_thead_tcm0_pmp_set(unsigned long auth)
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{
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sbi_printf("%s: auth:%lx \n", __func__, auth);
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unsigned int num, reg_val;
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reg_val = readl((void *)PMP_ENTRY_START_ADDR(26));
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if (reg_val != TCM0_START_ADDR >> 12)
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for(num = 0; num < 4; num++) {
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/* pmp entry 26 for dsp tcm0 */
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writel(TCM0_START_ADDR >> 12, (void *)(PMP_ENTRY_START_ADDR(26) + num*PMP_SIZE_PER_CORE));
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writel(TCM0_END_ADDR >> 12, (void *)(PMP_ENTRY_END_ADDR(26) + num*PMP_SIZE_PER_CORE));
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}
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for(num = 0; num < 4; num++) {
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/* pmp entry 26 config */
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reg_val = readl((void *)(PMP_ENTRY_CFG_ADDR(26) + num*PMP_SIZE_PER_CORE));
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reg_val = (reg_val & 0xff00ffff) | (auth << 16);
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writel(reg_val, (void *)(PMP_ENTRY_CFG_ADDR(26) + num*PMP_SIZE_PER_CORE));
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}
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sync_is();
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}
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static void sbi_thead_tcm1_pmp_set(unsigned long auth)
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{
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sbi_printf("%s: auth:%lx \n", __func__, auth);
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unsigned int num, reg_val;
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reg_val = readl((void *)PMP_ENTRY_START_ADDR(27));
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if (reg_val != TCM1_START_ADDR >> 12)
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for (num = 0; num < 4; num++) {
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/* pmp entry 27 for dsp tcm1 */
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writel(TCM1_START_ADDR >> 12, (void *)(PMP_ENTRY_START_ADDR(27) + num*PMP_SIZE_PER_CORE));
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writel(TCM1_END_ADDR >> 12, (void *)(PMP_ENTRY_END_ADDR(27) + num*PMP_SIZE_PER_CORE));
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}
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for (num = 0; num < 4; num++) {
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/* pmp entry 27 config */
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reg_val = readl((void *)(PMP_ENTRY_CFG_ADDR(27) + num*PMP_SIZE_PER_CORE));
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reg_val = (reg_val & 0x00ffffff) | (auth << 24);
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writel(reg_val, (void *)(PMP_ENTRY_CFG_ADDR(27) + num*PMP_SIZE_PER_CORE));
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}
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sync_is();
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}
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static void sbi_thead_pmp_set(unsigned long idx, unsigned long auth)
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{
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unsigned int reg_val;
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if (idx !=0 && idx != 1)
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return;
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/* read pmp entry 28 */
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reg_val = readl((void *)PMP_ENTRY_START_ADDR(28));
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if (reg_val != RESERVED_START_ADDR >> 12)
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sbi_thead_reserved_pmp_set();
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switch (idx) {
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case 0:
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sbi_thead_tcm0_pmp_set(auth);
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break;
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case 1:
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sbi_thead_tcm1_pmp_set(auth);
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break;
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default:
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break;
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}
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}
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static int thead_vendor_ext_provider(long extid, long funcid,
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const struct sbi_trap_regs *regs, unsigned long *out_value,
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struct sbi_trap_info *out_trap)
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{
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sbi_printf("%s: extid:%lx funcid:%lx \n", __func__,
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extid, funcid);
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switch (extid) {
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case SBI_EXT_VENDOR_PMU:
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sbi_thead_pmu_set(regs->a0, regs->a1, regs->a2);
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break;
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case SBI_EXT_VENDOR_PMP:
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sbi_thead_pmp_set(funcid, regs->a0);
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break;
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default:
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while(1);
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}
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return 0;
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}
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const struct sbi_platform_operations platform_ops = {
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.vendor_ext_provider = thead_vendor_ext_provider,
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.early_init = generic_early_init,
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.final_init = generic_final_init,
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.early_exit = generic_early_exit,
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.final_exit = generic_final_exit,
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.domains_init = generic_domains_init,
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.console_init = fdt_serial_init,
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.irqchip_init = fdt_irqchip_init,
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.irqchip_exit = fdt_irqchip_exit,
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.ipi_init = fdt_ipi_init,
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.ipi_exit = fdt_ipi_exit,
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.get_tlbr_flush_limit = generic_tlbr_flush_limit,
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.timer_init = fdt_timer_init,
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.timer_exit = fdt_timer_exit,
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};
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struct sbi_platform platform = {
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.opensbi_version = OPENSBI_VERSION,
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.platform_version = SBI_PLATFORM_VERSION(0x0, 0x01),
|
|
.name = "Generic",
|
|
.features = SBI_PLATFORM_DEFAULT_FEATURES,
|
|
.hart_count = SBI_HARTMASK_MAX_BITS,
|
|
.hart_index2id = generic_hart_index2id,
|
|
.hart_stack_size = SBI_PLATFORM_DEFAULT_HART_STACK_SIZE,
|
|
.platform_ops_addr = (unsigned long)&platform_ops
|
|
};
|