Linux_SDK_V1.1.2

arch/riscv/cpu/c9xx/cpu.c

@@ -122,6 +122,7 @@ void invalid_dcache_range(unsigned long start, unsigned long end)
 
 void icache_enable(void)
 {
+#ifdef CONFIG_SPL_BUILD
 #ifdef CONFIG_SPL_RISCV_MMODE
 #ifdef CONFIG_TARGET_LIGHT_C910
 	asm volatile (
@@ -131,10 +132,12 @@ void icache_enable(void)
     );
 #endif
 #endif
+#endif
 }
 
 void dcache_enable(void)
 {
+#ifdef CONFIG_SPL_BUILD
 #ifdef CONFIG_SPL_RISCV_MMODE
 #ifdef CONFIG_TARGET_LIGHT_C910
 	asm volatile (
@@ -143,4 +146,5 @@ void dcache_enable(void)
     );
 #endif
 #endif
+#endif
 }

arch/riscv/cpu/mtrap.S

@@ -30,7 +30,9 @@
 	.align 2
 	.global trap_entry
 trap_entry:
+#ifndef CONFIG_THEAD_PLIC
 	ebreak
+#endif
 	addi sp, sp, -32 * REGBYTES
 	SREG x1,   1 * REGBYTES(sp)
 	SREG x2,   2 * REGBYTES(sp)

arch/riscv/dts/Makefile

@@ -5,7 +5,7 @@ dtb-$(CONFIG_TARGET_SIFIVE_FU540) += hifive-unleashed-a00.dtb
 dtb-$(CONFIG_TARGET_ICE_C910) += ice-c910.dtb
 dtb-$(CONFIG_TARGET_LIGHT_EVB_MPW_C910) += light-evb-mpw-c910.dtb
 dtb-$(CONFIG_TARGET_LIGHT_FPGA_FM_C910) += light-fpga-fm-c910.dtb
-dtb-$(CONFIG_TARGET_LIGHT_C910) += light-a-val.dtb light-b-product.dtb light-a-product.dtb light-ant-evt.dtb
+dtb-$(CONFIG_TARGET_LIGHT_C910) += light-a-ref.dtb light-b-ref.dtb light-a-val.dtb light-b-product.dtb light-a-product.dtb light-ant-ref.dtb light-beagle.dtb light-b-power.dtb light-lpi4a.dtb
 
 targets += $(dtb-y)
 

arch/riscv/dts/light-a-ref.dts

@@ -0,0 +1,482 @@
+/dts-v1/;
+/ {
+	model = "T-HEAD c910 light";
+	compatible = "thead,c910_light";
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	memory@0 {
+		device_type = "memory";
+		reg = <0x0 0xc0000000 0x0 0x40000000>;
+	};
+
+	aliases {
+		spi0 = &spi0;
+		spi1 = &qspi0;
+		spi2 = &qspi1;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		timebase-frequency = <3000000>;
+		u-boot,dm-pre-reloc;
+		cpu@0 {
+			device_type = "cpu";
+			reg = <0>;
+			status = "okay";
+			compatible = "riscv";
+			riscv,isa = "rv64imafdcvsu";
+			mmu-type = "riscv,sv39";
+			u-boot,dm-pre-reloc;
+		};
+	};
+
+	soc {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		compatible = "simple-bus";
+		ranges;
+		u-boot,dm-pre-reloc;
+
+		dummy_apb: apb-clock {
+			compatible = "fixed-clock";
+			clock-frequency = <62500000>;
+			clock-output-names = "dummy_apb";
+			#clock-cells = <0>;
+			u-boot,dm-pre-reloc;
+		};
+
+		dummy_ahb: ahb-clock {
+			compatible = "fixed-clock";
+			clock-frequency = <250000000>;
+			clock-output-names = "core";
+			#clock-cells = <0>;
+			u-boot,dm-pre-reloc;
+		};
+
+		dummy_spi: spi-clock {
+			compatible = "fixed-clock";
+			clock-frequency = <396000000>;
+			clock-output-names = "dummy_spi";
+			#clock-cells = <0>;
+			u-boot,dm-pre-reloc;
+		};
+
+		dummy_qspi0: qspi0-clock {
+			compatible = "fixed-clock";
+			clock-frequency = <792000000>;
+			clock-output-names = "dummy_qspi0";
+			#clock-cells = <0>;
+			u-boot,dm-pre-reloc;
+		};
+
+		dummy_uart_sclk: uart-sclk-clock {
+			compatible = "fixed-clock";
+			clock-frequency = <100000000>;
+			clock-output-names = "dummy_uart_sclk";
+			#clock-cells = <0>;
+			u-boot,dm-pre-reloc;
+		};
+
+		dummy_i2c_icclk: i2c-icclk-clock {
+			compatible = "fixed-clock";
+			clock-frequency = <50000000>;
+			clock-output-names = "dummy_i2c_icclk";
+			#clock-cells = <0>;
+			u-boot,dm-pre-reloc;
+		};
+
+		dummy_dpu_pixclk: dpu-pix-clock {
+			compatible = "fixed-clock";
+			clock-frequency = <74250000>;
+			clock-output-names = "dummy_dpu_pixclk";
+			#clock-cells = <0>;
+			u-boot,dm-pre-reloc;
+		};
+
+		dummy_dphy_refclk: dphy-ref-clock {
+			compatible = "fixed-clock";
+			clock-frequency = <24000000>;
+			clock-output-names = "dummy_dpu_refclk";
+			#clock-cells = <0>;
+			u-boot,dm-pre-reloc;
+		};
+
+		i2c0: i2c@ffe7f20000 {
+			compatible = "snps,designware-i2c";
+			reg = <0xff 0xe7f20000 0x0 0x4000>;
+			clocks = <&dummy_i2c_icclk>;
+			clock-frequency = <100000>;
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c1: i2c@ffe7f24000{
+			compatible = "snps,designware-i2c";
+			reg = <0xff 0xe7f24000 0x0 0x4000>;
+			clocks = <&dummy_i2c_icclk>;
+			clock-frequency = <100000>;
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c2: i2c@ffec00c000{
+			compatible = "snps,designware-i2c";
+			reg = <0xff 0xec00c000 0x0 0x4000>;
+			clocks = <&dummy_i2c_icclk>;
+			clock-frequency = <100000>;
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c3: i2c@ffec014000{
+			compatible = "snps,designware-i2c";
+			reg = <0xff 0xec014000 0x0 0x4000>;
+			clocks = <&dummy_i2c_icclk>;
+			clock-frequency = <100000>;
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c4: i2c@ffe7f28000{
+			compatible = "snps,designware-i2c";
+			reg = <0xff 0xe7f28000 0x0 0x4000>;
+			clocks = <&dummy_i2c_icclk>;
+			clock-frequency = <100000>;
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			pcal6408ahk_a: gpio@20 {
+				compatible = "nxp,pca9554";
+				reg = <0x20>;
+				gpio-controller;
+				#gpio-cells = <2>;
+			};
+		};
+
+		i2c5: i2c@fff7f2c000{
+			compatible = "snps,designware-i2c";
+			reg = <0xff 0xf7f2c000 0x0 0x4000>;
+			clocks = <&dummy_i2c_icclk>;
+			clock-frequency = <100000>;
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		serial@ffe7014000 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0xff 0xe7014000 0x0 0x400>;
+			clocks = <&dummy_uart_sclk>;
+			clock-frequency = <100000000>;
+			clock-names = "baudclk";
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			u-boot,dm-pre-reloc;
+		};
+
+		gmac0: ethernet@ffe7070000 {
+			compatible = "snps,dwmac";
+			reg = <0xff 0xe7070000 0x0 0x2000>;
+			clocks = <&dummy_apb>;
+			clock-names = "stmmaceth";
+			snps,pbl = <32>;
+			snps,fixed-burst;
+
+			phy-mode = "rgmii-id";
+			phy-handle = <&phy_88E1111_a>;
+			status = "okay";
+			mdio0 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "snps,dwmac-mdio";
+
+				phy_88E1111_a: ethernet-phy@1 {
+					reg = <0x1>;
+				};
+
+				phy_88E1111_b: ethernet-phy@2 {
+					reg = <0x2>;
+				};
+			};
+		};
+
+		gmac1: ethernet@ffe7060000 {
+			compatible = "snps,dwmac";
+			reg = <0xff 0xe7060000 0x0 0x2000>;
+			clocks = <&dummy_apb>;
+			clock-names = "stmmaceth";
+			snps,pbl = <32>;
+			snps,fixed-burst;
+			phy-mode = "rgmii-id";
+			phy-handle = <&phy_88E1111_b>;
+			status = "okay";
+		};
+
+		emmc: sdhci@ffe7080000 {
+			compatible = "snps,dwcmshc-sdhci";
+			reg = <0xff 0xe7080000 0x0 0x10000>;
+			index = <0x0>;
+			clocks = <&dummy_ahb>;
+			clock-frequency = <198000000>;
+			clock-names = "core";
+			max-frequency = <198000000>;
+			sdhci-caps-mask = <0x0 0x1000000>;
+			mmc-hs400-1_8v;
+			non-removable;
+			no-sdio;
+			no-sd;
+			bus-width = <8>;
+			voltage= "1.8v";
+			pull_up;
+			io_fixed_1v8;
+			fifo-mode;
+			u-boot,dm-pre-reloc;
+		};
+
+		sdhci0: sd@ffe7090000 {
+			compatible = "snps,dwcmshc-sdhci";
+			reg = <0xff 0xe7090000 0x0 0x10000>;
+			index = <0x1>;
+			clocks = <&dummy_ahb>;
+			clock-frequency = <198000000>;
+			max-frequency = <198000000>;
+			sd-uhs-sdr104;
+			pull_up;
+			clock-names = "core";
+			bus-width = <4>;
+			voltage= "3.3v";
+		};
+
+		qspi0: spi@ffea000000 {
+			compatible = "snps,dw-apb-ssi-quad";
+			reg = <0xff 0xea000000 0x0 0x1000>;
+			clocks = <&dummy_qspi0>;
+			num-cs = <1>;
+			cs-gpio = <&gpio2_porta 3 0>; // GPIO_ACTIVE_HIGH: 0
+			spi-max-frequency = <100000000>;
+			#address-cells = <1>;
+			#size-cells =<0>;
+			spi-flash@0 {
+				#address-cells = <1>;
+				#size-cells = <1>;
+				compatible = "spi-nand";
+				spi-tx-bus-width = <4>;
+				spi-rx-bus-width = <4>;
+				reg = <0>;
+			};
+		};
+
+		qspi1: spi@fff8000000 {
+			compatible = "snps,dw-apb-ssi-quad";
+			reg = <0xff 0xf8000000 0x0 0x1000>;
+			clocks = <&dummy_spi>;
+			num-cs = <1>;
+			cs-gpio = <&gpio0_porta 1 0>; // GPIO_ACTIVE_HIGH: 0
+			spi-max-frequency = <66000000>;
+			#address-cells = <1>;
+			#size-cells =<0>;
+			spi-flash@0 {
+				#address-cells = <1>;
+				#size-cells = <1>;
+				compatible = "spi-nand";
+				spi-tx-bus-width = <4>;
+				spi-rx-bus-width = <4>;
+				reg = <0>;
+			};
+		};
+
+		spi0: spi@ffe700c000 {
+			compatible = "snps,dw-apb-ssi";
+			reg = <0xff 0xe700c000 0x0 0x1000>;
+			clocks = <&dummy_spi>;
+			cs-gpio = <&gpio2_porta 15 0>;
+			spi-max-frequency = <100000000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			flash@0 {
+				compatible = "jedec,spi-nor";
+				reg = <0>;
+				spi-max-frequency = <40000000>;
+			};
+		};
+
+		gpio2: gpio@ffe7f34000 {
+			compatible = "snps,dw-apb-gpio";
+			reg = <0xff 0xe7f34000 0x0 0x1000>;
+			clocks = <&dummy_apb>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			gpio2_porta: gpio-controller@0 {
+				compatible = "snps,dw-apb-gpio-port";
+				gpio-controller;
+				#gpio-cells = <2>;
+				snps,nr-gpios = <32>;
+				reg = <0>;
+			};
+		};
+
+		gpio0: gpio@ffec005000 {
+			compatible = "snps,dw-apb-gpio";
+			reg = <0xff 0xec005000 0x0 0x1000>;
+			clocks = <&dummy_apb>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			gpio0_porta: gpio-controller@0 {
+				compatible = "snps,dw-apb-gpio-port";
+				gpio-controller;
+				#gpio-cells = <2>;
+				snps,nr-gpios = <32>;
+				reg = <0>;
+			};
+		};
+
+		gpio1: gpio@ffec006000 {
+			compatible = "snps,dw-apb-gpio";
+			reg = <0xff 0xec006000 0x0 0x1000>;
+			clocks = <&dummy_apb>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			gpio1_porta: gpio-controller@0 {
+				compatible = "snps,dw-apb-gpio-port";
+				gpio-controller;
+				#gpio-cells = <2>;
+				snps,nr-gpios = <32>;
+				reg = <0>;
+			};
+		};
+
+		pwm: pwm@ffec01c000 {
+			compatible = "thead,pwm-light";
+			reg = <0xff 0xec01c000 0x0 0x4000>;
+			#pwm-cells = <2>;
+		};
+
+		dsi_regs: dsi-controller@ffef500000 {
+			compatible = "thead,light-dsi-regs", "syscon";
+			reg = <0xff 0xef500000 0x0 0x10000>;
+			status = "okay";
+		};
+
+		vosys_regs: vosys@ffef528000 {
+			compatible = "thead,light-vo-subsys", "syscon";
+			reg = <0xff 0xef528000 0x0 0x1000>;
+			status = "okay";
+		};
+
+		dpu: dc8200@ffef600000 {
+			compatible = "verisilicon,dc8200";
+			reg = <0xff 0xef600000 0x0 0x100>;
+		};
+
+		axiscr {
+			compatible = "thead,axiscr";
+			reg = <0xff 0xff004000 0x0 0x1000>;
+			lock-read = "okay";
+			lock-write = "okay";
+			#address-cells = <2>;
+			#size-cells = <2>;
+			u-boot,dm-pre-reloc;
+			axiscr0: axisrc@0 {
+				device_type = "axiscr";
+				region = <0x00 0x00000000 0x00 0x80000000>; // 4KB align
+				status = "disabled";
+				#address-cells = <2>;
+				#size-cells = <2>;
+				u-boot,dm-pre-reloc;
+			};
+			axiscr1: axisrc@1 {
+				device_type = "axiscr";
+				region = <0x00 0x80000000 0x00 0x80000000>; // 4KB align
+				status = "disabled";
+				#address-cells = <2>;
+				#size-cells = <2>;
+				u-boot,dm-pre-reloc;
+			};
+			axiscr2: axisrc@2 {
+				device_type = "axiscr";
+				region = <0x01 0x00000000 0x00 0x80000000>; // 4KB align
+				status = "disabled";
+				#address-cells = <2>;
+				#size-cells = <2>;
+				u-boot,dm-pre-reloc;
+			};
+		};
+
+		axiparity {
+			compatible = "thead,axiparity";
+			reg = <0xff 0xff00c000 0x0 0x1000>;
+			lock = "okay";
+			#address-cells = <2>;
+			#size-cells = <2>;
+			u-boot,dm-pre-reloc;
+			axiparity0: axiparity@0 {
+				device_type = "axiparity";
+				region = <0x00 0x00000000 0x01 0x0000000>; // 4KB align
+				status = "disabled";
+				#address-cells = <2>;
+				#size-cells = <2>;
+				u-boot,dm-pre-reloc;
+			};
+			axiparity1: axiparity@1 {
+				device_type = "axiparity";
+				region = <0x01 0x00000000 0x01 0x00000000>; // 4KB align
+				status = "disabled";
+				#address-cells = <2>;
+				#size-cells = <2>;
+				u-boot,dm-pre-reloc;
+			};
+		};
+
+		dsi_bridge: dsi-bridge {
+			compatible = "thead,light-dsi-bridge";
+			clocks = <&dummy_dpu_pixclk>;
+			clock-names = "pix-clk";
+			phys = <&dsi_dphy>;
+			phy-names = "dphy";
+		};
+
+		dsi_host: dsi-host {
+			compatible = "synopsys,dw-mipi-dsi";
+			regmap = <&dsi_regs>;
+			status = "okay";
+		};
+
+		dsi_dphy: dsi-dphy {
+			compatible = "synopsys,dw-dphy";
+			regmap = <&dsi_regs>;
+			vosys-regmap = <&vosys_regs>;
+			clocks = <&dummy_dpu_pixclk>, <&dummy_dphy_refclk>;
+			clock-names = "pix-clk", "ref-clk";
+			#phy-cells = <0>;
+			status = "okay";
+		};
+
+		lcd_backlight: pwm-backlight {
+			compatible = "pwm-backlight";
+			pwms = <&pwm 0 5000000>;
+			brightness-levels = <0 4 8 16 32 64 128 255>;
+			default-brightness-level = <7>;
+		};
+
+		ili9881c_panel {
+			compatible      = "ilitek,ili9881c";
+			backlight       = <&lcd_backlight>;
+			reset-gpios     = <&gpio1_porta 5 1>;   /* active low  */
+			lcd-en-gpios    = <&pcal6408ahk_a 2 0>; /* active high */
+			lcd-bias-en-gpios = <&pcal6408ahk_a 4 0>;/* active high */
+		};
+	};
+
+	chosen {
+		bootargs = "console=ttyS0,115200";
+		stdout-path = "/soc/serial@ffe7014000:115200";
+	};
+};

arch/riscv/dts/light-a-val.dts

@@ -39,6 +39,12 @@
 		ranges;
 		u-boot,dm-pre-reloc;
 
+		intc: interrupt-controller@ffd8000000 {
+			compatible = "riscv,plic0";
+			reg = <0xff 0xd8000000 0x0 0x04000000>;
+			status = "disabled";
+		};
+
 		dummy_apb: apb-clock {
 			compatible = "fixed-clock";
 			clock-frequency = <62500000>;

arch/riscv/dts/light-b-power.dts

@@ -0,0 +1,478 @@
+/dts-v1/;
+/ {
+	model = "T-HEAD c910 light";
+	compatible = "thead,c910_light";
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	memory@0 {
+		device_type = "memory";
+		reg = <0x0 0xc0000000 0x0 0x40000000>;
+	};
+
+	aliases {
+		spi0 = &spi0;
+		spi1 = &qspi0;
+		spi2 = &qspi1;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		timebase-frequency = <3000000>;
+		u-boot,dm-pre-reloc;
+		cpu@0 {
+			device_type = "cpu";
+			reg = <0>;
+			status = "okay";
+			compatible = "riscv";
+			riscv,isa = "rv64imafdcvsu";
+			mmu-type = "riscv,sv39";
+			u-boot,dm-pre-reloc;
+		};
+	};
+
+	soc {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		compatible = "simple-bus";
+		ranges;
+		u-boot,dm-pre-reloc;
+
+		dummy_apb: apb-clock {
+			compatible = "fixed-clock";
+			clock-frequency = <62500000>;
+			clock-output-names = "dummy_apb";
+			#clock-cells = <0>;
+			u-boot,dm-pre-reloc;
+		};
+
+		dummy_ahb: ahb-clock {
+			compatible = "fixed-clock";
+			clock-frequency = <250000000>;
+			clock-output-names = "core";
+			#clock-cells = <0>;
+			u-boot,dm-pre-reloc;
+		};
+
+		dummy_spi: spi-clock {
+			compatible = "fixed-clock";
+			clock-frequency = <396000000>;
+			clock-output-names = "dummy_spi";
+			#clock-cells = <0>;
+			u-boot,dm-pre-reloc;
+		};
+
+		dummy_qspi0: qspi0-clock {
+			compatible = "fixed-clock";
+			clock-frequency = <792000000>;
+			clock-output-names = "dummy_qspi0";
+			#clock-cells = <0>;
+			u-boot,dm-pre-reloc;
+		};
+
+		dummy_uart_sclk: uart-sclk-clock {
+			compatible = "fixed-clock";
+			clock-frequency = <100000000>;
+			clock-output-names = "dummy_uart_sclk";
+			#clock-cells = <0>;
+			u-boot,dm-pre-reloc;
+		};
+
+		dummy_i2c_icclk: i2c-icclk-clock {
+			compatible = "fixed-clock";
+			clock-frequency = <50000000>;
+			clock-output-names = "dummy_i2c_icclk";
+			#clock-cells = <0>;
+			u-boot,dm-pre-reloc;
+		};
+
+		dummy_dpu_pixclk: dpu-pix-clock {
+			compatible = "fixed-clock";
+			clock-frequency = <74250000>;
+			clock-output-names = "dummy_dpu_pixclk";
+			#clock-cells = <0>;
+			u-boot,dm-pre-reloc;
+		};
+
+		dummy_dphy_refclk: dphy-ref-clock {
+			compatible = "fixed-clock";
+			clock-frequency = <24000000>;
+			clock-output-names = "dummy_dpu_refclk";
+			#clock-cells = <0>;
+			u-boot,dm-pre-reloc;
+		};
+
+		i2c0: i2c@ffe7f20000 {
+			compatible = "snps,designware-i2c";
+			reg = <0xff 0xe7f20000 0x0 0x4000>;
+			clocks = <&dummy_i2c_icclk>;
+			clock-frequency = <100000>;
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c1: i2c@ffe7f24000{
+			compatible = "snps,designware-i2c";
+			reg = <0xff 0xe7f24000 0x0 0x4000>;
+			clocks = <&dummy_i2c_icclk>;
+			clock-frequency = <100000>;
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c2: i2c@ffec00c000{
+			compatible = "snps,designware-i2c";
+			reg = <0xff 0xec00c000 0x0 0x4000>;
+			clocks = <&dummy_i2c_icclk>;
+			clock-frequency = <100000>;
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c3: i2c@ffec014000{
+			compatible = "snps,designware-i2c";
+			reg = <0xff 0xec014000 0x0 0x4000>;
+			clocks = <&dummy_i2c_icclk>;
+			clock-frequency = <100000>;
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c4: i2c@ffe7f28000{
+			compatible = "snps,designware-i2c";
+			reg = <0xff 0xe7f28000 0x0 0x4000>;
+			clocks = <&dummy_i2c_icclk>;
+			clock-frequency = <100000>;
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c5: i2c@fff7f2c000{
+			compatible = "snps,designware-i2c";
+			reg = <0xff 0xf7f2c000 0x0 0x4000>;
+			clocks = <&dummy_i2c_icclk>;
+			clock-frequency = <100000>;
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		serial@ffe7014000 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0xff 0xe7014000 0x0 0x400>;
+			clocks = <&dummy_uart_sclk>;
+			clock-frequency = <100000000>;
+			clock-names = "baudclk";
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			u-boot,dm-pre-reloc;
+		};
+
+		gmac0: ethernet@ffe7070000 {
+			compatible = "snps,dwmac";
+			reg = <0xff 0xe7070000 0x0 0x2000>;
+			clocks = <&dummy_apb>;
+			clock-names = "stmmaceth";
+			snps,pbl = <32>;
+			snps,fixed-burst;
+
+			phy-mode = "rgmii-id";
+			phy-handle = <&phy_88E1111_a>;
+			status = "okay";
+			mdio0 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "snps,dwmac-mdio";
+
+				phy_88E1111_a: ethernet-phy@1 {
+					reg = <0x1>;
+				};
+
+				phy_88E1111_b: ethernet-phy@2 {
+					reg = <0x2>;
+				};
+			};
+		};
+
+		gmac1: ethernet@ffe7060000 {
+			compatible = "snps,dwmac";
+			reg = <0xff 0xe7060000 0x0 0x2000>;
+			clocks = <&dummy_apb>;
+			clock-names = "stmmaceth";
+			snps,pbl = <32>;
+			snps,fixed-burst;
+			phy-mode = "rgmii-id";
+			phy-handle = <&phy_88E1111_b>;
+			status = "disabled";
+		};
+
+		emmc: sdhci@ffe7080000 {
+			compatible = "snps,dwcmshc-sdhci";
+			reg = <0xff 0xe7080000 0x0 0x10000>;
+			index = <0x0>;
+			clocks = <&dummy_ahb>;
+			clock-frequency = <198000000>;
+			clock-names = "core";
+			max-frequency = <198000000>;
+			sdhci-caps-mask = <0x0 0x1000000>;
+			mmc-hs400-1_8v;
+			non-removable;
+			no-sdio;
+			no-sd;
+			bus-width = <8>;
+			voltage= "1.8v";
+			pull_up;
+			io_fixed_1v8;
+			fifo-mode;
+			u-boot,dm-pre-reloc;
+		};
+
+		sdhci0: sd@ffe7090000 {
+			compatible = "snps,dwcmshc-sdhci";
+			reg = <0xff 0xe7090000 0x0 0x10000>;
+			index = <0x1>;
+			clocks = <&dummy_ahb>;
+			clock-frequency = <198000000>;
+			max-frequency = <198000000>;
+			sd-uhs-sdr104;
+			pull_up;
+			clock-names = "core";
+			bus-width = <4>;
+			voltage= "3.3v";
+		};
+
+		qspi0: spi@ffea000000 {
+			compatible = "snps,dw-apb-ssi-quad";
+			reg = <0xff 0xea000000 0x0 0x1000>;
+			clocks = <&dummy_qspi0>;
+			num-cs = <1>;
+			cs-gpio = <&gpio2_porta 3 0>; // GPIO_ACTIVE_HIGH: 0
+			spi-max-frequency = <100000000>;
+			#address-cells = <1>;
+			#size-cells =<0>;
+			status = "disabled";
+			spi-flash@0 {
+				#address-cells = <1>;
+				#size-cells = <1>;
+				compatible = "spi-nand";
+				spi-tx-bus-width = <4>;
+				spi-rx-bus-width = <4>;
+				reg = <0>;
+			};
+		};
+
+		qspi1: spi@fff8000000 {
+			compatible = "snps,dw-apb-ssi-quad";
+			reg = <0xff 0xf8000000 0x0 0x1000>;
+			clocks = <&dummy_spi>;
+			num-cs = <1>;
+			cs-gpio = <&gpio0_porta 1 0>; // GPIO_ACTIVE_HIGH: 0
+			spi-max-frequency = <66000000>;
+			#address-cells = <1>;
+			#size-cells =<0>;
+			status = "disabled";
+			spi-flash@0 {
+				#address-cells = <1>;
+				#size-cells = <1>;
+				compatible = "spi-nand";
+				spi-tx-bus-width = <4>;
+				spi-rx-bus-width = <4>;
+				reg = <0>;
+			};
+		};
+
+		spi0: spi@ffe700c000 {
+			compatible = "snps,dw-apb-ssi";
+			reg = <0xff 0xe700c000 0x0 0x1000>;
+			clocks = <&dummy_spi>;
+			cs-gpio = <&gpio2_porta 15 0>;
+			spi-max-frequency = <100000000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+			flash@0 {
+				compatible = "jedec,spi-nor";
+				reg = <0>;
+				spi-max-frequency = <40000000>;
+			};
+		};
+
+		gpio2: gpio@ffe7f34000 {
+			compatible = "snps,dw-apb-gpio";
+			reg = <0xff 0xe7f34000 0x0 0x1000>;
+			clocks = <&dummy_apb>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			gpio2_porta: gpio-controller@0 {
+				compatible = "snps,dw-apb-gpio-port";
+				gpio-controller;
+				#gpio-cells = <2>;
+				snps,nr-gpios = <32>;
+				reg = <0>;
+			};
+		};
+
+		gpio0: gpio@ffec005000 {
+			compatible = "snps,dw-apb-gpio";
+			reg = <0xff 0xec005000 0x0 0x1000>;
+			clocks = <&dummy_apb>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			gpio0_porta: gpio-controller@0 {
+				compatible = "snps,dw-apb-gpio-port";
+				gpio-controller;
+				#gpio-cells = <2>;
+				snps,nr-gpios = <32>;
+				reg = <0>;
+			};
+		};
+
+		gpio1: gpio@ffec006000 {
+			compatible = "snps,dw-apb-gpio";
+			reg = <0xff 0xec006000 0x0 0x1000>;
+			clocks = <&dummy_apb>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			gpio1_porta: gpio-controller@0 {
+				compatible = "snps,dw-apb-gpio-port";
+				gpio-controller;
+				#gpio-cells = <2>;
+				snps,nr-gpios = <32>;
+				reg = <0>;
+			};
+		};
+
+		pwm: pwm@ffec01c000 {
+			compatible = "thead,pwm-light";
+			reg = <0xff 0xec01c000 0x0 0x4000>;
+			#pwm-cells = <2>;
+		};
+
+		dsi_regs: dsi-controller@ffef500000 {
+			compatible = "thead,light-dsi-regs", "syscon";
+			reg = <0xff 0xef500000 0x0 0x10000>;
+			status = "okay";
+		};
+
+		vosys_regs: vosys@ffef528000 {
+			compatible = "thead,light-vo-subsys", "syscon";
+			reg = <0xff 0xef528000 0x0 0x1000>;
+			status = "okay";
+		};
+
+		dpu: dc8200@ffef600000 {
+			compatible = "verisilicon,dc8200";
+			reg = <0xff 0xef600000 0x0 0x100>;
+		};
+
+		axiscr {
+			compatible = "thead,axiscr";
+			reg = <0xff 0xff004000 0x0 0x1000>;
+			lock-read = "okay";
+			lock-write = "okay";
+			#address-cells = <2>;
+			#size-cells = <2>;
+			u-boot,dm-pre-reloc;
+			axiscr0: axisrc@0 {
+				device_type = "axiscr";
+				region = <0x00 0x00000000 0x00 0x80000000>; // 4KB align
+				status = "disabled";
+				#address-cells = <2>;
+				#size-cells = <2>;
+				u-boot,dm-pre-reloc;
+			};
+			axiscr1: axisrc@1 {
+				device_type = "axiscr";
+				region = <0x00 0x80000000 0x00 0x80000000>; // 4KB align
+				status = "disabled";
+				#address-cells = <2>;
+				#size-cells = <2>;
+				u-boot,dm-pre-reloc;
+			};
+			axiscr2: axisrc@2 {
+				device_type = "axiscr";
+				region = <0x01 0x00000000 0x00 0x80000000>; // 4KB align
+				status = "disabled";
+				#address-cells = <2>;
+				#size-cells = <2>;
+				u-boot,dm-pre-reloc;
+			};
+		};
+
+		axiparity {
+			compatible = "thead,axiparity";
+			reg = <0xff 0xff00c000 0x0 0x1000>;
+			lock = "okay";
+			#address-cells = <2>;
+			#size-cells = <2>;
+			u-boot,dm-pre-reloc;
+			axiparity0: axiparity@0 {
+				device_type = "axiparity";
+				region = <0x00 0x00000000 0x01 0x0000000>; // 4KB align
+				status = "disabled";
+				#address-cells = <2>;
+				#size-cells = <2>;
+				u-boot,dm-pre-reloc;
+			};
+			axiparity1: axiparity@1 {
+				device_type = "axiparity";
+				region = <0x01 0x00000000 0x01 0x00000000>; // 4KB align
+				status = "disabled";
+				#address-cells = <2>;
+				#size-cells = <2>;
+				u-boot,dm-pre-reloc;
+			};
+		};
+
+		dsi_bridge: dsi-bridge {
+			compatible = "thead,light-dsi-bridge";
+			clocks = <&dummy_dpu_pixclk>;
+			clock-names = "pix-clk";
+			phys = <&dsi_dphy>;
+			phy-names = "dphy";
+		};
+
+		dsi_host: dsi-host {
+			compatible = "synopsys,dw-mipi-dsi";
+			regmap = <&dsi_regs>;
+			status = "okay";
+		};
+
+		dsi_dphy: dsi-dphy {
+			compatible = "synopsys,dw-dphy";
+			regmap = <&dsi_regs>;
+			vosys-regmap = <&vosys_regs>;
+			clocks = <&dummy_dpu_pixclk>, <&dummy_dphy_refclk>;
+			clock-names = "pix-clk", "ref-clk";
+			#phy-cells = <0>;
+			status = "okay";
+		};
+
+		lcd_backlight: pwm-backlight {
+			compatible = "pwm-backlight";
+			pwms = <&pwm 0 5000000>;
+			brightness-levels = <0 4 8 16 32 64 128 255>;
+			default-brightness-level = <7>;
+		};
+
+		ili9881c_panel {
+			compatible      = "ilitek,ili9881c";
+			backlight       = <&lcd_backlight>;
+			reset-gpios     = <&gpio1_porta 5 1>;   /* active low  */
+			lcd-en-gpios    = <&gpio1_porta 9 0>; /* active high */
+			lcd-bias-en-gpios = <&gpio1_porta 10 0>;/* active high */
+		};
+	};
+
+	chosen {
+		bootargs = "console=ttyS0,115200";
+		stdout-path = "/soc/serial@ffe7014000:115200";
+	};
+};

arch/riscv/dts/light-b-product.dts

@@ -151,13 +151,6 @@
 
 			#address-cells = <1>;
 			#size-cells = <0>;
-
-			pcal6408ahk_a: gpio@20 {
-				compatible = "nxp,pca9554";
-				reg = <0x20>;
-				gpio-controller;
-				#gpio-cells = <2>;
-			};
 		};
 
 		i2c5: i2c@fff7f2c000{

arch/riscv/dts/light-b-ref.dts

@@ -0,0 +1,485 @@
+/dts-v1/;
+/ {
+	model = "T-HEAD c910 light";
+	compatible = "thead,c910_light";
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	memory@0 {
+		device_type = "memory";
+		reg = <0x0 0xc0000000 0x0 0x40000000>;
+	};
+
+	aliases {
+		spi0 = &spi0;
+		spi1 = &qspi0;
+		spi2 = &qspi1;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		timebase-frequency = <3000000>;
+		u-boot,dm-pre-reloc;
+		cpu@0 {
+			device_type = "cpu";
+			reg = <0>;
+			status = "okay";
+			compatible = "riscv";
+			riscv,isa = "rv64imafdcvsu";
+			mmu-type = "riscv,sv39";
+			u-boot,dm-pre-reloc;
+		};
+	};
+
+	soc {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		compatible = "simple-bus";
+		ranges;
+		u-boot,dm-pre-reloc;
+
+		dummy_apb: apb-clock {
+			compatible = "fixed-clock";
+			clock-frequency = <62500000>;
+			clock-output-names = "dummy_apb";
+			#clock-cells = <0>;
+			u-boot,dm-pre-reloc;
+		};
+
+		dummy_ahb: ahb-clock {
+			compatible = "fixed-clock";
+			clock-frequency = <250000000>;
+			clock-output-names = "core";
+			#clock-cells = <0>;
+			u-boot,dm-pre-reloc;
+		};
+
+		dummy_spi: spi-clock {
+			compatible = "fixed-clock";
+			clock-frequency = <396000000>;
+			clock-output-names = "dummy_spi";
+			#clock-cells = <0>;
+			u-boot,dm-pre-reloc;
+		};
+
+		dummy_qspi0: qspi0-clock {
+			compatible = "fixed-clock";
+			clock-frequency = <792000000>;
+			clock-output-names = "dummy_qspi0";
+			#clock-cells = <0>;
+			u-boot,dm-pre-reloc;
+		};
+
+		dummy_uart_sclk: uart-sclk-clock {
+			compatible = "fixed-clock";
+			clock-frequency = <100000000>;
+			clock-output-names = "dummy_uart_sclk";
+			#clock-cells = <0>;
+			u-boot,dm-pre-reloc;
+		};
+
+		dummy_i2c_icclk: i2c-icclk-clock {
+			compatible = "fixed-clock";
+			clock-frequency = <50000000>;
+			clock-output-names = "dummy_i2c_icclk";
+			#clock-cells = <0>;
+			u-boot,dm-pre-reloc;
+		};
+
+		dummy_dpu_pixclk: dpu-pix-clock {
+			compatible = "fixed-clock";
+			clock-frequency = <74250000>;
+			clock-output-names = "dummy_dpu_pixclk";
+			#clock-cells = <0>;
+			u-boot,dm-pre-reloc;
+		};
+
+		dummy_dphy_refclk: dphy-ref-clock {
+			compatible = "fixed-clock";
+			clock-frequency = <24000000>;
+			clock-output-names = "dummy_dpu_refclk";
+			#clock-cells = <0>;
+			u-boot,dm-pre-reloc;
+		};
+
+		i2c0: i2c@ffe7f20000 {
+			compatible = "snps,designware-i2c";
+			reg = <0xff 0xe7f20000 0x0 0x4000>;
+			clocks = <&dummy_i2c_icclk>;
+			clock-frequency = <100000>;
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c1: i2c@ffe7f24000{
+			compatible = "snps,designware-i2c";
+			reg = <0xff 0xe7f24000 0x0 0x4000>;
+			clocks = <&dummy_i2c_icclk>;
+			clock-frequency = <100000>;
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c2: i2c@ffec00c000{
+			compatible = "snps,designware-i2c";
+			reg = <0xff 0xec00c000 0x0 0x4000>;
+			clocks = <&dummy_i2c_icclk>;
+			clock-frequency = <100000>;
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c3: i2c@ffec014000{
+			compatible = "snps,designware-i2c";
+			reg = <0xff 0xec014000 0x0 0x4000>;
+			clocks = <&dummy_i2c_icclk>;
+			clock-frequency = <100000>;
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c4: i2c@ffe7f28000{
+			compatible = "snps,designware-i2c";
+			reg = <0xff 0xe7f28000 0x0 0x4000>;
+			clocks = <&dummy_i2c_icclk>;
+			clock-frequency = <100000>;
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			pcal6408ahk_a: gpio@20 {
+				compatible = "nxp,pca9554";
+				reg = <0x20>;
+				gpio-controller;
+				#gpio-cells = <2>;
+			};
+		};
+
+		i2c5: i2c@fff7f2c000{
+			compatible = "snps,designware-i2c";
+			reg = <0xff 0xf7f2c000 0x0 0x4000>;
+			clocks = <&dummy_i2c_icclk>;
+			clock-frequency = <100000>;
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		serial@ffe7014000 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0xff 0xe7014000 0x0 0x400>;
+			clocks = <&dummy_uart_sclk>;
+			clock-frequency = <100000000>;
+			clock-names = "baudclk";
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			u-boot,dm-pre-reloc;
+		};
+
+		gmac0: ethernet@ffe7070000 {
+			compatible = "snps,dwmac";
+			reg = <0xff 0xe7070000 0x0 0x2000>;
+			clocks = <&dummy_apb>;
+			clock-names = "stmmaceth";
+			snps,pbl = <32>;
+			snps,fixed-burst;
+
+			phy-mode = "rgmii-id";
+			phy-handle = <&phy_88E1111_a>;
+			status = "okay";
+			mdio0 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "snps,dwmac-mdio";
+
+				phy_88E1111_a: ethernet-phy@1 {
+					reg = <0x1>;
+				};
+
+				phy_88E1111_b: ethernet-phy@2 {
+					reg = <0x2>;
+				};
+			};
+		};
+
+		gmac1: ethernet@ffe7060000 {
+			compatible = "snps,dwmac";
+			reg = <0xff 0xe7060000 0x0 0x2000>;
+			clocks = <&dummy_apb>;
+			clock-names = "stmmaceth";
+			snps,pbl = <32>;
+			snps,fixed-burst;
+			phy-mode = "rgmii-id";
+			phy-handle = <&phy_88E1111_b>;
+			status = "disabled";
+		};
+
+		emmc: sdhci@ffe7080000 {
+			compatible = "snps,dwcmshc-sdhci";
+			reg = <0xff 0xe7080000 0x0 0x10000>;
+			index = <0x0>;
+			clocks = <&dummy_ahb>;
+			clock-frequency = <198000000>;
+			clock-names = "core";
+			max-frequency = <198000000>;
+			sdhci-caps-mask = <0x0 0x1000000>;
+			mmc-hs400-1_8v;
+			non-removable;
+			no-sdio;
+			no-sd;
+			bus-width = <8>;
+			voltage= "1.8v";
+			pull_up;
+			io_fixed_1v8;
+			fifo-mode;
+			u-boot,dm-pre-reloc;
+		};
+
+		sdhci0: sd@ffe7090000 {
+			compatible = "snps,dwcmshc-sdhci";
+			reg = <0xff 0xe7090000 0x0 0x10000>;
+			index = <0x1>;
+			clocks = <&dummy_ahb>;
+			clock-frequency = <198000000>;
+			max-frequency = <198000000>;
+			sd-uhs-sdr104;
+			pull_up;
+			clock-names = "core";
+			bus-width = <4>;
+			voltage= "3.3v";
+		};
+
+		qspi0: spi@ffea000000 {
+			compatible = "snps,dw-apb-ssi-quad";
+			reg = <0xff 0xea000000 0x0 0x1000>;
+			clocks = <&dummy_qspi0>;
+			num-cs = <1>;
+			cs-gpio = <&gpio2_porta 3 0>; // GPIO_ACTIVE_HIGH: 0
+			spi-max-frequency = <100000000>;
+			#address-cells = <1>;
+			#size-cells =<0>;
+			status = "disabled";
+			spi-flash@0 {
+				#address-cells = <1>;
+				#size-cells = <1>;
+				compatible = "spi-nand";
+				spi-tx-bus-width = <4>;
+				spi-rx-bus-width = <4>;
+				reg = <0>;
+			};
+		};
+
+		qspi1: spi@fff8000000 {
+			compatible = "snps,dw-apb-ssi-quad";
+			reg = <0xff 0xf8000000 0x0 0x1000>;
+			clocks = <&dummy_spi>;
+			num-cs = <1>;
+			cs-gpio = <&gpio0_porta 1 0>; // GPIO_ACTIVE_HIGH: 0
+			spi-max-frequency = <66000000>;
+			#address-cells = <1>;
+			#size-cells =<0>;
+			status = "disabled";
+			spi-flash@0 {
+				#address-cells = <1>;
+				#size-cells = <1>;
+				compatible = "spi-nand";
+				spi-tx-bus-width = <4>;
+				spi-rx-bus-width = <4>;
+				reg = <0>;
+			};
+		};
+
+		spi0: spi@ffe700c000 {
+			compatible = "snps,dw-apb-ssi";
+			reg = <0xff 0xe700c000 0x0 0x1000>;
+			clocks = <&dummy_spi>;
+			cs-gpio = <&gpio2_porta 15 0>;
+			spi-max-frequency = <100000000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+			flash@0 {
+				compatible = "jedec,spi-nor";
+				reg = <0>;
+				spi-max-frequency = <40000000>;
+			};
+		};
+
+		gpio2: gpio@ffe7f34000 {
+			compatible = "snps,dw-apb-gpio";
+			reg = <0xff 0xe7f34000 0x0 0x1000>;
+			clocks = <&dummy_apb>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			gpio2_porta: gpio-controller@0 {
+				compatible = "snps,dw-apb-gpio-port";
+				gpio-controller;
+				#gpio-cells = <2>;
+				snps,nr-gpios = <32>;
+				reg = <0>;
+			};
+		};
+
+		gpio0: gpio@ffec005000 {
+			compatible = "snps,dw-apb-gpio";
+			reg = <0xff 0xec005000 0x0 0x1000>;
+			clocks = <&dummy_apb>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			gpio0_porta: gpio-controller@0 {
+				compatible = "snps,dw-apb-gpio-port";
+				gpio-controller;
+				#gpio-cells = <2>;
+				snps,nr-gpios = <32>;
+				reg = <0>;
+			};
+		};
+
+		gpio1: gpio@ffec006000 {
+			compatible = "snps,dw-apb-gpio";
+			reg = <0xff 0xec006000 0x0 0x1000>;
+			clocks = <&dummy_apb>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			gpio1_porta: gpio-controller@0 {
+				compatible = "snps,dw-apb-gpio-port";
+				gpio-controller;
+				#gpio-cells = <2>;
+				snps,nr-gpios = <32>;
+				reg = <0>;
+			};
+		};
+
+		pwm: pwm@ffec01c000 {
+			compatible = "thead,pwm-light";
+			reg = <0xff 0xec01c000 0x0 0x4000>;
+			#pwm-cells = <2>;
+		};
+
+		dsi_regs: dsi-controller@ffef500000 {
+			compatible = "thead,light-dsi-regs", "syscon";
+			reg = <0xff 0xef500000 0x0 0x10000>;
+			status = "okay";
+		};
+
+		vosys_regs: vosys@ffef528000 {
+			compatible = "thead,light-vo-subsys", "syscon";
+			reg = <0xff 0xef528000 0x0 0x1000>;
+			status = "okay";
+		};
+
+		dpu: dc8200@ffef600000 {
+			compatible = "verisilicon,dc8200";
+			reg = <0xff 0xef600000 0x0 0x100>;
+		};
+
+		axiscr {
+			compatible = "thead,axiscr";
+			reg = <0xff 0xff004000 0x0 0x1000>;
+			lock-read = "okay";
+			lock-write = "okay";
+			#address-cells = <2>;
+			#size-cells = <2>;
+			u-boot,dm-pre-reloc;
+			axiscr0: axisrc@0 {
+				device_type = "axiscr";
+				region = <0x00 0x00000000 0x00 0x80000000>; // 4KB align
+				status = "disabled";
+				#address-cells = <2>;
+				#size-cells = <2>;
+				u-boot,dm-pre-reloc;
+			};
+			axiscr1: axisrc@1 {
+				device_type = "axiscr";
+				region = <0x00 0x80000000 0x00 0x80000000>; // 4KB align
+				status = "disabled";
+				#address-cells = <2>;
+				#size-cells = <2>;
+				u-boot,dm-pre-reloc;
+			};
+			axiscr2: axisrc@2 {
+				device_type = "axiscr";
+				region = <0x01 0x00000000 0x00 0x80000000>; // 4KB align
+				status = "disabled";
+				#address-cells = <2>;
+				#size-cells = <2>;
+				u-boot,dm-pre-reloc;
+			};
+		};
+
+		axiparity {
+			compatible = "thead,axiparity";
+			reg = <0xff 0xff00c000 0x0 0x1000>;
+			lock = "okay";
+			#address-cells = <2>;
+			#size-cells = <2>;
+			u-boot,dm-pre-reloc;
+			axiparity0: axiparity@0 {
+				device_type = "axiparity";
+				region = <0x00 0x00000000 0x01 0x0000000>; // 4KB align
+				status = "disabled";
+				#address-cells = <2>;
+				#size-cells = <2>;
+				u-boot,dm-pre-reloc;
+			};
+			axiparity1: axiparity@1 {
+				device_type = "axiparity";
+				region = <0x01 0x00000000 0x01 0x00000000>; // 4KB align
+				status = "disabled";
+				#address-cells = <2>;
+				#size-cells = <2>;
+				u-boot,dm-pre-reloc;
+			};
+		};
+
+		dsi_bridge: dsi-bridge {
+			compatible = "thead,light-dsi-bridge";
+			clocks = <&dummy_dpu_pixclk>;
+			clock-names = "pix-clk";
+			phys = <&dsi_dphy>;
+			phy-names = "dphy";
+		};
+
+		dsi_host: dsi-host {
+			compatible = "synopsys,dw-mipi-dsi";
+			regmap = <&dsi_regs>;
+			status = "okay";
+		};
+
+		dsi_dphy: dsi-dphy {
+			compatible = "synopsys,dw-dphy";
+			regmap = <&dsi_regs>;
+			vosys-regmap = <&vosys_regs>;
+			clocks = <&dummy_dpu_pixclk>, <&dummy_dphy_refclk>;
+			clock-names = "pix-clk", "ref-clk";
+			#phy-cells = <0>;
+			status = "okay";
+		};
+
+		lcd_backlight: pwm-backlight {
+			compatible = "pwm-backlight";
+			pwms = <&pwm 0 5000000>;
+			brightness-levels = <0 4 8 16 32 64 128 255>;
+			default-brightness-level = <7>;
+		};
+
+		ili9881c_panel {
+			compatible      = "ilitek,ili9881c";
+			backlight       = <&lcd_backlight>;
+			reset-gpios     = <&gpio1_porta 5 1>;   /* active low  */
+			lcd-en-gpios    = <&gpio1_porta 9 0>; /* active high */
+			lcd-bias-en-gpios = <&gpio1_porta 10 0>;/* active high */
+		};
+	};
+
+	chosen {
+		bootargs = "console=ttyS0,115200";
+		stdout-path = "/soc/serial@ffe7014000:115200";
+	};
+};

arch/riscv/dts/light-beagle.dts

@@ -0,0 +1,488 @@
+/dts-v1/;
+/ {
+	model = "T-HEAD c910 light";
+	compatible = "thead,c910_light";
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	memory@0 {
+		device_type = "memory";
+		reg = <0x0 0xc0000000 0x0 0x40000000>;
+	};
+
+	aliases {
+		spi0 = &spi0;
+		spi1 = &qspi0;
+		spi2 = &qspi1;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		timebase-frequency = <3000000>;
+		u-boot,dm-pre-reloc;
+		cpu@0 {
+			device_type = "cpu";
+			reg = <0>;
+			status = "okay";
+			compatible = "riscv";
+			riscv,isa = "rv64imafdcvsu";
+			mmu-type = "riscv,sv39";
+			u-boot,dm-pre-reloc;
+		};
+	};
+
+	soc {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		compatible = "simple-bus";
+		ranges;
+		u-boot,dm-pre-reloc;
+
+		intc: interrupt-controller@ffd8000000 {
+			compatible = "riscv,plic0";
+			reg = <0xff 0xd8000000 0x0 0x04000000>;
+			status = "disabled";
+		};
+
+		dummy_apb: apb-clock {
+			compatible = "fixed-clock";
+			clock-frequency = <62500000>;
+			clock-output-names = "dummy_apb";
+			#clock-cells = <0>;
+			u-boot,dm-pre-reloc;
+		};
+
+		dummy_ahb: ahb-clock {
+			compatible = "fixed-clock";
+			clock-frequency = <250000000>;
+			clock-output-names = "core";
+			#clock-cells = <0>;
+			u-boot,dm-pre-reloc;
+		};
+
+		dummy_spi: spi-clock {
+			compatible = "fixed-clock";
+			clock-frequency = <396000000>;
+			clock-output-names = "dummy_spi";
+			#clock-cells = <0>;
+			u-boot,dm-pre-reloc;
+		};
+
+		dummy_qspi0: qspi0-clock {
+			compatible = "fixed-clock";
+			clock-frequency = <792000000>;
+			clock-output-names = "dummy_qspi0";
+			#clock-cells = <0>;
+			u-boot,dm-pre-reloc;
+		};
+
+		dummy_uart_sclk: uart-sclk-clock {
+			compatible = "fixed-clock";
+			clock-frequency = <100000000>;
+			clock-output-names = "dummy_uart_sclk";
+			#clock-cells = <0>;
+			u-boot,dm-pre-reloc;
+		};
+
+		dummy_i2c_icclk: i2c-icclk-clock {
+			compatible = "fixed-clock";
+			clock-frequency = <50000000>;
+			clock-output-names = "dummy_i2c_icclk";
+			#clock-cells = <0>;
+			u-boot,dm-pre-reloc;
+		};
+
+		dummy_dpu_pixclk: dpu-pix-clock {
+			compatible = "fixed-clock";
+			clock-frequency = <74250000>;
+			clock-output-names = "dummy_dpu_pixclk";
+			#clock-cells = <0>;
+			u-boot,dm-pre-reloc;
+		};
+
+		dummy_dphy_refclk: dphy-ref-clock {
+			compatible = "fixed-clock";
+			clock-frequency = <24000000>;
+			clock-output-names = "dummy_dpu_refclk";
+			#clock-cells = <0>;
+			u-boot,dm-pre-reloc;
+		};
+
+		i2c0: i2c@ffe7f20000 {
+			compatible = "snps,designware-i2c";
+			reg = <0xff 0xe7f20000 0x0 0x4000>;
+			clocks = <&dummy_i2c_icclk>;
+			clock-frequency = <100000>;
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c1: i2c@ffe7f24000{
+			compatible = "snps,designware-i2c";
+			reg = <0xff 0xe7f24000 0x0 0x4000>;
+			clocks = <&dummy_i2c_icclk>;
+			clock-frequency = <100000>;
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c2: i2c@ffec00c000{
+			compatible = "snps,designware-i2c";
+			reg = <0xff 0xec00c000 0x0 0x4000>;
+			clocks = <&dummy_i2c_icclk>;
+			clock-frequency = <100000>;
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c3: i2c@ffec014000{
+			compatible = "snps,designware-i2c";
+			reg = <0xff 0xec014000 0x0 0x4000>;
+			clocks = <&dummy_i2c_icclk>;
+			clock-frequency = <100000>;
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c4: i2c@ffe7f28000{
+			compatible = "snps,designware-i2c";
+			reg = <0xff 0xe7f28000 0x0 0x4000>;
+			clocks = <&dummy_i2c_icclk>;
+			clock-frequency = <100000>;
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			pcal6408ahk_a: gpio@20 {
+				compatible = "nxp,pca9554";
+				reg = <0x20>;
+				gpio-controller;
+				#gpio-cells = <2>;
+			};
+		};
+
+		i2c5: i2c@fff7f2c000{
+			compatible = "snps,designware-i2c";
+			reg = <0xff 0xf7f2c000 0x0 0x4000>;
+			clocks = <&dummy_i2c_icclk>;
+			clock-frequency = <100000>;
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		serial@ffe7014000 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0xff 0xe7014000 0x0 0x400>;
+			clocks = <&dummy_uart_sclk>;
+			clock-frequency = <100000000>;
+			clock-names = "baudclk";
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			u-boot,dm-pre-reloc;
+		};
+
+		gmac0: ethernet@ffe7070000 {
+			compatible = "snps,dwmac";
+			reg = <0xff 0xe7070000 0x0 0x2000>;
+			clocks = <&dummy_apb>;
+			clock-names = "stmmaceth";
+			snps,pbl = <32>;
+			snps,fixed-burst;
+
+			phy-mode = "rgmii-id";
+			phy-handle = <&phy_88E1111_a>;
+			status = "okay";
+			mdio0 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "snps,dwmac-mdio";
+
+				phy_88E1111_a: ethernet-phy@1 {
+					reg = <0x1>;
+				};
+
+				phy_88E1111_b: ethernet-phy@2 {
+					reg = <0x2>;
+				};
+			};
+		};
+
+		gmac1: ethernet@ffe7060000 {
+			compatible = "snps,dwmac";
+			reg = <0xff 0xe7060000 0x0 0x2000>;
+			clocks = <&dummy_apb>;
+			clock-names = "stmmaceth";
+			snps,pbl = <32>;
+			snps,fixed-burst;
+			phy-mode = "rgmii-id";
+			phy-handle = <&phy_88E1111_b>;
+			status = "okay";
+		};
+
+		emmc: sdhci@ffe7080000 {
+			compatible = "snps,dwcmshc-sdhci";
+			reg = <0xff 0xe7080000 0x0 0x10000>;
+			index = <0x0>;
+			clocks = <&dummy_ahb>;
+			clock-frequency = <198000000>;
+			clock-names = "core";
+			max-frequency = <198000000>;
+			sdhci-caps-mask = <0x0 0x1000000>;
+			mmc-hs400-1_8v;
+			non-removable;
+			no-sdio;
+			no-sd;
+			bus-width = <8>;
+			voltage= "1.8v";
+			pull_up;
+			io_fixed_1v8;
+			fifo-mode;
+			u-boot,dm-pre-reloc;
+		};
+
+		sdhci0: sd@ffe7090000 {
+			compatible = "snps,dwcmshc-sdhci";
+			reg = <0xff 0xe7090000 0x0 0x10000>;
+			index = <0x1>;
+			clocks = <&dummy_ahb>;
+			clock-frequency = <198000000>;
+			max-frequency = <198000000>;
+			sd-uhs-sdr104;
+			pull_up;
+			clock-names = "core";
+			bus-width = <4>;
+			voltage= "3.3v";
+		};
+
+		qspi0: spi@ffea000000 {
+			compatible = "snps,dw-apb-ssi-quad";
+			reg = <0xff 0xea000000 0x0 0x1000>;
+			clocks = <&dummy_qspi0>;
+			num-cs = <1>;
+			cs-gpio = <&gpio2_porta 3 0>; // GPIO_ACTIVE_HIGH: 0
+			spi-max-frequency = <100000000>;
+			#address-cells = <1>;
+			#size-cells =<0>;
+			spi-flash@0 {
+				#address-cells = <1>;
+				#size-cells = <1>;
+				compatible = "spi-nand";
+				spi-tx-bus-width = <4>;
+				spi-rx-bus-width = <4>;
+				reg = <0>;
+			};
+		};
+
+		qspi1: spi@fff8000000 {
+			compatible = "snps,dw-apb-ssi-quad";
+			reg = <0xff 0xf8000000 0x0 0x1000>;
+			clocks = <&dummy_spi>;
+			num-cs = <1>;
+			cs-gpio = <&gpio0_porta 1 0>; // GPIO_ACTIVE_HIGH: 0
+			spi-max-frequency = <66000000>;
+			#address-cells = <1>;
+			#size-cells =<0>;
+			spi-flash@0 {
+				#address-cells = <1>;
+				#size-cells = <1>;
+				compatible = "spi-nand";
+				spi-tx-bus-width = <4>;
+				spi-rx-bus-width = <4>;
+				reg = <0>;
+			};
+		};
+
+		spi0: spi@ffe700c000 {
+			compatible = "snps,dw-apb-ssi";
+			reg = <0xff 0xe700c000 0x0 0x1000>;
+			clocks = <&dummy_spi>;
+			cs-gpio = <&gpio2_porta 15 0>;
+			spi-max-frequency = <100000000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			flash@0 {
+				compatible = "jedec,spi-nor";
+				reg = <0>;
+				spi-max-frequency = <40000000>;
+			};
+		};
+
+		gpio2: gpio@ffe7f34000 {
+			compatible = "snps,dw-apb-gpio";
+			reg = <0xff 0xe7f34000 0x0 0x1000>;
+			clocks = <&dummy_apb>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			gpio2_porta: gpio-controller@0 {
+				compatible = "snps,dw-apb-gpio-port";
+				gpio-controller;
+				#gpio-cells = <2>;
+				snps,nr-gpios = <32>;
+				reg = <0>;
+			};
+		};
+
+		gpio0: gpio@ffec005000 {
+			compatible = "snps,dw-apb-gpio";
+			reg = <0xff 0xec005000 0x0 0x1000>;
+			clocks = <&dummy_apb>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			gpio0_porta: gpio-controller@0 {
+				compatible = "snps,dw-apb-gpio-port";
+				gpio-controller;
+				#gpio-cells = <2>;
+				snps,nr-gpios = <32>;
+				reg = <0>;
+			};
+		};
+
+		gpio1: gpio@ffec006000 {
+			compatible = "snps,dw-apb-gpio";
+			reg = <0xff 0xec006000 0x0 0x1000>;
+			clocks = <&dummy_apb>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			gpio1_porta: gpio-controller@0 {
+				compatible = "snps,dw-apb-gpio-port";
+				gpio-controller;
+				#gpio-cells = <2>;
+				snps,nr-gpios = <32>;
+				reg = <0>;
+			};
+		};
+
+		pwm: pwm@ffec01c000 {
+			compatible = "thead,pwm-light";
+			reg = <0xff 0xec01c000 0x0 0x4000>;
+			#pwm-cells = <2>;
+		};
+
+		dsi_regs: dsi-controller@ffef500000 {
+			compatible = "thead,light-dsi-regs", "syscon";
+			reg = <0xff 0xef500000 0x0 0x10000>;
+			status = "okay";
+		};
+
+		vosys_regs: vosys@ffef528000 {
+			compatible = "thead,light-vo-subsys", "syscon";
+			reg = <0xff 0xef528000 0x0 0x1000>;
+			status = "okay";
+		};
+
+		dpu: dc8200@ffef600000 {
+			compatible = "verisilicon,dc8200";
+			reg = <0xff 0xef600000 0x0 0x100>;
+		};
+
+		axiscr {
+			compatible = "thead,axiscr";
+			reg = <0xff 0xff004000 0x0 0x1000>;
+			lock-read = "okay";
+			lock-write = "okay";
+			#address-cells = <2>;
+			#size-cells = <2>;
+			u-boot,dm-pre-reloc;
+			axiscr0: axisrc@0 {
+				device_type = "axiscr";
+				region = <0x00 0x00000000 0x00 0x80000000>; // 4KB align
+				status = "disabled";
+				#address-cells = <2>;
+				#size-cells = <2>;
+				u-boot,dm-pre-reloc;
+			};
+			axiscr1: axisrc@1 {
+				device_type = "axiscr";
+				region = <0x00 0x80000000 0x00 0x80000000>; // 4KB align
+				status = "disabled";
+				#address-cells = <2>;
+				#size-cells = <2>;
+				u-boot,dm-pre-reloc;
+			};
+			axiscr2: axisrc@2 {
+				device_type = "axiscr";
+				region = <0x01 0x00000000 0x00 0x80000000>; // 4KB align
+				status = "disabled";
+				#address-cells = <2>;
+				#size-cells = <2>;
+				u-boot,dm-pre-reloc;
+			};
+		};
+
+		axiparity {
+			compatible = "thead,axiparity";
+			reg = <0xff 0xff00c000 0x0 0x1000>;
+			lock = "okay";
+			#address-cells = <2>;
+			#size-cells = <2>;
+			u-boot,dm-pre-reloc;
+			axiparity0: axiparity@0 {
+				device_type = "axiparity";
+				region = <0x00 0x00000000 0x01 0x0000000>; // 4KB align
+				status = "disabled";
+				#address-cells = <2>;
+				#size-cells = <2>;
+				u-boot,dm-pre-reloc;
+			};
+			axiparity1: axiparity@1 {
+				device_type = "axiparity";
+				region = <0x01 0x00000000 0x01 0x00000000>; // 4KB align
+				status = "disabled";
+				#address-cells = <2>;
+				#size-cells = <2>;
+				u-boot,dm-pre-reloc;
+			};
+		};
+
+		dsi_bridge: dsi-bridge {
+			compatible = "thead,light-dsi-bridge";
+			clocks = <&dummy_dpu_pixclk>;
+			clock-names = "pix-clk";
+			phys = <&dsi_dphy>;
+			phy-names = "dphy";
+		};
+
+		dsi_host: dsi-host {
+			compatible = "synopsys,dw-mipi-dsi";
+			regmap = <&dsi_regs>;
+			status = "okay";
+		};
+
+		dsi_dphy: dsi-dphy {
+			compatible = "synopsys,dw-dphy";
+			regmap = <&dsi_regs>;
+			vosys-regmap = <&vosys_regs>;
+			clocks = <&dummy_dpu_pixclk>, <&dummy_dphy_refclk>;
+			clock-names = "pix-clk", "ref-clk";
+			#phy-cells = <0>;
+			status = "okay";
+		};
+
+		lcd_backlight: pwm-backlight {
+			compatible = "pwm-backlight";
+			pwms = <&pwm 0 5000000>;
+			brightness-levels = <0 4 8 16 32 64 128 255>;
+			default-brightness-level = <7>;
+		};
+
+		ili9881c_panel {
+			compatible      = "ilitek,ili9881c";
+			backlight       = <&lcd_backlight>;
+			reset-gpios     = <&gpio1_porta 5 1>;   /* active low  */
+			lcd-en-gpios    = <&pcal6408ahk_a 2 0>; /* active high */
+			lcd-bias-en-gpios = <&pcal6408ahk_a 4 0>;/* active high */
+		};
+	};
+
+	chosen {
+		bootargs = "console=ttyS0,115200";
+		stdout-path = "/soc/serial@ffe7014000:115200";
+	};
+};

arch/riscv/dts/light-lpi4a.dts

@@ -0,0 +1,488 @@
+/dts-v1/;
+/ {
+	model = "T-HEAD c910 light";
+	compatible = "thead,c910_light";
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	memory@0 {
+		device_type = "memory";
+		reg = <0x0 0xc0000000 0x0 0x40000000>;
+	};
+
+	aliases {
+		spi0 = &spi0;
+		spi1 = &qspi0;
+		spi2 = &qspi1;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		timebase-frequency = <3000000>;
+		u-boot,dm-pre-reloc;
+		cpu@0 {
+			device_type = "cpu";
+			reg = <0>;
+			status = "okay";
+			compatible = "riscv";
+			riscv,isa = "rv64imafdcvsu";
+			mmu-type = "riscv,sv39";
+			u-boot,dm-pre-reloc;
+		};
+	};
+
+	soc {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		compatible = "simple-bus";
+		ranges;
+		u-boot,dm-pre-reloc;
+
+		intc: interrupt-controller@ffd8000000 {
+			compatible = "riscv,plic0";
+			reg = <0xff 0xd8000000 0x0 0x04000000>;
+			status = "disabled";
+		};
+
+		dummy_apb: apb-clock {
+			compatible = "fixed-clock";
+			clock-frequency = <62500000>;
+			clock-output-names = "dummy_apb";
+			#clock-cells = <0>;
+			u-boot,dm-pre-reloc;
+		};
+
+		dummy_ahb: ahb-clock {
+			compatible = "fixed-clock";
+			clock-frequency = <250000000>;
+			clock-output-names = "core";
+			#clock-cells = <0>;
+			u-boot,dm-pre-reloc;
+		};
+
+		dummy_spi: spi-clock {
+			compatible = "fixed-clock";
+			clock-frequency = <396000000>;
+			clock-output-names = "dummy_spi";
+			#clock-cells = <0>;
+			u-boot,dm-pre-reloc;
+		};
+
+		dummy_qspi0: qspi0-clock {
+			compatible = "fixed-clock";
+			clock-frequency = <792000000>;
+			clock-output-names = "dummy_qspi0";
+			#clock-cells = <0>;
+			u-boot,dm-pre-reloc;
+		};
+
+		dummy_uart_sclk: uart-sclk-clock {
+			compatible = "fixed-clock";
+			clock-frequency = <100000000>;
+			clock-output-names = "dummy_uart_sclk";
+			#clock-cells = <0>;
+			u-boot,dm-pre-reloc;
+		};
+
+		dummy_i2c_icclk: i2c-icclk-clock {
+			compatible = "fixed-clock";
+			clock-frequency = <50000000>;
+			clock-output-names = "dummy_i2c_icclk";
+			#clock-cells = <0>;
+			u-boot,dm-pre-reloc;
+		};
+
+		dummy_dpu_pixclk: dpu-pix-clock {
+			compatible = "fixed-clock";
+			clock-frequency = <74250000>;
+			clock-output-names = "dummy_dpu_pixclk";
+			#clock-cells = <0>;
+			u-boot,dm-pre-reloc;
+		};
+
+		dummy_dphy_refclk: dphy-ref-clock {
+			compatible = "fixed-clock";
+			clock-frequency = <24000000>;
+			clock-output-names = "dummy_dpu_refclk";
+			#clock-cells = <0>;
+			u-boot,dm-pre-reloc;
+		};
+
+		i2c0: i2c@ffe7f20000 {
+			compatible = "snps,designware-i2c";
+			reg = <0xff 0xe7f20000 0x0 0x4000>;
+			clocks = <&dummy_i2c_icclk>;
+			clock-frequency = <100000>;
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c1: i2c@ffe7f24000{
+			compatible = "snps,designware-i2c";
+			reg = <0xff 0xe7f24000 0x0 0x4000>;
+			clocks = <&dummy_i2c_icclk>;
+			clock-frequency = <100000>;
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c2: i2c@ffec00c000{
+			compatible = "snps,designware-i2c";
+			reg = <0xff 0xec00c000 0x0 0x4000>;
+			clocks = <&dummy_i2c_icclk>;
+			clock-frequency = <100000>;
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c3: i2c@ffec014000{
+			compatible = "snps,designware-i2c";
+			reg = <0xff 0xec014000 0x0 0x4000>;
+			clocks = <&dummy_i2c_icclk>;
+			clock-frequency = <100000>;
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c4: i2c@ffe7f28000{
+			compatible = "snps,designware-i2c";
+			reg = <0xff 0xe7f28000 0x0 0x4000>;
+			clocks = <&dummy_i2c_icclk>;
+			clock-frequency = <100000>;
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			pcal6408ahk_a: gpio@20 {
+				compatible = "nxp,pca9554";
+				reg = <0x20>;
+				gpio-controller;
+				#gpio-cells = <2>;
+			};
+		};
+
+		i2c5: i2c@fff7f2c000{
+			compatible = "snps,designware-i2c";
+			reg = <0xff 0xf7f2c000 0x0 0x4000>;
+			clocks = <&dummy_i2c_icclk>;
+			clock-frequency = <100000>;
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		serial@ffe7014000 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0xff 0xe7014000 0x0 0x400>;
+			clocks = <&dummy_uart_sclk>;
+			clock-frequency = <100000000>;
+			clock-names = "baudclk";
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			u-boot,dm-pre-reloc;
+		};
+
+		gmac0: ethernet@ffe7070000 {
+			compatible = "snps,dwmac";
+			reg = <0xff 0xe7070000 0x0 0x2000>;
+			clocks = <&dummy_apb>;
+			clock-names = "stmmaceth";
+			snps,pbl = <32>;
+			snps,fixed-burst;
+
+			phy-mode = "rgmii-id";
+			phy-handle = <&phy_88E1111_a>;
+			status = "okay";
+			mdio0 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "snps,dwmac-mdio";
+
+				phy_88E1111_a: ethernet-phy@1 {
+					reg = <0x1>;
+				};
+
+				phy_88E1111_b: ethernet-phy@2 {
+					reg = <0x2>;
+				};
+			};
+		};
+
+		gmac1: ethernet@ffe7060000 {
+			compatible = "snps,dwmac";
+			reg = <0xff 0xe7060000 0x0 0x2000>;
+			clocks = <&dummy_apb>;
+			clock-names = "stmmaceth";
+			snps,pbl = <32>;
+			snps,fixed-burst;
+			phy-mode = "rgmii-id";
+			phy-handle = <&phy_88E1111_b>;
+			status = "okay";
+		};
+
+		emmc: sdhci@ffe7080000 {
+			compatible = "snps,dwcmshc-sdhci";
+			reg = <0xff 0xe7080000 0x0 0x10000>;
+			index = <0x0>;
+			clocks = <&dummy_ahb>;
+			clock-frequency = <198000000>;
+			clock-names = "core";
+			max-frequency = <198000000>;
+			sdhci-caps-mask = <0x0 0x1000000>;
+			mmc-hs400-1_8v;
+			non-removable;
+			no-sdio;
+			no-sd;
+			bus-width = <8>;
+			voltage= "1.8v";
+			pull_up;
+			io_fixed_1v8;
+			fifo-mode;
+			u-boot,dm-pre-reloc;
+		};
+
+		sdhci0: sd@ffe7090000 {
+			compatible = "snps,dwcmshc-sdhci";
+			reg = <0xff 0xe7090000 0x0 0x10000>;
+			index = <0x1>;
+			clocks = <&dummy_ahb>;
+			clock-frequency = <198000000>;
+			max-frequency = <198000000>;
+			sd-uhs-sdr104;
+			pull_up;
+			clock-names = "core";
+			bus-width = <4>;
+			voltage= "3.3v";
+		};
+
+		qspi0: spi@ffea000000 {
+			compatible = "snps,dw-apb-ssi-quad";
+			reg = <0xff 0xea000000 0x0 0x1000>;
+			clocks = <&dummy_qspi0>;
+			num-cs = <1>;
+			cs-gpio = <&gpio2_porta 3 0>; // GPIO_ACTIVE_HIGH: 0
+			spi-max-frequency = <100000000>;
+			#address-cells = <1>;
+			#size-cells =<0>;
+			spi-flash@0 {
+				#address-cells = <1>;
+				#size-cells = <1>;
+				compatible = "spi-nand";
+				spi-tx-bus-width = <4>;
+				spi-rx-bus-width = <4>;
+				reg = <0>;
+			};
+		};
+
+		qspi1: spi@fff8000000 {
+			compatible = "snps,dw-apb-ssi-quad";
+			reg = <0xff 0xf8000000 0x0 0x1000>;
+			clocks = <&dummy_spi>;
+			num-cs = <1>;
+			cs-gpio = <&gpio0_porta 1 0>; // GPIO_ACTIVE_HIGH: 0
+			spi-max-frequency = <66000000>;
+			#address-cells = <1>;
+			#size-cells =<0>;
+			spi-flash@0 {
+				#address-cells = <1>;
+				#size-cells = <1>;
+				compatible = "spi-nand";
+				spi-tx-bus-width = <4>;
+				spi-rx-bus-width = <4>;
+				reg = <0>;
+			};
+		};
+
+		spi0: spi@ffe700c000 {
+			compatible = "snps,dw-apb-ssi";
+			reg = <0xff 0xe700c000 0x0 0x1000>;
+			clocks = <&dummy_spi>;
+			cs-gpio = <&gpio2_porta 15 0>;
+			spi-max-frequency = <100000000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			flash@0 {
+				compatible = "jedec,spi-nor";
+				reg = <0>;
+				spi-max-frequency = <40000000>;
+			};
+		};
+
+		gpio2: gpio@ffe7f34000 {
+			compatible = "snps,dw-apb-gpio";
+			reg = <0xff 0xe7f34000 0x0 0x1000>;
+			clocks = <&dummy_apb>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			gpio2_porta: gpio-controller@0 {
+				compatible = "snps,dw-apb-gpio-port";
+				gpio-controller;
+				#gpio-cells = <2>;
+				snps,nr-gpios = <32>;
+				reg = <0>;
+			};
+		};
+
+		gpio0: gpio@ffec005000 {
+			compatible = "snps,dw-apb-gpio";
+			reg = <0xff 0xec005000 0x0 0x1000>;
+			clocks = <&dummy_apb>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			gpio0_porta: gpio-controller@0 {
+				compatible = "snps,dw-apb-gpio-port";
+				gpio-controller;
+				#gpio-cells = <2>;
+				snps,nr-gpios = <32>;
+				reg = <0>;
+			};
+		};
+
+		gpio1: gpio@ffec006000 {
+			compatible = "snps,dw-apb-gpio";
+			reg = <0xff 0xec006000 0x0 0x1000>;
+			clocks = <&dummy_apb>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			gpio1_porta: gpio-controller@0 {
+				compatible = "snps,dw-apb-gpio-port";
+				gpio-controller;
+				#gpio-cells = <2>;
+				snps,nr-gpios = <32>;
+				reg = <0>;
+			};
+		};
+
+		pwm: pwm@ffec01c000 {
+			compatible = "thead,pwm-light";
+			reg = <0xff 0xec01c000 0x0 0x4000>;
+			#pwm-cells = <2>;
+		};
+
+		dsi_regs: dsi-controller@ffef500000 {
+			compatible = "thead,light-dsi-regs", "syscon";
+			reg = <0xff 0xef500000 0x0 0x10000>;
+			status = "okay";
+		};
+
+		vosys_regs: vosys@ffef528000 {
+			compatible = "thead,light-vo-subsys", "syscon";
+			reg = <0xff 0xef528000 0x0 0x1000>;
+			status = "okay";
+		};
+
+		dpu: dc8200@ffef600000 {
+			compatible = "verisilicon,dc8200";
+			reg = <0xff 0xef600000 0x0 0x100>;
+		};
+
+		axiscr {
+			compatible = "thead,axiscr";
+			reg = <0xff 0xff004000 0x0 0x1000>;
+			lock-read = "okay";
+			lock-write = "okay";
+			#address-cells = <2>;
+			#size-cells = <2>;
+			u-boot,dm-pre-reloc;
+			axiscr0: axisrc@0 {
+				device_type = "axiscr";
+				region = <0x00 0x00000000 0x00 0x80000000>; // 4KB align
+				status = "disabled";
+				#address-cells = <2>;
+				#size-cells = <2>;
+				u-boot,dm-pre-reloc;
+			};
+			axiscr1: axisrc@1 {
+				device_type = "axiscr";
+				region = <0x00 0x80000000 0x00 0x80000000>; // 4KB align
+				status = "disabled";
+				#address-cells = <2>;
+				#size-cells = <2>;
+				u-boot,dm-pre-reloc;
+			};
+			axiscr2: axisrc@2 {
+				device_type = "axiscr";
+				region = <0x01 0x00000000 0x00 0x80000000>; // 4KB align
+				status = "disabled";
+				#address-cells = <2>;
+				#size-cells = <2>;
+				u-boot,dm-pre-reloc;
+			};
+		};
+
+		axiparity {
+			compatible = "thead,axiparity";
+			reg = <0xff 0xff00c000 0x0 0x1000>;
+			lock = "okay";
+			#address-cells = <2>;
+			#size-cells = <2>;
+			u-boot,dm-pre-reloc;
+			axiparity0: axiparity@0 {
+				device_type = "axiparity";
+				region = <0x00 0x00000000 0x01 0x0000000>; // 4KB align
+				status = "disabled";
+				#address-cells = <2>;
+				#size-cells = <2>;
+				u-boot,dm-pre-reloc;
+			};
+			axiparity1: axiparity@1 {
+				device_type = "axiparity";
+				region = <0x01 0x00000000 0x01 0x00000000>; // 4KB align
+				status = "disabled";
+				#address-cells = <2>;
+				#size-cells = <2>;
+				u-boot,dm-pre-reloc;
+			};
+		};
+
+		dsi_bridge: dsi-bridge {
+			compatible = "thead,light-dsi-bridge";
+			clocks = <&dummy_dpu_pixclk>;
+			clock-names = "pix-clk";
+			phys = <&dsi_dphy>;
+			phy-names = "dphy";
+		};
+
+		dsi_host: dsi-host {
+			compatible = "synopsys,dw-mipi-dsi";
+			regmap = <&dsi_regs>;
+			status = "okay";
+		};
+
+		dsi_dphy: dsi-dphy {
+			compatible = "synopsys,dw-dphy";
+			regmap = <&dsi_regs>;
+			vosys-regmap = <&vosys_regs>;
+			clocks = <&dummy_dpu_pixclk>, <&dummy_dphy_refclk>;
+			clock-names = "pix-clk", "ref-clk";
+			#phy-cells = <0>;
+			status = "okay";
+		};
+
+		lcd_backlight: pwm-backlight {
+			compatible = "pwm-backlight";
+			pwms = <&pwm 0 5000000>;
+			brightness-levels = <0 4 8 16 32 64 128 255>;
+			default-brightness-level = <7>;
+		};
+
+		ili9881c_panel {
+			compatible      = "ilitek,ili9881c";
+			backlight       = <&lcd_backlight>;
+			reset-gpios     = <&gpio1_porta 5 1>;   /* active low  */
+			lcd-en-gpios    = <&pcal6408ahk_a 2 0>; /* active high */
+			lcd-bias-en-gpios = <&pcal6408ahk_a 4 0>;/* active high */
+		};
+	};
+
+	chosen {
+		bootargs = "console=ttyS0,115200";
+		stdout-path = "/soc/serial@ffe7014000:115200";
+	};
+};

arch/riscv/include/asm/arch-thead/light-plic.h

@@ -0,0 +1,51 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2022, Liuw  <lw312886@alibaba-inc.com>
+ *
+ * U-Boot syscon driver for Thead's Platform Level Interrupt Controller (PLIC)
+ */
+
+#ifndef _LIGHT_PLIC_H
+#define _LIGHT_PLIC_H
+
+/*
+ * M-mode
+ *	hart id: 0, 2, 4, 6
+ * S-mode
+ *	hart id: 1, 3, 5, 7
+ */
+
+/* interrupt priority register */
+#define PLIC_PRIO_REG(base, id)			((void __iomem *)(base) + 0x00 + (id) * 4)
+
+/* enable register */
+#define PLIC_ENABLE_REG(base, hart)		((void __iomem *)(base) + 0x2000 + (hart) * 0x80)
+
+/* pending registr */
+#define PLIC_PENDING_REG(base, hart)		((void __iomem *)(base) + 0x1000 + ((hart) / 4) * 4)
+
+/* threshold register */
+#define PLIC_THRESHOLD_REG(base, hart)		((void __iomem *)(base) + 0x200000 + (hart) * 0x1000 + 0x00)
+
+/* claim/complete register */
+#define PLIC_CLAIM_REG(base, hart)		((void __iomem *)(base) + 0x200000 + (hart) * 0x1000 + 0x04)
+
+#define MAX_IRQ_NUM	256
+typedef void (*irq_handler_t)(void);
+
+
+int irq_handler_register(int irq, irq_handler_t handler);
+
+void arch_local_irq_enable(void);
+
+void arch_local_irq_disable(void);
+
+void irq_enable(int hwirq);
+
+void irq_disable(int hwirq);
+
+void irq_priority_set(int prio);
+
+int plic_init(void);
+
+#endif

arch/riscv/include/asm/csr.h

@@ -12,6 +12,7 @@
 #include <linux/const.h>
 
 /* Status register flags */
+#define SR_MIE          _AC(0x00000008, UL) /* Machine Interrupt Enable */
 #define SR_SIE		_AC(0x00000002, UL) /* Supervisor Interrupt Enable */
 #define SR_SPIE		_AC(0x00000020, UL) /* Previous Supervisor IE */
 #define SR_SPP		_AC(0x00000100, UL) /* Previously Supervisor */
@@ -71,6 +72,7 @@
 
 /* SIE (Interrupt Enable) and SIP (Interrupt Pending) flags */
 #define MIE_MSIE		(_AC(0x1, UL) << IRQ_M_SOFT)
+#define MIE_MEIE		(_AC(0x1, UL) << IRQ_M_EXT)
 #define SIE_SSIE		(_AC(0x1, UL) << IRQ_S_SOFT)
 #define SIE_STIE		(_AC(0x1, UL) << IRQ_S_TIMER)
 #define SIE_SEIE		(_AC(0x1, UL) << IRQ_S_EXT)

arch/riscv/include/asm/dma-mapping.h

@@ -15,7 +15,7 @@
 
 static inline void *dma_alloc_coherent(size_t len, unsigned long *handle)
 {
-	*handle = (unsigned long)memalign(ARCH_DMA_MINALIGN, len);
+	*handle = (unsigned long)memalign(ARCH_DMA_MINALIGN, ROUND(len, ARCH_DMA_MINALIGN));
 	return (void *)*handle;
 }
 

arch/riscv/include/asm/global_data.h

@@ -18,7 +18,7 @@ struct arch_global_data {
 #ifdef CONFIG_SIFIVE_CLINT
 	void __iomem *clint;	/* clint base address */
 #endif
-#ifdef CONFIG_ANDES_PLIC
+#if (defined CONFIG_ANDES_PLIC) || (defined CONFIG_THEAD_PLIC)
 	void __iomem *plic;	/* plic base address */
 #endif
 #ifdef CONFIG_ANDES_PLMT

arch/riscv/lib/Makefile

@@ -15,6 +15,7 @@ obj-$(CONFIG_SIFIVE_CLINT) += sifive_clint.o
 obj-$(CONFIG_ANDES_PLIC) += andes_plic.o
 obj-$(CONFIG_ANDES_PLMT) += andes_plmt.o
 obj-$(CONFIG_THEAD_IPI) += thead_ipi.o
+obj-$(CONFIG_THEAD_PLIC) += thead_plic.o
 else
 obj-$(CONFIG_SBI_IPI) += sbi_ipi.o
 endif

arch/riscv/lib/interrupts.c

@@ -13,6 +13,11 @@
 #include <asm/system.h>
 #include <asm/encoding.h>
 
+__attribute__((weak)) int plic_init(void)
+{
+	return 0;
+}
+
 static void _exit_trap(ulong code, ulong epc, struct pt_regs *regs)
 {
 	static const char * const exception_code[] = {
@@ -47,6 +52,8 @@ static void _exit_trap(ulong code, ulong epc, struct pt_regs *regs)
 
 int interrupt_init(void)
 {
+	debug("[%s,%d]Initialize the plic\n", __func__, __LINE__);
+	plic_init();
 	return 0;
 }
 
@@ -72,10 +79,12 @@ ulong handle_trap(ulong cause, ulong epc, struct pt_regs *regs)
 	is_irq = (cause & MCAUSE_INT);
 	irq = (cause & ~MCAUSE_INT);
 
+	debug("[%s,%d]\n", __func__, __LINE__);
 	if (is_irq) {
 		switch (irq) {
 		case IRQ_M_EXT:
 		case IRQ_S_EXT:
+			debug("[%s,%d]\n", __func__, __LINE__);
 			external_interrupt(0);	/* handle external interrupt */
 			break;
 		case IRQ_M_TIMER:
@@ -90,6 +99,7 @@ ulong handle_trap(ulong cause, ulong epc, struct pt_regs *regs)
 		_exit_trap(cause, epc, regs);
 	}
 
+	debug("[%s,%d]\n", __func__, __LINE__);
 	return epc;
 }
 

arch/riscv/lib/reset.c

@@ -5,9 +5,21 @@
 
 #include <common.h>
 #include <command.h>
+#include <asm/io.h>
+
+#define AONSYS_RSTGEN_BASE			((void __iomem *)0xFFFFF44000UL)
+#define REG_RST_REQ_EN_0			(AONSYS_RSTGEN_BASE + 0x140)
+#define WDT0_SYS_RST_REQ			(1 << 8)
 
 static __attribute__((naked))void sys_wdt_reset(void)
 {
+    uint32_t data;
+
+	/* wdt0 reset enable */
+    data = readl(REG_RST_REQ_EN_0);
+	data |= WDT0_SYS_RST_REQ;
+	writel(data, REG_RST_REQ_EN_0);
+
     asm volatile (
     "1: \n\r"
         "li      a0, 0xFFEFC30000 \n\r"
@@ -21,7 +33,7 @@ static __attribute__((naked))void sys_wdt_reset(void)
 
 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
-	printf("resetting ...\n");
+    printf("resetting ...\n");
 
 	sys_wdt_reset();
 	hang();

arch/riscv/lib/thead_plic.c

@@ -0,0 +1,155 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2022, Liuw  <lw312886@alibaba-inc.com>
+ *
+ * U-Boot syscon driver for Thead's Platform Level Interrupt Controller (PLIC)
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <dm/device-internal.h>
+#include <dm/lists.h>
+#include <dm/uclass-internal.h>
+#include <regmap.h>
+#include <syscon.h>
+#include <asm/csr.h>
+#include <asm/io.h>
+#include <asm/syscon.h>
+#include <asm/global_data.h>
+#include <cpu.h>
+#include <linux/err.h>
+#include <asm/arch-thead/light-plic.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define PLIC_BASE_GET(void)						\
+	do {								\
+		long *ret;						\
+									\
+		if (!gd->arch.plic) {					\
+			ret = syscon_get_first_range(RISCV_SYSCON_PLIC); \
+			gd->arch.plic = ret;				\
+		}							\
+	} while (0)
+
+irq_handler_t irq_table[MAX_IRQ_NUM];
+
+void __iomem *plic_base = NULL;
+
+void external_interrupt(struct pt_regs *regs)
+{
+	void __iomem *claim;
+	irq_handler_t handler;
+	u32 irq_num;
+
+	debug("[%s,%d]\n", __func__, __LINE__);
+	if (!plic_base)
+		return;
+
+	debug("[%s,%d]\n", __func__, __LINE__);
+	claim = PLIC_CLAIM_REG(plic_base, 0);
+
+	while ((irq_num = readl(claim))) {
+		if (irq_num >= MAX_IRQ_NUM)
+			debug("Cannot find irq:%d\n", irq_num);
+		else {
+			handler = irq_table[irq_num];
+			if (handler)
+				handler();
+			writel(irq_num, claim);
+		}
+	}
+	debug("[%s,%d]\n", __func__, __LINE__);
+}
+
+static void plic_toggle(void __iomem *enable_base, int hwirq, int enable)
+{
+	u32 __iomem *reg = enable_base + (hwirq / 32) * sizeof(u32);
+	u32 hwirq_mask = 1 << (hwirq % 32);
+
+	if (enable)
+		writel(readl(reg) | hwirq_mask, reg);
+	else
+		writel(readl(reg) & ~hwirq_mask, reg);
+
+	debug("[%s,%d][0x%lx] = 0x%x\n", __func__, __LINE__,
+			(unsigned long)reg, readl(reg));
+}
+
+static void plic_set_threshold(void __iomem *thre_base, u32 threshold)
+{
+	writel(threshold, thre_base);
+	debug("[%s,%d][0x%lx] = 0x%x\n", __func__, __LINE__,
+			(unsigned long)thre_base, readl(thre_base));
+}
+
+static void plic_set_irq_priority(void __iomem *prio_base, int prio)
+{
+	writel(prio, prio_base);
+}
+
+int irq_handler_register(int irq, irq_handler_t handler)
+{
+	if (irq < 0 || irq >= MAX_IRQ_NUM) {
+		debug("invalid irq number to register\n");
+		return -EINVAL;
+	}
+
+	irq_table[irq] = handler;
+
+	return 0;
+}
+
+void arch_local_irq_enable(void)
+{
+	csr_set(CSR_MIE, MIE_MEIE);
+	csr_set(CSR_MSTATUS, SR_MIE);
+}
+
+void arch_local_irq_disable(void)
+{
+	csr_clear(CSR_MIE, MIE_MEIE);
+	csr_clear(CSR_MSTATUS, SR_MIE);
+}
+
+void irq_priority_set(int irq_id)
+{
+	plic_set_irq_priority(PLIC_PRIO_REG(gd->arch.plic, irq_id), 4);
+}
+
+void irq_enable(int hwirq)
+{
+	plic_toggle(PLIC_ENABLE_REG(gd->arch.plic, 0), hwirq, 1);
+}
+
+void irq_disable(int hwirq)
+{
+	plic_toggle(PLIC_ENABLE_REG(gd->arch.plic, 0), hwirq, 0);
+}
+
+int plic_init()
+{
+	PLIC_BASE_GET();
+	if (IS_ERR(gd->arch.plic))
+		return PTR_ERR(gd->arch.plic);
+
+	plic_base = gd->arch.plic;
+	debug("THEAD PLIC BASE: 0x%lx\n", (unsigned long)gd->arch.plic);
+
+	plic_set_threshold(PLIC_THRESHOLD_REG(gd->arch.plic, 0), 0);
+
+	arch_local_irq_enable(); //enale the global interrupt
+
+	return 0;
+}
+
+static const struct udevice_id thead_plic_ids[] = {
+	{ .compatible = "riscv,plic0", .data = RISCV_SYSCON_PLIC},
+	{ }
+};
+
+U_BOOT_DRIVER(thead_plic) = {
+	.name		= "thead_light_plic",
+	.id		= UCLASS_SYSCON,
+	.of_match	= thead_plic_ids,
+};

board/thead/light-c910/Kconfig

@@ -12,15 +12,15 @@ config PMIC_VOL_INIT
 
 config DDR_REGU_0V6
     int "uint in uv"
-    default 640000
+    default 600000
 
 config DDR_REGU_0V8
     int "uint in uv"
-    default 820000
+    default 800000
 
 config DDR_REGU_1V1
     int "uint in uv"
-    default 1200000
+    default 1100000
 
 config SYS_CPU
     default "c9xx"
@@ -45,8 +45,8 @@ config LIGHT_SEC_BOOT_WITH_VERIFY_VAL_A
 config LIGHT_SEC_BOOT_WITH_VERIFY_VAL_B
 	bool "light board-b security boot with verification"
 
-config LIGHT_SEC_BOOT_WITH_VERIFY_ANT_EVT
-	bool "light ant evt security boot with verification"
+config LIGHT_SEC_BOOT_WITH_VERIFY_ANT_REF
+	bool "light ant ref security boot with verification"
 
 config TARGET_LIGHT_FPGA_FM_C910
     bool "light fullmask FPGA board"
@@ -60,16 +60,36 @@ config TARGET_LIGHT_FM_C910_VAL_A
     bool "light fullmask VAL board-a for system validation"
     default n
 
+config TARGET_LIGHT_FM_C910_A_REF
+    bool "light fullmask reference A board"
+    default n
+
 config TARGET_LIGHT_FM_C910_VAL_B
     bool "light fullmask VAL board-b for system validation"
     default n
 
-config TARGET_LIGHT_FM_C910_VAL_ANT_EVT
-    bool "light fullmask for ant-evt board "
+config TARGET_LIGHT_FM_C910_B_REF
+    bool "light fullmask reference B board"
+    default n
+
+config TARGET_LIGHT_FM_C910_VAL_ANT_REF
+    bool "light fullmask for ant-ref board "
     default n
 
 config TARGET_LIGHT_FM_C910_VAL_ANT_DISCRETE
-    bool "light fullmask for ant-evt board "
+    bool "light fullmask for ant-discrete board "
+    default n
+
+config TARGET_LIGHT_FM_C910_BEAGLE
+    bool "light fullmask for beagle board "
+    default n
+
+config TARGET_LIGHT_FM_C910_LPI4A
+    bool "light fullmask for Lichee Pi 4A board "
+    default n
+
+config TARGET_LIGHT_FM_C910_B_POWER
+    bool "light fullmask for light-b-power board "
     default n
 
 config SYS_TEXT_BASE
@@ -78,13 +98,37 @@ config SYS_TEXT_BASE
 
 config SPL_TEXT_BASE
     hex
-    default 0xffe0000800 if LIGHT_SEC_BOOT_WITH_VERIFY_VAL_A || LIGHT_SEC_BOOT_WITH_VERIFY_VAL_B || LIGHT_SEC_BOOT_WITH_VERIFY_ANT_EVT
-    default 0xffe0000000 if !(LIGHT_SEC_BOOT_WITH_VERIFY_VAL_A || LIGHT_SEC_BOOT_WITH_VERIFY_VAL_B || LIGHT_SEC_BOOT_WITH_VERIFY_ANT_EVT)
+    default 0xffe0000800 if LIGHT_SEC_BOOT_WITH_VERIFY_VAL_A || LIGHT_SEC_BOOT_WITH_VERIFY_VAL_B || LIGHT_SEC_BOOT_WITH_VERIFY_ANT_REF
+    default 0xffe0000000 if !(LIGHT_SEC_BOOT_WITH_VERIFY_VAL_A || LIGHT_SEC_BOOT_WITH_VERIFY_VAL_B || LIGHT_SEC_BOOT_WITH_VERIFY_ANT_REF)
 
 config SPL_MAX_SIZE
     hex
     default 0x2f000
 
+config THEAD_PLIC
+	bool "Light PLIC Setting"
+	depends on RISCV_MMODE || SPL_RISCV_MMODE
+	select REGMAP
+	select SYSCON
+	default n
+	help
+	  The Thead PLIC block holds memory-mapped claim and pending registers
+	  associated with software interrupt.
+
+config THEAD_LIGHT_TIMER
+	bool "Light TIMER0 driver and test"
+	depends on THEAD_PLIC
+	default n
+	help
+	  The timer driver to verify the plic interrupt framework is ready
+
+config THEAD_LIGHT_DIGITAL_SENSOR
+	bool "Light Digital Sensor Setting"
+	depends on THEAD_PLIC
+	default n
+	help
+	  The security digital sensor driver
+
 config BOARD_SPECIFIC_OPTIONS
     def_bool y
     select RISCV_THEAD

board/thead/light-c910/Makefile

@@ -55,6 +55,8 @@ endif # // CONFIG_TARGET_LIGHT_FPGA_FM_C910
 else # // CONFIG_SPL_BUILD
 obj-y += light.o
 obj-y += board.o
+obj-$(CONFIG_THEAD_LIGHT_TIMER) += timer.o
+obj-$(CONFIG_THEAD_LIGHT_DIGITAL_SENSOR) += digital_sensor.o digital_sensor_test.o
 obj-y += clock_config.o
 obj-y += sec_check.o
 obj-y += boot.o
@@ -65,4 +67,5 @@ endif
 
 obj-y += light-sv/pll_io_test.o
 obj-y += light-sv/adc_test.o
+obj-y += version_rollback.o
 endif

board/thead/light-c910/board.c

@@ -12,7 +12,7 @@
 
 #ifdef CONFIG_USB_DWC3
 static struct dwc3_device dwc3_device_data = {
-	.maximum_speed = USB_SPEED_HIGH,
+	.maximum_speed = USB_SPEED_SUPER,
 	.dr_mode = USB_DR_MODE_PERIPHERAL,
 	.index = 0,
 };

board/thead/light-c910/boot.c

@@ -7,24 +7,29 @@
 #include <dm.h>
 #include <fdt_support.h>
 #include <fdtdec.h>
+#include <mmc.h>
 #include <opensbi.h>
 #include <asm/csr.h>
 #include <asm/arch-thead/boot_mode.h>
 #include "../../../lib/sec_library/include/csi_efuse_api.h"
-
-
+#include "../../../lib/sec_library/include/sec_crypto_sha.h"
+#include "../../../lib/sec_library/include/kdf.h"
+#include "../../../lib/sec_library/include/sec_crypto_mac.h"
 
 #if CONFIG_IS_ENABLED(LIGHT_SEC_UPGRADE)
 
-/* The micro is used to enable NON-COT boot with non-signed image */
+/* The macro is used to enable NON-COT boot with non-signed image */
 #define LIGHT_NON_COT_BOOT	1
 
-/* The micro is used to enable uboot version in efuse */
+/* The macro is used to enable uboot version in efuse */
 #define	LIGHT_UBOOT_VERSION_IN_ENV	1
 
-/* The micro is used to enble RPMB ACCESS KEY from KDF */
+/* The macro is used to enble RPMB ACCESS KEY from KDF */
 //#define LIGHT_KDF_RPMB_KEY	1
 
+/* The macro is used to enable secure image version check in boot */
+//#define LIGHT_IMG_VERSION_CHECK_IN_BOOT	1
+
 /* the sample rpmb key is only used for testing */
 #ifndef LIGHT_KDF_RPMB_KEY 
 static const unsigned char emmc_rpmb_key_sample[32] = {0x33, 0x22, 0x11, 0x00, 0x77, 0x66, 0x55, 0x44, \
@@ -34,17 +39,130 @@ static const unsigned char emmc_rpmb_key_sample[32] = {0x33, 0x22, 0x11, 0x00, 0
 #endif
 static unsigned int upgrade_image_version = 0;
 
+#define RPMB_EMMC_CID_SIZE 16
+#define RPMB_CID_PRV_OFFSET             9
+#define RPMB_CID_CRC_OFFSET             15
+static int tee_rpmb_key_gen(uint8_t* key, uint32_t * length)
+{
+	uint32_t data[RPMB_EMMC_CID_SIZE / 4];
+    uint8_t huk[32];
+    uint32_t huk_len;
+	struct mmc *mmc = find_mmc_device(0);
+	int i;
+	sc_mac_t mac_handle;
+	int ret = 0;
+
+	if (!mmc)
+		return -1;
+
+	if (!mmc->ext_csd)
+		return -1;
+
+	for (i = 0; i < ARRAY_SIZE(mmc->cid); i++)
+		data[i] = cpu_to_be32(mmc->cid[i]);
+	/*
+	 * PRV/CRC would be changed when doing eMMC FFU
+	 * The following fields should be masked off when deriving RPMB key
+	 *
+	 * CID [55: 48]: PRV (Product revision)
+	 * CID [07: 01]: CRC (CRC7 checksum)
+	 * CID [00]: not used
+	 */
+	memset((void *)((uint64_t)data + RPMB_CID_PRV_OFFSET), 0, 1);
+	memset((void *)((uint64_t)data + RPMB_CID_CRC_OFFSET), 0, 1);
+
+    /* Step1: Derive HUK from KDF function */
+	ret = csi_kdf_gen_hmac_key(huk, &huk_len);
+	if (ret) {
+		printf("kdf gen hmac key faild[%d]\r\n", ret);
+		return -1;
+	}
+
+    /* Step2: Using HUK and data to generate RPMB key */
+	ret = sc_mac_init(&mac_handle, 0);
+	if (ret) {
+		printf("mac init faild[%d]\r\n", ret);
+		ret = -1;
+		return -1;
+	}
+
+	/* LSB 16 bytes are used as key */
+	ret = sc_mac_set_key(&mac_handle, huk, 16);
+	if (ret) {
+		printf("mac set key faild[%d]\r\n", ret);
+		ret = -1;
+		goto func_exit;
+	}
+
+	ret = sc_mac_calc(&mac_handle, SC_SHA_MODE_256, (uint8_t *)&data, sizeof(data), key, length);
+	if (ret) {
+		printf("mac calc faild[%d]\r\n", ret);
+		ret = -1;
+		goto func_exit;
+	}
+
+func_exit:
+	sc_mac_uninit(&mac_handle);
+
+	return ret;
+
+}
+
+int csi_rpmb_write_access_key(void) 
+{
+    unsigned long *temp_rpmb_key_addr = NULL;
+    char runcmd[64] = {0};
+    uint8_t blkdata[256] = {0};
+    __attribute__((__aligned__(8))) uint8_t kdf_rpmb_key[32];
+	uint32_t kdf_rpmb_key_length = 0;
+	int ret = 0;
+
+#ifdef LIGHT_KDF_RPMB_KEY
+    /* Step1: retrive RPMB key from KDF function */
+	ret = tee_rpmb_key_gen(kdf_rpmb_key, &kdf_rpmb_key_length);
+	if (ret != 0) {
+		return -1;
+	}
+    /* Make sure rpmb key length must be 32*/
+    if (kdf_rpmb_key_length != 32) {
+        return -1;
+    }
+
+	temp_rpmb_key_addr = (unsigned long *)kdf_rpmb_key;
+
+    /* Step2: check whether RPMB key is available */
+    sprintf(runcmd, "mmc rpmb read 0x%lx 0 1 0x%lx", (unsigned long)blkdata, (unsigned long)temp_rpmb_key_addr);
+	ret = run_command(runcmd, 0);
+    if (ret == CMD_RET_SUCCESS) {
+        return -1;
+    }
+
+    /* Step3: Write RPMB key at once */
+    sprintf(runcmd, "mmc rpmb key 0x%lx", (unsigned long)temp_rpmb_key_addr);
+	ret = run_command(runcmd, 0);
+    if (ret != CMD_RET_SUCCESS) {
+        return -1;
+    }
+    return 0;
+#else
+    return 1;
+#endif
+}
+
 int csi_tf_get_image_version(unsigned int *ver)
 {
 	char runcmd[64] = {0};
 	unsigned char blkdata[256];
+	int ret = 0;
 
 	/* tf version reside in RPMB block#0, offset#16*/
 	sprintf(runcmd, "mmc rpmb read 0x%lx 0 1", (unsigned long)blkdata);
-	run_command(runcmd, 0);
-	*ver = (blkdata[16] << 8) + blkdata[17];
-
-	return 0;
+	ret = run_command(runcmd, 0);
+	if (ret == 0) {
+		*ver = (blkdata[16] << 8) + blkdata[17];
+	}
+	
+	return ret;
 }
 
 int csi_tf_set_image_version(unsigned int ver)
@@ -88,11 +206,27 @@ int csi_tee_get_image_version(unsigned int *ver)
 {
 	char runcmd[64] = {0};
 	unsigned char blkdata[256];
+	int ret = 0;
 
 	/* tf version reside in RPMB block#0, offset#0*/
 	sprintf(runcmd, "mmc rpmb read 0x%lx 0 1", (unsigned long)blkdata);
+	ret = run_command(runcmd, 0);
+	if (ret == 0) {
+		*ver = (blkdata[0] << 8) + blkdata[1];
+	}
+
+	return ret;
+}
+
+int csi_kernel_get_image_version(unsigned int *ver)
+{
+	char runcmd[64] = {0};
+	unsigned char blkdata[256];
+
+	/* kernel version reside in RPMB block#0, offset#32*/
+	sprintf(runcmd, "mmc rpmb read 0x%lx 0 1", (unsigned long)blkdata);
 	run_command(runcmd, 0);
-	*ver = (blkdata[0] << 8) + blkdata[1];
+	*ver = (blkdata[32] << 8) + blkdata[33];
 
 	return 0;
 }
@@ -266,6 +400,79 @@ int verify_image_version_rule(unsigned int new_ver, unsigned int cur_ver)
 	return 0;
 }
 
+int check_image_version_rule(unsigned int new_ver, unsigned int cur_ver)
+{
+	unsigned char new_ver_x = 0, new_ver_y = 0;
+	unsigned char cur_ver_x = 0, cur_ver_y = 0;
+
+	/* Get secure version X from image version X.Y */
+	new_ver_x = (new_ver & 0xFF00) >> 8;
+	new_ver_y = new_ver & 0xFF;
+	cur_ver_x = (cur_ver & 0xFF00) >> 8;
+	cur_ver_y = cur_ver & 0xFF;
+
+	/* Ensure image version must be less than expected version */
+	if (new_ver_x < cur_ver_x) {
+		return -1;
+	}
+
+	return 0;
+}
+
+int check_tf_version_in_boot(unsigned long tf_addr)
+{
+	int ret = 0;
+	unsigned int img_version = 0;
+	unsigned int expected_img_version = 0;
+	
+	img_version = get_image_version(tf_addr);
+	if (img_version == 0) {
+		printf("get tf image version fail\n");
+		return -1;
+	}
+
+	ret = csi_tf_get_image_version(&expected_img_version);
+	if (ret != 0) {
+		printf("Get tf expected img version fail\n");
+		return -1;
+	}
+
+	ret = check_image_version_rule(img_version, expected_img_version);
+	if (ret != 0) {
+		printf("Image version breaks the rule\n");
+		return -1;
+	}
+
+	return 0;
+}
+
+int check_tee_version_in_boot(unsigned long tee_addr)
+{
+	int ret = 0;
+	unsigned int img_version = 0;
+	unsigned int expected_img_version = 0;
+	
+	img_version = get_image_version(tee_addr);
+	if (img_version == 0) {
+		printf("get tee image version fail\n");
+		return -1;
+	}
+
+	ret = csi_tee_get_image_version(&expected_img_version);
+	if (ret != 0) {
+		printf("Get tee expected img version fail\n");
+		return -1;
+	}
+
+	ret = check_image_version_rule(img_version, expected_img_version);
+	if (ret != 0) {
+		printf("Image version breaks the rule\n");
+		return -1;
+	}
+
+	return 0;
+}
+
 int light_vimage(int argc, char *const argv[])
 {
 	int ret = 0;
@@ -307,6 +514,13 @@ int light_vimage(int argc, char *const argv[])
 			printf("Get tee img version fail\n");
 			return CMD_RET_FAILURE;
 		}
+	} else if (strcmp(imgname, KERNEL_PART_NAME) == 0){
+
+		ret = csi_kernel_get_image_version(&cur_img_version);
+		if (ret != 0) {
+			printf("Get kernel img version fail\n");
+			return CMD_RET_FAILURE;
+		}
 	} else if (strcmp(imgname, UBOOT_PART_NAME) == 0) {
 		ret = csi_uboot_get_image_version(&cur_img_version);
 		if (ret != 0) {
@@ -351,6 +565,11 @@ int light_vimage(int argc, char *const argv[])
 		if (ret != 0) {
 			return CMD_RET_FAILURE;
 		}
+	} else if (strcmp(imgname, KERNEL_PART_NAME) == 0) {
+		ret = verify_customer_image(T_KRLIMG, vimage_addr);
+		if (ret != 0) {
+			return CMD_RET_FAILURE;
+		}
 	} else if (strcmp(imgname, UBOOT_PART_NAME) == 0) {
 		ret = verify_customer_image(T_UBOOT, vimage_addr);
 		if (ret != 0) {
@@ -369,12 +588,17 @@ int light_secboot(int argc, char * const argv[])
 	int ret = 0;
 	unsigned long tf_addr = LIGHT_TF_FW_ADDR;
 	unsigned long tee_addr = LIGHT_TEE_FW_ADDR;
+    unsigned long kernel_addr = LIGHT_KERNEL_ADDR;
 	unsigned int tf_image_size = 0;
 	unsigned int tee_image_size = 0;
+	unsigned int kernel_image_size = 0;
 
 	printf("\n\n");
 	printf("Now, we start to verify all trust firmware before boot kernel !\n");
 
+    /* Enject RPMB KEY directly in startup */
+    csi_rpmb_write_access_key();
+
 	/* Initialize secure basis of functions */
 	ret = csi_sec_init();
 	if (ret != 0) {
@@ -383,6 +607,13 @@ int light_secboot(int argc, char * const argv[])
 
 	/* Step1. Check and verify TF image */
 	if (image_have_head(LIGHT_TF_FW_TMP_ADDR) == 1) {
+#ifdef LIGHT_IMG_VERSION_CHECK_IN_BOOT
+		printf("check TF version in boot \n");
+		ret = check_tf_version_in_boot(LIGHT_TF_FW_TMP_ADDR);
+		if (ret != 0) {
+			return CMD_RET_FAILURE;
+		}
+#endif
 
 		printf("Process TF image verification ...\n");
 		ret = verify_customer_image(T_TF, LIGHT_TF_FW_TMP_ADDR);
@@ -408,6 +639,14 @@ int light_secboot(int argc, char * const argv[])
 
 	/* Step2. Check and verify TEE image */
 	if (image_have_head(tee_addr) == 1) {
+#ifdef LIGHT_IMG_VERSION_CHECK_IN_BOOT
+		printf("check TEE version in boot \n");
+		ret = check_tee_version_in_boot(tee_addr);
+		if (ret != 0) {
+			return CMD_RET_FAILURE;
+		}
+#endif
+
 		printf("Process TEE image verification ...\n");
 		ret = verify_customer_image(T_TEE, tee_addr);
 		if (ret != 0) {
@@ -427,6 +666,29 @@ int light_secboot(int argc, char * const argv[])
 			return CMD_RET_FAILURE;
 		#endif
 	}
+
+    // /* Step3. Check and verify light kernel image */
+	// if (image_have_head(kernel_addr) == 1) {
+	// 	printf("Process kernel image verification ...\n");
+	// 	ret = verify_customer_image(T_KRLIMG, kernel_addr);
+	// 	if (ret != 0) {
+	// 		return CMD_RET_FAILURE;
+	// 	}
+
+	// 	kernel_image_size = get_image_size(kernel_addr);
+	// 	printf("Kernel image size: %d\n", kernel_image_size);
+	// 	if (kernel_image_size < 0) {
+	// 		printf("GET kernel image size error\n");
+	// 		return CMD_RET_FAILURE;
+	// 	}
+
+	// 	memmove((void *)kernel_addr, (const void *)(kernel_addr + HEADER_SIZE), kernel_image_size);
+	// } else {
+	// 	#ifndef LIGHT_NON_COT_BOOT
+	// 		return CMD_RET_FAILURE;
+	// 	#endif
+	// }
+
 	return 0;
 }
 
@@ -435,10 +697,22 @@ void sec_firmware_version_dump(void)
 	unsigned int tf_ver = 0;
 	unsigned int tee_ver = 0;
 	unsigned int uboot_ver = 0;
+	unsigned int tf_ver_env = 0;
+	unsigned int tee_ver_env = 0;
 
 	csi_uboot_get_image_version(&uboot_ver);
 	csi_tf_get_image_version(&tf_ver);
 	csi_tee_get_image_version(&tee_ver);
+	/* Keep sync with version in RPMB, the Following version could be leveraged by OTA client */
+	tee_ver_env = env_get_hex("tee_version", 0);
+	tf_ver_env = env_get_hex("tf_version", 0);
+	if ((tee_ver_env != tee_ver) && (tee_ver != 0)) {
+		env_set_hex("tee_version", tee_ver);
+	}
+
+	if ((tf_ver_env != tf_ver) && (tf_ver != 0)) {
+		env_set_hex("tf_version", tf_ver);
+	}
 
 	printf("\n\n");
 	printf("Secure Firmware image version info: \n");
@@ -452,6 +726,8 @@ void sec_upgrade_thread(void)
 {
 	const unsigned long temp_addr=0x200000;
 	char runcmd[80];
+    uint8_t * image_buffer = NULL;
+    uint8_t * image_malloc_buffer = NULL;
 	int ret = 0;
 	unsigned int sec_upgrade_flag = 0;
 	unsigned int upgrade_file_size = 0;
@@ -476,6 +752,15 @@ void sec_upgrade_thread(void)
 		upgrade_file_size = env_get_hex("filesize", 0);
 		printf("upgrade file size: %d\n", upgrade_file_size);
 
+        /*store image to temp buffer as temp_addr may be decrypted*/
+        image_malloc_buffer = malloc(upgrade_file_size);
+        if ( image_malloc_buffer == NULL ) {
+			image_buffer = (uint8_t*)temp_addr + upgrade_file_size;
+		} else {
+            image_buffer = image_malloc_buffer;
+        }
+        memcpy(image_buffer, temp_addr, upgrade_file_size);
+
 		/* STEP 2: verify its authentiticy here */
 		sprintf(runcmd, "vimage 0x%p tf", (void *)temp_addr);
 		printf("runcmd:%s\n", runcmd);
@@ -487,7 +772,7 @@ void sec_upgrade_thread(void)
 
 		/* STEP 3: update tf partition */
 		printf("read upgrade image (trust_firmware.bin) into tf partition \n");
-		sprintf(runcmd, "ext4write mmc 0:3 0x%p /trust_firmware.bin 0x%x", (void *)temp_addr, upgrade_file_size);
+		sprintf(runcmd, "ext4write mmc 0:3 0x%p /trust_firmware.bin 0x%x", (void *)image_buffer, upgrade_file_size);
 		printf("runcmd:%s\n", runcmd);
 		ret = run_command(runcmd, 0);
 		if (ret != 0) {
@@ -509,6 +794,10 @@ _upgrade_tf_exit:
 		run_command("saveenv", 0);
 		run_command("reset", 0);
 
+        if ( image_malloc_buffer != NULL ) {
+            free(image_malloc_buffer);
+            image_malloc_buffer = NULL;
+        }
 	} else if (sec_upgrade_flag == TEE_SEC_UPGRADE_FLAG) {
 
  		/* STEP 1: read upgrade image (tee.bin) from stash partition */
@@ -523,6 +812,15 @@ _upgrade_tf_exit:
 		/* Fetch the total file size after read out operation end */
 		upgrade_file_size = env_get_hex("filesize", 0);
 		printf("TEE upgrade file size: %d\n", upgrade_file_size);
+        
+        /*store image to temp buffer as temp_addr may be decrypted*/
+        image_malloc_buffer = malloc(upgrade_file_size);
+        if ( image_malloc_buffer == NULL ) {
+			image_buffer = (uint8_t*)temp_addr + upgrade_file_size;
+		} else {
+            image_buffer = image_malloc_buffer;
+        }
+        memcpy(image_buffer, temp_addr, upgrade_file_size);
 
 		/* STEP 2: verify its authentiticy here */
 		sprintf(runcmd, "vimage 0x%p tee", (void *)temp_addr);
@@ -535,7 +833,7 @@ _upgrade_tf_exit:
 
 		/* STEP 3: update tee partition */
 		printf("read upgrade image (tee.bin) into tf partition \n");
-		sprintf(runcmd, "ext4write mmc 0:4 0x%p /tee.bin 0x%x", (void *)temp_addr, upgrade_file_size);
+		sprintf(runcmd, "ext4write mmc 0:4 0x%p /tee.bin 0x%x", (void *)image_buffer, upgrade_file_size);
 		printf("runcmd:%s\n", runcmd);
 		ret = run_command(runcmd, 0);
 		if (ret != 0) {
@@ -556,7 +854,11 @@ _upgrade_tee_exit:
 		run_command("env set sec_upgrade_mode 0", 0);
 		run_command("saveenv", 0);
 		run_command("reset", 0);
-
+        
+        if ( image_malloc_buffer != NULL ) {
+            free(image_malloc_buffer);
+            image_malloc_buffer = NULL;
+        }
 	} else if (sec_upgrade_flag == UBOOT_SEC_UPGRADE_FLAG) { 
 		unsigned int block_cnt;
 		struct blk_desc *dev_desc;

board/thead/light-c910/clock_config.c

@@ -29,6 +29,19 @@
 #define VOSYS_SYSREG_BASE	(0xffef528000)
 #define VOSYS_CLK_GATE_REG	(VOSYS_SYSREG_BASE + 0x50)
 #define VOSYS_CLK_GATE1_REG	(VOSYS_SYSREG_BASE + 0x54)
+#define VOSYS_DPU_CCLK_CFG	(VOSYS_SYSREG_BASE + 0x64)
+
+/* VISYS_SYSREG_R */
+#define VISYS_SYSREG_BASE		(0xffe4040000)
+#define VISYS_MIPI_CSI0_PIXELCLK	(VISYS_SYSREG_BASE + 0x30)
+#define VISYS_ISP0_CLK_CFG		(VISYS_SYSREG_BASE + 0x24)
+#define VISYS_ISP1_CLK_CFG              (VISYS_SYSREG_BASE + 0x28)
+#define VISYS_ISP_RY_CLK_CFG            (VISYS_SYSREG_BASE + 0x2c)
+
+/* APSYS_SYSREG_R */
+#define APSYS_CLKGEN_BASE		(0xffef010000)
+#define APSYS_DPU0_PLL_DIV_CFG		(APSYS_CLKGEN_BASE + 0x1e8)
+#define APSYS_DPU1_PLL_DIV_CFG          (APSYS_CLKGEN_BASE + 0x1ec)
 
 /* AP_DPU0_PLL_CFG1 */
 #define AP_DPU0_PLL_RST		BIT(29)
@@ -105,6 +118,51 @@
 /* VOSYS_CLK_GATE1_REG */
 #define CLKCTRL_HDMI_PIXCLK_EN		BIT(0)
 
+/* VOSYS_DPU_CCLK_CFG */
+#define VOSYS_DPU_CCLK_DIV_NUM_MASK	0xf
+#define VOSYS_DPU_CCLK_DIV_NUM_SHIFT	0
+#define VOSYS_DPU_CCLK_DIV_EN		BIT(4)
+
+/* VISYS_MIPI_CSI0_PIXELCLK  */
+#define VISYS_MIPI_CSI0_PIXELCLK_DIV_NUM_SHIFT	0
+#define VISYS_MIPI_CSI0_PIXELCLK_DIV_NUM_MASK	0xf
+#define VISYS_MIPI_CSI0_PIXELCLK_DIV_EN		BIT(4)
+
+/* VISYS_ISP0_CLK_CFG */
+#define VISYS_ISP0_CLK_DIV_EN			BIT(4)
+#define VISYS_ISP0_CLK_DIV_NUM_SHIFT		(0)
+#define VISYS_ISP0_CLK_DIV_NUM_MASK		0xf
+
+/* VISYS_ISP1_CLK_CFG */
+#define VISYS_ISP1_CLK_DIV_EN			BIT(4)
+#define VISYS_ISP1_CLK_DIV_NUM_SHIFT		(0)
+#define VISYS_ISP1_CLK_DIV_NUM_MASK		0xf
+
+/* VISYS_ISP_RY_CLK_CFG */
+#define VISYS_ISP_RY_CLK_DIV_EN			BIT(4)
+#define VISYS_ISP_RY_CLK_DIV_NUM_SHIFT		(0)
+#define VISYS_ISP_RY_CLK_DIV_NUM_MASK		0xf
+
+/* APSYS_DPU0_PLL_DIV_CFG  */
+#define APSYS_DPU0_PLL_DIV_CLK_DIV_EN		BIT(8)
+#define APSYS_DPU0_PLL_DIV_CLK_DIV_NUM_MASK	0xff
+#define APSYS_DPU0_PLL_DIV_CLK_DIV_NUM_SHIFT	0
+
+/* APSYS_DPU1_PLL_DIV_CFG  */
+#define APSYS_DPU1_PLL_DIV_CLK_DIV_EN		BIT(8)
+#define APSYS_DPU1_PLL_DIV_CLK_DIV_NUM_MASK	0xff
+#define APSYS_DPU1_PLL_DIV_CLK_DIV_NUM_SHIFT	0
+
+enum multimedia_div_type {
+	VI_MIPI_CSI0_DIV,
+	VI_ISP0_CORE_DIV,
+	VI_ISP1_CORE_DIV,
+	VI_ISP_RY_CORE_DIV,
+	VO_DPU_CORE_DIV,
+	VO_DPU_PLL0_DIV,
+	VO_DPU_PLL1_DIV,
+};
+
 #define C910_CCLK	0
 #define C910_CCLK_I0	1
 #define CLK_END		16
@@ -189,6 +247,10 @@ static const struct light_pll_rate_table light_cpupll_tbl[] = {
 	LIGHT_PLL_RATE(3000000000U, 1000000000U, 1, 125, 0, 3, 1),
 	LIGHT_PLL_RATE(3000000000U, 1500000000U, 1, 125, 0, 2, 1),
 	LIGHT_PLL_RATE(1800000000U, 1800000000U, 1, 75,  0, 1, 1),
+	LIGHT_PLL_RATE(2256000000U, 752000000U,  1, 94,  0, 3, 1),
+	LIGHT_PLL_RATE(3000000000U, 300000000U,  1, 125, 0, 5, 2),
+	LIGHT_PLL_RATE(1848000000U, 1848000000U, 1, 77,  0, 1, 1),
+	LIGHT_PLL_RATE(1872000000U, 1872000000U, 1, 78,  0, 1, 1),
 };
 
 static const struct light_pll_rate_table light_audio_pll_tbl[] = {
@@ -605,11 +667,6 @@ struct clk_lightmux {
 	enum clk_device_type clk_dev_type;
 };
 
-struct clk_info {
-	const char *clk_name;
-	enum clk_device_type clk_dev_type;
-};
-
 static const struct clk_info c910_cclk_sels[] = {
 	{"c910_cclk_i0", CLK_DEV_MUX},
 	{"cpu_pll1_foutpostdiv", CLK_DEV_PLL},
@@ -686,7 +743,7 @@ int clk_light_set_parent(const char *clk_name, const char *parent)
 	if (!strcmp(clk->clk_name, parent))
 		return 0;
 
-	printf("clk->num_parents = %d\n", clk->num_parents);
+	debug("clk->num_parents = %d\n", clk->num_parents);
 
 	for (i = 0; i < clk->num_parents; i++) {
 		pr_debug("parent%d:%s\n", i, clk->parents[i].clk_name);
@@ -1007,7 +1064,7 @@ void ap_peri_clk_disable(void)
 {
 	unsigned int clk_cfg;
 
-#if (defined CONFIG_TARGET_LIGHT_FM_C910_VAL_B) || (defined CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_EVT) || (defined CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_DISCRETE)
+#if (defined CONFIG_TARGET_LIGHT_FM_C910_VAL_B) || (defined CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_REF) || (defined CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_DISCRETE) || (defined CONFIG_TARGET_LIGHT_FM_C910_B_POWER)
 	clk_cfg = readl((void __iomem *)AP_PERI_CLK_CFG);
 	clk_cfg &= ~(GMAC1_CLK_EN);
 	writel(clk_cfg, (void __iomem *)AP_PERI_CLK_CFG);
@@ -1089,6 +1146,70 @@ void ap_mipi_dsi1_clk_endisable(bool en)
 	writel(cfg1, (void __iomem *)AP_DPU1_PLL_CFG1);
 }
 
+static void ap_multimedia_div_num_set(enum multimedia_div_type type, unsigned int div_num)
+{
+	unsigned long div_reg;
+	unsigned int div_num_shift, div_num_mask, div_en;
+	unsigned int div_cfg;
+
+	switch (type) {
+	case VI_MIPI_CSI0_DIV:
+		div_reg = VISYS_MIPI_CSI0_PIXELCLK;
+		div_num_shift = VISYS_MIPI_CSI0_PIXELCLK_DIV_NUM_SHIFT;
+		div_num_mask = VISYS_MIPI_CSI0_PIXELCLK_DIV_NUM_MASK;
+		div_en = VISYS_MIPI_CSI0_PIXELCLK_DIV_EN;
+		break;
+	case VI_ISP0_CORE_DIV:
+		div_reg = VISYS_ISP0_CLK_CFG;
+		div_num_shift = VISYS_ISP0_CLK_DIV_NUM_SHIFT;
+		div_num_mask = VISYS_ISP0_CLK_DIV_NUM_MASK;
+		div_en = VISYS_ISP0_CLK_DIV_EN;
+		break;
+	case VI_ISP1_CORE_DIV:
+		div_reg = VISYS_ISP1_CLK_CFG;
+		div_num_shift = VISYS_ISP1_CLK_DIV_NUM_SHIFT;
+		div_num_mask = VISYS_ISP1_CLK_DIV_NUM_MASK;
+		div_en = VISYS_ISP1_CLK_DIV_EN;
+		break;
+	case VI_ISP_RY_CORE_DIV:
+		div_reg = VISYS_ISP_RY_CLK_CFG;
+		div_num_shift = VISYS_ISP_RY_CLK_DIV_NUM_SHIFT;
+		div_num_mask = VISYS_ISP_RY_CLK_DIV_NUM_MASK;
+		div_en = VISYS_ISP_RY_CLK_DIV_EN;
+		break;
+	case VO_DPU_CORE_DIV:
+		div_reg = VOSYS_DPU_CCLK_CFG;
+		div_num_shift = VOSYS_DPU_CCLK_DIV_NUM_SHIFT;
+		div_num_mask = VOSYS_DPU_CCLK_DIV_NUM_MASK;
+		div_en = VOSYS_DPU_CCLK_DIV_EN;
+		break;
+	case VO_DPU_PLL0_DIV:
+		div_reg =APSYS_DPU0_PLL_DIV_CFG;
+		div_num_shift = APSYS_DPU0_PLL_DIV_CLK_DIV_NUM_SHIFT;
+		div_num_mask = APSYS_DPU0_PLL_DIV_CLK_DIV_NUM_MASK;
+		div_en = APSYS_DPU0_PLL_DIV_CLK_DIV_EN;
+		break;
+	case VO_DPU_PLL1_DIV:
+		div_reg =APSYS_DPU1_PLL_DIV_CFG;
+		div_num_shift = APSYS_DPU1_PLL_DIV_CLK_DIV_NUM_SHIFT;
+		div_num_mask = APSYS_DPU1_PLL_DIV_CLK_DIV_NUM_MASK;
+		div_en = APSYS_DPU1_PLL_DIV_CLK_DIV_EN;
+		break;
+	default:
+		printf("invalid ap multimedia divider type\n");
+		return;
+	}
+
+	div_cfg = readl((void __iomem *)div_reg);
+	div_cfg &= ~div_en;
+	writel(div_cfg, (void __iomem *)div_reg);
+
+	div_cfg &= ~(div_num_mask << div_num_shift);
+	div_cfg |= (div_num & div_num_mask) << div_num_shift;
+	div_cfg |= div_en;
+	writel(div_cfg, (void __iomem *)div_reg);
+}
+
 int clk_config(void)
 {
 	unsigned long rate = clk_light_get_rate("c910_cclk", CLK_DEV_MUX);
@@ -1178,6 +1299,18 @@ int clk_config(void)
 	if (ret)
 		return ret;
 #endif
+
+	/* The boards other than the LightA board perform the bus down-speed operation */
+
+#if defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_DISCRETE) || defined (CONFIG_TARGET_LIGHT_FM_C910_BEAGLE) || defined (CONFIG_TARGET_LIGHT_FM_C910_B_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_B_POWER) || defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_B) || defined (CONFIG_TARGET_LIGHT_FM_C910_LPI4A)
+	ap_multimedia_div_num_set(VI_MIPI_CSI0_DIV, 12); /* Input frquency: 2376MHZ */
+	ap_multimedia_div_num_set(VI_ISP0_CORE_DIV, 15); /* Input frquency: 2376MHZ */
+	ap_multimedia_div_num_set(VI_ISP1_CORE_DIV, 12); /* Input frquency: 2376MHZ */
+	ap_multimedia_div_num_set(VI_ISP_RY_CORE_DIV, 12); /* Input frquency: 2376MHZ */
+	ap_multimedia_div_num_set(VO_DPU_CORE_DIV, 4);	/* Input frquency: 2376MHZ */
+	ap_multimedia_div_num_set(VO_DPU_PLL0_DIV, 16);
+	ap_multimedia_div_num_set(VO_DPU_PLL1_DIV, 4);
+#endif
 	ap_hdmi_clk_endisable(false);
 	ap_mipi_dsi1_clk_endisable(false);
 

board/thead/light-c910/digital_sensor.c

@@ -0,0 +1,449 @@
+/*
+ * Copyright (C) 2017-2020 Alibaba Group Holding Limited
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/types.h>
+#include <thead/clock_config.h>
+#include <linux/bitops.h>
+#include <asm/arch-thead/light-iopmp.h>
+#include <asm/arch-thead/light-plic.h>
+
+#define LIGHT_TEE_SYSREG_BASE	((void __iomem*)0xffff200000)
+#define REG_SECURITY_ERR_3	(LIGHT_TEE_SYSREG_BASE + 0x30)
+
+/* id: 0~8 */
+#define DS_C910_BASE(id)	(0xffffc57000 + (id) * 0x40)
+#define DS_APB_BASE(id)		(0xffff270000 + ((id) - 4) * 0x1000)
+
+#define DS_BASE(id)		(((id) > 3) ? (DS_APB_BASE(id)) : (DS_C910_BASE(id)))
+
+#define REG_HW_VERSION(id)			((void __iomem *)DS_BASE(id) + 0x00)	//RO
+#define REG_SENSOR_ALARM(id)			((void __iomem *)DS_BASE(id) + 0x04)	//RO
+#define REG_HEALTH_TEST_ALARM(id)		((void __iomem *)DS_BASE(id) + 0x08)	//RO
+#define REG_HEALTH_TEST_STATUS(id)		((void __iomem *)DS_BASE(id) + 0x0C)	//RO
+#define REG_CONTROL(id)				((void __iomem *)DS_BASE(id) + 0x10)	//WO
+#define REG_IRQ_STATUS(id)			((void __iomem *)DS_BASE(id) + 0x14)	//RO
+#define REG_IRQ_CLEAR(id)			((void __iomem *)DS_BASE(id) + 0x18)	//WO
+#define REG_IRQ_CONFIG(id)			((void __iomem *)DS_BASE(id) + 0x1C)	//RW
+#define REG_STATUS_DSX(id, x)			((void __iomem *)DS_BASE(id) + 0x20 + 0x04 * x)	//RO
+
+#define LIGHT_SEC_IRQ_NUM			91
+
+#define MAX_DIGITAL_SENSOR_NUM			9
+#define MAX_HW_MACRO_NUM_PER_DS			16
+
+#define DS_HW_MACRO_TL_MASK			0xffff
+
+#define DS_INVALID_MACRO_ID			MAX_HW_MACRO_NUM_PER_DS
+
+#define DS_1_ERR				BIT(16)	//digital_sensor_C910_0 ~ digital_sensor_C910_3
+#define DS_3_ERR				BIT(18) //digital_sensor_apb_3
+#define DS_4_ERR				BIT(19) //digital_sensor_apb_4
+#define DS_5_ERR				BIT(20) //digital_sensor_apb_5
+#define DS_6_ERR				BIT(21) //digital_sensor_apb_6
+#define DS_7_ERR				BIT(22) //digital_sensor_apb_7
+#define DS_ERR					(DS_1_ERR | DS_3_ERR | DS_4_ERR | DS_5_ERR | DS_6_ERR | DS_7_ERR)
+
+#define CFG_DS_CPU_THREAT_LEVEL			0
+#define CFG_APB0_THREAT_LEVEL			0
+#define CFG_APB1_THREAT_LEVEL			0
+
+#define AONSYS_RSTGEN_BASE			((void __iomem *)0xFFFFF44000UL)
+#define REG_SYS_RST_CFG				(AONSYS_RSTGEN_BASE + 0x10)
+#define SW_SYS_RST_REQ				(1 << 0)
+#define REG_RST_REQ_EN_0			(AONSYS_RSTGEN_BASE + 0x140)
+#define SW_GLB_RST_EN				(1 << 0)
+
+struct ds_data {
+	int id;
+	u32 hw_macro_num;
+};
+
+struct ds_data ds_array[MAX_DIGITAL_SENSOR_NUM] = {
+	{0, 4},		//digital_sensor_C910_0
+	{1, 4},		//digital_sensor_C910_1
+	{2, 4},		//digital_sensor_C910_2
+	{3, 4},		//digital_sensor_C910_3
+	{4, 16},	//digital_sensor_apb_3
+	{5, 11},	//digital_sensor_apb_4
+	{6, 4},		//digital_sensor_apb_5
+	{7, 16},	//digital_sensor_apb_6
+	{8, 8},		//digital_sensor_apb_7
+};
+
+static void system_reset(void)
+{
+	u32 data = readl(REG_RST_REQ_EN_0);
+
+	/* global reset enable */
+	data |= SW_GLB_RST_EN;
+	writel(data, REG_RST_REQ_EN_0);
+
+	/* global reset request */
+	writel(SW_SYS_RST_REQ, REG_SYS_RST_CFG);
+	mdelay(1000);
+}
+
+static u32 ds_hw_macro_threat_level_get(int ds_id, u32 macro_id)
+{
+	return readl(REG_STATUS_DSX(ds_id, macro_id)) & DS_HW_MACRO_TL_MASK;
+}
+
+static __maybe_unused int ds_health_test_done_status(int ds_id, u32 macro_id)
+{
+	return readl(REG_HEALTH_TEST_STATUS(ds_id)) & (1 << macro_id) ? 1 : 0;
+}
+
+static __maybe_unused int ds_health_test_alarm_status(int ds_id, u32 macro_id)
+{
+	return readl(REG_HEALTH_TEST_ALARM(ds_id)) & (1 << macro_id) ? 1 : 0;
+}
+
+static __maybe_unused bool ds_sensor_alarm_event_hw_macro_get(int ds_id, u32 *event_macro)
+{
+	u32 alarm_status = readl(REG_SENSOR_ALARM(ds_id));
+	int num = ds_array[ds_id].hw_macro_num;
+	int s_alarm_bit = 0, j = 0;
+	bool sensor_alarm_event_occured = false;
+
+	for (int i = 0; i < num; i++) {
+		s_alarm_bit = 1 << i;
+		if (alarm_status & s_alarm_bit) {
+			event_macro[j] = i;
+			j++;
+			sensor_alarm_event_occured = true;
+		}
+	}
+
+	return sensor_alarm_event_occured;
+}
+
+static __maybe_unused bool ds_health_alarm_event_hw_macro_get(int ds_id, u32 *event_macro)
+{
+	u32 h_alarm_status = readl(REG_HEALTH_TEST_ALARM(ds_id));
+	int num = ds_array[ds_id].hw_macro_num;
+	int h_alarm_bit = 0, j = 0;
+	bool health_alarm_event_occured = false;
+
+	for (int i = 0; i < num; i++) {
+		h_alarm_bit = 1 << i;
+		if (h_alarm_status & h_alarm_bit) {
+			event_macro[j] = i;
+			j++;
+			health_alarm_event_occured = true;
+		}
+	}
+
+	return health_alarm_event_occured;
+}
+
+static bool ds_sensor_irq_hw_macro_get(int ds_id, u32 *irq_macro)
+{
+	u32 irq_status = readl(REG_IRQ_STATUS(ds_id));
+	int num = ds_array[ds_id].hw_macro_num;
+	int s_alarm_bit = 0, j = 0;
+	bool sensor_alarm_irq_occured = false;
+
+	for (int i = 0; i < num; i++) {
+		s_alarm_bit = 1 << ((i << 1) + 1);
+		if (irq_status & s_alarm_bit) {
+			irq_macro[j] = i;
+			debug("[%s,%d]irq_macro[%d] = %d\n", __func__, __LINE__,
+							j, irq_macro[j]);
+			j++;
+			sensor_alarm_irq_occured = true;
+		}
+	}
+
+	debug("[%s,%d] sensor_alarm_irq_occured = %d\n", __func__, __LINE__,
+							sensor_alarm_irq_occured);
+	return sensor_alarm_irq_occured;
+}
+
+static __maybe_unused bool ds_health_irq_hw_macro_get(int ds_id, u32 *irq_macro)
+{
+	u32 irq_status = readl(REG_IRQ_STATUS(ds_id));
+	int num = ds_array[ds_id].hw_macro_num;
+	int h_alarm_bit = 0, j = 0;
+	bool health_alarm_irq_occured = false;
+
+	for (int i = 0; i < num; i++) {
+		h_alarm_bit = 1 << (i << 1);
+		if (irq_status & h_alarm_bit) {
+			irq_macro[j] = i;
+			j++;
+			health_alarm_irq_occured = true;
+		}
+	}
+
+	return health_alarm_irq_occured;
+}
+
+static void ds_sensor_irq_clear(int ds_id, u32 macro_id)
+{
+	int s_alarm_bit = 1 << ((macro_id << 1) + 1);
+
+	debug("[%s,%d]reg: 0x%lx, s_alarm_bit = 0x%x\n", __func__, __LINE__,
+							(unsigned long)REG_IRQ_CLEAR(ds_id), s_alarm_bit);
+
+	writel(s_alarm_bit, REG_IRQ_CLEAR(ds_id));
+}
+
+static __maybe_unused void ds_health_irq_clear(int ds_id, u32 macro_id)
+{
+	int h_alarm_bit = 1 << (macro_id << 1);
+
+	writel(h_alarm_bit, REG_IRQ_CLEAR(ds_id));
+}
+
+static void ds_hw_macro_sensor_alarm_endisable(int ds_id, u32 macro_id, bool en)
+{
+	int s_alarm_bit = 1 << ((macro_id << 1) + 1);
+	u32 bitmap = readl(REG_IRQ_CONFIG(ds_id));
+
+	if (en)
+		bitmap |= s_alarm_bit;
+	else
+		bitmap &= ~s_alarm_bit;
+
+	writel(bitmap, REG_IRQ_CONFIG(ds_id));
+}
+
+static __maybe_unused void ds_hw_macro_health_alarm_endisable(int ds_id, u32 macro_id, bool en)
+{
+	int h_alarm_bit = 1 <<  (macro_id << 1);
+	u32 bitmap = readl(REG_IRQ_CONFIG(ds_id));
+
+	if (en)
+		bitmap |= h_alarm_bit;
+	else
+		bitmap &= ~h_alarm_bit;
+
+	writel(bitmap, REG_IRQ_CONFIG(ds_id));
+}
+
+static void ds_hw_macro_rearm(int ds_id, u32 macro_id, int macro_size)
+{
+	int rearm_bit = 1 << (macro_id + macro_size);
+
+	debug("[%s,%d]rearm_bit = 0x%x\n", __func__, __LINE__, rearm_bit);
+	writel(rearm_bit, REG_CONTROL(ds_id));
+}
+
+static __maybe_unused void ds_hw_macro_health_test_start(int ds_id, u32 macro_id)
+{
+	int start_bit = 1 << macro_id;
+
+	writel(start_bit, REG_CONTROL(ds_id));
+}
+
+static void light_sec_irq_handler(void)
+{
+	u32 id, i, j = 0, t = 0, size;
+	u32 tl;
+	u32 irq_macro[MAX_HW_MACRO_NUM_PER_DS] = {0};
+	u32 apb_ds[8] = {0};
+	u32 status = readl(REG_SECURITY_ERR_3);
+
+	if (!status)
+		return;
+
+	if (!(status & DS_ERR)) {
+		printf("Unexpected security interrupt but not ditital sensor alarm occured\n");
+		return; //drop other security interrupts, how to clear ?
+	}
+
+	if (status & DS_1_ERR) {
+		printf("C910 cpu digital sensor detect error event\n");
+
+		for (id = 0; id < 4; id++) {
+			for (i = 0; i < ARRAY_SIZE(irq_macro); i++)
+				irq_macro[i] = DS_INVALID_MACRO_ID;
+
+			if (!ds_sensor_irq_hw_macro_get(id, irq_macro))
+				continue;
+
+			size = ds_array[id].hw_macro_num;
+
+			i = 0;
+			while (i < MAX_HW_MACRO_NUM_PER_DS && irq_macro[i] != DS_INVALID_MACRO_ID) {
+
+				tl = ds_hw_macro_threat_level_get(id, irq_macro[i]);
+
+				printf("DS%d-MACRO%d Threat Level: 0x%x\n", id, irq_macro[i], tl);
+
+				if (tl >= CFG_DS_CPU_THREAT_LEVEL) {
+#if 0
+					run_command("ds_cpu_alarm 1500000000", 0);
+#else
+					system_reset();
+#endif
+				} else {
+#if 0
+					run_command("ds_cpu_alarm 1500000000", 0);
+#else
+					system_reset();
+#endif
+				}
+
+				//Fixmed: before irq clear !!!
+				ds_hw_macro_rearm(id, irq_macro[i], size);
+
+				ds_sensor_irq_clear(id, irq_macro[i]);
+
+				i++;
+			}
+		}
+	}
+
+	if (status & DS_3_ERR) {
+		printf("apb digital sensor3 detect error event\n");
+		apb_ds[j++] = 4;
+	}
+
+	if (status & DS_4_ERR) {
+		printf("apb digital sensor4 detect error event\n");
+		apb_ds[j++] = 5;
+	}
+
+	if (status & DS_5_ERR) {
+		printf("apb digital sensor5 detect error event\n");
+		apb_ds[j++] = 6;
+	}
+
+	if (status & DS_6_ERR) {
+		printf("apb digital sensor6 detect error event\n");
+		apb_ds[j++] = 7;
+	}
+
+	if (status & DS_7_ERR) {
+		printf("apb digital sensor7 detect error event\n");
+		apb_ds[j++] = 8;
+	}
+
+
+	while (apb_ds[t]) {
+		if (apb_ds[t] < 4 || apb_ds[t] > 8) {
+			printf("invalid digial sensor id(%d)\n", apb_ds[t]);
+			return;
+		}
+
+		for (i = 0; i < ARRAY_SIZE(irq_macro); i++)
+			irq_macro[i] = DS_INVALID_MACRO_ID;
+
+		size = ds_array[apb_ds[t]].hw_macro_num;
+
+		if (ds_sensor_irq_hw_macro_get(apb_ds[t], irq_macro)) {
+
+			i = 0;
+			while (i < MAX_HW_MACRO_NUM_PER_DS && irq_macro[i] != DS_INVALID_MACRO_ID) {//hardware macro
+
+				debug("[%s,%d]irq_status = 0x%x, alarm_status = 0x%x\n", __func__, __LINE__,
+						readl(REG_IRQ_STATUS(apb_ds[t])), readl(REG_SENSOR_ALARM(apb_ds[t])));
+
+				tl = ds_hw_macro_threat_level_get(apb_ds[t], irq_macro[i]);
+				if (tl)
+					printf("DS%d-MACRO%d Threat Level: 0x%x\n", apb_ds[t], irq_macro[i], tl);
+
+				if (apb_ds[t] == 8 && tl >= CFG_APB1_THREAT_LEVEL) {
+					//handle1
+					run_command("ds_3to6_alarm 4", 0);
+				} else if (tl >= CFG_APB0_THREAT_LEVEL) {
+					//handle2
+					run_command("ds_3to6_alarm 4", 0);
+				} else {
+					//handle3
+					run_command("ds_3to6_alarm 4", 0);
+				}
+
+				//Fixmed: before irq clear !!!
+				ds_hw_macro_rearm(apb_ds[t], irq_macro[i], size);
+
+				ds_sensor_irq_clear(apb_ds[t], irq_macro[i]);
+
+				i++;
+			}
+		}
+
+		t++; //digital number
+	}
+}
+
+static int ds_platform_init(void)
+{
+	int ds_id, macro_id, ret = 0;
+
+	for (ds_id = 0; ds_id < MAX_DIGITAL_SENSOR_NUM; ds_id++) {
+
+		printf("Digital Sensor%d HW Version: 0x%x\n", ds_id, readl(REG_HW_VERSION(ds_id)));
+
+		for (macro_id = 0; macro_id < ds_array[ds_id].hw_macro_num; macro_id++) {
+			ds_hw_macro_sensor_alarm_endisable(ds_id,
+					                   macro_id, true);
+			ds_hw_macro_health_test_start(ds_id, macro_id);
+			udelay(5);
+			ret = ds_health_test_done_status(ds_id, macro_id);
+			if (!ret) {
+				printf("health test failed for DS%d-Macro%d\n", ds_id, macro_id);
+				ds_hw_macro_sensor_alarm_endisable(ds_id,
+								   macro_id, false);
+			} else {
+				ret = ds_health_test_alarm_status(ds_id, macro_id);
+				if (ret) {
+					ds_hw_macro_sensor_alarm_endisable(ds_id,
+								   macro_id, false);
+					printf("health test failed for DS%d-Macro%d\n", ds_id, macro_id);
+				}
+			}
+		}
+	}
+
+	return 0;
+}
+
+static int ds_sec_interrupt_init(void)
+{
+	int ret;
+
+	ret = irq_handler_register(LIGHT_SEC_IRQ_NUM, light_sec_irq_handler);
+	if (ret) {
+		printf("failed to register security interrupt handler\n");
+		return ret;
+	}
+
+	irq_priority_set(LIGHT_SEC_IRQ_NUM);
+	irq_enable(LIGHT_SEC_IRQ_NUM);
+
+	return 0;
+}
+
+void ds_uninit(void)
+{
+	int ds_id, macro_id;
+
+	irq_disable(LIGHT_SEC_IRQ_NUM);
+
+	for (ds_id = 0; ds_id < MAX_DIGITAL_SENSOR_NUM; ds_id++) {
+		for (macro_id = 0; macro_id < ds_array[ds_id].hw_macro_num; macro_id++)
+			ds_hw_macro_sensor_alarm_endisable(ds_id, macro_id, false);
+	}
+
+	irq_handler_register(LIGHT_SEC_IRQ_NUM, NULL);
+}
+
+int ds_init(void)
+{
+	int ret;
+
+	ds_platform_init();
+
+	ret = ds_sec_interrupt_init();
+	if (ret)
+		return ret;
+
+	return 0;
+}

board/thead/light-c910/digital_sensor_test.c

@@ -0,0 +1,153 @@
+/*
+ * Copyright (C) 2017-2022 Alibaba Group Holding Limited
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/types.h>
+#include <thead/clock_config.h>
+#include <linux/bitops.h>
+#include <asm/arch-thead/light-iopmp.h>
+#include <asm/arch-thead/light-plic.h>
+#include <thead/clock_config.h>
+
+#define TEE_LIGHT_APCLK_ADDRBASE	((void __iomem *)0xffff011000)
+#define REG_TEESYS_CLK_TEECFG		((void __iomem *)TEE_LIGHT_APCLK_ADDRBASE + 0x1cc)
+
+/* VIDEO PLL */
+#define	TEESYS_I1_HCLK_DIV_EN		BIT(12)
+#define TEESYS_I1_HCLK_DIV_NUM_SHIFT	8
+#define TEESYS_I1_HCLK_DIV_NUM_MASK	0xf
+
+#define LIGHT_CPUFREQ_THRE              1500000
+#define LIGHT_C910_BUS_CLK_SYNC         BIT(11)
+#define LIGHT_C910_BUS_CLK_RATIO_MASK   0x700
+#define LIGHT_C910_BUS_CLK_DIV_RATIO_2  0x100
+#define LIGHT_C910_BUS_CLK_DIV_RATIO_3  0x200
+
+extern int ds_init(void);
+
+bool global_ds_init = false;
+
+static int ds_cpu_alarm_clk_set(cmd_tbl_t *cmdtp, int flag, int argc,
+				char * const argv[])
+{
+	unsigned long new_freq;
+	int ret = 0;
+	u32 val;
+	const struct clk_info *parent;
+
+	if (argc != 2) {
+		printf("invalid input parameters\n");
+		return -EINVAL;
+	}
+
+	if (strict_strtoul(argv[1], 10, &new_freq) < 0)
+		return CMD_RET_USAGE;
+
+	val = readl(TEE_LIGHT_APCLK_ADDRBASE + 0x100);
+	val &= ~LIGHT_C910_BUS_CLK_RATIO_MASK;
+	val |= LIGHT_C910_BUS_CLK_DIV_RATIO_3;
+
+	writel(val, TEE_LIGHT_APCLK_ADDRBASE + 0x100);
+	val &= ~LIGHT_C910_BUS_CLK_SYNC;
+	writel(val, TEE_LIGHT_APCLK_ADDRBASE + 0x100);
+	udelay(1);
+	val |= LIGHT_C910_BUS_CLK_SYNC;
+	writel(val, TEE_LIGHT_APCLK_ADDRBASE + 0x100);
+	udelay(1);
+
+	printf("wait for cpu frequency alarm, rate: %ld\n", new_freq);
+
+	parent = clk_light_get_parent("c910_cclk");
+	if (!strcmp(parent->clk_name,  "cpu_pll1_foutpostdiv")) {
+		ret = clk_light_set_rate("c910_cclk_i0", CLK_DEV_MUX, new_freq);
+		if (ret) {
+			printf("failed to set cpu frequency\n");
+			ret = -EINVAL;
+			goto out;
+		}
+		udelay(3);
+		ret = clk_light_set_parent("c910_cclk", "c910_cclk_i0");
+		if (ret) {
+			printf("failed to set parent clock for cpu\n");
+			ret = -EINVAL;
+			goto out;
+		}
+	} else {
+		ret = clk_light_set_rate("cpu_pll1_foutpostdiv", CLK_DEV_PLL, new_freq);
+		if (ret) {
+			printf("failed to set cpu frequency\n");
+			ret = -EINVAL;
+			goto out;
+		}
+		udelay(3);
+		ret = clk_light_set_parent("c910_cclk", "cpu_pll1_foutpostdiv");
+		if (ret) {
+			printf("failed to set parent clock for cpu\n");
+			ret = -EINVAL;
+			goto out;
+		}
+	}
+
+	printf("C910 CPU FREQ: %ldMHz\n", new_freq / 1000000);
+
+out:
+	return ret;
+}
+
+static int ds_3to6_alarm_clk_set(cmd_tbl_t *cmdtp, int flag, int argc,
+				 char * const argv[])
+{
+	unsigned long div;
+	int ret = 0;
+	u32 cfg;
+
+	if (argc != 2) {
+		printf("invalid input parameters\n");
+		return -EINVAL;
+	}
+
+	if (strict_strtoul(argv[1], 10, &div) < 0)
+		return CMD_RET_USAGE;
+
+	if (div < 2 || div > 15) {
+		printf("invalid teesys clock divider number(%ld)\n", div);
+		return -EINVAL;
+	}
+
+	cfg = readl(REG_TEESYS_CLK_TEECFG);
+	cfg &= ~TEESYS_I1_HCLK_DIV_EN;
+	writel(cfg, REG_TEESYS_CLK_TEECFG);
+
+	cfg &= ~(TEESYS_I1_HCLK_DIV_NUM_MASK << TEESYS_I1_HCLK_DIV_NUM_SHIFT);
+	cfg |= (div & TEESYS_I1_HCLK_DIV_NUM_MASK) << TEESYS_I1_HCLK_DIV_NUM_SHIFT;
+	cfg |= TEESYS_I1_HCLK_DIV_EN;
+	writel(cfg, REG_TEESYS_CLK_TEECFG);
+
+	return ret;
+}
+
+static int ds_7_alarm_clk_set(cmd_tbl_t *cmdtp, int flag, int argc,
+			      char * const argv[])
+{
+	return ds_3to6_alarm_clk_set(cmdtp, flag, argc, argv);
+}
+
+static int ds_init_cfg(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	if (!global_ds_init) {
+		global_ds_init = true;
+		return ds_init();
+	}
+
+	return 0;
+}
+
+U_BOOT_CMD(ds_init, 1, 0, ds_init_cfg, "ds_init", "Initalize the digital sensor controller");
+U_BOOT_CMD(ds_cpu_alarm, 2, 0, ds_cpu_alarm_clk_set, "ds_cpu_alarm 1500000000", "digital sensor cpu0~cpu3 alarm test");
+U_BOOT_CMD(ds_3to6_alarm, 2, 0, ds_3to6_alarm_clk_set, "ds_3to6_alarm 3", "digital sensor for digital3~digital6 alarm test");
+U_BOOT_CMD(ds_7_alarm, 2, 0, ds_7_alarm_clk_set, "ds_7_alarm 3", "digital sensor for digital7 alarm test");
+

board/thead/light-c910/light.c

@@ -5,6 +5,7 @@
  */
 
 #include <common.h>
+#include <command.h>
 #include <asm/io.h>
 #include <asm/types.h>
 #include <thead/clock_config.h>
@@ -805,7 +806,7 @@ static void light_iopin_init(void)
 	light_pin_cfg(GMAC0_RXD3, PIN_SPEED_NORMAL, PIN_PN, 0xF);
 
 }
-#elif defined   ( CONFIG_TARGET_LIGHT_FM_C910_VAL_B)
+#elif defined ( CONFIG_TARGET_LIGHT_FM_C910_VAL_B) || defined ( CONFIG_TARGET_LIGHT_FM_C910_B_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_B_POWER)
 static void light_iopin_init(void)
 {
 	/* aon-padmux config */
@@ -826,12 +827,25 @@ static void light_iopin_init(void)
 	light_pin_mux(AOGPIO_12,1);
 	light_pin_mux(AOGPIO_13,1);
 	light_pin_mux(AOGPIO_14,0);
+	light_pin_cfg(AOGPIO_14,PIN_SPEED_NORMAL,PIN_PU,2);  ///WL_DEV_WAKE_HOST
 	light_pin_mux(AOGPIO_15,0);
+	light_pin_cfg(AOGPIO_15,PIN_SPEED_NORMAL,PIN_PU,2);  ///BT_DEV_WAKE_HOST
+
+	light_pin_mux(AUDIO_PA4,3);                           ///NC
+	light_pin_cfg(AUDIO_PA4,PIN_SPEED_NORMAL,PIN_PN,2);
+	light_pin_mux(AUDIO_PA5,3);                           ///NC
+	light_pin_cfg(AUDIO_PA5,PIN_SPEED_NORMAL,PIN_PN,2);
+	light_pin_mux(AUDIO_PA11,3);                          ///NC
+	light_pin_cfg(AUDIO_PA11,PIN_SPEED_NORMAL,PIN_PN,2);
+	light_pin_mux(AUDIO_PA16,3);                          ///NC
+	light_pin_cfg(AUDIO_PA16,PIN_SPEED_NORMAL,PIN_PN,2);
 
 	light_pin_mux(AUDIO_PA9,3);
 	light_pin_cfg(AUDIO_PA9,PIN_SPEED_NORMAL,PIN_PU,2);// reset signal for audio-pa
-	light_pin_mux(AUDIO_PA10,3);
-	light_pin_mux(AUDIO_PA12,3);
+	light_pin_mux(AUDIO_PA10,3);                          ///NC
+	light_pin_cfg(AUDIO_PA10,PIN_SPEED_NORMAL,PIN_PN,2);
+	light_pin_mux(AUDIO_PA12,3);                          ///NC
+	light_pin_cfg(AUDIO_PA12,PIN_SPEED_NORMAL,PIN_PN,2);
 	light_pin_mux(AUDIO_PA13,0);
 
 	/*ap-padmux on left/top */
@@ -840,8 +854,8 @@ static void light_iopin_init(void)
 	light_pin_cfg(QSPI1_SCLK,PIN_SPEED_NORMAL,PIN_PN,8);
 	light_pin_cfg(QSPI1_D0_MOSI,PIN_SPEED_NORMAL,PIN_PU,8);
 	light_pin_cfg(QSPI1_D1_MISO,PIN_SPEED_NORMAL,PIN_PU,8);
-	light_pin_cfg(QSPI1_D2_WP,PIN_SPEED_NORMAL,PIN_PU,8);
-	light_pin_cfg(QSPI1_D3_HOLD,PIN_SPEED_NORMAL,PIN_PU,8);
+	light_pin_cfg(QSPI1_D2_WP,PIN_SPEED_NORMAL,PIN_PN,8);
+	light_pin_cfg(QSPI1_D3_HOLD,PIN_SPEED_NORMAL,PIN_PN,8);
 
 	light_pin_cfg(I2C0_SCL,PIN_SPEED_NORMAL,PIN_PN,4);
 	light_pin_cfg(I2C0_SDA,PIN_SPEED_NORMAL,PIN_PN,4);
@@ -871,9 +885,9 @@ static void light_iopin_init(void)
 	light_pin_mux(GPIO0_30,0);
 	light_pin_cfg(GPIO0_20,PIN_SPEED_NORMAL,PIN_PN,2);
 	light_pin_cfg(GPIO0_21,PIN_SPEED_NORMAL,PIN_PN,2);
-	light_pin_cfg(GPIO0_27,PIN_SPEED_NORMAL,PIN_PD,2);//soc_dovdd18_ir_reg
-	light_pin_cfg(GPIO0_28,PIN_SPEED_NORMAL,PIN_PD,2);//soc_avdd25_ir_reg
-	light_pin_cfg(GPIO0_29,PIN_SPEED_NORMAL,PIN_PD,2);//soc_dvdd12_ir_reg
+	light_pin_cfg(GPIO0_27,PIN_SPEED_NORMAL,PIN_PN,2);//soc_dovdd18_ir_reg
+	light_pin_cfg(GPIO0_28,PIN_SPEED_NORMAL,PIN_PN,2);//soc_avdd25_ir_reg
+	light_pin_cfg(GPIO0_29,PIN_SPEED_NORMAL,PIN_PN,2);//soc_dvdd12_ir_reg
 	light_pin_cfg(GPIO0_30,PIN_SPEED_NORMAL,PIN_PU,2);//soc_vdd_3v3_en_reg for uart/gmac/debug_port/hdmi/sd
 
 	light_pin_mux(GPIO1_0,1);
@@ -896,13 +910,21 @@ static void light_iopin_init(void)
 	light_pin_cfg(GPIO1_2,PIN_SPEED_NORMAL,PIN_PN,2);
 	light_pin_cfg(GPIO1_3,PIN_SPEED_NORMAL,PIN_PN,2);
 	light_pin_cfg(GPIO1_4,PIN_SPEED_NORMAL,PIN_PN,2);
-	light_pin_cfg(GPIO1_9,PIN_SPEED_NORMAL,PIN_PD,2); //soc_vdd18_lcd0_en_reg --backup regulator
-	light_pin_cfg(GPIO1_10,PIN_SPEED_NORMAL,PIN_PU,2);//soc_lcd0_bias_en_reg
+#ifndef defined (CONFIG_TARGET_LIGHT_FM_C910_B_POWER)
+	light_pin_cfg(GPIO1_9,PIN_SPEED_NORMAL,PIN_PN,2); //soc_vdd18_lcd0_en_reg --backup regulator
+#else
+	light_pin_cfg(GPIO1_9,PIN_SPEED_NORMAL,PIN_PU,2); //soc_vdd18_lcd0_en_reg
+#endif
+	light_pin_cfg(GPIO1_10,PIN_SPEED_NORMAL,PIN_PN,2);//soc_lcd0_bias_en_reg
 	light_pin_cfg(GPIO1_11,PIN_SPEED_NORMAL,PIN_PN,2);
-	light_pin_cfg(GPIO1_12,PIN_SPEED_NORMAL,PIN_PD,2);//reg_tp_pwr_en --touch pannel
-	light_pin_cfg(GPIO1_13,PIN_SPEED_NORMAL,PIN_PD,2);//soc_dovdd18_rgb_reg
-	light_pin_cfg(GPIO1_14,PIN_SPEED_NORMAL,PIN_PD,2);//soc_dvdd12_rgb_reg
-	light_pin_cfg(GPIO1_15,PIN_SPEED_NORMAL,PIN_PD,2);//soc_avdd28_rgb_reg
+#ifndef defined (CONFIG_TARGET_LIGHT_FM_C910_B_POWER)
+	light_pin_cfg(GPIO1_12,PIN_SPEED_NORMAL,PIN_PN,2);//reg_tp_pwr_en --touch pannel
+#else
+	light_pin_cfg(GPIO1_12,PIN_SPEED_NORMAL,PIN_PU,2);//reg_tp_pwr_en --touch pannel
+#endif
+	light_pin_cfg(GPIO1_13,PIN_SPEED_NORMAL,PIN_PN,2);//soc_dovdd18_rgb_reg
+	light_pin_cfg(GPIO1_14,PIN_SPEED_NORMAL,PIN_PN,2);//soc_dvdd12_rgb_reg
+	light_pin_cfg(GPIO1_15,PIN_SPEED_NORMAL,PIN_PN,2);//soc_avdd28_rgb_reg
 	light_pin_cfg(GPIO1_16,PIN_SPEED_NORMAL,PIN_PN,2);
 	light_pin_cfg(GPIO1_24,PIN_SPEED_NORMAL,PIN_PN,2);
 	light_pin_cfg(GPIO1_25,PIN_SPEED_NORMAL,PIN_PN,2);
@@ -911,7 +933,7 @@ static void light_iopin_init(void)
 	light_pin_mux(CLK_OUT_1,1);
 	light_pin_mux(CLK_OUT_2,3);
 	light_pin_mux(CLK_OUT_3,1);
-	light_pin_cfg(CLK_OUT_2,PIN_SPEED_NORMAL,PIN_PU,2);
+	light_pin_cfg(CLK_OUT_2,PIN_SPEED_NORMAL,PIN_PU,2);///volume key
 
 	/*ap-pdmux on righ/top*/
 	light_pin_mux(QSPI0_SCLK,2);
@@ -931,14 +953,16 @@ static void light_iopin_init(void)
 	light_pin_mux(SPI_MOSI,3);
 	light_pin_mux(SPI_MISO,3);
 	light_pin_mux(SPI_SCLK,3);
-	light_pin_cfg(SPI_SCLK,PIN_SPEED_NORMAL,PIN_PU,2);
+	light_pin_cfg(SPI_SCLK,PIN_SPEED_NORMAL,PIN_PU,2);  ///vdd5v_se_en
 
 	light_pin_mux(GPIO2_18,0);
 	light_pin_mux(GPIO2_19,0);
 	light_pin_mux(GPIO2_20,0);
 	light_pin_mux(GPIO2_21,0);
 	light_pin_mux(GPIO2_22,0);
+	light_pin_cfg(GPIO2_22,PIN_SPEED_NORMAL,PIN_PU,2); ///WL_HOST_WAKE_DEV
 	light_pin_mux(GPIO2_23,0);
+	light_pin_cfg(GPIO2_23,PIN_SPEED_NORMAL,PIN_PU,2); ///BT_DEV_WAKE_HOST
 	light_pin_mux(GPIO2_24,0);
 	light_pin_mux(GPIO2_25,0);
 
@@ -953,20 +977,20 @@ static void light_iopin_init(void)
 
 
 	light_pin_mux(SDIO0_WPRTN,3);
-	light_pin_cfg(SDIO0_WPRTN,PIN_SPEED_NORMAL,PIN_PU,2);
+	light_pin_cfg(SDIO0_WPRTN,PIN_SPEED_NORMAL,PIN_PN,2);///NC
 	light_pin_mux(SDIO1_WPRTN,3);
-	light_pin_cfg(SDIO1_WPRTN,PIN_SPEED_NORMAL,PIN_PU,2);//wcn33_en
+	light_pin_cfg(SDIO1_WPRTN,PIN_SPEED_NORMAL,PIN_PD,2);//gpio2_28 vbus_en
 	light_pin_mux(SDIO1_DETN,3);
-	light_pin_cfg(SDIO1_DETN,PIN_SPEED_NORMAL,PIN_PU,2); //se_5v_en
+	light_pin_cfg(SDIO1_DETN,PIN_SPEED_NORMAL,PIN_PN,2); //gpio2_29 wcn33_en
 
 	light_pin_mux(GPIO2_30,0);
 	light_pin_mux(GPIO2_31,0);
 	light_pin_mux(GPIO3_0,0);
 	light_pin_mux(GPIO3_1,0);
 	light_pin_mux(GPIO3_2,1);
-	light_pin_cfg(GPIO2_30, PIN_SPEED_NORMAL, PIN_PD, 0x2);//soc_avdd28_scan_en_reg
-	light_pin_cfg(GPIO2_31, PIN_SPEED_NORMAL, PIN_PD, 0x2);//soc_dovdd18_scan_reg
-	light_pin_cfg(GPIO3_0, PIN_SPEED_NORMAL, PIN_PD, 0x2); //soc_dvdd12_scan_reg
+	light_pin_cfg(GPIO2_30, PIN_SPEED_NORMAL, PIN_PN, 0x2);//soc_avdd28_scan_en_reg
+	light_pin_cfg(GPIO2_31, PIN_SPEED_NORMAL, PIN_PN, 0x2);//soc_dovdd18_scan_reg
+	light_pin_cfg(GPIO3_0, PIN_SPEED_NORMAL, PIN_PN, 0x2); //soc_dvdd12_scan_reg
 	light_pin_cfg(GPIO3_1, PIN_SPEED_NORMAL, PIN_PN, 0x2);
 	light_pin_cfg(GPIO3_2, PIN_SPEED_NORMAL, PIN_PN, 0xF);
 
@@ -996,8 +1020,8 @@ static void light_iopin_init(void)
 	/* aon-padmux config */
 	light_pin_cfg(I2C_AON_SCL,PIN_SPEED_NORMAL,PIN_PN,8);
 	light_pin_cfg(I2C_AON_SDA,PIN_SPEED_NORMAL,PIN_PN,8);
-	light_pin_cfg(AOGPIO_7,PIN_SPEED_NORMAL,PIN_PU,2);
-	light_pin_cfg(AOGPIO_8,PIN_SPEED_NORMAL,PIN_PU,2);
+	light_pin_cfg(AOGPIO_7,PIN_SPEED_NORMAL,PIN_PN,2);    ///NC
+	light_pin_cfg(AOGPIO_8,PIN_SPEED_NORMAL,PIN_PN,2);    ///NC
 	light_pin_cfg(AOGPIO_9,PIN_SPEED_NORMAL,PIN_PN,2);
 	light_pin_cfg(AOGPIO_10,PIN_SPEED_NORMAL,PIN_PN,2);
 	light_pin_cfg(AOGPIO_11,PIN_SPEED_NORMAL,PIN_PN,2);
@@ -1008,27 +1032,28 @@ static void light_iopin_init(void)
 	light_pin_mux(AOGPIO_9,3);
 	light_pin_mux(AOGPIO_10,3);
 	light_pin_mux(AOGPIO_11,0);
-	light_pin_mux(AOGPIO_12,0);
-	light_pin_mux(AOGPIO_13,0);
+	light_pin_mux(AOGPIO_12,0);                           ///aud-tx
+	light_pin_mux(AOGPIO_13,0);                           ///aud-rx
 	light_pin_mux(AOGPIO_14,0);
 	light_pin_mux(AOGPIO_15,0);
 
+
 	light_pin_mux(AUDIO_PA9,3);
-	light_pin_cfg(AUDIO_PA9,PIN_SPEED_NORMAL,PIN_PU,2);
-	light_pin_mux(AUDIO_PA10,3);
+	light_pin_cfg(AUDIO_PA9,PIN_SPEED_NORMAL,PIN_PN,2);  ///audio-pa-rst
+	light_pin_mux(AUDIO_PA10,3);                         ///aud_3v3_en
 	light_pin_cfg(AUDIO_PA10,PIN_SPEED_NORMAL,PIN_PU,2);
-	light_pin_mux(AUDIO_PA12,3);
+	light_pin_mux(AUDIO_PA12,3);                         ///aud_1v8_en
 	light_pin_cfg(AUDIO_PA12,PIN_SPEED_NORMAL,PIN_PU,2);
 	light_pin_mux(AUDIO_PA13,0);
 
 	/*ap-padmux on left/top */
 	light_pin_mux(QSPI1_CSN0,3);
-	light_pin_cfg(QSPI1_CSN0,PIN_SPEED_NORMAL,PIN_PN,8);
-	light_pin_cfg(QSPI1_SCLK,PIN_SPEED_NORMAL,PIN_PN,8);
-	light_pin_cfg(QSPI1_D0_MOSI,PIN_SPEED_NORMAL,PIN_PU,8);
-	light_pin_cfg(QSPI1_D1_MISO,PIN_SPEED_NORMAL,PIN_PU,8);
-	light_pin_cfg(QSPI1_D2_WP,PIN_SPEED_NORMAL,PIN_PU,8);
-	light_pin_cfg(QSPI1_D3_HOLD,PIN_SPEED_NORMAL,PIN_PU,8);
+	light_pin_cfg(QSPI1_CSN0,PIN_SPEED_NORMAL,PIN_PN,8);     ///se-spi
+	light_pin_cfg(QSPI1_SCLK,PIN_SPEED_NORMAL,PIN_PN,8);     ///se-spi
+	light_pin_cfg(QSPI1_D0_MOSI,PIN_SPEED_NORMAL,PIN_PU,8);  ///se-spi
+	light_pin_cfg(QSPI1_D1_MISO,PIN_SPEED_NORMAL,PIN_PU,8);  ///se-spi
+	light_pin_cfg(QSPI1_D2_WP,PIN_SPEED_NORMAL,PIN_PN,8);    ///uart5-rx
+	light_pin_cfg(QSPI1_D3_HOLD,PIN_SPEED_NORMAL,PIN_PN,8);  ///uart5-tx
 
 	light_pin_cfg(I2C0_SCL,PIN_SPEED_NORMAL,PIN_PN,4);
 	light_pin_cfg(I2C0_SDA,PIN_SPEED_NORMAL,PIN_PN,4);
@@ -1058,10 +1083,10 @@ static void light_iopin_init(void)
 	light_pin_mux(GPIO0_30,0);
 	light_pin_cfg(GPIO0_20,PIN_SPEED_NORMAL,PIN_PN,2);
 	light_pin_cfg(GPIO0_21,PIN_SPEED_NORMAL,PIN_PN,2);
-	light_pin_cfg(GPIO0_27,PIN_SPEED_NORMAL,PIN_PU,2);
-	light_pin_cfg(GPIO0_28,PIN_SPEED_NORMAL,PIN_PU,2);
-	light_pin_cfg(GPIO0_29,PIN_SPEED_NORMAL,PIN_PU,2);
-	light_pin_cfg(GPIO0_30,PIN_SPEED_NORMAL,PIN_PU,2);
+	light_pin_cfg(GPIO0_27,PIN_SPEED_NORMAL,PIN_PN,2); /// NC
+	light_pin_cfg(GPIO0_28,PIN_SPEED_NORMAL,PIN_PN,2); /// AVDD25_IR_EN
+	light_pin_cfg(GPIO0_29,PIN_SPEED_NORMAL,PIN_PN,2); /// DVDD12_IR_EN
+	light_pin_cfg(GPIO0_30,PIN_SPEED_NORMAL,PIN_PN,2); /// vdd-3v3-en (gmac,uart,led)
 
 	light_pin_mux(GPIO1_0,1);
 	light_pin_mux(GPIO1_1,1);
@@ -1086,26 +1111,26 @@ static void light_iopin_init(void)
 	light_pin_cfg(GPIO1_2,PIN_SPEED_NORMAL,PIN_PN,2);
 	light_pin_cfg(GPIO1_3,PIN_SPEED_NORMAL,PIN_PN,2);
 	light_pin_cfg(GPIO1_4,PIN_SPEED_NORMAL,PIN_PN,2);
-	light_pin_cfg(GPIO1_9,PIN_SPEED_NORMAL,PIN_PU,2);
-	light_pin_cfg(GPIO1_10,PIN_SPEED_NORMAL,PIN_PU,2);
-	light_pin_cfg(GPIO1_11,PIN_SPEED_NORMAL,PIN_PN,2);
-	light_pin_cfg(GPIO1_12,PIN_SPEED_NORMAL,PIN_PU,2);
-	light_pin_cfg(GPIO1_13,PIN_SPEED_NORMAL,PIN_PU,2);
-	light_pin_cfg(GPIO1_14,PIN_SPEED_NORMAL,PIN_PU,2);
-	light_pin_cfg(GPIO1_15,PIN_SPEED_NORMAL,PIN_PU,2);
-	light_pin_cfg(GPIO1_16,PIN_SPEED_NORMAL,PIN_PN,2);
+	light_pin_cfg(GPIO1_9,PIN_SPEED_NORMAL,PIN_PN,2);   ///VDD18_LCD0_EN
+	light_pin_cfg(GPIO1_10,PIN_SPEED_NORMAL,PIN_PN,2);  ///LCD0_BIAS_EN
+	light_pin_cfg(GPIO1_11,PIN_SPEED_NORMAL,PIN_PN,2);  /// LCD_ID0
+	light_pin_cfg(GPIO1_12,PIN_SPEED_NORMAL,PIN_PN,2);  /// VDD28_TP0_EN
+	light_pin_cfg(GPIO1_13,PIN_SPEED_NORMAL,PIN_PN,2);  /// DOVDD18_RGB_EN
+	light_pin_cfg(GPIO1_14,PIN_SPEED_NORMAL,PIN_PN,2);  /// DVDD12_RGB_EN
+	light_pin_cfg(GPIO1_15,PIN_SPEED_NORMAL,PIN_PN,2);  /// AVDD28_RGB_EN
+	light_pin_cfg(GPIO1_16,PIN_SPEED_NORMAL,PIN_PN,2);  /// RGBCAM_RESET
 	light_pin_cfg(GPIO1_21,PIN_SPEED_NORMAL,PIN_PN,2);
 	light_pin_cfg(GPIO1_22,PIN_SPEED_NORMAL,PIN_PN,2);
 	light_pin_cfg(GPIO1_23,PIN_SPEED_NORMAL,PIN_PN,2);
 	light_pin_cfg(GPIO1_24,PIN_SPEED_NORMAL,PIN_PN,2);
 	light_pin_cfg(GPIO1_25,PIN_SPEED_NORMAL,PIN_PN,2);
-	light_pin_cfg(GPIO1_26,PIN_SPEED_NORMAL,PIN_PD,2);
+	light_pin_cfg(GPIO1_26,PIN_SPEED_NORMAL,PIN_PN,2);  /// DBB2LEDDRIVER_EN1
 
 	light_pin_mux(CLK_OUT_0,1);
 	light_pin_mux(CLK_OUT_1,1);
 	light_pin_mux(CLK_OUT_3,1);
 	light_pin_mux(CLK_OUT_2,3);
-	light_pin_cfg(CLK_OUT_2,PIN_SPEED_NORMAL,PIN_PU,2);
+	light_pin_cfg(CLK_OUT_2,PIN_SPEED_NORMAL,PIN_PU,2); ///volume key
 
 	/*ap-pdmux on righ/top*/
 	light_pin_mux(QSPI0_SCLK,2);
@@ -1125,7 +1150,7 @@ static void light_iopin_init(void)
 	light_pin_mux(SPI_MOSI,3);
 	light_pin_mux(SPI_MISO,3);
 	light_pin_mux(SPI_SCLK,3);
-	light_pin_cfg(SPI_SCLK,PIN_SPEED_NORMAL,PIN_PU,2);
+	light_pin_cfg(SPI_SCLK,PIN_SPEED_NORMAL,PIN_PN,2); ///NC
 
 	light_pin_mux(GPIO2_18,0);
 	light_pin_mux(GPIO2_19,0);
@@ -1139,19 +1164,215 @@ static void light_iopin_init(void)
 	light_pin_cfg(GPIO2_18,PIN_SPEED_NORMAL,PIN_PN,2);
 	light_pin_cfg(GPIO2_19,PIN_SPEED_NORMAL,PIN_PN,2);
 	light_pin_cfg(GPIO2_20,PIN_SPEED_NORMAL,PIN_PN,2);
-	light_pin_cfg(GPIO2_21,PIN_SPEED_NORMAL,PIN_PU,2);
-	light_pin_cfg(GPIO2_22,PIN_SPEED_NORMAL,PIN_PU,2);
-	light_pin_cfg(GPIO2_23,PIN_SPEED_NORMAL,PIN_PU,2);
-	light_pin_cfg(GPIO2_24,PIN_SPEED_NORMAL,PIN_PU,2);
-	light_pin_cfg(GPIO2_25,PIN_SPEED_NORMAL,PIN_PU,2);
+	light_pin_cfg(GPIO2_21,PIN_SPEED_NORMAL,PIN_PN,2); ///NC
+	light_pin_cfg(GPIO2_22,PIN_SPEED_NORMAL,PIN_PN,2); ///WIFI_BT_GPIO2
+	light_pin_cfg(GPIO2_23,PIN_SPEED_NORMAL,PIN_PN,2); ///WIFI_BT_GPIO3
+	light_pin_cfg(GPIO2_24,PIN_SPEED_NORMAL,PIN_PN,2); ///WIFI_BT_RST_N
+	light_pin_cfg(GPIO2_25,PIN_SPEED_NORMAL,PIN_PU,2); ///KEY1
 
 
 	light_pin_mux(SDIO0_WPRTN,3);
-	light_pin_cfg(SDIO0_WPRTN,PIN_SPEED_NORMAL,PIN_PU,2);
+	light_pin_cfg(SDIO0_WPRTN,PIN_SPEED_NORMAL,PIN_PN,2); ///NC
 	light_pin_mux(SDIO1_WPRTN,3);
-	light_pin_cfg(SDIO1_WPRTN,PIN_SPEED_NORMAL,PIN_PU,2);
+	light_pin_cfg(SDIO1_WPRTN,PIN_SPEED_NORMAL,PIN_PU,2); ///VBUS_EN
 	light_pin_mux(SDIO1_DETN,3);
-	light_pin_cfg(SDIO1_DETN,PIN_SPEED_NORMAL,PIN_PU,2);
+	light_pin_cfg(SDIO1_DETN,PIN_SPEED_NORMAL,PIN_PN,2);  ///WCN33_EN
+
+	light_pin_mux(GPIO2_30,0);
+	light_pin_mux(GPIO2_31,0);
+	light_pin_mux(GPIO3_0,0);
+
+	light_pin_mux(GPIO3_1,0);
+	light_pin_mux(GPIO3_2,1);
+	light_pin_mux(GPIO3_3,0);
+	light_pin_cfg(GPIO2_30, PIN_SPEED_NORMAL, PIN_PN, 0x2); ///NC
+	light_pin_cfg(GPIO2_31, PIN_SPEED_NORMAL, PIN_PN, 0x2); ///NC
+	light_pin_cfg(GPIO3_0, PIN_SPEED_NORMAL, PIN_PN, 0x2);  ///NC
+	light_pin_cfg(GPIO3_1, PIN_SPEED_NORMAL, PIN_PN, 0x2);
+	light_pin_cfg(GPIO3_2, PIN_SPEED_NORMAL, PIN_PN, 0xF);
+	light_pin_cfg(GPIO3_3, PIN_SPEED_NORMAL, PIN_PN, 0x2);  /// WAKEUP_IN_CAT1
+
+	light_pin_mux(GMAC0_COL,3);
+	light_pin_mux(GMAC0_CRS,3);
+	light_pin_cfg(GMAC0_COL,PIN_SPEED_NORMAL,PIN_PU,2);
+	light_pin_cfg(GMAC0_CRS,PIN_SPEED_NORMAL,PIN_PU,2);
+
+	/* GMAC0 pad drive strength configurate to 0xF */
+	light_pin_cfg(GMAC0_TX_CLK, PIN_SPEED_NORMAL, PIN_PN, 0xF);
+	light_pin_cfg(GMAC0_RX_CLK, PIN_SPEED_NORMAL, PIN_PN, 0xF);
+	light_pin_cfg(GMAC0_TXEN, PIN_SPEED_NORMAL, PIN_PN, 0xF);
+	light_pin_cfg(GMAC0_TXD0, PIN_SPEED_NORMAL, PIN_PN, 0xF);
+	light_pin_cfg(GMAC0_TXD1, PIN_SPEED_NORMAL, PIN_PN, 0xF);
+	light_pin_cfg(GMAC0_TXD2, PIN_SPEED_NORMAL, PIN_PN, 0xF);
+	light_pin_cfg(GMAC0_TXD3, PIN_SPEED_NORMAL, PIN_PN, 0xF);
+	light_pin_cfg(GMAC0_RXDV, PIN_SPEED_NORMAL, PIN_PN, 0xF);
+	light_pin_cfg(GMAC0_RXD0, PIN_SPEED_NORMAL, PIN_PN, 0xF);
+	light_pin_cfg(GMAC0_RXD1, PIN_SPEED_NORMAL, PIN_PN, 0xF);
+	light_pin_cfg(GMAC0_RXD2, PIN_SPEED_NORMAL, PIN_PN, 0xF);
+	light_pin_cfg(GMAC0_RXD3, PIN_SPEED_NORMAL, PIN_PN, 0xF);
+}
+#elif defined   (CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_BEAGLE)
+static void light_iopin_init(void)
+{
+	/* aon-padmux config */
+	light_pin_cfg(I2C_AON_SCL,PIN_SPEED_NORMAL,PIN_PN,8);
+	light_pin_cfg(I2C_AON_SDA,PIN_SPEED_NORMAL,PIN_PN,8);
+	light_pin_cfg(AOGPIO_7,PIN_SPEED_NORMAL,PIN_PN,2);     ///NC
+	light_pin_cfg(AOGPIO_8,PIN_SPEED_NORMAL,PIN_PN,2);     ///NC
+	light_pin_cfg(AOGPIO_9,PIN_SPEED_NORMAL,PIN_PN,2);
+	light_pin_cfg(AOGPIO_10,PIN_SPEED_NORMAL,PIN_PN,2);
+	light_pin_cfg(AOGPIO_11,PIN_SPEED_NORMAL,PIN_PN,2);
+	light_pin_cfg(AOGPIO_14,PIN_SPEED_NORMAL,PIN_PN,2);
+	light_pin_cfg(AOGPIO_15,PIN_SPEED_NORMAL,PIN_PN,2);
+	light_pin_mux(AOGPIO_7,3);
+	light_pin_mux(AOGPIO_8,3);
+	light_pin_mux(AOGPIO_9,3);
+	light_pin_mux(AOGPIO_10,3);
+	light_pin_mux(AOGPIO_11,0);
+	light_pin_mux(AOGPIO_12,1);
+	light_pin_mux(AOGPIO_13,1);
+	light_pin_mux(AOGPIO_14,0);
+	light_pin_mux(AOGPIO_15,0);
+
+	light_pin_mux(AUDIO_PA9,3);                         ///AUDIO-PA-RESET
+	light_pin_cfg(AUDIO_PA9,PIN_SPEED_NORMAL,PIN_PN,2);
+	light_pin_mux(AUDIO_PA10,3);                        /// AUD-3V3-EN
+	light_pin_cfg(AUDIO_PA10,PIN_SPEED_NORMAL,PIN_PU,2);
+	light_pin_mux(AUDIO_PA12,3);                        /// AUD-1V8-EN
+	light_pin_cfg(AUDIO_PA12,PIN_SPEED_NORMAL,PIN_PU,2);
+	light_pin_mux(AUDIO_PA13,0);
+
+	/*ap-padmux on left/top */
+	light_pin_mux(QSPI1_CSN0,3);
+	light_pin_cfg(QSPI1_CSN0,PIN_SPEED_NORMAL,PIN_PN,8);  ///se-spi
+	light_pin_cfg(QSPI1_SCLK,PIN_SPEED_NORMAL,PIN_PN,8);  ///se-spi
+	light_pin_cfg(QSPI1_D0_MOSI,PIN_SPEED_NORMAL,PIN_PU,8);  ///se-spi
+	light_pin_cfg(QSPI1_D1_MISO,PIN_SPEED_NORMAL,PIN_PU,8);  ///se-spi
+	light_pin_cfg(QSPI1_D2_WP,PIN_SPEED_NORMAL,PIN_PN,8);    ///NC
+	light_pin_cfg(QSPI1_D3_HOLD,PIN_SPEED_NORMAL,PIN_PN,8);  ///NC
+
+	light_pin_cfg(I2C0_SCL,PIN_SPEED_NORMAL,PIN_PN,4);
+	light_pin_cfg(I2C0_SDA,PIN_SPEED_NORMAL,PIN_PN,4);
+	light_pin_cfg(I2C1_SCL,PIN_SPEED_NORMAL,PIN_PN,4);
+	light_pin_cfg(I2C1_SDA,PIN_SPEED_NORMAL,PIN_PN,4);
+
+	light_pin_mux(UART3_TXD,1);
+	light_pin_mux(UART3_RXD,1);
+	light_pin_cfg(UART3_TXD,PIN_SPEED_NORMAL,PIN_PN,2);
+	light_pin_cfg(UART3_RXD,PIN_SPEED_NORMAL,PIN_PN,2);
+
+	light_pin_mux(GPIO0_18,1);
+	light_pin_mux(GPIO0_19,1);
+	light_pin_cfg(GPIO0_18,PIN_SPEED_NORMAL,PIN_PN,4);
+	light_pin_cfg(GPIO0_19,PIN_SPEED_NORMAL,PIN_PN,4);
+
+	light_pin_mux(GPIO0_20,0);
+	light_pin_mux(GPIO0_21,0);
+	light_pin_mux(GPIO0_22,1);
+	light_pin_mux(GPIO0_23,1);
+	light_pin_mux(GPIO0_24,1);
+	light_pin_mux(GPIO0_25,1);
+	light_pin_mux(GPIO0_26,1);
+	light_pin_mux(GPIO0_27,0);
+	light_pin_mux(GPIO0_28,0);
+	light_pin_mux(GPIO0_29,0);
+	light_pin_mux(GPIO0_30,0);
+	light_pin_cfg(GPIO0_20,PIN_SPEED_NORMAL,PIN_PN,2);
+	light_pin_cfg(GPIO0_21,PIN_SPEED_NORMAL,PIN_PN,2);
+	light_pin_cfg(GPIO0_27,PIN_SPEED_NORMAL,PIN_PN,2);                          ///< NC(not used)
+	light_pin_cfg(GPIO0_28,PIN_SPEED_NORMAL,PIN_PN,2);                          ///< AVDD25_IR_EN
+	light_pin_cfg(GPIO0_29,PIN_SPEED_NORMAL,PIN_PN,2);                          ///< DVDD12_IR_EN
+	light_pin_cfg(GPIO0_30,PIN_SPEED_NORMAL,PIN_PU,2);                          ///< gmac,uart,led
+
+	light_pin_mux(GPIO1_0,1);
+	light_pin_mux(GPIO1_1,1);
+	light_pin_mux(GPIO1_2,1);
+	light_pin_mux(GPIO1_3,1);
+	light_pin_mux(GPIO1_4,1);
+	light_pin_mux(GPIO1_9,0);
+	light_pin_mux(GPIO1_10,0);
+	light_pin_mux(GPIO1_11,0);
+	light_pin_mux(GPIO1_12,0);
+	light_pin_mux(GPIO1_13,0);
+	light_pin_mux(GPIO1_14,0);
+	light_pin_mux(GPIO1_15,0);
+	light_pin_mux(GPIO1_16,0);
+	light_pin_mux(GPIO1_21,3);
+	light_pin_mux(GPIO1_22,3);
+	light_pin_mux(GPIO1_23,3);
+	light_pin_mux(GPIO1_24,3);
+	light_pin_mux(GPIO1_25,3);
+	light_pin_cfg(GPIO1_0,PIN_SPEED_NORMAL,PIN_PN,2);
+	light_pin_cfg(GPIO1_1,PIN_SPEED_NORMAL,PIN_PN,2);
+	light_pin_cfg(GPIO1_2,PIN_SPEED_NORMAL,PIN_PN,2);
+	light_pin_cfg(GPIO1_3,PIN_SPEED_NORMAL,PIN_PN,2);
+	light_pin_cfg(GPIO1_4,PIN_SPEED_NORMAL,PIN_PN,2);
+	light_pin_cfg(GPIO1_9,PIN_SPEED_NORMAL,PIN_PN,2);                          ///<VDD18_LCD0_EN
+	light_pin_cfg(GPIO1_10,PIN_SPEED_NORMAL,PIN_PN,2);                         ///<LCD0_BIAS_EN
+	light_pin_cfg(GPIO1_11,PIN_SPEED_NORMAL,PIN_PN,2);
+	light_pin_cfg(GPIO1_12,PIN_SPEED_NORMAL,PIN_PN,2);                         ///<TOUCH-PANNEL VDD28_TP0_EN
+	light_pin_cfg(GPIO1_13,PIN_SPEED_NORMAL,PIN_PN,2);                         ///<DOVDD18_RGB_EN
+	light_pin_cfg(GPIO1_14,PIN_SPEED_NORMAL,PIN_PN,2);                         ///<DVDD12_RGB_EN
+	light_pin_cfg(GPIO1_15,PIN_SPEED_NORMAL,PIN_PN,2);                         ///<AVDD28_RGB_EN
+	light_pin_cfg(GPIO1_16,PIN_SPEED_NORMAL,PIN_PN,2);
+	light_pin_cfg(GPIO1_21,PIN_SPEED_NORMAL,PIN_PN,2);
+	light_pin_cfg(GPIO1_22,PIN_SPEED_NORMAL,PIN_PN,2);
+	light_pin_cfg(GPIO1_23,PIN_SPEED_NORMAL,PIN_PN,2);                         ///<LED_PDN
+	light_pin_cfg(GPIO1_24,PIN_SPEED_NORMAL,PIN_PN,2);
+	light_pin_cfg(GPIO1_25,PIN_SPEED_NORMAL,PIN_PN,2);
+	light_pin_cfg(GPIO1_26,PIN_SPEED_NORMAL,PIN_PN,2);                         ///<DBB2LEDDRIVER_EN
+
+	light_pin_mux(CLK_OUT_0,1);
+	light_pin_mux(CLK_OUT_1,1);
+	light_pin_mux(CLK_OUT_3,1);
+	light_pin_mux(CLK_OUT_2,3);
+	light_pin_cfg(CLK_OUT_2,PIN_SPEED_NORMAL,PIN_PU,2);                        ///volume key "-"
+
+	/*ap-pdmux on righ/top*/
+	light_pin_mux(QSPI0_SCLK,3);            ///NC
+	light_pin_mux(QSPI0_CSN0,3);            ///NC
+	light_pin_mux(QSPI0_CSN1,3);            ///NC
+	light_pin_mux(QSPI0_D0_MOSI,3);         ///NC
+	light_pin_mux(QSPI0_D1_MISO,3);         ///NC
+	light_pin_mux(QSPI0_D2_WP,3);           ///NC
+	light_pin_mux(QSPI0_D3_HOLD,3);         ///NC
+
+	light_pin_cfg(I2C2_SCL,PIN_SPEED_NORMAL,PIN_PN,4);
+	light_pin_cfg(I2C2_SDA,PIN_SPEED_NORMAL,PIN_PN,4);
+	light_pin_cfg(I2C3_SCL,PIN_SPEED_NORMAL,PIN_PN,4);
+	light_pin_cfg(I2C3_SDA,PIN_SPEED_NORMAL,PIN_PN,4);
+
+	light_pin_mux(SPI_CSN,3);                                                /// W_DISABLE_CATE1
+	light_pin_mux(SPI_MOSI,3);                                               /// NC
+	light_pin_mux(SPI_MISO,3);                                               /// RERST1_N_CAT1
+	light_pin_mux(SPI_SCLK,3);
+	light_pin_cfg(SPI_SCLK,PIN_SPEED_NORMAL,PIN_PN,2);                       /// NC
+
+	light_pin_mux(GPIO2_18,0);
+	light_pin_mux(GPIO2_19,0);
+	light_pin_mux(GPIO2_20,0);
+	light_pin_mux(GPIO2_21,0);
+	light_pin_mux(GPIO2_22,0);
+	light_pin_mux(GPIO2_23,0);
+	light_pin_mux(GPIO2_24,0);
+	light_pin_mux(GPIO2_25,0);
+
+	light_pin_cfg(GPIO2_18,PIN_SPEED_NORMAL,PIN_PN,2);
+	light_pin_cfg(GPIO2_19,PIN_SPEED_NORMAL,PIN_PN,2);
+	light_pin_cfg(GPIO2_20,PIN_SPEED_NORMAL,PIN_PN,2);
+	light_pin_cfg(GPIO2_21,PIN_SPEED_NORMAL,PIN_PN,2);                        ///<NC
+	light_pin_cfg(GPIO2_22,PIN_SPEED_NORMAL,PIN_PN,2);                        ///<WIFI_BT_GPIO2
+	light_pin_cfg(GPIO2_23,PIN_SPEED_NORMAL,PIN_PN,2);                        ///<WIFI_BT_GPIO3
+	light_pin_cfg(GPIO2_24,PIN_SPEED_NORMAL,PIN_PN,2);                        ///<WIFI_BT_RST_N
+	light_pin_cfg(GPIO2_25,PIN_SPEED_NORMAL,PIN_PU,2);                        ///KEY1
+
+
+	light_pin_mux(SDIO0_WPRTN,3);
+	light_pin_cfg(SDIO0_WPRTN,PIN_SPEED_NORMAL,PIN_PN,2);                    ///< NC
+	light_pin_mux(SDIO1_WPRTN,3);
+	light_pin_cfg(SDIO1_WPRTN,PIN_SPEED_NORMAL,PIN_PU,2);                   ///VBUS_EN
+	light_pin_mux(SDIO1_DETN,3);
+	light_pin_cfg(SDIO1_DETN,PIN_SPEED_NORMAL,PIN_PN,2);                    ///WCN_33_EN
 
 	light_pin_mux(GPIO2_30,0);
 	light_pin_mux(GPIO2_31,0);
@@ -1159,9 +1380,9 @@ static void light_iopin_init(void)
 	light_pin_mux(GPIO3_1,0);
 	light_pin_mux(GPIO3_2,1);
 	light_pin_mux(GPIO3_3,0);
-	light_pin_cfg(GPIO2_30, PIN_SPEED_NORMAL, PIN_PU, 0x2);
-	light_pin_cfg(GPIO2_31, PIN_SPEED_NORMAL, PIN_PU, 0x2);
-	light_pin_cfg(GPIO3_0, PIN_SPEED_NORMAL, PIN_PU, 0x2);
+	light_pin_cfg(GPIO2_30, PIN_SPEED_NORMAL, PIN_PN, 0x2);                 ///NC
+	light_pin_cfg(GPIO2_31, PIN_SPEED_NORMAL, PIN_PN, 0x2);                 ///NC
+	light_pin_cfg(GPIO3_0, PIN_SPEED_NORMAL, PIN_PN, 0x2);                  ///NC
 	light_pin_cfg(GPIO3_1, PIN_SPEED_NORMAL, PIN_PN, 0x2);
 	light_pin_cfg(GPIO3_2, PIN_SPEED_NORMAL, PIN_PN, 0xF);
 	light_pin_cfg(GPIO3_3, PIN_SPEED_NORMAL, PIN_PN, 0x2);
@@ -1185,186 +1406,258 @@ static void light_iopin_init(void)
 	light_pin_cfg(GMAC0_RXD2, PIN_SPEED_NORMAL, PIN_PN, 0xF);
 	light_pin_cfg(GMAC0_RXD3, PIN_SPEED_NORMAL, PIN_PN, 0xF);
 }
-#elif defined   (CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_EVT)
+#elif defined (CONFIG_TARGET_LIGHT_FM_C910_LPI4A)
 static void light_iopin_init(void)
 {
 	/* aon-padmux config */
-	light_pin_cfg(I2C_AON_SCL,PIN_SPEED_NORMAL,PIN_PN,8);
-	light_pin_cfg(I2C_AON_SDA,PIN_SPEED_NORMAL,PIN_PN,8);
-	light_pin_cfg(AOGPIO_7,PIN_SPEED_NORMAL,PIN_PU,2);
-	light_pin_cfg(AOGPIO_8,PIN_SPEED_NORMAL,PIN_PU,2);
-	light_pin_cfg(AOGPIO_9,PIN_SPEED_NORMAL,PIN_PN,2);
-	light_pin_cfg(AOGPIO_10,PIN_SPEED_NORMAL,PIN_PN,2);
-	light_pin_cfg(AOGPIO_11,PIN_SPEED_NORMAL,PIN_PN,2);
-	light_pin_cfg(AOGPIO_14,PIN_SPEED_NORMAL,PIN_PN,2);
-	light_pin_cfg(AOGPIO_15,PIN_SPEED_NORMAL,PIN_PN,2);
-	light_pin_mux(AOGPIO_7,3);
-	light_pin_mux(AOGPIO_8,3);
-	light_pin_mux(AOGPIO_9,3);
-	light_pin_mux(AOGPIO_10,3);
-	light_pin_mux(AOGPIO_11,0);
-	light_pin_mux(AOGPIO_12,1);
-	light_pin_mux(AOGPIO_13,1);
-	light_pin_mux(AOGPIO_14,0);
-	light_pin_mux(AOGPIO_15,0);
+	light_pin_cfg(I2C_AON_SCL, PIN_SPEED_NORMAL, PIN_PN, 8);
+	light_pin_cfg(I2C_AON_SDA, PIN_SPEED_NORMAL, PIN_PN, 8);
 
-	light_pin_mux(AUDIO_PA9,3);
-	light_pin_cfg(AUDIO_PA9,PIN_SPEED_NORMAL,PIN_PU,2);
-	light_pin_mux(AUDIO_PA10,3);
-	light_pin_cfg(AUDIO_PA10,PIN_SPEED_NORMAL,PIN_PU,2);
-	light_pin_mux(AUDIO_PA12,3);
-	light_pin_cfg(AUDIO_PA12,PIN_SPEED_NORMAL,PIN_PU,2);
-	light_pin_mux(AUDIO_PA13,0);
+	light_pin_mux(CPU_JTG_TCLK, 3);
+	light_pin_cfg(CPU_JTG_TCLK, PIN_SPEED_NORMAL, PIN_PN, 2);
+	light_pin_mux(CPU_JTG_TMS, 3);
+	light_pin_cfg(CPU_JTG_TMS, PIN_SPEED_NORMAL, PIN_PN, 2);
+	light_pin_mux(CPU_JTG_TDI, 3);
+	light_pin_cfg(CPU_JTG_TDI, PIN_SPEED_NORMAL, PIN_PN, 2);
+
+	light_pin_mux(AOGPIO_7, 1);
+	light_pin_mux(AOGPIO_8, 1);
+	// light_pin_mux(AOGPIO_9, 0);
+	light_pin_mux(AOGPIO_10, 1);
+	light_pin_mux(AOGPIO_11, 1);
+	light_pin_mux(AOGPIO_12, 1);
+	light_pin_mux(AOGPIO_13, 1);
+	light_pin_mux(AOGPIO_14, 0);
+	// light_pin_mux(AOGPIO_15,0);
+	light_pin_cfg(AOGPIO_7, PIN_SPEED_NORMAL, PIN_PN, 2);     ///NC
+	light_pin_cfg(AOGPIO_8, PIN_SPEED_NORMAL, PIN_PN, 2);     ///NC
+	// light_pin_cfg(AOGPIO_9,PIN_SPEED_NORMAL,PIN_PN,2);
+	light_pin_cfg(AOGPIO_10, PIN_SPEED_NORMAL, PIN_PN, 2);
+	light_pin_cfg(AOGPIO_11, PIN_SPEED_NORMAL, PIN_PN, 2);
+	light_pin_cfg(AOGPIO_12, PIN_SPEED_NORMAL, PIN_PN, 2);
+	light_pin_cfg(AOGPIO_13, PIN_SPEED_NORMAL, PIN_PN, 2);
+	light_pin_cfg(AOGPIO_14, PIN_SPEED_NORMAL, PIN_PN, 2);
+	// light_pin_cfg(AOGPIO_15,PIN_SPEED_NORMAL,PIN_PN,2);
+
+	light_pin_mux(AUDIO_PA0, 0);
+	light_pin_cfg(AUDIO_PA0, PIN_SPEED_NORMAL, PIN_PN, 2);
+	light_pin_mux(AUDIO_PA1, 0);
+	light_pin_cfg(AUDIO_PA1, PIN_SPEED_NORMAL, PIN_PN, 2);
+	light_pin_mux(AUDIO_PA3, 0);
+	light_pin_cfg(AUDIO_PA3, PIN_SPEED_NORMAL, PIN_PN, 2);
+	light_pin_mux(AUDIO_PA4, 0);
+	light_pin_cfg(AUDIO_PA4, PIN_SPEED_NORMAL, PIN_PN, 2);
+	light_pin_mux(AUDIO_PA5, 0);
+	light_pin_cfg(AUDIO_PA5, PIN_SPEED_NORMAL, PIN_PN, 2);
+	light_pin_mux(AUDIO_PA6, 0);
+	light_pin_cfg(AUDIO_PA6, PIN_SPEED_NORMAL, PIN_PN, 2);
+	light_pin_mux(AUDIO_PA7, 0);
+	light_pin_cfg(AUDIO_PA7, PIN_SPEED_NORMAL, PIN_PN, 2);
+	light_pin_mux(AUDIO_PA14, 0);
+	light_pin_cfg(AUDIO_PA14, PIN_SPEED_NORMAL, PIN_PN, 2);
+	light_pin_mux(AUDIO_PA15, 0);
+	light_pin_cfg(AUDIO_PA15, PIN_SPEED_NORMAL, PIN_PN, 2);
+	light_pin_mux(AUDIO_PA16, 0);
+	light_pin_cfg(AUDIO_PA16, PIN_SPEED_NORMAL, PIN_PN, 2);
+	light_pin_mux(AUDIO_PA17, 0);
+	light_pin_cfg(AUDIO_PA17, PIN_SPEED_NORMAL, PIN_PN, 2);
+	light_pin_mux(AUDIO_PA29, 0);
+	light_pin_cfg(AUDIO_PA29, PIN_SPEED_NORMAL, PIN_PN, 2);
+	light_pin_mux(AUDIO_PA30, 0);
+	light_pin_cfg(AUDIO_PA30, PIN_SPEED_NORMAL, PIN_PN, 2);
+
+	// light_pin_mux(AUDIO_PA9,3);                         ///AUDIO-PA-RESET
+	// light_pin_cfg(AUDIO_PA9,PIN_SPEED_NORMAL,PIN_PN,2);
+	// light_pin_mux(AUDIO_PA10,3);                        /// AUD-3V3-EN
+	// light_pin_cfg(AUDIO_PA10,PIN_SPEED_NORMAL,PIN_PU,2);
+	// light_pin_mux(AUDIO_PA12,3);                        /// AUD-1V8-EN
+	// light_pin_cfg(AUDIO_PA12,PIN_SPEED_NORMAL,PIN_PU,2);
+	// light_pin_mux(AUDIO_PA13,0);
 
 	/*ap-padmux on left/top */
-	light_pin_mux(QSPI1_CSN0,3);
-	light_pin_cfg(QSPI1_CSN0,PIN_SPEED_NORMAL,PIN_PN,8);
-	light_pin_cfg(QSPI1_SCLK,PIN_SPEED_NORMAL,PIN_PN,8);
-	light_pin_cfg(QSPI1_D0_MOSI,PIN_SPEED_NORMAL,PIN_PU,8);
-	light_pin_cfg(QSPI1_D1_MISO,PIN_SPEED_NORMAL,PIN_PU,8);
-	light_pin_cfg(QSPI1_D2_WP,PIN_SPEED_NORMAL,PIN_PU,8);
-	light_pin_cfg(QSPI1_D3_HOLD,PIN_SPEED_NORMAL,PIN_PU,8);
+	light_pin_mux(QSPI1_SCLK, 4);
+	light_pin_cfg(QSPI1_SCLK, PIN_SPEED_NORMAL,PIN_PN, 8);  ///se-spi
+	light_pin_mux(QSPI1_CSN0, 4);
+	light_pin_cfg(QSPI1_CSN0, PIN_SPEED_NORMAL, PIN_PN, 8);  ///se-spi
+	light_pin_mux(QSPI1_D0_MOSI, 4);
+	light_pin_cfg(QSPI1_D0_MOSI, PIN_SPEED_NORMAL, PIN_PU, 8);  ///se-spi
+	light_pin_mux(QSPI1_D1_MISO, 4);
+	light_pin_cfg(QSPI1_D1_MISO, PIN_SPEED_NORMAL, PIN_PU, 8);  ///se-spi
+	light_pin_mux(QSPI1_D2_WP, 4);
+	light_pin_cfg(QSPI1_D2_WP, PIN_SPEED_NORMAL, PIN_PN, 8);    ///NC
+	// light_pin_mux(QSPI1_D3_HOLD, 4);
+	// light_pin_cfg(QSPI1_D3_HOLD, PIN_SPEED_NORMAL, PIN_PN, 8);  ///NC
 
-	light_pin_cfg(I2C0_SCL,PIN_SPEED_NORMAL,PIN_PN,4);
-	light_pin_cfg(I2C0_SDA,PIN_SPEED_NORMAL,PIN_PN,4);
-	light_pin_cfg(I2C1_SCL,PIN_SPEED_NORMAL,PIN_PN,4);
-	light_pin_cfg(I2C1_SDA,PIN_SPEED_NORMAL,PIN_PN,4);
+	light_pin_cfg(I2C0_SCL, PIN_SPEED_NORMAL, PIN_PN, 4);
+	light_pin_cfg(I2C0_SDA, PIN_SPEED_NORMAL, PIN_PN, 4);
+	light_pin_cfg(I2C1_SCL, PIN_SPEED_NORMAL, PIN_PN, 4);
+	light_pin_cfg(I2C1_SDA, PIN_SPEED_NORMAL, PIN_PN, 4);
 
-	light_pin_mux(UART3_TXD,1);
-	light_pin_mux(UART3_RXD,1);
-	light_pin_cfg(UART3_TXD,PIN_SPEED_NORMAL,PIN_PN,2);
-	light_pin_cfg(UART3_RXD,PIN_SPEED_NORMAL,PIN_PN,2);
+	light_pin_cfg(UART1_TXD, PIN_SPEED_NORMAL, PIN_PN, 2);
+	light_pin_cfg(UART1_RXD, PIN_SPEED_NORMAL, PIN_PN, 2);
+	light_pin_cfg(UART4_TXD, PIN_SPEED_NORMAL, PIN_PN, 2);
+	light_pin_cfg(UART4_RXD, PIN_SPEED_NORMAL, PIN_PN, 2);
+	light_pin_cfg(UART4_CTSN, PIN_SPEED_NORMAL, PIN_PN, 2);
+	light_pin_cfg(UART4_RTSN, PIN_SPEED_NORMAL, PIN_PN, 2);
+	light_pin_mux(UART3_TXD, 1);
+	light_pin_cfg(UART3_TXD, PIN_SPEED_NORMAL, PIN_PN, 2);
+	light_pin_mux(UART3_RXD, 1);
+	light_pin_cfg(UART3_RXD, PIN_SPEED_NORMAL, PIN_PN, 2);
 
-	light_pin_mux(GPIO0_18,1);
-	light_pin_mux(GPIO0_19,1);
-	light_pin_cfg(GPIO0_18,PIN_SPEED_NORMAL,PIN_PN,4);
-	light_pin_cfg(GPIO0_19,PIN_SPEED_NORMAL,PIN_PN,4);
+	// light_pin_mux(GPIO0_18,1);
+	// light_pin_mux(GPIO0_19,1);
+	// light_pin_cfg(GPIO0_18,PIN_SPEED_NORMAL,PIN_PN,4);
+	// light_pin_cfg(GPIO0_19,PIN_SPEED_NORMAL,PIN_PN,4);
 
-	light_pin_mux(GPIO0_20,0);
-	light_pin_mux(GPIO0_21,0);
-	light_pin_mux(GPIO0_22,1);
-	light_pin_mux(GPIO0_23,1);
-	light_pin_mux(GPIO0_24,1);
-	light_pin_mux(GPIO0_25,1);
-	light_pin_mux(GPIO0_26,1);
-	light_pin_mux(GPIO0_27,0);
-	light_pin_mux(GPIO0_28,0);
-	light_pin_mux(GPIO0_29,0);
-	light_pin_mux(GPIO0_30,0);
-	light_pin_cfg(GPIO0_20,PIN_SPEED_NORMAL,PIN_PN,2);
-	light_pin_cfg(GPIO0_21,PIN_SPEED_NORMAL,PIN_PN,2);
-	light_pin_cfg(GPIO0_27,PIN_SPEED_NORMAL,PIN_PD,2);                          ///< NC(not used)
-	light_pin_cfg(GPIO0_28,PIN_SPEED_NORMAL,PIN_PD,2);                          ///<AVDD25_IR_EN
-	light_pin_cfg(GPIO0_29,PIN_SPEED_NORMAL,PIN_PD,2);                          ///<DVDD12_IR_EN
-	light_pin_cfg(GPIO0_30,PIN_SPEED_NORMAL,PIN_PU,2);
+	// light_pin_mux(GPIO0_20,0);
+	// light_pin_mux(GPIO0_21,0);
+	// light_pin_mux(GPIO0_22,1);
+	// light_pin_mux(GPIO0_23,1);
+	// light_pin_mux(GPIO0_24,1);
+	// light_pin_mux(GPIO0_25,1);
+	// light_pin_mux(GPIO0_26,1);
+	// light_pin_mux(GPIO0_27,0);
+	// light_pin_mux(GPIO0_28,0);
+	// light_pin_mux(GPIO0_29,0);
+	// light_pin_mux(GPIO0_30,0);
+	// light_pin_cfg(GPIO0_20,PIN_SPEED_NORMAL,PIN_PN,2);
+	// light_pin_cfg(GPIO0_21,PIN_SPEED_NORMAL,PIN_PN,2);
+	light_pin_cfg(GPIO0_24, PIN_SPEED_NORMAL, PIN_PN, 2);
+	light_pin_cfg(GPIO0_25, PIN_SPEED_NORMAL, PIN_PN, 2);
+	light_pin_cfg(GPIO0_27, PIN_SPEED_NORMAL, PIN_PN, 2);                          ///< NC(not used)
+	light_pin_cfg(GPIO0_28, PIN_SPEED_NORMAL, PIN_PN, 2);                          ///< AVDD25_IR_EN
+	// light_pin_cfg(GPIO0_29,PIN_SPEED_NORMAL,PIN_PN,2);                          ///< DVDD12_IR_EN
+	light_pin_cfg(GPIO0_30, PIN_SPEED_NORMAL, PIN_PU, 2);                          ///< gmac,uart,led
+	light_pin_cfg(GPIO0_31, PIN_SPEED_NORMAL, PIN_PN, 2);
 
-	light_pin_mux(GPIO1_0,1);
-	light_pin_mux(GPIO1_1,1);
-	light_pin_mux(GPIO1_2,1);
-	light_pin_mux(GPIO1_3,1);
-	light_pin_mux(GPIO1_4,1);
-	light_pin_mux(GPIO1_9,0);
-	light_pin_mux(GPIO1_10,0);
-	light_pin_mux(GPIO1_11,0);
-	light_pin_mux(GPIO1_12,0);
-	light_pin_mux(GPIO1_13,0);
-	light_pin_mux(GPIO1_14,0);
-	light_pin_mux(GPIO1_15,0);
-	light_pin_mux(GPIO1_16,0);
-	light_pin_mux(GPIO1_21,3);
-	light_pin_mux(GPIO1_22,3);
-	light_pin_mux(GPIO1_23,3);
-	light_pin_mux(GPIO1_24,3);
-	light_pin_mux(GPIO1_25,3);
-	light_pin_cfg(GPIO1_0,PIN_SPEED_NORMAL,PIN_PN,2);
-	light_pin_cfg(GPIO1_1,PIN_SPEED_NORMAL,PIN_PN,2);
-	light_pin_cfg(GPIO1_2,PIN_SPEED_NORMAL,PIN_PN,2);
-	light_pin_cfg(GPIO1_3,PIN_SPEED_NORMAL,PIN_PN,2);
-	light_pin_cfg(GPIO1_4,PIN_SPEED_NORMAL,PIN_PN,2);
-	light_pin_cfg(GPIO1_9,PIN_SPEED_NORMAL,PIN_PD,2);                          ///<VDD18_LCD0_EN
-	light_pin_cfg(GPIO1_10,PIN_SPEED_NORMAL,PIN_PD,2);                         ///<LCD0_BIAS_EN
-	light_pin_cfg(GPIO1_11,PIN_SPEED_NORMAL,PIN_PN,2);
-	light_pin_cfg(GPIO1_12,PIN_SPEED_NORMAL,PIN_PD,2);                         ///<TOUCH-PANNEL VDD28_TP0_EN
-	light_pin_cfg(GPIO1_13,PIN_SPEED_NORMAL,PIN_PD,2);                         ///<DOVDD18_RGB_EN
-	light_pin_cfg(GPIO1_14,PIN_SPEED_NORMAL,PIN_PD,2);                         ///<DVDD12_RGB_EN
-	light_pin_cfg(GPIO1_15,PIN_SPEED_NORMAL,PIN_PD,2);                         ///<AVDD28_RGB_EN
-	light_pin_cfg(GPIO1_16,PIN_SPEED_NORMAL,PIN_PN,2);
-	light_pin_cfg(GPIO1_21,PIN_SPEED_NORMAL,PIN_PN,2);
-	light_pin_cfg(GPIO1_22,PIN_SPEED_NORMAL,PIN_PN,2);
-	light_pin_cfg(GPIO1_23,PIN_SPEED_NORMAL,PIN_PD,2);                         ///<LED_PDN
-	light_pin_cfg(GPIO1_24,PIN_SPEED_NORMAL,PIN_PN,2);
-	light_pin_cfg(GPIO1_25,PIN_SPEED_NORMAL,PIN_PN,2);
-	light_pin_cfg(GPIO1_26,PIN_SPEED_NORMAL,PIN_PD,2);                         ///<DBB2LEDDRIVER_EN
+	light_pin_mux(GPIO1_0, 0);
+	// light_pin_mux(GPIO1_1,1);
+	// light_pin_mux(GPIO1_2,1);
+	light_pin_mux(GPIO1_3, 0);
+	light_pin_mux(GPIO1_4, 0);
+	light_pin_mux(GPIO1_5, 0);
+	light_pin_mux(GPIO1_6, 0);
+	light_pin_mux(GPIO1_9, 0);
+	light_pin_mux(GPIO1_10, 0);
+	// light_pin_mux(GPIO1_11,0);
+	// light_pin_mux(GPIO1_12,0);
+	light_pin_mux(GPIO1_13, 0);
+	light_pin_mux(GPIO1_14, 0);
+	// light_pin_mux(GPIO1_15,0);
+	// light_pin_mux(GPIO1_16,0);
+	light_pin_cfg(GPIO1_0, PIN_SPEED_NORMAL, PIN_PN, 2);
+	// light_pin_cfg(GPIO1_1,PIN_SPEED_NORMAL,PIN_PN,2);
+	// light_pin_cfg(GPIO1_2,PIN_SPEED_NORMAL,PIN_PN,2);
+	light_pin_cfg(GPIO1_3, PIN_SPEED_NORMAL, PIN_PN, 2);
+	light_pin_cfg(GPIO1_4, PIN_SPEED_NORMAL, PIN_PN, 2);
+	light_pin_cfg(GPIO1_5, PIN_SPEED_NORMAL, PIN_PN, 2);
+	light_pin_cfg(GPIO1_6, PIN_SPEED_NORMAL, PIN_PN, 2);
+	light_pin_cfg(GPIO1_9, PIN_SPEED_NORMAL, PIN_PN, 2);                          ///<VDD18_LCD0_EN
+	light_pin_cfg(GPIO1_10, PIN_SPEED_NORMAL, PIN_PN, 2);                         ///<LCD0_BIAS_EN
+	// light_pin_cfg(GPIO1_11,PIN_SPEED_NORMAL,PIN_PN,2);
+	// light_pin_cfg(GPIO1_12,PIN_SPEED_NORMAL,PIN_PN,2);                         ///<TOUCH-PANNEL VDD28_TP0_EN
+	light_pin_cfg(GPIO1_13, PIN_SPEED_NORMAL, PIN_PN, 2);                         ///<DOVDD18_RGB_EN
+	light_pin_cfg(GPIO1_14, PIN_SPEED_NORMAL, PIN_PN, 2);                         ///<DVDD12_RGB_EN
+	// light_pin_cfg(GPIO1_15,PIN_SPEED_NORMAL,PIN_PN,2);                         ///<AVDD28_RGB_EN
+	// light_pin_cfg(GPIO1_16,PIN_SPEED_NORMAL,PIN_PN,2);
 
-	light_pin_mux(CLK_OUT_0,1);
-	light_pin_mux(CLK_OUT_1,1);
-	light_pin_mux(CLK_OUT_3,1);
-	light_pin_mux(CLK_OUT_2,3);
-	light_pin_cfg(CLK_OUT_2,PIN_SPEED_NORMAL,PIN_PU,2);
+	light_pin_mux(CLK_OUT_0, 1);
+	light_pin_cfg(CLK_OUT_0, PIN_SPEED_NORMAL, PIN_PU, 2);
+	light_pin_mux(CLK_OUT_1, 1);
+	light_pin_cfg(CLK_OUT_1, PIN_SPEED_NORMAL, PIN_PU, 2);
+	light_pin_mux(CLK_OUT_2, 0);
+	light_pin_cfg(CLK_OUT_2, PIN_SPEED_NORMAL, PIN_PU, 2);
+	light_pin_mux(CLK_OUT_3, 0);
+	light_pin_cfg(CLK_OUT_3, PIN_SPEED_NORMAL, PIN_PU, 2);    
+
+	// light_pin_mux(GPIO1_21,3);
+	light_pin_mux(GPIO1_22, 3);
+	// light_pin_mux(GPIO1_23,3);
+	light_pin_mux(GPIO1_24, 3);
+	// light_pin_mux(GPIO1_25,3);
+	// light_pin_mux(GPIO1_26,3);
+	// light_pin_mux(GPIO1_27,3);
+	light_pin_mux(GPIO1_28, 0);
+	// light_pin_mux(GPIO1_29,3);
+	light_pin_mux(GPIO1_30, 0);
+	// light_pin_cfg(GPIO1_21,PIN_SPEED_NORMAL,PIN_PN,2);
+	light_pin_cfg(GPIO1_22, PIN_SPEED_NORMAL, PIN_PN,2);
+	// light_pin_cfg(GPIO1_23,PIN_SPEED_NORMAL,PIN_PN,2);                         ///<LED_PDN
+	light_pin_cfg(GPIO1_24, PIN_SPEED_NORMAL, PIN_PN, 2);
+	light_pin_cfg(GPIO1_28, PIN_SPEED_NORMAL, PIN_PN, 2);
+	light_pin_cfg(GPIO1_30, PIN_SPEED_NORMAL, PIN_PN, 2);                         ///<DBB2LEDDRIVER_EN
+
+	light_pin_cfg(UART0_TXD, PIN_SPEED_NORMAL, PIN_PN, 2);
+	light_pin_cfg(UART0_RXD, PIN_SPEED_NORMAL, PIN_PN, 2);            
 
 	/*ap-pdmux on righ/top*/
-	light_pin_mux(QSPI0_SCLK,2);
-	light_pin_mux(QSPI0_CSN0,2);
-	light_pin_mux(QSPI0_CSN1,2);
-	light_pin_mux(QSPI0_D0_MOSI,2);
-	light_pin_mux(QSPI0_D1_MISO,2);
-	light_pin_mux(QSPI0_D2_WP,2);
-	light_pin_mux(QSPI0_D3_HOLD,2);
+	// light_pin_mux(QSPI0_SCLK,3);            ///NC
+	// light_pin_mux(QSPI0_CSN0,3);            ///NC
+	// light_pin_mux(QSPI0_CSN1,3);            ///NC
+	// light_pin_mux(QSPI0_D0_MOSI,3);         ///NC
+	// light_pin_mux(QSPI0_D1_MISO,3);         ///NC
+	// light_pin_mux(QSPI0_D2_WP,3);           ///NC
+	// light_pin_mux(QSPI0_D3_HOLD,3);         ///NC
 
-	light_pin_cfg(I2C2_SCL,PIN_SPEED_NORMAL,PIN_PN,4);
-	light_pin_cfg(I2C2_SDA,PIN_SPEED_NORMAL,PIN_PN,4);
-	light_pin_cfg(I2C3_SCL,PIN_SPEED_NORMAL,PIN_PN,4);
-	light_pin_cfg(I2C3_SDA,PIN_SPEED_NORMAL,PIN_PN,4);
+	light_pin_cfg(I2C2_SCL, PIN_SPEED_NORMAL, PIN_PN, 4);
+	light_pin_cfg(I2C2_SDA, PIN_SPEED_NORMAL, PIN_PN, 4);
+	light_pin_cfg(I2C3_SCL, PIN_SPEED_NORMAL, PIN_PN, 4);
+	light_pin_cfg(I2C3_SDA, PIN_SPEED_NORMAL, PIN_PN, 4);
 
-	light_pin_mux(SPI_CSN,3);
-	light_pin_mux(SPI_MOSI,3);
-	light_pin_mux(SPI_MISO,3);
-	light_pin_mux(SPI_SCLK,3);
-	light_pin_cfg(SPI_SCLK,PIN_SPEED_NORMAL,PIN_PU,2);
+	// light_pin_mux(SPI_CSN,3);                                                /// W_DISABLE_CATE1
+	// light_pin_mux(SPI_MOSI,3);                                               /// NC
+	// light_pin_mux(SPI_MISO,3);                                               /// RERST1_N_CAT1
+	// light_pin_mux(SPI_SCLK,3);
+	light_pin_cfg(SPI_CSN, PIN_SPEED_NORMAL, PIN_PN, 2);
+	light_pin_cfg(SPI_MOSI, PIN_SPEED_NORMAL, PIN_PN, 2);
+	light_pin_cfg(SPI_MISO, PIN_SPEED_NORMAL, PIN_PN, 2);
+	light_pin_cfg(SPI_SCLK, PIN_SPEED_NORMAL, PIN_PN, 2);
 
-	light_pin_mux(GPIO2_18,0);
-	light_pin_mux(GPIO2_19,0);
-	light_pin_mux(GPIO2_20,0);
-	light_pin_mux(GPIO2_21,0);
-	light_pin_mux(GPIO2_22,0);
-	light_pin_mux(GPIO2_23,0);
-	light_pin_mux(GPIO2_24,0);
-	light_pin_mux(GPIO2_25,0);
+	light_pin_mux(GPIO2_13, 0);
+	light_pin_mux(GPIO2_18, 1);
+	light_pin_mux(GPIO2_19, 1);
+	light_pin_mux(GPIO2_20, 1);
+	light_pin_mux(GPIO2_21, 1);
+	light_pin_mux(GPIO2_22, 1);
+	light_pin_mux(GPIO2_23, 1);
+	light_pin_mux(GPIO2_24, 1);
+	light_pin_mux(GPIO2_25, 1);
 
-	light_pin_cfg(GPIO2_18,PIN_SPEED_NORMAL,PIN_PN,2);
-	light_pin_cfg(GPIO2_19,PIN_SPEED_NORMAL,PIN_PN,2);
-	light_pin_cfg(GPIO2_20,PIN_SPEED_NORMAL,PIN_PN,2);
-	light_pin_cfg(GPIO2_21,PIN_SPEED_NORMAL,PIN_PD,2);                        ///<NC(not-connected)
-	light_pin_cfg(GPIO2_22,PIN_SPEED_NORMAL,PIN_PU,2);
-	light_pin_cfg(GPIO2_23,PIN_SPEED_NORMAL,PIN_PU,2);
-	light_pin_cfg(GPIO2_24,PIN_SPEED_NORMAL,PIN_PU,2);
-	light_pin_cfg(GPIO2_25,PIN_SPEED_NORMAL,PIN_PU,2);
+	light_pin_cfg(GPIO2_13, PIN_SPEED_NORMAL, PIN_PN, 2);
+	light_pin_cfg(GPIO2_18, PIN_SPEED_NORMAL, PIN_PN, 0xF);
+	light_pin_cfg(GPIO2_19, PIN_SPEED_NORMAL, PIN_PN, 0xF);
+	light_pin_cfg(GPIO2_20, PIN_SPEED_NORMAL, PIN_PN, 0xF);
+	light_pin_cfg(GPIO2_21, PIN_SPEED_NORMAL, PIN_PN, 0xF);                        ///<NC
+	light_pin_cfg(GPIO2_22, PIN_SPEED_NORMAL, PIN_PN, 0xF);                        ///<WIFI_BT_GPIO2
+	light_pin_cfg(GPIO2_23, PIN_SPEED_NORMAL, PIN_PN, 0xF);                        ///<WIFI_BT_GPIO3
+	light_pin_cfg(GPIO2_24, PIN_SPEED_NORMAL, PIN_PN, 0xF);                        ///<WIFI_BT_RST_N
+	light_pin_cfg(GPIO2_25, PIN_SPEED_NORMAL, PIN_PU, 0xF);                        ///KEY1
 
+	light_pin_mux(SDIO0_DETN, 0);
+	light_pin_cfg(SDIO0_DETN, PIN_SPEED_NORMAL, PIN_PN, 2);
+	// light_pin_mux(SDIO0_WPRTN,3);
+	// light_pin_cfg(SDIO0_WPRTN,PIN_SPEED_NORMAL,PIN_PN,2);                    ///< NC
+	// light_pin_mux(SDIO1_WPRTN,3);
+	// light_pin_cfg(SDIO1_WPRTN,PIN_SPEED_NORMAL,PIN_PU,2);                   ///VBUS_EN
+	// light_pin_mux(SDIO1_DETN,3);
+	// light_pin_cfg(SDIO1_DETN,PIN_SPEED_NORMAL,PIN_PN,2);                    ///WCN_33_EN
 
-	light_pin_mux(SDIO0_WPRTN,3);
-	light_pin_cfg(SDIO0_WPRTN,PIN_SPEED_NORMAL,PIN_PU,2);
-	light_pin_mux(SDIO1_WPRTN,3);
-	light_pin_cfg(SDIO1_WPRTN,PIN_SPEED_NORMAL,PIN_PU,2);
-	light_pin_mux(SDIO1_DETN,3);
-	light_pin_cfg(SDIO1_DETN,PIN_SPEED_NORMAL,PIN_PU,2);
-
-	light_pin_mux(GPIO2_30,0);
-	light_pin_mux(GPIO2_31,0);
-	light_pin_mux(GPIO3_0,0);
-	light_pin_mux(GPIO3_1,0);
-	light_pin_mux(GPIO3_2,1);
-	light_pin_mux(GPIO3_3,0);
-	light_pin_cfg(GPIO2_30, PIN_SPEED_NORMAL, PIN_PU, 0x2);
-	light_pin_cfg(GPIO2_31, PIN_SPEED_NORMAL, PIN_PU, 0x2);
-	light_pin_cfg(GPIO3_0, PIN_SPEED_NORMAL, PIN_PU, 0x2);
-	light_pin_cfg(GPIO3_1, PIN_SPEED_NORMAL, PIN_PN, 0x2);
+	light_pin_mux(GPIO2_30, 1);
+	light_pin_mux(GPIO2_31, 1);
+	light_pin_mux(GPIO3_0, 1);
+	light_pin_mux(GPIO3_1, 1);
+	light_pin_mux(GPIO3_2, 1);
+	light_pin_mux(GPIO3_3, 1);
+	light_pin_cfg(GPIO2_30, PIN_SPEED_NORMAL, PIN_PN, 0xF);                 ///NC
+	light_pin_cfg(GPIO2_31, PIN_SPEED_NORMAL, PIN_PN, 0xF);                 ///NC
+	light_pin_cfg(GPIO3_0, PIN_SPEED_NORMAL, PIN_PN, 0xF);                  ///NC
+	light_pin_cfg(GPIO3_1, PIN_SPEED_NORMAL, PIN_PN, 0xF);
 	light_pin_cfg(GPIO3_2, PIN_SPEED_NORMAL, PIN_PN, 0xF);
-	light_pin_cfg(GPIO3_3, PIN_SPEED_NORMAL, PIN_PN, 0x2);
+	light_pin_cfg(GPIO3_3, PIN_SPEED_NORMAL, PIN_PN, 0xF);
 
-	light_pin_mux(GMAC0_COL,3);
-	light_pin_mux(GMAC0_CRS,3);
-	light_pin_cfg(GMAC0_COL,PIN_SPEED_NORMAL,PIN_PU,2);
-	light_pin_cfg(GMAC0_CRS,PIN_SPEED_NORMAL,PIN_PU,2);
+	light_pin_cfg(HDMI_SCL, PIN_SPEED_NORMAL, PIN_PN, 0x2);
+	light_pin_cfg(HDMI_SDA, PIN_SPEED_NORMAL, PIN_PN, 0x2);
+	light_pin_cfg(HDMI_CEC, PIN_SPEED_NORMAL, PIN_PN, 0x2);
 
 	/* GMAC0 pad drive strength configurate to 0xF */
 	light_pin_cfg(GMAC0_TX_CLK, PIN_SPEED_NORMAL, PIN_PN, 0xF);
@@ -1379,6 +1672,13 @@ static void light_iopin_init(void)
 	light_pin_cfg(GMAC0_RXD1, PIN_SPEED_NORMAL, PIN_PN, 0xF);
 	light_pin_cfg(GMAC0_RXD2, PIN_SPEED_NORMAL, PIN_PN, 0xF);
 	light_pin_cfg(GMAC0_RXD3, PIN_SPEED_NORMAL, PIN_PN, 0xF);
+	// light_pin_cfg(GMAC0_MDC, PIN_SPEED_NORMAL, PIN_PN, 0xF);
+	// light_pin_cfg(GMAC0_MDIO, PIN_SPEED_NORMAL, PIN_PN, 0xF);
+
+	light_pin_mux(GMAC0_COL, 3);
+	light_pin_mux(GMAC0_CRS, 3);
+	light_pin_cfg(GMAC0_COL, PIN_SPEED_NORMAL, PIN_PU, 2);
+	light_pin_cfg(GMAC0_CRS, PIN_SPEED_NORMAL, PIN_PU, 2);
 }
 #else
 static void light_iopin_init(void)
@@ -1557,7 +1857,9 @@ int board_init(void)
 static void light_usb_boot_check(void)
 {
 	int boot_mode;
-
+	uchar env_enetaddr[6]={0};
+	uchar env_enet1addr[6]={0};
+	int env_ethaddr_flag,env_eth1addr_flag;
 	boot_mode = readl((void *)SOC_OM_ADDRBASE) & 0x7;
 	if (boot_mode & BIT(2))
 		return;
@@ -1565,8 +1867,26 @@ static void light_usb_boot_check(void)
 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
 	env_set("usb_fastboot", "yes");
 #endif
+	/*Get this version ethaddr(mac addr) env,which follows one board, trans to next version env*/
+	env_ethaddr_flag  = eth_env_get_enetaddr_by_index("eth", 0, env_enetaddr);
+	env_eth1addr_flag = eth_env_get_enetaddr_by_index("eth", 1, env_enet1addr);
 
 	run_command("env default -a -f", 0);
+	/*If mac addr in last version env  is valid, before save,inherit env mac addr */
+	if(env_ethaddr_flag){
+		eth_env_set_enetaddr_by_index("eth", 0, env_enetaddr);
+		run_command("printenv ethaddr",0);
+	}else{
+		printf("env ethaddr not exist or invalid\n");
+	}
+
+	if(env_eth1addr_flag){
+		eth_env_set_enetaddr_by_index("eth", 1, env_enet1addr);
+		run_command("printenv eth1addr",0);
+	}else{
+		printf("env eth1addr not exist or invalid\n");
+	}
+
 	run_command("env save", 0);
 	run_command("run gpt_partition", 0);
 	run_command("fastboot usb 0", 0);
@@ -1587,3 +1907,30 @@ int board_late_init(void)
 	ap_peri_clk_disable();
 	return 0;
 }
+
+static int do_env_ethaddr_check(cmd_tbl_t *cmdtp, int flag, int argc,
+		       char * const argv[])
+{
+	uchar env_enetaddr[6]={0};
+	int i;
+	for(i=0;i<2;i++){
+		if(eth_env_get_enetaddr_by_index("eth", i, env_enetaddr)){
+			printf("env (eth%d) MAC address ok- %pM\n",i, env_enetaddr);
+		}
+		else {
+			printf("env (eth%d) MAC address invalid - %pM\n",i, env_enetaddr);
+			printf(" * Check that the Ethernet address (MAC) is not 00:00:00:00:00:00,\n"
+				   " is not a multicast address(first byte low bit zero is not multi addr), \n"
+					"and is not FF:FF:FF:FF:FF:FF.\n");
+		}
+
+	}
+	return 0;
+
+}
+
+U_BOOT_CMD(
+	chk_ethaddr, 2, 0,	do_env_ethaddr_check,
+	"check ethaddrs in environment variables is valid",
+	""
+);

board/thead/light-c910/lpddr-regu/ddr_regu.c

@@ -136,9 +136,9 @@ static const struct regulator_t g_apcpu_regu_id_list[] = {
 		REGU_ID_DEF(IIC_IDX_AONIIC,APCPU_REGU_VDDM,0x31,0x39,0,1,800000,600000,3500000,12500,1),
 	},
 };
-#elif defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_EVT)
+#elif defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_A_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_B_REF) || (CONFIG_TARGET_LIGHT_FM_C910_BEAGLE) || defined (CONFIG_TARGET_LIGHT_FM_C910_LPI4A)
 /**
- * board for ant-evt
+ * board for ant-ref
  *
  */
 static const struct regulator_t g_regu_id_list[] = {
@@ -817,13 +817,14 @@ int pmic_ddr_regu_init(void)
 
 int pmic_ddr_set_voltage(void)
 {
-	int ret = -1;
+	int ret = 0;
 	uint32_t val = 0;
 	uint32_t regu_num = ARRAY_SIZE(g_regu_id_list);
 	uint32_t i;
 	struct regulator_t *pregu;
 	csi_iic_t          *dev_handle;
 
+#if 0 //currently,no need to modify ddr regulator voltage
 	pregu = (struct regulator_t*)g_regu_id_list;
 	for (i = 0; i < regu_num; i++, pregu++) {
 		if (pregu->regu_vol_target < pregu->regu_vol_min || pregu->regu_vol_target > pregu->regu_vol_max)
@@ -834,6 +835,8 @@ int pmic_ddr_set_voltage(void)
 		if (ret)
 			return ret;
 	}
+#endif
+
 #if defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_B)
 	/*enable lcd0_en ldo*/
 	pregu = (struct regulator_t*)&g_regu_id_list[LCD0_EN];
@@ -941,7 +944,7 @@ int pmic_reset_apcpu_voltage(void)
 		return ret;
 	return 0;
 }
-#elif defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_EVT)
+#elif defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_A_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_B_REF)|| (CONFIG_TARGET_LIGHT_FM_C910_BEAGLE) || defined (CONFIG_TARGET_LIGHT_FM_C910_LPI4A)
 int pmic_reset_apcpu_voltage(void)
 {
 	int                ret = -1;

board/thead/light-c910/sec_check.c

@@ -180,16 +180,7 @@ err:
 	return CMD_RET_FAILURE;
 }
 
-U_BOOT_CMD(
-	efuse, CONFIG_SYS_MAXARGS, 0, do_fuse,
-	"eFuse sub-system",
-	"read <addr> [<cnt>] - read 1 or 'cnt' fuse bytes,\n"
-	" starting at 'addr'\n"
-	"efuse write [-y] <addr> <hexval> [<hexval>...]  - program 1 or\n"
-	" several fuse bytes, starting at 'addr'\n"
-);
-
-#if CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_VAL_A) || CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_VAL_B) || CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_ANT_EVT)
+#if CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_VAL_A) || CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_VAL_B) || CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_ANT_REF)
 /* Secure function for image verificaiton here */
 int get_image_version(unsigned long img_src_addr)
 {
@@ -244,7 +235,8 @@ void dump_image_header_info(long addr)
 int verify_customer_image(img_type_t type, long addr)
 {
 	int ret;
-
+    const char *image_name = "";
+    
 	/* Double check image number */
 	if (image_have_head(addr) == 0)
 		return -1;
@@ -253,10 +245,10 @@ int verify_customer_image(img_type_t type, long addr)
 	dump_image_header_info(addr);
 
 	/* Call customer image verification function */
-	if ((type == T_TF) || (type == T_TEE)) {
+	if ((type == T_TF) || (type == T_TEE) || (type == T_KRLIMG)) {
 		ret = csi_sec_custom_image_verify(addr, UBOOT_STAGE_ADDR);
 		if (ret) {
-			printf("Image(%s) is verified fail, Please go to check!\n\n", (type == T_TF)?"tf":"tee");
+			printf("Image(%d) is verified fail, Please go to check!\n\n", type);
 			return ret;
 		}
 	} else if (type == T_UBOOT) {
@@ -269,5 +261,13 @@ int verify_customer_image(img_type_t type, long addr)
 
 	return 0;
 }
-
+#else
+U_BOOT_CMD(
+	efuse, CONFIG_SYS_MAXARGS, 0, do_fuse,
+	"eFuse sub-system",
+	"read <addr> [<cnt>] - read 1 or 'cnt' fuse bytes,\n"
+	" starting at 'addr'\n"
+	"efuse write [-y] <addr> <hexval> [<hexval>...]  - program 1 or\n"
+	" several fuse bytes, starting at 'addr'\n"
+);
 #endif

board/thead/light-c910/spl.c

@@ -304,9 +304,9 @@ void cpu_performance_enable(void)
 	csr_write(CSR_MHINT2_E, csr_read(CSR_MHINT2_E) | 0x20000);
 	csr_write(CSR_MHINT4, csr_read(CSR_MHINT4) | 0x410);
 	csr_write(CSR_MCCR2, 0xe2490009);
-	csr_write(CSR_MHCR, 0x11ff);
+	csr_write(CSR_MHCR, 0x117f); // clear bit7 to disable indirect brantch prediction
 	csr_write(CSR_MXSTATUS, 0x638000);
-	csr_write(CSR_MHINT, 0x6e30c);
+	csr_write(CSR_MHINT, 0x6e30c | (1<<21) | (1<<22)); // set bit21 & bit 22 to close tlb & fence broadcast
 }
 
 static int bl1_img_have_head(unsigned long img_src_addr)

board/thead/light-c910/sys_clk.c

@@ -18,6 +18,8 @@
 #define LIGHT_DSP_SUBSYS_ADDRBASE	0xffff041000
 #define LIGHT_AUDIO_SUBSYS_ADDRBASE	0xffcb000000
 #define LIGHT_APSYS_RSTGEN_ADDRBASE	0xffff015000
+#define LIGHT_DPU_CLOCK_GATING_CTRL0	0xffef601A28
+#define LIGHT_DPU_CLOCK_GATING_CTRL1    0xffef601A2C
 
 void show_sys_clk(void)
 {
@@ -285,6 +287,52 @@ void sys_clk_config(void)
 	tmp = readl((void *)LIGHT_APCLK_ADDRBASE + 0x1c8);
 	tmp |= 0x30;
 	writel(tmp, (void *)LIGHT_APCLK_ADDRBASE + 0x1c8);
+
+	/* The boards other than the LightA board perform the bus down-speed operation */
+
+#if defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_DISCRETE) || defined (CONFIG_TARGET_LIGHT_FM_C910_BEAGLE) || defined (CONFIG_TARGET_LIGHT_FM_C910_B_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_B_POWER) || defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_B) || defined (CONFIG_TARGET_LIGHT_FM_C910_LPI4A)
+	/* axi_sram_clk: 812.8512MHz -> 688.128MHz */
+	tmp = readl((void *)LIGHT_AONCLK_ADDRBASE + 0x104);
+	tmp |= 0x2000;
+	writel(tmp, (void *)LIGHT_AONCLK_ADDRBASE + 0x104);
+
+	/* visys_aclk_m decrease frequency 792MHZ->594MHZ */
+	tmp = readl((void *)LIGHT_APCLK_ADDRBASE + 0x1d0);
+	tmp &= ~0x00100000;
+	writel(tmp, (void *)LIGHT_APCLK_ADDRBASE + 0x1d0);
+
+	tmp &= ~0x000f0000;
+	tmp |= 0x00140000;
+	writel(tmp, (void *)LIGHT_APCLK_ADDRBASE + 0x1d0);
+	/* vosys_aclk_m：792MHz->594MHz */
+	tmp = readl((void *)LIGHT_APCLK_ADDRBASE + 0x1dc);
+	tmp &= ~0x00000020;
+	writel(tmp, (void *)LIGHT_APCLK_ADDRBASE + 0x1dc);
+
+	tmp &= ~0x0000000f;
+	tmp |= 0x00000024;
+	writel(tmp, (void *)LIGHT_APCLK_ADDRBASE + 0x1dc);
+
+	/* vpsys_axi_aclk：792MHz->594MHz */
+	tmp = readl((void *)LIGHT_APCLK_ADDRBASE + 0x1e0);
+	tmp &= ~0x00001000;
+	writel(tmp, (void *)LIGHT_APCLK_ADDRBASE + 0x1e0);
+
+	tmp &= ~0x00000f00;
+	tmp |= 0x00001400;
+	writel(tmp, (void *)LIGHT_APCLK_ADDRBASE + 0x1e0);
+
+	/* npu_cclk：1000MHz->792MHz */
+	tmp = readl((void *)LIGHT_APCLK_ADDRBASE + 0x1c8);
+	tmp |= 0x00000040;
+	writel(tmp, (void *)LIGHT_APCLK_ADDRBASE + 0x1c8);
+
+
+	/* Enable dpu auto clock gating */
+	writel(0, (void __iomem *)LIGHT_DPU_CLOCK_GATING_CTRL0);
+	writel(0, (void __iomem *)LIGHT_DPU_CLOCK_GATING_CTRL1);
+#endif
+
 #endif
 }
 

board/thead/light-c910/timer.c

@@ -0,0 +1,224 @@
+/*
+ * Copyright (C) 2017-2020 Alibaba Group Holding Limited
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/types.h>
+#include <thead/clock_config.h>
+#include <linux/bitops.h>
+#include <asm/arch-thead/light-iopmp.h>
+#include <asm/arch-thead/light-plic.h>
+
+#define DW_TIMER0_BASE		0xffefc32000
+#define DW_TIMER0_TLC_REG	(DW_TIMER0_BASE + 0x00)		/* Offset: 0x000 (R/W) TimerLoadCount */
+#define DW_TIMER0_TCV_REG	(DW_TIMER0_BASE + 0X04)		/* Offset: 0x004 (R/ ) TimerCurrentValue */
+#define DW_TIMER0_TCR_REG       (DW_TIMER0_BASE + 0X08)         /* Offset: 0x008 (R/W) TimerControlReg */
+#define DW_TIMER0_TEOI_REG      (DW_TIMER0_BASE + 0X0C)         /* Offset: 0x00c (R/ ) TimerEOI */
+#define DW_TIMER0_TIS_REG       (DW_TIMER0_BASE + 0X10)         /* Offset: 0x010 (R/ ) TimerIntStatus */
+
+/*! Timer Int Status,     offset: 0x10 */
+#define DW_TIMER_INT_STATUS_Pos                                        (0U)
+#define DW_TIMER_INT_STATUS_Msk                                        (0x1U << DW_TIMER_INT_STATUS_Pos)
+#define DW_TIMER_INT_STATUS_EN                                         DW_TIMER_INT_STATUS_Msk
+
+/*! Timer1 Control Reg,	       offset: 0x08 */
+#define DW_TIMER_CTL_ENABLE_SEL_Pos                                    (0U)
+#define DW_TIMER_CTL_ENABLE_SEL_Msk                                    (0x1U << DW_TIMER_CTL_ENABLE_SEL_Pos)
+#define DW_TIMER_CTL_ENABLE_SEL_EN                                     DW_TIMER_CTL_ENABLE_SEL_Msk
+
+#define DW_TIMER_CTL_MODE_SEL_Pos                                      (1U)
+#define DW_TIMER_CTL_MODE_SEL_Msk                                      (0x1U << DW_TIMER_CTL_MODE_SEL_Pos)
+#define DW_TIMER_CTL_MODE_SEL_EN                                       DW_TIMER_CTL_MODE_SEL_Msk
+
+#define DW_TIMER_CTL_INT_MASK_Pos                                      (2U)
+#define DW_TIMER_CTL_INT_MASK_Msk                                      (0x1U << DW_TIMER_CTL_INT_MASK_Pos)
+#define DW_TIMER_CTL_INT_MAKS_EN                                       DW_TIMER_CTL_INT_MASK_Msk
+
+#define DW_TIMER_CTL_HARD_TRIG_Pos                                     (4U)
+#define DW_TIMER_CTL_HARD_TRIG_Msk                                     (0x1U << DW_TIMER_CTL_HARD_TRIG_Pos)
+#define DW_TIMER_CTL_HARD_TRIG_EN                                      DW_TIMER_CTL_HARD_TRIG_Msk
+
+/*! Timer EOI,            offset: 0x0c */
+#define DW_TIMER_EOI_REG_Pos                                           (0U)
+#define DW_TIMER_EOI_REG_Msk                                           (0x1U << DW_TIMER_EOI_REG_Pos)
+#define DW_TIMER_EOI_REG_EN                                            DW_TIMER_EOI_REG_Msk
+
+#define TIMER0_IRQ_NUM	16
+#define TIMER0_FREQ_HZ	125000000U
+#define DW_TIMER_GET_RELOAD_VAL(_tim_, _frq_)      ((_tim_ < 25000U) ? ((_frq_ * _tim_) / 1000U) : (_frq_ * (_tim_ / 1000U)))
+
+static int time_user_defined_flag = 0;
+
+static void csi_timer_stop(void);
+
+static inline u32 dw_timer_get_int_status(void)
+{
+	return (readl((void __iomem *)DW_TIMER0_TIS_REG) & DW_TIMER_INT_STATUS_EN) ?  1 : 0;
+}
+
+static inline void dw_timer_clear_irq(void)
+{
+	readl((void __iomem *)DW_TIMER0_TEOI_REG);
+}
+
+static inline void dw_timer_write_load(uint32_t value)
+{
+	writel(value, (void __iomem *)DW_TIMER0_TLC_REG);
+}
+
+static inline void dw_timer_set_mode_load(void)
+{
+	writel((readl((void __iomem *)DW_TIMER0_TCR_REG) | DW_TIMER_CTL_MODE_SEL_EN), (void __iomem *)DW_TIMER0_TCR_REG);
+}
+
+static inline void dw_timer_set_disable(void)
+{
+	u32 data = readl((void __iomem *)DW_TIMER0_TCR_REG);
+
+	data &= ~DW_TIMER_CTL_ENABLE_SEL_EN;
+	writel(data, (void __iomem *)DW_TIMER0_TCR_REG);
+}
+
+static inline void dw_timer_set_enable(void)
+{
+	u32 data = readl((void __iomem *)DW_TIMER0_TCR_REG);
+
+	data |= DW_TIMER_CTL_ENABLE_SEL_EN;
+	writel(data, (void __iomem *)DW_TIMER0_TCR_REG);
+}
+
+static inline void dw_timer_set_unmask(void)
+{
+	u32 data = readl((void __iomem *)DW_TIMER0_TCR_REG);
+
+	data &= ~DW_TIMER_CTL_INT_MAKS_EN;
+	writel(data, (void __iomem *)DW_TIMER0_TCR_REG);
+}
+
+static inline void dw_timer_set_mask(void)
+{
+	u32 data = readl((void __iomem *)DW_TIMER0_TCR_REG);
+
+	data |= DW_TIMER_CTL_INT_MAKS_EN;
+	writel(data, (void __iomem *)DW_TIMER0_TCR_REG);
+}
+
+static void dw_timer_irq_handler(void)
+{
+	debug("[%s,%d]\n", __func__, __LINE__);
+	if (dw_timer_get_int_status()) {
+		dw_timer_clear_irq();
+		csi_timer_stop();
+		debug("[%s,%d]\n", __func__, __LINE__);
+		time_user_defined_flag = 1;
+	}
+}
+
+static inline void dw_timer_reset_register(void)
+{
+	writel(0, (void __iomem *)DW_TIMER0_TLC_REG);
+	writel(0, (void __iomem *)DW_TIMER0_TCV_REG);
+}
+
+static int csi_timer_start(u32 timeout_us)
+{
+	u32 timer_freq = TIMER0_FREQ_HZ;
+	u32 tmp_load = DW_TIMER_GET_RELOAD_VAL(timeout_us, timer_freq);
+
+	dw_timer_set_mode_load();
+
+	//FIXME: no less than 10
+	if (tmp_load < 10)
+		tmp_load = 10;
+
+	dw_timer_write_load(tmp_load);
+
+	dw_timer_set_disable();
+	dw_timer_set_enable();
+	dw_timer_set_unmask();
+
+	return 0;
+}
+
+static void csi_timer_stop(void)
+{
+	dw_timer_set_mask();
+	dw_timer_set_disable();
+}
+
+static void timer_interrupt_init(void)
+{
+	irq_handler_register(TIMER0_IRQ_NUM, dw_timer_irq_handler);
+	irq_priority_set(TIMER0_IRQ_NUM);
+	irq_enable(TIMER0_IRQ_NUM);
+	arch_local_irq_enable();
+}
+
+static void timer_interrupt_uninit(void)
+{
+	arch_local_irq_disable();
+	irq_disable(TIMER0_IRQ_NUM);
+}
+
+static int csi_timer_init(void)
+{
+	dw_timer_reset_register();
+	timer_interrupt_init();
+	return 0;
+}
+
+static void csi_timer_uinit(void)
+{
+	timer_interrupt_uninit();
+	dw_timer_reset_register();
+}
+
+int timer_alarm_set(cmd_tbl_t *cmdtp, int flag, int argc,
+		char * const argv[])
+{
+	unsigned long time_us;
+	int ret, state;
+	u32 timeout = 0;
+
+	if (argc != 2) {
+		printf("invalid input parameters\n");
+		return -EINVAL;
+	}
+
+	if (strict_strtoul(argv[1], 10, &time_us) < 0)
+		return CMD_RET_USAGE;
+
+	time_us = time_us * 1000000;
+	ret = csi_timer_init();
+	if(ret) {
+		printf("failed to initialize the timer\n");
+		return -EINVAL;
+	}
+
+	time_user_defined_flag = 0;
+	state = csi_timer_start(time_us);
+	if (state) {
+		printf("failed to start the timer0\n");
+		return ret;
+	}
+
+	do {
+
+		timeout++;
+		//if (!timeout)
+		//	break;
+		mdelay(1000);
+		printf("[%s,%d]wait for timer interrupt, %d seconds elapsed\n",
+				__func__, __LINE__, timeout);
+
+	} while (!time_user_defined_flag);
+
+	csi_timer_uinit();
+
+	return 0;
+}
+
+U_BOOT_CMD(timer_alarm, 2, 0, timer_alarm_set, "timer_alarm 10", "timer interrupt test");

board/thead/light-c910/version_rollback.c

@@ -0,0 +1,100 @@
+/*
+ * Copyright (C) 2017-2020 Alibaba Group Holding Limited
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <env.h>
+
+
+static int rollback_part(const char *partition, const char *partition_alt)
+{
+	char *p;
+	int ret;
+	int tmp;
+
+	p = env_get(partition_alt);
+	if (p == NULL) {
+		return 0;
+	}
+	tmp = 1;
+	printf("Rollback partition %s to %s\n", partition, p);
+	ret = env_set(partition, p);
+	if (ret) {
+		printf("Failed to set env %s %s: ret = %d\n", partition, p, ret);
+		tmp = -1;
+	}
+	ret = env_set(partition_alt, NULL);
+	if (ret) {
+		printf("Failed to del env %s: ret = %d\n", partition_alt, ret);
+		tmp = -1;
+	}
+	return tmp;
+}
+
+static int upgrade_rollback_check(void)
+{
+	unsigned long bootlimit;
+	unsigned long bootcount;
+	char *p;
+	char buf[20];
+	int ret;
+	int save;
+
+	p = env_get("bootlimit");
+	if (p == NULL) {
+		return -1;
+	}
+	if (!strcmp(p, "0")) {
+		return 0;
+	} else {
+		if (strict_strtoul(p, 16, &bootlimit) < 0) {
+			printf("Failed to strict_strtoul bootlimit\n");
+			return -1;
+		}
+	}
+	p = env_get("bootcount");
+	if (p == NULL) {
+		bootcount = 0;
+	} else if (strict_strtoul(p, 16, &bootcount) < 0) {
+		bootcount = 0;
+	}
+	save = 0;
+	bootcount++;
+	if (bootcount == bootlimit + 1) {
+		save = 1;
+		printf("Failed to start for %lu times, will rollback!\n", bootlimit);
+		rollback_part("boot_partition", "boot_partition_alt");
+		rollback_part("root_partition", "root_partition_alt");
+	} else if (bootcount < bootlimit + 1) {
+		save = 1;
+	}
+	if (save) {
+		snprintf(buf, sizeof(buf), "%lu", bootcount);
+		ret = env_set("bootcount", buf);
+		if (ret) {
+			printf("Failed to set env bootcount %s: ret = %d\n", buf, ret);
+		}
+		ret = env_save();
+		if (ret) {
+			printf("Failed to env_save: ret = %d\n", ret);
+		}
+	}
+	
+	return 0;
+}
+
+static int do_rollback(cmd_tbl_t *cmdtp, int flag, int argc,
+			char * const argv[])
+{
+    upgrade_rollback_check();
+	return CMD_RET_SUCCESS;
+}
+
+U_BOOT_CMD(
+	rollback, 1, 1,	do_rollback,
+	"Automatic rollback if upgrade fails",
+	NULL
+);

cmd/booti.c

@@ -119,12 +119,14 @@ U_BOOT_CMD(
 
 #endif
 
-#if CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_VAL_A) || CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_VAL_B) || CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_ANT_EVT)
+#if CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_VAL_A) || CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_VAL_B) || CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_ANT_REF)
 extern int light_secboot(int argc, char * const argv[]);
 int do_secboot(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
-	if (light_secboot(argc, argv) != 0)
-		return -1;
+    if (light_secboot(argc, argv) != 0) {
+        run_command("reset", 0);
+        return -1;
+    }
 
 	return 0;
 }

config.mk

@@ -63,6 +63,11 @@ ifdef FTRACE
 PLATFORM_CPPFLAGS += -finstrument-functions -DFTRACE
 endif
 
+ifeq ($(BUILD_TYPE),RELEASE)
+PLATFORM_CPPFLAGS += -DU_BUILD_RELEASE
+else # default build debug 
+PLATFORM_CPPFLAGS += -DU_BUILD_DEBUG
+endif
 #########################################################################
 
 RELFLAGS := $(PLATFORM_RELFLAGS)

configs/light_a_ref_defconfig

@@ -0,0 +1,103 @@
+CONFIG_RISCV=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_ENV_SIZE=0x20000
+CONFIG_ENV_OFFSET=0xe0000
+CONFIG_NR_DRAM_BANKS=8
+CONFIG_SPL=y
+CONFIG_SMP=y
+CONFIG_TARGET_LIGHT_C910=y
+CONFIG_TARGET_LIGHT_FM_C910_A_REF=y
+CONFIG_ARCH_RV64I=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_BUILD_TARGET="u-boot-with-spl.bin"
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_DISPLAY_BOARDINFO=y
+# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
+CONFIG_SPL_RAM_SUPPORT=y
+CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SYS_PROMPT="C910 Light# "
+CONFIG_DDR_LP4X_3733_SINGLERANK=y
+# CONFIG_DDR_LP4_3733_DUALRANK is not set
+CONFIG_DDR_BOARD_CONFIG=y
+CONFIG_CMD_BOOT_SLAVE=y
+CONFIG_CMD_ERASEENV=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_DDR_SCAN=y
+CONFIG_DDR_PRBS_TEST=n
+# CONFIG_DOS_PARTITION is not set
+# CONFIG_ISO_PARTITION is not set
+CONFIG_PARTITION_TYPE_GUID=y
+CONFIG_OF_EMBED=y
+CONFIG_DEFAULT_DEVICE_TREE="light-a-ref"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SPL_CLK=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_UDP_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x10000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_DW=y
+CONFIG_DWAPB_GPIO=y
+# CONFIG_MMC_SPI is not set
+CONFIG_MMC_VERBOSE=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_SNPS=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SNPS=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MMC_RPMB=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_SPI_NAND=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_PHY_REALTEK=y
+CONFIG_RTL8211E_PINE64_GIGABIT_FIX=y
+CONFIG_RTL8211X_PHY_FORCE_MASTER=y
+CONFIG_RTL8211F_PHY_FORCE_EEE_RXC_ON=y
+CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_DESIGNWARE_SPI=y
+CONFIG_DESIGNWARE_QSPI=y
+CONFIG_USB=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="U-Boot-THEAD"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1234
+CONFIG_USB_GADGET_PRODUCT_NUM=0x8888
+# CONFIG_SPL_USE_TINY_PRINTF is not set
+# CONFIG_EFI_LOADER is not set
+# CONFIG_LIGHT_SEC_BOOT is not set
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_DM_VIDEO=y
+CONFIG_PHY=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_CMD_BMP=y
+CONFIG_VIDEO_BRIDGE=y
+CONFIG_DM_PCA953X=y
+CONFIG_VIDEO_VS_DPU=y
+CONFIG_VIDEO_LCD_ILITEK_ILI9881C=y
+CONFIG_VIDEO_DW_DSI_LIGHT=y
+CONFIG_VIDEO_DW_DPHY=y
+CONFIG_VIDEO_DW_DSI_HOST=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_PMIC_VOL_INIT=y
+CONFIG_DDR_REGU_0V6=600000
+CONFIG_DDR_REGU_0V8=800000
+CONFIG_DDR_REGU_1V1=1100000

configs/light_a_val_defconfig

@@ -6,6 +6,9 @@ CONFIG_NR_DRAM_BANKS=8
 CONFIG_SPL=y
 CONFIG_SMP=y
 CONFIG_TARGET_LIGHT_C910=y
+# CONFIG_THEAD_PLIC is not set
+# CONFIG_THEAD_LIGHT_TIMER is not set
+# CONFIG_THEAD_LIGHT_DIGITAL_SENSOR is not set
 CONFIG_ARCH_RV64I=y
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_BUILD_TARGET="u-boot-with-spl.bin"

configs/light_ant_discrete_defconfig

@@ -34,7 +34,7 @@ CONFIG_DDR_PRBS_TEST=n
 # CONFIG_ISO_PARTITION is not set
 CONFIG_PARTITION_TYPE_GUID=y
 CONFIG_OF_EMBED=y
-CONFIG_DEFAULT_DEVICE_TREE="light-ant-evt"
+CONFIG_DEFAULT_DEVICE_TREE="light-ant-ref"
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_SPL_CLK=y

configs/light_ant_ref_defconfig

@@ -6,7 +6,7 @@ CONFIG_NR_DRAM_BANKS=8
 CONFIG_SPL=y
 CONFIG_SMP=y
 CONFIG_TARGET_LIGHT_C910=y
-CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_EVT=y
+CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_REF=y
 CONFIG_ARCH_RV64I=y
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_BUILD_TARGET="u-boot-with-spl.bin"
@@ -34,7 +34,7 @@ CONFIG_DDR_PRBS_TEST=n
 # CONFIG_ISO_PARTITION is not set
 CONFIG_PARTITION_TYPE_GUID=y
 CONFIG_OF_EMBED=y
-CONFIG_DEFAULT_DEVICE_TREE="light-ant-evt"
+CONFIG_DEFAULT_DEVICE_TREE="light-ant-ref"
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_SPL_CLK=y

configs/light_ant_ref_sec_defconfig

@@ -6,7 +6,7 @@ CONFIG_NR_DRAM_BANKS=8
 CONFIG_SPL=y
 CONFIG_SMP=y
 CONFIG_TARGET_LIGHT_C910=y
-CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_EVT=y
+CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_REF=y
 CONFIG_ARCH_RV64I=y
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_BUILD_TARGET="u-boot-with-spl.bin"
@@ -34,7 +34,7 @@ CONFIG_DDR_PRBS_TEST=n
 # CONFIG_ISO_PARTITION is not set
 CONFIG_PARTITION_TYPE_GUID=y
 CONFIG_OF_EMBED=y
-CONFIG_DEFAULT_DEVICE_TREE="light-ant-evt"
+CONFIG_DEFAULT_DEVICE_TREE="light-ant-ref"
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_SPL_CLK=y
@@ -82,7 +82,7 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x1234
 CONFIG_USB_GADGET_PRODUCT_NUM=0x8888
 # CONFIG_SPL_USE_TINY_PRINTF is not set
 # CONFIG_EFI_LOADER is not set
-CONFIG_LIGHT_SEC_BOOT_WITH_VERIFY_ANT_EVT=y
+CONFIG_LIGHT_SEC_BOOT_WITH_VERIFY_ANT_REF=y
 CONFIG_LIGHT_SEC_UPGRADE=y
 CONFIG_BOARD_LATE_INIT=y
 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y

configs/light_b_power_defconfig

@@ -0,0 +1,106 @@
+CONFIG_RISCV=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_ENV_SIZE=0x20000
+CONFIG_ENV_OFFSET=0xe0000
+CONFIG_NR_DRAM_BANKS=8
+CONFIG_SPL=y
+CONFIG_SMP=y
+CONFIG_TARGET_LIGHT_C910=y
+CONFIG_TARGET_LIGHT_FM_C910_B_POWER=y
+CONFIG_ARCH_RV64I=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_BUILD_TARGET="u-boot-with-spl.bin"
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_DISPLAY_BOARDINFO=y
+# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
+CONFIG_SPL_RAM_SUPPORT=y
+CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SYS_PROMPT="C910 Light# "
+CONFIG_DDR_LP4X_3200_SINGLERANK=y
+CONFIG_DDR_H32_MODE=y
+# CONFIG_DDR_LP4_3733_DUALRANK is not set
+CONFIG_DDR_BOARD_CONFIG=y
+CONFIG_CMD_BOOT_SLAVE=y
+CONFIG_CMD_ERASEENV=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_TIME=y
+CONFIG_DDR_SCAN=y
+CONFIG_DDR_PRBS_TEST=n
+# CONFIG_DOS_PARTITION is not set
+# CONFIG_ISO_PARTITION is not set
+CONFIG_PARTITION_TYPE_GUID=y
+CONFIG_OF_EMBED=y
+CONFIG_DEFAULT_DEVICE_TREE="light-b-power"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SPL_CLK=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_UDP_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x10000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_DW=y
+CONFIG_DWAPB_GPIO=y
+# CONFIG_MMC_SPI is not set
+CONFIG_MMC_VERBOSE=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_SNPS=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SNPS=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MMC_RPMB=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_SPI_NAND=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_PHY_REALTEK=y
+CONFIG_RTL8211E_PINE64_GIGABIT_FIX=y
+CONFIG_RTL8211X_PHY_FORCE_MASTER=y
+CONFIG_RTL8211F_PHY_FORCE_EEE_RXC_ON=y
+CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_DESIGNWARE_SPI=y
+CONFIG_DESIGNWARE_QSPI=y
+CONFIG_USB=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="U-Boot-THEAD"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1234
+CONFIG_USB_GADGET_PRODUCT_NUM=0x8888
+# CONFIG_SPL_USE_TINY_PRINTF is not set
+# CONFIG_EFI_LOADER is not set
+# CONFIG_LIGHT_SEC_BOOT is not set
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_DM_VIDEO=y
+CONFIG_PHY=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_CMD_BMP=y
+CONFIG_VIDEO_BRIDGE=y
+CONFIG_DM_PCA953X=y
+CONFIG_VIDEO_VS_DPU=y
+CONFIG_VIDEO_LCD_ILITEK_ILI9881C=y
+CONFIG_VIDEO_DW_DSI_LIGHT=y
+CONFIG_VIDEO_DW_DPHY=y
+CONFIG_VIDEO_DW_DSI_HOST=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_SYS_TEXT_BASE=0x7b000000
+CONFIG_PMIC_VOL_INIT=y
+CONFIG_DDR_REGU_0V6=600000
+CONFIG_DDR_REGU_0V8=800000
+CONFIG_DDR_REGU_1V1=1100000

configs/light_b_ref_defconfig

@@ -0,0 +1,106 @@
+CONFIG_RISCV=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_ENV_SIZE=0x20000
+CONFIG_ENV_OFFSET=0xe0000
+CONFIG_NR_DRAM_BANKS=8
+CONFIG_SPL=y
+CONFIG_SMP=y
+CONFIG_TARGET_LIGHT_C910=y
+CONFIG_TARGET_LIGHT_FM_C910_B_REF=y
+CONFIG_ARCH_RV64I=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_BUILD_TARGET="u-boot-with-spl.bin"
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_DISPLAY_BOARDINFO=y
+# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
+CONFIG_SPL_RAM_SUPPORT=y
+CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SYS_PROMPT="C910 Light# "
+CONFIG_DDR_LP4X_3200_SINGLERANK=y
+CONFIG_DDR_H32_MODE=y
+# CONFIG_DDR_LP4_3733_DUALRANK is not set
+CONFIG_DDR_BOARD_CONFIG=y
+CONFIG_CMD_BOOT_SLAVE=y
+CONFIG_CMD_ERASEENV=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_TIME=y
+CONFIG_DDR_SCAN=y
+CONFIG_DDR_PRBS_TEST=n
+# CONFIG_DOS_PARTITION is not set
+# CONFIG_ISO_PARTITION is not set
+CONFIG_PARTITION_TYPE_GUID=y
+CONFIG_OF_EMBED=y
+CONFIG_DEFAULT_DEVICE_TREE="light-b-ref"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SPL_CLK=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_UDP_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x10000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_DW=y
+CONFIG_DWAPB_GPIO=y
+# CONFIG_MMC_SPI is not set
+CONFIG_MMC_VERBOSE=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_SNPS=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SNPS=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MMC_RPMB=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_SPI_NAND=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_PHY_REALTEK=y
+CONFIG_RTL8211E_PINE64_GIGABIT_FIX=y
+CONFIG_RTL8211X_PHY_FORCE_MASTER=y
+CONFIG_RTL8211F_PHY_FORCE_EEE_RXC_ON=y
+CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_DESIGNWARE_SPI=y
+CONFIG_DESIGNWARE_QSPI=y
+CONFIG_USB=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="U-Boot-THEAD"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1234
+CONFIG_USB_GADGET_PRODUCT_NUM=0x8888
+# CONFIG_SPL_USE_TINY_PRINTF is not set
+# CONFIG_EFI_LOADER is not set
+# CONFIG_LIGHT_SEC_BOOT is not set
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_DM_VIDEO=y
+CONFIG_PHY=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_CMD_BMP=y
+CONFIG_VIDEO_BRIDGE=y
+CONFIG_DM_PCA953X=y
+CONFIG_VIDEO_VS_DPU=y
+CONFIG_VIDEO_LCD_ILITEK_ILI9881C=y
+CONFIG_VIDEO_DW_DSI_LIGHT=y
+CONFIG_VIDEO_DW_DPHY=y
+CONFIG_VIDEO_DW_DSI_HOST=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_SYS_TEXT_BASE=0x7b000000
+CONFIG_PMIC_VOL_INIT=y
+CONFIG_DDR_REGU_0V6=600000
+CONFIG_DDR_REGU_0V8=800000
+CONFIG_DDR_REGU_1V1=1100000

configs/light_beagle_defconfig

@@ -0,0 +1,106 @@
+CONFIG_RISCV=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_ENV_SIZE=0x20000
+CONFIG_ENV_OFFSET=0xe0000
+CONFIG_NR_DRAM_BANKS=8
+CONFIG_SPL=y
+CONFIG_SMP=y
+CONFIG_TARGET_LIGHT_C910=y
+CONFIG_TARGET_LIGHT_FM_C910_BEAGLE=y
+# CONFIG_THEAD_PLIC is not set
+# CONFIG_THEAD_LIGHT_TIMER is not set
+# CONFIG_THEAD_LIGHT_DIGITAL_SENSOR is not set
+CONFIG_ARCH_RV64I=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_BUILD_TARGET="u-boot-with-spl.bin"
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_DISPLAY_BOARDINFO=y
+# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
+CONFIG_SPL_RAM_SUPPORT=y
+CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SYS_PROMPT="C910 Light# "
+CONFIG_DDR_LP4X_3733_SINGLERANK=y
+# CONFIG_DDR_LP4_3733_DUALRANK is not set
+CONFIG_DDR_BOARD_CONFIG=y
+CONFIG_CMD_BOOT_SLAVE=y
+CONFIG_CMD_ERASEENV=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_DDR_SCAN=y
+CONFIG_DDR_PRBS_TEST=n
+# CONFIG_DOS_PARTITION is not set
+# CONFIG_ISO_PARTITION is not set
+CONFIG_PARTITION_TYPE_GUID=y
+CONFIG_OF_EMBED=y
+CONFIG_DEFAULT_DEVICE_TREE="light-a-val"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SPL_CLK=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_UDP_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x10000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_DW=y
+CONFIG_DWAPB_GPIO=y
+# CONFIG_MMC_SPI is not set
+CONFIG_MMC_VERBOSE=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_SNPS=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SNPS=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MMC_RPMB=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_SPI_NAND=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_PHY_REALTEK=y
+CONFIG_RTL8211E_PINE64_GIGABIT_FIX=y
+CONFIG_RTL8211X_PHY_FORCE_MASTER=y
+CONFIG_RTL8211F_PHY_FORCE_EEE_RXC_ON=y
+CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_DESIGNWARE_SPI=y
+CONFIG_DESIGNWARE_QSPI=y
+CONFIG_USB=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="U-Boot-THEAD"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1234
+CONFIG_USB_GADGET_PRODUCT_NUM=0x8888
+# CONFIG_SPL_USE_TINY_PRINTF is not set
+# CONFIG_EFI_LOADER is not set
+# CONFIG_LIGHT_SEC_BOOT is not set
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_DM_VIDEO=y
+CONFIG_PHY=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_CMD_BMP=y
+CONFIG_VIDEO_BRIDGE=y
+CONFIG_DM_PCA953X=y
+CONFIG_VIDEO_VS_DPU=y
+CONFIG_VIDEO_LCD_ILITEK_ILI9881C=y
+CONFIG_VIDEO_DW_DSI_LIGHT=y
+CONFIG_VIDEO_DW_DPHY=y
+CONFIG_VIDEO_DW_DSI_HOST=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_PMIC_VOL_INIT=y
+CONFIG_DDR_REGU_0V6=600000
+CONFIG_DDR_REGU_0V8=800000
+CONFIG_DDR_REGU_1V1=1100000

configs/light_lpi4a_defconfig

@@ -0,0 +1,106 @@
+CONFIG_RISCV=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_ENV_SIZE=0x20000
+CONFIG_ENV_OFFSET=0xe0000
+CONFIG_NR_DRAM_BANKS=8
+CONFIG_SPL=y
+CONFIG_SMP=y
+CONFIG_TARGET_LIGHT_C910=y
+CONFIG_TARGET_LIGHT_FM_C910_LPI4A=y
+# CONFIG_THEAD_PLIC is not set
+# CONFIG_THEAD_LIGHT_TIMER is not set
+# CONFIG_THEAD_LIGHT_DIGITAL_SENSOR is not set
+CONFIG_ARCH_RV64I=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_BUILD_TARGET="u-boot-with-spl.bin"
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_DISPLAY_BOARDINFO=y
+# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
+CONFIG_SPL_RAM_SUPPORT=y
+CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SYS_PROMPT="C910 Light# "
+CONFIG_DDR_LP4X_3733_DUALRANK=y
+# CONFIG_DDR_LP4_3733_DUALRANK is not set
+CONFIG_DDR_BOARD_CONFIG=y
+CONFIG_CMD_BOOT_SLAVE=y
+CONFIG_CMD_ERASEENV=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_DDR_SCAN=y
+CONFIG_DDR_PRBS_TEST=n
+# CONFIG_DOS_PARTITION is not set
+# CONFIG_ISO_PARTITION is not set
+CONFIG_PARTITION_TYPE_GUID=y
+CONFIG_OF_EMBED=y
+CONFIG_DEFAULT_DEVICE_TREE="light-lpi4a"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SPL_CLK=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_UDP_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x10000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_DW=y
+CONFIG_DWAPB_GPIO=y
+# CONFIG_MMC_SPI is not set
+CONFIG_MMC_VERBOSE=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_SNPS=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SNPS=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MMC_RPMB=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_SPI_NAND=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_PHY_REALTEK=y
+CONFIG_RTL8211E_PINE64_GIGABIT_FIX=y
+CONFIG_RTL8211X_PHY_FORCE_MASTER=y
+CONFIG_RTL8211F_PHY_FORCE_EEE_RXC_ON=y
+CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_DESIGNWARE_SPI=y
+CONFIG_DESIGNWARE_QSPI=y
+CONFIG_USB=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="U-Boot-THEAD"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1234
+CONFIG_USB_GADGET_PRODUCT_NUM=0x8888
+# CONFIG_SPL_USE_TINY_PRINTF is not set
+# CONFIG_EFI_LOADER is not set
+# CONFIG_LIGHT_SEC_BOOT is not set
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_DM_VIDEO=y
+CONFIG_PHY=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_CMD_BMP=y
+CONFIG_VIDEO_BRIDGE=y
+CONFIG_DM_PCA953X=y
+CONFIG_VIDEO_VS_DPU=y
+CONFIG_VIDEO_LCD_ILITEK_ILI9881C=y
+CONFIG_VIDEO_DW_DSI_LIGHT=y
+CONFIG_VIDEO_DW_DPHY=y
+CONFIG_VIDEO_DW_DSI_HOST=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_PMIC_VOL_INIT=y
+CONFIG_DDR_REGU_0V6=600000
+CONFIG_DDR_REGU_0V8=800000
+CONFIG_DDR_REGU_1V1=1100000

configs/light_lpi4a_singlerank_defconfig

@@ -0,0 +1,106 @@
+CONFIG_RISCV=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_ENV_SIZE=0x20000
+CONFIG_ENV_OFFSET=0xe0000
+CONFIG_NR_DRAM_BANKS=8
+CONFIG_SPL=y
+CONFIG_SMP=y
+CONFIG_TARGET_LIGHT_C910=y
+CONFIG_TARGET_LIGHT_FM_C910_LPI4A=y
+# CONFIG_THEAD_PLIC is not set
+# CONFIG_THEAD_LIGHT_TIMER is not set
+# CONFIG_THEAD_LIGHT_DIGITAL_SENSOR is not set
+CONFIG_ARCH_RV64I=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_BUILD_TARGET="u-boot-with-spl.bin"
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_DISPLAY_BOARDINFO=y
+# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
+CONFIG_SPL_RAM_SUPPORT=y
+CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SYS_PROMPT="C910 Light# "
+CONFIG_DDR_LP4X_3733_SINGLERANK=y
+# CONFIG_DDR_LP4_3733_DUALRANK is not set
+CONFIG_DDR_BOARD_CONFIG=y
+CONFIG_CMD_BOOT_SLAVE=y
+CONFIG_CMD_ERASEENV=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_DDR_SCAN=y
+CONFIG_DDR_PRBS_TEST=n
+# CONFIG_DOS_PARTITION is not set
+# CONFIG_ISO_PARTITION is not set
+CONFIG_PARTITION_TYPE_GUID=y
+CONFIG_OF_EMBED=y
+CONFIG_DEFAULT_DEVICE_TREE="light-lpi4a"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SPL_CLK=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_UDP_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x10000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_DW=y
+CONFIG_DWAPB_GPIO=y
+# CONFIG_MMC_SPI is not set
+CONFIG_MMC_VERBOSE=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_SNPS=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SNPS=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MMC_RPMB=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_SPI_NAND=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_PHY_REALTEK=y
+CONFIG_RTL8211E_PINE64_GIGABIT_FIX=y
+CONFIG_RTL8211X_PHY_FORCE_MASTER=y
+CONFIG_RTL8211F_PHY_FORCE_EEE_RXC_ON=y
+CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_DESIGNWARE_SPI=y
+CONFIG_DESIGNWARE_QSPI=y
+CONFIG_USB=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="U-Boot-THEAD"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1234
+CONFIG_USB_GADGET_PRODUCT_NUM=0x8888
+# CONFIG_SPL_USE_TINY_PRINTF is not set
+# CONFIG_EFI_LOADER is not set
+# CONFIG_LIGHT_SEC_BOOT is not set
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_DM_VIDEO=y
+CONFIG_PHY=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_CMD_BMP=y
+CONFIG_VIDEO_BRIDGE=y
+CONFIG_DM_PCA953X=y
+CONFIG_VIDEO_VS_DPU=y
+CONFIG_VIDEO_LCD_ILITEK_ILI9881C=y
+CONFIG_VIDEO_DW_DSI_LIGHT=y
+CONFIG_VIDEO_DW_DPHY=y
+CONFIG_VIDEO_DW_DSI_HOST=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_PMIC_VOL_INIT=y
+CONFIG_DDR_REGU_0V6=600000
+CONFIG_DDR_REGU_0V8=800000
+CONFIG_DDR_REGU_1V1=1100000

drivers/fastboot/fb_command.c

@@ -41,6 +41,7 @@ static void reboot_bootloader(char *, char *);
 #if CONFIG_IS_ENABLED(FASTBOOT_CMD_OEM_FORMAT)
 static void oem_format(char *, char *);
 #endif
+static void oem_command(char *, char *);
 
 static const struct {
 	const char *command;
@@ -90,6 +91,10 @@ static const struct {
 		.dispatch = oem_format,
 	},
 #endif
+	[FASTBOOT_COMMAND_OEM_COMMAND] = {
+		.command = "oem command",
+		.dispatch = oem_command,
+	},
 };
 
 /**
@@ -439,3 +444,17 @@ static void oem_format(char *cmd_parameter, char *response)
 	}
 }
 #endif
+
+/**
+ * oem_command() - Execute the OEM command
+ *
+ * @cmd_parameter: Pointer to command parameter
+ * @response: Pointer to fastboot response buffer
+ */
+static void oem_command(char *cmd_parameter, char *response)
+{
+	if (run_command(cmd_parameter, 0))
+		fastboot_fail("", response);
+	else
+		fastboot_okay(NULL, response);
+}

drivers/usb/dwc3/ep0.c

@@ -905,6 +905,7 @@ static void dwc3_ep0_xfer_complete(struct dwc3 *dwc,
 	dep->flags &= ~DWC3_EP_BUSY;
 	dep->resource_index = 0;
 	dwc->setup_packet_pending = false;
+	invalid_dcache_range(dwc->ctrl_req, (dmaaddr_t)dwc->ctrl_req + ROUND(sizeof(*dwc->ctrl_req), CACHELINE_SIZE));
 
 	switch (dwc->ep0state) {
 	case EP0_SETUP_PHASE:

include/configs/light-c910.h

@@ -41,7 +41,7 @@
 #define CONFIG_ENV_ADDR             (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
 #define CONFIG_SYS_MMC_ENV_DEV      0
 
-#define CONFIG_SYS_SDRAM_BASE       	0
+#define CONFIG_SYS_SDRAM_BASE           0
 #define MEMTEST_MAX_SIZE                0x200000000 /* 8GB DDR */
 #define CONFIG_SYS_MEMTEST_START        0x00000000 // larger than Uboot end addr
 #define CONFIG_SYS_MEMTEST_END          CONFIG_SYS_SDRAM_BASE + MEMTEST_MAX_SIZE
@@ -75,6 +75,7 @@
 #define TEE_PART_NAME		"tee"
 #define UBOOT_PART_NAME		"uboot"
 #define STASH_PART_NAME 	"stash"
+#define KERNEL_PART_NAME	"kernel"
 
 #define UBOOT_STAGE_ADDR	SRAM_BASE_ADDR
 
@@ -90,10 +91,33 @@
 #define TEE_SEC_UPGRADE_FLAG 0x5a5aa5a5
 #define UBOOT_SEC_UPGRADE_FLAG	0xa5a5aa55
 
+/* Define secure debug log level */
+#define LOG_LEVEL	1
+#if defined (LOG_LEVEL)
+#define SECLOG_PRINT	printf
+#else
+#define SECLOG_PRINT
+#endif
+
 #define UBOOT_MAX_VER		64
+#define CONFIG_SYS_CBSIZE 	512
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE /* Boot args buffer */
+#define CONFIG_SYS_MAXARGS	64		/* max number of command args */
+/* List of different env in debug/release version  */
+#if defined (U_BUILD_DEBUG)
+#define ENV_KERNEL_LOGLEVEL "kernel_loglevel=7\0"
+#define ENV_STR_BOOT_DELAY  
+#else
+#define ENV_KERNEL_LOGLEVEL "kernel_loglevel=4\0"
+#define ENV_STR_BOOT_DELAY	"bootdelay=0\0"
+#endif
 
 #if defined (CONFIG_LIGHT_SEC_BOOT_WITH_VERIFY_VAL_A)
 #define CONFIG_EXTRA_ENV_SETTINGS \
+	"splashimage=0x30000000\0" \
+	"splashpos=m,m\0" \
 	"fdt_high=0xffffffffffffffff\0" \
 	"tf_addr=0x100000\0" \
 	"dtb_addr=0x01f00000\0" \
@@ -104,22 +128,31 @@
 	"tee_addr=0x1c000000\0" \
 	"sec_upgrade_mode=0\0"\
 	"mmcdev=0\0" \
-	"mmcpart=6\0" \
+	"boot_partition=bootA\0" \
+	"root_partition=rootfsA\0" \
+	"kdump_buf=1M\0" \
 	"uboot_version=0x0000000000000000\0"\
+	"tee_version=0x00000000\0"\
+	"tf_version=0x00000000\0"\
+	"findpart=rollback; if test ${boot_partition} = bootB; then mmcbootpart=7; else mmcbootpart=2; fi; if test ${root_partition} = rootfsB; then mmcpart=8; else mmcpart=6; fi;\0" \
 	"fdt_file=light-a-val-sec.dtb\0" \
-	"uuid_rootfs=80a5a8e9-c744-491a-93c1-4f4194fd690b\0" \
-	"partitions=name=table,size=2031KB;name=boot,size=200MiB,type=boot;name=tf,size=50MiB,type=boot;name=tee,size=50MiB,type=boot;name=stash,size=50MiB,type=boot;name=root,size=4000MiB,type=linux,uuid=${uuid_rootfs};name=data,size=-,type=linux\0" \
+	"uuid_rootfsA=80a5a8e9-c744-491a-93c1-4f4194fd690a\0" \
+	"uuid_rootfsB=80a5a8e9-c744-491a-93c1-4f4194fd690b\0" \
+	"partitions=name=table,size=2031KB;name=boot,size=200MiB,type=boot;name=tf,size=50MiB,type=boot;name=tee,size=50MiB,type=boot;name=stash,size=50MiB,type=boot;name=root,size=4000MiB,type=linux,uuid=${uuid_rootfsA};name=bootB,size=200MiB,type=boot;name=rootB,size=4000MiB,type=linux,uuid=${uuid_rootfsB};name=data,size=-,type=linux\0" \
 	"finduuid=part uuid mmc ${mmcdev}:${mmcpart} uuid\0" \
 	"gpt_partition=gpt write mmc ${mmcdev} $partitions\0" \
-	"set_bootargs=setenv bootargs console=ttyS0,115200 root=PARTUUID=${uuid} rootfstype=ext4 rdinit=/sbin/init rootwait rw earlycon clk_ignore_unused loglevel=7 eth=$ethaddr\0" \
-	"load_aon=ext4load mmc 0:2 $fwaddr light_aon_fpga.bin;cp.b $fwaddr $aon_ram_addr $filesize\0"\
-	"load_c906_audio=ext4load mmc 0:2 $fwaddr light_c906_audio.bin;cp.b $fwaddr $audio_ram_addr $filesize\0"\
-	"bootcmd_load=run load_aon;run load_c906_audio; ext4load mmc 0:3 $tf_addr trust_firmware.bin; ext4load mmc 0:4 $tee_addr tee.bin;ext4load mmc 0:2 $dtb_addr ${fdt_file}; ext4load mmc 0:2 $kernel_addr Image\0" \
+	"set_bootargs=setenv bootargs console=ttyS0,115200 root=PARTUUID=${uuid} rootfstype=ext4 rdinit=/sbin/init rootwait rw earlycon clk_ignore_unused loglevel=7 eth=$ethaddr rootrw=PARTLABEL=data init=/init rootinit=/sbin/init rootrwoptions=rw,noatime rootrwreset=${factory_reset} crashkernel=${kdump_buf}\0" \
+	"load_aon=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_aon_fpga.bin;cp.b $fwaddr $aon_ram_addr $filesize\0"\
+	"load_c906_audio=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_c906_audio.bin;cp.b $fwaddr $audio_ram_addr $filesize\0"\
+	"bootcmd_load=run findpart;run load_aon;run load_c906_audio; ext4load mmc 0:3 $tf_addr trust_firmware.bin; ext4load mmc 0:4 $tee_addr tee.bin;ext4load mmc ${mmcdev}:${mmcbootpart} $dtb_addr ${fdt_file}; ext4load mmc ${mmcdev}:${mmcbootpart} $kernel_addr Image\0" \
 	"bootcmd=run bootcmd_load; bootslave; run finduuid; run set_bootargs; secboot; booti $kernel_addr - $dtb_addr;\0" \
+	"factory_reset=yes\0"\
         "\0"
 
 #elif defined (CONFIG_LIGHT_SEC_BOOT_WITH_VERIFY_VAL_B)
 #define CONFIG_EXTRA_ENV_SETTINGS \
+	"splashimage=0x30000000\0" \
+	"splashpos=m,m\0" \
 	"fdt_high=0xffffffffffffffff\0" \
 	"tf_addr=0x100000\0" \
 	"dtb_addr=0x01f00000\0" \
@@ -130,22 +163,31 @@
 	"tee_addr=0x1c000000\0" \
 	"sec_upgrade_mode=0\0"\
 	"mmcdev=0\0" \
-	"mmcpart=6\0" \
+	"boot_partition=bootA\0" \
+	"root_partition=rootfsA\0" \
+	"kdump_buf=1M\0" \
 	"uboot_version=0x0000000000000000\0"\
+	"tee_version=0x00000000\0"\
+	"tf_version=0x00000000\0"\
+	"findpart=rollback; if test ${boot_partition} = bootB; then mmcbootpart=7; else mmcbootpart=2; fi; if test ${root_partition} = rootfsB; then mmcpart=8; else mmcpart=6; fi;\0" \
 	"fdt_file=light-b-product-sec.dtb\0" \
-	"uuid_rootfs=80a5a8e9-c744-491a-93c1-4f4194fd690b\0" \
-	"partitions=name=table,size=2031KB;name=boot,size=200MiB,type=boot;name=tf,size=50MiB,type=boot;name=tee,size=50MiB,type=boot;name=stash,size=50MiB,type=boot;name=root,size=4000MiB,type=linux,uuid=${uuid_rootfs};name=data,size=-,type=linux\0" \
+	"uuid_rootfsA=80a5a8e9-c744-491a-93c1-4f4194fd690a\0" \
+	"uuid_rootfsB=80a5a8e9-c744-491a-93c1-4f4194fd690b\0" \
+	"partitions=name=table,size=2031KB;name=boot,size=200MiB,type=boot;name=tf,size=50MiB,type=boot;name=tee,size=50MiB,type=boot;name=stash,size=50MiB,type=boot;name=root,size=4000MiB,type=linux,uuid=${uuid_rootfsA};name=bootB,size=200MiB,type=boot;name=rootB,size=4000MiB,type=linux,uuid=${uuid_rootfsB};name=data,size=-,type=linux\0" \
 	"finduuid=part uuid mmc ${mmcdev}:${mmcpart} uuid\0" \
 	"gpt_partition=gpt write mmc ${mmcdev} $partitions\0" \
-	"set_bootargs=setenv bootargs console=ttyS0,115200 root=PARTUUID=${uuid} rootfstype=ext4 rdinit=/sbin/init rootwait rw earlycon clk_ignore_unused loglevel=7 eth=$ethaddr\0" \
-	"load_aon=ext4load mmc 0:2 $fwaddr light_aon_fpga.bin;cp.b $fwaddr $aon_ram_addr $filesize\0"\
-	"load_c906_audio=ext4load mmc 0:2 $fwaddr light_c906_audio.bin;cp.b $fwaddr $audio_ram_addr $filesize\0"\
-	"bootcmd_load=run load_aon;run load_c906_audio; ext4load mmc 0:3 $tf_addr trust_firmware.bin; ext4load mmc 0:4 $tee_addr tee.bin;ext4load mmc 0:2 $dtb_addr ${fdt_file}; ext4load mmc 0:2 $kernel_addr Image\0" \
+	"set_bootargs=setenv bootargs console=ttyS0,115200 root=PARTUUID=${uuid} rootfstype=ext4 rdinit=/sbin/init rootwait rw earlycon clk_ignore_unused loglevel=7 eth=$ethaddr rootrw=PARTLABEL=data init=/init rootinit=/sbin/init rootrwoptions=rw,noatime rootrwreset=${factory_reset} crashkernel=${kdump_buf}\0" \
+	"load_aon=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_aon_fpga.bin;cp.b $fwaddr $aon_ram_addr $filesize\0"\
+	"load_c906_audio=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_c906_audio.bin;cp.b $fwaddr $audio_ram_addr $filesize\0"\
+	"bootcmd_load=run findpart;run load_aon;run load_c906_audio; ext4load mmc 0:3 $tf_addr trust_firmware.bin; ext4load mmc 0:4 $tee_addr tee.bin;ext4load mmc ${mmcdev}:${mmcbootpart} $dtb_addr ${fdt_file}; ext4load mmc ${mmcdev}:${mmcbootpart} $kernel_addr Image\0" \
 	"bootcmd=run bootcmd_load; bootslave; run finduuid; run set_bootargs; secboot; booti $kernel_addr - $dtb_addr;\0" \
+	"factory_reset=yes\0"\
         "\0"
 
-#elif defined (CONFIG_LIGHT_SEC_BOOT_WITH_VERIFY_ANT_EVT)
+#elif defined (CONFIG_LIGHT_SEC_BOOT_WITH_VERIFY_ANT_REF)
 #define CONFIG_EXTRA_ENV_SETTINGS \
+	"splashimage=0x30000000\0" \
+	"splashpos=m,m\0" \
 	"fdt_high=0xffffffffffffffff\0" \
 	"tf_addr=0x100000\0" \
 	"dtb_addr=0x01f00000\0" \
@@ -156,18 +198,25 @@
 	"tee_addr=0x1c000000\0" \
 	"sec_upgrade_mode=0\0"\
 	"mmcdev=0\0" \
-	"mmcpart=6\0" \
+	"boot_partition=bootA\0" \
+	"root_partition=rootfsA\0" \
+	"kdump_buf=1M\0" \
 	"uboot_version=0x0000000000000000\0"\
-	"fdt_file=light-ant-evt-sec.dtb\0" \
-	"uuid_rootfs=80a5a8e9-c744-491a-93c1-4f4194fd690b\0" \
-	"partitions=name=table,size=2031KB;name=boot,size=200MiB,type=boot;name=tf,size=50MiB,type=boot;name=tee,size=50MiB,type=boot;name=stash,size=50MiB,type=boot;name=root,size=4000MiB,type=linux,uuid=${uuid_rootfs};name=data,size=-,type=linux\0" \
+	"tee_version=0x00000000\0"\
+	"tf_version=0x00000000\0"\
+	"findpart=rollback; if test ${boot_partition} = bootB; then mmcbootpart=7; else mmcbootpart=2; fi; if test ${root_partition} = rootfsB; then mmcpart=8; else mmcpart=6; fi;\0" \
+	"fdt_file=light-ant-ref-sec.dtb\0" \
+	"uuid_rootfsA=80a5a8e9-c744-491a-93c1-4f4194fd690a\0" \
+	"uuid_rootfsB=80a5a8e9-c744-491a-93c1-4f4194fd690b\0" \
+	"partitions=name=table,size=2031KB;name=boot,size=200MiB,type=boot;name=tf,size=50MiB,type=boot;name=tee,size=50MiB,type=boot;name=stash,size=50MiB,type=boot;name=root,size=4000MiB,type=linux,uuid=${uuid_rootfsA};name=bootB,size=200MiB,type=boot;name=rootB,size=4000MiB,type=linux,uuid=${uuid_rootfsB};name=data,size=-,type=linux\0" \
 	"finduuid=part uuid mmc ${mmcdev}:${mmcpart} uuid\0" \
 	"gpt_partition=gpt write mmc ${mmcdev} $partitions\0" \
-	"set_bootargs=setenv bootargs console=ttyS0,115200 root=PARTUUID=${uuid} rootfstype=ext4 rdinit=/sbin/init rootwait rw earlycon clk_ignore_unused loglevel=7 eth=$ethaddr\0" \
-	"load_aon=ext4load mmc 0:2 $fwaddr light_aon_fpga.bin;cp.b $fwaddr $aon_ram_addr $filesize\0"\
-	"load_c906_audio=ext4load mmc 0:2 $fwaddr light_c906_audio.bin;cp.b $fwaddr $audio_ram_addr $filesize\0"\
-	"bootcmd_load=run load_aon;run load_c906_audio; ext4load mmc 0:3 $tf_addr trust_firmware.bin; ext4load mmc 0:4 $tee_addr tee.bin;ext4load mmc 0:2 $dtb_addr ${fdt_file}; ext4load mmc 0:2 $kernel_addr Image\0" \
+	"set_bootargs=setenv bootargs console=ttyS0,115200 root=PARTUUID=${uuid} rootfstype=ext4 rdinit=/sbin/init rootwait rw earlycon clk_ignore_unused loglevel=7 eth=$ethaddr rootrw=PARTLABEL=data init=/init rootinit=/sbin/init rootrwoptions=rw,noatime rootrwreset=${factory_reset} crashkernel=${kdump_buf}\0" \
+	"load_aon=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_aon_fpga.bin;cp.b $fwaddr $aon_ram_addr $filesize\0"\
+	"load_c906_audio=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_c906_audio.bin;cp.b $fwaddr $audio_ram_addr $filesize\0"\
+	"bootcmd_load=run findpart;run load_aon;run load_c906_audio; ext4load mmc 0:3 $tf_addr trust_firmware.bin; ext4load mmc 0:4 $tee_addr tee.bin;ext4load mmc ${mmcdev}:${mmcbootpart} $dtb_addr ${fdt_file}; ext4load mmc ${mmcdev}:${mmcbootpart} $kernel_addr Image\0" \
 	"bootcmd=run bootcmd_load; bootslave; run finduuid; run set_bootargs; secboot; booti $kernel_addr - $dtb_addr;\0" \
+	"factory_reset=yes\0"\
         "\0"
 
 #else
@@ -184,16 +233,18 @@
 	"fwaddr=0x10000000\0"\
 	"mmcdev=0\0" \
 	"mmcpart=3\0" \
+	"kdump_buf=1M\0" \
 	"fdt_file=light-a-product.dtb\0" \
 	"uuid_rootfs=80a5a8e9-c744-491a-93c1-4f4194fd690b\0" \
 	"partitions=name=table,size=2031KB;name=boot,size=200MiB,type=boot;name=root,size=4000MiB,type=linux,uuid=${uuid_rootfs};name=data,size=-,type=linux\0" \
 	"finduuid=part uuid mmc ${mmcdev}:${mmcpart} uuid\0" \
 	"gpt_partition=gpt write mmc ${mmcdev} $partitions\0" \
-	"set_bootargs=setenv bootargs console=ttyS0,115200 root=PARTUUID=${uuid} rootfstype=ext4 rdinit=/sbin/init rootwait rw earlycon clk_ignore_unused loglevel=7 eth=$ethaddr\0" \
+	"set_bootargs=setenv bootargs console=ttyS0,115200 root=PARTUUID=${uuid} rootfstype=ext4 rdinit=/sbin/init rootwait rw earlycon clk_ignore_unused loglevel=7 eth=$ethaddr rootrwreset=${factory_reset} crashkernel=${kdump_buf}\0" \
 	"load_aon=ext4load mmc 0:2 $fwaddr light_aon_fpga.bin;cp.b $fwaddr $aon_ram_addr $filesize\0"\
 	"load_c906_audio=ext4load mmc 0:2 $fwaddr light_c906_audio.bin;cp.b $fwaddr $audio_ram_addr $filesize\0"\
 	"bootcmd_load=run load_aon;run load_c906_audio; ext4load mmc 0:2 $opensbi_addr fw_dynamic.bin; ext4load mmc 0:2 $dtb_addr ${fdt_file}; ext4load mmc 0:2 $kernel_addr Image\0" \
 	"bootcmd=run bootcmd_load; bootslave; run finduuid; run set_bootargs; booti $kernel_addr - $dtb_addr;\0" \
+	"factory_reset=yes\0"\
         "\0"
 #elif defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_B)
 #define CONFIG_EXTRA_ENV_SETTINGS \
@@ -209,20 +260,24 @@
 	"mmcdev=0\0" \
 	"boot_partition=bootA\0" \
 	"root_partition=rootfsA\0" \
-	"findpart=if test ${boot_partition} = bootB; then mmcbootpart=4; else mmcbootpart=2; fi; if test ${root_partition} = rootfsB; then mmcpart=5; else mmcpart=3; fi;\0" \
+	ENV_KERNEL_LOGLEVEL \
+	"kdump_buf=1M\0" \
+	ENV_STR_BOOT_DELAY \
+	"findpart=rollback; if test ${boot_partition} = bootB; then mmcbootpart=4; else mmcbootpart=2; fi; if test ${root_partition} = rootfsB; then mmcpart=5; else mmcpart=3; fi;\0" \
 	"fdt_file=light-b-product.dtb\0" \
 	"uuid_rootfsA=80a5a8e9-c744-491a-93c1-4f4194fd690a\0" \
 	"uuid_rootfsB=80a5a8e9-c744-491a-93c1-4f4194fd690b\0" \
 	"partitions=name=table,size=2031KB;name=boot,size=200MiB,type=boot;name=root,size=4000MiB,type=linux,uuid=${uuid_rootfsA};name=bootB,size=200MiB,type=boot;name=rootB,size=4000MiB,type=linux,uuid=${uuid_rootfsB};name=data,size=-,type=linux\0" \
 	"finduuid=part uuid mmc ${mmcdev}:${mmcpart} uuid\0" \
 	"gpt_partition=gpt write mmc ${mmcdev} $partitions\0" \
-	"set_bootargs=setenv bootargs console=ttyS0,115200 root=PARTUUID=${uuid} rootfstype=ext4 rdinit=/sbin/init rootwait rw earlycon clk_ignore_unused loglevel=7 eth=$ethaddr rootrw=PARTLABEL=data init=/init rootinit=/sbin/init rootrwoptions=rw,noatime\0" \
+	"set_bootargs=setenv bootargs console=ttyS0,115200 root=PARTUUID=${uuid} rootfstype=ext4 rdinit=/sbin/init rootwait rw earlycon clk_ignore_unused loglevel=${kernel_loglevel} eth=$ethaddr rootrw=PARTLABEL=data init=/init rootinit=/sbin/init rootrwoptions=rw,noatime rootrwreset=${factory_reset} crashkernel=${kdump_buf}\0" \
 	"load_aon=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_aon_fpga.bin;cp.b $fwaddr $aon_ram_addr $filesize\0"\
 	"load_c906_audio=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_c906_audio.bin;cp.b $fwaddr $audio_ram_addr $filesize\0"\
 	"bootcmd_load=run findpart;run load_aon;run load_c906_audio; ext4load mmc ${mmcdev}:${mmcbootpart} $opensbi_addr fw_dynamic.bin; ext4load mmc ${mmcdev}:${mmcbootpart} $dtb_addr ${fdt_file};ext4load mmc ${mmcdev}:${mmcbootpart} $kernel_addr Image;\0" \
 	"bootcmd=run bootcmd_load; bootslave ; run finduuid; run set_bootargs; booti $kernel_addr - $dtb_addr;\0" \
+	"factory_reset=yes\0"\
         "\0"
-#elif defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_EVT)
+#elif defined (CONFIG_TARGET_LIGHT_FM_C910_B_REF)
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	"splashimage=0x30000000\0" \
 	"splashpos=m,m\0" \
@@ -237,7 +292,7 @@
 	"boot_partition=bootA\0" \
 	"root_partition=rootfsA\0" \
 	"findpart=if test ${boot_partition} = bootB; then mmcbootpart=4; else mmcbootpart=2; fi; if test ${root_partition} = rootfsB; then mmcpart=5; else mmcpart=3; fi;\0" \
-	"fdt_file=light-ant-evt.dtb\0" \
+	"fdt_file=light-b-ref.dtb\0" \
 	"uuid_rootfsA=80a5a8e9-c744-491a-93c1-4f4194fd690a\0" \
 	"uuid_rootfsB=80a5a8e9-c744-491a-93c1-4f4194fd690b\0" \
 	"partitions=name=table,size=2031KB;name=boot,size=200MiB,type=boot;name=root,size=4000MiB,type=linux,uuid=${uuid_rootfsA};name=bootB,size=200MiB,type=boot;name=rootB,size=4000MiB,type=linux,uuid=${uuid_rootfsB};name=data,size=-,type=linux\0" \
@@ -246,8 +301,68 @@
 	"set_bootargs=setenv bootargs console=ttyS0,115200 root=PARTUUID=${uuid} rootfstype=ext4 rdinit=/sbin/init rootwait rw earlycon clk_ignore_unused loglevel=7 eth=$ethaddr rootrw=PARTLABEL=data init=/init rootinit=/sbin/init rootrwoptions=rw,noatime\0" \
 	"load_aon=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_aon_fpga.bin;cp.b $fwaddr $aon_ram_addr $filesize\0"\
 	"load_c906_audio=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_c906_audio.bin;cp.b $fwaddr $audio_ram_addr $filesize\0"\
+	"bootcmd_load=run findpart;run load_aon;run load_c906_audio; ext4load mmc ${mmcdev}:${mmcbootpart} $opensbi_addr fw_dynamic.bin; ext4load mmc ${mmcdev}:${mmcbootpart} $dtb_addr ${fdt_file};ext4load mmc ${mmcdev}:${mmcbootpart} $kernel_addr Image;\0" \
+	"bootcmd=run bootcmd_load; bootslave ; run finduuid; run set_bootargs; booti $kernel_addr - $dtb_addr;\0" \
+        "\0"
+#elif defined (CONFIG_TARGET_LIGHT_FM_C910_B_POWER)
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"splashimage=0x30000000\0" \
+	"splashpos=m,m\0" \
+	"fdt_high=0xffffffffffffffff\0" \
+	"opensbi_addr=0x0\0" \
+	"dtb_addr=0x01f00000\0" \
+	"kernel_addr=0x00200000\0" \
+	"aon_ram_addr=0xffffef8000\0" \
+	"audio_ram_addr=0xffc0000000\0" \
+	"fwaddr=0x10000000\0"\
+	"mmcdev=0\0" \
+	"boot_partition=bootA\0" \
+	"root_partition=rootfsA\0" \
+	"kdump_buf=1M\0" \
+	"findpart=rollback; if test ${boot_partition} = bootB; then mmcbootpart=4; else mmcbootpart=2; fi; if test ${root_partition} = rootfsB; then mmcpart=5; else mmcpart=3; fi;\0" \
+	"fdt_file=light-b-power.dtb\0" \
+	"uuid_rootfsA=80a5a8e9-c744-491a-93c1-4f4194fd690a\0" \
+	"uuid_rootfsB=80a5a8e9-c744-491a-93c1-4f4194fd690b\0" \
+	"partitions=name=table,size=2031KB;name=boot,size=200MiB,type=boot;name=root,size=4000MiB,type=linux,uuid=${uuid_rootfsA};name=bootB,size=200MiB,type=boot;name=rootB,size=4000MiB,type=linux,uuid=${uuid_rootfsB};name=data,size=-,type=linux\0" \
+	"finduuid=part uuid mmc ${mmcdev}:${mmcpart} uuid\0" \
+	"gpt_partition=gpt write mmc ${mmcdev} $partitions\0" \
+	"set_bootargs=setenv bootargs console=ttyS0,115200 root=PARTUUID=${uuid} rootfstype=ext4 rdinit=/sbin/init rootwait rw earlycon clk_ignore_unused loglevel=7 eth=$ethaddr rootrw=PARTLABEL=data init=/init rootinit=/sbin/init rootrwoptions=rw,noatime rootrwreset=${factory_reset} crashkernel=${kdump_buf}\0" \
+	"load_aon=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_aon_fpga.bin;cp.b $fwaddr $aon_ram_addr $filesize\0"\
+	"load_c906_audio=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_c906_audio.bin;cp.b $fwaddr $audio_ram_addr $filesize\0"\
 	"bootcmd_load=run findpart;run load_aon;run load_c906_audio; ext4load mmc ${mmcdev}:${mmcbootpart} $opensbi_addr fw_dynamic.bin; ext4load mmc ${mmcdev}:${mmcbootpart} $dtb_addr ${fdt_file}; ext4load mmc ${mmcdev}:${mmcbootpart} $kernel_addr Image\0" \
 	"bootcmd=run bootcmd_load; bootslave; run finduuid; run set_bootargs; booti $kernel_addr - $dtb_addr;\0" \
+	"factory_reset=yes\0"\
+        "\0"
+#elif defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_REF)
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"splashimage=0x30000000\0" \
+	"splashpos=m,m\0" \
+	"fdt_high=0xffffffffffffffff\0" \
+	"opensbi_addr=0x0\0" \
+	"dtb_addr=0x01f00000\0" \
+	"kernel_addr=0x00200000\0" \
+	"aon_ram_addr=0xffffef8000\0" \
+	"audio_ram_addr=0xffc0000000\0" \
+	"fwaddr=0x10000000\0"\
+	"mmcdev=0\0" \
+	"boot_partition=bootA\0" \
+	"root_partition=rootfsA\0" \
+	ENV_KERNEL_LOGLEVEL \
+	"kdump_buf=1M\0" \
+	ENV_STR_BOOT_DELAY \
+	"findpart=rollback; if test ${boot_partition} = bootB; then mmcbootpart=4; else mmcbootpart=2; fi; if test ${root_partition} = rootfsB; then mmcpart=5; else mmcpart=3; fi;\0" \
+	"fdt_file=light-ant-ref.dtb\0" \
+	"uuid_rootfsA=80a5a8e9-c744-491a-93c1-4f4194fd690a\0" \
+	"uuid_rootfsB=80a5a8e9-c744-491a-93c1-4f4194fd690b\0" \
+	"partitions=name=table,size=2031KB;name=boot,size=200MiB,type=boot;name=root,size=4000MiB,type=linux,uuid=${uuid_rootfsA};name=bootB,size=200MiB,type=boot;name=rootB,size=4000MiB,type=linux,uuid=${uuid_rootfsB};name=data,size=-,type=linux\0" \
+	"finduuid=part uuid mmc ${mmcdev}:${mmcpart} uuid\0" \
+	"gpt_partition=gpt write mmc ${mmcdev} $partitions\0" \
+	"set_bootargs=setenv bootargs console=ttyS0,115200 root=PARTUUID=${uuid} rootfstype=ext4 rdinit=/sbin/init rootwait rw earlycon clk_ignore_unused loglevel=${kernel_loglevel} eth=$ethaddr rootrw=PARTLABEL=data init=/init rootinit=/sbin/init rootrwoptions=rw,noatime rootrwreset=${factory_reset} crashkernel=${kdump_buf}\0" \
+	"load_aon=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_aon_fpga.bin;cp.b $fwaddr $aon_ram_addr $filesize\0"\
+	"load_c906_audio=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_c906_audio.bin;cp.b $fwaddr $audio_ram_addr $filesize\0"\
+	"bootcmd_load=run findpart;run load_aon;run load_c906_audio; ext4load mmc ${mmcdev}:${mmcbootpart} $opensbi_addr fw_dynamic.bin; ext4load mmc ${mmcdev}:${mmcbootpart} $dtb_addr ${fdt_file}; ext4load mmc ${mmcdev}:${mmcbootpart} $kernel_addr Image\0" \
+	"bootcmd=run bootcmd_load; bootslave; run finduuid; run set_bootargs; booti $kernel_addr - $dtb_addr;\0" \
+	"factory_reset=yes\0"\
         "\0"
 #elif defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_DISCRETE)
 #define CONFIG_EXTRA_ENV_SETTINGS \
@@ -263,13 +378,100 @@
 	"mmcdev=0\0" \
 	"boot_partition=bootA\0" \
 	"root_partition=rootfsA\0" \
-	"findpart=if test ${boot_partition} = bootB; then mmcbootpart=4; else mmcbootpart=2; fi; if test ${root_partition} = rootfsB; then mmcpart=5; else mmcpart=3; fi;\0" \
+	"kdump_buf=1M\0" \
+	"findpart=rollback; if test ${boot_partition} = bootB; then mmcbootpart=4; else mmcbootpart=2; fi; if test ${root_partition} = rootfsB; then mmcpart=5; else mmcpart=3; fi;\0" \
 	"fdt_file=light-ant-discrete.dtb\0" \
 	"uuid_rootfsA=80a5a8e9-c744-491a-93c1-4f4194fd690a\0" \
 	"uuid_rootfsB=80a5a8e9-c744-491a-93c1-4f4194fd690b\0" \
 	"partitions=name=table,size=2031KB;name=boot,size=200MiB,type=boot;name=root,size=4000MiB,type=linux,uuid=${uuid_rootfsA};name=bootB,size=200MiB,type=boot;name=rootB,size=4000MiB,type=linux,uuid=${uuid_rootfsB};name=data,size=-,type=linux\0" \
 	"finduuid=part uuid mmc ${mmcdev}:${mmcpart} uuid\0" \
 	"gpt_partition=gpt write mmc ${mmcdev} $partitions\0" \
+	"set_bootargs=setenv bootargs console=ttyS0,115200 root=PARTUUID=${uuid} rootfstype=ext4 rdinit=/sbin/init rootwait rw earlycon clk_ignore_unused loglevel=7 eth=$ethaddr rootrw=PARTLABEL=data init=/init rootinit=/sbin/init rootrwoptions=rw,noatime rootrwreset=${factory_reset} crashkernel=${kdump_buf}\0" \
+	"load_aon=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_aon_fpga.bin;cp.b $fwaddr $aon_ram_addr $filesize\0"\
+	"load_c906_audio=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_c906_audio.bin;cp.b $fwaddr $audio_ram_addr $filesize\0"\
+	"bootcmd_load=run findpart;run load_aon;run load_c906_audio; ext4load mmc ${mmcdev}:${mmcbootpart} $opensbi_addr fw_dynamic.bin; ext4load mmc ${mmcdev}:${mmcbootpart} $dtb_addr ${fdt_file}; ext4load mmc ${mmcdev}:${mmcbootpart} $kernel_addr Image\0" \
+	"bootcmd=run bootcmd_load; bootslave; run finduuid; run set_bootargs; booti $kernel_addr - $dtb_addr;\0" \
+	"factory_reset=yes\0"\
+        "\0"
+#elif defined (CONFIG_TARGET_LIGHT_FM_C910_BEAGLE)
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"splashimage=0x30000000\0" \
+	"splashpos=m,m\0" \
+	"fdt_high=0xffffffffffffffff\0" \
+	"opensbi_addr=0x0\0" \
+	"dtb_addr=0x01f00000\0" \
+	"kernel_addr=0x00200000\0" \
+	"aon_ram_addr=0xffffef8000\0" \
+	"audio_ram_addr=0xffc0000000\0" \
+	"fwaddr=0x10000000\0"\
+	"mmcdev=0\0" \
+	"boot_partition=bootA\0" \
+	"root_partition=rootfsA\0" \
+	"kdump_buf=500M\0" \
+	"findpart=rollback; if test ${boot_partition} = bootB; then mmcbootpart=4; else mmcbootpart=2; fi; if test ${root_partition} = rootfsB; then mmcpart=5; else mmcpart=3; fi;\0" \
+	"fdt_file=light-beagle.dtb\0" \
+	"uuid_rootfsA=80a5a8e9-c744-491a-93c1-4f4194fd690a\0" \
+	"uuid_rootfsB=80a5a8e9-c744-491a-93c1-4f4194fd690b\0" \
+	"partitions=name=table,size=2031KB;name=boot,size=200MiB,type=boot;name=root,size=4000MiB,type=linux,uuid=${uuid_rootfsA};name=bootB,size=200MiB,type=boot;name=rootB,size=4000MiB,type=linux,uuid=${uuid_rootfsB};name=data,size=-,type=linux\0" \
+	"finduuid=part uuid mmc ${mmcdev}:${mmcpart} uuid\0" \
+	"gpt_partition=gpt write mmc ${mmcdev} $partitions\0" \
+	"set_bootargs=setenv bootargs console=ttyS0,115200 root=PARTUUID=${uuid} rootfstype=ext4 rdinit=/sbin/init rootwait rw earlycon clk_ignore_unused loglevel=7 eth=$ethaddr rootrw=PARTLABEL=data init=/init rootinit=/sbin/init rootrwoptions=rw,noatime rootrwreset=${factory_reset} crashkernel=${kdump_buf}\0" \
+	"load_aon=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_aon_fpga.bin;cp.b $fwaddr $aon_ram_addr $filesize\0"\
+	"load_c906_audio=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_c906_audio.bin;cp.b $fwaddr $audio_ram_addr $filesize\0"\
+	"bootcmd_load=run findpart;run load_aon;run load_c906_audio; ext4load mmc ${mmcdev}:${mmcbootpart} $opensbi_addr fw_dynamic.bin; ext4load mmc ${mmcdev}:${mmcbootpart} $dtb_addr ${fdt_file}; ext4load mmc ${mmcdev}:${mmcbootpart} $kernel_addr Image\0" \
+	"bootcmd=run bootcmd_load; bootslave; run finduuid; run set_bootargs; booti $kernel_addr - $dtb_addr;\0" \
+	"factory_reset=yes\0"\
+        "\0"
+#elif defined (CONFIG_TARGET_LIGHT_FM_C910_LPI4A)
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"splashimage=0x30000000\0" \
+	"splashpos=m,m\0" \
+	"fdt_high=0xffffffffffffffff\0" \
+	"opensbi_addr=0x0\0" \
+	"dtb_addr=0x01f00000\0" \
+	"kernel_addr=0x00200000\0" \
+	"aon_ram_addr=0xffffef8000\0" \
+	"audio_ram_addr=0xffc0000000\0" \
+	"fwaddr=0x10000000\0"\
+	"mmcdev=0\0" \
+	"boot_partition=bootA\0" \
+	"root_partition=rootfsA\0" \
+	"kdump_buf=500M\0" \
+	"findpart=rollback; if test ${boot_partition} = bootB; then mmcbootpart=4; else mmcbootpart=2; fi; if test ${root_partition} = rootfsB; then mmcpart=5; else mmcpart=3; fi;\0" \
+	"fdt_file=light-lpi4a.dtb\0" \
+	"uuid_rootfsA=80a5a8e9-c744-491a-93c1-4f4194fd690a\0" \
+	"uuid_rootfsB=80a5a8e9-c744-491a-93c1-4f4194fd690b\0" \
+	"partitions=name=table,size=2031KB;name=boot,size=200MiB,type=boot;name=root,size=4000MiB,type=linux,uuid=${uuid_rootfsA};name=bootB,size=200MiB,type=boot;name=rootB,size=4000MiB,type=linux,uuid=${uuid_rootfsB};name=data,size=-,type=linux\0" \
+	"finduuid=part uuid mmc ${mmcdev}:${mmcpart} uuid\0" \
+	"gpt_partition=gpt write mmc ${mmcdev} $partitions\0" \
+	"set_bootargs=setenv bootargs console=ttyS0,115200 root=PARTUUID=${uuid} rootfstype=ext4 rdinit=/sbin/init rootwait rw earlycon clk_ignore_unused loglevel=7 eth=$ethaddr rootrw=PARTLABEL=data init=/init rootinit=/sbin/init rootrwoptions=rw,noatime rootrwreset=${factory_reset} crashkernel=${kdump_buf}\0" \
+	"load_aon=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_aon_fpga.bin;cp.b $fwaddr $aon_ram_addr $filesize\0"\
+	"load_c906_audio=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_c906_audio.bin;cp.b $fwaddr $audio_ram_addr $filesize\0"\
+	"bootcmd_load=run findpart;run load_aon;run load_c906_audio; ext4load mmc ${mmcdev}:${mmcbootpart} $opensbi_addr fw_dynamic.bin; ext4load mmc ${mmcdev}:${mmcbootpart} $dtb_addr ${fdt_file}; ext4load mmc ${mmcdev}:${mmcbootpart} $kernel_addr Image\0" \
+	"bootcmd=run bootcmd_load; bootslave; run finduuid; run set_bootargs; booti $kernel_addr - $dtb_addr;\0" \
+	"factory_reset=yes\0"\
+        "\0"
+#elif defined (CONFIG_TARGET_LIGHT_FM_C910_A_REF)
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"splashimage=0x30000000\0" \
+	"splashpos=m,m\0" \
+	"fdt_high=0xffffffffffffffff\0" \
+	"opensbi_addr=0x0\0" \
+	"dtb_addr=0x01f00000\0" \
+	"kernel_addr=0x00200000\0" \
+	"aon_ram_addr=0xffffef8000\0" \
+	"audio_ram_addr=0xffc0000000\0" \
+	"fwaddr=0x10000000\0"\
+	"mmcdev=0\0" \
+	"boot_partition=bootA\0" \
+	"root_partition=rootfsA\0" \
+	"findpart=if test ${boot_partition} = bootB; then mmcbootpart=4; else mmcbootpart=2; fi; if test ${root_partition} = rootfsB; then mmcpart=5; else mmcpart=3; fi;\0" \
+	"fdt_file=light-a-ref.dtb\0" \
+	"uuid_rootfsA=80a5a8e9-c744-491a-93c1-4f4194fd690a\0" \
+	"uuid_rootfsB=80a5a8e9-c744-491a-93c1-4f4194fd690b\0" \
+	"partitions=name=table,size=2031KB;name=boot,size=200MiB,type=boot;name=root,size=4000MiB,type=linux,uuid=${uuid_rootfsA};name=bootB,size=200MiB,type=boot;name=rootB,size=4000MiB,type=linux,uuid=${uuid_rootfsB};name=data,size=-,type=linux\0" \
+	"finduuid=part uuid mmc ${mmcdev}:${mmcpart} uuid\0" \
+	"gpt_partition=gpt write mmc ${mmcdev} $partitions\0" \
 	"set_bootargs=setenv bootargs console=ttyS0,115200 root=PARTUUID=${uuid} rootfstype=ext4 rdinit=/sbin/init rootwait rw earlycon clk_ignore_unused loglevel=7 eth=$ethaddr rootrw=PARTLABEL=data init=/init rootinit=/sbin/init rootrwoptions=rw,noatime\0" \
 	"load_aon=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_aon_fpga.bin;cp.b $fwaddr $aon_ram_addr $filesize\0"\
 	"load_c906_audio=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_c906_audio.bin;cp.b $fwaddr $audio_ram_addr $filesize\0"\
@@ -290,18 +492,20 @@
 	"mmcdev=0\0" \
 	"boot_partition=bootA\0" \
 	"root_partition=rootfsA\0" \
-	"findpart=if test ${boot_partition} = bootB; then mmcbootpart=4; else mmcbootpart=2; fi; if test ${root_partition} = rootfsB; then mmcpart=5; else mmcpart=3; fi;\0" \
-	"fdt_file=light-a-val.dtb\0" \
+	"kdump_buf=500M\0" \
+	"findpart=rollback; if test ${boot_partition} = bootB; then mmcbootpart=4; else mmcbootpart=2; fi; if test ${root_partition} = rootfsB; then mmcpart=5; else mmcpart=3; fi;\0" \
+	"fdt_file=light-a-val-dsi0-hdmi.dtb\0" \
 	"uuid_rootfsA=80a5a8e9-c744-491a-93c1-4f4194fd690a\0" \
 	"uuid_rootfsB=80a5a8e9-c744-491a-93c1-4f4194fd690b\0" \
 	"partitions=name=table,size=2031KB;name=boot,size=200MiB,type=boot;name=root,size=4000MiB,type=linux,uuid=${uuid_rootfsA};name=bootB,size=200MiB,type=boot;name=rootB,size=4000MiB,type=linux,uuid=${uuid_rootfsB};name=data,size=-,type=linux\0" \
 	"finduuid=part uuid mmc ${mmcdev}:${mmcpart} uuid\0" \
 	"gpt_partition=gpt write mmc ${mmcdev} $partitions\0" \
-	"set_bootargs=setenv bootargs console=ttyS0,115200 root=PARTUUID=${uuid} rootfstype=ext4 rdinit=/sbin/init rootwait rw earlycon clk_ignore_unused loglevel=7 eth=$ethaddr rootrw=PARTLABEL=data init=/init rootinit=/sbin/init rootrwoptions=rw,noatime\0" \
+	"set_bootargs=setenv bootargs console=ttyS0,115200 root=PARTUUID=${uuid} rootfstype=ext4 rdinit=/sbin/init rootwait rw earlycon clk_ignore_unused loglevel=7 eth=$ethaddr rootrw=PARTLABEL=data init=/init rootinit=/sbin/init rootrwoptions=rw,noatime rootrwreset=${factory_reset} crashkernel=${kdump_buf}\0" \
 	"load_aon=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_aon_fpga.bin;cp.b $fwaddr $aon_ram_addr $filesize\0"\
 	"load_c906_audio=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_c906_audio.bin;cp.b $fwaddr $audio_ram_addr $filesize\0"\
 	"bootcmd_load=run findpart;run load_aon;run load_c906_audio; ext4load mmc ${mmcdev}:${mmcbootpart} $opensbi_addr fw_dynamic.bin; ext4load mmc ${mmcdev}:${mmcbootpart} $dtb_addr ${fdt_file}; ext4load mmc ${mmcdev}:${mmcbootpart} $kernel_addr Image\0" \
 	"bootcmd=run bootcmd_load; bootslave; run finduuid; run set_bootargs; booti $kernel_addr - $dtb_addr;\0" \
+	"factory_reset=yes\0"\
         "\0"
 #endif
 #endif

include/fastboot.h

@@ -48,6 +48,7 @@ enum {
 	FASTBOOT_COMMAND_ACMD,
 	FASTBOOT_COMMAND_UCMD,
 #endif
+	FASTBOOT_COMMAND_OEM_COMMAND,
 
 	FASTBOOT_COMMAND_COUNT
 };

include/thead/clock_config.h

@@ -29,9 +29,16 @@ enum light_pll_clktype {
 	LIGHT_DPU1_PLL,
 };
 
+struct clk_info {
+	const char *clk_name;
+	enum clk_device_type clk_dev_type;
+};
+
 int clk_config(void);
 int clk_light_set_rate(const char *clk_name, enum clk_device_type clk_dev_type, unsigned long rate);
 unsigned long clk_light_get_rate(const char *clk_name, enum clk_device_type clk_dev_type);
+int clk_light_set_parent(const char *clk_name, const char *parent);
+const struct clk_info *clk_light_get_parent(const char *clk_name);
 
 void ap_dpu_clk_endisable(bool en);
 void ap_hdmi_clk_endisable(bool en);

lib/sec_library/include/aes.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2017-2021 Alibaba Group Holding Limited
+ * Copyright (C) 2017-2020 Alibaba Group Holding Limited
  */
 
 /******************************************************************************
@@ -14,23 +14,86 @@
 #define _DRV_AES_H_
 
 #include <stdint.h>
-#include <drv/common.h>
+#include "common.h"
 
 #ifdef __cplusplus
 extern "C" {
 #endif
 
 /*----- Encrypt & Decrypt: Config key length -----*/
+#define AES_KEY_LEN_BYTES_32  (32)
+#define AES_KEY_LEN_BYTES_24  (24)
+#define AES_KEY_LEN_BYTES_16  (16)
+
+#define AES_BLOCK_IV_SIZE     (16)
+#define AES_BLOCK_TAG_SIZE    (16)
+#define AES_BLOCK_CRYPTO_SIZE (16)
+
+#define AES_DIR_ENCRYPT       (1)
+#define AES_DIR_DECRYPT       (0)
+
+#define KEY_128_BITS          (0x08)
+#define KEY_192_BITS          (0x10)
+#define KEY_256_BITS          (0x18)
+
+#define AES_DMA_ENABLE        (1)
+#define AES_DMA_DISABLE       (0)
+
+/**
+\brief DES data transfer mode config
+*/
+typedef enum {
+    AES_SLAVE_MODE = 0U,         ///< slave mode
+    AES_DMA_MODE,                ///< dma mode
+} csi_aes_trans_mode_t;
+
+/**
+\brief AES Keylen type
+*/
 typedef enum {
     AES_KEY_LEN_BITS_128        = 0,       ///< 128 Data bits
     AES_KEY_LEN_BITS_192,                  ///< 192 Data bits
     AES_KEY_LEN_BITS_256                   ///< 256 Data bits
 } csi_aes_key_bits_t;
 
+/**
+\brief AES mode config
+*/
+typedef enum{
+    AES_MODE_ECB = 0,
+    AES_MODE_CBC = 0x20000020,
+    AES_MODE_CTR = 0x200001c0,
+    AES_MODE_CFB = 0x20000400,
+    AES_MODE_GCM = 0x20030040,
+    AES_MODE_CCM = 0x21D40040,
+    AES_MODE_OFB = 0x24000000,
+} csi_aes_mode_t;
+
+/**
+\brief AES state
+*/
+typedef struct {
+    uint32_t busy             : 1;        ///< Calculate busy flag
+    uint32_t error            : 1;        ///< Calculate error flag
+} csi_aes_state_t;
+
+/**
+\brief AES Context
+*/
+typedef struct {
+    uint32_t            key_len_byte;
+    uint8_t             key[32];          ///< Data block being processed
+    uint32_t            sca;
+    uint32_t            is_kdf;
+    uint32_t            is_dma;
+} csi_aes_context_t;
+
 /**
 \brief AES Ctrl Block
 */
 typedef struct {
+    csi_aes_state_t         state;
+    csi_aes_context_t       context;
     csi_dev_t               dev;
     void                    *priv;
 } csi_aes_t;
@@ -97,7 +160,7 @@ csi_error_t csi_aes_ecb_decrypt(csi_aes_t *aes, void *in, void *out, uint32_t si
   \param[in]   iv      Init vector
   \return      Error code \ref Csi_error_t
 */
-csi_error_t csi_aes_cbc_encrypt(csi_aes_t *aes, void *in, void *out, uint32_t size, void *iv);
+csi_error_t csi_aes_cbc_encrypt(csi_aes_t *aes, void *in, void *out, uint32_t size, void *iv) ;
 
 /**
   \brief       AES cbc decrypt
@@ -161,10 +224,9 @@ csi_error_t csi_aes_cfb8_decrypt(csi_aes_t *aes, void *in, void *out, uint32_t s
   \param[out]  out     Pointer to the result data
   \param[in]   size    The source data size
   \param[in]   iv      Init vector
-  \param[out]  num     The number of the 128-bit block we have used
   \return      Error code \ref csi_error_t
 */
-csi_error_t csi_aes_cfb128_decrypt(csi_aes_t *aes, void *in, void *out, uint32_t size, void *iv, uint32_t *num);
+csi_error_t csi_aes_cfb128_decrypt(csi_aes_t *aes, void *in, void *out, uint32_t size, void *iv);
 
 /**
   \brief       AES cfb128 encrypt
@@ -173,10 +235,9 @@ csi_error_t csi_aes_cfb128_decrypt(csi_aes_t *aes, void *in, void *out, uint32_t
   \param[out]  out     Pointer to the result data
   \param[in]   size    The source data size
   \param[in]   iv      Init vector
-  \param[out]  num     The number of the 128-bit block we have used
   \return      Error code \ref csi_error_t
 */
-csi_error_t csi_aes_cfb128_encrypt(csi_aes_t *aes, void *in, void *out, uint32_t size, void *iv, uint32_t *num);
+csi_error_t csi_aes_cfb128_encrypt(csi_aes_t *aes, void *in, void *out, uint32_t size, void *iv);
 
 /**
   \brief       AES ofb encrypt
@@ -185,22 +246,22 @@ csi_error_t csi_aes_cfb128_encrypt(csi_aes_t *aes, void *in, void *out, uint32_t
   \param[out]  out     Pointer to the result data
   \param[in]   size    The source data size
   \param[in]   iv      Init vector
-  \param[out]  num     The number of the 128-bit block we have used
+  \param[in]  key_len key bits
   \return      Error code \ref csi_error_t
 */
-csi_error_t csi_aes_ofb_encrypt(csi_aes_t *aes, void *in, void *out, uint32_t size, void *iv, uint32_t *num);
+csi_error_t csi_aes_ofb_encrypt(csi_aes_t *aes, void *in, void *out, uint32_t size, void *iv);
 
 /**
-  \brief       AES ofb decrypt
-  \param[in]   aes     Handle to operate
-  \param[in]   in      Pointer to the source data
-  \param[out]  out     Pointer to the result data
-  \param[in]   size    The source data size
-  \param[in]   iv      Init vector
-  \param[out]  num     The number of the 128-bit block we have used
-  \return      Error code \ref csi_error_t
+  \brief       Aes ofb decrypt
+  \param[in]   dev_aes     dev_aes handle to operate
+  \param[in]   in      Pointer to the Source data
+  \param[out]  out     Pointer to the Result data
+  \param[in]   size    the Source data size
+  \param[in]   iv      init vector
+  \param[in]  key_len key bits
+  \return      error code \ref csi_error_t
 */
-csi_error_t csi_aes_ofb_decrypt(csi_aes_t *aes, void *in, void *out, uint32_t size, void *iv, uint32_t *num);
+csi_error_t csi_aes_ofb_decrypt(csi_aes_t *aes, void *in, void *out,uint32_t size, void *iv);
 
 /**
   \brief       AES ctr encrypt
@@ -208,20 +269,10 @@ csi_error_t csi_aes_ofb_decrypt(csi_aes_t *aes, void *in, void *out, uint32_t si
   \param[in]   in               Pointer to the source data
   \param[out]  out              Pointer to the result data
   \param[in]   size             The source data size
-  \param[in]   nonce_counter    Pointer to the 128-bit nonce and counter
-  \param[in]   stream_block     Pointer to the saved stream-block for resuming
   \param[in]   iv               Init vector
-  \param[out]  num              The number of the 128-bit block we have used
   \return      Error code \ref csi_error_t
 */
-csi_error_t csi_aes_ctr_encrypt(csi_aes_t *aes,
-                                void *in,
-                                void *out,
-                                uint32_t size,
-                                uint8_t nonce_counter[16],
-                                uint8_t stream_block[16],
-                                void *iv,
-                                uint32_t *num);
+csi_error_t csi_aes_ctr_encrypt(csi_aes_t *aes,void *in,void *out,uint32_t size,void *iv);
 
 /**
   \brief       AES ctr decrypt
@@ -229,20 +280,56 @@ csi_error_t csi_aes_ctr_encrypt(csi_aes_t *aes,
   \param[in]   in               Pointer to the source data
   \param[out]  out              Pointer to the result data
   \param[in]   size             The source data size
-  \param[in]   nonce_counter    Pointer to the 128-bit nonce and counter
-  \param[in]   stream_block     Pointer to the saved stream-block for resuming
   \param[in]   iv               Init vecotr
-  \param[out]  num              The number of the 128-bit block we have used
   \return      Error code \ref csi_error_t
 */
-csi_error_t csi_aes_ctr_decrypt(csi_aes_t *aes,
-                                void *in,
-                                void *out,
-                                uint32_t size,
-                                uint8_t nonce_counter[16],
-                                uint8_t stream_block[16],
-                                void *iv,
-                                uint32_t *num);
+csi_error_t csi_aes_ctr_decrypt(csi_aes_t *aes,void *in,void *out,uint32_t size,void *iv);
+
+/**
+  \brief       Aes gcm encrypt
+  \param[in]   dev_aes              dev_aes handle to operate
+  \param[in]   in               Pointer to the Source data
+  \param[out]  out              Pointer to the Result data
+  \param[in]   size             the Source data size
+  \param[in]   iv               init vector
+  \return      error code \ref csi_error_t
+*/
+csi_error_t csi_aes_gcm_encrypt(csi_aes_t *aes, void *in, void *out,uint32_t size, uint32_t add_len, void *iv);
+
+/**
+  \brief       Aes gcm decrypt
+  \param[in]   dev_aes              dev_aes handle to operate
+  \param[in]   in               Pointer to the Source data.
+  \param[out]  out              Pointer to the Result data
+  \param[in]   size             the Source data size
+  \param[in]   iv               init vecotr
+  \return      error code \ref csi_error_t
+*/
+csi_error_t csi_aes_gcm_decrypt(csi_aes_t *aes, void *in, void *out,uint32_t size, uint32_t add_len, void *iv);
+
+/**
+  \brief       Aes ccm encrypt
+  \param[in]   dev_aes              dev_aes handle to operate
+  \param[in]   in               Pointer to the Source data
+  \param[out]  out              Pointer to the Result data
+  \param[in]   size             the Source data size
+  \param[in]   iv               init vector
+  \param[in]   tag_out          tag output
+  \return      error code \ref csi_error_t
+*/
+csi_error_t csi_aes_ccm_encrypt(csi_aes_t *aes, void *in, void *out,uint32_t size, uint32_t add_len, void *iv, uint8_t *tag_out);
+
+/**
+  \brief       Aes ccm decrypt
+  \param[in]   dev_aes              dev_aes handle to operate
+  \param[in]   in               Pointer to the Source data
+  \param[out]  out              Pointer to the Result data
+  \param[in]   size             the Source data size
+  \param[in]   iv               init vecotr
+  \param[in]   tag_out          tag output
+  \return      error code \ref csi_error_t
+*/
+csi_error_t csi_aes_ccm_decrypt(csi_aes_t *aes, void *in, void *out,uint32_t size, uint32_t add_len, void *iv, uint8_t *tag_out);
 
 /**
   \brief       Enable AES power manage
@@ -258,6 +345,13 @@ csi_error_t csi_aes_enable_pm(csi_aes_t *aes);
 */
 void csi_aes_disable_pm(csi_aes_t *aes);
 
+/**
+  \brief       Config AES data transfer mode
+  \param[in]   mode    \ref csi_des_trans_mode_t 
+  \return      None
+*/
+void csi_aes_trans_config(csi_aes_t *aes, csi_aes_trans_mode_t mode);
+
 #ifdef __cplusplus
 }
 #endif

lib/sec_library/include/common.h

@@ -0,0 +1,144 @@
+/*
+ * Copyright (C) 2017-2020 Alibaba Group Holding Limited
+ */
+
+/******************************************************************************
+ * @file     drv/common.h
+ * @brief    Header File for Common Driver
+ * @version  V1.0
+ * @date     31. March 2020
+ * @model    common
+ ******************************************************************************/
+
+#ifndef _DRV_COMMON_H_
+#define _DRV_COMMON_H_
+
+#include <stdint.h>
+#include <stdio.h>
+#include <string.h>
+#include <stdbool.h>
+#include "list.h"
+#include "dev_tag.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef CONFIG_DEBUG_MODE
+#define CSI_ASSERT(expr)                            \
+    do {                                        \
+        if ((unsigned long)expr == (unsigned long)NULL) {   \
+            printf("PROGRAM ASSERT\n");         \
+            while(1);                           \
+        }                                       \
+    } while(0);
+#else
+#define CSI_ASSERT(expr)        ((void)0U)
+#endif
+
+#ifdef CONFIG_PARAM_NOT_CHECK
+#define CSI_PARAM_CHK(para, err)                    \
+    do {                                            \
+        if ((unsigned long)para == (unsigned long)NULL) {       \
+            return (err);                           \
+        }                                           \
+    } while (0)
+
+#define CSI_PARAM_CHK_NORETVAL(para)                \
+    do {                                            \
+        if ((unsigned long)para == (unsigned long)NULL) {       \
+            return;                                 \
+        }                                           \
+    } while (0)
+#else
+#define CSI_PARAM_CHK(para, err)
+#define CSI_PARAM_CHK_NORETVAL(para)
+#endif
+
+#define CSI_EXAMPLE_RESULT(val)                     \
+    do {                                            \
+        if(val>=0)                                  \
+        {                                           \
+            printf("-*success*-\n");                \
+        }                                           \
+        else                                        \
+        {                                           \
+            printf("-*fail*-\n");                   \
+        }                                           \
+    } while (0);
+
+typedef enum {
+    CSI_OK            =  0,
+    CSI_ERROR         = -1,
+    CSI_BUSY          = -2,
+    CSI_TIMEOUT       = -3,
+    CSI_UNSUPPORTED   = -4,
+    CSI_INVALID_PARAM = -5,
+    CSI_CRYPT_FAIL    = -6,
+} csi_error_t;
+
+typedef struct {
+    uint8_t    readable;
+    uint8_t    writeable;
+    uint8_t    error;
+} csi_state_t;
+
+typedef struct csi_dev csi_dev_t;
+
+#ifdef CONFIG_PM
+typedef enum {
+    PM_DEV_SUSPEND,
+    PM_DEV_RESUME,
+} csi_pm_dev_action_t;
+
+typedef enum {
+    PM_MODE_RUN                  = 0,   ///< Running mode
+    PM_MODE_SLEEP_1,                    ///< Sleep LV1 mode
+    PM_MODE_SLEEP_2,                    ///< Sleep LV2 mode
+    PM_MODE_DEEP_SLEEP_1,               ///< Deep sleep LV1 mode
+    PM_MODE_DEEP_SLEEP_2,               ///< Deep sleep LV2 mode
+    PM_MODE_DEEP_SLEEP_3,               ///< Deep sleep LV3 mode
+} csi_pm_mode_t;
+
+typedef struct {
+    slist_t     next;
+    csi_error_t (*pm_action)(csi_dev_t *dev, csi_pm_dev_action_t action);
+    uint32_t    *reten_mem;
+    uint32_t    size;
+} csi_pm_dev_t;
+#include <drv/pm.h>
+#endif
+
+struct csi_dev {
+    unsigned long reg_base;
+    uint8_t       irq_num;
+    uint8_t       idx;
+    uint16_t      dev_tag;
+    void          (*irq_handler)(void *);
+#ifdef CONFIG_PM
+    csi_pm_dev_t pm_dev;
+#endif
+};
+
+#define HANDLE_REG_BASE(handle)     (handle->dev.reg_base)
+#define HANDLE_IRQ_NUM(handle)      (handle->dev.irq_num)
+#define HANDLE_DEV_IDX(handle)      (handle->dev.idx)
+#define HANDLE_IRQ_HANDLER(handle)  (handle->dev.irq_handler)
+
+typedef struct {
+    unsigned long    reg_base;
+    uint8_t          irq_num;
+    uint8_t          idx;
+    uint16_t         dev_tag;
+} csi_perip_info_t;
+
+csi_error_t target_get(csi_dev_tag_t dev_tag, uint32_t idx, csi_dev_t *dev);
+csi_error_t target_get_optimal_dma_channel(void *dma_list, uint32_t ctrl_num, csi_dev_t *parent_dev, void *ch_info);
+void msleep(uint32_t ms);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _DRV_COMMON_H_ */
+

lib/sec_library/include/core/README.txt

@@ -0,0 +1 @@
+Just include csi_core.h!

lib/sec_library/include/core/cmsis/ARMCM0.h

@@ -0,0 +1,126 @@
+/**************************************************************************//**
+ * @file     ARMCM0.h
+ * @brief    CMSIS Core Peripheral Access Layer Header File for
+ *           ARMCM0 Device
+ * @version  V5.3.1
+ * @date     09. July 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef ARMCM0_H
+#define ARMCM0_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/* -------------------------  Interrupt Number Definition  ------------------------ */
+
+typedef enum IRQn
+{
+/* -------------------  Processor Exceptions Numbers  ----------------------------- */
+  NonMaskableInt_IRQn           = -14,     /*  2 Non Maskable Interrupt */
+  HardFault_IRQn                = -13,     /*  3 HardFault Interrupt */
+
+
+
+  SVCall_IRQn                   =  -5,     /* 11 SV Call Interrupt */
+
+  PendSV_IRQn                   =  -2,     /* 14 Pend SV Interrupt */
+  SysTick_IRQn                  =  -1,     /* 15 System Tick Interrupt */
+
+/* -------------------  Processor Interrupt Numbers  ------------------------------ */
+  Interrupt0_IRQn               =   0,
+  Interrupt1_IRQn               =   1,
+  Interrupt2_IRQn               =   2,
+  Interrupt3_IRQn               =   3,
+  Interrupt4_IRQn               =   4,
+  Interrupt5_IRQn               =   5,
+  Interrupt6_IRQn               =   6,
+  Interrupt7_IRQn               =   7,
+  Interrupt8_IRQn               =   8,
+  Interrupt9_IRQn               =   9
+  /* Interrupts 10 .. 31 are left out */
+} IRQn_Type;
+
+
+/* ================================================================================ */
+/* ================      Processor and Core Peripheral Section     ================ */
+/* ================================================================================ */
+
+/* -------  Start of section using anonymous unions and disabling warnings  ------- */
+#if   defined (__CC_ARM)
+  #pragma push
+  #pragma anon_unions
+#elif defined (__ICCARM__)
+  #pragma language=extended
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wc11-extensions"
+  #pragma clang diagnostic ignored "-Wreserved-id-macro"
+#elif defined (__GNUC__)
+  /* anonymous unions are enabled by default */
+#elif defined (__TMS470__)
+  /* anonymous unions are enabled by default */
+#elif defined (__TASKING__)
+  #pragma warning 586
+#elif defined (__CSMC__)
+  /* anonymous unions are enabled by default */
+#else
+  #warning Not supported compiler type
+#endif
+
+
+/* --------  Configuration of Core Peripherals  ----------------------------------- */
+#define __CM0_REV                 0x0000U   /* Core revision r0p0 */
+#define __MPU_PRESENT             0U        /* no MPU present */
+#define __VTOR_PRESENT            0U        /* no VTOR present */
+#define __NVIC_PRIO_BITS          2U        /* Number of Bits used for Priority Levels */
+#define __Vendor_SysTickConfig    0U        /* Set to 1 if different SysTick Config is used */
+
+#include "core_cm0.h"                       /* Processor and core peripherals */
+#include "system_ARMCM0.h"                  /* System Header */
+
+
+/* --------  End of section using anonymous unions and disabling warnings  -------- */
+#if   defined (__CC_ARM)
+  #pragma pop
+#elif defined (__ICCARM__)
+  /* leave anonymous unions enabled */
+#elif (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
+  #pragma clang diagnostic pop
+#elif defined (__GNUC__)
+  /* anonymous unions are enabled by default */
+#elif defined (__TMS470__)
+  /* anonymous unions are enabled by default */
+#elif defined (__TASKING__)
+  #pragma warning restore
+#elif defined (__CSMC__)
+  /* anonymous unions are enabled by default */
+#else
+  #warning Not supported compiler type
+#endif
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* ARMCM0_H */

lib/sec_library/include/core/cmsis/cmsis_compiler.h

@@ -0,0 +1,271 @@
+/**************************************************************************//**
+ * @file     cmsis_compiler.h
+ * @brief    CMSIS compiler generic header file
+ * @version  V5.1.0
+ * @date     09. October 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_COMPILER_H
+#define __CMSIS_COMPILER_H
+
+#include <stdint.h>
+
+/*
+ * Arm Compiler 4/5
+ */
+#if   defined ( __CC_ARM )
+  #include "cmsis_armcc.h"
+
+
+/*
+ * Arm Compiler 6.6 LTM (armclang)
+ */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100)
+  #include "cmsis_armclang_ltm.h"
+
+  /*
+ * Arm Compiler above 6.10.1 (armclang)
+ */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100)
+  #include "cmsis_armclang.h"
+
+
+/*
+ * GNU Compiler
+ */
+#elif defined ( __GNUC__ )
+  #include "cmsis_gcc.h"
+
+
+/*
+ * IAR Compiler
+ */
+#elif defined ( __ICCARM__ )
+  #include <cmsis_iccarm.h>
+
+
+/*
+ * TI Arm Compiler
+ */
+#elif defined ( __TI_ARM__ )
+  #include <cmsis_ccs.h>
+
+  #ifndef   __ASM
+    #define __ASM                                  __asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                               inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE                        static inline
+  #endif
+  #ifndef   __STATIC_FORCEINLINE
+    #define __STATIC_FORCEINLINE                   __STATIC_INLINE
+  #endif
+  #ifndef   __NO_RETURN
+    #define __NO_RETURN                            __attribute__((noreturn))
+  #endif
+  #ifndef   __USED
+    #define __USED                                 __attribute__((used))
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                                 __attribute__((weak))
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                               __attribute__((packed))
+  #endif
+  #ifndef   __PACKED_STRUCT
+    #define __PACKED_STRUCT                        struct __attribute__((packed))
+  #endif
+  #ifndef   __PACKED_UNION
+    #define __PACKED_UNION                         union __attribute__((packed))
+  #endif
+  #ifndef   __UNALIGNED_UINT32        /* deprecated */
+    struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT16_WRITE
+    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT16_READ
+    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT32_WRITE
+    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT32_READ
+    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #define __ALIGNED(x)                           __attribute__((aligned(x)))
+  #endif
+  #ifndef   __RESTRICT
+    #define __RESTRICT                             __restrict
+  #endif
+
+
+/*
+ * TASKING Compiler
+ */
+#elif defined ( __TASKING__ )
+  /*
+   * The CMSIS functions have been implemented as intrinsics in the compiler.
+   * Please use "carm -?i" to get an up to date list of all intrinsics,
+   * Including the CMSIS ones.
+   */
+
+  #ifndef   __ASM
+    #define __ASM                                  __asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                               inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE                        static inline
+  #endif
+  #ifndef   __STATIC_FORCEINLINE
+    #define __STATIC_FORCEINLINE                   __STATIC_INLINE
+  #endif
+  #ifndef   __NO_RETURN
+    #define __NO_RETURN                            __attribute__((noreturn))
+  #endif
+  #ifndef   __USED
+    #define __USED                                 __attribute__((used))
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                                 __attribute__((weak))
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                               __packed__
+  #endif
+  #ifndef   __PACKED_STRUCT
+    #define __PACKED_STRUCT                        struct __packed__
+  #endif
+  #ifndef   __PACKED_UNION
+    #define __PACKED_UNION                         union __packed__
+  #endif
+  #ifndef   __UNALIGNED_UINT32        /* deprecated */
+    struct __packed__ T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT16_WRITE
+    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT16_READ
+    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT32_WRITE
+    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT32_READ
+    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #define __ALIGNED(x)              __align(x)
+  #endif
+  #ifndef   __RESTRICT
+    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+    #define __RESTRICT
+  #endif
+
+
+/*
+ * COSMIC Compiler
+ */
+#elif defined ( __CSMC__ )
+   #include <cmsis_csm.h>
+
+ #ifndef   __ASM
+    #define __ASM                                  _asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                               inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE                        static inline
+  #endif
+  #ifndef   __STATIC_FORCEINLINE
+    #define __STATIC_FORCEINLINE                   __STATIC_INLINE
+  #endif
+  #ifndef   __NO_RETURN
+    // NO RETURN is automatically detected hence no warning here
+    #define __NO_RETURN
+  #endif
+  #ifndef   __USED
+    #warning No compiler specific solution for __USED. __USED is ignored.
+    #define __USED
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                                 __weak
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                               @packed
+  #endif
+  #ifndef   __PACKED_STRUCT
+    #define __PACKED_STRUCT                        @packed struct
+  #endif
+  #ifndef   __PACKED_UNION
+    #define __PACKED_UNION                         @packed union
+  #endif
+  #ifndef   __UNALIGNED_UINT32        /* deprecated */
+    @packed struct T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT16_WRITE
+    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT16_READ
+    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT32_WRITE
+    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT32_READ
+    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
+    #define __ALIGNED(x)
+  #endif
+  #ifndef   __RESTRICT
+    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+    #define __RESTRICT
+  #endif
+
+
+#else
+  #error Unknown compiler.
+#endif
+
+
+#endif /* __CMSIS_COMPILER_H */
+

lib/sec_library/include/core/cmsis/cmsis_version.h

@@ -0,0 +1,39 @@
+/**************************************************************************//**
+ * @file     cmsis_version.h
+ * @brief    CMSIS Core(M) Version definitions
+ * @version  V5.0.2
+ * @date     19. April 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CMSIS_VERSION_H
+#define __CMSIS_VERSION_H
+
+/*  CMSIS Version definitions */
+#define __CM_CMSIS_VERSION_MAIN  ( 5U)                                      /*!< [31:16] CMSIS Core(M) main version */
+#define __CM_CMSIS_VERSION_SUB   ( 1U)                                      /*!< [15:0]  CMSIS Core(M) sub version */
+#define __CM_CMSIS_VERSION       ((__CM_CMSIS_VERSION_MAIN << 16U) | \
+                                   __CM_CMSIS_VERSION_SUB           )       /*!< CMSIS Core(M) version number */
+#endif

lib/sec_library/include/core/cmsis/core_cm0.h

@@ -0,0 +1,949 @@
+/**************************************************************************//**
+ * @file     core_cm0.h
+ * @brief    CMSIS Cortex-M0 Core Peripheral Access Layer Header File
+ * @version  V5.0.6
+ * @date     13. March 2019
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM0_H_GENERIC
+#define __CORE_CM0_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_M0
+  @{
+ */
+
+#include "cmsis_version.h"
+ 
+/*  CMSIS CM0 definitions */
+#define __CM0_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)              /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM0_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)               /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __CM0_CMSIS_VERSION       ((__CM0_CMSIS_VERSION_MAIN << 16U) | \
+                                    __CM0_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M                (0U)                                   /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0U
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_FP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM0_H_DEPENDANT
+#define __CORE_CM0_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM0_REV
+    #define __CM0_REV               0x0000U
+    #warning "__CM0_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          2U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M0 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
+    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:1;               /*!< bit:      0  Reserved */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[1U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[31U];
+  __IOM uint32_t ICER[1U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RESERVED1[31U];
+  __IOM uint32_t ISPR[1U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[31U];
+  __IOM uint32_t ICPR[1U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[31U];
+        uint32_t RESERVED4[64U];
+  __IOM uint32_t IP[8U];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+        uint32_t RESERVED0;
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+        uint32_t RESERVED1;
+  __IOM uint32_t SHP[2U];                /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
+            Therefore they are not covered by the Cortex-M0 header file.
+  @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
+
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+/*#define NVIC_GetActive              __NVIC_GetActive             not available for Cortex-M0 */
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */
+#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */
+#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */
+
+
+/* Interrupt Priorities are WORD accessible only under Armv6-M                  */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
+#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
+#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
+
+#define __NVIC_SetPriorityGrouping(X) (void)(X)
+#define __NVIC_GetPriorityGrouping()  (0U)
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+  else
+  {
+    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           Address 0 must be mapped to SRAM.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+  uint32_t vectors = 0x0U;
+  (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+  uint32_t vectors = 0x0U;
+  return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4));
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+    return 0U;           /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */

lib/sec_library/include/core/cmsis/csi_core.h

@@ -0,0 +1,56 @@
+/*
+ * Copyright (C) 2017-2019 Alibaba Group Holding Limited
+ */
+
+
+/******************************************************************************
+ * @file     csi_core.h
+ * @brief    Header File for csi_core
+ * @version  V1.0
+ * @date     12. june 2019
+ ******************************************************************************/
+#ifndef _CSI_CORE_H_
+#define _CSI_CORE_H_
+
+#include <stddef.h>
+#include <cmsis_gcc.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef __GNUC__
+__STATIC_INLINE size_t csi_irq_save(void)
+{
+    uint32_t result;
+    result = __get_PRIMASK();
+    __disable_irq();
+    return (result);
+}
+
+__STATIC_INLINE void csi_irq_restore(size_t irq_state)
+{
+    __set_PRIMASK(irq_state);
+}
+#else
+static inline __asm size_t csi_irq_save(void)
+{
+    MRS     R0, PRIMASK
+    CPSID   I
+    BX      LR
+
+    return 0;
+}
+
+static inline __asm void csi_irq_restore(size_t irq_state)
+{
+    MSR     PRIMASK, R0
+    BX      LR
+}
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _CSI_CORE_H_ */

lib/sec_library/include/core/cmsis/system_ARMCM0.h

@@ -0,0 +1,55 @@
+/**************************************************************************//**
+ * @file     system_ARMCM0.h
+ * @brief    CMSIS Device System Header File for
+ *           ARMCM0 Device
+ * @version  V5.3.1
+ * @date     09. July 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef SYSTEM_ARMCM0_H
+#define SYSTEM_ARMCM0_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+extern uint32_t SystemCoreClock;     /*!< System Clock Frequency (Core Clock) */
+
+
+/**
+  \brief Setup the microcontroller system.
+
+   Initialize the System and update the SystemCoreClock variable.
+ */
+extern void SystemInit (void);
+
+
+/**
+  \brief  Update SystemCoreClock variable.
+
+   Updates the SystemCoreClock with current core Clock retrieved from cpu registers.
+ */
+extern void SystemCoreClockUpdate (void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SYSTEM_ARMCM0_H */

lib/sec_library/include/core/core_810.h

@@ -0,0 +1,873 @@
+/*
+ * Copyright (C) 2017-2019 Alibaba Group Holding Limited
+ */
+
+
+/******************************************************************************
+ * @file     core_ck810.h
+ * @brief    CSI CK810 Core Peripheral Access Layer Header File
+ * @version  V1.0
+ * @date     26. Jan 2018
+ ******************************************************************************/
+
+#ifndef __CORE_CK810_H_GENERIC
+#define __CORE_CK810_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*******************************************************************************
+ *                 CSI definitions
+ ******************************************************************************/
+/**
+  \ingroup CK810
+  @{
+ */
+
+/*  CSI CK810 definitions */
+#define __CK810_CSI_VERSION_MAIN  (0x04U)                                      /*!< [31:16] CSI HAL main version */
+#define __CK810_CSI_VERSION_SUB   (0x1EU)                                      /*!< [15:0]  CSI HAL sub version */
+#define __CK810_CSI_VERSION       ((__CK810_CSI_VERSION_MAIN << 16U) | \
+                                   __CK810_CSI_VERSION_SUB           )         /*!< CSI HAL version number */
+
+#ifndef __CK810
+#define __CK810                (0x0aU)                                         /*!< CK810 Core */
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not.
+*/
+#define __FPU_USED      1U
+
+#if defined ( __GNUC__ )
+#if defined (__VFP_FP__) && !defined(__SOFTFP__)
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CK810_H_GENERIC */
+
+#ifndef __CSI_GENERIC
+
+#ifndef __CORE_CK810_H_DEPENDANT
+#define __CORE_CK810_H_DEPENDANT
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#ifndef __CK810_REV
+#define __CK810_REV               0x0000U
+#endif
+
+#ifndef __GSR_GCR_PRESENT
+#define __GSR_GCR_PRESENT         0U
+#endif
+
+#ifndef __ICACHE_PRESENT
+#define __ICACHE_PRESENT          1U
+#endif
+
+#ifndef __DCACHE_PRESENT
+#define __DCACHE_PRESENT          1U
+#endif
+
+#include <core/csi_gcc.h>
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CSI_glob_defs CSI Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+#define     __I      volatile             /*!< Defines 'read only' permissions */
+#else
+#define     __I      volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O      volatile             /*!< Defines 'write only' permissions */
+#define     __IO     volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const       /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile             /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile             /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group CK810 */
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+ ******************************************************************************/
+/**
+  \defgroup CSI_core_register Defines and Type Definitions
+  \brief Type definitions and defines for CK810 processor based devices.
+*/
+
+/**
+  \ingroup    CSI_core_register
+  \defgroup   CSI_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Access Processor Status Register(PSR)struct definition.
+ */
+typedef union {
+    struct {
+        uint32_t C: 1;                       /*!< bit:      0  Conditional code/Carry flag */
+        uint32_t AF: 1;                      /*!< bit:      1  Alternate register valid control bit */
+        uint32_t _reserved0: 2;              /*!< bit:  2.. 3  Reserved */
+        uint32_t FE: 1;                      /*!< bit:      4  Fast interrupt enable control bit */
+        uint32_t _reserved1: 1;              /*!< bit:      5  Reserved */
+        uint32_t IE: 1;                      /*!< bit:      6  Interrupt effective control bit */
+        uint32_t IC: 1;                      /*!< bit:      7  Interrupt control bit */
+        uint32_t EE: 1;                      /*!< bit:      8  Abnormally effective control bit */
+        uint32_t MM: 1;                      /*!< bit:      9  Unsymmetrical masking bit */
+        uint32_t _reserved2: 2;              /*!< bit: 10..11  Reserved */
+        uint32_t TE: 1;                      /*!< bit:     12  Trace transmission control bit */
+        uint32_t TP: 1;                      /*!< bit:     13  Pending trace exception set bit */
+        uint32_t TM: 2;                      /*!< bit: 14..15  Tracing mode bit */
+        uint32_t VEC: 8;                     /*!< bit: 16..23  Abnormal event vector value */
+        uint32_t _reserved3: 7;              /*!< bit: 24..30  Reserved */
+        uint32_t S: 1;                       /*!< bit:     31  Superuser mode set bit */
+    } b;                                     /*!< Structure    Access by bit */
+    uint32_t w;                              /*!< Type         Access by whole register */
+} PSR_Type;
+
+/* PSR Register Definitions */
+#define PSR_S_Pos                          31U                                            /*!< PSR: S Position */
+#define PSR_S_Msk                          (0x1UL << PSR_S_Pos)                           /*!< PSR: S Mask */
+
+#define PSR_VEC_Pos                        16U                                            /*!< PSR: VEC Position */
+#define PSR_VEC_Msk                        (0xFFUL << PSR_VEC_Pos)                        /*!< PSR: VEC Mask */
+
+#define PSR_TM_Pos                         14U                                            /*!< PSR: TM Position */
+#define PSR_TM_Msk                         (0x3UL << PSR_TM_Pos)                          /*!< PSR: TM Mask */
+
+#define PSR_TP_Pos                         13U                                            /*!< PSR: TP Position */
+#define PSR_TP_Msk                         (0x1UL << PSR_TM_Pos)                          /*!< PSR: TP Mask */
+
+#define PSR_TE_Pos                         12U                                            /*!< PSR: TE Position */
+#define PSR_TE_Msk                         (0x1UL << PSR_TE_Pos)                          /*!< PSR: TE Mask */
+
+#define PSR_MM_Pos                         9U                                             /*!< PSR: MM Position */
+#define PSR_MM_Msk                         (0x1UL << PSR_MM_Pos)                          /*!< PSR: MM Mask */
+
+#define PSR_EE_Pos                         8U                                             /*!< PSR: EE Position */
+#define PSR_EE_Msk                         (0x1UL << PSR_EE_Pos)                          /*!< PSR: EE Mask */
+
+#define PSR_IC_Pos                         7U                                             /*!< PSR: IC Position */
+#define PSR_IC_Msk                         (0x1UL << PSR_IC_Pos)                          /*!< PSR: IC Mask */
+
+#define PSR_IE_Pos                         6U                                             /*!< PSR: IE Position */
+#define PSR_IE_Msk                         (0x1UL << PSR_IE_Pos)                          /*!< PSR: IE Mask */
+
+#define PSR_FE_Pos                         4U                                             /*!< PSR: FE Position */
+#define PSR_FE_Msk                         (0x1UL << PSR_FE_Pos)                          /*!< PSR: FE Mask */
+
+#define PSR_AF_Pos                         1U                                             /*!< PSR: AF Position */
+#define PSR_AF_Msk                         (0x1UL << PSR_AF_Pos)                          /*!< PSR: AF Mask */
+
+#define PSR_C_Pos                          0U                                             /*!< PSR: C Position */
+#define PSR_C_Msk                          (0x1UL << PSR_C_Pos)                           /*!< PSR: C Mask */
+
+/**
+  \brief Consortium definition for accessing Cache Configuration Registers(CCR, CR<18, 0>).
+ */
+typedef union {
+    struct {
+        uint32_t MP: 2;                      /*!< bit:  0.. 1  memory protection settings */
+        uint32_t IE: 1;                      /*!< bit:      2  Instruction cache enable */
+        uint32_t DE: 1;                      /*!< bit:      3  Data cache enable */
+        uint32_t WB: 1;                      /*!< bit:      4  Cache write back */
+        uint32_t RS: 1;                      /*!< bit:      5  Address return stack settings */
+        uint32_t Z: 1;                       /*!< bit:      6  Allow predictive jump bit */
+        uint32_t BE: 1;                      /*!< bit:      7  Endian mode */
+        uint32_t SCK: 3;                     /*!< bit:  8..10  the clock ratio of the system and the processor */
+        uint32_t _reserved0: 1;              /*!< bit:     11  Reserved */
+        uint32_t WA: 1;                      /*!< bit:     12  Write allocate enable */
+        uint32_t E_V2: 1;                    /*!< bit:     13  V2 Endian mode */
+        uint32_t BSTE: 1;                    /*!< bit:     14  Burst transmit enable */
+        uint32_t IPE: 1;                     /*!< bit:     15  Indirect predict enable */
+        uint32_t _reserved1: 16;             /*!< bit: 16..31  Reserved */
+    } b;                                   /*!< Structure    Access by bit */
+    uint32_t w;                            /*!< Type         Access by whole register */
+} CCR_Type;
+
+/* CCR Register Definitions */
+#define CCR_IPE_Pos                       15u                                            /*!< CCR: IPE Position */
+#define CCR_IPE_Msk                       (0x1UL << CCR_IPE_Pos)                         /*!< CCR: IPE Mask */
+
+#define CCR_BSTE_Pos                      14u                                            /*!< CCR: BSTE Position */
+#define CCR_BSTE_Msk                      (0x1UL << CCR_BSTE_Pos)                        /*!< CCR: BSTE Mask */
+
+#define CCR_E_V2_Pos                      13U                                            /*!< CCR: E_V2 Position */
+#define CCR_E_V2_Msk                      (0x1UL << CCR_E_V2_Pos)                        /*!< CCR: E_V2 Mask */
+
+#define CCR_WA_Pos                        12u                                            /*!< CCR: WA Position */
+#define CCR_WA_Msk                        (0x1UL << CCR_WA_Pos)                          /*!< CCR: WA Mask */
+
+#define CCR_SCK_Pos                       8U                                             /*!< CCR: SCK Position */
+#define CCR_SCK_Msk                       (0x3UL << CCR_SCK_Pos)                         /*!< CCR: SCK Mask */
+
+#define CCR_BE_Pos                        7U                                             /*!< CCR: BE Position */
+#define CCR_BE_Msk                        (0x1UL << CCR_BE_Pos)                          /*!< CCR: BE Mask */
+
+#define CCR_Z_Pos                         6U                                             /*!< CCR: Z Position */
+#define CCR_Z_Msk                         (0x1UL << CCR_BE_Pos)                          /*!< CCR: Z Mask */
+
+#define CCR_RS_Pos                        5U                                             /*!< CCR: RS Position */
+#define CCR_RS_Msk                        (0x1UL << CCR_BE_Pos)                          /*!< CCR: RS Mask */
+
+#define CCR_WB_Pos                        4U                                             /*!< CCR: WB Position */
+#define CCR_WB_Msk                        (0x1UL << CCR_BE_Pos)                          /*!< CCR: WB Mask */
+
+#define CCR_DE_Pos                        3U                                             /*!< CCR: DE Position */
+#define CCR_DE_Msk                        (0x1UL << CCR_BE_Pos)                          /*!< CCR: DE Mask */
+
+#define CCR_IE_Pos                        2U                                             /*!< CCR: IE Position */
+#define CCR_IE_Msk                        (0x1UL << CCR_BE_Pos)                          /*!< CCR: IE Mask */
+
+#define CCR_MP_Pos                        0U                                             /*!< CCR: MP Position */
+#define CCR_MP_Msk                        (0x3UL << CCR_MP_Pos)                          /*!< CCR: MP Mask */
+
+/**
+  \brief  Consortium definition for accessing mmu index register(MIR,CR<0,15>).
+ */
+typedef union {
+    struct {
+        uint32_t Index: 10;                  /*!< bit:   0.. 9   TLB index */
+        uint32_t _reserved: 20;              /*!< bit:  10.. 29  Reserved */
+        uint32_t TF: 1;                      /*!< bit:       30  TLB fatal error */
+        uint32_t P: 1;                       /*!< bit:       31  TLBP instruction */
+    } b;
+    uint32_t w;
+} MIR_Type;
+
+/* MIR Register Definitions */
+#define MIR_P_Pos                          31                                            /*!< PRSR: P(TLBP instruction) Position */
+#define MIR_P_Msk                          (0x1UL << MIR_P_Pos)                          /*!< PRSR: P(TLBP instruction) Mask */
+
+#define MIR_TF_Pos                         30                                            /*!< PRSR: Tfatal Position */
+#define MIR_TF_Msk                         (0x1UL << MIR_TF_Pos)                         /*!< PRSR: Tfatal Mask */
+
+#define MIR_Index_Pos                      0                                             /*!< PRSR: Index Position */
+#define MIR_Index_Msk                      (0x3ffUL << MIR_Index_Pos)                    /*!< PRSR: Index Mask */
+
+
+/**
+  \brief  Consortium definition for accessing mmu entry of high physical address register(MEL, CR<2,15> and CR<3,15>).
+ */
+typedef union {
+    struct {
+        uint32_t G: 1;                        /*!< bit:       0   Global enbale bit */
+        uint32_t V: 1;                        /*!< bit:       1   TLB mapping valid bit */
+        uint32_t D: 1;                        /*!< bit:       2   TLB Page dirty bit */
+        uint32_t C: 1;                        /*!< bit:       3   TLB Page cacheable bit */
+        uint32_t SEC: 1;                      /*!< bit:       4   TLB Page security bit */
+        uint32_t SO: 1;                       /*!< bit:       2   Strong order enable bit */
+        uint32_t B: 1;                        /*!< bit:       2   TLB Page bufferable bit */
+        uint32_t _reserved: 5;                /*!< bit:   7.. 11  Reserved */
+        uint32_t PFN: 20;                     /*!< bit:  12.. 31  Physical frame number */
+    } b;
+    uint32_t w;
+} MEL_Type;
+
+/* MEL Register Definitions */
+#define MEL_PFN_Pos                        12                                            /*!< MEL: PFN Position */
+#define MEL_PFN_Msk                        (0xFFFFFUL << MEL_PFN_Pos)                    /*!< MEL: PFN Mask */
+
+#define MEL_B_Pos                          6                                             /*!< MEL: B Position */
+#define MEL_B_Msk                          (0x1UL << MEL_B_Pos)                          /*!< MEL: B Mask */
+
+#define MEL_SO_Pos                         5                                             /*!< MEL: SO Position */
+#define MEL_SO_Msk                         (0x1UL << MEL_SO_Pos)                         /*!< MEL: SO Mask */
+
+#define MEL_SEC_Pos                        4                                             /*!< MEL: SEC Position */
+#define MEL_SEC_Msk                        (0x1UL << MEL_SEC_Pos)                        /*!< MEL: SEC Mask */
+
+#define MEL_C_Pos                          3                                             /*!< MEL: C Position */
+#define MEL_C_Msk                          (0x1UL << MEL_C_Pos)                          /*!< MEL: C Mask */
+
+#define MEL_D_Pos                          2                                             /*!< MEL: D Position */
+#define MEL_D_Msk                          (0x1UL << MIR_D_Pos)                          /*!< MEL: D Mask */
+
+#define MEL_V_Pos                          1                                             /*!< MEL: V Position */
+#define MEL_V_Msk                          (0x1UL << MIR_V_Pos)                          /*!< MEL: V Mask */
+
+#define MEL_G_Pos                          0                                             /*!< MEL: G Position */
+#define MEL_G_Msk                          (0x1UL << MIR_G_Pos)                          /*!< MEL: G Mask */
+
+
+/**
+  \brief  Consortium definition for accessing mmu entry of high physical address register(MEH, CR<4,15>).
+ */
+typedef union {
+    struct {
+        uint32_t ASID :8;                     /*!< bit:   0.. 7   ASID */
+        uint32_t _reserved :4;                /*!< bit:   7.. 10  Reserved */
+        uint32_t VPN :20;                     /*!< bit:  11.. 31  Virtual page number */
+    } b;
+    uint32_t w;
+} MEH_Type;
+
+/* MEH Register Definitions */
+#define MEH_VPN_Pos                        12                                             /*!< MEH: VPN Position */
+#define MEH_VPN_Msk                        (0xFFFFFUL << MEH_VPN_Pos)                     /*!< MEH: VPN Mask */
+
+#define MEH_ASID_Pos                       0                                              /*!< MEH: ASID Position */
+#define MEH_ASID_Msk                       (0xFFUL << MEH_ASID_Pos)                       /*!< MEH: ASID Mask */
+
+
+/**
+  \brief  Consortium definition for accessing mmu entry of high physical address register(MPR, CR<6,15>).
+ */
+typedef union {
+    struct {
+        uint32_t _reserved0: 13;              /*!< bit:   0.. 12   Reserved */
+        uint32_t page_mask: 12;               /*!< bit:  13.. 24   Page mask */
+        uint32_t _reserved1: 7;               /*!< bit:  25.. 31   Reserved */
+    } b;
+    uint32_t w;
+} MPR_Type;
+
+/* MPR Register Definitions */
+#define MPR_PAGE_MASK_Pos                        13                                             /*!< MPR: PAGE_MASK Position */
+#define MPR_PAGE_MASK_Msk                        (0xFFFUL << MPR_PAGE_MASK_Pos)                 /*!< MPR: PAGE_MASK Mask */
+
+
+/**
+  \brief  Consortium definition for accessing mmu entry of high physical address register(CR<8,15>).
+ */
+typedef union {
+    struct {
+        uint32_t ASID: 8;                     /*!< bit:   0.. 7   ASID */
+        uint32_t _reserved: 17;               /*!< bit:   8.. 24  Reserved */
+        uint32_t TLBINV_INDEX: 1;             /*!< bit:       25  TLBINV_INDEX */
+        uint32_t TLBINV_ALL: 1;               /*!< bit:       26  TLBINV_ALL */
+        uint32_t TLBINV: 1;                   /*!< bit:       27  TLBINV */
+        uint32_t TLBWR: 1;                    /*!< bit:       28  TLBWR */
+        uint32_t TLBWI: 1;                    /*!< bit:       29  TLBWI */
+        uint32_t TLBR: 1;                     /*!< bit:       30  TLBR */
+        uint32_t TLBP: 1;                     /*!< bit:       31  TLBP */
+    } b;
+    uint32_t w;
+} MCIR_Type;
+
+/* MCIR Register Definitions */
+#define MCIR_TLBP_Pos                        31                                               /*!< MCIR: TLBP Position */
+#define MCIR_TLBP_Msk                        (0x1UL << MCIR_TLBP_Pos)                         /*!< MCIR: TLBP Mask */
+
+#define MCIR_TLBR_Pos                        30                                               /*!< MCIR: TLBR Position */
+#define MCIR_TLBR_Msk                        (0x1UL << MCIR_TLBR_Pos)                         /*!< MCIR: TLBR Mask */
+
+#define MCIR_TLBWI_Pos                       29                                               /*!< MCIR: TLBWI Position */
+#define MCIR_TLBWI_Msk                       (0x1UL << MCIR_TLBWI_Pos)                        /*!< MCIR: TLBWI Mask */
+
+#define MCIR_TLBWR_Pos                       28                                               /*!< MCIR: TLBWR Position */
+#define MCIR_TLBWR_Msk                       (0x1UL << MCIR_TLBWR_Pos)                        /*!< MCIR: TLBWR Mask */
+
+#define MCIR_TLBINV_Pos                      27                                               /*!< MCIR: TLBINV Position */
+#define MCIR_TLBINV_Msk                      (0x1UL << MCIR_TLBINV_Pos)                       /*!< MCIR: TLBINV Mask */
+
+#define MCIR_TLBINV_ALL_Pos                  26                                               /*!< MCIR: TLBINV_ALL Position */
+#define MCIR_TLBINV_ALL_Msk                  (0x1UL << MCIR_TLBINV_ALL_Pos)                   /*!< MCIR: TLBINV_ALL Mask */
+
+#define MCIR_TLBINV_INDEX_Pos                25                                               /*!< MCIR: TLBINV_INDEX Position */
+#define MCIR_TLBINV_INDEX_Msk                (0x1UL << MCIR_TLBINV_INDEX_Pos)                 /*!< MCIR: TLBINV_INDEX Mask */
+
+#define MCIR_ASID_Pos                        0                                                /*!< MCIR: ASID Position */
+#define MCIR_ASID_Msk                        (0xFFUL << MCIR_ASID_Pos)                        /*!< MCIR: ASID Mask */
+
+
+/*@} end of group CSI_CORE */
+
+
+/**
+  \ingroup    CSI_core_register
+  \defgroup   CSI_CACHE
+  \brief      Type definitions for the cache Registers
+  @{
+ */
+
+/**
+  \brief  Consortium definition for accessing protection area selection register(CFR,CR<17,0>).
+ */
+typedef union {
+    struct {
+        uint32_t CACHE_SEL: 2;                      /*!< bit:  0..1  Instruction and data cache selection */
+        uint32_t _reserved0: 2;                     /*!< bit:  2..3  Reserved */
+        uint32_t INV: 1;                            /*!< bit:     4  Invalid data in cache */
+        uint32_t CLR: 1;                            /*!< bit:     5  Clear the dirty tlb table */
+        uint32_t OMS: 1;                            /*!< bit:     6  Cache invalid and clear operation mode (one line or all line)*/
+        uint32_t ITS: 1;                            /*!< bit:     7  Cache invalid and clear operation mode (CIR used as virtual index or SET/WAY/LEVE index)*/
+        uint32_t UNLOCK: 1;                         /*!< bit:     8  Unclock data cache line. */
+        uint32_t _reserved1: 7;                     /*!< bit: 9..15  Reserved */
+        uint32_t BHT_INV: 1;                        /*!< bit:    16  Invalid data in branch history table */
+        uint32_t BTB_INV: 1;                        /*!< bit:    17  Invalid data in branch table buffer */
+        uint32_t _reserved2: 13;                    /*!< bit: 18..30 Reserved */
+        uint32_t LICF: 1;                           /*!< bit:     31 Failure of clearing or invalid cache line */
+    } b;                                            /*!< Structure    Access by bit */
+    uint32_t w;                                     /*!< Type         Access by whole register */
+} CFR_Type;
+
+#define CFR_LICF_Pos                     31U                                             /*!< CFR: LICF Position */
+#define CFR_LICF_Msk                     (0x1UL << CFR_LICF_Pos)                         /*!< CFR: LICF Mask */
+
+#define CFR_BTB_INV_Pos                  17U                                             /*!< CFR: BTB Position */
+#define CFR_BTB_INV_Msk                  (0x1UL << CFR_BTB_INV_Pos)                      /*!< CFR: BTB Mask */
+
+#define CFR_BHT_INV_Pos                  16U                                             /*!< CFR: BHT Position */
+#define CFR_BHT_INV_Msk                  (0x1UL << CFR_BHT_INV_Pos)                      /*!< CFR: BHT Mask */
+
+#define CFR_UNLOCK_Pos                   8U                                              /*!< CFR: UNLOCK Position */
+#define CFR_UNLOCK_Msk                   (0x1UL << CFR_UNLOCK_Pos)                       /*!< CFR: UNLOCK Mask */
+
+#define CFR_ITS_Pos                      7U                                              /*!< CFR: ITS Position */
+#define CFR_ITS_Msk                      (0x1UL << CFR_ITS_Pos)                          /*!< CFR: ITS Mask */
+
+#define CFR_OMS_Pos                      6U                                              /*!< CFR: OMS Position */
+#define CFR_OMS_Msk                      (0x1UL << CFR_OMS_Pos)                          /*!< CFR: OMS Mask */
+
+#define CFR_CLR_Pos                      5U                                              /*!< CFR: CLR Position */
+#define CFR_CLR_Msk                      (0x1UL << CFR_CLR_Pos)                          /*!< CFR: CLR Mask */
+
+#define CFR_INV_Pos                      4U                                              /*!< CFR: INV Position */
+#define CFR_INV_Msk                      (0x1UL << CFR_INV_Pos)                          /*!< CFR: INV Mask */
+
+#define CFR_CACHE_SEL_Pos                0                                               /*!< CFR: CACHE_SEL Position */    
+#define CFR_CACHE_SEL_Msk                (0x3UL << CFR_CACHE_SEL_Pos)                    /*!< CFR: CACHE_SEL Masok */
+
+/* CFR Register Definitions */
+/*@} end of group CSI_CACHE */
+
+
+/**
+  \ingroup    CSI_core_register
+  \defgroup   CSI_CACHE
+  \brief      Type definitions for the cache Registers
+  @{
+ */
+#define SSEG0_BASE_ADDR         0x80000000
+#define CACHE_RANGE_MAX_SIZE    0x80000
+
+#define INS_CACHE               (1 << 0)
+#define DATA_CACHE              (1 << 1)
+#define CACHE_INV               (1 << 4)
+#define CACHE_CLR               (1 << 5)
+#define CACHE_OMS               (1 << 6)
+#define CACHE_ITS               (1 << 7)
+#define CACHE_LICF              (1 << 31)
+
+#define    L1_CACHE_SHIFT       4      /* 16 Bytes */
+#define    L1_CACHE_BYTES       (1 << L1_CACHE_SHIFT)
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    ((value << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    ((value & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CSI_core_bitfield */
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core VIC Functions
+  - Core CORET Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
+#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
+
+
+/* ##########################  Cache functions  #################################### */
+/**
+  \ingroup  CSI_Core_FunctionInterface
+  \defgroup CSI_Core_CacheFunctions Cache Functions
+  \brief    Functions that configure Instruction and Data cache.
+  @{
+ */
+
+/**
+  \brief   Enable I-Cache
+  \details Turns on I-Cache
+  */
+__STATIC_INLINE void csi_icache_enable (void)
+{
+   __set_CCR(__get_CCR() | 0x00000004);
+}
+
+
+/**
+  \brief   Disable I-Cache
+  \details Turns off I-Cache
+  */
+__STATIC_INLINE void csi_icache_disable (void)
+{
+   __set_CCR(__get_CCR() & 0xFFFFFFFB);
+}
+
+
+/**
+  \brief   Invalidate I-Cache
+  \details Invalidates I-Cache
+  */
+__STATIC_INLINE void csi_icache_invalid (void)
+{
+    __set_CFR(0x11);
+    __set_CFR(INS_CACHE | CACHE_INV);
+}
+
+
+/**
+  \brief   Enable D-Cache
+  \details Turns on D-Cache
+  \note    I-Cache also turns on.
+  */
+__STATIC_INLINE void csi_dcache_enable (void)
+{
+   __set_CCR(__get_CCR() | 0x00000008);
+}
+
+
+/**
+  \brief   Disable D-Cache
+  \details Turns off D-Cache
+  \note    I-Cache also turns off.
+  */
+__STATIC_INLINE void csi_dcache_disable (void)
+{
+   __set_CCR(__get_CCR() & 0xFFFFFFF7);
+}
+
+
+/**
+  \brief   Invalidate D-Cache
+  \details Invalidates D-Cache
+  \note    I-Cache also invalid
+  */
+__STATIC_INLINE void csi_dcache_invalid (void)
+{
+    __set_CFR(DATA_CACHE | CACHE_INV);
+}
+
+
+/**
+  \brief   Clean D-Cache
+  \details Cleans D-Cache
+  \note    I-Cache also cleans
+  */
+__STATIC_INLINE void csi_dcache_clean (void)
+{
+    __set_CFR(DATA_CACHE | CACHE_CLR);
+}
+
+/**
+  \brief   Clean & Invalidate D-Cache
+  \details Cleans and Invalidates D-Cache
+  \note    I-Cache also flush.
+  */
+__STATIC_INLINE void csi_dcache_clean_invalid (void)
+{
+    __set_CFR(DATA_CACHE | CACHE_CLR | CACHE_INV);
+}
+
+__STATIC_INLINE  void set_cache_range (uint32_t start, uint32_t end, uint32_t value)
+{
+    if (!(start & SSEG0_BASE_ADDR) || (end - start) &~(CACHE_RANGE_MAX_SIZE - 1)) {
+        __set_CFR(value);
+    }
+
+    if (value & INS_CACHE) {
+        csi_icache_disable();
+    }
+    uint32_t i;
+    for (i = start; i < end; i += L1_CACHE_BYTES) {
+        __set_CIR(i);
+        __set_CFR(CACHE_OMS | value);
+    }
+
+    if (end & (L1_CACHE_BYTES-1)) {
+        __set_CIR(end);
+        __set_CFR(CACHE_OMS | value);
+    }
+
+    if (value & INS_CACHE) {
+        csi_icache_enable();
+    }
+
+}
+
+/**
+  \brief   D-Cache Invalidate by address
+  \details Invalidates D-Cache for the given address
+  \param[in]   addr    address (aligned to 16-byte boundary)
+  \param[in]   dsize   size of memory block (aligned to 16-byte boundary)
+*/
+__STATIC_INLINE void csi_dcache_invalid_range (uint32_t *addr, int32_t dsize)
+{
+    set_cache_range((uint32_t)addr, (uint32_t)addr + dsize, (DATA_CACHE | CACHE_INV));
+}
+
+
+/**
+  \brief   D-Cache Clean by address
+  \details Cleans D-Cache for the given address
+  \param[in]   addr    address (aligned to 16-byte boundary)
+  \param[in]   dsize   size of memory block (aligned to 16-byte boundary)
+*/
+__STATIC_INLINE void csi_dcache_clean_range (uint32_t *addr, int32_t dsize)
+{
+    set_cache_range((uint32_t)addr, (uint32_t)addr + dsize, (DATA_CACHE | CACHE_CLR));
+}
+
+
+/**
+  \brief   D-Cache Clean and Invalidate by address
+  \details Cleans and invalidates D_Cache for the given address
+  \param[in]   addr    address (aligned to 16-byte boundary)
+  \param[in]   dsize   size of memory block (aligned to 16-byte boundary)
+*/
+__STATIC_INLINE void csi_dcache_clean_invalid_range (uint32_t *addr, int32_t dsize)
+{
+    set_cache_range((uint32_t)addr, (uint32_t)addr + dsize, (DATA_CACHE | CACHE_CLR | CACHE_INV));
+}
+
+
+/*@} end of CSI_Core_CacheFunctions */
+
+/* ##########################  MMU functions  #################################### */
+/**
+  \ingroup  CSI_Core_FunctionInterface
+  \defgroup CSI_Core_MMUFunctions MMU Functions
+  \brief    Functions that configure MMU.
+  @{
+ */
+
+typedef struct {
+    uint32_t global: 1;         /* tlb page global access. */
+    uint32_t valid: 1;          /* tlb page valid */
+    uint32_t writeable: 1;      /* tlb page writeable */
+    uint32_t cacheable: 1;      /* tlb page cacheable*/
+    uint32_t is_secure: 1;      /* tlb page security access */
+    uint32_t strong_order: 1;   /* the sequence of accessing data on tlb page is corresponding to the program flow? */
+    uint32_t bufferable: 1;     /* tlb page bufferable */
+} page_attr_t;
+
+typedef enum {
+    PAGE_SIZE_4KB   = 0x000,
+    PAGE_SIZE_16KB  = 0x003,
+    PAGE_SIZE_64KB  = 0x00F,
+    PAGE_SIZE_256KB = 0x03F,
+    PAGE_SIZE_1MB   = 0x0FF,
+    PAGE_SIZE_4MB   = 0x3FF,
+    PAGE_SIZE_16MB  = 0xFFF
+} page_size_e;
+
+
+/**
+  \brief  enable mmu
+  \details
+  */
+__STATIC_INLINE void csi_mmu_enable(void)
+{
+    __set_CCR(__get_CCR() | (1u << CCR_MP_Pos));
+}
+
+/**
+  \brief  disable mmu
+  \details
+  */
+__STATIC_INLINE void csi_mmu_disable(void)
+{
+    __set_CCR(__get_CCR() & (~(1u << CCR_MP_Pos)));
+}
+
+/**
+  \brief  create page with feature.
+  \details
+  \param [in]  vaddr     virtual address.
+  \param [in]  paddr     physical address.
+  \param [in]  asid      address sapce id (default: 0).
+  \param [in]  attr      \ref page_attr_t. tlb page attribute.
+  */
+__STATIC_INLINE void csi_mmu_set_tlb(uint32_t vaddr, uint32_t paddr, uint32_t asid, page_attr_t attr)
+{
+     MPR_Type pgmask;
+     MEH_Type meh;
+     MEL_Type mel;
+     uint32_t vaddr_bit;
+     uint32_t page_feature = 0;
+
+     page_feature |= attr.global << MEL_G_Pos | attr.valid << MEL_V_Pos |
+                     attr.writeable << MEL_D_Pos | attr.cacheable << MEL_C_Pos |
+                     attr.is_secure << MEL_SEC_Pos | attr.strong_order << MEL_SO_Pos |
+                     attr.bufferable << MEL_B_Pos;
+
+     pgmask.w = __get_MPR();
+     vaddr_bit = 44 - __FF0(~((uint32_t)pgmask.b.page_mask));
+
+     meh.b.ASID = (uint8_t)asid;
+     meh.b.VPN  = (vaddr & ((~pgmask.w | 0xFE000000) & 0xFFFFE000)) >> MEH_VPN_Pos;
+     __set_MEH(meh.w);
+
+     __set_MCIR(1u << MCIR_TLBP_Pos);
+
+     mel.w = ((paddr & ~(pgmask.b.page_mask << 12)) | page_feature);
+     if (vaddr & (1 << vaddr_bit)) {
+         __set_MEL1(mel.w);
+     }
+     else {
+         __set_MEL0(mel.w);
+     }
+
+     if (__get_MIR() & (1 << MIR_P_Pos)) {
+        __set_MCIR(1u << MCIR_TLBWR_Pos);
+     } else {
+        __set_MCIR(1u << MCIR_TLBWI_Pos);
+     }
+}
+
+
+/**
+  \brief  enble mmu
+  \details
+  \param [in]  size  tlb page size.
+  */
+__STATIC_INLINE void csi_mmu_set_pagesize(page_size_e size)
+{
+    MPR_Type pgmask;
+    pgmask.b.page_mask = size;
+    __set_MPR(pgmask.w);
+}
+
+
+/**
+  \brief  read MEH, MEL0, MEL1 by tlb index.
+  \details
+  \param [in]    index  tlb index(0, 1, 2, ...)
+  \param [out]   meh    pointer to variable for retrieving MEH.
+  \param [out]   mel0   pointer to variable for retrieving MEL0.
+  \param [out]   mel1   pointer to variable for retrieving MEL1.
+  */
+__STATIC_INLINE void csi_mmu_read_by_index(uint32_t index, uint32_t *meh, uint32_t *mel0, uint32_t *mel1)
+{
+    MIR_Type mir;
+
+    if (meh == NULL || mel0 == NULL || mel1 == NULL) {
+        return;
+    }
+
+    mir.b.Index = index;
+    __set_MIR(mir.w);
+    __set_MCIR(1u << MCIR_TLBR_Pos);
+
+    *meh = __get_MEH();
+    *mel0 = __get_MEL0();
+    *mel1 = __get_MEL1();
+}
+
+
+/**
+  \brief  flush all mmu tlb.
+  \details
+  */
+__STATIC_INLINE void csi_mmu_invalid_tlb_all(void)
+{
+    __set_MCIR(1u << MCIR_TLBINV_ALL_Pos);
+}
+
+
+/**
+  \brief  flush mmu tlb by index.
+  \details
+  */
+__STATIC_INLINE void csi_mmu_invalid_tlb_by_index(uint32_t index)
+{
+    MIR_Type mir;
+
+    mir.b.Index = index;
+    __set_MIR(mir.w);
+    __set_MCIR(1u << MCIR_TLBINV_INDEX_Pos);
+}
+
+
+/**
+  \brief  flush mmu tlb by virtual address.
+  \details
+  */
+__STATIC_INLINE void csi_mmu_invalid_tlb_by_vaddr(uint32_t vaddr, uint32_t asid)
+{
+    __set_MEH(vaddr | (asid & MEH_ASID_Msk));
+    __set_MCIR(1u << MCIR_TLBP_Pos);
+
+    if (__get_MIR() & (1 << MIR_P_Pos)) {
+        return;
+    } else {
+        __set_MCIR(1u << MCIR_TLBINV_INDEX_Pos);
+    }
+}
+
+/*@} end of CSI_Core_MMUFunctions */
+
+
+/* ##################################    IRQ Functions  ############################################ */
+
+/**
+  \brief   Save the Irq context
+  \details save the psr result before disable irq.
+  \param [in]      irq_num  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE uint32_t csi_irq_save(void)
+{
+    uint32_t result;
+    result = __get_PSR();
+    __disable_irq();
+    return(result);
+}
+
+/**
+  \brief   Restore the Irq context
+  \details restore saved primask state.
+  \param [in]      irq_state  psr irq state.
+ */
+__STATIC_INLINE void csi_irq_restore(uint32_t irq_state)
+{
+    __set_PSR(irq_state);
+}
+
+/*@} end of IRQ Functions */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CK810_H_DEPENDANT */
+
+#endif /* __CSI_GENERIC */

lib/sec_library/include/core/core_ck610.h

@@ -0,0 +1,973 @@
+/*
+ * Copyright (C) 2017-2019 Alibaba Group Holding Limited
+ */
+
+
+/******************************************************************************
+ * @file     core_ck610.h
+ * @brief    CSI CK610 Core Peripheral Access Layer Header File
+ * @version  V1.0
+ * @date     02. June 2017
+ ******************************************************************************/
+
+#ifndef __CORE_CK610_H_GENERIC
+#define __CORE_CK610_H_GENERIC
+
+#include <stdint.h>
+#include <stdio.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*******************************************************************************
+ *                 CSI definitions
+ ******************************************************************************/
+/**
+  \ingroup Ck610
+  @{
+ */
+
+/*  CSI CK610 definitions */
+#define __CK610_CSI_VERSION_MAIN  (0x01U)                                      /*!< [31:16] CSI HAL main version */
+#define __CK610_CSI_VERSION_SUB   (0x1EU)                                      /*!< [15:0]  CSI HAL sub version */
+#define __CK610_CSI_VERSION       ((__CK610_CSI_VERSION_MAIN << 16U) | \
+                                   __CK610_CSI_VERSION_SUB           )         /*!< CSI HAL version number */
+
+#define __CK610                   (0x01U)                                      /*!< CK610 Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       1U
+
+#if defined ( __GNUC__ )
+#if defined (__VFP_FP__) && !defined(__SOFTFP__)
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CK610_H_GENERIC */
+
+#ifndef __CSI_GENERIC
+
+#ifndef __CORE_CK610_H_DEPENDANT
+#define __CORE_CK610_H_DEPENDANT
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#ifndef __CK610_REV
+#define __CK610_REV               0x0000U
+#endif
+
+#ifndef __GSR_GCR_PRESENT
+#define __GSR_GCR_PRESENT         0U
+#endif
+
+#ifndef __MPU_PRESENT
+#define __MPU_PRESENT             0U
+#endif
+
+#ifndef __ICACHE_PRESENT
+#define __ICACHE_PRESENT          1U
+#endif
+
+#ifndef __DCACHE_PRESENT
+#define __DCACHE_PRESENT          1U
+#endif
+
+#include <csi_gcc.h>
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CSI_glob_defs CSI Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+#define     __I      volatile             /*!< Defines 'read only' permissions */
+#else
+#define     __I      volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O      volatile             /*!< Defines 'write only' permissions */
+#define     __IO     volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const       /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile             /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile             /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group CK610 */
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core MGU Register
+  - Core MMU Register
+ ******************************************************************************/
+/**
+  \defgroup CSI_core_register Defines and Type Definitions
+  \brief Type definitions and defines for CK610 processor based devices.
+*/
+
+/**
+  \brief  Access Processor Status Register(PSR)struct definition.
+ */
+typedef union {
+    struct {
+        uint32_t C: 1;                       /*!< bit:      0  Conditional code/Carry flag */
+        uint32_t AF: 1;                      /*!< bit:      1  Alternate register valid control bit */
+        uint32_t _reserved0: 2;              /*!< bit:  2.. 3  Reserved */
+        uint32_t FE: 1;                      /*!< bit:      4  Fast interrupt enable control bit */
+        uint32_t _reserved1: 1;              /*!< bit:      5  Reserved */
+        uint32_t IE: 1;                      /*!< bit:      6  Interrupt effective control bit */
+        uint32_t IC: 1;                      /*!< bit:      7  Interrupt control bit */
+        uint32_t EE: 1;                      /*!< bit:      8  Abnormally effective control bit */
+        uint32_t MM: 1;                      /*!< bit:      9  Unsymmetrical masking bit */
+        uint32_t _reserved2: 2;              /*!< bit: 10..11  Reserved */
+        uint32_t TE: 1;                      /*!< bit:     12  Trace transmission control bit */
+        uint32_t TP: 1;                      /*!< bit:     13  Pending trace exception set bit */
+        uint32_t TM: 2;                      /*!< bit: 14..15  Tracing mode bit */
+        uint32_t VEC: 8;                     /*!< bit: 16..23  Abnormal event vector value */
+        uint32_t CPID: 4;                    /*!< bit: 24..27  Number of processor currently running */
+        uint32_t _reserved3: 3;              /*!< bit: 28..30  Reserved */
+        uint32_t S: 1;                       /*!< bit:     31  Superuser mode set bit */
+    } b;                                     /*!< Structure    Access by bit */
+    uint32_t w;                              /*!< Type         Access by whole register */
+} PSR_Type;
+
+/* PSR Register Definitions */
+#define PSR_S_Pos                          31U                                            /*!< PSR: S Position */
+#define PSR_S_Msk                          (0x1UL << PSR_S_Pos)                           /*!< PSR: S Mask */
+
+#define PSR_CPID_Pos                       24U                                            /*!< PSR: CPID Position */
+#define PSR_CPID_Msk                       (0xFUL << PSR_CPID_Pos)                        /*!< PSR: CPID Mask */
+
+#define PSR_VEC_Pos                        16U                                            /*!< PSR: VEC Position */
+#define PSR_VEC_Msk                        (0xFFUL << PSR_VEC_Pos)                        /*!< PSR: VEC Mask */
+
+#define PSR_TM_Pos                         14U                                            /*!< PSR: TM Position */
+#define PSR_TM_Msk                         (0x3UL << PSR_TM_Pos)                          /*!< PSR: TM Mask */
+
+#define PSR_TP_Pos                         13U                                            /*!< PSR: TP Position */
+#define PSR_TP_Msk                         (0x1UL << PSR_TM_Pos)                          /*!< PSR: TP Mask */
+
+#define PSR_TE_Pos                         12U                                            /*!< PSR: TE Position */
+#define PSR_TE_Msk                         (0x1UL << PSR_TE_Pos)                          /*!< PSR: TE Mask */
+
+#define PSR_MM_Pos                         9U                                             /*!< PSR: MM Position */
+#define PSR_MM_Msk                         (0x1UL << PSR_MM_Pos)                          /*!< PSR: MM Mask */
+
+#define PSR_EE_Pos                         8U                                             /*!< PSR: EE Position */
+#define PSR_EE_Msk                         (0x1UL << PSR_EE_Pos)                          /*!< PSR: EE Mask */
+
+#define PSR_IC_Pos                         7U                                             /*!< PSR: IC Position */
+#define PSR_IC_Msk                         (0x1UL << PSR_IC_Pos)                          /*!< PSR: IC Mask */
+
+#define PSR_IE_Pos                         6U                                             /*!< PSR: IE Position */
+#define PSR_IE_Msk                         (0x1UL << PSR_IE_Pos)                          /*!< PSR: IE Mask */
+
+#define PSR_FE_Pos                         4U                                             /*!< PSR: FE Position */
+#define PSR_FE_Msk                         (0x1UL << PSR_FE_Pos)                          /*!< PSR: FE Mask */
+
+#define PSR_AF_Pos                         1U                                             /*!< PSR: AF Position */
+#define PSR_AF_Msk                         (0x1UL << PSR_AF_Pos)                          /*!< PSR: AF Mask */
+
+#define PSR_C_Pos                          0U                                             /*!< PSR: C Position */
+#define PSR_C_Msk                          (0x1UL << PSR_C_Pos)                           /*!< PSR: C Mask */
+
+/**
+  \brief Consortium definition for accessing Cache Configuration Registers(CCR, CR<18, 0>).
+ */
+typedef union {
+    struct {
+        uint32_t MP: 2;                      /*!< bit:  0..1   Memory protection settings */
+        uint32_t IE: 1;                      /*!< bit:      2  Endian mode */
+        uint32_t DE: 1;                      /*!< bit:      3  Endian mode */
+        uint32_t WB: 1;                      /*!< bit:      4  Endian mode */
+        uint32_t RS: 1;                      /*!< bit:      5  Endian mode */
+        uint32_t Z:  1;                      /*!< bit:      6  Endian mode */
+        uint32_t BE: 1;                      /*!< bit:      7  Endian mode */
+        uint32_t SCK: 3;                     /*!< bit:  8..10  The clock ratio of the system and the processor */
+        uint32_t _reserved0: 21;             /*!< bit:  11..31 Reserved */
+    } b;                                     /*!< Structure    Access by bit */
+    uint32_t w;                              /*!< Type         Access by whole register */
+} CCR_Type;
+
+/* CCR Register Definitions */
+#define CCR_SCK_Pos                        8U                                               /*!< CCR: SCK Position */
+#define CCR_SCK_Msk                        (0x7UL << CCR_SCK_Pos)                           /*!< CCR: SCK Mask */
+
+#define CCR_BE_Pos                         7U                                               /*!< CCR: BE Position */
+#define CCR_BE_Msk                         (0x1UL << CCR_BE_Pos)                            /*!< CCR: BE Mask */
+
+#define CCR_Z_Pos                          6U                                               /*!< CCR: Z Position */
+#define CCR_Z_Msk                          (0x1UL << CCR_Z_Pos)                             /*!< CCR: Z Mask */
+
+#define CCR_RS_Pos                         5U                                               /*!< CCR: RS Position */
+#define CCR_RS_Msk                         (0x1UL << CCR_RS_Pos)                            /*!< CCR: RS Mask */
+
+#define CCR_WB_Pos                         4U                                               /*!< CCR: WB Position */
+#define CCR_WB_Msk                         (0x1UL << CCR_WB_Pos)                            /*!< CCR: WB Mask */
+
+#define CCR_DE_Pos                         3U                                               /*!< CCR: DE Position */
+#define CCR_DE_Msk                         (0x1UL << CCR_DE_Pos)                            /*!< CCR: DE Mask */
+
+#define CCR_IE_Pos                         2U                                               /*!< CCR: IE Position */
+#define CCR_IE_Msk                         (0x1UL << CCR_IE_Pos)                            /*!< CCR: IE Mask */
+
+#define CCR_MP_Pos                         0U                                               /*!< CCR: MP Position */
+#define CCR_MP_Msk                         (0x3UL << CCR_MP_Pos)                            /*!< CCR: MP Mask */
+
+
+/**
+  \brief  Consortium definition for accessing high ease access permission configutation registers(CAPR, CR<19,0>)
+ */
+typedef union {
+    struct {
+        uint32_t C0: 1;                      /*!< bit:      0  Cacheable setting */
+        uint32_t C1: 1;                      /*!< bit:      1  Cacheable setting */
+        uint32_t C2: 1;                      /*!< bit:      2  Cacheable setting */
+        uint32_t C3: 1;                      /*!< bit:      3  Cacheable setting */
+        uint32_t _reserved0: 4;              /*!< bit:  4.. 7  Reserved */
+        uint32_t AP0: 2;                     /*!< bit:  8.. 9  access permissions settings bit */
+        uint32_t AP1: 2;                     /*!< bit: 10..11  access permissions settings bit */
+        uint32_t AP2: 2;                     /*!< bit: 12..13  access permissions settings bit */
+        uint32_t AP3: 2;                     /*!< bit: 14..15  access permissions settings bit */
+        uint32_t _reserved1: 16;             /*!< bit: 16..31  Reserved */
+    } b;                                   /*!< Structure    Access by bit */
+    uint32_t w;                            /*!< Type         Access by whole register */
+} CAPR_Type;
+
+/* CAPR Register Definitions */
+#define CAPR_AP3_Pos                       14U                                            /*!< CAPR: AP3 Position */
+#define CAPR_AP3_Msk                       (0x3UL << CAPR_AP3_Pos)                        /*!< CAPR: AP3 Mask */
+
+#define CAPR_AP2_Pos                       12U                                            /*!< CAPR: AP2 Position */
+#define CAPR_AP2_Msk                       (0x3UL << CAPR_AP2_Pos)                        /*!< CAPR: AP2 Mask */
+
+#define CAPR_AP1_Pos                       10U                                            /*!< CAPR: AP1 Position */
+#define CAPR_AP1_Msk                       (0x3UL << CAPR_AP1_Pos)                        /*!< CAPR: AP1 Mask */
+
+#define CAPR_AP0_Pos                       8U                                             /*!< CAPR: AP0 Position */
+#define CAPR_AP0_Msk                       (0x3UL << CAPR_AP0_Pos)                        /*!< CAPR: AP0 Mask */
+
+#define CAPR_X3_Pos                        3U                                             /*!< CAPR: X3 Position */
+#define CAPR_X3_Msk                        (0x1UL << CAPR_X3_Pos)                         /*!< CAPR: X3 Mask */
+
+#define CAPR_X2_Pos                        2U                                             /*!< CAPR: X2 Position */
+#define CAPR_X2_Msk                        (0x1UL << CAPR_X2_Pos)                         /*!< CAPR: X2 Mask */
+
+#define CAPR_X1_Pos                        1U                                             /*!< CAPR: X1 Position */
+#define CAPR_X1_Msk                        (0x1UL << CAPR_X1_Pos)                         /*!< CAPR: X1 Mask */
+
+#define CAPR_X0_Pos                        0U                                             /*!< CAPR: X0 Position */
+#define CAPR_X0_Msk                        (0x1UL << CAPR_X0_Pos)                         /*!< CAPR: X0 Mask */
+
+
+/**
+  \brief  Consortium definition for accessing control register(PACR, CR<20,0>).
+ */
+typedef union {
+    struct {
+        uint32_t E: 1;                       /*!< bit:      0  Effective setting of protected area */
+        uint32_t size: 5;                    /*!< bit:  1.. 5  Size of protected area */
+        uint32_t _reserved0: 6;              /*!< bit:  6.. 11 Reserved */
+        uint32_t base_addr: 20;              /*!< bit:  10..31 The high position of the address of a protected area */
+    } b;                                     /*!< Structure    Access by bit */
+    uint32_t w;                              /*!< Type         Access by whole register */
+} PACR_Type;
+
+    /* PACR Register Definitions */
+#define PACR_BASE_ADDR_Pos                 12U                                            /*!< PACR: base_addr Position */
+#define PACR_BASE_ADDR_Msk                 (0xFFFFFUL << PACR_BASE_ADDR_Pos)              /*!< PACR: base_addr Mask */
+
+#define PACR_SIZE_Pos                      1U                                             /*!< PACR: Size Position */
+#define PACR_SIZE_Msk                      (0x1FUL << PACR_SIZE_Pos)                      /*!< PACR: Size Mask */
+
+#define PACR_E_Pos                         0U                                             /*!< PACR: E Position */
+#define PACR_E_Msk                         (0x1UL << PACR_E_Pos)                          /*!< PACR: E Mask */
+
+/**
+  \brief  Consortium definition for accessing protection area selection register(PRSR,CR<21,0>).
+ */
+typedef union {
+    struct {
+        uint32_t RID: 2;                     /*!< bit:  0.. 1  Protected area index value */
+        uint32_t _reserved0: 30;             /*!< bit:  2..31  Reserved */
+    } b;                                     /*!< Structure    Access by bit */
+    uint32_t w;                              /*!< Type         Access by whole register */
+} PRSR_Type;
+
+/* PRSR Register Definitions */
+#define PRSR_RID_Pos                       0U                                            /*!< PRSR: RID Position */
+#define PRSR_RID_Msk                       (0x3UL << PRSR_RID_Pos)                       /*!< PRSR: RID Mask */
+
+/**
+  \brief  Consortium definition for accessing mmu index register(MIR,CP15_CR0).
+ */
+typedef union {
+    struct {
+        uint32_t Index: 10;
+        uint32_t _reserved: 20;
+        uint32_t TF: 1;
+        uint32_t P: 1;
+    } b;
+    uint32_t w;
+} MIR_Type;
+
+/* MIR Register Definitions */
+#define MIR_P_Pos                          31                                            /*!< PRSR: P(TLBP instruction) Position */
+#define MIR_P_Msk                          (0x1UL << MIR_P_Pos)                          /*!< PRSR: P(TLBP instruction) Mask */
+
+#define MIR_TF_Pos                         30                                            /*!< PRSR: Tfatal Position */
+#define MIR_TF_Msk                         (0x1UL << MIR_TF_Pos)                         /*!< PRSR: Tfatal Mask */
+
+#define MIR_Index_Pos                      0                                             /*!< PRSR: Index Position */
+#define MIR_Index_Msk                      (0x3ffUL << MIR_Index_Pos)                    /*!< PRSR: Index Mask */
+
+
+/**
+  \brief  Consortium definition for accessing mmu entry of high physical address register(MEL, CP15_CR2 and CP15_CR3).
+ */
+typedef union {
+    struct {
+        uint32_t G: 1;
+        uint32_t V: 1;
+        uint32_t D: 1;
+        uint32_t C: 3;
+        uint32_t PFN: 20;
+        uint32_t _reserved: 6;
+    } b;
+    uint32_t w;
+} MEL_Type;
+
+/* MEL Register Definitions */
+#define MEL_PFN_Pos                        6                                             /*!< MEL: PFN Position */
+#define MEL_PFN_Msk                        (0xFFFFFUL << MEL_PFN_Pos)                    /*!< MEL: PFN Mask */
+
+#define MEL_C_Pos                          3                                             /*!< MEL: C Position */
+#define MEL_C_Msk                          (0x7UL << MEL_C_Pos)                          /*!< MEL: C Mask */
+
+#define MEL_D_Pos                          2                                             /*!< MEL: D Position */
+#define MEL_D_Msk                          (0x1UL << MIR_D_Pos)                          /*!< MEL: D Mask */
+
+#define MEL_V_Pos                          1                                             /*!< MEL: V Position */
+#define MEL_V_Msk                          (0x1UL << MIR_V_Pos)                          /*!< MEL: V Mask */
+
+#define MEL_G_Pos                          0                                             /*!< MEL: G Position */
+#define MEL_G_Msk                          (0x1UL << MIR_G_Pos)                          /*!< MEL: G Mask */
+
+
+/**
+  \brief  Consortium definition for accessing mmu entry of high physical address register(MEH, CP15_CR4).
+ */
+typedef union {
+    struct {
+        uint32_t ASID :8;
+        uint32_t _reserved :4;
+        uint32_t VPN :20;
+    } b;
+    uint32_t w;
+} MEH_Type;
+
+/* MEH Register Definitions */
+#define MEH_VPN_Pos                        12                                             /*!< MEH: VPN Position */
+#define MEH_VPN_Msk                        (0xFFFFFUL << MEH_VPN_Pos)                     /*!< MEH: VPN Mask */
+
+#define MEH_ASID_Pos                       0                                              /*!< MEH: ASID Position */
+#define MEH_ASID_Msk                       (0xFFUL << MEH_ASID_Pos)                       /*!< MEH: ASID Mask */
+
+
+/**
+  \brief  Consortium definition for accessing mmu entry of high physical address register(MPR, CP15_CR6).
+ */
+typedef union {
+    struct {
+        uint32_t _reserved0: 13;
+        uint32_t page_mask: 12;
+        uint32_t _reserved1: 7;
+    } b;
+    uint32_t w;
+} MPR_Type;
+
+/* MPR Register Definitions */
+#define MPR_PAGE_MASK_Pos                        13                                             /*!< MPR: PAGE_MASK Position */
+#define MPR_PAGE_MASK_Msk                        (0xFFFUL << MPR_PAGE_MASK_Pos)                 /*!< MPR: PAGE_MASK Mask */
+
+
+/**
+  \brief  Consortium definition for accessing mmu entry of high physical address register(MCIR, CP15_CR8).
+ */
+typedef union {
+    struct {
+        uint32_t ASID: 8;
+        uint32_t _reserved: 17;
+        uint32_t TLBINV_INDEX: 1;
+        uint32_t TLBINV_ALL: 1;
+        uint32_t TLBINV: 1;
+        uint32_t TLBWR: 1;
+        uint32_t TLBWI: 1;
+        uint32_t TLBR: 1;
+        uint32_t TLBP: 1;
+    } b;
+    uint32_t w;
+} MCIR_Type;
+
+/* MCIR Register Definitions */
+#define MCIR_TLBP_Pos                        31                                               /*!< MCIR: TLBP Position */
+#define MCIR_TLBP_Msk                        (0x1UL << MCIR_TLBP_Pos)                         /*!< MCIR: TLBP Mask */
+
+#define MCIR_TLBR_Pos                        30                                               /*!< MCIR: TLBR Position */
+#define MCIR_TLBR_Msk                        (0x1UL << MCIR_TLBR_Pos)                         /*!< MCIR: TLBR Mask */
+
+#define MCIR_TLBWI_Pos                       29                                               /*!< MCIR: TLBWI Position */
+#define MCIR_TLBWI_Msk                       (0x1UL << MCIR_TLBWI_Pos)                        /*!< MCIR: TLBWI Mask */
+
+#define MCIR_TLBWR_Pos                       28                                               /*!< MCIR: TLBWR Position */
+#define MCIR_TLBWR_Msk                       (0x1UL << MCIR_TLBWR_Pos)                        /*!< MCIR: TLBWR Mask */
+
+#define MCIR_TLBINV_Pos                      27                                               /*!< MCIR: TLBINV Position */
+#define MCIR_TLBINV_Msk                      (0x1UL << MCIR_TLBINV_Pos)                       /*!< MCIR: TLBINV Mask */
+
+#define MCIR_TLBINV_ALL_Pos                  26                                               /*!< MCIR: TLBINV_ALL Position */
+#define MCIR_TLBINV_ALL_Msk                  (0x1UL << MCIR_TLBINV_ALL_Pos)                   /*!< MCIR: TLBINV_ALL Mask */
+
+#define MCIR_TLBINV_INDEX_Pos                25                                               /*!< MCIR: TLBINV_INDEX Position */
+#define MCIR_TLBINV_INDEX_Msk                (0x1UL << MCIR_TLBINV_INDEX_Pos)                 /*!< MCIR: TLBINV_INDEX Mask */
+
+#define MCIR_ASID_Pos                        0                                                /*!< MCIR: ASID Position */
+#define MCIR_ASID_Msk                        (0xFFUL << MCIR_ASID_Pos)                        /*!< MCIR: ASID Mask */
+
+
+/*@} end of group CSI_CORE */
+
+
+/**
+  \ingroup    CSI_core_register
+  \defgroup   CSI_CACHE
+  \brief      Type definitions for the cache Registers
+  @{
+ */
+
+#define SSEG0_BASE_ADDR         0x80000000
+#define CACHE_RANGE_MAX_SIZE    0x80000
+
+#define INS_CACHE               (1 << 0)
+#define DATA_CACHE              (1 << 1)
+#define CACHE_INV               (1 << 4)
+#define CACHE_CLR               (1 << 5)
+#define CACHE_OMS               (1 << 6)
+#define CACHE_ITS               (1 << 7)
+#define CACHE_LICF              (1 << 31)
+
+#define    L1_CACHE_SHIFT       4      /* 16 Bytes */
+#define    L1_CACHE_BYTES       (1 << L1_CACHE_SHIFT)
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    ((value << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    ((value & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CSI_core_bitfield */
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core VIC Functions
+  - Core CORET Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/* ##########################  Cache functions  #################################### */
+/**
+  \ingroup  CSI_Core_FunctionInterface
+  \defgroup CSI_Core_CacheFunctions Cache Functions
+  \brief    Functions that configure Instruction and Data cache.
+  @{
+ */
+
+/**
+  \brief   Enable I-Cache
+  \details Turns on I-Cache
+  */
+__STATIC_INLINE void csi_icache_enable (void)
+{
+   __set_CCR(__get_CCR() | 0x00000004);
+}
+
+
+/**
+  \brief   Disable I-Cache
+  \details Turns off I-Cache
+  */
+__STATIC_INLINE void csi_icache_disable (void)
+{
+   __set_CCR(__get_CCR() & 0xFFFFFFFB);
+}
+
+
+/**
+  \brief   Invalidate I-Cache
+  \details Invalidates I-Cache
+  */
+__STATIC_INLINE void csi_icache_invalid (void)
+{
+    __set_CFR(0x11);
+    __set_CFR(INS_CACHE | CACHE_INV);
+}
+
+
+/**
+  \brief   Enable D-Cache
+  \details Turns on D-Cache
+  \note    I-Cache also turns on.
+  */
+__STATIC_INLINE void csi_dcache_enable (void)
+{
+   __set_CCR(__get_CCR() | 0x00000008);
+}
+
+
+/**
+  \brief   Disable D-Cache
+  \details Turns off D-Cache
+  \note    I-Cache also turns off.
+  */
+__STATIC_INLINE void csi_dcache_disable (void)
+{
+   __set_CCR(__get_CCR() & 0xFFFFFFF7);
+}
+
+
+/**
+  \brief   Invalidate D-Cache
+  \details Invalidates D-Cache
+  \note    I-Cache also invalid
+  */
+__STATIC_INLINE void csi_dcache_invalid (void)
+{
+    __set_CFR(DATA_CACHE | CACHE_INV);
+}
+
+
+/**
+  \brief   Clean D-Cache
+  \details Cleans D-Cache
+  \note    I-Cache also cleans
+  */
+__STATIC_INLINE void csi_dcache_clean (void)
+{
+    __set_CFR(DATA_CACHE | CACHE_CLR);
+}
+
+
+/**
+  \brief   Clean & Invalidate D-Cache
+  \details Cleans and Invalidates D-Cache
+  \note    I-Cache also flush.
+  */
+__STATIC_INLINE void csi_dcache_clean_invalid (void)
+{
+    __set_CFR(DATA_CACHE | CACHE_CLR | CACHE_INV);
+}
+
+__STATIC_INLINE  void set_cache_range (uint32_t start, uint32_t end, uint32_t value)
+{
+    if (!(start & SSEG0_BASE_ADDR) || (end - start) &~(CACHE_RANGE_MAX_SIZE - 1)) {
+        __set_CFR(value);
+    }
+
+    if (value & INS_CACHE) {
+        csi_icache_disable();
+    }
+    uint32_t i;
+    for (i = start; i < end; i += L1_CACHE_BYTES) {
+        __set_CIR(i);
+        __set_CFR(CACHE_OMS | value);
+    }
+
+    if (end & (L1_CACHE_BYTES-1)) {
+        __set_CIR(end);
+        __set_CFR(CACHE_OMS | value);
+    }
+
+    if (value & INS_CACHE) {
+        csi_icache_enable();
+    }
+
+}
+
+/**
+  \brief   D-Cache Invalidate by address
+  \details Invalidates D-Cache for the given address
+  \param[in]   addr    address (aligned to 16-byte boundary)
+  \param[in]   dsize   size of memory block (in number of bytes)
+*/
+__STATIC_INLINE void csi_dcache_invalid_range (uint32_t *addr, int32_t dsize)
+{
+    set_cache_range((uint32_t)addr, (uint32_t)addr + dsize, (DATA_CACHE | CACHE_INV));
+}
+
+
+/**
+  \brief   D-Cache Clean by address
+  \details Cleans D-Cache for the given address
+  \param[in]   addr    address (aligned to 16-byte boundary)
+  \param[in]   dsize   size of memory block (in number of bytes)
+*/
+__STATIC_INLINE void csi_dcache_clean_range (uint32_t *addr, int32_t dsize)
+{
+    set_cache_range((uint32_t)addr, (uint32_t)addr + dsize, (DATA_CACHE | CACHE_CLR));
+}
+
+
+/**
+  \brief   D-Cache Clean and Invalidate by address
+  \details Cleans and invalidates D_Cache for the given address
+  \param[in]   addr    address (aligned to 16-byte boundary)
+  \param[in]   dsize   size of memory block (in number of bytes)
+*/
+__STATIC_INLINE void csi_dcache_clean_invalid_range (uint32_t *addr, int32_t dsize)
+{
+    set_cache_range((uint32_t)addr, (uint32_t)addr + dsize, (DATA_CACHE | CACHE_CLR | CACHE_INV));
+}
+
+/*@} end of CSI_Core_CacheFunctions */
+
+
+/* ##########################  MMU functions  #################################### */
+/**
+  \ingroup  CSI_Core_FunctionInterface
+  \defgroup CSI_Core_MMUFunctions MMU Functions
+  \brief    Functions that configure MMU.
+  @{
+ */
+
+typedef struct {
+    uint32_t global: 1;         /* tlb page global access. */
+    uint32_t valid: 1;          /* tlb page valid */
+    uint32_t writeable: 1;      /* tlb page writeable */
+    uint32_t cacheable: 1;      /* tlb page cacheable*/
+} page_attr_t;
+
+typedef enum {
+    PAGE_SIZE_4KB   = 0x000,
+    PAGE_SIZE_16KB  = 0x003,
+    PAGE_SIZE_64KB  = 0x00F,
+    PAGE_SIZE_256KB = 0x03F,
+    PAGE_SIZE_1MB   = 0x0FF,
+    PAGE_SIZE_4MB   = 0x3FF,
+    PAGE_SIZE_16MB  = 0xFFF
+} page_size_e;
+
+/**
+  \brief  enable mmu
+  \details
+  */
+__STATIC_INLINE void csi_mmu_enable(void)
+{
+    __set_CCR(__get_CCR() | (1u << CCR_MP_Pos));
+}
+
+/**
+  \brief  disable mmu
+  \details
+  */
+__STATIC_INLINE void csi_mmu_disable(void)
+{
+    __set_CCR(__get_CCR() & (~(1u << CCR_MP_Pos)));
+}
+
+/**
+  \brief  create page with feature.
+  \details
+  \param [in]  vaddr     virtual address.
+  \param [in]  paddr     physical address.
+  \param [in]  asid      address sapce id (default: 0).
+  \param [in]  attr      \ref page_attr_t. tlb page attribute.
+  */
+__STATIC_INLINE void csi_mmu_set_tlb(uint32_t vaddr, uint32_t paddr, uint32_t asid, page_attr_t attr)
+{
+    MPR_Type pgmask;
+    MEL_Type mel;
+    MEH_Type meh;
+    uint32_t vaddr_bit = 0;
+    uint32_t page_feature = 0;
+
+    page_feature |= attr.global << MEL_G_Pos | attr.valid << MEL_V_Pos |
+                    attr.writeable << MEL_D_Pos | (attr.cacheable | 0x2) << MEL_C_Pos;
+
+    pgmask.w = __FF1(__get_MPR());
+    vaddr_bit = (pgmask.w == 32 ? 12 : (31 - pgmask.w));
+
+    meh.b.ASID = asid;
+    meh.b.VPN  = (vaddr & ((~pgmask.w | 0xFE000000) & 0xFFFFE000)) >> MEH_VPN_Pos;
+    __set_MEH(meh.w);
+
+    __set_MCIR(1u << MCIR_TLBP_Pos);
+
+    mel.w = (((paddr >> 6) & ~(pgmask.b.page_mask << 6)) | page_feature);
+
+    if (vaddr & (1 << vaddr_bit)) {
+        __set_MEL1(mel.w);
+    } else {
+        __set_MEL0(mel.w);
+    }
+
+    if (__get_MIR() & (1 << MIR_P_Pos)) {
+       __set_MCIR(1u << MCIR_TLBWR_Pos);
+    } else {
+       __set_MCIR(1u << MCIR_TLBWI_Pos);
+    }
+}
+
+
+/**
+  \brief  enble mmu
+  \details
+  \param [in]  size  tlb page size.
+  */
+__STATIC_INLINE void csi_mmu_set_pagesize(page_size_e size)
+{
+    MPR_Type mpr;
+    mpr.w = __get_MPR();
+    mpr.b.page_mask = size;
+    __set_MPR(mpr.w);
+}
+
+
+/**
+  \brief  read MEH, MEL0, MEL1 by tlb index.
+  \details
+  \param [in]    index  tlb index(0, 1, 2, ...)
+  \param [out]   meh    pointer to variable for retrieving MEH.
+  \param [out]   mel0   pointer to variable for retrieving MEL0.
+  \param [out]   mel1   pointer to variable for retrieving MEL1.
+  */
+__STATIC_INLINE void csi_mmu_read_by_index(uint32_t index, uint32_t *meh, uint32_t *mel0, uint32_t *mel1)
+{
+    MIR_Type mir;
+
+    if (meh == NULL || mel0 == NULL || mel1 == NULL) {
+        return;
+    }
+
+    mir.b.Index = index;
+    __set_MIR(mir.w);
+    __set_MCIR(1u << MCIR_TLBR_Pos);
+
+    *meh = __get_MEH();
+    *mel0 = __get_MEL0();
+    *mel1 = __get_MEL1();
+}
+
+
+/**
+  \brief  flush all mmu tlb.
+  \details
+  */
+__STATIC_INLINE void csi_mmu_invalid_tlb_all(void)
+{
+    __set_MCIR(1u << MCIR_TLBINV_ALL_Pos);
+}
+
+
+/**
+  \brief  flush mmu tlb by index.
+  \details
+  */
+__STATIC_INLINE void csi_mmu_invalid_tlb_by_index(uint32_t index)
+{
+    MIR_Type mir;
+
+    mir.b.Index = index;
+    __set_MIR(mir.w);
+    __set_MCIR(1u << MCIR_TLBINV_INDEX_Pos);
+}
+
+
+/**
+  \brief  flush mmu tlb by virtual address.
+  \details
+  */
+__STATIC_INLINE void csi_mmu_invalid_tlb_by_vaddr(uint32_t vaddr, uint32_t asid)
+{
+    __set_MEH(vaddr | (asid & MEH_ASID_Msk));
+    __set_MCIR(__get_MCIR() | (1 << MCIR_TLBP_Pos));
+
+    if (__get_MIR() & (1 << MIR_P_Pos)) {
+        return;
+    } else {
+        __set_MCIR(__get_MCIR() | (1 << MCIR_TLBINV_INDEX_Pos));
+    }
+}
+
+/*@} end of CSI_Core_MMUFunctions */
+
+/* ##########################  MPU functions  #################################### */
+/**
+  \ingroup  CSI_Core_FunctionInterface
+  \defgroup CSI_Core_MPUFunctions MPU Functions
+  \brief    Functions that configure MPU.
+  @{
+ */
+
+typedef enum {
+    REGION_SIZE_4KB      = 0xB,
+    REGION_SIZE_8KB      = 0xC,
+    REGION_SIZE_16KB     = 0xD,
+    REGION_SIZE_32KB     = 0xE,
+    REGION_SIZE_64KB     = 0xF,
+    REGION_SIZE_128KB    = 0x10,
+    REGION_SIZE_256KB    = 0x11,
+    REGION_SIZE_512KB    = 0x12,
+    REGION_SIZE_1MB      = 0x13,
+    REGION_SIZE_2MB      = 0x14,
+    REGION_SIZE_4MB      = 0x15,
+    REGION_SIZE_8MB      = 0x16,
+    REGION_SIZE_16MB     = 0x17,
+    REGION_SIZE_32MB     = 0x18,
+    REGION_SIZE_64MB     = 0x19,
+    REGION_SIZE_128MB    = 0x1A,
+    REGION_SIZE_256MB    = 0x1B,
+    REGION_SIZE_512MB    = 0x1C,
+    REGION_SIZE_1GB      = 0x1D,
+    REGION_SIZE_2GB      = 0x1E,
+    REGION_SIZE_4GB      = 0x1F
+} region_size_e;
+
+typedef enum {
+    AP_BOTH_INACCESSIBLE = 0,
+    AP_SUPER_RW_USER_INACCESSIBLE,
+    AP_SUPER_RW_USER_RDONLY,
+    AP_BOTH_RW
+} access_permission_e;
+
+typedef struct {
+    access_permission_e ap: 2;    /* super user and normal user access.*/
+    uint32_t c: 1;                /* cacheable */
+} mpu_region_attr_t;
+/**
+  \brief  enable mpu
+  \details
+  */
+__STATIC_INLINE void csi_mpu_enable(void)
+{
+    __set_CCR(__get_CCR() | CCR_MP_Msk);
+}
+
+/**
+  \brief  disable mpu
+  \details
+  */
+__STATIC_INLINE void csi_mpu_disable(void)
+{
+    __set_CCR(__get_CCR() & (~CCR_MP_Msk));
+}
+
+/**
+  \brief  configure memory protected region.
+  \details
+  \param [in]  idx        memory protected region (0, 1, 2, 3.).
+  \param [in]  base_addr  base address must be aligned with page size.
+  \param [in]  size       \ref region_size_e. memory protected region size.
+  \param [in]  attr       \ref region_size_t. memory protected region attribute.
+  \param [in]  enable     enable or disable memory protected region.
+  */
+__STATIC_INLINE void csi_mpu_config_region(uint32_t idx, uint32_t base_addr, region_size_e size,
+                                           mpu_region_attr_t attr, uint32_t enable)
+{
+    if (idx > 3) {
+        return;
+    }
+
+    CAPR_Type capr;
+    PACR_Type pacr;
+    PRSR_Type prsr;
+
+    capr.w = __get_CAPR();
+    pacr.w = __get_PACR();
+    prsr.w = __get_PRSR();
+
+    pacr.b.base_addr = (base_addr >> PACR_BASE_ADDR_Pos) & (0xFFFFF);
+
+    prsr.b.RID = idx;
+    __set_PRSR(prsr.w);
+
+    if (size != REGION_SIZE_4KB) {
+        pacr.w &= ~(((1u << (size -11)) - 1) << 12);
+    }
+
+    pacr.b.size = size;
+
+    capr.w = (0xFFFFFFFE & capr.w) | (attr.c << idx);
+    capr.w = ((~((0x3) << (2*idx + 8))) & capr.w) | (attr.ap << (2*idx + 8));
+    __set_CAPR(capr.w);
+
+    pacr.b.E = enable;
+    __set_PACR(pacr.w);
+}
+
+/**
+  \brief  enable mpu region by idx.
+  \details
+  \param [in]  idx        memory protected region (0, 1, 2, 3.).
+  */
+__STATIC_INLINE void csi_mpu_enable_region(uint32_t idx)
+{
+    if (idx > 3) {
+        return;
+    }
+
+    __set_PRSR((__get_PRSR() & (~PRSR_RID_Msk)) | idx);
+    __set_PACR(__get_PACR() | PACR_E_Msk);
+}
+
+/**
+  \brief  disable mpu region by idx.
+  \details
+  \param [in]  idx        memory protected region (0, 1, 2, 3.).
+  */
+__STATIC_INLINE void csi_mpu_disable_region(uint32_t idx)
+{
+    if (idx > 3) {
+        return;
+    }
+
+    __set_PRSR((__get_PRSR() & (~PRSR_RID_Msk)) | idx);
+    __set_PACR(__get_PACR() & (~PACR_E_Msk));
+}
+
+/*@} end of CSI_Core_MMUFunctions */
+
+/*@} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CK610_H_DEPENDANT */
+
+#endif /* __CSI_GENERIC */

lib/sec_library/include/core/core_ck801.h

@@ -0,0 +1,18 @@
+/*
+ * Copyright (C) 2017-2019 Alibaba Group Holding Limited
+ */
+
+
+/******************************************************************************
+ * @file     core_ck801.h
+ * @brief    CSI CK801 Core Peripheral Access Layer Header File
+ * @version  V1.0
+ * @date     02. June 2017
+ ******************************************************************************/
+
+#ifndef __CORE_CK801_H_GENERIC
+#define __CORE_CK801_H_GENERIC
+
+#include <core_801.h>
+
+#endif /* __CORE_CK801_H_DEPENDANT */

lib/sec_library/include/core/core_ck802.h

@@ -0,0 +1,18 @@
+/*
+ * Copyright (C) 2017-2019 Alibaba Group Holding Limited
+ */
+
+
+/******************************************************************************
+ * @file     core_ck802.h
+ * @brief    CSI CK802 Core Peripheral Access Layer Header File
+ * @version  V1.0
+ * @date     02. June 2017
+ ******************************************************************************/
+
+#ifndef __CORE_CK802_H_GENERIC
+#define __CORE_CK802_H_GENERIC
+
+#include <core_802.h>
+
+#endif /* __CORE_CK802_H_DEPENDANT */

lib/sec_library/include/core/core_ck803.h

@@ -0,0 +1,18 @@
+/*
+ * Copyright (C) 2017-2019 Alibaba Group Holding Limited
+ */
+
+
+/******************************************************************************
+ * @file     core_ck803.h
+ * @brief    CSI CK803 Core Peripheral Access Layer Header File
+ * @version  V1.0
+ * @date     02. June 2017
+ ******************************************************************************/
+
+#ifndef __CORE_CK803_H_GENERIC
+#define __CORE_CK803_H_GENERIC
+
+#include <core_803.h>
+
+#endif /* __CORE_CK803_H_DEPENDANT */

lib/sec_library/include/core/core_ck807.h

@@ -0,0 +1,847 @@
+/*
+ * Copyright (C) 2017-2019 Alibaba Group Holding Limited
+ */
+
+
+/******************************************************************************
+ * @file     core_ck807.h
+ * @brief    CSI CK807 Core Peripheral Access Layer Header File
+ * @version  V1.0
+ * @date     26. Jan 2018
+ ******************************************************************************/
+
+#ifndef __CORE_CK807_H_GENERIC
+#define __CORE_CK807_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*******************************************************************************
+ *                 CSI definitions
+ ******************************************************************************/
+/**
+  \ingroup CK807
+  @{
+ */
+
+/*  CSI CK807 definitions */
+#define __CK807_CSI_VERSION_MAIN  (0x04U)                                      /*!< [31:16] CSI HAL main version */
+#define __CK807_CSI_VERSION_SUB   (0x1EU)                                      /*!< [15:0]  CSI HAL sub version */
+#define __CK807_CSI_VERSION       ((__CK807_CSI_VERSION_MAIN << 16U) | \
+                                   __CK807_CSI_VERSION_SUB           )         /*!< CSI HAL version number */
+
+#ifndef __CK807
+#define __CK807                   (0x07U)                                      /*!< CK807 Core */
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not.
+*/
+#define __FPU_USED       1U
+
+#if defined ( __GNUC__ )
+#if defined (__VFP_FP__) && !defined(__SOFTFP__)
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CK807_H_GENERIC */
+
+#ifndef __CSI_GENERIC
+
+#ifndef __CORE_CK807_H_DEPENDANT
+#define __CORE_CK807_H_DEPENDANT
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#ifndef __CK807_REV
+#define __CK807_REV               0x0000U
+#endif
+
+#ifndef __GSR_GCR_PRESENT
+#define __GSR_GCR_PRESENT         0U
+#endif
+
+#ifndef __ICACHE_PRESENT
+#define __ICACHE_PRESENT          1U
+#endif
+
+#ifndef __DCACHE_PRESENT
+#define __DCACHE_PRESENT          1U
+#endif
+
+#include <csi_gcc.h>
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CSI_glob_defs CSI Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+#define     __I      volatile             /*!< Defines 'read only' permissions */
+#else
+#define     __I      volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O      volatile             /*!< Defines 'write only' permissions */
+#define     __IO     volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const       /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile             /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile             /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group CK807 */
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+ ******************************************************************************/
+/**
+  \defgroup CSI_core_register Defines and Type Definitions
+  \brief Type definitions and defines for CK807 processor based devices.
+*/
+
+/**
+  \ingroup    CSI_core_register
+  \defgroup   CSI_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Access Processor Status Register(PSR)struct definition.
+ */
+typedef union {
+    struct {
+        uint32_t C: 1;                       /*!< bit:      0  Conditional code/Carry flag */
+        uint32_t _reserved0: 5;              /*!< bit:  2.. 5  Reserved */
+        uint32_t IE: 1;                      /*!< bit:      6  Interrupt effective control bit */
+        uint32_t IC: 1;                      /*!< bit:      7  Interrupt control bit */
+        uint32_t EE: 1;                      /*!< bit:      8  Abnormally effective control bit */
+        uint32_t MM: 1;                      /*!< bit:      9  Unsymmetrical masking bit */
+        uint32_t _reserved1: 6;              /*!< bit: 10..15  Reserved */
+        uint32_t VEC: 8;                     /*!< bit: 16..23  Abnormal event vector value */
+        uint32_t _reserved2: 5;              /*!< bit: 24..28  Reserved */
+        uint32_t SP: 1;                      /*!< bit:     29  Secure pedning bit */
+        uint32_t T: 1;                       /*!< bit:     30  TEE mode bit */
+        uint32_t S: 1;                       /*!< bit:     31  Superuser mode set bit */
+    } b;                                   /*!< Structure    Access by bit */
+    uint32_t w;                            /*!< Type         Access by whole register */
+} PSR_Type;
+
+/* PSR Register Definitions */
+#define PSR_S_Pos                          31U                                            /*!< PSR: S Position */
+#define PSR_S_Msk                          (1UL << PSR_S_Pos)                             /*!< PSR: S Mask */
+
+#define PSR_VEC_Pos                        16U                                            /*!< PSR: VEC Position */
+#define PSR_VEC_Msk                        (0x7FUL << PSR_VEC_Pos)                        /*!< PSR: VEC Mask */
+
+#define PSR_MM_Pos                         9U                                             /*!< PSR: MM Position */
+#define PSR_MM_Msk                         (1UL << PSR_MM_Pos)                            /*!< PSR: MM Mask */
+
+#define PSR_EE_Pos                         8U                                             /*!< PSR: EE Position */
+#define PSR_EE_Msk                         (1UL << PSR_EE_Pos)                            /*!< PSR: EE Mask */
+
+#define PSR_IC_Pos                         7U                                             /*!< PSR: IC Position */
+#define PSR_IC_Msk                         (1UL << PSR_IC_Pos)                            /*!< PSR: IC Mask */
+
+#define PSR_IE_Pos                         6U                                             /*!< PSR: IE Position */
+#define PSR_IE_Msk                         (1UL << PSR_IE_Pos)                            /*!< PSR: IE Mask */
+
+#define PSR_C_Pos                          0U                                             /*!< PSR: C Position */
+#define PSR_C_Msk                          (1UL << PSR_C_Pos)                             /*!< PSR: C Mask */
+
+/**
+  \brief Consortium definition for accessing Cache Configuration Registers(CCR, CR<18, 0>).
+ */
+typedef union {
+    struct {
+        uint32_t MP: 2;                      /*!< bit:  0.. 1  memory protection settings */
+        uint32_t IE: 1;                      /*!< bit:      2  Instruction cache enable */
+        uint32_t DE: 1;                      /*!< bit:      3  Data cache enable */
+        uint32_t WB: 1;                      /*!< bit:      4  Cache write back */
+        uint32_t RS: 1;                      /*!< bit:      5  Address return stack settings */
+        uint32_t Z: 1;                       /*!< bit:      6  Allow predictive jump bit */
+        uint32_t BE: 1;                      /*!< bit:      7  Endian mode */
+        uint32_t SCK: 3;                     /*!< bit:  8..10  the clock ratio of the system and the processor */
+        uint32_t _reserved0: 1;              /*!< bit:     11  Reserved */
+        uint32_t WA: 1;                      /*!< bit:     12  Write allocate enable */
+        uint32_t E_V2: 1;                    /*!< bit:     13  V2 Endian mode */
+        uint32_t BSTE: 1;                    /*!< bit:     14  Burst transmit enable */
+        uint32_t IPE: 1;                     /*!< bit:     15  Indirect predict enable */
+        uint32_t _reserved1: 16;             /*!< bit: 16..31  Reserved */
+    } b;                                   /*!< Structure    Access by bit */
+    uint32_t w;                            /*!< Type         Access by whole register */
+} CCR_Type;
+
+/* CCR Register Definitions */
+#define CCR_IPE_Pos                       15u                                            /*!< CCR: IPE Position */
+#define CCR_IPE_Msk                       (0x1UL << CCR_IPE_Pos)                         /*!< CCR: IPE Mask */
+
+#define CCR_BSTE_Pos                      14u                                            /*!< CCR: BSTE Position */
+#define CCR_BSTE_Msk                      (0x1UL << CCR_BSTE_Pos)                        /*!< CCR: BSTE Mask */
+
+#define CCR_E_V2_Pos                      13U                                            /*!< CCR: E_V2 Position */
+#define CCR_E_V2_Msk                      (0x1UL << CCR_E_V2_Pos)                        /*!< CCR: E_V2 Mask */
+
+#define CCR_WA_Pos                        12u                                            /*!< CCR: WA Position */
+#define CCR_WA_Msk                        (0x1UL << CCR_WA_Pos)                          /*!< CCR: WA Mask */
+
+#define CCR_SCK_Pos                       8U                                             /*!< CCR: SCK Position */
+#define CCR_SCK_Msk                       (0x3UL << CCR_SCK_Pos)                         /*!< CCR: SCK Mask */
+
+#define CCR_BE_Pos                        7U                                             /*!< CCR: BE Position */
+#define CCR_BE_Msk                        (0x1UL << CCR_BE_Pos)                          /*!< CCR: BE Mask */
+
+#define CCR_Z_Pos                         6U                                             /*!< CCR: Z Position */
+#define CCR_Z_Msk                         (0x1UL << CCR_BE_Pos)                          /*!< CCR: Z Mask */
+
+#define CCR_RS_Pos                        5U                                             /*!< CCR: RS Position */
+#define CCR_RS_Msk                        (0x1UL << CCR_BE_Pos)                          /*!< CCR: RS Mask */
+
+#define CCR_WB_Pos                        4U                                             /*!< CCR: WB Position */
+#define CCR_WB_Msk                        (0x1UL << CCR_BE_Pos)                          /*!< CCR: WB Mask */
+
+#define CCR_DE_Pos                        3U                                             /*!< CCR: DE Position */
+#define CCR_DE_Msk                        (0x1UL << CCR_BE_Pos)                          /*!< CCR: DE Mask */
+
+#define CCR_IE_Pos                        2U                                             /*!< CCR: IE Position */
+#define CCR_IE_Msk                        (0x1UL << CCR_BE_Pos)                          /*!< CCR: IE Mask */
+
+#define CCR_MP_Pos                        0U                                             /*!< CCR: MP Position */
+#define CCR_MP_Msk                        (0x3UL << CCR_MP_Pos)                          /*!< CCR: MP Mask */
+
+/**
+  \brief  Consortium definition for accessing mmu index register(MIR,CR<0,15>).
+ */
+typedef union {
+    struct {
+        uint32_t Index: 10;                  /*!< bit:   0.. 9   TLB index */
+        uint32_t _reserved: 20;              /*!< bit:  10.. 29  Reserved */
+        uint32_t TF: 1;                      /*!< bit:       30  TLB fatal error */
+        uint32_t P: 1;                       /*!< bit:       31  TLBP instruction */
+    } b;
+    uint32_t w;
+} MIR_Type;
+
+/* MIR Register Definitions */
+#define MIR_P_Pos                          31                                            /*!< PRSR: P(TLBP instruction) Position */
+#define MIR_P_Msk                          (0x1UL << MIR_P_Pos)                          /*!< PRSR: P(TLBP instruction) Mask */
+
+#define MIR_TF_Pos                         30                                            /*!< PRSR: Tfatal Position */
+#define MIR_TF_Msk                         (0x1UL << MIR_TF_Pos)                         /*!< PRSR: Tfatal Mask */
+
+#define MIR_Index_Pos                      0                                             /*!< PRSR: Index Position */
+#define MIR_Index_Msk                      (0x3ffUL << MIR_Index_Pos)                    /*!< PRSR: Index Mask */
+
+
+/**
+  \brief  Consortium definition for accessing mmu entry of high physical address register(MEL, CR<2,15> and CR<3,15>).
+ */
+typedef union {
+    struct {
+        uint32_t G: 1;                        /*!< bit:       0   Global enbale bit */
+        uint32_t V: 1;                        /*!< bit:       1   TLB mapping valid bit */
+        uint32_t D: 1;                        /*!< bit:       2   TLB Page dirty bit */
+        uint32_t C: 1;                        /*!< bit:       3   TLB Page cacheable bit */
+        uint32_t SEC: 1;                      /*!< bit:       4   TLB Page security bit */
+        uint32_t SO: 1;                       /*!< bit:       2   Strong order enable bit */
+        uint32_t B: 1;                        /*!< bit:       2   TLB Page bufferable bit */
+        uint32_t _reserved: 5;                /*!< bit:   7.. 11  Reserved */
+        uint32_t PFN: 20;                     /*!< bit:  12.. 31  Physical frame number */
+    } b;
+    uint32_t w;
+} MEL_Type;
+
+/* MEL Register Definitions */
+#define MEL_PFN_Pos                        12                                            /*!< MEL: PFN Position */
+#define MEL_PFN_Msk                        (0xFFFFFUL << MEL_PFN_Pos)                    /*!< MEL: PFN Mask */
+
+#define MEL_B_Pos                          6                                             /*!< MEL: B Position */
+#define MEL_B_Msk                          (0x1UL << MEL_B_Pos)                          /*!< MEL: B Mask */
+
+#define MEL_SO_Pos                         5                                             /*!< MEL: SO Position */
+#define MEL_SO_Msk                         (0x1UL << MEL_SO_Pos)                         /*!< MEL: SO Mask */
+
+#define MEL_SEC_Pos                        4                                             /*!< MEL: SEC Position */
+#define MEL_SEC_Msk                        (0x1UL << MEL_SEC_Pos)                        /*!< MEL: SEC Mask */
+
+#define MEL_C_Pos                          3                                             /*!< MEL: C Position */
+#define MEL_C_Msk                          (0x1UL << MEL_C_Pos)                          /*!< MEL: C Mask */
+
+#define MEL_D_Pos                          2                                             /*!< MEL: D Position */
+#define MEL_D_Msk                          (0x1UL << MIR_D_Pos)                          /*!< MEL: D Mask */
+
+#define MEL_V_Pos                          1                                             /*!< MEL: V Position */
+#define MEL_V_Msk                          (0x1UL << MIR_V_Pos)                          /*!< MEL: V Mask */
+
+#define MEL_G_Pos                          0                                             /*!< MEL: G Position */
+#define MEL_G_Msk                          (0x1UL << MIR_G_Pos)                          /*!< MEL: G Mask */
+
+
+/**
+  \brief  Consortium definition for accessing mmu entry of high physical address register(MEH, CR<4,15>).
+ */
+typedef union {
+    struct {
+        uint32_t ASID :8;                     /*!< bit:   0.. 7   ASID */
+        uint32_t _reserved :4;                /*!< bit:   7.. 10  Reserved */
+        uint32_t VPN :20;                     /*!< bit:  11.. 31  Virtual page number */
+    } b;
+    uint32_t w;
+} MEH_Type;
+
+/* MEH Register Definitions */
+#define MEH_VPN_Pos                        12                                             /*!< MEH: VPN Position */
+#define MEH_VPN_Msk                        (0xFFFFFUL << MEH_VPN_Pos)                     /*!< MEH: VPN Mask */
+
+#define MEH_ASID_Pos                       0                                              /*!< MEH: ASID Position */
+#define MEH_ASID_Msk                       (0xFFUL << MEH_ASID_Pos)                       /*!< MEH: ASID Mask */
+
+
+/**
+  \brief  Consortium definition for accessing mmu entry of high physical address register(MPR, CR<6,15>). 
+*/
+
+typedef union {
+    struct {
+        uint32_t _reserved0: 13;              /*!< bit:   0.. 12   Reserved */
+        uint32_t page_mask: 12;               /*!< bit:  13.. 24   Page mask */
+        uint32_t _reserved1: 7;               /*!< bit:  25.. 31   Reserved */
+    } b;
+    uint32_t w;
+} MPR_Type;
+
+/* MPR Register Definitions */
+#define MPR_PAGE_MASK_Pos                        13                                             /*!< MPR: PAGE_MASK Position */
+#define MPR_PAGE_MASK_Msk                        (0xFFFUL << MPR_PAGE_MASK_Pos)                 /*!< MPR: PAGE_MASK Mask */
+
+
+/**
+  \brief  Consortium definition for accessing mmu entry of high physical address register(CR<8,15>).
+ */
+typedef union {
+    struct {
+        uint32_t ASID: 8;                     /*!< bit:   0.. 7   ASID */
+        uint32_t _reserved: 17;               /*!< bit:   8.. 24  Reserved */
+        uint32_t TLBINV_INDEX: 1;             /*!< bit:       25  TLBINV_INDEX */
+        uint32_t TLBINV_ALL: 1;               /*!< bit:       26  TLBINV_ALL */
+        uint32_t TLBINV: 1;                   /*!< bit:       27  TLBINV */
+        uint32_t TLBWR: 1;                    /*!< bit:       28  TLBWR */
+        uint32_t TLBWI: 1;                    /*!< bit:       29  TLBWI */
+        uint32_t TLBR: 1;                     /*!< bit:       30  TLBR */
+        uint32_t TLBP: 1;                     /*!< bit:       31  TLBP */
+    } b;
+    uint32_t w;
+} MCIR_Type;
+
+/* MCIR Register Definitions */
+#define MCIR_TLBP_Pos                        31                                               /*!< MCIR: TLBP Position */
+#define MCIR_TLBP_Msk                        (0x1UL << MCIR_TLBP_Pos)                         /*!< MCIR: TLBP Mask */
+
+#define MCIR_TLBR_Pos                        30                                               /*!< MCIR: TLBR Position */
+#define MCIR_TLBR_Msk                        (0x1UL << MCIR_TLBR_Pos)                         /*!< MCIR: TLBR Mask */
+
+#define MCIR_TLBWI_Pos                       29                                               /*!< MCIR: TLBWI Position */
+#define MCIR_TLBWI_Msk                       (0x1UL << MCIR_TLBWI_Pos)                        /*!< MCIR: TLBWI Mask */
+
+#define MCIR_TLBWR_Pos                       28                                               /*!< MCIR: TLBWR Position */
+#define MCIR_TLBWR_Msk                       (0x1UL << MCIR_TLBWR_Pos)                        /*!< MCIR: TLBWR Mask */
+
+#define MCIR_TLBINV_Pos                      27                                               /*!< MCIR: TLBINV Position */
+#define MCIR_TLBINV_Msk                      (0x1UL << MCIR_TLBINV_Pos)                       /*!< MCIR: TLBINV Mask */
+
+#define MCIR_TLBINV_ALL_Pos                  26                                               /*!< MCIR: TLBINV_ALL Position */
+#define MCIR_TLBINV_ALL_Msk                  (0x1UL << MCIR_TLBINV_ALL_Pos)                   /*!< MCIR: TLBINV_ALL Mask */
+
+#define MCIR_TLBINV_INDEX_Pos                25                                               /*!< MCIR: TLBINV_INDEX Position */
+#define MCIR_TLBINV_INDEX_Msk                (0x1UL << MCIR_TLBINV_INDEX_Pos)                 /*!< MCIR: TLBINV_INDEX Mask */
+
+#define MCIR_ASID_Pos                        0                                                /*!< MCIR: ASID Position */
+#define MCIR_ASID_Msk                        (0xFFUL << MCIR_ASID_Pos)                        /*!< MCIR: ASID Mask */
+
+
+/*@} end of group CSI_CORE */
+
+
+/**
+  \ingroup    CSI_core_register
+  \defgroup   CSI_CACHE
+  \brief      Type definitions for the cache Registers
+  @{
+ */
+
+/**
+  \brief  Consortium definition for accessing protection area selection register(CFR,CR<17,0>).
+ */
+typedef union {
+    struct {
+        uint32_t CACHE_SEL: 2;                      /*!< bit:  0..1  Instruction and data cache selection */
+        uint32_t _reserved0: 2;                     /*!< bit:  2..3  Reserved */
+        uint32_t INV: 1;                            /*!< bit:     4  Invalid data in cache */
+        uint32_t CLR: 1;                            /*!< bit:     5  Clear the dirty tlb table */
+        uint32_t OMS: 1;                            /*!< bit:     6  Cache invalid and clear operation mode (one line or all line)*/
+        uint32_t ITS: 1;                            /*!< bit:     7  Cache invalid and clear operation mode (CIR used as virtual index or SET/WAY/LEVE index)*/
+        uint32_t _reserved1: 8;                     /*!< bit: 8..15  Reserved */
+        uint32_t BHT_INV: 1;                        /*!< bit:    16  Invalid data in branch history table */
+        uint32_t _reserved2: 14;                    /*!< bit: 17..30 Reserved */
+        uint32_t LICF: 1;                           /*!< bit:     31 Failure of clearing or invalid cache line */
+    } b;                                            /*!< Structure    Access by bit */
+    uint32_t w;                                     /*!< Type         Access by whole register */
+} CFR_Type;
+
+#define CFR_LICF_Pos                     31U                                             /*!< CFR: LICF Position */
+#define CFR_LICF_Msk                     (0x1UL << CFR_LICF_Pos)                         /*!< CFR: LICF Mask */
+
+#define CFR_BHT_INV_Pos                  16U                                             /*!< CFR: BHT Position */
+#define CFR_BHT_INV_Msk                  (0x1UL << CFR_BHT_INV_Pos)                      /*!< CFR: BHT Mask */
+
+#define CFR_ITS_Pos                      7U                                              /*!< CFR: ITS Position */
+#define CFR_ITS_Msk                      (0x1UL << CFR_ITS_Pos)                          /*!< CFR: ITS Mask */
+
+#define CFR_OMS_Pos                      6U                                              /*!< CFR: OMS Position */
+#define CFR_OMS_Msk                      (0x1UL << CFR_OMS_Pos)                          /*!< CFR: OMS Mask */
+
+#define CFR_CLR_Pos                      5U                                              /*!< CFR: CLR Position */
+#define CFR_CLR_Msk                      (0x1UL << CFR_CLR_Pos)                          /*!< CFR: CLR Mask */
+
+#define CFR_INV_Pos                      4U                                              /*!< CFR: INV Position */
+#define CFR_INV_Msk                      (0x1UL << CFR_INV_Pos)                          /*!< CFR: INV Mask */
+
+#define CFR_CACHE_SEL_Pos                0                                               /*!< CFR: CACHE_SEL Position */    
+#define CFR_CACHE_SEL_Msk                (0x3UL << CFR_CACHE_SEL_Pos)                    /*!< CFR: CACHE_SEL Masok */
+
+/* CFR Register Definitions */
+/*@} end of group CSI_CACHE */
+
+
+/**
+  \ingroup    CSI_core_register
+  \defgroup   CSI_CACHE
+  \brief      Type definitions for the cache Registers
+  @{
+ */
+#define SSEG0_BASE_ADDR         0x80000000
+#define CACHE_RANGE_MAX_SIZE    0x80000
+
+#define INS_CACHE               (1 << 0)
+#define DATA_CACHE              (1 << 1)
+#define CACHE_INV               (1 << 4)
+#define CACHE_CLR               (1 << 5)
+#define CACHE_OMS               (1 << 6)
+#define CACHE_ITS               (1 << 7)
+#define CACHE_LICF              (1 << 31)
+
+#define    L1_CACHE_SHIFT       4      /* 16 Bytes */
+#define    L1_CACHE_BYTES       (1 << L1_CACHE_SHIFT)
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    ((value << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    ((value & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CSI_core_bitfield */
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core VIC Functions
+  - Core CORET Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
+#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
+
+
+/* ##########################  Cache functions  #################################### */
+/**
+  \ingroup  CSI_Core_FunctionInterface
+  \defgroup CSI_Core_CacheFunctions Cache Functions
+  \brief    Functions that configure Instruction and Data cache.
+  @{
+ */
+
+/**
+  \brief   Enable I-Cache
+  \details Turns on I-Cache
+  */
+__STATIC_INLINE void csi_icache_enable (void)
+{
+   __set_CCR(__get_CCR() | 0x00000004);
+}
+
+
+/**
+  \brief   Disable I-Cache
+  \details Turns off I-Cache
+  */
+__STATIC_INLINE void csi_icache_disable (void)
+{
+   __set_CCR(__get_CCR() & 0xFFFFFFFB);
+}
+
+
+/**
+  \brief   Invalidate I-Cache
+  \details Invalidates I-Cache
+  */
+__STATIC_INLINE void csi_icache_invalid (void)
+{
+    __set_CFR(0x11);
+    __set_CFR(INS_CACHE | CACHE_INV);
+}
+
+
+/**
+  \brief   Enable D-Cache
+  \details Turns on D-Cache
+  \note    I-Cache also turns on.
+  */
+__STATIC_INLINE void csi_dcache_enable (void)
+{
+   __set_CCR(__get_CCR() | 0x00000008);
+}
+
+
+/**
+  \brief   Disable D-Cache
+  \details Turns off D-Cache
+  \note    I-Cache also turns off.
+  */
+__STATIC_INLINE void csi_dcache_disable (void)
+{
+   __set_CCR(__get_CCR() & 0xFFFFFFF7);
+}
+
+
+/**
+  \brief   Invalidate D-Cache
+  \details Invalidates D-Cache
+  \note    I-Cache also invalid
+  */
+__STATIC_INLINE void csi_dcache_invalid (void)
+{
+    __set_CFR(DATA_CACHE | CACHE_INV);
+}
+
+
+/**
+  \brief   Clean D-Cache
+  \details Cleans D-Cache
+  \note    I-Cache also cleans
+  */
+__STATIC_INLINE void csi_dcache_clean (void)
+{
+    __set_CFR(DATA_CACHE | CACHE_CLR);
+}
+
+/**
+  \brief   Clean & Invalidate D-Cache
+  \details Cleans and Invalidates D-Cache
+  \note    I-Cache also flush.
+  */
+__STATIC_INLINE void csi_dcache_clean_invalid (void)
+{
+    __set_CFR(DATA_CACHE | CACHE_CLR | CACHE_INV);
+}
+
+__STATIC_INLINE  void set_cache_range (uint32_t start, uint32_t end, uint32_t value)
+{
+    if (!(start & SSEG0_BASE_ADDR) || (end - start) &~(CACHE_RANGE_MAX_SIZE - 1)) {
+        __set_CFR(value);
+    }
+
+    if (value & INS_CACHE) {
+        csi_icache_disable();
+    }
+    uint32_t i;
+    for (i = start; i < end; i += L1_CACHE_BYTES) {
+        __set_CIR(i);
+        __set_CFR(CACHE_OMS | value);
+    }
+
+    if (end & (L1_CACHE_BYTES-1)) {
+        __set_CIR(end);
+        __set_CFR(CACHE_OMS | value);
+    }
+
+    if (value & INS_CACHE) {
+        csi_icache_enable();
+    }
+
+}
+
+/**
+  \brief   D-Cache Invalidate by address
+  \details Invalidates D-Cache for the given address
+  \param[in]   addr    address (aligned to 16-byte boundary)
+  \param[in]   dsize   size of memory block (in number of bytes)
+*/
+__STATIC_INLINE void csi_dcache_invalid_range (uint32_t *addr, int32_t dsize)
+{
+    set_cache_range((uint32_t)addr, (uint32_t)addr + dsize, (DATA_CACHE | CACHE_INV));
+}
+
+
+/**
+  \brief   D-Cache Clean by address
+  \details Cleans D-Cache for the given address
+  \param[in]   addr    address (aligned to 16-byte boundary)
+  \param[in]   dsize   size of memory block (in number of bytes)
+*/
+__STATIC_INLINE void csi_dcache_clean_range (uint32_t *addr, int32_t dsize)
+{
+    set_cache_range((uint32_t)addr, (uint32_t)addr + dsize, (DATA_CACHE | CACHE_CLR));
+}
+
+
+/**
+  \brief   D-Cache Clean and Invalidate by address
+  \details Cleans and invalidates D_Cache for the given address
+  \param[in]   addr    address (aligned to 16-byte boundary)
+  \param[in]   dsize   size of memory block (in number of bytes)
+*/
+__STATIC_INLINE void csi_dcache_clean_invalid_range (uint32_t *addr, int32_t dsize)
+{
+    set_cache_range((uint32_t)addr, (uint32_t)addr + dsize, (DATA_CACHE | CACHE_CLR | CACHE_INV));
+}
+
+
+/*@} end of CSI_Core_CacheFunctions */
+
+
+/* ##########################  MMU functions  #################################### */
+/**
+  \ingroup  CSI_Core_FunctionInterface
+  \defgroup CSI_Core_MMUFunctions MMU Functions
+  \brief    Functions that configure MMU.
+  @{
+ */
+
+typedef struct {
+    uint32_t global: 1;         /* tlb page global access. */
+    uint32_t valid: 1;          /* tlb page valid */
+    uint32_t writeable: 1;      /* tlb page writeable */
+    uint32_t cacheable: 1;      /* tlb page cacheable*/
+    uint32_t is_secure: 1;      /* tlb page security access */
+    uint32_t strong_order: 1;   /* the sequence of accessing data on tlb page is corresponding to the program flow? */
+    uint32_t bufferable: 1;     /* tlb page bufferable */
+} page_attr_t;
+
+typedef enum {
+    PAGE_SIZE_4KB   = 0x000,
+    PAGE_SIZE_16KB  = 0x003,
+    PAGE_SIZE_64KB  = 0x00F,
+    PAGE_SIZE_256KB = 0x03F,
+    PAGE_SIZE_1MB   = 0x0FF,
+    PAGE_SIZE_4MB   = 0x3FF,
+    PAGE_SIZE_16MB  = 0xFFF
+} page_size_e;
+
+
+/**
+  \brief  enable mmu
+  \details
+  */
+__STATIC_INLINE void csi_mmu_enable(void)
+{
+    __set_CCR(__get_CCR() | (1u << CCR_MP_Pos));
+}
+
+/**
+  \brief  disable mmu
+  \details
+  */
+__STATIC_INLINE void csi_mmu_disable(void)
+{
+    __set_CCR(__get_CCR() & (~(1u << CCR_MP_Pos)));
+}
+
+/**
+  \brief  create page with feature.
+  \details
+  \param [in]  vaddr     virtual address.
+  \param [in]  paddr     physical address.
+  \param [in]  asid      address sapce id (default: 0).
+  \param [in]  attr      \ref page_attr_t. tlb page attribute.
+  */
+__STATIC_INLINE void csi_mmu_set_tlb(uint32_t vaddr, uint32_t paddr, uint32_t asid, page_attr_t attr)
+{
+     MPR_Type pgmask;
+     MEH_Type meh;
+     MEL_Type mel;
+     uint32_t vaddr_bit;
+     uint32_t page_feature = 0;
+
+     page_feature |= attr.global << MEL_G_Pos | attr.valid << MEL_V_Pos |
+                     attr.writeable << MEL_D_Pos | attr.cacheable << MEL_C_Pos |
+                     attr.is_secure << MEL_SEC_Pos | attr.strong_order << MEL_SO_Pos |
+                     attr.bufferable << MEL_B_Pos;
+
+     pgmask.w = __get_MPR();
+     vaddr_bit = 44 - __FF0(~((uint32_t)pgmask.b.page_mask));
+
+     meh.b.ASID = (uint8_t)asid;
+     meh.b.VPN  = (vaddr & ((~pgmask.w | 0xFE000000) & 0xFFFFE000)) >> MEH_VPN_Pos;
+     __set_MEH(meh.w);
+
+     __set_MCIR(1u << MCIR_TLBP_Pos);
+
+     mel.w = ((paddr & ~(pgmask.b.page_mask << 12)) | page_feature);
+     if (vaddr & (1 << vaddr_bit)) {
+         __set_MEL1(mel.w);
+     }
+     else {
+         __set_MEL0(mel.w);
+     }
+
+     if (__get_MIR() & (1 << MIR_P_Pos)) {
+        __set_MCIR(1u << MCIR_TLBWR_Pos);
+     } else {
+        __set_MCIR(1u << MCIR_TLBWI_Pos);
+     }
+}
+
+
+/**
+  \brief  enble mmu
+  \details
+  \param [in]  size  tlb page size.
+  */
+__STATIC_INLINE void csi_mmu_set_pagesize(page_size_e size)
+{
+    MPR_Type pgmask;
+    pgmask.b.page_mask = size;
+    __set_MPR(pgmask.w);
+}
+
+
+/**
+  \brief  read MEH, MEL0, MEL1 by tlb index.
+  \details
+  \param [in]    index  tlb index(0, 1, 2, ...)
+  \param [out]   meh    pointer to variable for retrieving MEH.
+  \param [out]   mel0   pointer to variable for retrieving MEL0.
+  \param [out]   mel1   pointer to variable for retrieving MEL1.
+  */
+__STATIC_INLINE void csi_mmu_read_by_index(uint32_t index, uint32_t *meh, uint32_t *mel0, uint32_t *mel1)
+{
+    MIR_Type mir;
+
+    if (meh == NULL || mel0 == NULL || mel1 == NULL) {
+        return;
+    }
+
+    mir.b.Index = index;
+    __set_MIR(mir.w);
+    __set_MCIR(1u << MCIR_TLBR_Pos);
+
+    *meh = __get_MEH();
+    *mel0 = __get_MEL0();
+    *mel1 = __get_MEL1();
+}
+
+
+/**
+  \brief  flush all mmu tlb.
+  \details
+  */
+__STATIC_INLINE void csi_mmu_invalid_tlb_all(void)
+{
+    __set_MCIR(1u << MCIR_TLBINV_ALL_Pos);
+}
+
+/**
+  \brief  flush mmu tlb by index.
+  \details
+  */
+__STATIC_INLINE void csi_mmu_invalid_tlb_by_index(uint32_t index)
+{
+    MIR_Type mir;
+
+    mir.b.Index = index;
+    __set_MIR(mir.w);
+    __set_MCIR(1u << MCIR_TLBINV_INDEX_Pos);
+}
+
+
+/**
+  \brief  flush mmu tlb by virtual address.
+  \details
+  */
+__STATIC_INLINE void csi_mmu_invalid_tlb_by_vaddr(uint32_t vaddr, uint32_t asid)
+{
+    __set_MEH(vaddr | (asid & MEH_ASID_Msk));
+    __set_MCIR(1u << MCIR_TLBP_Pos);
+
+    if (__get_MIR() & (1 << MIR_P_Pos)) {
+        return;
+    } else {
+        __set_MCIR(1u << MCIR_TLBINV_INDEX_Pos);
+    }
+}
+
+/*@} end of CSI_Core_MMUFunctions */
+
+
+/* ##################################    IRQ Functions  ############################################ */
+
+/**
+  \brief   Save the Irq context
+  \details save the psr result before disable irq.
+  \param [in]      irq_num  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE uint32_t csi_irq_save(void)
+{
+    uint32_t result;
+    result = __get_PSR();
+    __disable_irq();
+    return(result);
+}
+
+/**
+  \brief   Restore the Irq context
+  \details restore saved primask state.
+  \param [in]      irq_state  psr irq state.
+ */
+__STATIC_INLINE void csi_irq_restore(uint32_t irq_state)
+{
+    __set_PSR(irq_state);
+}
+
+/*@} end of IRQ Functions */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CK807_H_DEPENDANT */
+
+#endif /* __CSI_GENERIC */

lib/sec_library/include/core/core_ck810.h

@@ -0,0 +1,854 @@
+/*
+ * Copyright (C) 2017-2019 Alibaba Group Holding Limited
+ */
+
+
+/******************************************************************************
+ * @file     core_ck810.h
+ * @brief    CSI CK810 Core Peripheral Access Layer Header File
+ * @version  V1.0
+ * @date     26. Jan 2018
+ ******************************************************************************/
+
+#ifndef __CORE_CK810_H_GENERIC
+#define __CORE_CK810_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*******************************************************************************
+ *                 CSI definitions
+ ******************************************************************************/
+/**
+  \ingroup CK810
+  @{
+ */
+
+/*  CSI CK810 definitions */
+#define __CK810_CSI_VERSION_MAIN  (0x04U)                                      /*!< [31:16] CSI HAL main version */
+#define __CK810_CSI_VERSION_SUB   (0x1EU)                                      /*!< [15:0]  CSI HAL sub version */
+#define __CK810_CSI_VERSION       ((__CK810_CSI_VERSION_MAIN << 16U) | \
+                                   __CK810_CSI_VERSION_SUB           )         /*!< CSI HAL version number */
+
+#ifndef __CK810
+#define __CK810                (0x0aU)                                         /*!< CK810 Core */
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not.
+*/
+#define __FPU_USED      1U
+
+#if defined ( __GNUC__ )
+#if defined (__VFP_FP__) && !defined(__SOFTFP__)
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CK810_H_GENERIC */
+
+#ifndef __CSI_GENERIC
+
+#ifndef __CORE_CK810_H_DEPENDANT
+#define __CORE_CK810_H_DEPENDANT
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#ifndef __CK810_REV
+#define __CK810_REV               0x0000U
+#endif
+
+#ifndef __GSR_GCR_PRESENT
+#define __GSR_GCR_PRESENT         0U
+#endif
+
+#ifndef __ICACHE_PRESENT
+#define __ICACHE_PRESENT          1U
+#endif
+
+#ifndef __DCACHE_PRESENT
+#define __DCACHE_PRESENT          1U
+#endif
+
+#include <csi_gcc.h>
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CSI_glob_defs CSI Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+#define     __I      volatile             /*!< Defines 'read only' permissions */
+#else
+#define     __I      volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O      volatile             /*!< Defines 'write only' permissions */
+#define     __IO     volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const       /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile             /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile             /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group CK810 */
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+ ******************************************************************************/
+/**
+  \defgroup CSI_core_register Defines and Type Definitions
+  \brief Type definitions and defines for CK810 processor based devices.
+*/
+
+/**
+  \ingroup    CSI_core_register
+  \defgroup   CSI_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Access Processor Status Register(PSR)struct definition.
+ */
+typedef union {
+    struct {
+        uint32_t C: 1;                       /*!< bit:      0  Conditional code/Carry flag */
+        uint32_t _reserved0: 5;              /*!< bit:  2.. 5  Reserved */
+        uint32_t IE: 1;                      /*!< bit:      6  Interrupt effective control bit */
+        uint32_t IC: 1;                      /*!< bit:      7  Interrupt control bit */
+        uint32_t EE: 1;                      /*!< bit:      8  Abnormally effective control bit */
+        uint32_t MM: 1;                      /*!< bit:      9  Unsymmetrical masking bit */
+        uint32_t _reserved1: 6;              /*!< bit: 10..15  Reserved */
+        uint32_t VEC: 8;                     /*!< bit: 16..23  Abnormal event vector value */
+        uint32_t _reserved2: 5;              /*!< bit: 24..28  Reserved */
+        uint32_t SP: 1;                      /*!< bit:     29  Secure pedning bit */
+        uint32_t T: 1;                       /*!< bit:     30  TEE mode bit */
+        uint32_t S: 1;                       /*!< bit:     31  Superuser mode set bit */
+    } b;                                   /*!< Structure    Access by bit */
+    uint32_t w;                            /*!< Type         Access by whole register */
+} PSR_Type;
+
+/* PSR Register Definitions */
+#define PSR_S_Pos                          31U                                            /*!< PSR: S Position */
+#define PSR_S_Msk                          (1UL << PSR_S_Pos)                             /*!< PSR: S Mask */
+
+#define PSR_VEC_Pos                        16U                                            /*!< PSR: VEC Position */
+#define PSR_VEC_Msk                        (0x7FUL << PSR_VEC_Pos)                        /*!< PSR: VEC Mask */
+
+#define PSR_MM_Pos                         9U                                             /*!< PSR: MM Position */
+#define PSR_MM_Msk                         (1UL << PSR_MM_Pos)                            /*!< PSR: MM Mask */
+
+#define PSR_EE_Pos                         8U                                             /*!< PSR: EE Position */
+#define PSR_EE_Msk                         (1UL << PSR_EE_Pos)                            /*!< PSR: EE Mask */
+
+#define PSR_IC_Pos                         7U                                             /*!< PSR: IC Position */
+#define PSR_IC_Msk                         (1UL << PSR_IC_Pos)                            /*!< PSR: IC Mask */
+
+#define PSR_IE_Pos                         6U                                             /*!< PSR: IE Position */
+#define PSR_IE_Msk                         (1UL << PSR_IE_Pos)                            /*!< PSR: IE Mask */
+
+#define PSR_C_Pos                          0U                                             /*!< PSR: C Position */
+#define PSR_C_Msk                          (1UL << PSR_C_Pos)                             /*!< PSR: C Mask */
+
+/**
+  \brief Consortium definition for accessing Cache Configuration Registers(CCR, CR<18, 0>).
+ */
+typedef union {
+    struct {
+        uint32_t MP: 2;                      /*!< bit:  0.. 1  memory protection settings */
+        uint32_t IE: 1;                      /*!< bit:      2  Instruction cache enable */
+        uint32_t DE: 1;                      /*!< bit:      3  Data cache enable */
+        uint32_t WB: 1;                      /*!< bit:      4  Cache write back */
+        uint32_t RS: 1;                      /*!< bit:      5  Address return stack settings */
+        uint32_t Z: 1;                       /*!< bit:      6  Allow predictive jump bit */
+        uint32_t BE: 1;                      /*!< bit:      7  Endian mode */
+        uint32_t SCK: 3;                     /*!< bit:  8..10  the clock ratio of the system and the processor */
+        uint32_t _reserved0: 1;              /*!< bit:     11  Reserved */
+        uint32_t WA: 1;                      /*!< bit:     12  Write allocate enable */
+        uint32_t E_V2: 1;                    /*!< bit:     13  V2 Endian mode */
+        uint32_t BSTE: 1;                    /*!< bit:     14  Burst transmit enable */
+        uint32_t IPE: 1;                     /*!< bit:     15  Indirect predict enable */
+        uint32_t _reserved1: 16;             /*!< bit: 16..31  Reserved */
+    } b;                                   /*!< Structure    Access by bit */
+    uint32_t w;                            /*!< Type         Access by whole register */
+} CCR_Type;
+
+/* CCR Register Definitions */
+#define CCR_IPE_Pos                       15u                                            /*!< CCR: IPE Position */
+#define CCR_IPE_Msk                       (0x1UL << CCR_IPE_Pos)                         /*!< CCR: IPE Mask */
+
+#define CCR_BSTE_Pos                      14u                                            /*!< CCR: BSTE Position */
+#define CCR_BSTE_Msk                      (0x1UL << CCR_BSTE_Pos)                        /*!< CCR: BSTE Mask */
+
+#define CCR_E_V2_Pos                      13U                                            /*!< CCR: E_V2 Position */
+#define CCR_E_V2_Msk                      (0x1UL << CCR_E_V2_Pos)                        /*!< CCR: E_V2 Mask */
+
+#define CCR_WA_Pos                        12u                                            /*!< CCR: WA Position */
+#define CCR_WA_Msk                        (0x1UL << CCR_WA_Pos)                          /*!< CCR: WA Mask */
+
+#define CCR_SCK_Pos                       8U                                             /*!< CCR: SCK Position */
+#define CCR_SCK_Msk                       (0x3UL << CCR_SCK_Pos)                         /*!< CCR: SCK Mask */
+
+#define CCR_BE_Pos                        7U                                             /*!< CCR: BE Position */
+#define CCR_BE_Msk                        (0x1UL << CCR_BE_Pos)                          /*!< CCR: BE Mask */
+
+#define CCR_Z_Pos                         6U                                             /*!< CCR: Z Position */
+#define CCR_Z_Msk                         (0x1UL << CCR_BE_Pos)                          /*!< CCR: Z Mask */
+
+#define CCR_RS_Pos                        5U                                             /*!< CCR: RS Position */
+#define CCR_RS_Msk                        (0x1UL << CCR_BE_Pos)                          /*!< CCR: RS Mask */
+
+#define CCR_WB_Pos                        4U                                             /*!< CCR: WB Position */
+#define CCR_WB_Msk                        (0x1UL << CCR_BE_Pos)                          /*!< CCR: WB Mask */
+
+#define CCR_DE_Pos                        3U                                             /*!< CCR: DE Position */
+#define CCR_DE_Msk                        (0x1UL << CCR_BE_Pos)                          /*!< CCR: DE Mask */
+
+#define CCR_IE_Pos                        2U                                             /*!< CCR: IE Position */
+#define CCR_IE_Msk                        (0x1UL << CCR_BE_Pos)                          /*!< CCR: IE Mask */
+
+#define CCR_MP_Pos                        0U                                             /*!< CCR: MP Position */
+#define CCR_MP_Msk                        (0x3UL << CCR_MP_Pos)                          /*!< CCR: MP Mask */
+
+/**
+  \brief  Consortium definition for accessing mmu index register(MIR,CR<0,15>).
+ */
+typedef union {
+    struct {
+        uint32_t Index: 10;                  /*!< bit:   0.. 9   TLB index */
+        uint32_t _reserved: 20;              /*!< bit:  10.. 29  Reserved */
+        uint32_t TF: 1;                      /*!< bit:       30  TLB fatal error */
+        uint32_t P: 1;                       /*!< bit:       31  TLBP instruction */
+    } b;
+    uint32_t w;
+} MIR_Type;
+
+/* MIR Register Definitions */
+#define MIR_P_Pos                          31                                            /*!< PRSR: P(TLBP instruction) Position */
+#define MIR_P_Msk                          (0x1UL << MIR_P_Pos)                          /*!< PRSR: P(TLBP instruction) Mask */
+
+#define MIR_TF_Pos                         30                                            /*!< PRSR: Tfatal Position */
+#define MIR_TF_Msk                         (0x1UL << MIR_TF_Pos)                         /*!< PRSR: Tfatal Mask */
+
+#define MIR_Index_Pos                      0                                             /*!< PRSR: Index Position */
+#define MIR_Index_Msk                      (0x3ffUL << MIR_Index_Pos)                    /*!< PRSR: Index Mask */
+
+
+/**
+  \brief  Consortium definition for accessing mmu entry of high physical address register(MEL, CR<2,15> and CR<3,15>).
+ */
+typedef union {
+    struct {
+        uint32_t G: 1;                        /*!< bit:       0   Global enbale bit */
+        uint32_t V: 1;                        /*!< bit:       1   TLB mapping valid bit */
+        uint32_t D: 1;                        /*!< bit:       2   TLB Page dirty bit */
+        uint32_t C: 1;                        /*!< bit:       3   TLB Page cacheable bit */
+        uint32_t SEC: 1;                      /*!< bit:       4   TLB Page security bit */
+        uint32_t SO: 1;                       /*!< bit:       2   Strong order enable bit */
+        uint32_t B: 1;                        /*!< bit:       2   TLB Page bufferable bit */
+        uint32_t _reserved: 5;                /*!< bit:   7.. 11  Reserved */
+        uint32_t PFN: 20;                     /*!< bit:  12.. 31  Physical frame number */
+    } b;
+    uint32_t w;
+} MEL_Type;
+
+/* MEL Register Definitions */
+#define MEL_PFN_Pos                        12                                            /*!< MEL: PFN Position */
+#define MEL_PFN_Msk                        (0xFFFFFUL << MEL_PFN_Pos)                    /*!< MEL: PFN Mask */
+
+#define MEL_B_Pos                          6                                             /*!< MEL: B Position */
+#define MEL_B_Msk                          (0x1UL << MEL_B_Pos)                          /*!< MEL: B Mask */
+
+#define MEL_SO_Pos                         5                                             /*!< MEL: SO Position */
+#define MEL_SO_Msk                         (0x1UL << MEL_SO_Pos)                         /*!< MEL: SO Mask */
+
+#define MEL_SEC_Pos                        4                                             /*!< MEL: SEC Position */
+#define MEL_SEC_Msk                        (0x1UL << MEL_SEC_Pos)                        /*!< MEL: SEC Mask */
+
+#define MEL_C_Pos                          3                                             /*!< MEL: C Position */
+#define MEL_C_Msk                          (0x1UL << MEL_C_Pos)                          /*!< MEL: C Mask */
+
+#define MEL_D_Pos                          2                                             /*!< MEL: D Position */
+#define MEL_D_Msk                          (0x1UL << MIR_D_Pos)                          /*!< MEL: D Mask */
+
+#define MEL_V_Pos                          1                                             /*!< MEL: V Position */
+#define MEL_V_Msk                          (0x1UL << MIR_V_Pos)                          /*!< MEL: V Mask */
+
+#define MEL_G_Pos                          0                                             /*!< MEL: G Position */
+#define MEL_G_Msk                          (0x1UL << MIR_G_Pos)                          /*!< MEL: G Mask */
+
+
+/**
+  \brief  Consortium definition for accessing mmu entry of high physical address register(MEH, CR<4,15>).
+ */
+typedef union {
+    struct {
+        uint32_t ASID :8;                     /*!< bit:   0.. 7   ASID */
+        uint32_t _reserved :4;                /*!< bit:   7.. 10  Reserved */
+        uint32_t VPN :20;                     /*!< bit:  11.. 31  Virtual page number */
+    } b;
+    uint32_t w;
+} MEH_Type;
+
+/* MEH Register Definitions */
+#define MEH_VPN_Pos                        12                                             /*!< MEH: VPN Position */
+#define MEH_VPN_Msk                        (0xFFFFFUL << MEH_VPN_Pos)                     /*!< MEH: VPN Mask */
+
+#define MEH_ASID_Pos                       0                                              /*!< MEH: ASID Position */
+#define MEH_ASID_Msk                       (0xFFUL << MEH_ASID_Pos)                       /*!< MEH: ASID Mask */
+
+
+/**
+  \brief  Consortium definition for accessing mmu entry of high physical address register(MPR, CR<6,15>).
+ */
+typedef union {
+    struct {
+        uint32_t _reserved0: 13;              /*!< bit:   0.. 12   Reserved */
+        uint32_t page_mask: 12;               /*!< bit:  13.. 24   Page mask */
+        uint32_t _reserved1: 7;               /*!< bit:  25.. 31   Reserved */
+    } b;
+    uint32_t w;
+} MPR_Type;
+
+/* MPR Register Definitions */
+#define MPR_PAGE_MASK_Pos                        13                                             /*!< MPR: PAGE_MASK Position */
+#define MPR_PAGE_MASK_Msk                        (0xFFFUL << MPR_PAGE_MASK_Pos)                 /*!< MPR: PAGE_MASK Mask */
+
+
+/**
+  \brief  Consortium definition for accessing mmu entry of high physical address register(CR<8,15>).
+ */
+typedef union {
+    struct {
+        uint32_t ASID: 8;                     /*!< bit:   0.. 7   ASID */
+        uint32_t _reserved: 17;               /*!< bit:   8.. 24  Reserved */
+        uint32_t TLBINV_INDEX: 1;             /*!< bit:       25  TLBINV_INDEX */
+        uint32_t TLBINV_ALL: 1;               /*!< bit:       26  TLBINV_ALL */
+        uint32_t TLBINV: 1;                   /*!< bit:       27  TLBINV */
+        uint32_t TLBWR: 1;                    /*!< bit:       28  TLBWR */
+        uint32_t TLBWI: 1;                    /*!< bit:       29  TLBWI */
+        uint32_t TLBR: 1;                     /*!< bit:       30  TLBR */
+        uint32_t TLBP: 1;                     /*!< bit:       31  TLBP */
+    } b;
+    uint32_t w;
+} MCIR_Type;
+
+/* MCIR Register Definitions */
+#define MCIR_TLBP_Pos                        31                                               /*!< MCIR: TLBP Position */
+#define MCIR_TLBP_Msk                        (0x1UL << MCIR_TLBP_Pos)                         /*!< MCIR: TLBP Mask */
+
+#define MCIR_TLBR_Pos                        30                                               /*!< MCIR: TLBR Position */
+#define MCIR_TLBR_Msk                        (0x1UL << MCIR_TLBR_Pos)                         /*!< MCIR: TLBR Mask */
+
+#define MCIR_TLBWI_Pos                       29                                               /*!< MCIR: TLBWI Position */
+#define MCIR_TLBWI_Msk                       (0x1UL << MCIR_TLBWI_Pos)                        /*!< MCIR: TLBWI Mask */
+
+#define MCIR_TLBWR_Pos                       28                                               /*!< MCIR: TLBWR Position */
+#define MCIR_TLBWR_Msk                       (0x1UL << MCIR_TLBWR_Pos)                        /*!< MCIR: TLBWR Mask */
+
+#define MCIR_TLBINV_Pos                      27                                               /*!< MCIR: TLBINV Position */
+#define MCIR_TLBINV_Msk                      (0x1UL << MCIR_TLBINV_Pos)                       /*!< MCIR: TLBINV Mask */
+
+#define MCIR_TLBINV_ALL_Pos                  26                                               /*!< MCIR: TLBINV_ALL Position */
+#define MCIR_TLBINV_ALL_Msk                  (0x1UL << MCIR_TLBINV_ALL_Pos)                   /*!< MCIR: TLBINV_ALL Mask */
+
+#define MCIR_TLBINV_INDEX_Pos                25                                               /*!< MCIR: TLBINV_INDEX Position */
+#define MCIR_TLBINV_INDEX_Msk                (0x1UL << MCIR_TLBINV_INDEX_Pos)                 /*!< MCIR: TLBINV_INDEX Mask */
+
+#define MCIR_ASID_Pos                        0                                                /*!< MCIR: ASID Position */
+#define MCIR_ASID_Msk                        (0xFFUL << MCIR_ASID_Pos)                        /*!< MCIR: ASID Mask */
+
+
+/*@} end of group CSI_CORE */
+
+
+/**
+  \ingroup    CSI_core_register
+  \defgroup   CSI_CACHE
+  \brief      Type definitions for the cache Registers
+  @{
+ */
+
+/**
+  \brief  Consortium definition for accessing protection area selection register(CFR,CR<17,0>).
+ */
+typedef union {
+    struct {
+        uint32_t CACHE_SEL: 2;                      /*!< bit:  0..1  Instruction and data cache selection */
+        uint32_t _reserved0: 2;                     /*!< bit:  2..3  Reserved */
+        uint32_t INV: 1;                            /*!< bit:     4  Invalid data in cache */
+        uint32_t CLR: 1;                            /*!< bit:     5  Clear the dirty tlb table */
+        uint32_t OMS: 1;                            /*!< bit:     6  Cache invalid and clear operation mode (one line or all line)*/
+        uint32_t ITS: 1;                            /*!< bit:     7  Cache invalid and clear operation mode (CIR used as virtual index or SET/WAY/LEVE index)*/
+        uint32_t UNLOCK: 1;                         /*!< bit:     8  Unclock data cache line. */
+        uint32_t _reserved1: 7;                     /*!< bit: 9..15  Reserved */
+        uint32_t BHT_INV: 1;                        /*!< bit:    16  Invalid data in branch history table */
+        uint32_t BTB_INV: 1;                        /*!< bit:    17  Invalid data in branch table buffer */
+        uint32_t _reserved2: 13;                    /*!< bit: 18..30 Reserved */
+        uint32_t LICF: 1;                           /*!< bit:     31 Failure of clearing or invalid cache line */
+    } b;                                            /*!< Structure    Access by bit */
+    uint32_t w;                                     /*!< Type         Access by whole register */
+} CFR_Type;
+
+#define CFR_LICF_Pos                     31U                                             /*!< CFR: LICF Position */
+#define CFR_LICF_Msk                     (0x1UL << CFR_LICF_Pos)                         /*!< CFR: LICF Mask */
+
+#define CFR_BTB_INV_Pos                  17U                                             /*!< CFR: BTB Position */
+#define CFR_BTB_INV_Msk                  (0x1UL << CFR_BTB_INV_Pos)                      /*!< CFR: BTB Mask */
+
+#define CFR_BHT_INV_Pos                  16U                                             /*!< CFR: BHT Position */
+#define CFR_BHT_INV_Msk                  (0x1UL << CFR_BHT_INV_Pos)                      /*!< CFR: BHT Mask */
+
+#define CFR_UNLOCK_Pos                   8U                                              /*!< CFR: UNLOCK Position */
+#define CFR_UNLOCK_Msk                   (0x1UL << CFR_UNLOCK_Pos)                       /*!< CFR: UNLOCK Mask */
+
+#define CFR_ITS_Pos                      7U                                              /*!< CFR: ITS Position */
+#define CFR_ITS_Msk                      (0x1UL << CFR_ITS_Pos)                          /*!< CFR: ITS Mask */
+
+#define CFR_OMS_Pos                      6U                                              /*!< CFR: OMS Position */
+#define CFR_OMS_Msk                      (0x1UL << CFR_OMS_Pos)                          /*!< CFR: OMS Mask */
+
+#define CFR_CLR_Pos                      5U                                              /*!< CFR: CLR Position */
+#define CFR_CLR_Msk                      (0x1UL << CFR_CLR_Pos)                          /*!< CFR: CLR Mask */
+
+#define CFR_INV_Pos                      4U                                              /*!< CFR: INV Position */
+#define CFR_INV_Msk                      (0x1UL << CFR_INV_Pos)                          /*!< CFR: INV Mask */
+
+#define CFR_CACHE_SEL_Pos                0                                               /*!< CFR: CACHE_SEL Position */    
+#define CFR_CACHE_SEL_Msk                (0x3UL << CFR_CACHE_SEL_Pos)                    /*!< CFR: CACHE_SEL Masok */
+
+/* CFR Register Definitions */
+/*@} end of group CSI_CACHE */
+
+
+/**
+  \ingroup    CSI_core_register
+  \defgroup   CSI_CACHE
+  \brief      Type definitions for the cache Registers
+  @{
+ */
+#define SSEG0_BASE_ADDR         0x80000000
+#define CACHE_RANGE_MAX_SIZE    0x80000
+
+#define INS_CACHE               (1 << 0)
+#define DATA_CACHE              (1 << 1)
+#define CACHE_INV               (1 << 4)
+#define CACHE_CLR               (1 << 5)
+#define CACHE_OMS               (1 << 6)
+#define CACHE_ITS               (1 << 7)
+#define CACHE_LICF              (1 << 31)
+
+#define    L1_CACHE_SHIFT       4      /* 16 Bytes */
+#define    L1_CACHE_BYTES       (1 << L1_CACHE_SHIFT)
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    ((value << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    ((value & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CSI_core_bitfield */
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core VIC Functions
+  - Core CORET Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
+#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
+
+
+/* ##########################  Cache functions  #################################### */
+/**
+  \ingroup  CSI_Core_FunctionInterface
+  \defgroup CSI_Core_CacheFunctions Cache Functions
+  \brief    Functions that configure Instruction and Data cache.
+  @{
+ */
+
+/**
+  \brief   Enable I-Cache
+  \details Turns on I-Cache
+  */
+__STATIC_INLINE void csi_icache_enable (void)
+{
+   __set_CCR(__get_CCR() | 0x00000004);
+}
+
+
+/**
+  \brief   Disable I-Cache
+  \details Turns off I-Cache
+  */
+__STATIC_INLINE void csi_icache_disable (void)
+{
+   __set_CCR(__get_CCR() & 0xFFFFFFFB);
+}
+
+
+/**
+  \brief   Invalidate I-Cache
+  \details Invalidates I-Cache
+  */
+__STATIC_INLINE void csi_icache_invalid (void)
+{
+    __set_CFR(0x11);
+    __set_CFR(INS_CACHE | CACHE_INV);
+}
+
+
+/**
+  \brief   Enable D-Cache
+  \details Turns on D-Cache
+  \note    I-Cache also turns on.
+  */
+__STATIC_INLINE void csi_dcache_enable (void)
+{
+   __set_CCR(__get_CCR() | 0x00000008);
+}
+
+
+/**
+  \brief   Disable D-Cache
+  \details Turns off D-Cache
+  \note    I-Cache also turns off.
+  */
+__STATIC_INLINE void csi_dcache_disable (void)
+{
+   __set_CCR(__get_CCR() & 0xFFFFFFF7);
+}
+
+
+/**
+  \brief   Invalidate D-Cache
+  \details Invalidates D-Cache
+  \note    I-Cache also invalid
+  */
+__STATIC_INLINE void csi_dcache_invalid (void)
+{
+    __set_CFR(DATA_CACHE | CACHE_INV);
+}
+
+
+/**
+  \brief   Clean D-Cache
+  \details Cleans D-Cache
+  \note    I-Cache also cleans
+  */
+__STATIC_INLINE void csi_dcache_clean (void)
+{
+    __set_CFR(DATA_CACHE | CACHE_CLR);
+}
+
+/**
+  \brief   Clean & Invalidate D-Cache
+  \details Cleans and Invalidates D-Cache
+  \note    I-Cache also flush.
+  */
+__STATIC_INLINE void csi_dcache_clean_invalid (void)
+{
+    __set_CFR(DATA_CACHE | CACHE_CLR | CACHE_INV);
+}
+
+__STATIC_INLINE  void set_cache_range (uint32_t start, uint32_t end, uint32_t value)
+{
+    if (!(start & SSEG0_BASE_ADDR) || (end - start) &~(CACHE_RANGE_MAX_SIZE - 1)) {
+        __set_CFR(value);
+    }
+
+    if (value & INS_CACHE) {
+        csi_icache_disable();
+    }
+    uint32_t i;
+    for (i = start; i < end; i += L1_CACHE_BYTES) {
+        __set_CIR(i);
+        __set_CFR(CACHE_OMS | value);
+    }
+
+    if (end & (L1_CACHE_BYTES-1)) {
+        __set_CIR(end);
+        __set_CFR(CACHE_OMS | value);
+    }
+
+    if (value & INS_CACHE) {
+        csi_icache_enable();
+    }
+
+}
+
+/**
+  \brief   D-Cache Invalidate by address
+  \details Invalidates D-Cache for the given address
+  \param[in]   addr    address (aligned to 16-byte boundary)
+  \param[in]   dsize   size of memory block (in number of bytes)
+*/
+__STATIC_INLINE void csi_dcache_invalid_range (uint32_t *addr, int32_t dsize)
+{
+    set_cache_range((uint32_t)addr, (uint32_t)addr + dsize, (DATA_CACHE | CACHE_INV));
+}
+
+
+/**
+  \brief   D-Cache Clean by address
+  \details Cleans D-Cache for the given address
+  \param[in]   addr    address (aligned to 16-byte boundary)
+  \param[in]   dsize   size of memory block (in number of bytes)
+*/
+__STATIC_INLINE void csi_dcache_clean_range (uint32_t *addr, int32_t dsize)
+{
+    set_cache_range((uint32_t)addr, (uint32_t)addr + dsize, (DATA_CACHE | CACHE_CLR));
+}
+
+
+/**
+  \brief   D-Cache Clean and Invalidate by address
+  \details Cleans and invalidates D_Cache for the given address
+  \param[in]   addr    address (aligned to 16-byte boundary)
+  \param[in]   dsize   size of memory block (in number of bytes)
+*/
+__STATIC_INLINE void csi_dcache_clean_invalid_range (uint32_t *addr, int32_t dsize)
+{
+    set_cache_range((uint32_t)addr, (uint32_t)addr + dsize, (DATA_CACHE | CACHE_CLR | CACHE_INV));
+}
+
+
+/*@} end of CSI_Core_CacheFunctions */
+
+/* ##########################  MMU functions  #################################### */
+/**
+  \ingroup  CSI_Core_FunctionInterface
+  \defgroup CSI_Core_MMUFunctions MMU Functions
+  \brief    Functions that configure MMU.
+  @{
+ */
+
+typedef struct {
+    uint32_t global: 1;         /* tlb page global access. */
+    uint32_t valid: 1;          /* tlb page valid */
+    uint32_t writeable: 1;      /* tlb page writeable */
+    uint32_t cacheable: 1;      /* tlb page cacheable*/
+    uint32_t is_secure: 1;      /* tlb page security access */
+    uint32_t strong_order: 1;   /* the sequence of accessing data on tlb page is corresponding to the program flow? */
+    uint32_t bufferable: 1;     /* tlb page bufferable */
+} page_attr_t;
+
+typedef enum {
+    PAGE_SIZE_4KB   = 0x000,
+    PAGE_SIZE_16KB  = 0x003,
+    PAGE_SIZE_64KB  = 0x00F,
+    PAGE_SIZE_256KB = 0x03F,
+    PAGE_SIZE_1MB   = 0x0FF,
+    PAGE_SIZE_4MB   = 0x3FF,
+    PAGE_SIZE_16MB  = 0xFFF
+} page_size_e;
+
+
+/**
+  \brief  enable mmu
+  \details
+  */
+__STATIC_INLINE void csi_mmu_enable(void)
+{
+    __set_CCR(__get_CCR() | (1u << CCR_MP_Pos));
+}
+
+/**
+  \brief  disable mmu
+  \details
+  */
+__STATIC_INLINE void csi_mmu_disable(void)
+{
+    __set_CCR(__get_CCR() & (~(1u << CCR_MP_Pos)));
+}
+
+/**
+  \brief  create page with feature.
+  \details
+  \param [in]  vaddr     virtual address.
+  \param [in]  paddr     physical address.
+  \param [in]  asid      address sapce id (default: 0).
+  \param [in]  attr      \ref page_attr_t. tlb page attribute.
+  */
+__STATIC_INLINE void csi_mmu_set_tlb(uint32_t vaddr, uint32_t paddr, uint32_t asid, page_attr_t attr)
+{
+     MPR_Type pgmask;
+     MEH_Type meh;
+     MEL_Type mel;
+     uint32_t vaddr_bit;
+     uint32_t page_feature = 0;
+
+     page_feature |= attr.global << MEL_G_Pos | attr.valid << MEL_V_Pos |
+                     attr.writeable << MEL_D_Pos | attr.cacheable << MEL_C_Pos |
+                     attr.is_secure << MEL_SEC_Pos | attr.strong_order << MEL_SO_Pos |
+                     attr.bufferable << MEL_B_Pos;
+
+     pgmask.w = __get_MPR();
+     vaddr_bit = 44 - __FF0(~((uint32_t)pgmask.b.page_mask));
+
+     meh.b.ASID = (uint8_t)asid;
+     meh.b.VPN  = (vaddr & ((~pgmask.w | 0xFE000000) & 0xFFFFE000)) >> MEH_VPN_Pos;
+     __set_MEH(meh.w);
+
+     __set_MCIR(1u << MCIR_TLBP_Pos);
+
+     mel.w = ((paddr & ~(pgmask.b.page_mask << 12)) | page_feature);
+     if (vaddr & (1 << vaddr_bit)) {
+         __set_MEL1(mel.w);
+     }
+     else {
+         __set_MEL0(mel.w);
+     }
+
+     if (__get_MIR() & (1 << MIR_P_Pos)) {
+        __set_MCIR(1u << MCIR_TLBWR_Pos);
+     } else {
+        __set_MCIR(1u << MCIR_TLBWI_Pos);
+     }
+}
+
+
+/**
+  \brief  enble mmu
+  \details
+  \param [in]  size  tlb page size.
+  */
+__STATIC_INLINE void csi_mmu_set_pagesize(page_size_e size)
+{
+    MPR_Type pgmask;
+    pgmask.b.page_mask = size;
+    __set_MPR(pgmask.w);
+}
+
+
+/**
+  \brief  read MEH, MEL0, MEL1 by tlb index.
+  \details
+  \param [in]    index  tlb index(0, 1, 2, ...)
+  \param [out]   meh    pointer to variable for retrieving MEH.
+  \param [out]   mel0   pointer to variable for retrieving MEL0.
+  \param [out]   mel1   pointer to variable for retrieving MEL1.
+  */
+__STATIC_INLINE void csi_mmu_read_by_index(uint32_t index, uint32_t *meh, uint32_t *mel0, uint32_t *mel1)
+{
+    MIR_Type mir;
+
+    if (meh == NULL || mel0 == NULL || mel1 == NULL) {
+        return;
+    }
+
+    mir.b.Index = index;
+    __set_MIR(mir.w);
+    __set_MCIR(1u << MCIR_TLBR_Pos);
+
+    *meh = __get_MEH();
+    *mel0 = __get_MEL0();
+    *mel1 = __get_MEL1();
+}
+
+
+/**
+  \brief  flush all mmu tlb.
+  \details
+  */
+__STATIC_INLINE void csi_mmu_invalid_tlb_all(void)
+{
+    __set_MCIR(1u << MCIR_TLBINV_ALL_Pos);
+}
+
+
+/**
+  \brief  flush mmu tlb by index.
+  \details
+  */
+__STATIC_INLINE void csi_mmu_invalid_tlb_by_index(uint32_t index)
+{
+    MIR_Type mir;
+
+    mir.b.Index = index;
+    __set_MIR(mir.w);
+    __set_MCIR(1u << MCIR_TLBINV_INDEX_Pos);
+}
+
+
+/**
+  \brief  flush mmu tlb by virtual address.
+  \details
+  */
+__STATIC_INLINE void csi_mmu_invalid_tlb_by_vaddr(uint32_t vaddr, uint32_t asid)
+{
+    __set_MEH(vaddr | (asid & MEH_ASID_Msk));
+    __set_MCIR(1u << MCIR_TLBP_Pos);
+
+    if (__get_MIR() & (1 << MIR_P_Pos)) {
+        return;
+    } else {
+        __set_MCIR(1u << MCIR_TLBINV_INDEX_Pos);
+    }
+}
+
+/*@} end of CSI_Core_MMUFunctions */
+
+
+/* ##################################    IRQ Functions  ############################################ */
+
+/**
+  \brief   Save the Irq context
+  \details save the psr result before disable irq.
+  \param [in]      irq_num  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE uint32_t csi_irq_save(void)
+{
+    uint32_t result;
+    result = __get_PSR();
+    __disable_irq();
+    return(result);
+}
+
+/**
+  \brief   Restore the Irq context
+  \details restore saved primask state.
+  \param [in]      irq_state  psr irq state.
+ */
+__STATIC_INLINE void csi_irq_restore(uint32_t irq_state)
+{
+    __set_PSR(irq_state);
+}
+
+/*@} end of IRQ Functions */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CK810_H_DEPENDANT */
+
+#endif /* __CSI_GENERIC */

lib/sec_library/include/csi_core.h

@@ -0,0 +1,62 @@
+/*
+ * Copyright (C) 2017-2019 Alibaba Group Holding Limited
+ */
+
+
+/******************************************************************************
+ * @file     csi_core.h
+ * @brief    CSI Core Layer Header File
+ * @version  V1.0
+ * @date     02. June 2017
+ ******************************************************************************/
+
+#ifndef _CORE_H_
+#define _CORE_H_
+
+#include <stdint.h>
+
+#if defined(__CK801__) || defined(__E801__)
+#include "core/core_801.h"
+#elif defined(__CK802__) || defined(__E802__) || defined(__E802T__) || defined(__S802__) || defined(__S802T__)
+#include "core/core_802.h"
+#elif defined(__CK804__) || defined(__E804D__) || defined(__E804DT__) || defined(__E804F__)  || defined(__E804FT__) || defined (__E804DF__) || defined(__E804DFT__)
+#include "core/core_804.h"
+#elif defined(__CK803__) || defined(__E803__) || defined(__E803T__) || defined(__S803__) || defined(__S803T__)
+#include "core/core_803.h"
+#elif defined(__CK805__) || defined(__I805__) || defined(__I805F__)
+#include "core/core_805.h"
+#elif defined(__CK610__)
+#include "core/core_ck610.h"
+#elif defined(__CK810__) || defined(__C810__) || defined(__C810T__) || defined(__C810V__) || defined(__C810VT__)
+#include "core/core_810.h"
+#elif defined(__CK807__) || defined(__C807__) || defined(__C807F__) || defined(__C807FV__) || defined(__R807__)
+#include "core/core_807.h"
+#elif defined(__riscv) && defined(CONFIG_CSKY_CORETIM)
+#include "core/core_rv32_old.h"
+#elif defined(__riscv) && (__riscv_xlen == 32)
+#include "core/core_rv32.h"
+#elif defined(__riscv) && (__riscv_xlen == 64)
+#include "core/core_rv64.h"
+#endif
+
+#if defined(__riscv) && (__riscv_xlen == 32)
+#include "core/csi_rv32_gcc.h"
+#elif defined(__riscv) && (__riscv_xlen == 64)
+#include "core/csi_rv64_gcc.h"
+#elif defined(__csky__)
+#include "core/csi_gcc.h"
+#endif
+
+#ifdef __arm__
+#include "csi_core_cmsis.h"
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _CORE_H_ */

lib/sec_library/include/csi_efuse_api.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2019-2021 Alibaba Group Holding Limited
+ * Copyright (C) 2019-2020 Alibaba Group Holding Limited
  */
 #ifndef __CSI_EFUSE_API_H__
 #define __CSI_EFUSE_API_H__
@@ -22,8 +22,7 @@ typedef enum {
 } img_encrypt_st_t;
 
 int csi_efuse_api_int(void);
-
-int csi_efuse_api_uninit(void);
+void csi_efuse_api_uninit(void);
 
 int csi_efuse_get_secure_boot_st(sboot_st_t *sboot_st);
 
@@ -53,4 +52,4 @@ int csi_efuse_write_raw(uint32_t addr, const void *data, uint32_t cnt);
 }
 #endif
 
-#endif	/* __CSI_EFUSE_API_H__ */
+#endif	/* __CSI_EFUSE_API_H__ */

lib/sec_library/include/csi_sec_img_verify.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2019-2021 Alibaba Group Holding Limited
+ * Copyright (C) 2019-2020 Alibaba Group Holding Limited
  */
 #ifndef __CSI_SEC_IMG_VERIFY_H__
 #define __CSI_SEC_IMG_VERIFY_H__
@@ -28,4 +28,4 @@ int csi_sec_get_lib_version(char ** p_version);
 }
 #endif
 
-#endif	/* __CSI_SEC_IMG_VERIFY_H__ */
+#endif	/* __CSI_SEC_IMG_VERIFY_H__ */

lib/sec_library/include/des.h

@@ -0,0 +1,221 @@
+/*
+ * Copyright (C) 2017-2020 Alibaba Group Holding Limited
+ */
+
+/******************************************************************************
+ * @file       drv/des.h
+ * @brief      Header File for DES Driver
+ * @version    V1.0
+ * @date       24. Oct 2022
+ * @model      des
+ ******************************************************************************/
+
+#ifndef _DRV_DES_H_
+#define _DRV_DES_H_
+
+#include <stdint.h>
+#include "common.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*----- Encrypt & Decrypt: Config key length -----*/
+/**
+\brief DES data transfer mode config
+*/
+typedef enum {
+    DES_SLAVE_MODE = 0U,         ///< slave mode
+    DES_DMA_MODE,                ///< dma mode
+} csi_des_trans_mode_t;
+
+/**
+\brief DES key-len-bits type
+*/
+typedef enum {
+    DES_KEY_LEN_BITS_64        = 0,        ///< 64 Data bits
+    DES_KEY_LEN_BITS_128,                  ///< 128 Data bits
+    DES_KEY_LEN_BITS_192,                  ///< 192 Data bits
+} csi_des_key_bits_t;
+
+typedef enum{
+    DES_MODE_ECB    = 0x00000000,
+    DES_MODE_CBC    = 0x20000020,
+    TDES_MODE_ECB   = 0x00000008,
+    TDES_MODE_CBC   = 0x20000028,
+} des_mode_t;
+
+
+#define DES_KEY_LEN_BYTES_32    (32)
+#define DES_KEY_LEN_BYTES_16    (16)
+#define DES_KEY_LEN_BYTES_24    (24)
+#define DES_KEY_LEN_BYTES_8     (8)
+
+#define DES_BLOCK_IV_SIZE       (16)
+#define DES_BLOCK_CRYPTO_SIZE   (8)
+#define TDES_BLOCK_CRYPTO_SIZE  (16)
+
+#define DES_DIR_ENCRYPT         (1)
+#define DES_DIR_DECRYPT         (0)
+
+#define DES_KEY_128_BITS        (0x8)
+#define DES_KEY_192_BITS        (0x10)
+
+/**
+\brief DES State
+*/
+typedef struct {
+    uint32_t busy             : 1;        ///< Calculate busy flag
+    uint32_t error            : 1;        ///< Calculate error flag
+} csi_des_state_t;
+
+/**
+\brief DES Context
+*/
+typedef struct {
+    uint32_t            key_len_byte;
+    uint8_t             key[32];          ///< Data block being processed
+    uint32_t            sca;
+    uint32_t            is_kdf;
+    uint32_t            is_dma;
+} csi_des_context_t;
+
+/**
+\brief DES Ctrl Block
+*/
+typedef struct {
+    csi_des_state_t         state;
+    csi_des_context_t       context;
+    csi_dev_t               dev;
+    void                    *priv;
+} csi_des_t;
+
+/**
+  \brief       Initialize DES interface. Initializes the resources needed for the DES interface
+  \param[in]   des    Handle to operate
+  \param[in]   idx    Device id
+  \return      Error code \ref csi_error_t
+*/
+csi_error_t csi_des_init(csi_des_t *des, uint32_t idx);
+
+/**
+  \brief       De-initialize DES interface. Stops operation and releases the software resources used by the interface
+  \param[in]   des    Dandle to operate
+  \return      None
+*/
+void csi_des_uninit(csi_des_t *des);
+
+/**
+  \brief       Set encrypt key
+  \param[in]   des        Handle to operate
+  \param[in]   key        Pointer to the key buf
+  \param[in]   key_len    Pointer to \ref csi_des_key_bits_t
+  \return      Error code \ref Csi_error_t
+*/
+csi_error_t csi_des_set_encrypt_key(csi_des_t *des, void *key, csi_des_key_bits_t key_len);
+
+/**
+  \brief       Set decrypt key
+  \param[in]   des        Handle to operate
+  \param[in]   key        Pointer to the key buf
+  \param[in]   key_len    Pointer to \ref csi_des_key_bits_t
+  \return      Error code \ref Csi_error_t
+*/
+csi_error_t csi_des_set_decrypt_key(csi_des_t *des, void *key, csi_des_key_bits_t key_len);
+
+/**
+  \brief       DES ecb encrypt
+  \param[in]   des     Handle to operate
+  \param[in]   in      Pointer to the source data
+  \param[out]  out     Pointer to the result data
+  \param[in]   size    The source data size
+  \return      Error code \ref Csi_error_t
+*/
+csi_error_t csi_des_ecb_encrypt(csi_des_t *des, void *in, void *out, uint32_t size);
+
+/**
+  \brief       DES ecb decrypt
+  \param[in]   des     Handle to operate
+  \param[in]   in      Pointer to the source data
+  \param[out]  out     Pointer to the result data
+  \param[in]   size    The source data size
+  \return      Error code \ref Csi_error_t
+*/
+csi_error_t csi_des_ecb_decrypt(csi_des_t *des, void *in, void *out, uint32_t size);
+
+/**
+  \brief       DES cbc encrypt
+  \param[in]   des     Handle to operate
+  \param[in]   in      Pointer to the source data
+  \param[out]  out     Pointer to the result data
+  \param[in]   size    The source data size
+  \param[in]   iv      Init vector
+  \return      Error code \ref Csi_error_t
+*/
+csi_error_t csi_des_cbc_encrypt(csi_des_t *des, void *in, void *out, uint32_t size, void *iv) ;
+
+/**
+  \brief       DES cbc decrypt
+  \param[in]   des     Handle to operate
+  \param[in]   in      Pointer to the source data
+  \param[out]  out     Pointer to the result data
+  \param[in]   size    The source data size
+  \param[in]   iv      Init vector
+  \return      Error code \ref Csi_error_t
+*/
+csi_error_t csi_des_cbc_decrypt(csi_des_t *des, void *in, void *out, uint32_t size, void *iv);
+
+/**
+  \brief       TDES ecb encrypt
+  \param[in]   des     Handle to operate
+  \param[in]   in      Pointer to the source data
+  \param[out]  out     Pointer to the result data
+  \param[in]   size    The source data size
+  \return      Error code \ref Csi_error_t
+*/
+csi_error_t csi_tdes_ecb_encrypt(csi_des_t *des, void *in, void *out, uint32_t size);
+
+/**
+  \brief       TDES ecb decrypt
+  \param[in]   des     Handle to operate
+  \param[in]   in      Pointer to the source data
+  \param[out]  out     Pointer to the result data
+  \param[in]   size    The source data size
+  \return      Error code \ref Csi_error_t
+*/
+csi_error_t csi_tdes_ecb_decrypt(csi_des_t *des, void *in, void *out, uint32_t size);
+
+/**
+  \brief       TDES cbc encrypt
+  \param[in]   des     Handle to operate
+  \param[in]   in      Pointer to the source data
+  \param[out]  out     Pointer to the result data
+  \param[in]   size    The source data size
+  \param[in]   iv      Init vector
+  \return      Error code \ref Csi_error_t
+*/
+csi_error_t csi_tdes_cbc_encrypt(csi_des_t *des, void *in, void *out, uint32_t size, void *iv) ;
+
+/**
+  \brief       TDES cbc decrypt
+  \param[in]   des     Handle to operate
+  \param[in]   in      Pointer to the source data
+  \param[out]  out     Pointer to the result data
+  \param[in]   size    The source data size
+  \param[in]   iv      Init vector
+  \return      Error code \ref Csi_error_t
+*/
+csi_error_t csi_tdes_cbc_decrypt(csi_des_t *des, void *in, void *out, uint32_t size, void *iv);
+
+/**
+  \brief       Config DES mode dma or slave
+  \param[in]   mode    \ref csi_des_trans_mode_t 
+  \return      None
+*/
+void csi_des_trans_config(csi_des_t *des, csi_des_trans_mode_t mode);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _DRV_AES_H_ */

lib/sec_library/include/dev_tag.h

@@ -0,0 +1,87 @@
+/*
+ * Copyright (C) 2017-2020 Alibaba Group Holding Limited
+ */
+
+/******************************************************************************
+ * @file     drv/dev_tag.h
+ * @brief    Header File for DEV TAG Driver
+ * @version  V1.0
+ * @date     31. March 2020
+ * @model    common
+ ******************************************************************************/
+
+#ifndef _DRV_DEV_TAG_H_
+#define _DRV_DEV_TAG_H_
+
+#include <stdint.h>
+#include <stdio.h>
+#include <string.h>
+#include <stdbool.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+    DEV_BLANK_TAG = 0U,
+    DEV_DW_UART_TAG,
+    DEV_DW_DMA_TAG,
+    DEV_DW_GPIO_TAG,
+    DEV_DW_IIC_TAG,
+    DEV_DW_QSPI_TAG,
+    DEV_DW_SDMMC_TAG,
+    DEV_DW_SDHCI_TAG,
+    DEV_DW_SPI_TAG,
+    DEV_DW_TIMER_TAG,
+    DEV_DW_WDT_TAG,
+    DEV_WJ_ADC_TAG,
+    DEV_WJ_AES_TAG,
+    DEV_WJ_CODEC_TAG,
+    DEV_WJ_CRC_TAG,
+    DEV_WJ_DMA_TAG,
+    DEV_WJ_EFLASH_TAG,
+    DEV_WJ_EFUSE_TAG,
+    DEV_WJ_ETB_TAG,
+    DEV_WJ_FFT_TAG,
+    DEV_WJ_I2S_TAG,
+    DEV_WJ_MBOX_TAG,
+    DEV_WJ_PADREG_TAG,
+    DEV_WJ_PDM_TAG,
+    DEV_WJ_PINMUX_TAG,
+    DEV_WJ_PMU_TAG,
+    DEV_WJ_PWM_TAG,
+    DEV_WJ_PWMR_TAG,
+    DEV_WJ_RNG_TAG,
+    DEV_WJ_ROM_TAG,
+    DEV_WJ_RSA_TAG,
+    DEV_WJ_RTC_TAG,
+    DEV_WJ_SASC_TAG,
+    DEV_WJ_SHA_TAG,
+    DEV_WJ_SPDIF_TAG,
+    DEV_WJ_SPIDF_TAG,
+    DEV_WJ_TDM_TAG,
+    DEV_WJ_TIPC_TAG,
+    DEV_WJ_USB_TAG,
+    DEV_WJ_USI_TAG,
+    DEV_WJ_VAD_TAG,
+    DEV_CD_QSPI_TAG,
+    DEV_DCD_ISO7816_TAG,
+    DEV_OSR_RNG_TAG,
+    DEV_QX_RTC_TAG,
+    DEV_RCHBAND_CODEC_TAG,
+    DEV_CMSDK_UART_TAG,
+    DEV_RAMBUS_150B_PKA_TAG,
+    DEV_RAMBUS_150B_TRNG_TAG,
+    DEV_RAMBUS_120SI_TAG,
+    DEV_RAMBUS_120SII_TAG,
+    DEV_RAMBUS_120SIII_TAG,
+	DEV_WJ_AVFS_TAG,
+    DEV_WJ_BMU_TAG,
+} csi_dev_tag_t;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _DRV_TAG_H_ */
+

lib/sec_library/include/device_types.h

@@ -0,0 +1,73 @@
+/*
+ * Copyright (C) 2017-2020 Alibaba Group Holding Limited
+ */
+/* device_types.h
+ *
+ * Driver Framework, Device API, Type Definitions
+ *
+ * The document "Driver Framework Porting Guide" contains the detailed
+ * specification of this API. The information contained in this header file
+ * is for reference only.
+ */
+
+
+
+#ifndef INCLUDE_GUARD_DEVICE_TYPES_H
+#define INCLUDE_GUARD_DEVICE_TYPES_H
+
+/*----------------------------------------------------------------------------
+ * Device_Handle_t
+ *
+ * This handle represents a device, typically one hardware block instance.
+ *
+ * The Device API can access the static device resources (registers and RAM
+ * inside the device) using offsets inside the device. This abstracts memory
+ * map knowledge and simplifies device instantiation.
+ *
+ * Each device has its own configuration, including the endianness swapping
+ * need for the words transferred. Endianness swapping can thus be performed
+ * on the fly and transparent to the caller.
+ *
+ * The details of the handle are implementation specific and must not be
+ * relied on, with one exception: NULL is guaranteed to be a non-existing
+ * handle.
+ */
+
+
+
+typedef void * Device_Handle_t;
+
+
+/*----------------------------------------------------------------------------
+ * Device_Reference_t
+ *
+ * This is an implementation-specific reference for the device. It can
+ * be passed from the implementation of the Device API to other modules
+ * for use, for example, with OS services that require such a reference.
+ *
+ * The details of the handle are implementation specific and must not be
+ * relied on, with one exception: NULL is guaranteed to be a non-existing
+ * handle.
+ */
+typedef void * Device_Reference_t;
+
+
+/*----------------------------------------------------------------------------
+ * Device_Data_t
+ *
+ * This is an implementation-specific reference for the device. It can
+ * be passed from the implementation of the Device API to other modules
+ * for use, for example, with OS services that require such a reference.
+ */
+typedef struct
+{
+    // Physical address of the device mapped in memory
+    void * PhysAddr;
+
+} Device_Data_t;
+
+
+#endif /* Include Guard */
+
+
+/* end of file device_types.h */

lib/sec_library/include/ecc.h

@@ -0,0 +1,306 @@
+/*
+ * Copyright (C) 2017-2022 Alibaba Group Holding Limited
+ */
+
+/******************************************************************************
+ * @file       drv/ecc.h
+ * @brief      Header File for ECC Driver
+ * @version    V3.3
+ * @date       30. May 2022
+ * @model      ECC
+ ******************************************************************************/
+
+#ifndef _DRV_ECC_H_
+#define _DRV_ECC_H_
+
+#include <stdint.h>
+#include "common.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define CSI_ECC_PUBKEY_LEN      (65-1)
+#define CSI_ECC_PRIVKEY_LEN     (32)
+#define CSI_ECC_PUBKEYTMP_LEN   (65)
+#define CSI_ECC_RK_LEN          (24) //random
+#define CSI_ECC_SIGNATURE_LEN   (64)
+#define CSI_ECC_DIGEST_LEN      (32)
+
+#define ECC_PRIME_CURVE_G_BYTES (64)
+#define ECC_PRIME_CURVE_P_BYTES (70)
+
+typedef struct {
+    uint32_t ecc_curve : 1; ///< supports 256bits curve
+} ecc_capabilities_t;
+
+/**
+\brief ECC ciphertext order
+*/
+typedef enum {
+    ECC_C1C3C2 = 0,
+    ECC_C1C2C3,
+} ecc_cipher_order_e;
+
+/**
+\brief ECC endian mode
+*/
+typedef enum {
+    ECC_ENDIAN_LITTLE = 0, ///< Little Endian
+    ECC_ENDIAN_BIG         ///< Big Endian
+} ecc_endian_mode_e;
+
+/**
+\brief ECC prime curve type
+*/
+typedef enum {
+    ECC_PRIME256V1 = 0,
+} ecc_prime_curve_type;
+
+/**
+\brief ECC key exchange role
+*/
+typedef enum { ECC_Role_Sponsor = 0, ECC_Role_Responsor } ecc_exchange_role_e;
+
+/****** ECC Event *****/
+typedef enum {
+    ECC_EVENT_MAKE_KEY_COMPLETE = 0, ///< Make key completed
+    ECC_EVENT_ENCRYPT_COMPLETE,      ///< Encrypt completed
+    ECC_EVENT_DECRYPT_COMPLETE,      ///< Decrypt completed
+    ECC_EVENT_SIGN_COMPLETE,         ///< Sign completed
+    ECC_EVENT_VERIFY_COMPLETE,       ///< Verify completed
+    ECC_EVENT_EXCHANGE_KEY_COMPLETE, ///< Exchange key completed
+} ecc_event_e;
+
+/**
+\brief ECC prime curve param
+*/
+typedef struct {
+    ecc_prime_curve_type type;
+    uint32_t *p;
+} csi_ecc_prime_curve_t;
+
+/**
+\brief ECC curve type g param
+*/
+typedef struct {
+    ecc_prime_curve_type type;
+    uint8_t *G;
+    uint8_t *n;
+} csi_ecc_curve_g_t;
+
+/**
+\brief ECC status
+*/
+typedef struct {
+    uint32_t busy : 1; ///< Calculate busy flag
+} csi_ecc_state_t;
+
+/**
+\brief ECC handle
+*/
+typedef struct {
+    csi_dev_t       dev;
+    void *          cb;
+    void *          arg;
+    csi_ecc_state_t state;
+    ecc_prime_curve_type  type;
+} csi_ecc_t;
+
+///< Pointer to \ref csi_ecc_callback_t : ECC Event call back.
+typedef void (*csi_ecc_callback_t)(ecc_event_e event);
+
+/**
+  \brief       Initialize ECC.
+  \param[in]   idx  device id
+  \return      Error code \ref csi_error_t
+*/
+csi_error_t csi_ecc_init(csi_ecc_t *ecc, uint32_t idx);
+
+/**
+  \brief       De-initialize ECC Interface. stops operation and releases the software resources used by the interface
+  \param[in]   ecc  ecc handle to operate.
+  \return      none
+*/
+void csi_ecc_uninit(csi_ecc_t *ecc);
+
+/**
+  \brief       ecc get capability.
+  \param[in]   ecc  Operate handle.
+  \return      Error code \ref csi_error_t
+*/
+csi_error_t csi_ecc_config(csi_ecc_t *ecc, ecc_cipher_order_e co, ecc_endian_mode_e endian);
+
+/**
+  \brief       Attach the callback handler to ECC
+  \param[in]   ecc  Operate handle.
+  \param[in]   cb    Callback function
+  \param[in]   arg   User can define it by himself as callback's param
+  \return      Error code Error code \ref csi_error_t
+*/
+csi_error_t csi_ecc_attach_callback(csi_ecc_t *ecc, csi_ecc_callback_t cb, void *arg);
+
+/**
+  \brief       Detach the callback handler
+  \param[in]   ecc  Operate handle.
+  \return      Error code Error code \ref csi_error_t
+*/
+csi_error_t csi_ecc_detach_callback(csi_ecc_t *ecc);
+
+/**
+  \brief       ecc get capability.
+  \param[in]   ecc  Operate handle.
+  \param[out]  cap  Pointer of ecc_capabilities_t.
+  \return      Error code Error code \ref csi_error_t
+*/
+csi_error_t csi_ecc_get_capabilities(csi_ecc_t *ecc, ecc_capabilities_t *cap);
+
+/**
+  \brief       check whether the public key and private key are a pair.
+  \param[in]   ecc       ecc handle to operate.
+  \param[in]   private   Pointer to the ecc private key, alloc by caller.
+  \param[in]   public    Pointer to the ecc public key, alloc by caller.
+  \return      Error code \ref csi_error_t
+*/
+csi_error_t csi_ecc_check_keypair(csi_ecc_t *ecc, uint8_t pubkey[65], uint8_t prikey[32]);
+
+/**
+  \brief       generate ecc key.
+  \param[in]   ecc       ecc handle to operate.
+  \param[out]  private   Pointer to the ecc private key, alloc by caller.
+  \param[out]  public    Pointer to the ecc public key, alloc by caller.
+  \return      Error code \ref csi_error_t
+*/
+csi_error_t csi_ecc_gen_key(csi_ecc_t *ecc, uint8_t pubkey[65], uint8_t prikey[32]);
+
+/**
+  \brief       generate ecc public key by private key.
+  \param[in]   ecc       ecc handle to operate.
+  \param[out]  private   Pointer to the ecc private key, alloc by caller.
+  \param[out]  public    Pointer to the ecc public key, alloc by caller.
+  \return      Error code \ref csi_error_t
+*/
+csi_error_t csi_ecc_gen_pubkey(csi_ecc_t *ecc, uint8_t pubkey[65], uint8_t prikey[32]);
+
+/**
+  \brief       ecc sign
+  \param[in]   ecc      ecc handle to operate.
+  \param[in]   d        Pointer to the digest.
+  \param[out]  privkey  Pointer to the private key
+  \param[out]  s        Pointer to the signature
+  \return      Error code \ref csi_error_t
+*/
+csi_error_t csi_ecc_sign(csi_ecc_t *ecc, uint8_t d[32], uint8_t prikey[32], uint8_t s[64]);
+
+/**
+  \brief       ecc sign asybnc
+  \param[in]   ecc      ecc handle to operate.
+  \param[in]   d        Pointer to the digest.
+  \param[out]  privkey  Pointer to the private key
+  \param[out]  s        Pointer to the signature
+  \return      Error code \ref csi_error_t
+*/
+csi_error_t csi_ecc_sign_async(csi_ecc_t *ecc, uint8_t d[32], uint8_t prikey[32], uint8_t s[64]);
+
+/* TODO */
+/**
+  \brief       ecc verify
+  \param[in]   ecc      ecc handle to operate.
+  \param[in]   d        Pointer to the digest.
+  \param[out]  privkey  Pointer to the private key
+  \param[out]  s        Pointer to the signature
+  \return      verify result 
+*/
+bool csi_ecc_verify(csi_ecc_t *ecc, uint8_t d[32], uint8_t pubkey[65], uint8_t s[64]);
+
+/**
+  \brief       ecc verify
+  \param[in]   ecc      ecc handle to operate.
+  \param[in]   d        Pointer to the digest.
+  \param[out]  privkey  Pointer to the private key
+  \param[out]  s        Pointer to the signature
+  \return      verify result
+*/
+bool csi_ecc_verify_async(csi_ecc_t *ecc, uint8_t d[32], uint8_t pubkey[65], uint8_t s[64]);
+
+/**
+  \brief       ecc encrypto
+  \param[in]   ecc              ecc handle to operate.
+  \param[in]   Plain            Pointer to the plaintext.
+  \param[in]   PlainByteLen     plaintext len
+  \param[in]   pubKey           public key.
+  \param[out]  Cipher           Pointer to the chipher
+  \param[out]  CipherByteLen    Pointer to the chipher len.
+  \return      Error code \ref csi_error_t
+*/
+csi_error_t csi_ecc_encrypt(csi_ecc_t *ecc, uint8_t *Plain,
+                            uint32_t PlainByteLen, uint8_t pubKey[65],
+                            uint8_t *Cipher, uint32_t *CipherByteLen);
+
+/**
+  \brief       ecc encrypto
+  \param[in]   ecc              ecc handle to operate.
+  \param[in]   Cipher           Pointer to the chipher
+  \param[in]   CipherByteLen    chipher len.
+  \param[in]   prikey           private key.
+  \param[out]  Plain            Pointer to the plaintext.
+  \param[out]  PlainByteLen     plaintext len
+  \return      Error code \ref csi_error_t
+*/
+csi_error_t csi_ecc_decrypt(csi_ecc_t *ecc, uint8_t *Cipher,
+                            uint32_t CipherByteLen, uint8_t prikey[32],
+                            uint8_t *Plain, uint32_t *PlainByteLen);
+
+/**
+  \brief       ecc key exchange
+  \param[in]   ecc       ecc handle to operate.
+  \return      Error code \ref csi_error_t
+*/
+csi_error_t csi_ecc_exchangekey(csi_ecc_t *ecc, ecc_exchange_role_e role,
+                                uint8_t *dA, uint8_t *PB, uint8_t *rA,
+                                uint8_t *RA, uint8_t *RB, uint8_t *ZA,
+                                uint8_t *ZB, uint32_t kByteLen, uint8_t *KA,
+                                uint8_t *S1, uint8_t *SA);
+
+/**
+  \brief       ecc key exchange get Z.
+  \param[in]   ecc       ecc handle to operate.
+  \return      Error code Error code \ref csi_error_t
+*/
+csi_error_t csi_ecc_getZ(csi_ecc_t *ecc, uint8_t *ID, uint32_t byteLenofID,
+                         uint8_t pubKey[65], uint8_t Z[32]);
+
+/**
+  \brief       ecc key exchange get E
+  \param[in]   ecc       ecc handle to operate.
+  \return      Error code Error code \ref csi_error_t
+*/
+csi_error_t csi_ecc_getE(csi_ecc_t *ecc, uint8_t *M, uint32_t byteLen,
+                         uint8_t Z[32], uint8_t E[32]);
+
+/**
+  \brief       Get ECC state.
+  \param[in]   ecc      ECC handle to operate.
+  \param[out]  state    ECC state \ref csi_ecc_state_t.
+  \return      Error code Error code \ref csi_error_t
+*/
+csi_error_t csi_ecc_get_state(csi_ecc_t *ecc, csi_ecc_state_t *state);
+
+/**
+  \brief       Enable ecc power manage
+  \param[in]   ecc  ECC handle to operate.
+  \return      Error code Error code \ref csi_error_t
+*/
+csi_error_t csi_ecc_enable_pm(csi_ecc_t *ecc);
+
+/**
+  \brief       Disable ecc power manage
+  \param[in]   ecc  ECC handle to operate.
+*/
+void csi_ecc_disable_pm(csi_ecc_t *ecc);
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#endif

lib/sec_library/include/ecdh.h

@@ -0,0 +1,43 @@
+/*
+ * Copyright (C) 2017-2022 Alibaba Group Holding Limited
+ */
+
+/******************************************************************************
+ * @file       drv/ecdh.h
+ * @brief      Header File for ECDH Driver
+ * @version    V3.3
+ * @date       10.June 2022
+ * @model      ECC
+ ******************************************************************************/
+
+#ifndef _DRV_ECDH_H_
+#define _DRV_ECDH_H_
+
+#include <stdint.h>
+#include "common.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define CSI_ECDH_PUBKEY_LEN   (65-1)
+#define CSI_ECDH_PRIVKEY_LEN  (32)
+#define CSI_ECDH_SHARE_LEN    (64)
+#define CSI_ECDH_SHAREKEY_LEN (32)
+
+/**
+  \brief       ecdh cacl share secret
+  \param[in]  ecc       ecc handle to operate.
+  \param[in]  pubkey    Pointer to the A public key.
+  \param[in]  prikey    Pointer to the B private key.
+  \param[out] shareKey  Pointer to the share secret.
+  \param[out] len       length of the share secret.
+  \return     Error code \ref csi_error_t
+*/
+csi_error_t csi_ecdh_calc_secret(csi_ecc_t *ecc, uint8_t privkey[32], uint8_t pubkey[65], uint8_t shareKey[32], uint32_t *len);
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#endif

lib/sec_library/include/kdf.h

@@ -1,12 +1,19 @@
 /*
- * Copyright (C) 2019-2021 Alibaba Group Holding Limited
+ * Copyright (C) 2019-2020 Alibaba Group Holding Limited
  */
 
 #ifndef __KDF_H__
 #define __KDF_H__
+#ifdef SEC_LIB_VERSION
 #include "drv/aes.h"
 #include "drv/sm4.h"
 #include "drv/common.h"
+#else
+#include "aes.h"
+#include "sm4.h"
+#include "common.h"
+#endif
+
 #include <stdint.h>
 
 typedef enum {
@@ -50,6 +57,9 @@ typedef enum {
         KDF_KEY_TYPE_TDES_192,
         KDF_KEY_TYPE_TDES_128,
         KDF_KEY_TYPE_DES,
+	/* for rpmb, str */
+/* 	KDF_KEY_TYPE_HMAC_SHA256,
+ */
         KDF_KEY_TYPE_MAX,
 } csi_kdf_key_type_t;
 
@@ -113,12 +123,12 @@ csi_error_t csi_kdf_destory_key(csi_kdf_t *kdf, csi_kdf_derived_key_t dkey);
 
 /**
   \brief       Set key to algorithim engine.
-  \param[in]   handle    Handle to cipher.
   \param[in]   kdf    Handle to operate.
+  \param[in]   handle    Handle to cipher.
   \param[in]   dkey derived key type.
   \return      error code
 */
-csi_error_t csi_kdf_set_key(csi_kdf_key_handle_t *handle, csi_kdf_t *kdf,
+csi_error_t csi_kdf_set_key(csi_kdf_t *kdf, csi_kdf_key_handle_t *handle,
                             csi_kdf_derived_key_t dkey);
 
 /**
@@ -139,4 +149,11 @@ csi_error_t csi_kdf_clear_key(csi_kdf_t *kdf, csi_kdf_derived_key_t dkey);
 csi_error_t csi_kdf_get_key_attr(csi_kdf_t *kdf, csi_kdf_derived_key_t dkey,
                                  csi_kdf_key_attr_t *attr);
 
+
+/**
+  \brief       kdf generate hmac key.
+  \param[in]   kdf    Handle to operate
+*/
+csi_error_t csi_kdf_gen_hmac_key(uint8_t* key,uint32_t * length);
+
 #endif

lib/sec_library/include/keyram.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2017-2021 Alibaba Group Holding Limited
+ * Copyright (C) 2017-2020 Alibaba Group Holding Limited
  */
 
 /******************************************************************************
@@ -9,7 +9,7 @@
  * @date     12. MAR 2021
  ******************************************************************************/
 
-#include "drv/kdf.h"
+#include "kdf.h"
 #include <stdio.h>
 #include <string.h>
 
@@ -45,7 +45,7 @@
  *
  * @return uint32_t
  */
-uint32_t keyram_init();
+uint32_t keyram_init(void);
 
 /**
  * @brief keyram set key.
@@ -70,9 +70,9 @@ uint32_t keyram_get_key_addr(csi_kdf_derived_key_t key, uint64_t *addr);
  *
  * @return uint32_t
  */
-uint32_t keyram_clear();
+uint32_t keyram_clear(void);
 
 /**
  * @brief Uninit. This function will lock KDF.
  */
-void keyram_uninit();
+void keyram_uninit(void);

lib/sec_library/include/list.h

@@ -0,0 +1,367 @@
+/*
+ * Copyright (C) 2015-2020 Alibaba Group Holding Limited
+ */
+
+/******************************************************************************
+ * @file       drv/list.h
+ * @brief      Header File for LIST Driver
+ * @version    V1.0
+ * @date       10. Oct 2020
+ * @model      list
+ ******************************************************************************/
+
+#ifndef AOS_LIST_H
+#define AOS_LIST_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ \brief       Get offset of a member variable
+ \param[in]   type      The type of the struct this is embedded in
+ \param[in]   member    The name of the variable within the struct
+ \return      None
+*/
+#define aos_offsetof(type, member)   ((size_t)&(((type *)0)->member))
+
+/**
+ \brief       Get the struct for this entry
+ \param[in]   ptr       The list head to take the element from
+ \param[in]   type      The type of the struct this is embedded in
+ \param[in]   member    The name of the variable within the struct
+ \return      None
+*/
+#define aos_container_of(ptr, type, member) \
+    ((type *) ((char *) (ptr) - aos_offsetof(type, member)))
+
+/* For double link list */
+typedef struct dlist_s {
+    struct dlist_s *prev;
+    struct dlist_s *next;
+} dlist_t;
+
+static inline void __dlist_add(dlist_t *node, dlist_t *prev, dlist_t *next)
+{
+    node->next = next;
+    node->prev = prev;
+
+    prev->next = node;
+    next->prev = node;
+}
+
+/**
+ \brief       Get the struct for this entry
+ \param[in]   addr      The list head to take the element from
+ \param[in]   type      The type of the struct this is embedded in
+ \param[in]   member    The name of the dlist_t within the struct
+ \return      None
+*/
+#define dlist_entry(addr, type, member) \
+    ((type *)((long)addr - aos_offsetof(type, member)))
+
+
+static inline void dlist_add(dlist_t *node, dlist_t *queue)
+{
+    __dlist_add(node, queue, queue->next);
+}
+
+static inline void dlist_add_tail(dlist_t *node, dlist_t *queue)
+{
+    __dlist_add(node, queue->prev, queue);
+}
+
+static inline void dlist_del(dlist_t *node)
+{
+    dlist_t *prev = node->prev;
+    dlist_t *next = node->next;
+
+    prev->next = next;
+    next->prev = prev;
+}
+
+static inline void dlist_init(dlist_t *node)
+{
+    node->next = (node->prev = node);
+}
+
+static inline void INIT_AOS_DLIST_HEAD(dlist_t *list)
+{
+    list->next = list;
+    list->prev = list;
+}
+
+static inline int dlist_empty(const dlist_t *head)
+{
+    return head->next == head;
+}
+
+/**
+ \brief       Initialise the list
+ \param[in]   list    The list to be inited
+ \return      None
+*/
+#define AOS_DLIST_INIT(list)  {&(list), &(list)}
+
+/**
+ \brief       Get the first element from a list
+ \param[in]   ptr       The list head to take the element from
+ \param[in]   type      The type of the struct this is embedded in
+ \param[in]   member    The name of the dlist_t within the struct
+ \return      None
+*/
+#define dlist_first_entry(ptr, type, member) \
+    dlist_entry((ptr)->next, type, member)
+
+/**
+ \brief       Iterate over a list
+ \param[in]   pos     The &struct dlist_t to use as a loop cursor
+ \param[in]   head    The head for your list
+ \return      None
+*/
+#define dlist_for_each(pos, head) \
+    for (pos = (head)->next; pos != (head); pos = pos->next)
+
+/**
+ \brief       Iterate over a list safe against removal of list entry
+ \param[in]   pos     The &struct dlist_t to use as a loop cursor
+ \param[in]   n       Another &struct dlist_t to use as temporary storage
+ \param[in]   head    The head for your list
+ \return      None
+*/
+#define dlist_for_each_safe(pos, n, head) \
+    for (pos = (head)->next, n = pos->next; pos != (head); \
+         pos = n, n = pos->next)
+
+/**
+ \brief       Iterate over list of given type
+ \param[in]   queue     The head for your list
+ \param[in]   node      The &struct dlist_t to use as a loop cursor
+ \param[in]   type      The type of the struct this is embedded in
+ \param[in]   member    The name of the dlist_t within the struct
+ \return      None
+*/
+#define dlist_for_each_entry(queue, node, type, member) \
+    for (node = aos_container_of((queue)->next, type, member); \
+         &node->member != (queue); \
+         node = aos_container_of(node->member.next, type, member))
+
+/**
+ \brief       Iterate over list of given type safe against removal of list entry
+ \param[in]   queue     The head for your list
+ \param[in]   n         The type * to use as a temp
+ \param[in]   node      The type * to use as a loop cursor
+ \param[in]   type      The type of the struct this is embedded in
+ \param[in]   member    The name of the dlist_t within the struct
+ \return      None
+*/
+#define dlist_for_each_entry_safe(queue, n, node, type, member) \
+    for (node = aos_container_of((queue)->next, type, member),  \
+         n = (queue)->next ? (queue)->next->next : NULL;        \
+         &node->member != (queue);                              \
+         node = aos_container_of(n, type, member), n = n ? n->next : NULL)
+
+/**
+ \brief       Get the struct for this entry
+ \param[in]   ptr       The list head to take the element from
+ \param[in]   type      The type of the struct this is embedded in
+ \param[in]   member    The name of the variable within the struct
+ \return      None
+ */
+#define list_entry(ptr, type, member) \
+    aos_container_of(ptr, type, member)
+
+
+/**
+ \brief       Iterate backwards over list of given type
+ \param[in]   pos       The type * to use as a loop cursor
+ \param[in]   head      The head for your list
+ \param[in]   member    The name of the dlist_t within the struct
+ \param[in]   type      The type of the struct this is embedded in
+ \return      None
+*/
+#define dlist_for_each_entry_reverse(pos, head, member, type) \
+    for (pos = list_entry((head)->prev, type, member);        \
+         &pos->member != (head);                              \
+         pos = list_entry(pos->member.prev, type, member))
+
+/**
+ \brief       Get the list length
+ \param[in]   queue     The head for your list
+ \return      None
+*/
+int dlist_entry_number(dlist_t *queue);
+
+/**
+ \brief       Initialise the list
+ \param[in]   name    The list to be initialized
+ \return      None
+*/
+#define AOS_DLIST_HEAD_INIT(name) { &(name), &(name) }
+
+/**
+ \brief       Initialise the list
+ \param[in]   name    The list to be initialized
+ \return      None
+*/
+#define AOS_DLIST_HEAD(name) \
+    dlist_t name = AOS_DLIST_HEAD_INIT(name)
+
+/* For single link list */
+typedef struct slist_s {
+    struct slist_s *next;
+} slist_t;
+
+static inline void slist_add(slist_t *node, slist_t *head)
+{
+    node->next = head->next;
+    head->next = node;
+}
+
+void slist_add_tail(slist_t *node, slist_t *head);
+
+static inline void slist_del(slist_t *node, slist_t *head)
+{
+    while (head->next) {
+        if (head->next == node) {
+            head->next = node->next;
+            break;
+        }
+
+        head = head->next;
+    }
+}
+
+static inline int slist_empty(const slist_t *head)
+{
+    return !head->next;
+}
+
+static inline void slist_init(slist_t *head)
+{
+    head->next = 0;
+}
+
+static inline slist_t *slist_remove(slist_t *l, slist_t *n)
+{
+    /* Remove slist head */
+    struct slist_s *node = l;
+
+    while (node->next && (node->next != n)) {
+        node = node->next;
+    }
+
+    /* Remove node */
+    if (node->next != (slist_t *)0) {
+        node->next = node->next->next;
+    }
+
+    return l;
+}
+
+static inline slist_t *slist_first(slist_t *l)
+{
+    return l->next;
+}
+
+static inline slist_t *slist_tail(slist_t *l)
+{
+    while (l->next) {
+        l = l->next;
+    }
+
+    return l;
+}
+
+static inline slist_t *slist_next(slist_t *n)
+{
+    return n->next;
+}
+
+/**
+  \brief       Iterate over list of given type
+  \param[in]   node      The type * to use as a loop cursor
+  \param[in]   type      The type of the struct this is embedded in
+  \param[in]   member    The name of the slist_t within the struct
+  \param[in]   queue     The head for your list
+  \return      None
+*/
+#define slist_for_each_entry(queue, node, type, member)        \
+    for (node = aos_container_of((queue)->next, type, member); \
+         &node->member;                                        \
+         node = aos_container_of(node->member.next, type, member))
+
+/**
+ \brief       Iterate over list of given type safe against removal of list entry
+ \param[in]   queue     The head for your list
+ \param[in]   tmp       The type * to use as a temp
+ \param[in]   node      The type * to use as a loop cursor
+ \param[in]   type      The type of the struct this is embedded in
+ \param[in]   member    The name of the slist_t within the struct
+ \return      None
+*/
+#define slist_for_each_entry_safe(queue, tmp, node, type, member) \
+    for (node = aos_container_of((queue)->next, type, member),    \
+         tmp = (queue)->next ? (queue)->next->next : NULL;        \
+         &node->member;                                           \
+         node = aos_container_of(tmp, type, member), tmp = tmp ? tmp->next : tmp)
+
+/**
+ \brief       Initialise the list
+ \param[in]   name    The list to be initialized
+ \return      None
+*/
+#define AOS_SLIST_HEAD_INIT(name) {0}
+
+/**
+ \brief       Initialise the list
+ \param[in]   name    The list to be initialized
+ \return      None
+*/
+#define AOS_SLIST_HEAD(name) \
+    slist_t name = AOS_SLIST_HEAD_INIT(name)
+
+/**
+ \brief       Get the struct for this entry
+ \param[in]   addr      The list head to take the element from
+ \param[in]   type      The type of the struct this is embedded in
+ \param[in]   member    The name of the slist_t within the struct
+ \return      None
+*/
+#define slist_entry(addr, type, member) (                                   \
+        addr ? (type *)((long)addr - aos_offsetof(type, member)) : (type *)addr \
+                                        )
+
+/**
+ \brief       Get the first element from a list
+ \param[in]   ptr       The list head to take the element from
+ \param[in]   type      The type of the struct this is embedded in
+ \param[in]   member    The name of the slist_t within the struct
+ \return      None
+*/
+#define slist_first_entry(ptr, type, member) \
+    slist_entry((ptr)->next, type, member)
+
+/**
+ \brief       Slist_tail_entry - get the tail element from a slist
+ \param[in]   ptr       The slist head to take the element from
+ \param[in]   type      The type of the struct this is embedded in
+ \param[in]   member    The name of the slist_struct within the struct
+ \return      None
+ \note        That slist is expected to be not empty
+*/
+#define slist_tail_entry(ptr, type, member) \
+    slist_entry(slist_tail(ptr), type, member)
+
+/**
+ \brief       Get the list length
+ \param[in]   queue    The head for your list
+ \return      None
+*/
+int slist_entry_number(slist_t *queue);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* AOS_LIST_H */

lib/sec_library/include/rambus.h

@@ -0,0 +1,149 @@
+/*
+ * Copyright (C) 2017-2020 Alibaba Group Holding Limited
+ */
+
+#ifndef INC_RAMBUS_H
+#define INC_RAMBUS_H
+
+#include "device_types.h"
+#ifdef SEC_LIB_VERSION
+#include "drv/common.h"
+#include "device_rw.h"
+#include "rambus_log.h"
+#include "rambus_errcode.h"
+#else
+#include "common.h"
+#endif
+
+extern uint64_t g_freq_timer;
+extern uint64_t g_freq_ip;
+extern uint64_t g_start_ctr;
+extern uint64_t g_end_ctr;
+extern uint64_t g_data_len_in_bits;
+extern uint32_t g_type;
+
+enum rambus_cipher_padding_mode {
+    PADDING_ZERO,
+    PADDING_FF,
+    PADDING_RANDOM,
+};
+
+uint32_t rb_get_random_byte(uint8_t *buf, uint32_t count);
+
+uint32_t rb_get_random_byte_nozero(uint8_t *buf, uint32_t count);
+
+uint32_t kdf_get_mask(uint8_t *mask, uint32_t len);
+
+/* 1 bpc, 2 tps, 3 bps */
+void rb_perf_init(uint32_t data_len_in_bits, uint32_t type);
+void rb_perf_start(void);
+void rb_perf_end(void);
+void rb_perf_get(char *ncase);
+
+#define DEFAULT_TIMEOUT 1000U
+
+#ifdef CONFIG_ALG_PERF_TEST
+#define RB_PERF_INIT(bits, type)                                               \
+        do {                                                                   \
+                if (data_len_in_bits != 0) {                                   \
+                        g_data_len_in_bits = data_len_in_bits;                 \
+                }                                                              \
+                if (type != 0) {                                               \
+                        g_type = type;                                         \
+                }                                                              \
+        } while (0)
+
+#define RB_PERF_START_POINT()                                                  \
+        do {                                                                   \
+                g_start_ctr = ((((uint64_t)csi_coret_get_valueh() << 32U) |    \
+                                csi_coret_get_value()));                       \
+        } while (0)
+
+#define RB_PERF_END_POINT()                                                    \
+        do {                                                                   \
+                g_end_ctr = ((((uint64_t)csi_coret_get_valueh() << 32U) |      \
+                              csi_coret_get_value()));                         \
+        } while (0)
+
+#else
+#define RB_PERF_INIT(...)
+#define RB_PERF_START_POINT(...)
+#define RB_PERF_END_POINT(...)
+#endif
+
+static inline void rb_xor(uint32_t *a, uint32_t *b, uint32_t *c, uint32_t len) {
+        for (int i = 0; i < (int)len; i++) {
+                c[i] = a[i] ^ b[i];
+        }
+}
+
+/**
+ * @brief Get the aes sca enable config
+ *
+ * @param is_en is enable
+ * @return uint32_t
+ */
+uint32_t rb_get_aes_sca(uint32_t *is_en);
+
+/**
+ * @brief Get the sm4 sca enable config
+ *
+ * @param is_en is enable
+ * @return uint32_t
+ */
+uint32_t rb_get_sm4_sca(uint32_t *is_en);
+
+/**
+ * @brief Get the pka sca enable config
+ *
+ * @param is_en is enable
+ * @return uint32_t
+ */
+uint32_t rb_get_pka_sca(uint32_t *is_en);
+
+/**
+ * @brief rb_cache_en
+ * @return uint32_t enable: 1
+ *
+ */
+uint32_t rb_cache_en(void);
+
+/**
+ * @brief trng init
+ *
+ * @return csi_error_t
+ */
+csi_error_t trng_init(void);
+
+/**
+ * @brief rb wait status
+ *
+ * @param dev
+ * @param offset
+ * @param mask
+ * @param status
+ * @return uint32_t
+ */
+csi_error_t rb_wait_status(Device_Handle_t *dev, const uint32_t offset, uint32_t mask,
+                 uint32_t status);
+
+/**
+ * \brief          rambus crypto init.
+ * \return         0 if successful, or error code
+ */
+uint32_t rambus_crypto_init(void);
+
+/**
+ * @brief rambus crypto uninit.
+ *
+ */
+void rambus_crypto_uninit(void);
+
+/**
+ * \brief              rambus set cipher padding type.
+ * @param padding_mode cipher padding mode
+ * \return             0 if successful, or error code
+ */
+uint32_t rambus_enable_cipher_padding_type(enum rambus_cipher_padding_mode padding_mode);
+
+#endif

lib/sec_library/include/rng.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2017-2021 Alibaba Group Holding Limited
+ * Copyright (C) 2017-2020 Alibaba Group Holding Limited
  */
 
 /******************************************************************************
@@ -12,7 +12,7 @@
 #ifndef _DRV_TNG_H_
 #define _DRV_TNG_H_
 
-#include "drv/common.h"
+#include "common.h"
 #include <stdint.h>
 
 #ifdef __cplusplus

lib/sec_library/include/rsa.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2017-2021 Alibaba Group Holding Limited
+ * Copyright (C) 2017-2020 Alibaba Group Holding Limited
  */
 /******************************************************************************
  * @file     drv/rsa.h
@@ -16,7 +16,29 @@ extern "C" {
 #endif
 
 #include <stdint.h>
-#include <drv/common.h>
+#include "common.h"
+
+#define RSA_PRIME_256_BIT_LEN   (128)
+#define RSA_PRIME_512_BIT_LEN   (256)
+#define RSA_PRIME_1024_BIT_LEN  (512)
+#define RSA_PRIME_2048_BIT_LEN  (1024)
+#define RSA_PRIME_4096_BIT_LEN  (2048)
+
+#define RSA_256_BYTE_LEN        (32)
+#define RSA_512_BYTE_LEN        (64)
+#define RSA_1024_BYTE_LEN       (128)
+#define RSA_2048_BYTE_LEN       (256)
+#define RSA_4096_BYTE_LEN       (512)
+#define RSA_EM_BYTE_LEN         RSA_4096_BYTE_LEN
+
+#define SHA256_DIGEST_BYTE_LEN  32
+#define RSA_PKCS1_PADDING_SIZE  11
+#define RSA_MD5_OID_LEN         (6 + 8 + 4)
+#define RSA_SHA1_OID_LEN        (6 + 5 + 4)
+#define RSA_SHA224_OID_LEN      (6 + 9 + 4)
+#define RSA_SHA256_OID_LEN      (6 + 9 + 4)
+#define RSA_SHA384_OID_LEN      (6 + 9 + 4)
+#define RSA_SHA512_OID_LEN      (6 + 9 + 4)
 
 /*----- RSA Control Codes: Mode Parameters: Key Bits -----*/
 typedef enum {
@@ -47,11 +69,17 @@ typedef enum {
     RSA_HASH_TYPE_SHA512
 } csi_rsa_hash_type_t;
 
+typedef struct {
+    csi_rsa_hash_type_t hash_type;
+    uint32_t            oid_len;
+    uint8_t             *oid;
+}RSA_OID;
+
 typedef struct {
     void *n;                                ///< Pointer to the public modulus
     void *e;                                ///< Pointer to the public exponent
     void *d;                                ///< Pointer to the private exponent
-    csi_rsa_key_bits_t  key_bits;           ///< RSA KEY BITS
+    csi_rsa_key_bits_t     key_bits;        ///< RSA KEY BITS
     csi_rsa_padding_type_t padding_type;    ///< RSA PADDING TYPE
 } csi_rsa_context_t;
 
@@ -257,6 +285,30 @@ csi_error_t csi_rsa_enable_pm(csi_rsa_t *rsa);
 */
 void csi_rsa_disable_pm(csi_rsa_t *rsa);
 
+/**
+  \brief       Get publickey by p q prime data
+  \param[in]   rsa          rsa handle to operate.
+  \param[in]   p            Pointer to the prime p
+  \param[in]   p_byte_len   Pointer to the prime p byte length
+  \param[in]   q            Pointer to the prime q
+  \param[in]   q_byte_len   Pointer to the prime q byte length
+  \param[in]   out          Pointer to the publickey
+  \param[in]   keybits_len  Pointer to the publickey bits length
+  \return      \ref csi_error_t
+*/
+csi_error_t csi_rsa_get_publickey(csi_rsa_t *rsa, void *p, uint32_t p_byte_len, void *q, uint32_t q_byte_len, void *out, csi_rsa_key_bits_t keybits_len);
+
+/**
+  \brief       Generation rsa keyparis 
+  \param[in]   rsa          rsa handle to operate.
+  \param[in]   context      Pointer to the rsa context
+  \param[in]   keybits_len  Pointer to the publickey bits length
+  \return      \ref csi_error_t
+*/
+csi_error_t csi_rsa_gen_keypairs(csi_rsa_t *rsa, csi_rsa_context_t *context, csi_rsa_key_bits_t keybits_len);
+
+void csi_rsa_set_ignore_decrypt_error(bool checked);
+
 #ifdef __cplusplus
 }
 #endif

lib/sec_library/include/sec_crypto_aes.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2017-2021 Alibaba Group Holding Limited
+ * Copyright (C) 2017-2020 Alibaba Group Holding Limited
  */
 /******************************************************************************
  * @file     seccrypt_aes.h
@@ -11,11 +11,16 @@
 #ifndef _SC_AES_H_
 #define _SC_AES_H_
 
+#include "sec_include_config.h"
 #include <stdint.h>
-#include <sec_crypto_errcode.h>
+#include "sec_crypto_errcode.h"
 
 #ifdef CONFIG_SYSTEM_SECURE
-#include "drv/aes.h"
+#ifdef SEC_LIB_VERSION
+#include <drv/aes.h>
+#else
+#include "aes.h"
+#endif
 #endif
 
 #ifdef CONFIG_SEC_CRYPTO_AES_SW
@@ -26,6 +31,17 @@
 extern "C" {
 #endif
 
+/**
+\brief AES data transfer mode config
+*/
+typedef enum {
+    SC_AES_SLAVE_MODE = 0U,         ///< slave mode
+    SC_AES_DMA_MODE,                ///< dma mode
+} sc_aes_trans_mode_t;
+
+/**
+\brief AES key-len-bits type
+*/
 typedef enum {
     SC_AES_KEY_LEN_BITS_128 = 0U, ///< 128 Data bits
     SC_AES_KEY_LEN_BITS_192,      ///< 192 Data bits
@@ -187,8 +203,7 @@ uint32_t sc_aes_cfb8_decrypt(sc_aes_t *aes, void *in, void *out, uint32_t size,
   \param[out]  num     the number of the 128-bit block we have used
   \return      error code \ref uint32_t
 */
-uint32_t sc_aes_cfb128_decrypt(sc_aes_t *aes, void *in, void *out, uint32_t size, void *iv,
-                               uint32_t *num);
+uint32_t sc_aes_cfb128_decrypt(sc_aes_t *aes, void *in, void *out, uint32_t size, void *iv);
 
 /**
   \brief       Aes cfb128 encrypt
@@ -200,8 +215,7 @@ uint32_t sc_aes_cfb128_decrypt(sc_aes_t *aes, void *in, void *out, uint32_t size
   \param[out]  num     the number of the 128-bit block we have used
   \return      error code \ref uint32_t
 */
-uint32_t sc_aes_cfb128_encrypt(sc_aes_t *aes, void *in, void *out, uint32_t size, void *iv,
-                               uint32_t *num);
+uint32_t sc_aes_cfb128_encrypt(sc_aes_t *aes, void *in, void *out, uint32_t size, void *iv);
 /**
   \brief       Aes ofb encrypt
   \param[in]   aes     handle to operate
@@ -209,11 +223,11 @@ uint32_t sc_aes_cfb128_encrypt(sc_aes_t *aes, void *in, void *out, uint32_t size
   \param[out]  out     Pointer to the Result data
   \param[in]   size    the Source data size
   \param[in]   iv      init vector
-  \param[out]  num     the number of the 128-bit block we have used
+  \param[in]  key_len key bits
   \return      error code \ref uint32_t
 */
-uint32_t sc_aes_ofb_encrypt(sc_aes_t *aes, void *in, void *out, uint32_t size, void *iv,
-                            uint32_t *num);
+uint32_t sc_aes_ofb_encrypt(sc_aes_t *aes, void *in, void *out, uint32_t size, void *iv);
+
 /**
   \brief       Aes ofb decrypt
   \param[in]   aes     handle to operate
@@ -221,43 +235,86 @@ uint32_t sc_aes_ofb_encrypt(sc_aes_t *aes, void *in, void *out, uint32_t size, v
   \param[out]  out     Pointer to the Result data
   \param[in]   size    the Source data size
   \param[in]   iv      init vector
-  \param[out]  num     the number of the 128-bit block we have used
+  \param[in]  key_len key bits
   \return      error code \ref uint32_t
 */
-uint32_t sc_aes_ofb_decrypt(sc_aes_t *aes, void *in, void *out, uint32_t size, void *iv,
-                            uint32_t *num);
+uint32_t sc_aes_ofb_decrypt(sc_aes_t *aes, void *in, void *out, uint32_t size, void *iv);
+
 /**
   \brief       Aes ctr encrypt
   \param[in]   aes              handle to operate
   \param[in]   in               Pointer to the Source data
   \param[out]  out              Pointer to the Result data
   \param[in]   size             the Source data size
-  \param[in]   nonce_counter    Pointer to the 128-bit nonce and counter
-  \param[in]   stream_block     Pointer to the saved stream-block for resuming
   \param[in]   iv               init vector
-  \param[out]  num              the number of the 128-bit block we have used
   \return      error code \ref uint32_t
 */
-uint32_t sc_aes_ctr_encrypt(sc_aes_t *aes, void *in, void *out, uint32_t size,
-                            uint8_t nonce_counter[16], uint8_t stream_block[16], void *iv,
-                            uint32_t *num);
+uint32_t sc_aes_ctr_encrypt(sc_aes_t *aes, void *in, void *out, uint32_t size,void *iv);
+
 /**
   \brief       Aes ctr decrypt
   \param[in]   aes              handle to operate
   \param[in]   in               Pointer to the Source data
   \param[out]  out              Pointer to the Result data
   \param[in]   size             the Source data size
-  \param[in]   nonce_counter    Pointer to the 128-bit nonce and counter
-  \param[in]   stream_block     Pointer to the saved stream-block for resuming
   \param[in]   iv               init vecotr
-  \param[out]  num              the number of the 128-bit block we have used
   \return      error code \ref uint32_t
 */
-uint32_t sc_aes_ctr_decrypt(sc_aes_t *aes, void *in, void *out, uint32_t size,
-                            uint8_t nonce_counter[16], uint8_t stream_block[16], void *iv,
-                            uint32_t *num);
+uint32_t sc_aes_ctr_decrypt(sc_aes_t *aes, void *in, void *out, uint32_t size,void *iv);
+
+/**
+  \brief       Aes gcm encrypt
+  \param[in]   dev_aes          dev_aes handle to operate
+  \param[in]   in               Pointer to the Source data.
+  \param[out]  out              Pointer to the Result data
+  \param[in]   size             the Source data size
+  \param[in]   iv               init vector
+  \return      error code \ref csi_error_t
+*/
+uint32_t sc_aes_gcm_encrypt(sc_aes_t *aes, void *in, void *out,uint32_t size, uint32_t add_len, void *iv);
+
+/**
+  \brief       Aes gcm decrypt
+  \param[in]   dev_aes          dev_aes handle to operate
+  \param[in]   in               Pointer to the Source data.
+  \param[out]  out              Pointer to the Result data
+  \param[in]   size             the Source data size
+  \param[in]   iv               init vecotr
+  \return      error code \ref csi_error_t
+*/
+uint32_t sc_aes_gcm_decrypt(sc_aes_t *aes, void *in, void *out,uint32_t size, uint32_t add_len, void *iv);
+
+/**
+  \brief       Aes gcm encrypt
+  \param[in]   dev_aes          dev_aes handle to operate
+  \param[in]   in               Pointer to the Source data.
+  \param[out]  out              Pointer to the Result data
+  \param[in]   size             the Source data size
+  \param[in]   iv               init vector
+  \param[in]   tag_out          tag output ,parse null if not needed
+  \return      error code \ref csi_error_t
+*/
+uint32_t sc_aes_ccm_encrypt(sc_aes_t *aes, void *in, void *out,uint32_t size, uint32_t add_len, void *iv, uint8_t* tag_out);
+
+/**
+  \brief       Aes gcm decrypt
+  \param[in]   dev_aes          dev_aes handle to operate
+  \param[in]   in               Pointer to the Source data.
+  \param[out]  out              Pointer to the Result data
+  \param[in]   size             the Source data size
+  \param[in]   iv               init vecotr
+  \param[in]   tag_out tag output,parse null if not needed
+  \return      error code \ref csi_error_t
+*/
+uint32_t sc_aes_ccm_decrypt(sc_aes_t *aes, void *in, void *out,uint32_t size, uint32_t add_len, void *iv, uint8_t* tag_out);
+
+/**
+  \brief       Aes data transfer config
+*/
+void sc_aes_trans_config(sc_aes_t *aes, sc_aes_trans_mode_t mode) ;
 
 #ifdef __cplusplus
 }
 #endif
+
 #endif /* _SC_AES_H_ */

lib/sec_library/include/sec_crypto_common.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2019-2021 Alibaba Group Holding Limited
+ * Copyright (C) 2019-2020 Alibaba Group Holding Limited
  */
 
 

lib/sec_library/include/sec_crypto_des.h

@@ -0,0 +1,205 @@
+/*
+ * Copyright (C) 2017-2022 Alibaba Group Holding Limited
+ */
+/******************************************************************************
+ * @file     sec_crypt0_des.h
+ * @brief    Header File for DES
+ * @version  V1.0
+ * @date     24. Oct 2022
+ * @model    des
+ ******************************************************************************/
+#ifndef _SC_DES_H_
+#define _SC_DES_H_
+
+#include "sec_include_config.h"
+#include <stdint.h>
+#include "sec_crypto_errcode.h"
+
+#ifdef CONFIG_SYSTEM_SECURE
+#ifdef SEC_LIB_VERSION
+#include <drv/des.h>
+#else
+#include "des.h"
+#endif
+#endif
+
+#ifdef CONFIG_SEC_CRYPTO_DES_SW
+#include "crypto_des.h"
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+\brief DES data transfer mode config
+*/
+typedef enum {
+    SC_DES_SLAVE_MODE = 0U,         ///< slave mode
+    SC_DES_DMA_MODE,                ///< dma mode
+} sc_des_trans_mode_t;
+
+/**
+\brief DES key-len-bits type
+*/
+typedef enum {
+    SC_DES_KEY_LEN_BITS_64 = 0U,    ///< 64 Data bits
+    SC_DES_KEY_LEN_BITS_128,        ///< 128 Data bits
+    SC_TDES_KEY_LEN_BITS_192,       ///< 192 Data bits
+} sc_des_key_bits_t;
+
+/**
+\brief DES Ctrl Block
+*/
+typedef struct {
+#ifdef CONFIG_SYSTEM_SECURE
+#ifdef CONFIG_CSI_V1
+    des_handle_t  handle;
+    unsigned char key[32];
+    unsigned int  key_len;
+#endif
+#ifdef CONFIG_CSI_V2
+    csi_des_t     csi_des;
+    //unsigned char sc_ctx[SC_DES_CTX_SIZE];
+#endif
+#endif
+#if defined(CONFIG_TEE_CA)
+    unsigned char key[32];
+    unsigned int  key_len;
+#endif
+#if defined(CONFIG_SEC_CRYPTO_DES_SW)
+    sc_mbedtls_des_context des_ctx;
+#endif
+    //void *ctx;
+} sc_des_t;
+
+// Function documentation
+/**
+  \brief       Initialize DES Interface. Initializes the resources needed for the DES interface
+  \param[in]   des    operate handle
+  \param[in]   idx    device id
+  \return      error code \ref uint32_t
+*/
+uint32_t sc_des_init(sc_des_t *des, uint32_t idx);
+
+/**
+  \brief       De-initialize DES Interface. stops operation and releases the software resources used by the interface
+  \param[in]   des    handle to operate
+  \return      None
+*/
+void sc_des_uninit(sc_des_t *des);
+
+/**
+  \brief       Set encrypt key
+  \param[in]   des        handle to operate
+  \param[in]   key        Pointer to the key buf
+  \param[in]   key_len    Pointer to \ref sc_des_key_bits_t
+  \return      error code \ref uint32_t
+*/
+uint32_t sc_des_set_encrypt_key(sc_des_t *des, void *key, sc_des_key_bits_t key_len);
+
+/**
+  \brief       Set decrypt key
+  \param[in]   des        handle to operate
+  \param[in]   key        Pointer to the key buf
+  \param[in]   key_len    Pointer to \ref sc_des_key_bits_t
+  \return      error code \ref uint32_t
+*/
+uint32_t sc_des_set_decrypt_key(sc_des_t *des, void *key, sc_des_key_bits_t key_len);
+
+/**
+  \brief       Des ecb encrypt
+  \param[in]   des     handle to operate
+  \param[in]   in      Pointer to the Source data
+  \param[out]  out     Pointer to the Result data
+  \param[in]   size    the Source data size
+  \return      error code \ref uint32_t
+*/
+uint32_t sc_des_ecb_encrypt(sc_des_t *des, void *in, void *out, uint32_t size);
+
+/**
+  \brief       Des ecb decrypt
+  \param[in]   des     handle to operate
+  \param[in]   in      Pointer to the Source data
+  \param[out]  out     Pointer to the Result data
+  \param[in]   size    the Source data size
+  \return      error code \ref uint32_t
+*/
+uint32_t sc_des_ecb_decrypt(sc_des_t *des, void *in, void *out, uint32_t size);
+
+/**
+  \brief       Des cbc encrypt
+  \param[in]   des     handle to operate
+  \param[in]   in      Pointer to the Source data
+  \param[out]  out     Pointer to the Result data
+  \param[in]   size    the Source data size
+  \param[in]   iv      init vector
+  \return      error code \ref uint32_t
+*/
+uint32_t sc_des_cbc_encrypt(sc_des_t *des, void *in, void *out, uint32_t size, void *iv);
+
+/**
+  \brief       Des cbc decrypt
+  \param[in]   des     handle to operate
+  \param[in]   in      Pointer to the Source data
+  \param[out]  out     Pointer to the Result data
+  \param[in]   size    the Source data size
+  \param[in]   iv      init vector
+  \return      error code \ref uint32_t
+*/
+uint32_t sc_des_cbc_decrypt(sc_des_t *des, void *in, void *out, uint32_t size, void *iv);
+
+/**
+  \brief       TDes ecb encrypt
+  \param[in]   des     handle to operate
+  \param[in]   in      Pointer to the Source data
+  \param[out]  out     Pointer to the Result data
+  \param[in]   size    the Source data size
+  \return      error code \ref uint32_t
+*/
+uint32_t sc_tdes_ecb_encrypt(sc_des_t *des, void *in, void *out, uint32_t size);
+
+/**
+  \brief       TDes ecb decrypt
+  \param[in]   des     handle to operate
+  \param[in]   in      Pointer to the Source data
+  \param[out]  out     Pointer to the Result data
+  \param[in]   size    the Source data size
+  \return      error code \ref uint32_t
+*/
+uint32_t sc_tdes_ecb_decrypt(sc_des_t *des, void *in, void *out, uint32_t size);
+
+/**
+  \brief       TDes cbc encrypt
+  \param[in]   des     handle to operate
+  \param[in]   in      Pointer to the Source data
+  \param[out]  out     Pointer to the Result data
+  \param[in]   size    the Source data size
+  \param[in]   iv      init vector
+  \return      error code \ref uint32_t
+*/
+uint32_t sc_tdes_cbc_encrypt(sc_des_t *des, void *in, void *out, uint32_t size, void *iv);
+
+/**
+  \brief       TDes cbc decrypt
+  \param[in]   des     handle to operate
+  \param[in]   in      Pointer to the Source data
+  \param[out]  out     Pointer to the Result data
+  \param[in]   size    the Source data size
+  \param[in]   iv      init vector
+  \return      error code \ref uint32_t
+*/
+uint32_t sc_tdes_cbc_decrypt(sc_des_t *des, void *in, void *out, uint32_t size, void *iv);
+
+/**
+  \brief       Config DES mode dma or slave
+  \param[in]   mode    \ref sc_des_trans_mode_t 
+  \return      None
+*/
+void sc_des_trans_config(sc_des_t *des, sc_des_trans_mode_t mode) ;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _SC_DES_H_ */

lib/sec_library/include/sec_crypto_ecc.h

@@ -0,0 +1,265 @@
+/*
+ * Copyright (C) 2017-2022 Alibaba Group Holding Limited
+ */
+/******************************************************************************
+ * @file     sec_crypt_ecc.h
+ * @brief    Header File for ECC
+ * @version  V3.3
+ * @date     30. May 2022
+ * @model    ecc
+ ******************************************************************************/
+#ifndef _SC_ECC_H_
+#define _SC_ECC_H_
+#include "sec_include_config.h"
+
+#define CONFIG_SEC_CRYPTO_ECC
+
+#ifdef CONFIG_SEC_CRYPTO_ECC
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef SEC_LIB_VERSION
+#include "drv/ecc.h"
+#else
+#include "ecc.h"
+#endif
+
+typedef enum {
+    SC_ECC_PRIME256V1 = 0,
+} sc_ecc_curve_type;
+
+/**
+\brief ECC ciphertext order
+*/
+typedef enum {
+        SC_ECC_C1C3C2 = 0,
+        SC_ECC_C1C2C3,
+} sc_ecc_cipher_order_e;
+
+typedef enum {
+        SC_ECC_ENDIAN_LITTLE = 0, ///< Little Endian
+        SC_ECC_ENDIAN_BIG         ///< Big Endian
+} sc_ecc_endian_mode_e;
+
+/**
+\brief ECC key exchange role
+*/
+typedef enum { SC_ECC_Role_Sponsor = 0, SC_ECC_Role_Responsor } sc_ecc_exchange_role_e;
+
+/****** ECC Event *****/
+typedef enum {
+        SC_ECC_EVENT_MAKE_KEY_COMPLETE = 0, ///< Make key completed
+        SC_ECC_EVENT_ENCRYPT_COMPLETE,      ///< Encrypt completed
+        SC_ECC_EVENT_DECRYPT_COMPLETE,      ///< Decrypt completed
+        SC_ECC_EVENT_SIGN_COMPLETE,         ///< Sign completed
+        SC_ECC_EVENT_VERIFY_COMPLETE,       ///< Verify completed
+        SC_ECC_EVENT_EXCHANGE_KEY_COMPLETE, ///< Exchange key completed
+} sc_ecc_event_e;
+
+typedef struct {
+        uint32_t ecc_curve : 1; ///< supports 256bits curve
+} sc_ecc_capabilities_t;
+
+/**
+\brief ECC status
+*/
+typedef struct {
+        uint32_t busy : 1; ///< Calculate busy flag
+} sc_ecc_state_t;
+
+typedef struct {
+#ifdef CONFIG_CSI_V2
+        csi_ecc_t ecc;
+#endif
+} sc_ecc_t;
+
+///< Pointer to \ref sc_ecc_callback_t : ECC Event call back.
+typedef void (*sc_ecc_callback_t)(sc_ecc_event_e event);
+
+/**
+  \brief       Initialize ECC.
+  \param[in]   ecc  ecc handle to operate.
+  \param[in]   idx  device id
+  \return      \ref uint32_t
+*/
+uint32_t sc_ecc_init(sc_ecc_t *ecc, uint32_t idx);
+
+/**
+  \brief       De-initialize ECC Interface. stops operation and releases the
+  software resources used by the interface \param[in]   ecc  ecc handle to
+  operate. \return      none
+*/
+void sc_ecc_uninit(sc_ecc_t *ecc);
+
+/**
+  \brief       ecc get capability.
+  \param[in]   ecc  Operate handle.
+  \return      \ref uint32_t
+*/
+uint32_t sc_ecc_config(sc_ecc_t *ecc, sc_ecc_cipher_order_e co,
+                       sc_ecc_endian_mode_e endian);
+
+/**
+  \brief       Attach the callback handler to ECC
+  \param[in]   ecc  Operate handle.
+  \param[in]   cb    Callback function
+  \param[in]   arg   User can define it by himself as callback's param
+  \return      Error code \ref uint32_t
+*/
+uint32_t sc_ecc_attach_callback(sc_ecc_t *ecc, sc_ecc_callback_t cb, void *arg);
+
+/**
+  \brief       Detach the callback handler
+  \param[in]   ecc  Operate handle.
+*/
+uint32_t sc_ecc_detach_callback(sc_ecc_t *ecc);
+
+/**
+  \brief       ecc get capability.
+  \param[in]   ecc  Operate handle.
+  \param[out]   cap  Pointer of sc_ecc_capabilities_t.
+  \return      \ref uint32_t
+*/
+uint32_t sc_ecc_get_capabilities(sc_ecc_t *ecc, sc_ecc_capabilities_t *cap);
+
+uint32_t sc_ecc_check_keypair(sc_ecc_t *ecc, uint8_t pubkey[65],
+                              uint8_t prikey[32]);
+
+/**
+  \brief       generate ecc key.
+  \param[in]   ecc       ecc handle to operate.
+  \param[out]  private   Pointer to the ecc private key, alloc by caller.
+  \param[out]  public   Pointer to the ecc public key, alloc by caller.
+  \return      \ref uint32_t
+*/
+uint32_t sc_ecc_gen_key(sc_ecc_t *ecc, uint8_t pubkey[65], uint8_t prikey[32]);
+
+
+/**
+  \brief       generate ecc pubkey.
+  \param[in]   ecc      ecc handle to operate.
+  \param[in]   prikey   Pointer to the ecc private key, alloc by caller.
+  \param[out]  pubkey   Pointer to the ecc public key, alloc by caller.
+  \return      \ref uint32_t
+*/
+uint32_t sc_ecc_gen_pubkey(sc_ecc_t *ecc, uint8_t pubkey[65], 
+                    uint8_t prikey[32], sc_ecc_curve_type type);
+
+/**
+  \brief       ecc sign
+  \param[in]   ecc       ecc handle to operate.
+  \param[in]   d       Pointer to the digest.
+  \param[out]  privkey Pointer to the private key
+  \param[out]  s Pointer to the signature
+  \return      \ref uint32_t
+*/
+uint32_t sc_ecc_sign(sc_ecc_t *ecc, uint8_t d[32], uint8_t prikey[32],
+                     uint8_t s[64], sc_ecc_curve_type type);
+
+/**
+  \brief       ecc sign
+  \param[in]   ecc       ecc handle to operate.
+  \param[in]   d       Pointer to the digest.
+  \param[out]  privkey Pointer to the private key
+  \param[out]  s Pointer to the signature
+  \return      \ref uint32_t
+*/
+uint32_t sc_ecc_sign_async(sc_ecc_t *ecc, uint8_t d[32], uint8_t prikey[32],
+                           uint8_t s[64], sc_ecc_curve_type type);
+
+/* TODO */
+/**
+  \brief       ecc verify
+  \param[in]   ecc       ecc handle to operate.
+  \param[in]   d       Pointer to the digest.
+  \param[out]  privkey Pointer to the private key
+  \param[out]  s Pointer to the signature
+  \return      verify result
+*/
+bool sc_ecc_verify(sc_ecc_t *ecc, uint8_t d[32], uint8_t pubkey[65],
+                   uint8_t s[64], sc_ecc_curve_type type);
+
+/**
+  \brief       ecc verify
+  \param[in]   ecc       ecc handle to operate.
+  \param[in]   d       Pointer to the digest.
+  \param[out]  privkey Pointer to the private key
+  \param[out]  s Pointer to the signature
+  \return      verify result
+*/
+bool sc_ecc_verify_async(sc_ecc_t *ecc, uint8_t d[32], uint8_t pubkey[65],
+                         uint8_t s[64], sc_ecc_curve_type type);
+
+/**
+  \brief       ecc encrypto
+  \param[in]   ecc       ecc handle to operate.
+  \param[in]   plain       Pointer to the plaintext.
+  \param[in]  PlainByteLen plaintext len
+  \param[in]  pubKey public key.
+  \param[out]  cipher Pointer to the chipher
+  \param[out]  cipher_byte_len Pointer to the chipher len.
+  \return      uint32_t
+*/
+uint32_t sc_ecc_encrypt(sc_ecc_t *ecc, uint8_t *plain, uint32_t plain_len,
+                        uint8_t pubKey[65], uint8_t *cipher,
+                        uint32_t *cipher_len);
+
+/**
+  \brief       ecc encrypto
+  \param[in]   ecc       ecc handle to operate.
+  \param[in]  cipher Pointer to the chipher
+  \param[in]  CipherByteLen chipher len.
+  \param[in]  prikey private key.
+  \param[out]   plain       Pointer to the plaintext.
+  \param[out]  PlainByteLen plaintext len
+  \return      uint32_t
+*/
+uint32_t sc_ecc_decrypt(sc_ecc_t *ecc, uint8_t *cipher, uint32_t cipher_len,
+                        uint8_t prikey[32], uint8_t *plain,
+                        uint32_t *plain_len);
+
+/**
+  \brief       ecc key exchange
+  \param[in]   ecc       ecc handle to operate.
+  \return      uint32_t
+*/
+uint32_t sc_ecc_exchangekey(sc_ecc_t *ecc, sc_ecc_exchange_role_e role,
+                            uint8_t *da, uint8_t *pb, uint8_t *ra1, uint8_t *ra,
+                            uint8_t *rb, uint8_t *za, uint8_t *zb,
+                            uint32_t k_len, uint8_t *ka, uint8_t *s1,
+                            uint8_t *sa);
+
+/**
+  \brief       ecc key exchange get Z.
+  \param[in]   ecc       ecc handle to operate.
+  \return      uint32_t
+*/
+uint32_t sc_ecc_getZ(sc_ecc_t *ecc, uint8_t *id, uint32_t id_len,
+                     uint8_t pubkey[65], uint8_t z[32]);
+
+/**
+  \brief       ecc key exchange get E
+  \param[in]   ecc       ecc handle to operate.
+  \return      uint32_t
+*/
+uint32_t sc_ecc_getE(sc_ecc_t *ecc, uint8_t *m, uint32_t len, uint8_t z[32],
+                     uint8_t e[32]);
+
+/**
+  \brief       Get ECC state.
+  \param[in]   ecc      ECC handle to operate.
+  \param[out]  state    ECC state \ref sc_ecc_state_t.
+  \return      Error code \ref uint32_t
+*/
+uint32_t sc_ecc_get_state(sc_ecc_t *ecc, sc_ecc_state_t *state);
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#endif
+
+#endif /* _SC_ECC_H_ */
+

lib/sec_library/include/sec_crypto_ecdh.h

@@ -0,0 +1,53 @@
+/*
+ * Copyright (C) 2017-2022 Alibaba Group Holding Limited
+ */
+/******************************************************************************
+ * @file     sec_crypto_ecdh.h
+ * @brief    Header File for curve25519( a state-of-the-art Diffie-Hellman function)
+ * @version  V3.3
+ * @date     10. June 2022
+ * @model    ecdh
+ ******************************************************************************/
+#ifndef _SC_ECDH_H_
+#define _SC_ECDH_H_
+#include "sec_include_config.h"
+
+#define CONFIG_SEC_CRYPTO_ECC
+
+#ifdef CONFIG_SEC_CRYPTO_ECC
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef SEC_LIB_VERSION
+#include "drv/ecdh.h"
+#include "drv/ecc.h"
+#include "sec_crypto_ecc.h"
+#else
+#include "ecdh.h"
+#include "ecc.h"
+#include "sec_crypto_ecc.h"
+#endif
+
+/**
+  \brief       ecdh calc secret
+  \param[in]   ecc ecc handle to operate.
+  \param[in]   pubkey  Pointer to the A(or B) public key.
+  \param[out]  privkey Pointer to the B(or A) private key.
+  \param[out]  out Pointer to the share secret.
+  \param[out]  len length of the share secret.
+  \return      \ref uint32_t.
+*/
+
+uint32_t sc_ecdh_calc_secret(sc_ecc_t *ecc, uint8_t privkey[32],
+                            uint8_t pubkey[65], uint8_t out[32], 
+                            uint32_t *len, sc_ecc_curve_type type) ;
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#endif
+
+#endif /* _SC_CURVE15519_H_ */

lib/sec_library/include/sec_crypto_errcode.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2019-2021 Alibaba Group Holding Limited
+ * Copyright (C) 2019-2020 Alibaba Group Holding Limited
  */
 
 #ifndef _SC_ERRCODE_H
@@ -89,4 +89,4 @@
 #define CHECK_PARAM CHECK_PARAM_RET
 #endif
 
-#endif
+#endif

lib/sec_library/include/sec_crypto_kdf.h

@@ -0,0 +1,96 @@
+/*
+ * Copyright (C) 2019-2020 Alibaba Group Holding Limited
+ */
+
+#ifndef __SC_KDF_H__
+#define __SC_KDF_H__
+#include "sec_crypto_errcode.h"
+#include "sec_crypto_aes.h"
+#include "sec_crypto_sm4.h"
+#include "sec_crypto_mac.h"
+#include <stdint.h>
+
+typedef enum {
+	SC_KDF_DERIVED_DFT_CHALLENGE_EK,
+	SC_KDF_DERIVED_C910TJTAG_CHALLENGE_EK,
+	SC_KDF_DERIVED_E902JTAG_CHALLENGE_EK,
+	SC_KDF_DERIVED_IMAGE_EK,
+	SC_KDF_DERIVED_SECURE_STORAGE_EK1,
+	SC_KDF_DERIVED_SECURE_STORAGE_EK2,
+	SC_KDF_DERIVED_SECURE_STORAGE_EK3,
+	SC_KDF_DERIVED_SECURE_STORAGE_EK4,
+	SC_KDF_DERIVED_SECURE_STORAGE_EK5,
+	SC_KDF_DERIVED_SECURE_STORAGE_EK6,
+	SC_KDF_DERIVED_SECURE_STORAGE_EK7,
+	SC_KDF_DERIVED_SECURE_STORAGE_EK8,
+	SC_KDF_DERIVED_SECURE_STORAGE_EK9,
+	SC_KDF_DERIVED_SECURE_STORAGE_EK10,
+	SC_KDF_DERIVED_SECURE_STORAGE_EK11,
+	SC_KDF_DERIVED_SECURE_STORAGE_EK12,
+	SC_KDF_DERIVED_SECURE_STORAGE_EK13,
+	SC_KDF_DERIVED_SECURE_STORAGE_EK14,
+	SC_KDF_DERIVED_SECURE_STORAGE_EK15,
+	SC_KDF_DERIVED_SECURE_STORAGE_EK16,
+	SC_KDF_DERIVED_RPMB_ACCESS_EK,
+	SC_KDF_DERIVED_MAX,
+} sc_kdf_derived_key_t;
+
+typedef enum {
+	SC_KDF_KEY_TYPE_AES_256,
+	SC_KDF_KEY_TYPE_AES_192,
+	SC_KDF_KEY_TYPE_AES_128,
+	SC_KDF_KEY_TYPE_SM4,
+	SC_KDF_KEY_TYPE_TDES_192,
+	SC_KDF_KEY_TYPE_TDES_128,
+	SC_KDF_KEY_TYPE_DES,
+	/* for rpmb, str */
+/* 	SC_KDF_KEY_TYPE_HMAC_SHA256,
+ */
+	SC_KDF_KEY_TYPE_MAX,
+} sc_kdf_key_type_t;
+
+/**
+\brief KDF Ctrl Block
+*/
+typedef struct {
+	union {
+		sc_aes_t *aes;
+		sc_sm4_t *sm4;
+		sc_mac_t *mac;
+
+	};
+	sc_kdf_key_type_t type;
+} sc_kdf_key_handle_t;
+
+/**
+\brief KDF Ctrl Block
+*/
+typedef struct {
+	void *priv;
+} sc_kdf_t;
+
+/**
+  \brief       kdf initialiez.
+  \param[in]   kdf    Handle to operate.
+  \param[in]   idx    Device id.
+  \return      error code
+*/
+uint32_t sc_kdf_init(sc_kdf_t *kdf, uint32_t idx);
+
+/**
+  \brief       kdf uninitialiez.
+  \param[in]   kdf    Handle to operate
+*/
+void sc_kdf_uninit(sc_kdf_t *kdf);
+
+/**
+  \brief       Set key to algorithim engine.
+  \param[in]   handle    Handle to cipher.
+  \param[in]   kdf    Handle to operate.
+  \param[in]   dkey derived key type.
+  \return      error code
+*/
+uint32_t sc_kdf_set_key(sc_kdf_t *kdf, sc_kdf_key_handle_t *handle,
+			  sc_kdf_derived_key_t dkey);
+
+#endif