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base: t-head:Linux_SDK_V1.2.1
Branches Tags
t-head:th1520 t-head:thead-sdk t-head:huiwei t-head:downclock-sd t-head:develop t-head:master
t-head:20260504 t-head:20251124 t-head:20250930 t-head:20250813 t-head:20250110 t-head:20241223 t-head:Linux_SDK_V2.0.2 t-head:20240720 t-head:20240529 t-head:Linux_SDK_V1.5.4 t-head:20240328 t-head:20240324 t-head:20240131 t-head:20240127 t-head:Linux_SDK_V1.4.2 t-head:Linux_SDK_V1.3.3 t-head:Linux_SDK_V1.2.1 t-head:Linux_SDK_V1.2.0 t-head:Linux_SDK_V1.1.2 t-head:Linux_SDK_V1.0.3 t-head:Linux_SDK_V1.0.2 t-head:Linux_SDK_V0.9.5
..
compare: t-head:Linux_SDK_V2.0.2
Branches Tags
t-head:th1520 t-head:thead-sdk t-head:huiwei t-head:downclock-sd t-head:develop t-head:master
t-head:20260504 t-head:20251124 t-head:20250930 t-head:20250813 t-head:20250110 t-head:20241223 t-head:Linux_SDK_V2.0.2 t-head:20240720 t-head:20240529 t-head:Linux_SDK_V1.5.4 t-head:20240328 t-head:20240324 t-head:20240131 t-head:20240127 t-head:Linux_SDK_V1.4.2 t-head:Linux_SDK_V1.3.3 t-head:Linux_SDK_V1.2.1 t-head:Linux_SDK_V1.2.0 t-head:Linux_SDK_V1.1.2 t-head:Linux_SDK_V1.0.3 t-head:Linux_SDK_V1.0.2 t-head:Linux_SDK_V0.9.5

4 Commits
Linux_SDK_ ... Linux_SDK_

Author SHA1 Message Date
devops_admin
316b169ffe Linux_SDK_V2.0.2 
Signed-off-by: devops_admin <devops_admin@alibabacloud.com>
 2024-09-20 22:46:25 +08:00
thead_admin
d8c8b62185 Linux_SDK_V1.5.4 
Signed-off-by: thead_admin <occ_thead@service.alibaba.com>
 2024-05-08 06:14:10 +00:00
thead_admin
ba628b63b3 Linux_SDK_V1.4.2 
Signed-off-by: thead_admin <occ_thead@service.alibaba.com>
 2023-12-24 19:20:14 +08:00
thead_admin
60c2e85ba7 Linux_SDK_V1.3.3 
Signed-off-by: thead_admin <occ_thead@service.alibaba.com>
 2023-12-24 19:19:50 +08:00
163 changed files with 27271 additions and 770 deletions
Expand all files Collapse all files

3
Makefile
View File

@@ -727,6 +727,7 @@ UBOOTINCLUDE := \
-I$(srctree)/arch/$(ARCH)/thumb1/include),) \
-I$(srctree)/arch/$(ARCH)/include \
$(if $(CONFIG_TARGET_LIGHT_C910), -I$(srctree)/lib/sec_library/include) \
$(if $(CONFIG_TARGET_LIGHT_C910), -I$(srctree)/lib/sec_library/include/soft_crypto) \
-include $(srctree)/include/linux/kconfig.h
NOSTDINC_FLAGS += -nostdinc -isystem $(shell $(CC) -print-file-name=include)
@@ -757,6 +758,8 @@ libs-y += drivers/net/phy/
libs-y += drivers/power/ \
drivers/power/domain/ \
drivers/power/fuel_gauge/ \
drivers/power/charge/ \
drivers/mcu/ \
drivers/power/mfd/ \
drivers/power/pmic/ \
drivers/power/battery/ \

1
arch/riscv/cpu/c9xx/Makefile
View File

@@ -6,3 +6,4 @@
obj-y += dram.o
obj-y += cpu.o
obj-y += feature.o

6
arch/riscv/cpu/c9xx/dram.c
View File

@@ -14,9 +14,9 @@ DECLARE_GLOBAL_DATA_PTR;
int dram_init(void)
{
#ifdef CONFIG_DDR_BOARD_CONFIG
extern unsigned long get_ddr_density(void);
// update ram_size from board config info
gd->ram_size = get_ddr_density();
// already setup during ddr initial flow
gd->bd->bi_memsize = gd->ram_size;
gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
return 0;
#else
return fdtdec_setup_mem_size_base();

114
arch/riscv/cpu/c9xx/feature.c Normal file
View File

@@ -0,0 +1,114 @@
#include <common.h>
#include <asm/types.h>
#include <asm/asm.h>
#include <asm/csr.h>
void setup_features(void)
{
unsigned int i, cpu_type, cpu_ver;
unsigned long version[8];
for (i = 0; i < 8; i++)
version[i] = csr_read(CSR_MCPUID);
cpu_type = (version[0] >> 18) & 0xf;
cpu_ver = (version[1] >> 12) & 0xffff;
/*
* Warning: CSR_MCCR2 contains an L2 cache latency setting,
* you need to confirm it by your own soc design.
*/
switch (cpu_type) {
case 0x3:
if (cpu_ver >= 0x1080 && cpu_ver <= 0x10bf) { //1.2.0~1.2.x
csr_write(CSR_MCCR2, 0xe0010009);
csr_write(CSR_MXSTATUS, 0x638000);
csr_write(CSR_MHINT, 0x6e30c);
csr_write(CSR_MHCR, 0x1ff);
} else if (cpu_ver == 0x10ca) { //1.3.10
csr_write(CSR_MSMPR, 0x1);
csr_write(CSR_MCCR2, 0xe2490009);
csr_write(CSR_MXSTATUS, 0x638000);
csr_write(CSR_MHINT, 0x66e30c);
csr_write(CSR_MHCR, 0x17f);
csr_write(CSR_MHINT2, 0x420000);
csr_write(CSR_MHINT4, 0x410);
} else if (cpu_ver >= 0x1100 && cpu_ver <= 0x113f) { //1.4.0~1.4.x
csr_write(CSR_MSMPR, 0x1);
csr_write(CSR_MCCR2, 0xe2490009);
csr_write(CSR_MXSTATUS, 0x638000);
csr_write(CSR_MHINT, 0x16e30c);
csr_write(CSR_MHCR, 0x1ff);
} else if (cpu_ver >= 0x1140 && cpu_ver <= 0x117f) { //1.5.0~1.5.x
csr_write(CSR_MSMPR, 0x1);
csr_write(CSR_MCCR2, 0xe2490009);
csr_write(CSR_MXSTATUS, 0x638000);
csr_write(CSR_MHINT, 0xe6e30c);
csr_write(CSR_MHINT2, 0x180);
csr_write(CSR_MHCR, 0x1ff);
} else if (cpu_ver >= 0x1180 && cpu_ver <= 0x1183) { //1.6.0~1.6.3
csr_write(CSR_MSMPR, 0x1);
csr_write(CSR_MCCR2, 0xe249000b);
csr_write(CSR_MXSTATUS, 0x638000);
csr_write(CSR_MHINT, 0x1ee30c);
csr_write(CSR_MHINT2, 0x180);
csr_write(CSR_MHCR, 0x1ff);
} else if (cpu_ver >= 0x1184 && cpu_ver <= 0x123f) { //1.6.4~1.8.x
csr_write(CSR_MSMPR, 0x1);
csr_write(CSR_MCCR2, 0xe249000b);
csr_write(CSR_MXSTATUS, 0x638000);
csr_write(CSR_MHINT, 0x1ee30c);
csr_write(CSR_MHINT2, 0x180);
csr_write(CSR_MHCR, 0x11ff);
} else if (cpu_ver >= 0x2000 && cpu_ver <= 0xffff) { //2.0.0~
csr_write(CSR_MSMPR, 0x1);
csr_write(CSR_MCCR2, 0xe249000b);
csr_write(CSR_MXSTATUS, 0x438000);
csr_write(CSR_MHINT, 0x31ea32c);
csr_write(CSR_MHINT2, 0x180);
csr_write(CSR_MHCR, 0x11ff);
} else {
while(1);
}
break;
case 0x4:
if (cpu_ver >= 0x1002 && cpu_ver <= 0xffff) {
csr_write(CSR_MHCR, 0x17f);
csr_write(CSR_MXSTATUS, 0x638000);
csr_write(CSR_MHINT, 0x650c);
} else {
while(1);
}
break;
case 0x5:
if (cpu_ver >= 0x0000 && cpu_ver <= 0x0007) { //0.0.0~0.0.7
csr_write(CSR_MSMPR, 0x1);
csr_write(CSR_MCCR2, 0xe0420008);
csr_write(CSR_MXSTATUS, 0x638000);
csr_write(CSR_MHINT, 0x2c50c);
csr_write(CSR_MHCR, 0x11ff);
} else if (cpu_ver >= 0x0040 && cpu_ver <= 0xffff) { //0.1.0~
csr_write(CSR_MSMPR, 0x1);
csr_write(CSR_MCCR2, 0xa042000a);
csr_write(CSR_MXSTATUS, 0x438000);
csr_write(CSR_MHINT, 0x21aa10c);
csr_write(CSR_MHCR, 0x10011ff);
} else {
while(1);
}
break;
case 0x6:
if (cpu_ver >= 0x0) {
csr_write(CSR_MSMPR, 0x1);
csr_write(CSR_MCCR2, 0xA042000A);
csr_write(CSR_MXSTATUS, 0x638001);
csr_write(CSR_MHINT, 0x3A1AA10C);
csr_write(CSR_MHCR, 0x10011BF);
} else {
while(1);
}
break;
default:
while(1);
}
}

9
arch/riscv/cpu/cpu.c
View File

@@ -27,6 +27,15 @@ u32 hart_lottery __attribute__((section(".data"))) = 0;
u32 available_harts_lock = 1;
#endif
void arch_setup_gd(struct global_data *gd_ptr)
{
// sync specific info from spl
gd_ptr->ram_size = gd->ram_size;
// setup gd ptr
gd = gd_ptr;
}
static inline bool supports_extension(char ext)
{
#ifdef CONFIG_CPU

42
arch/riscv/cpu/mtrap.S
View File

@@ -104,3 +104,45 @@ trap_entry:
LREG x2, 2 * REGBYTES(sp)
addi sp, sp, 32 * REGBYTES
MODE_PREFIX(ret)
/* trap secondary_entry */
.align 10
.global secondary_entry
secondary_entry:
/*
* Clear L1 cache & BTB & BHT ...
*/
li t0, 0x70013
csrw CSR_MCOR, t0
/*
* Enable cache coherency
*/
li t0, 1
csrw CSR_MSMPR, t0
/*
*Prepare percpu stack
*/
csrr t0, mhartid
li t1, 0x100
mul t1, t1, t0
lla sp, stacks
add sp, sp, t1
/*
* Call C routine
*/
call setup_features
call next_stage
/*
* Never get here, dead loop
*/
j .
.align 10
stacks:
.rept 0x1000
.long
.endr

28
arch/riscv/cpu/start.S
View File

@@ -104,12 +104,6 @@ call_board_init_f_0:
mv a0, sp
jal board_init_f_alloc_reserve
/*
* Set global data pointer here for all harts, uninitialized at this
* point.
*/
mv gp, a0
/* setup stack */
#ifdef CONFIG_SMP
/* tp: hart id */
@@ -127,16 +121,34 @@ call_board_init_f_0:
la t0, hart_lottery
li s2, 1
amoswap.w s2, t1, 0(t0)
bnez s2, wait_for_gd_init
beqz s2, call_board_init_f_1
/*
* Set global data pointer here for secondary harts, uninitialized at this
* point.
*/
mv gp, a0
jal wait_for_gd_init
#else
bnez tp, secondary_hart_loop
beqz tp, call_board_init_f_1
/*
* Set global data pointer here for secondary harts, uninitialized at this
* point.
*/
mv gp, a0
jal secondary_hart_loop
#endif
call_board_init_f_1:
#ifdef CONFIG_OF_PRIOR_STAGE
la t0, prior_stage_fdt_address
SREG s1, 0(t0)
#endif
/* Set global data pointer here for main hart */
jal board_init_f_init_reserve
/* save the boot hart id to global_data */

2
arch/riscv/dts/Makefile
View File

@@ -5,7 +5,7 @@ dtb-$(CONFIG_TARGET_SIFIVE_FU540) += hifive-unleashed-a00.dtb
dtb-$(CONFIG_TARGET_ICE_C910) += ice-c910.dtb
dtb-$(CONFIG_TARGET_LIGHT_EVB_MPW_C910) += light-evb-mpw-c910.dtb
dtb-$(CONFIG_TARGET_LIGHT_FPGA_FM_C910) += light-fpga-fm-c910.dtb
dtb-$(CONFIG_TARGET_LIGHT_C910) += light-a-ref.dtb light-b-ref.dtb light-a-val.dtb light-b-product.dtb light-a-product.dtb light-ant-ref.dtb light-beagle.dtb light-b-power.dtb light-lpi4a.dtb
dtb-$(CONFIG_TARGET_LIGHT_C910) += light-a-ref.dtb light-b-ref.dtb light-a-val.dtb light-b-product.dtb light-a-product.dtb light-ant-ref.dtb light-beagle.dtb light-b-power.dtb light-lpi4a.dtb th1520-rvbook.dtb
targets += $(dtb-y)

446
arch/riscv/dts/light-a-val.dts
View File

@@ -1,4 +1,7 @@
/dts-v1/;
#include <dt-bindings/pmic/light_pmic.h>
/ {
model = "T-HEAD c910 light";
compatible = "thead,c910_light";
@@ -306,10 +309,10 @@
spi-max-frequency = <100000000>;
#address-cells = <1>;
#size-cells = <0>;
flash@0 {
compatible = "jedec,spi-nor";
tpm@0{
compatible = "z32h330tc,z32h330tc-spi";
reg = <0>;
spi-max-frequency = <40000000>;
spi-max-frequency = <20000000>;
};
};
@@ -359,6 +362,20 @@
};
};
usb: usb@ffe7040000 {
compatible = "snps,dwc3";
reg = <0xff 0xe7040000 0x0 0x10000>;
interrupts = <68>;
reg-shift = <2>;
reg-io-width = <4>;
maximum-speed = "super-speed";
dr_mode = "host";
dma-mask = <0xf 0xffffffff>;
snps,usb3_lpm_capable;
snps,usb_sofitpsync;
status = "okay";
};
pwm: pwm@ffec01c000 {
compatible = "thead,pwm-light";
reg = <0xff 0xec01c000 0x0 0x4000>;
@@ -479,6 +496,429 @@
lcd-en-gpios = <&pcal6408ahk_a 2 0>; /* active high */
lcd-bias-en-gpios = <&pcal6408ahk_a 4 0>;/* active high */
};
aon {
compatible = "thead,light-aon";
status = "okay";
wakeup-by-gpio-on;
wakeup-by-rtc-on;
pd: light-aon-pd {
compatible = "thead,light-aon-pd";
#power-domain-cells = <1>;
};
light-regu-reg {
compatible = "thead,light-dialog-pmic";
status = "okay";
soc_dvdd18_aon_reg: soc_dvdd18_aon {
regulator-name = "soc_dvdd18_aon";
regulator-boot-on;
regulator-always-on;
};
soc_avdd33_usb3_reg: soc_avdd33_usb3 {
regulator-name = "soc_avdd33_usb3";
regulator-boot-on;
regulator-always-on;
};
soc_dvdd08_aon_reg: soc_dvdd08_aon {
regulator-name = "soc_dvdd08_aon";
regulator-boot-on;
regulator-always-on;
};
soc_apcpu_dvdd_dvddm_reg: soc_apcpu_dvdd_dvddm {
regulator-name = "soc_apcpu_dvdd_dvddm";
regulator-min-microvolt = <300000>;
regulator-max-microvolt = <1570000>;
regulator-boot-on;
regulator-always-on;
};
soc_dvdd08_ddr_reg: soc_dvdd08_ddr {
regulator-name = "soc_dvdd08_ddr";
regulator-boot-on;
regulator-always-on;
};
soc_vdd_ddr_1v8_reg: soc_vdd_ddr_1v8 {
regulator-name = "soc_vdd_ddr_1v8";
regulator-boot-on;
regulator-always-on;
};
soc_vdd_ddr_1v1_reg: soc_vdd_ddr_1v1 {
regulator-name = "soc_vdd_ddr_1v1";
regulator-boot-on;
regulator-always-on;
};
soc_vdd_ddr_0v6_reg: soc_vdd_ddr_0v6 {
regulator-name = "soc_vdd_ddr_0v6";
regulator-boot-on;
regulator-always-on;
};
soc_dvdd18_ap_reg: soc_dvdd18_ap {
regulator-name = "soc_dvdd18_ap";
regulator-boot-on;
regulator-always-on;
};
soc_dvdd08_ap_reg: soc_dvdd08_ap {
regulator-name = "soc_dvdd08_ap";
regulator-boot-on;
regulator-always-on;
};
soc_avdd08_mipi_hdmi_reg: soc_avdd08_mipi_hdmi {
regulator-name = "soc_avdd08_mipi_hdmi";
regulator-boot-on;
regulator-always-on;
};
soc_avdd18_mipi_hdmi_reg: soc_avdd18_mipi_hdmi {
regulator-name = "soc_avdd18_mipi_hdmi";
regulator-boot-on;
regulator-always-on;
};
soc_dvdd33_emmc_reg: soc_dvdd33_emmc {
regulator-name = "soc_dvdd33_emmc";
regulator-boot-on;
regulator-always-on;
};
soc_dvdd18_emmc_reg: soc_dvdd18_emmc {
regulator-name = "soc_vdd18_emmc";
regulator-boot-on;
regulator-always-on;
};
soc_dovdd18_scan_reg: soc_dovdd18_scan {
regulator-name = "soc_dovdd18_scan";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <3600000>;
};
soc_vext_2v8_reg: soc_vext_2v8 {
regulator-name = "soc_vext_2v8";
regulator-boot-on;
regulator-always-on;
};
soc_dvdd12_scan_reg: soc_dvdd12_scan {
regulator-name = "soc_dvdd12_scan";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <3600000>;
};
soc_avdd28_scan_en_reg: soc_avdd28_scan_en {
regulator-name = "soc_avdd28_scan_en";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
};
soc_avdd28_rgb_reg: soc_avdd28_rgb {
regulator-name = "soc_avdd28_rgb";
regulator-min-microvolt = <2200000>;
regulator-max-microvolt = <3475000>;
regulator-boot-on;
regulator-always-on;
};
soc_dovdd18_rgb_reg: soc_dovdd18_rgb {
regulator-name = "soc_dovdd18_rgb";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3600000>;
regulator-boot-on;
regulator-always-on;
};
soc_dvdd12_rgb_reg: soc_dvdd12_rgb {
regulator-name = "soc_dvdd12_rgb";
regulator-min-microvolt = <400000>;
regulator-max-microvolt = <1675000>;
regulator-boot-on;
regulator-always-on;
};
soc_avdd25_ir_reg: soc_avdd25_ir {
regulator-name = "soc_avdd25_ir";
regulator-min-microvolt = <2200000>;
regulator-max-microvolt = <3475000>;
regulator-boot-on;
regulator-always-on;
};
soc_dovdd18_ir_reg: soc_dovdd18_ir {
regulator-name = "soc_dovdd18_ir";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3600000>;
regulator-boot-on;
regulator-always-on;
};
soc_dvdd12_ir_reg: soc_dvdd12_ir {
regulator-name = "soc_dvdd12_ir";
regulator-min-microvolt = <400000>;
regulator-max-microvolt = <1675000>;
regulator-boot-on;
regulator-always-on;
};
};
aon_pmic_config {
compatible = "thead,light-pmic-conf";
status = "okay";
#address-cells = <1>;
#size-cells = <0>;
iic-config = <0 0 2>;
pmic_dev_0: pmic-dev@0 {
pmic-name = "dialog,da9063,v1";
pmic-addr = <0x5a 0x5b>;
pmic_wdt_on;
errio_gpio = <0 14 3>;
status = "okay";
};
pmic_dev_1: pmic-dev@1 {
pmic-name = "dialog,da9121,v1";
pmic-addr = <0x68>;
status = "okay";
};
pmic_dev_2: pmic-dev@2 {
pmic-name = "dialog,slg51000,v1";
pmic-addr = <0x75>;
status = "okay";
};
regu_config_0 {
reg_info = <&soc_dvdd18_aon_reg>;
status = "okay";
regu_id@0 {
pmic_dev = <&pmic_dev_0 DA9063_ID_LDO3>;
};
};
regu_config_1 {
reg_info = <&soc_avdd33_usb3_reg>;
status = "okay";
regu_id@0 {
pmic_dev = <&pmic_dev_0 DA9063_ID_LDO9>;
};
};
regu_config_2 {
reg_info = <&soc_dvdd08_aon_reg>;
status = "okay";
regu_id@0 {
pmic_dev = <&pmic_dev_0 DA9063_ID_LDO2>;
};
};
regu_config_3 {
reg_info = <&soc_apcpu_dvdd_dvddm_reg>;
status = "okay";
regu_id@0 {
pmic_dev = <&pmic_dev_0 DA9063_ID_BCORE1>;
auto_on_info = <0 0 800000>;
};
regu_id@1 {
pmic_dev = <&pmic_dev_0 DA9063_ID_BCORE2>;
auto_on_info = <1 0 800000>;
};
coupling_info@0 {
negative-min;
info = <0 1 5 30>;
};
};
regu_config_4 {
reg_info = <&soc_dvdd08_ddr_reg>;
status = "okay";
regu_id@0 {
pmic_dev = <&pmic_dev_0 DA9063_ID_BUCKPERI>;
};
};
regu_config_5 {
reg_info = <&soc_vdd_ddr_1v8_reg>;
status = "okay";
regu_id@0 {
pmic_dev = <&pmic_dev_0 DA9063_ID_LDO4>;
};
};
regu_config_6 {
reg_info = <&soc_vdd_ddr_1v1_reg>;
status = "okay";
regu_id@0 {
pmic_dev = <&pmic_dev_0 DA9063_ID_BUCKMEM>;
};
regu_id@1 {
pmic_dev = <&pmic_dev_0 DA9063_ID_BUCKIO>;
};
};
regu_config_7 {
reg_info = <&soc_vdd_ddr_0v6_reg>;
status = "okay";
regu_id@0 {
pmic_dev = <&pmic_dev_0 DA9063_ID_BUCKPRO>;
};
};
regu_config_8 {
reg_info = <&soc_dvdd18_ap_reg>;
status = "okay";
regu_id@0 {
pmic_dev = <&pmic_dev_0 DA9063_ID_LDO11>;
};
};
regu_config_9 {
reg_info = <&soc_avdd08_mipi_hdmi_reg>;
status = "okay";
regu_id@0 {
pmic_dev = <&pmic_dev_0 DA9063_ID_LDO1>;
};
};
regu_config_10 {
reg_info = <&soc_avdd18_mipi_hdmi_reg>;
status = "okay";
regu_id@0 {
pmic_dev = <&pmic_dev_0 DA9063_ID_LDO5>;
};
};
regu_config_11 {
reg_info = <&soc_dvdd33_emmc_reg>;
status = "okay";
regu_id@0 {
pmic_dev = <&pmic_dev_0 DA9063_ID_LDO10>;
};
};
regu_config_12 {
reg_info = <&soc_dovdd18_scan_reg>;
status = "okay";
regu_id@0 {
pmic_dev = <&pmic_dev_0 DA9063_ID_LDO6>;
auto_on_info = <2 1 1800000>;
auto_off_info = <7 1>;
};
};
regu_config_13 {
reg_info = <&soc_vext_2v8_reg>;
status = "okay";
regu_id@0 {
pmic_dev = <&pmic_dev_0 DA9063_ID_LDO7>;
auto_on_info = <3 1 2800000>;
auto_off_info = <8 1>;
};
};
regu_config_14 {
reg_info = <&soc_dvdd12_scan_reg>;
status = "okay";
regu_id@0 {
pmic_dev = <&pmic_dev_0 DA9063_ID_LDO8>;
auto_on_info = <4 1 1200000>;
auto_off_info = <9 1>;
};
};
regu_config_15 {
reg_info = <&soc_avdd28_scan_en_reg>;
status = "okay";
regu_id@0 {
pmic_dev = <&pmic_dev_0 DA9063_ID_GPIO4>;
auto_on_info = <5 1 2800000>;
auto_off_info = <6 1>;
};
};
regu_config_16 {
reg_info = <&soc_dvdd08_ap_reg>;
status = "okay";
regu_id@0 {
pmic_dev = <&pmic_dev_1 DA9121_ID_BUCK1>;
parent_pmic_dev = <&pmic_dev_0 2 0>;
};
};
regu_config_17 {
reg_info = <&soc_avdd28_rgb_reg>;
status = "okay";
regu_id@0 {
pmic_dev = <&pmic_dev_2 SLG51000_ID_LDO1>;
auto_on_info = <6 0 2800000>;
auto_off_info = <0 1>;
};
};
regu_config_18 {
reg_info = <&soc_avdd25_ir_reg>;
status = "okay";
regu_id@0 {
pmic_dev = <&pmic_dev_2 SLG51000_ID_LDO2>;
auto_on_info = <7 0 2500000>;
auto_off_info = <1 1>;
};
};
regu_config_19 {
reg_info = <&soc_dvdd18_emmc_reg>;
status = "okay";
regu_id@0 {
pmic_dev = <&pmic_dev_2 SLG51000_ID_LDO3>;
parent_pmic_dev = <&pmic_dev_0 7 0>;
};
};
regu_config_20 {
reg_info = <&soc_dovdd18_rgb_reg>;
status = "okay";
regu_id@0 {
pmic_dev = <&pmic_dev_2 SLG51000_ID_LDO4>;
auto_on_info = <8 0 1800000>;
auto_off_info = <2 1>;
};
};
regu_config_21 {
reg_info = <&soc_dvdd12_rgb_reg>;
status = "okay";
regu_id@0 {
pmic_dev = <&pmic_dev_2 SLG51000_ID_LDO5>;
auto_on_info = <9 0 1200000>;
auto_off_info = <3 1>;
};
};
regu_config_22 {
reg_info = <&soc_dvdd12_ir_reg>;
status = "okay";
regu_id@0 {
pmic_dev = <&pmic_dev_2 SLG51000_ID_LDO6>;
auto_on_info = <10 0 1200000>;
auto_off_info = <4 1>;
};
};
regu_config_23 {
reg_info = <&soc_dovdd18_ir_reg>;
status = "okay";
regu_id@0 {
pmic_dev = <&pmic_dev_2 SLG51000_ID_LDO7>;
auto_on_info = <11 0 1800000>;
auto_off_info = <5 1>;
};
};
};
};
};
chosen {

359
arch/riscv/dts/light-b-product.dts
View File

@@ -1,4 +1,7 @@
/dts-v1/;
#include <dt-bindings/pmic/light_pmic.h>
/ {
model = "T-HEAD c910 light";
compatible = "thead,c910_light";
@@ -469,6 +472,362 @@
lcd-en-gpios = <&gpio1_porta 9 0>; /* active high */
lcd-bias-en-gpios = <&gpio1_porta 10 0>;/* active high */
};
aon {
compatible = "thead,light-aon";
status = "okay";
wakeup-by-gpio-on;
wakeup-by-rtc-on;
pd: light-aon-pd {
compatible = "thead,light-aon-pd";
#power-domain-cells = <1>;
};
light-regu-reg {
compatible = "thead,light-dialog-pmic";
status = "okay";
soc_dvdd18_aon_reg: soc_dvdd18_aon {
regulator-name = "soc_dvdd18_aon";
regulator-boot-on;
regulator-always-on;
};
soc_avdd33_usb3_reg: soc_avdd33_usb3 {
regulator-name = "soc_avdd33_usb3";
regulator-boot-on;
regulator-always-on;
};
soc_dvdd08_aon_reg: soc_dvdd08_aon {
regulator-name = "soc_dvdd08_aon";
regulator-boot-on;
regulator-always-on;
};
soc_apcpu_dvdd_dvddm_reg: soc_apcpu_dvdd_dvddm {
regulator-name = "soc_apcpu_dvdd_dvddm";
regulator-min-microvolt = <300000>;
regulator-max-microvolt = <1570000>;
regulator-boot-on;
regulator-always-on;
};
soc_dvdd08_ddr_reg: soc_dvdd08_ddr {
regulator-name = "soc_dvdd08_ddr";
regulator-boot-on;
regulator-always-on;
};
soc_vdd_ddr_1v8_reg: soc_vdd_ddr_1v8 {
regulator-name = "soc_vdd_ddr_1v8";
regulator-boot-on;
regulator-always-on;
};
soc_vdd_ddr_1v1_reg: soc_vdd_ddr_1v1 {
regulator-name = "soc_vdd_ddr_1v1";
regulator-boot-on;
regulator-always-on;
};
soc_vdd_ddr_0v6_reg: soc_vdd_ddr_0v6 {
regulator-name = "soc_vdd_ddr_0v6";
regulator-boot-on;
regulator-always-on;
};
soc_dvdd18_ap_reg: soc_dvdd18_ap {
regulator-name = "soc_dvdd18_ap";
regulator-boot-on;
regulator-always-on;
};
soc_dvdd08_ap_reg: soc_dvdd08_ap {
regulator-name = "soc_dvdd08_ap";
regulator-boot-on;
regulator-always-on;
};
soc_avdd08_mipi_hdmi_reg: soc_avdd08_mipi_hdmi {
regulator-name = "soc_avdd08_mipi_hdmi";
regulator-boot-on;
regulator-always-on;
};
soc_avdd18_mipi_hdmi_reg: soc_avdd18_mipi_hdmi {
regulator-name = "soc_avdd18_mipi_hdmi";
regulator-boot-on;
regulator-always-on;
};
soc_dvdd33_emmc_reg: soc_dvdd33_emmc {
regulator-name = "soc_dvdd33_emmc";
regulator-boot-on;
regulator-always-on;
};
soc_dvdd18_emmc_reg: soc_dvdd18_emmc {
regulator-name = "soc_vdd18_emmc";
regulator-boot-on;
regulator-always-on;
};
soc_dovdd18_scan_reg: soc_dovdd18_scan {
regulator-name = "soc_dovdd18_scan";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <3600000>;
status = "disabled";
};
soc_vext_2v8_reg: soc_vext_2v8 {
regulator-name = "soc_vext_2v8";
regulator-boot-on;
regulator-always-on;
status = "disabled";
};
soc_dvdd12_scan_reg: soc_dvdd12_scan {
regulator-name = "soc_dvdd12_scan";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <3600000>;
status = "disabled";
};
soc_avdd28_scan_en_reg: soc_avdd28_scan_en {
regulator-name = "soc_avdd28_scan_en";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
status = "disabled";
};
soc_avdd28_rgb_reg: soc_avdd28_rgb {
regulator-name = "soc_avdd28_rgb";
regulator-min-microvolt = <2200000>;
regulator-max-microvolt = <3475000>;
regulator-boot-on;
regulator-always-on;
status = "disabled";
};
soc_dovdd18_rgb_reg: soc_dovdd18_rgb {
regulator-name = "soc_dovdd18_rgb";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3600000>;
regulator-boot-on;
regulator-always-on;
status = "disabled";
};
soc_dvdd12_rgb_reg: soc_dvdd12_rgb {
regulator-name = "soc_dvdd12_rgb";
regulator-min-microvolt = <400000>;
regulator-max-microvolt = <1675000>;
regulator-boot-on;
regulator-always-on;
status = "disabled";
};
soc_avdd25_ir_reg: soc_avdd25_ir {
regulator-name = "soc_avdd25_ir";
regulator-min-microvolt = <2200000>;
regulator-max-microvolt = <3475000>;
regulator-boot-on;
regulator-always-on;
status = "disabled";
};
soc_dovdd18_ir_reg: soc_dovdd18_ir {
regulator-name = "soc_dovdd18_ir";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3600000>;
regulator-boot-on;
regulator-always-on;
status = "disabled";
};
soc_dvdd12_ir_reg: soc_dvdd12_ir {
regulator-name = "soc_dvdd12_ir";
regulator-min-microvolt = <400000>;
regulator-max-microvolt = <1675000>;
regulator-boot-on;
regulator-always-on;
status = "disabled";
};
soc_adc_vref_reg: soc_adc_vref {
regulator-name = "soc_adc_vref";
};
soc_lcd0_en_reg: soc_lcd0_en {
regulator-name = "soc_lcd0_en";
};
soc_vext_1v8_reg: soc_vext_1v8 {
regulator-name = "soc_vext_1v8";
};
};
aon_pmic_config {
compatible = "thead,light-pmic-conf";
status = "okay";
#address-cells = <1>;
#size-cells = <0>;
iic-config = <0 0 2>;
pmic_dev_0: pmic-dev@0 {
pmic-name = "ricoh,rn5t567,v0";
pmic-addr = <0x31>;
pmic_wdt_on;
status = "okay";
};
pmic_dev_1: pmic-dev@1 {
pmic-name = "ricoh,rn5t567,v1";
pmic-addr = <0x32>;
status = "okay";
};
regu_config_0 {
reg_info = <&soc_dvdd18_aon_reg>;
status = "okay";
regu_id@0 {
pmic_dev = <&pmic_dev_0 RICOH567_ID_LDO4>;
};
};
regu_config_1 {
reg_info = <&soc_avdd33_usb3_reg>;
status = "okay";
regu_id@0 {
pmic_dev = <&pmic_dev_0 RICOH567_ID_LDO1>;
};
};
regu_config_2 {
reg_info = <&soc_dvdd08_aon_reg>;
status = "okay";
regu_id@0 {
pmic_dev = <&pmic_dev_0 RICOH567_ID_LDO3>;
};
};
regu_config_3 {
reg_info = <&soc_apcpu_dvdd_dvddm_reg>;
status = "okay";
regu_id@0 {
pmic_dev = <&pmic_dev_0 RICOH567_ID_DC3>;
auto_on_info = <2 0 800000>;
};
regu_id@1 {
pmic_dev = <&pmic_dev_0 RICOH567_ID_DC4>;
auto_on_info = <3 0 800000>;
};
coupling_info@0 {
negative-min;
info = <0 1 5 30>;
};
};
regu_config_4 {
reg_info = <&soc_dvdd08_ddr_reg>;
status = "okay";
regu_id@0 {
pmic_dev = <&pmic_dev_0 RICOH567_ID_DC1>;
};
};
regu_config_5 {
reg_info = <&soc_vdd_ddr_1v8_reg>;
status = "okay";
regu_id@0 {
pmic_dev = <&pmic_dev_0 RICOH567_ID_LDO2>;
};
};
regu_config_6 {
reg_info = <&soc_vdd_ddr_1v1_reg>;
status = "okay";
regu_id@0 {
pmic_dev = <&pmic_dev_1 RICOH567_ID_DC2>;
};
};
regu_config_7 {
reg_info = <&soc_vdd_ddr_0v6_reg>;
status = "okay";
regu_id@0 {
pmic_dev = <&pmic_dev_1 RICOH567_ID_DC1>;
};
};
regu_config_8 {
reg_info = <&soc_dvdd18_ap_reg>;
status = "okay";
regu_id@0 {
pmic_dev = <&pmic_dev_1 RICOH567_ID_LDO2>;
};
};
regu_config_9 {
reg_info = <&soc_avdd08_mipi_hdmi_reg>;
status = "okay";
regu_id@0 {
pmic_dev = <&pmic_dev_1 RICOH567_ID_LDO3>;
};
};
regu_config_10 {
reg_info = <&soc_avdd18_mipi_hdmi_reg>;
status = "okay";
regu_id@0 {
pmic_dev = <&pmic_dev_1 RICOH567_ID_LDO4>;
};
};
regu_config_11 {
reg_info = <&soc_dvdd33_emmc_reg>;
status = "okay";
regu_id@0 {
pmic_dev = <&pmic_dev_1 RICOH567_ID_LDO1>;
};
};
regu_config_12 {
reg_info = <&soc_dvdd08_ap_reg>;
status = "okay";
regu_id@0 {
pmic_dev = <&pmic_dev_1 RICOH567_ID_GPIO3>;
};
};
regu_config_13 {
reg_info = <&soc_dvdd18_emmc_reg>;
status = "okay";
regu_id@0 {
pmic_dev = <&pmic_dev_1 RICOH567_ID_DC3>;
};
};
regu_config_14 {
reg_info = <&soc_adc_vref_reg>;
status = "okay";
regu_id@0 {
pmic_dev = <&pmic_dev_1 RICOH567_ID_LDO5>;
};
};
regu_config_15 {
reg_info = <&soc_lcd0_en_reg>;
status = "okay";
regu_id@0 {
pmic_dev = <&pmic_dev_0 RICOH567_ID_LDO5>;
auto_on_info = <0 0 1800000>;
};
};
regu_config_16 {
reg_info = <&soc_vext_1v8_reg>;
status = "okay";
regu_id@0 {
pmic_dev = <&pmic_dev_1 RICOH567_ID_DC4>;
auto_on_info = <1 0 1800000>;
};
};
};
};
};
chosen {

404
arch/riscv/dts/light-lpi4a.dts
View File

@@ -1,4 +1,7 @@
/dts-v1/;
#include <dt-bindings/pmic/light_pmic.h>
/ {
model = "T-HEAD c910 light";
compatible = "thead,c910_light";
@@ -147,6 +150,13 @@
#address-cells = <1>;
#size-cells = <0>;
pcal6408ahk_d: gpio@20 {
compatible = "nxp,pca9557";
reg = <0x18>;
gpio-controller;
#gpio-cells = <2>;
};
};
i2c4: i2c@ffe7f28000{
@@ -157,13 +167,6 @@
#address-cells = <1>;
#size-cells = <0>;
pcal6408ahk_a: gpio@20 {
compatible = "nxp,pca9554";
reg = <0x20>;
gpio-controller;
#gpio-cells = <2>;
};
};
i2c5: i2c@fff7f2c000{
@@ -382,6 +385,20 @@
reg = <0xff 0xef600000 0x0 0x100>;
};
usb: usb@ffe7040000 {
compatible = "snps,dwc3";
reg = <0xff 0xe7040000 0x0 0x10000>;
interrupts = <68>;
reg-shift = <2>;
reg-io-width = <4>;
maximum-speed = "super-speed";
dr_mode = "host";
dma-mask = <0xf 0xffffffff>;
snps,usb3_lpm_capable;
snps,usb_sofitpsync;
status = "okay";
};
axiscr {
compatible = "thead,axiscr";
reg = <0xff 0xff004000 0x0 0x1000>;
@@ -472,13 +489,376 @@
default-brightness-level = <7>;
};
ili9881c_panel {
compatible = "ilitek,ili9881c";
jadard_jd9365da {
compatible = "jadard,jd9365da-h3";
backlight = <&lcd_backlight>;
reset-gpios = <&gpio1_porta 5 1>; /* active low */
lcd-en-gpios = <&pcal6408ahk_a 2 0>; /* active high */
lcd-bias-en-gpios = <&pcal6408ahk_a 4 0>;/* active high */
reset-gpio = <&pcal6408ahk_d 7 0>;
hsvcc-gpio = <&pcal6408ahk_d 6 1>;
vspn3v3-gpio = <&pcal6408ahk_d 5 1>;
};
aon {
compatible = "thead,light-aon";
status = "okay";
wakeup-by-gpio-on;
wakeup-by-rtc-on;
pd: light-aon-pd {
compatible = "thead,light-aon-pd";
#power-domain-cells = <1>;
};
light-regu-reg {
compatible = "thead,light-dialog-pmic";
status = "okay";
soc_dvdd18_aon_reg: soc_dvdd18_aon {
regulator-name = "soc_dvdd18_aon";
regulator-boot-on;
regulator-always-on;
};
soc_avdd33_usb3_reg: soc_avdd33_usb3 {
regulator-name = "soc_avdd33_usb3";
regulator-boot-on;
regulator-always-on;
};
soc_dvdd08_aon_reg: soc_dvdd08_aon {
regulator-name = "soc_dvdd08_aon";
regulator-boot-on;
regulator-always-on;
};
soc_apcpu_dvdd_dvddm_reg: soc_apcpu_dvdd_dvddm {
regulator-name = "soc_apcpu_dvdd_dvddm";
regulator-min-microvolt = <300000>;
regulator-max-microvolt = <1570000>;
regulator-boot-on;
regulator-always-on;
};
soc_dvdd08_ddr_reg: soc_dvdd08_ddr {
regulator-name = "soc_dvdd08_ddr";
regulator-boot-on;
regulator-always-on;
};
soc_vdd_ddr_1v8_reg: soc_vdd_ddr_1v8 {
regulator-name = "soc_vdd_ddr_1v8";
regulator-boot-on;
regulator-always-on;
};
soc_vdd_ddr_1v1_reg: soc_vdd_ddr_1v1 {
regulator-name = "soc_vdd_ddr_1v1";
regulator-boot-on;
regulator-always-on;
};
soc_vdd_ddr_0v6_reg: soc_vdd_ddr_0v6 {
regulator-name = "soc_vdd_ddr_0v6";
regulator-boot-on;
regulator-always-on;
};
soc_dvdd18_ap_reg: soc_dvdd18_ap {
regulator-name = "soc_dvdd18_ap";
regulator-boot-on;
regulator-always-on;
};
soc_dvdd08_ap_reg: soc_dvdd08_ap {
regulator-name = "soc_dvdd08_ap";
regulator-boot-on;
regulator-always-on;
};
soc_avdd08_mipi_hdmi_reg: soc_avdd08_mipi_hdmi {
regulator-name = "soc_avdd08_mipi_hdmi";
regulator-boot-on;
regulator-always-on;
};
soc_avdd18_mipi_hdmi_reg: soc_avdd18_mipi_hdmi {
regulator-name = "soc_avdd18_mipi_hdmi";
regulator-boot-on;
regulator-always-on;
};
soc_dvdd33_emmc_reg: soc_dvdd33_emmc {
regulator-name = "soc_dvdd33_emmc";
regulator-boot-on;
regulator-always-on;
};
soc_dvdd18_emmc_reg: soc_dvdd18_emmc {
regulator-name = "soc_vdd18_emmc";
regulator-boot-on;
regulator-always-on;
};
soc_dovdd18_scan_reg: soc_dovdd18_scan {
regulator-name = "soc_dovdd18_scan";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <3600000>;
};
soc_vext_2v8_reg: soc_vext_2v8 {
regulator-name = "soc_vext_2v8";
regulator-boot-on;
regulator-always-on;
status = "disabled";
};
soc_dvdd12_scan_reg: soc_dvdd12_scan {
regulator-name = "soc_dvdd12_scan";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <3600000>;
};
soc_avdd28_scan_en_reg: soc_avdd28_scan_en {
regulator-name = "soc_avdd28_scan_en";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
};
soc_avdd28_rgb_reg: soc_avdd28_rgb {
regulator-name = "soc_avdd28_rgb";
regulator-min-microvolt = <2200000>;
regulator-max-microvolt = <3475000>;
regulator-boot-on;
regulator-always-on;
status = "disabled";
};
soc_dovdd18_rgb_reg: soc_dovdd18_rgb {
regulator-name = "soc_dovdd18_rgb";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3600000>;
regulator-boot-on;
regulator-always-on;
status = "disabled";
};
soc_dvdd12_rgb_reg: soc_dvdd12_rgb {
regulator-name = "soc_dvdd12_rgb";
regulator-min-microvolt = <400000>;
regulator-max-microvolt = <1675000>;
regulator-boot-on;
regulator-always-on;
status = "disabled";
};
soc_avdd25_ir_reg: soc_avdd25_ir {
regulator-name = "soc_avdd25_ir";
regulator-min-microvolt = <2200000>;
regulator-max-microvolt = <3475000>;
regulator-boot-on;
regulator-always-on;
status = "disabled";
};
soc_dovdd18_ir_reg: soc_dovdd18_ir {
regulator-name = "soc_dovdd18_ir";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3600000>;
regulator-boot-on;
regulator-always-on;
status = "disabled";
};
soc_dvdd12_ir_reg: soc_dvdd12_ir {
regulator-name = "soc_dvdd12_ir";
regulator-min-microvolt = <400000>;
regulator-max-microvolt = <1675000>;
regulator-boot-on;
regulator-always-on;
status = "disabled";
};
};
aon_pmic_config {
compatible = "thead,light-pmic-conf";
status = "okay";
#address-cells = <1>;
#size-cells = <0>;
iic-config = <0 0 2>;
pmic_dev_0: pmic-dev@0 {
pmic-name = "dialog,da9063,v1";
pmic-addr = <0x5a 0x5b>;
pmic_wdt_on;
status = "okay";
};
pmic_dev_1: pmic-dev@1 {
pmic-name = "dialog,da9121,v1";
pmic-addr = <0x68>;
status = "okay";
};
regu_config_0 {
reg_info = <&soc_dvdd18_aon_reg>;
status = "okay";
regu_id@0 {
pmic_dev = <&pmic_dev_0 DA9063_ID_LDO3>;
};
};
regu_config_1 {
reg_info = <&soc_avdd33_usb3_reg>;
status = "okay";
regu_id@0 {
pmic_dev = <&pmic_dev_0 DA9063_ID_LDO9>;
};
};
regu_config_2 {
reg_info = <&soc_dvdd08_aon_reg>;
status = "okay";
regu_id@0 {
pmic_dev = <&pmic_dev_0 DA9063_ID_LDO2>;
};
};
regu_config_3 {
reg_info = <&soc_apcpu_dvdd_dvddm_reg>;
status = "okay";
regu_id@0 {
pmic_dev = <&pmic_dev_0 DA9063_ID_BCORE1>;
auto_on_info = <0 0 800000>;
};
regu_id@1 {
pmic_dev = <&pmic_dev_0 DA9063_ID_BCORE2>;
auto_on_info = <1 0 800000>;
};
regu_id@2 {
pmic_dev = <&pmic_dev_0 DA9063_ID_BUCKIO>;
auto_on_info = <2 0 800000>;
};
coupling_info@0 {
negative-min;
info = <0 2 5 30>;
};
coupling_info@1 {
negative-min;
info = <1 2 5 30>;
};
};
regu_config_4 {
reg_info = <&soc_dvdd08_ddr_reg>;
status = "okay";
regu_id@0 {
pmic_dev = <&pmic_dev_0 DA9063_ID_BUCKPERI>;
};
};
regu_config_5 {
reg_info = <&soc_vdd_ddr_1v8_reg>;
status = "okay";
regu_id@0 {
pmic_dev = <&pmic_dev_0 DA9063_ID_LDO4>;
};
};
regu_config_6 {
reg_info = <&soc_vdd_ddr_1v1_reg>;
status = "okay";
regu_id@0 {
pmic_dev = <&pmic_dev_0 DA9063_ID_BUCKMEM>;
};
};
regu_config_7 {
reg_info = <&soc_vdd_ddr_0v6_reg>;
status = "okay";
regu_id@0 {
pmic_dev = <&pmic_dev_0 DA9063_ID_BUCKPRO>;
};
};
regu_config_8 {
reg_info = <&soc_dvdd18_ap_reg>;
status = "okay";
regu_id@0 {
pmic_dev = <&pmic_dev_0 DA9063_ID_LDO11>;
};
};
regu_config_9 {
reg_info = <&soc_avdd08_mipi_hdmi_reg>;
status = "okay";
regu_id@0 {
pmic_dev = <&pmic_dev_0 DA9063_ID_LDO1>;
};
};
regu_config_10 {
reg_info = <&soc_avdd18_mipi_hdmi_reg>;
status = "okay";
regu_id@0 {
pmic_dev = <&pmic_dev_0 DA9063_ID_LDO5>;
};
};
regu_config_11 {
reg_info = <&soc_dvdd33_emmc_reg>;
status = "okay";
regu_id@0 {
pmic_dev = <&pmic_dev_0 DA9063_ID_LDO10>;
};
};
regu_config_12 {
reg_info = <&soc_dovdd18_scan_reg>;
status = "okay";
regu_id@0 {
pmic_dev = <&pmic_dev_0 DA9063_ID_LDO6>;
auto_on_info = <3 1 1800000>;
auto_off_info = <1 1>;
};
};
regu_config_13 {
reg_info = <&soc_dvdd12_scan_reg>;
status = "okay";
regu_id@0 {
pmic_dev = <&pmic_dev_0 DA9063_ID_LDO8>;
auto_on_info = <4 1 1200000>;
auto_off_info = <2 1>;
};
};
regu_config_14 {
reg_info = <&soc_avdd28_scan_en_reg>;
status = "okay";
regu_id@0 {
pmic_dev = <&pmic_dev_0 DA9063_ID_LDO7>;
auto_on_info = <5 1 2800000>;
auto_off_info = <0 1>;
};
};
regu_config_15 {
reg_info = <&soc_dvdd08_ap_reg>;
status = "okay";
regu_id@0 {
pmic_dev = <&pmic_dev_1 DA9121_ID_BUCK1>;
parent_pmic_dev = <&pmic_dev_0 2 0>;
};
};
regu_config_16 {
reg_info = <&soc_dvdd18_emmc_reg>;
status = "okay";
regu_id@0 {
pmic_dev = <&pmic_dev_0 DA9063_ID_GPIO7>;
parent_pmic_dev = <&pmic_dev_0 7 0>;
};
};
};
};
};
chosen {

947
arch/riscv/dts/th1520-rvbook.dts Normal file
View File

@@ -0,0 +1,947 @@
/dts-v1/;
#include <dt-bindings/usb/pd.h>
#include <dt-bindings/pmic/light_pmic.h>
/ {
model = "T-HEAD c910 light";
compatible = "thead,c910_light";
#address-cells = <2>;
#size-cells = <2>;
charge-animation {
compatible = "rockchip,uboot-charge";
uboot-low-power-voltage = <7300>;
powerkey-gpio= <&ao_gpio_porta 6 0>;
status = "okay";
};
leds {
status = "okay";
compatible = "gpio-leds";
red-led {
gpios = <&gpio1_porta 14 0>; // GPIO_ACTIVE_HIGH: 0
label = "battery_charging";
default-state = "off";
};
green-led {
gpios = <&gpio1_porta 13 0>; // GPIO_ACTIVE_HIGH: 0
label = "battery_full";
default-state = "off";
};
blue-led {
gpios = <&gpio1_porta 15 0>; // GPIO_ACTIVE_HIGH: 0
label = "battery_start";
default-state = "off";
};
};
memory@0 {
device_type = "memory";
reg = <0x0 0xc0000000 0x0 0x40000000>;
};
aliases {
spi0 = &spi0;
spi1 = &qspi0;
spi2 = &qspi1;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
timebase-frequency = <3000000>;
u-boot,dm-pre-reloc;
cpu@0 {
device_type = "cpu";
reg = <0>;
status = "okay";
compatible = "riscv";
riscv,isa = "rv64imafdcvsu";
mmu-type = "riscv,sv39";
u-boot,dm-pre-reloc;
};
};
soc {
#address-cells = <2>;
#size-cells = <2>;
compatible = "simple-bus";
ranges;
u-boot,dm-pre-reloc;
intc: interrupt-controller@ffd8000000 {
compatible = "riscv,plic0";
reg = <0xff 0xd8000000 0x0 0x04000000>;
status = "disabled";
};
dummy_apb: apb-clock {
compatible = "fixed-clock";
clock-frequency = <62500000>;
clock-output-names = "dummy_apb";
#clock-cells = <0>;
u-boot,dm-pre-reloc;
};
dummy_ahb: ahb-clock {
compatible = "fixed-clock";
clock-frequency = <250000000>;
clock-output-names = "core";
#clock-cells = <0>;
u-boot,dm-pre-reloc;
};
dummy_spi: spi-clock {
compatible = "fixed-clock";
clock-frequency = <396000000>;
clock-output-names = "dummy_spi";
#clock-cells = <0>;
u-boot,dm-pre-reloc;
};
dummy_qspi0: qspi0-clock {
compatible = "fixed-clock";
clock-frequency = <792000000>;
clock-output-names = "dummy_qspi0";
#clock-cells = <0>;
u-boot,dm-pre-reloc;
};
dummy_uart_sclk: uart-sclk-clock {
compatible = "fixed-clock";
clock-frequency = <100000000>;
clock-output-names = "dummy_uart_sclk";
#clock-cells = <0>;
u-boot,dm-pre-reloc;
};
dummy_i2c_icclk: i2c-icclk-clock {
compatible = "fixed-clock";
clock-frequency = <50000000>;
clock-output-names = "dummy_i2c_icclk";
#clock-cells = <0>;
u-boot,dm-pre-reloc;
};
dummy_dpu_pixclk: dpu-pix-clock {
compatible = "fixed-clock";
clock-frequency = <74250000>;
clock-output-names = "dummy_dpu_pixclk";
#clock-cells = <0>;
u-boot,dm-pre-reloc;
};
dummy_dphy_refclk: dphy-ref-clock {
compatible = "fixed-clock";
clock-frequency = <24000000>;
clock-output-names = "dummy_dpu_refclk";
#clock-cells = <0>;
u-boot,dm-pre-reloc;
};
i2c0: i2c@ffe7f20000 {
compatible = "snps,designware-i2c";
reg = <0xff 0xe7f20000 0x0 0x4000>;
clocks = <&dummy_i2c_icclk>;
clock-frequency = <100000>;
#address-cells = <1>;
#size-cells = <0>;
usbc0: husb311_0@4e {
compatible = "hynetek,husb311";
int-n-gpios = <&gpio3_porta 10 1>;
reg = <0x4e>;
status = "okay";
usb_con0: connector {
compatible = "usb-c-connector";
label = "USB-C";
data-role = "dual";
power-role = "dual";
try-power-role = "sink";
source-pdos = <PDO_FIXED(5000, 2000, PDO_FIXED_USB_COMM)>;
sink-pdos =
<PDO_FIXED(5000, 2000, PDO_FIXED_USB_COMM)
PDO_FIXED(9000, 3000, PDO_FIXED_USB_COMM)
PDO_FIXED(12000, 3000, PDO_FIXED_USB_COMM)>;
op-sink-microwatt = <10000000>;
};
};
cw2015@62 {
clock-frequency = <100000>;
status = "okay";
compatible = "cellwise,cw2015";
reg = <0x62>;
cellwise,battery-profile = /bits/ 8
<0x17 0x67 0x66 0x65 0x64 0x63 0x61 0x5E
0x52 0x6D 0x4D 0x58 0x5B 0x51 0x44 0x3B
0x33 0x2C 0x26 0x23 0x24 0x29 0x34 0x42
0x49 0x16 0x0E 0xB8 0x3D 0x5D 0x68 0x7D
0x78 0x75 0x7B 0x7A 0x3F 0x18 0x82 0x48
0x09 0x4A 0x1A 0x47 0x86 0x93 0x97 0x15
0x49 0x71 0x9A 0xC3 0x80 0x41 0x4F 0xCB
0x2F 0x00 0x64 0xA5 0xB5 0x0D 0xB8 0x91>;
cellwise,monitor-interval-ms = <5000>;
cellwise,dual-cell = <1>;
};
bq25703: bq25703@6b {
status = "okay";
compatible = "ti,bq25703";
reg = <0x6b>;
typec0-enable-gpios = <&gpio3_porta 13 0>; //CHG_PATH_SEL0_180
typec1-enable-gpios = <&gpio3_porta 12 0>; //CHG_PATH_SEL1_180
ti,charge-current = <2500000>;
ti,max-input-voltage = <5000000>;
ti,input-current = <2000000>;
};
};
i2c1: i2c@ffe7f24000{
compatible = "snps,designware-i2c";
reg = <0xff 0xe7f24000 0x0 0x4000>;
clocks = <&dummy_i2c_icclk>;
clock-frequency = <100000>;
#address-cells = <1>;
#size-cells = <0>;
mcu_hc32fx:mcu-hc32fx@0x4c {
status = "okay";
compatible = "mcu_hc32fx";
reg = <0x4c>;
};
usbc1: husb311_1@4e {
compatible = "hynetek,husb311";
int-n-gpios = <&gpio1_porta 5 1>;
reg = <0x4e>;
status = "okay";
usb_con1: connector {
compatible = "usb-c-connector";
label = "USB-C";
data-role = "dual";
power-role = "dual";
try-power-role = "sink";
source-pdos = <PDO_FIXED(5000, 2000, PDO_FIXED_USB_COMM)>;
sink-pdos =
<PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
PDO_FIXED(9000, 3000, PDO_FIXED_USB_COMM)
PDO_FIXED(12000, 3000, PDO_FIXED_USB_COMM)>;
op-sink-microwatt = <10000000>;
};
};
};
i2c2: i2c@ffec00c000{
compatible = "snps,designware-i2c";
reg = <0xff 0xec00c000 0x0 0x4000>;
clocks = <&dummy_i2c_icclk>;
clock-frequency = <100000>;
#address-cells = <1>;
#size-cells = <0>;
};
i2c3: i2c@ffec014000{
compatible = "snps,designware-i2c";
reg = <0xff 0xec014000 0x0 0x4000>;
clocks = <&dummy_i2c_icclk>;
clock-frequency = <100000>;
#address-cells = <1>;
#size-cells = <0>;
};
i2c4: i2c@ffe7f28000{
compatible = "snps,designware-i2c";
reg = <0xff 0xe7f28000 0x0 0x4000>;
clocks = <&dummy_i2c_icclk>;
clock-frequency = <100000>;
#address-cells = <1>;
#size-cells = <0>;
pcal6408ahk_a: gpio@20 {
compatible = "nxp,pca9554";
reg = <0x20>;
gpio-controller;
#gpio-cells = <2>;
};
};
i2c5: i2c@fff7f2c000{
compatible = "snps,designware-i2c";
reg = <0xff 0xf7f2c000 0x0 0x4000>;
clocks = <&dummy_i2c_icclk>;
clock-frequency = <100000>;
#address-cells = <1>;
#size-cells = <0>;
};
serial@ffe7014000 {
compatible = "snps,dw-apb-uart";
reg = <0xff 0xe7014000 0x0 0x400>;
clocks = <&dummy_uart_sclk>;
clock-frequency = <100000000>;
clock-names = "baudclk";
reg-shift = <2>;
reg-io-width = <4>;
u-boot,dm-pre-reloc;
};
gmac0: ethernet@ffe7070000 {
compatible = "snps,dwmac";
reg = <0xff 0xe7070000 0x0 0x2000>;
clocks = <&dummy_apb>;
clock-names = "stmmaceth";
snps,pbl = <32>;
snps,fixed-burst;
phy-mode = "rgmii-id";
phy-handle = <&phy_88E1111_a>;
status = "disabled";
mdio0 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,dwmac-mdio";
phy_88E1111_a: ethernet-phy@1 {
reg = <0x1>;
};
phy_88E1111_b: ethernet-phy@2 {
reg = <0x2>;
};
};
};
gmac1: ethernet@ffe7060000 {
compatible = "snps,dwmac";
reg = <0xff 0xe7060000 0x0 0x2000>;
clocks = <&dummy_apb>;
clock-names = "stmmaceth";
snps,pbl = <32>;
snps,fixed-burst;
phy-mode = "rgmii-id";
phy-handle = <&phy_88E1111_b>;
status = "disabled";
};
emmc: sdhci@ffe7080000 {
compatible = "snps,dwcmshc-sdhci";
reg = <0xff 0xe7080000 0x0 0x10000>;
index = <0x0>;
clocks = <&dummy_ahb>;
clock-frequency = <198000000>;
clock-names = "core";
max-frequency = <198000000>;
sdhci-caps-mask = <0x0 0x1000000>;
mmc-hs400-1_8v;
non-removable;
no-sdio;
no-sd;
bus-width = <8>;
voltage= "1.8v";
pull_up;
io_fixed_1v8;
fifo-mode;
u-boot,dm-pre-reloc;
};
sdhci0: sd@ffe7090000 {
compatible = "snps,dwcmshc-sdhci";
reg = <0xff 0xe7090000 0x0 0x10000>;
index = <0x1>;
clocks = <&dummy_ahb>;
clock-frequency = <198000000>;
max-frequency = <198000000>;
sd-uhs-sdr104;
pull_up;
clock-names = "core";
bus-width = <4>;
voltage= "3.3v";
};
qspi0: spi@ffea000000 {
compatible = "snps,dw-apb-ssi-quad";
reg = <0xff 0xea000000 0x0 0x1000>;
clocks = <&dummy_qspi0>;
num-cs = <1>;
cs-gpio = <&gpio2_porta 3 0>; // GPIO_ACTIVE_HIGH: 0
spi-max-frequency = <100000000>;
#address-cells = <1>;
#size-cells =<0>;
spi-flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spi-nand";
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
reg = <0>;
};
};
qspi1: spi@fff8000000 {
compatible = "snps,dw-apb-ssi-quad";
reg = <0xff 0xf8000000 0x0 0x1000>;
clocks = <&dummy_spi>;
num-cs = <1>;
cs-gpio = <&gpio0_porta 1 0>; // GPIO_ACTIVE_HIGH: 0
spi-max-frequency = <66000000>;
#address-cells = <1>;
#size-cells =<0>;
spi-flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spi-nand";
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
reg = <0>;
};
};
spi0: spi@ffe700c000 {
compatible = "snps,dw-apb-ssi";
reg = <0xff 0xe700c000 0x0 0x1000>;
clocks = <&dummy_spi>;
cs-gpio = <&gpio2_porta 15 0>;
spi-max-frequency = <100000000>;
#address-cells = <1>;
#size-cells = <0>;
tpm@0{
compatible = "z32h330tc,z32h330tc-spi";
reg = <0>;
spi-max-frequency = <22000000>;
};
};
gpio2: gpio@ffe7f34000 {
compatible = "snps,dw-apb-gpio";
reg = <0xff 0xe7f34000 0x0 0x1000>;
clocks = <&dummy_apb>;
#address-cells = <1>;
#size-cells = <0>;
gpio2_porta: gpio-controller@0 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
snps,nr-gpios = <32>;
reg = <0>;
};
};
gpio3: gpio@ffe7f38000 {
compatible = "snps,dw-apb-gpio";
reg = <0xff 0xe7f38000 0x0 0x1000>;
clocks = <&dummy_apb>;
#address-cells = <1>;
#size-cells = <0>;
gpio3_porta: gpio-controller@0 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
snps,nr-gpios = <32>;
reg = <0>;
};
};
gpio0: gpio@ffec005000 {
compatible = "snps,dw-apb-gpio";
reg = <0xff 0xec005000 0x0 0x1000>;
clocks = <&dummy_apb>;
#address-cells = <1>;
#size-cells = <0>;
gpio0_porta: gpio-controller@0 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
snps,nr-gpios = <32>;
reg = <0>;
};
};
ao_gpio: gpio@fffff41000 {
compatible = "snps,dw-apb-gpio";
reg = <0xff 0xfff41000 0x0 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
ao_gpio_porta: ao_gpio-controller@0 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
nr-gpios-snps = <32>;
reg = <0>;
};
};
gpio1: gpio@ffec006000 {
compatible = "snps,dw-apb-gpio";
reg = <0xff 0xec006000 0x0 0x1000>;
clocks = <&dummy_apb>;
#address-cells = <1>;
#size-cells = <0>;
gpio1_porta: gpio-controller@0 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
snps,nr-gpios = <32>;
reg = <0>;
};
};
pwm: pwm@ffec01c000 {
compatible = "thead,pwm-light";
reg = <0xff 0xec01c000 0x0 0x4000>;
#pwm-cells = <2>;
};
dsi_regs: dsi-controller@ffef500000 {
compatible = "thead,light-dsi-regs", "syscon";
reg = <0xff 0xef500000 0x0 0x10000>;
status = "okay";
};
vosys_regs: vosys@ffef528000 {
compatible = "thead,light-vo-subsys", "syscon";
reg = <0xff 0xef528000 0x0 0x1000>;
status = "okay";
};
dpu: dc8200@ffef600000 {
compatible = "verisilicon,dc8200";
reg = <0xff 0xef600000 0x0 0x100>;
};
axiscr {
compatible = "thead,axiscr";
reg = <0xff 0xff004000 0x0 0x1000>;
lock-read = "okay";
lock-write = "okay";
#address-cells = <2>;
#size-cells = <2>;
u-boot,dm-pre-reloc;
axiscr0: axisrc@0 {
device_type = "axiscr";
region = <0x00 0x00000000 0x00 0x80000000>; // 4KB align
status = "disabled";
#address-cells = <2>;
#size-cells = <2>;
u-boot,dm-pre-reloc;
};
axiscr1: axisrc@1 {
device_type = "axiscr";
region = <0x00 0x80000000 0x00 0x80000000>; // 4KB align
status = "disabled";
#address-cells = <2>;
#size-cells = <2>;
u-boot,dm-pre-reloc;
};
axiscr2: axisrc@2 {
device_type = "axiscr";
region = <0x01 0x00000000 0x00 0x80000000>; // 4KB align
status = "disabled";
#address-cells = <2>;
#size-cells = <2>;
u-boot,dm-pre-reloc;
};
};
axiparity {
compatible = "thead,axiparity";
reg = <0xff 0xff00c000 0x0 0x1000>;
lock = "okay";
#address-cells = <2>;
#size-cells = <2>;
u-boot,dm-pre-reloc;
axiparity0: axiparity@0 {
device_type = "axiparity";
region = <0x00 0x00000000 0x01 0x0000000>; // 4KB align
status = "disabled";
#address-cells = <2>;
#size-cells = <2>;
u-boot,dm-pre-reloc;
};
axiparity1: axiparity@1 {
device_type = "axiparity";
region = <0x01 0x00000000 0x01 0x00000000>; // 4KB align
status = "disabled";
#address-cells = <2>;
#size-cells = <2>;
u-boot,dm-pre-reloc;
};
};
dsi_bridge: dsi-bridge {
compatible = "thead,light-dsi-bridge";
clocks = <&dummy_dpu_pixclk>;
clock-names = "pix-clk";
phys = <&dsi_dphy>;
phy-names = "dphy";
};
dsi_host: dsi-host {
compatible = "synopsys,dw-mipi-dsi";
regmap = <&dsi_regs>;
status = "okay";
};
dsi_dphy: dsi-dphy {
compatible = "synopsys,dw-dphy";
regmap = <&dsi_regs>;
vosys-regmap = <&vosys_regs>;
clocks = <&dummy_dpu_pixclk>, <&dummy_dphy_refclk>;
clock-names = "pix-clk", "ref-clk";
#phy-cells = <0>;
status = "okay";
};
lcd_backlight: pwm-backlight {
compatible = "pwm-backlight";
pwms = <&pwm 0 5000000>;
brightness-levels = <0 4 8 16 32 64 128 255>;
default-brightness-level = <7>;
};
ili9881c_panel {
status = "disabled";
compatible = "ilitek,ili9881c";
backlight = <&lcd_backlight>;
reset-gpios = <&gpio1_porta 5 1>; /* active low */
lcd-en-gpios = <&pcal6408ahk_a 2 0>; /* active high */
lcd-bias-en-gpios = <&pcal6408ahk_a 4 0>;/* active high */
};
aon {
compatible = "thead,light-aon";
status = "okay";
wakeup-by-gpio-on;
wakeup-by-rtc-on;
pd: light-aon-pd {
compatible = "thead,light-aon-pd";
#power-domain-cells = <1>;
};
light-regu-reg {
compatible = "thead,light-dialog-pmic";
status = "okay";
soc_dvdd18_aon_reg: soc_dvdd18_aon {
regulator-name = "soc_dvdd18_aon";
regulator-boot-on;
regulator-always-on;
};
soc_avdd33_usb3_reg: soc_avdd33_usb3 {
regulator-name = "soc_avdd33_usb3";
regulator-boot-on;
regulator-always-on;
};
soc_dvdd08_aon_reg: soc_dvdd08_aon {
regulator-name = "soc_dvdd08_aon";
regulator-boot-on;
regulator-always-on;
};
soc_apcpu_dvdd_dvddm_reg: soc_apcpu_dvdd_dvddm {
regulator-name = "soc_apcpu_dvdd_dvddm";
regulator-min-microvolt = <300000>;
regulator-max-microvolt = <1570000>;
regulator-boot-on;
regulator-always-on;
};
soc_dvdd08_ddr_reg: soc_dvdd08_ddr {
regulator-name = "soc_dvdd08_ddr";
regulator-boot-on;
regulator-always-on;
};
soc_vdd_ddr_1v8_reg: soc_vdd_ddr_1v8 {
regulator-name = "soc_vdd_ddr_1v8";
regulator-boot-on;
regulator-always-on;
};
soc_vdd_ddr_1v1_reg: soc_vdd_ddr_1v1 {
regulator-name = "soc_vdd_ddr_1v1";
regulator-boot-on;
regulator-always-on;
};
soc_vdd_ddr_0v6_reg: soc_vdd_ddr_0v6 {
regulator-name = "soc_vdd_ddr_0v6";
regulator-boot-on;
regulator-always-on;
};
soc_dvdd18_ap_reg: soc_dvdd18_ap {
regulator-name = "soc_dvdd18_ap";
regulator-boot-on;
regulator-always-on;
};
soc_dvdd08_ap_reg: soc_dvdd08_ap {
regulator-name = "soc_dvdd08_ap";
regulator-boot-on;
regulator-always-on;
};
soc_avdd08_mipi_hdmi_reg: soc_avdd08_mipi_hdmi {
regulator-name = "soc_avdd08_mipi_hdmi";
regulator-boot-on;
regulator-always-on;
};
soc_avdd18_mipi_hdmi_reg: soc_avdd18_mipi_hdmi {
regulator-name = "soc_avdd18_mipi_hdmi";
regulator-boot-on;
regulator-always-on;
};
soc_dvdd33_emmc_reg: soc_dvdd33_emmc {
regulator-name = "soc_dvdd33_emmc";
regulator-boot-on;
regulator-always-on;
};
soc_dvdd18_emmc_reg: soc_dvdd18_emmc {
regulator-name = "soc_vdd18_emmc";
regulator-boot-on;
regulator-always-on;
};
soc_dovdd18_scan_reg: soc_dovdd18_scan {
regulator-name = "soc_dovdd18_scan";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <3600000>;
};
soc_vext_2v8_reg: soc_vext_2v8 {
regulator-name = "soc_vext_2v8";
regulator-boot-on;
regulator-always-on;
};
soc_dvdd12_scan_reg: soc_dvdd12_scan {
regulator-name = "soc_dvdd12_scan";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <3600000>;
};
soc_avdd28_scan_en_reg: soc_avdd28_scan_en {
regulator-name = "soc_avdd28_scan_en";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
};
};
aon_pmic_config {
compatible = "thead,light-pmic-conf";
status = "okay";
#address-cells = <1>;
#size-cells = <0>;
iic-config = <0 0 2>;
pmic_dev_0: pmic-dev@0 {
pmic-name = "dialog,da9063,v1";
pmic-addr = <0x5a 0x5b>;
pmic_wdt_on;
status = "okay";
};
pmic_dev_1: pmic-dev@1 {
pmic-name = "dialog,da9121,v1";
pmic-addr = <0x68>;
status = "okay";
};
regu_config_0 {
reg_info = <&soc_dvdd18_aon_reg>;
status = "okay";
regu_id@0 {
pmic_dev = <&pmic_dev_0 DA9063_ID_LDO3>;
};
};
regu_config_1 {
reg_info = <&soc_avdd33_usb3_reg>;
status = "okay";
regu_id@0 {
pmic_dev = <&pmic_dev_0 DA9063_ID_LDO9>;
};
};
regu_config_2 {
reg_info = <&soc_dvdd08_aon_reg>;
status = "okay";
regu_id@0 {
pmic_dev = <&pmic_dev_0 DA9063_ID_LDO2>;
};
};
regu_config_3 {
reg_info = <&soc_apcpu_dvdd_dvddm_reg>;
status = "okay";
regu_id@0 {
pmic_dev = <&pmic_dev_0 DA9063_ID_BCORE1>;
auto_on_info = <0 0 800000>;
};
regu_id@1 {
pmic_dev = <&pmic_dev_0 DA9063_ID_BCORE2>;
auto_on_info = <1 0 800000>;
};
regu_id@2 {
pmic_dev = <&pmic_dev_0 DA9063_ID_BUCKIO>;
auto_on_info = <2 0 800000>;
};
coupling_info@0 {
negative-min;
info = <0 2 5 30>;
};
coupling_info@1 {
negative-min;
info = <1 2 5 30>;
};
};
regu_config_4 {
reg_info = <&soc_dvdd08_ddr_reg>;
status = "okay";
regu_id@0 {
pmic_dev = <&pmic_dev_0 DA9063_ID_BUCKPERI>;
};
};
regu_config_5 {
reg_info = <&soc_vdd_ddr_1v8_reg>;
status = "okay";
regu_id@0 {
pmic_dev = <&pmic_dev_0 DA9063_ID_LDO4>;
};
};
regu_config_6 {
reg_info = <&soc_vdd_ddr_1v1_reg>;
status = "okay";
regu_id@0 {
pmic_dev = <&pmic_dev_0 DA9063_ID_BUCKMEM>;
};
};
regu_config_7 {
reg_info = <&soc_vdd_ddr_0v6_reg>;
status = "okay";
regu_id@0 {
pmic_dev = <&pmic_dev_0 DA9063_ID_BUCKPRO>;
};
};
regu_config_8 {
reg_info = <&soc_dvdd18_ap_reg>;
status = "okay";
regu_id@0 {
pmic_dev = <&pmic_dev_0 DA9063_ID_LDO11>;
};
};
regu_config_9 {
reg_info = <&soc_dvdd08_ap_reg>;
status = "okay";
regu_id@0 {
pmic_dev = <&pmic_dev_1 DA9121_ID_BUCK1>;
parent_pmic_dev = <&pmic_dev_0 2 0>;
};
};
regu_config_10 {
reg_info = <&soc_avdd08_mipi_hdmi_reg>;
status = "okay";
regu_id@0 {
pmic_dev = <&pmic_dev_0 DA9063_ID_LDO1>;
};
};
regu_config_11 {
reg_info = <&soc_avdd18_mipi_hdmi_reg>;
status = "okay";
regu_id@0 {
pmic_dev = <&pmic_dev_0 DA9063_ID_LDO5>;
};
};
regu_config_12 {
reg_info = <&soc_dvdd33_emmc_reg>;
status = "okay";
regu_id@0 {
pmic_dev = <&pmic_dev_0 DA9063_ID_LDO10>;
};
};
regu_config_13 {
reg_info = <&soc_dvdd18_emmc_reg>;
status = "okay";
regu_id@0 {
pmic_dev = <&pmic_dev_0 DA9063_ID_GPIO7>;
parent_pmic_dev = <&pmic_dev_0 7 0>;
};
};
regu_config_14 {
reg_info = <&soc_dovdd18_scan_reg>;
status = "okay";
regu_id@0 {
pmic_dev = <&pmic_dev_0 DA9063_ID_LDO6>;
auto_on_info = <2 1 1800000>;
auto_off_info = <7 1>;
};
};
regu_config_15 {
reg_info = <&soc_vext_2v8_reg>;
status = "okay";
regu_id@0 {
pmic_dev = <&pmic_dev_0 DA9063_ID_LDO7>;
auto_on_info = <3 1 2800000>;
auto_off_info = <8 1>;
};
};
regu_config_16 {
reg_info = <&soc_dvdd12_scan_reg>;
status = "okay";
regu_id@0 {
pmic_dev = <&pmic_dev_0 DA9063_ID_LDO8>;
auto_on_info = <4 1 1200000>;
auto_off_info = <9 1>;
};
};
regu_config_17 {
reg_info = <&soc_avdd28_scan_en_reg>;
status = "okay";
regu_id@0 {
pmic_dev = <&pmic_dev_0 DA9063_ID_GPIO4>;
};
};
};
};
};
chosen {
bootargs = "console=ttyS0,115200";
stdout-path = "/soc/serial@ffe7014000:115200";
};
};

4
arch/riscv/include/asm/arch-thead/boot_mode.h
View File

@@ -34,7 +34,9 @@ typedef enum image_type {
T_ROOTFS = 4,
T_TF = 2,
T_TEE = 5,
T_UBOOT = 6
T_UBOOT = 6,
T_USER = 7,
T_SBMETA = 8,
} img_type_t;
static const char header_magic[4] = {'T', 'H', 'E', 'D'};

17
arch/riscv/include/asm/arch-thead/light-reset.h Normal file
View File

@@ -0,0 +1,17 @@
#ifndef __LIGHT_RESET_H__
#define __LIGHT_RESET_H__
#define APSYS_RSTGEN_BASE 0xFFEF014000
#define REG_C910_SWRST (APSYS_RSTGEN_BASE + 0x4)
#define APSYS_REG_BASE 0xFFEF018000
#define REG_C910_CORE0_RVBA_L (APSYS_REG_BASE + 0x50)
#define REG_C910_CORE0_RVBA_H (APSYS_REG_BASE + 0x54)
#define REG_C910_CORE1_RVBA_L (APSYS_REG_BASE + 0x58)
#define REG_C910_CORE1_RVBA_H (APSYS_REG_BASE + 0x5C)
#define REG_C910_CORE2_RVBA_L (APSYS_REG_BASE + 0x60)
#define REG_C910_CORE2_RVBA_H (APSYS_REG_BASE + 0x64)
#define REG_C910_CORE3_RVBA_L (APSYS_REG_BASE + 0x68)
#define REG_C910_CORE3_RVBA_H (APSYS_REG_BASE + 0x6C)
#define REG_PLIC_DELEGATE 0xffd81ffffc
#endif /* __LIGHT_RESET_H__ */

53
arch/riscv/include/asm/atomic.h Normal file
View File

@@ -0,0 +1,53 @@
#ifndef _ASM_RISCV_ATOMIC_H
#define _ASM_RISCV_ATOMIC_H
#include <linux/types.h>
#include <asm/barrier.h>
typedef struct {
volatile long counter;
} atomic_t;
#define ATOMIC_INIT(_lptr, val) (_lptr)->counter = (val)
#define ATOMIC_INITIALIZER(val) \
{ \
.counter = (val), \
}
long atomic_read(atomic_t *atom)
{
long ret = atom->counter;
rmb();
return ret;
}
void atomic_write(atomic_t *atom, long value)
{
atom->counter = value;
wmb();
}
long atomic_add_return(atomic_t *atom, long value)
{
long ret;
#if __SIZEOF_LONG__ == 4
__asm__ __volatile__(" amoadd.w.aqrl %1, %2, %0"
: "+A"(atom->counter), "=r"(ret)
: "r"(value)
: "memory");
#elif __SIZEOF_LONG__ == 8
__asm__ __volatile__(" amoadd.d.aqrl %1, %2, %0"
: "+A"(atom->counter), "=r"(ret)
: "r"(value)
: "memory");
#endif
return ret + value;
}
long atomic_sub_return(atomic_t *atom, long value)
{
return atomic_add_return(atom, -value);
}
#endif /* _ASM_RISCV_ATOMIC_H */

12
arch/riscv/include/asm/csr.h
View File

@@ -104,15 +104,23 @@
#define CSR_CYCLEH 0xc80
#define CSR_TIMEH 0xc81
#define CSR_INSTRETH 0xc82
#define CSR_MVENDORID 0xf11
#define CSR_MARCHID 0xf12
#define CSR_MIMPID 0xf13
#define CSR_MHARTID 0xf14
#define CSR_MCPUID 0xfc0
#define CSR_SMPEN 0x7f3
#define CSR_MTEE 0x7f4
#define CSR_SMPEN 0x7f3
#define CSR_MTEE 0x7f4
#define CSR_MCOR 0x7c2
#define CSR_MHCR 0x7c1
#define CSR_MCCR2 0x7c3
#define CSR_MHINT 0x7c5
#define CSR_MHINT2 0x7cc
#define CSR_MHINT3 0x7cd
#define CSR_MHINT4 0x7ce
#define CSR_MXSTATUS 0x7c0
#define CSR_MSMPR 0x7f3
#define CSR_PLIC_BASE 0xfc1
#define sync_is() asm volatile (".long 0x01b0000b")

87
arch/riscv/lib/bootm.c
View File

@@ -14,7 +14,11 @@
#include <opensbi.h>
#include <asm/byteorder.h>
#include <asm/csr.h>
#include <asm/io.h>
#include <asm/smp.h>
#include <asm/barrier.h>
#include <asm/atomic.h>
#include <asm/arch-thead/light-reset.h>
#include <dm/device.h>
#include <dm/root.h>
#include <u-boot/zlib.h>
@@ -22,6 +26,12 @@
DECLARE_GLOBAL_DATA_PTR;
static struct fw_dynamic_info opensbi_info;
static atomic_t _harts_count = ATOMIC_INITIALIZER(3);
static ulong _load_start;
static ulong _dtb_addr;
static ulong _dyn_info_addr;
extern void secondary_entry();
__weak void board_quiesce_devices(void)
{
@@ -81,6 +91,58 @@ static void boot_prep_linux(bootm_headers_t *images)
}
}
void next_stage(void)
{
void (*next_entry)(unsigned long arg0,unsigned long arg1,unsigned long arg2);
next_entry = (void (*))(_load_start);
ulong hartid = csr_read(CSR_MHARTID);
atomic_sub_return(&_harts_count, 1);
/*
* set $a0 = hartid
* set $a1 = $dtb_addr
* set $a2 = $dyn_info_addr
*/
next_entry(hartid, _dtb_addr , _dyn_info_addr);
}
bool has_reset_sample(ulong dtb_addr)
{
int node_offset;
node_offset = fdt_path_offset(dtb_addr, "/soc/reset-sample");
if (node_offset < 0) {
printf("## fdt has no reset_sample\n");
return false;
} else {
printf("## fdt has reset_sample\n");
return true;
}
}
static void reset_sample(void)
{
ulong addr;
uint addr_l, addr_h;
// RESET ADDR
addr = (unsigned long)(void *)secondary_entry;
addr_h = (uint)(addr >> 32);
addr_l = (uint)(addr & 0xFFFFFFFF);
// writel(addr_h, (volatile void *)REG_C910_CORE0_RVBA_H);
// writel(addr_l, (volatile void *)REG_C910_CORE0_RVBA_L);
writel(addr_h, (volatile void *)REG_C910_CORE1_RVBA_H);
writel(addr_l, (volatile void *)REG_C910_CORE1_RVBA_L);
writel(addr_h, (volatile void *)REG_C910_CORE2_RVBA_H);
writel(addr_l, (volatile void *)REG_C910_CORE2_RVBA_L);
writel(addr_h, (volatile void *)REG_C910_CORE3_RVBA_H);
writel(addr_l, (volatile void *)REG_C910_CORE3_RVBA_L);
// RESET
writel(0x1F, (volatile void *)REG_C910_SWRST);
writel(0x1, (volatile void *)REG_PLIC_DELEGATE);
}
static void boot_jump_linux(bootm_headers_t *images, int flag)
{
void (*kernel)(ulong hart, void *dtb, struct fw_dynamic_info *p);
@@ -98,12 +160,25 @@ static void boot_jump_linux(bootm_headers_t *images, int flag)
announce_and_cleanup(fake);
opensbi_info.magic = FW_DYNAMIC_INFO_MAGIC_VALUE;
opensbi_info.version = 0x1;
opensbi_info.next_addr = images->os.start;
opensbi_info.next_mode = FW_DYNAMIC_INFO_NEXT_MODE_S;
opensbi_info.options = 0;
opensbi_info.boot_hart = 0;
_load_start = kernel;
_dtb_addr = images->ft_addr;
_dyn_info_addr = (ulong)&opensbi_info;
if (!has_reset_sample(_dtb_addr)) {
opensbi_info.magic = FW_DYNAMIC_INFO_MAGIC_VALUE;
opensbi_info.version = 0x2;
opensbi_info.next_addr = images->os.start;
opensbi_info.next_mode = FW_DYNAMIC_INFO_NEXT_MODE_S;
opensbi_info.options = 0;
opensbi_info.boot_hart = 0;
reset_sample();
} else {
opensbi_info.magic = FW_DYNAMIC_INFO_MAGIC_VALUE;
opensbi_info.version = 0x1;
opensbi_info.next_addr = images->os.start;
opensbi_info.next_mode = FW_DYNAMIC_INFO_NEXT_MODE_S;
opensbi_info.options = 0;
opensbi_info.boot_hart = 0;
}
if (!fake) {
if (IMAGE_ENABLE_OF_LIBFDT && images->ft_len) {

26
board/thead/light-c910/Kconfig
View File

@@ -66,6 +66,10 @@ config LIGHT_ANDROID_BOOT_IMAGE_VAL_LPI4A
bool "light board-lpi4a android image"
default n
config LIGHT_ANDROID_BOOT_IMAGE_ANT_REF
bool "light board ant ref android image"
default n
config LIGHT_SEC_BOOT_WITH_VERIFY_VAL_A
bool "light board-a security boot with verification"
default n
@@ -82,6 +86,10 @@ config LIGHT_SEC_BOOT_WITH_VERIFY_LPI4A
bool "light lpi4a security boot with verification"
default n
config LIGHT_SEC_BOOT_WITH_VERIFY_RVBOOK
bool "light lpi4a security boot with verification"
default n
config TARGET_LIGHT_FPGA_FM_C910
bool "light fullmask FPGA board"
default n
@@ -122,6 +130,10 @@ config TARGET_LIGHT_FM_C910_LPI4A
bool "light fullmask for Lichee Pi 4A board "
default n
config TARGET_LIGHT_FM_C910_RVBOOK
bool "light fullmask for RVBOOK board "
default n
config TARGET_LIGHT_FM_C910_B_POWER
bool "light fullmask for light-b-power board "
default n
@@ -132,8 +144,7 @@ config SYS_TEXT_BASE
config SPL_TEXT_BASE
hex
default 0xffe0000800 if LIGHT_SEC_BOOT_WITH_VERIFY_VAL_A || LIGHT_SEC_BOOT_WITH_VERIFY_VAL_B || LIGHT_SEC_BOOT_WITH_VERIFY_ANT_REF || LIGHT_SEC_BOOT_WITH_VERIFY_LPI4A
default 0xffe0000000 if !(LIGHT_SEC_BOOT_WITH_VERIFY_VAL_A || LIGHT_SEC_BOOT_WITH_VERIFY_VAL_B || LIGHT_SEC_BOOT_WITH_VERIFY_ANT_REF || LIGHT_SEC_BOOT_WITH_VERIFY_LPI4A)
default 0xffe0000800
config SPL_MAX_SIZE
hex
@@ -244,6 +255,17 @@ config DDR_LP4_2133_SINGLERANK
help
Enabling this will support lpddr4 2133 singlerank configuration.
config DDR_DDP
bool "LPDDR4/4X Dual Die Package support"
help
Enabling this will support ddr Dual Die Package configuration.
e.g. to support 8GB ddr device with 17-bit row address (16:0)
config FIXUP_MEMORY_REGION
bool "self-adapt to query and fixup memory region"
help
Enabling this will support self-adapt to query and fixup memory region
config DDR_H32_MODE
bool "LPDDR4/4X 32bit mode configuration"
help

7
board/thead/light-c910/Makefile
View File

@@ -7,6 +7,10 @@ DDR_SRC_PATH=lpddr4/src
DDR_REGU_SRC=lpddr-regu
DDR_FW_PATH=$(DDR_SRC_PATH)/ddr_phy_fw
ifdef CONFIG_RV_BOOK
obj-y += sys_clk.o
endif
ifdef CONFIG_SPL_BUILD
obj-y += spl.o
obj-y += sys_clk.o
@@ -23,6 +27,7 @@ obj-$(CONFIG_LPDDR) += $(DDR_SRC_PATH)/init_ddr.o
obj-$(CONFIG_LPDDR) += $(DDR_SRC_PATH)/pinmux.o
obj-$(CONFIG_LPDDR) += $(DDR_SRC_PATH)/waitfwdone.o
obj-$(CONFIG_LPDDR) += $(DDR_SRC_PATH)/ddr_common_func.o
obj-$(CONFIG_LPDDR) += $(DDR_SRC_PATH)/ddr_retention.o
obj-$(CONFIG_LPDDR) += $(DDR_SRC_PATH)/common_lib.o
obj-$(CONFIG_LPDDR) += $(DDR_SRC_PATH)/lpddr4_init.o
ifdef CONFIG_DDR_DBI_OFF
@@ -60,8 +65,10 @@ obj-$(CONFIG_THEAD_LIGHT_DIGITAL_SENSOR) += digital_sensor.o digital_sensor_test
obj-y += clock_config.o
obj-y += sec_check.o
obj-y += boot.o
obj-y += sbmeta/sbmeta.o
ifndef CONFIG_TARGET_LIGHT_FPGA_FM_C910
obj-$(CONFIG_LPDDR) += $(DDR_SRC_PATH)/ddr_common_func.o
obj-$(CONFIG_LPDDR) += $(DDR_SRC_PATH)/ddr_retention.o
obj-$(CONFIG_LPDDR) += $(DDR_SRC_PATH)/common_lib.o
endif

203
board/thead/light-c910/board.c
View File

@@ -8,11 +8,24 @@
#include <asm/io.h>
#include <dwc3-uboot.h>
#include <usb.h>
#include <usb/xhci.h>
#include <cpu_func.h>
#include <abuf.h>
#include "sec_library.h"
#ifdef CONFIG_LIGHT_AON_CONF
#include "../../../drivers/misc/light_regu.h"
#include "dm/device.h"
#include "dm/uclass.h"
#endif
#ifdef CONFIG_USB_DWC3
static struct dwc3_device dwc3_device_data = {
#ifdef CONFIG_RV_BOOK
.maximum_speed = USB_SPEED_HIGH,
#else
.maximum_speed = USB_SPEED_SUPER,
#endif
.dr_mode = USB_DR_MODE_PERIPHERAL,
.index = 0,
};
@@ -26,6 +39,13 @@ int usb_gadget_handle_interrupts(int index)
int board_usb_init(int index, enum usb_init_type init)
{
dwc3_device_data.base = 0xFFE7040000UL;
if (init == USB_INIT_DEVICE) {
dwc3_device_data.dr_mode = USB_DR_MODE_PERIPHERAL;
} else {
dwc3_device_data.dr_mode = USB_DR_MODE_HOST;
}
return dwc3_uboot_init(&dwc3_device_data);
}
@@ -35,6 +55,28 @@ int board_usb_cleanup(int index, enum usb_init_type init)
return 0;
}
int xhci_hcd_init(int index, struct xhci_hccr **hccr, struct xhci_hcor **hcor)
{
int ret = board_usb_init(index, USB_INIT_HOST);
if (ret != 0) {
puts("Failed to initialize board for USB\n");
return ret;
}
*hccr = (struct xhci_hccr *)dwc3_device_data.base;
*hcor = (struct xhci_hcor *)(dwc3_device_data.base +
HC_LENGTH(xhci_readl(&(*hccr)->cr_capbase)));;
return ret;
}
void xhci_hcd_stop(int index)
{
board_usb_cleanup(index, USB_INIT_HOST);
}
int g_dnl_board_usb_cable_connected(void)
{
return 1;
@@ -42,17 +84,24 @@ int g_dnl_board_usb_cable_connected(void)
#endif
#ifdef CONFIG_CMD_BOOT_SLAVE
#ifdef CONFIG_LIGHT_AON_CONF
#define E902_AON_CONFIG_SIZE 0xC00
#else
#define E902_AON_CONFIG_SIZE 0x000
#endif
#define E902_SYSREG_START 0xfffff48044
#define E902_SYSREG_RESET 0xfffff44024
#define E902_START_ADDRESS 0xFFEF8000
#define E902_START_ADDRESS (0xFFEF8000 + E902_AON_CONFIG_SIZE)
#define C910_E902_START_ADDRESS 0xFFFFEF8000
#define E902_IOPMP_BASE 0xFFFFC21000
#define C906_RST_ADDR_L 0xfffff48048
#define C906_RST_ADDR_H 0xfffff4804C
#define C906_START_ADDRESS_L 0x32000000
#define C906_START_ADDRESS_H 0x00
#define C910_C906_START_ADDRESS 0x0032000000
#define C906_CPR_IPCG_ADDRESS 0xFFCB000010
#define C906_IOCTL_GPIO_SEL_ADDRESS 0xFFCB01D000
#define C906_IOCTL_AF_SELH_ADDRESS 0xFFCB01D008
@@ -82,32 +131,164 @@ void set_c906_cpu_entry(phys_addr_t entry_h, phys_addr_t entry_l)
void boot_audio(void)
{
writel(0x37, (volatile void *)C906_RESET_REG);
writel(0x37, (volatile void *)C906_RESET_REG);
set_c906_cpu_entry(C906_START_ADDRESS_H, C906_START_ADDRESS_L);
flush_cache((uintptr_t)C910_C906_START_ADDRESS, 0x20000);
set_c906_cpu_entry(C906_START_ADDRESS_H, C906_START_ADDRESS_L);
flush_cache((uintptr_t)C910_C906_START_ADDRESS, 0x20000);
writel(0x7ffff1f, (volatile void *)C906_CPR_IPCG_ADDRESS);
writel((1<<23) | (1<<24), (volatile void *)C906_IOCTL_GPIO_SEL_ADDRESS);
writel(0, (volatile void *)C906_IOCTL_AF_SELH_ADDRESS);
writel(0x7ffff1f, (volatile void *)C906_CPR_IPCG_ADDRESS);
writel((1<<23) | (1<<24), (volatile void *)C906_IOCTL_GPIO_SEL_ADDRESS);
writel(0, (volatile void *)C906_IOCTL_AF_SELH_ADDRESS);
writel(0x3f, (volatile void *)C906_RESET_REG);
writel(0x3f, (volatile void *)C906_RESET_REG);
}
void boot_aon(void)
#ifdef CONFIG_LIGHT_AON_CONF
int get_and_set_aon_config_data(void)
{
int ret =0;
struct udevice *dev;
struct mic_regu_platdata *config_data =NULL;
ret = uclass_first_device_err(UCLASS_MISC, &dev);
if(ret){
printf("get light aon config faild %d\n", ret);
return ret;
}
config_data = (struct mic_regu_platdata *)(dev->platdata);
volatile aon_config_t* read_config = (aon_config_t* )C910_E902_START_ADDRESS;
if(strncmp((const char*)read_config->magic , AON_CONFIG_MAGIC, strlen(AON_CONFIG_MAGIC))) {
printf("No aon config magic found in aon bin, please check the aon bin\n");
return -1;
}
if(strncmp((const char*)read_config->version, AON_CONFIG_VERSION, strlen(AON_CONFIG_VERSION))) {
printf("Err aon config version, aon bin is:%s, u-boot is:%s\n", read_config->version, AON_CONFIG_VERSION);
return -1;
}
if(PMIC_MAX_HW_ID_NUM > read_config->max_hw_id_num) {
printf("Invald max hw id num, aon bin support %d , u-boot is %d\n",read_config->max_hw_id_num, PMIC_MAX_HW_ID_NUM);
return -1;
}
/*set pmic dev info */
int pmic_dev_num = config_data->pmic_list.pmic_num;
int pmic_dev_list_offset = sizeof(aon_config_t);
uint64_t pmic_dev_start_addr = C910_E902_START_ADDRESS + pmic_dev_list_offset;
int regu_num = config_data->regu_id_list.regu_id_num;
int regu_id_list_offset = pmic_dev_list_offset + pmic_dev_num * sizeof(pmic_dev_info_t);
uint64_t regu_start_addr = C910_E902_START_ADDRESS + regu_id_list_offset;
int aon_bin_size = regu_id_list_offset + regu_num* sizeof(csi_regu_id_t);
if( aon_bin_size > read_config->aon_config_partition_size) {
printf("Invalid aon partition size, aon bin support:%lld, u-boot is %d\n", read_config->aon_config_partition_size, aon_bin_size);
return -1;
}
printf("pmic_dev_num:%d offset:%d addr:%lld\n",pmic_dev_num, pmic_dev_list_offset, pmic_dev_start_addr);
memcpy((void*)pmic_dev_start_addr, config_data->pmic_list.pmic_list, pmic_dev_num * sizeof(pmic_dev_info_t));
printf("regu_num:%d offset:%d addr:%lld\n",regu_num,regu_id_list_offset, regu_start_addr);
memcpy((void*)regu_start_addr, config_data->regu_id_list.regu_id_list, regu_num * sizeof(csi_regu_id_t));
read_config->wakeup_flag = config_data->wakeup_flag;
read_config->aon_pmic.iic_config.iic_id = config_data->iic_config.iic_id;
read_config->aon_pmic.iic_config.addr_mode = config_data->iic_config.addr_mode;
read_config->aon_pmic.iic_config.speed = config_data->iic_config.speed;
read_config->aon_pmic.pmic_dev_num = pmic_dev_num;
read_config->aon_pmic.pmic_dev_list_offset = pmic_dev_list_offset;
/*set regu list info*/
read_config->aon_pmic.regu_num = regu_num;
read_config->aon_pmic.regu_id_list_offset = regu_id_list_offset;
memcpy((void*)read_config->uboot_set_magic, UBOOT_CONFIG_MAGIC, strlen(UBOOT_CONFIG_MAGIC));
flush_cache((uintptr_t)C910_E902_START_ADDRESS, aon_bin_size);
printf("-->pmic_dev_num:%d offset:%d\n",read_config->aon_pmic.pmic_dev_num, read_config->aon_pmic.pmic_dev_list_offset);
printf("-->regu_num:%d offset:%d\n",read_config->aon_pmic.regu_num,read_config->aon_pmic.regu_id_list_offset);
return 0;
}
#endif
int do_boot_aon(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
{
#ifdef CONFIG_LIGHT_AON_CONF
int ret = 0;
ret = get_and_set_aon_config_data();
if(ret) {
printf("aon config and set faild %d", ret);
hang();
return ret;
}
#endif
writel(0xffffffff, (void *)(E902_IOPMP_BASE + 0xc0));
disable_slave_cpu();
set_slave_cpu_entry(E902_START_ADDRESS);
flush_cache((uintptr_t)C910_E902_START_ADDRESS, 0x10000);
enable_slave_cpu();
return 0;
}
U_BOOT_CMD(
bootaon, CONFIG_SYS_MAXARGS, 0, do_boot_aon,
"Boot aon from memory ",
" "
);
int do_bootslave(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
{
boot_aon();
mdelay(100);
boot_audio();
return 0;
}
#endif
#ifdef CONFIG_BOARD_RNG_SEED
const char pre_gen_seed[128] = {211, 134, 226, 116, 1, 13, 224, 196, 88, 213, 188, 219, 128, 41, 231, 228, 129, 123, 173, 234, 219, 79, 152, 154, 169, 27, 183, 166, 52, 21, 118, 7, 155, 89, 124, 156, 102, 92, 96, 190, 49, 28, 154, 177, 69, 129, 149, 199, 253, 66, 177, 216, 146, 73, 114, 59, 100, 41, 225, 152, 62, 88, 160, 217, 177, 28, 117, 23, 120, 213, 213, 169, 242, 111, 90, 55, 241, 239, 254, 238, 50, 175, 198, 196, 248, 56, 255, 92, 97, 224, 245, 160, 56, 149, 121, 233, 177, 239, 0, 41, 196, 214, 210, 182, 69, 44, 238, 54, 27, 236, 36, 77, 156, 234, 17, 148, 34, 16, 241, 132, 241, 230, 36, 41, 123, 157, 19, 44};
/* Use hardware rng to seed Linux random. */
int board_rng_seed(struct abuf *buf)
{
size_t len = 128;
uint8_t *data = NULL;
int sc_err = SC_FAIL;
/* abuf is working up in asynchronization mode, so the memory usage for random data storage must
be allocated first. */
data = malloc(len);
if (!data) {
printf("Fail to allocate memory, using pre-defined entropy\n");
return -1;
}
#if defined(CONFIG_AVB_HW_ENGINE_ENABLE)
/* We still use pre-define entropy data in case hardware random engine does not work */
sc_err = csi_sec_library_init();
if (sc_err != SC_OK) {
printf("Fail to initialize sec library, using pre-defined entropy\n");
goto _err;
}
sc_err = sc_rng_get_random_bytes(data, len);
if (sc_err != SC_OK) {
printf("Fail to retrieve random data, using pre-defined entropy\n");
goto _err;
}
abuf_init_set(buf, data, len);
return 0;
_err:
#endif
/* use pre-defined random data in case of the random engine is disable */
memcpy(data, pre_gen_seed, len);
abuf_init_set(buf, data, len);
return 0;
}
#endif

724
board/thead/light-c910/boot.c
View File

@@ -15,6 +15,7 @@
#include "../../../lib/sec_library/include/sec_crypto_sha.h"
#include "../../../lib/sec_library/include/kdf.h"
#include "../../../lib/sec_library/include/sec_crypto_mac.h"
#include "fastboot.h"
#if CONFIG_IS_ENABLED(LIGHT_SEC_UPGRADE)
@@ -24,6 +25,14 @@
/* The macro is used to enable uboot version in efuse */
#define LIGHT_UBOOT_VERSION_IN_ENV 1
/* The macro is used to enable secimg version in env */
#define LIGHT_SECIMG_VERSION_IN_ENV 1
/* vimage return value */
#define VIMAGE_UPGRADE_NOT_REQUIRED 1
#define VIMAGE_BREAK_VERSION_RULE_ERROR 2
#define VIMAGE_SIGNATRE_VERIFICATION_FAILED 3
/* The macro is used to enble RPMB ACCESS KEY from KDF */
//#define LIGHT_KDF_RPMB_KEY 1
@@ -31,14 +40,15 @@
//#define LIGHT_IMG_VERSION_CHECK_IN_BOOT 1
/* the sample rpmb key is only used for testing */
#ifndef LIGHT_KDF_RPMB_KEY
#ifndef LIGHT_KDF_RPMB_KEY
static const unsigned char emmc_rpmb_key_sample[32] = {0x33, 0x22, 0x11, 0x00, 0x77, 0x66, 0x55, 0x44, \
0xbb, 0xaa, 0x99, 0x88, 0xff, 0xee, 0xdd, 0xcc, \
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, \
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
#endif
static unsigned int upgrade_image_version = 0;
static char *current_slot = "a";
static char *update_slot = "b";
#define RPMB_EMMC_CID_SIZE 16
#define RPMB_CID_PRV_OFFSET 9
#define RPMB_CID_CRC_OFFSET 15
@@ -46,8 +56,8 @@ static unsigned int upgrade_image_version = 0;
static int tee_rpmb_key_gen(uint8_t* key, uint32_t * length)
{
uint32_t data[RPMB_EMMC_CID_SIZE / 4];
uint8_t huk[32];
uint32_t huk_len;
uint8_t huk[32];
uint32_t huk_len;
struct mmc *mmc = find_mmc_device(0);
int i;
sc_mac_t mac_handle;
@@ -72,14 +82,14 @@ static int tee_rpmb_key_gen(uint8_t* key, uint32_t * length)
memset((void *)((uint64_t)data + RPMB_CID_PRV_OFFSET), 0, 1);
memset((void *)((uint64_t)data + RPMB_CID_CRC_OFFSET), 0, 1);
/* Step1: Derive HUK from KDF function */
/* Step1: Derive HUK from KDF function */
ret = csi_kdf_gen_hmac_key(huk, &huk_len);
if (ret) {
printf("kdf gen hmac key faild[%d]\r\n", ret);
return -1;
}
/* Step2: Using HUK and data to generate RPMB key */
/* Step2: Using HUK and data to generate RPMB key */
ret = sc_mac_init(&mac_handle, 0);
if (ret) {
printf("mac init faild[%d]\r\n", ret);
@@ -110,7 +120,7 @@ func_exit:
}
#endif
int csi_rpmb_write_access_key(void)
int csi_rpmb_write_access_key(void)
{
#ifdef LIGHT_KDF_RPMB_KEY
unsigned long *temp_rpmb_key_addr = NULL;
@@ -152,22 +162,25 @@ int csi_rpmb_write_access_key(void)
int csi_tf_get_image_version(unsigned int *ver)
{
int ret = 0;
#if !LIGHT_SECIMG_VERSION_IN_ENV
char runcmd[64] = {0};
unsigned char blkdata[256];
int ret = 0;
/* tf version reside in RPMB block#0, offset#16*/
sprintf(runcmd, "mmc rpmb read 0x%lx 0 1", (unsigned long)blkdata);
ret = run_command(runcmd, 0);
if (ret == 0) {
*ver = (blkdata[16] << 8) + blkdata[17];
}
#else
*ver = env_get_hex("tf_version", 0);
#endif
return ret;
}
int csi_tf_set_image_version(unsigned int ver)
{
#if !LIGHT_SECIMG_VERSION_IN_ENV
char runcmd[64] = {0};
unsigned char blkdata[256];
unsigned long *temp_rpmb_key_addr = NULL;
@@ -179,9 +192,9 @@ int csi_tf_set_image_version(unsigned int ver)
blkdata[17] = ver & 0xFF;
/* tf version reside in RPMB block#0, offset#16*/
#ifndef LIGHT_KDF_RPMB_KEY
#ifndef LIGHT_KDF_RPMB_KEY
temp_rpmb_key_addr = (unsigned long *)emmc_rpmb_key_sample;
#else
#else
uint8_t kdf_rpmb_key[32];
uint32_t kdf_rpmb_key_length = 0;
int ret = 0;
@@ -194,7 +207,9 @@ int csi_tf_set_image_version(unsigned int ver)
sprintf(runcmd, "mmc rpmb write 0x%lx 0 1 0x%lx", (unsigned long)blkdata, (unsigned long)temp_rpmb_key_addr);
run_command(runcmd, 0);
#else
env_set_hex("tf_version", ver);
#endif
return 0;
}
@@ -205,17 +220,19 @@ int csi_tf_set_upgrade_version(void)
int csi_tee_get_image_version(unsigned int *ver)
{
int ret = 0;
#if !LIGHT_SECIMG_VERSION_IN_ENV
char runcmd[64] = {0};
unsigned char blkdata[256];
int ret = 0;
/* tf version reside in RPMB block#0, offset#0*/
sprintf(runcmd, "mmc rpmb read 0x%lx 0 1", (unsigned long)blkdata);
ret = run_command(runcmd, 0);
if (ret == 0) {
*ver = (blkdata[0] << 8) + blkdata[1];
}
#else
*ver = env_get_hex("tee_version", 0);
#endif
return ret;
}
@@ -234,6 +251,7 @@ int csi_kernel_get_image_version(unsigned int *ver)
int csi_tee_set_image_version(unsigned int ver)
{
#if !LIGHT_SECIMG_VERSION_IN_ENV
char runcmd[64] = {0};
unsigned char blkdata[256];
unsigned long *temp_rpmb_key_addr = NULL;
@@ -245,9 +263,9 @@ int csi_tee_set_image_version(unsigned int ver)
blkdata[1] = ver & 0xFF;
/* tf version reside in RPMB block#0, offset#16*/
#ifndef LIGHT_KDF_RPMB_KEY
#ifndef LIGHT_KDF_RPMB_KEY
temp_rpmb_key_addr = (unsigned long *)emmc_rpmb_key_sample;
#else
#else
uint8_t kdf_rpmb_key[32];
uint32_t kdf_rpmb_key_length = 0;
int ret = 0;
@@ -259,7 +277,9 @@ int csi_tee_set_image_version(unsigned int ver)
#endif
sprintf(runcmd, "mmc rpmb write 0x%lx 0 1 0x%lx", (unsigned long)blkdata, (unsigned long)temp_rpmb_key_addr);
run_command(runcmd, 0);
#else
env_set_hex("tee_version", ver);
#endif
return 0;
}
@@ -268,6 +288,62 @@ int csi_tee_set_upgrade_version(void)
return csi_tee_set_image_version(upgrade_image_version);
}
int csi_sbmeta_get_image_version(unsigned int *ver)
{
int ret = 0;
#if !LIGHT_SECIMG_VERSION_IN_ENV
char runcmd[64] = {0};
unsigned char blkdata[256];
/* sbmeta version reside in RPMB block#0, offset#48*/
sprintf(runcmd, "mmc rpmb read 0x%lx 0 1", (unsigned long)blkdata);
ret = run_command(runcmd, 0);
if (ret == 0) {
*ver = (blkdata[48] << 8) + blkdata[49];
}
#else
*ver = env_get_hex("sbmeta_version", 0);
#endif
return ret;
}
int csi_sbmeta_set_image_version(unsigned int ver)
{
#if !LIGHT_SECIMG_VERSION_IN_ENV
char runcmd[64] = {0};
unsigned char blkdata[256];
unsigned long *temp_rpmb_key_addr = NULL;
/* sbmeta version reside in RPMB block#0, offset#48*/
sprintf(runcmd, "mmc rpmb read 0x%lx 0 1", (unsigned long)blkdata);
run_command(runcmd, 0);
blkdata[48] = (ver & 0xFF00) >> 8;
blkdata[49] = ver & 0xFF;
/* sbmeta version reside in RPMB block#0, offset#48*/
#ifndef LIGHT_KDF_RPMB_KEY
temp_rpmb_key_addr = (unsigned long *)emmc_rpmb_key_sample;
#else
uint8_t kdf_rpmb_key[32];
uint32_t kdf_rpmb_key_length = 0;
int ret = 0;
ret = csi_kdf_gen_hmac_key(kdf_rpmb_key, &kdf_rpmb_key_length);
if (ret != 0) {
return -1;
}
temp_rpmb_key_addr = (unsigned long *)kdf_rpmb_key;
#endif
sprintf(runcmd, "mmc rpmb write 0x%lx 0 1 0x%lx", (unsigned long)blkdata, (unsigned long)temp_rpmb_key_addr);
run_command(runcmd, 0);
#else
env_set_hex("sbmeta_version", ver);
#endif
return 0;
}
int csi_sbmeta_set_upgrade_version(void)
{
return csi_sbmeta_set_image_version(upgrade_image_version);
}
int csi_uboot_get_image_version(unsigned int *ver)
{
#ifdef LIGHT_UBOOT_VERSION_IN_ENV
@@ -387,13 +463,13 @@ int verify_image_version_rule(unsigned int new_ver, unsigned int cur_ver)
/* This is unsecure function */
if ((new_ver_y - cur_ver_y) == 0) {
printf("New version is equal to Current version, upgrade process terminates \n\n\n");
return -1;
return VIMAGE_UPGRADE_NOT_REQUIRED;
}
printf("This is unsecure function upgrade, going on uprade anyway\n");
} else if ((new_ver_x - cur_ver_x) != 1) {
/* Check the seure version rule */
printf("The upgrade version(X) breaks against the rule\n\n\n");
return -1;
return VIMAGE_BREAK_VERSION_RULE_ERROR;
}
printf("check image verison rule pass\n\n\n");
@@ -476,61 +552,103 @@ int check_tee_version_in_boot(unsigned long tee_addr)
return 0;
}
int check_sbmeta_version_in_boot(unsigned long sbmeta_addr)
{
int ret = 0;
unsigned int img_version = 0;
unsigned int expected_img_version = 0;
img_version = get_image_version(sbmeta_addr);
if (img_version == 0) {
printf("get sbmeta image version fail\n");
return -1;
}
ret = csi_sbmeta_get_image_version(&expected_img_version);
if (ret != 0) {
printf("Get sbmeta expected img version fail\n");
return -1;
}
ret = check_image_version_rule(img_version, expected_img_version);
if (ret != 0) {
printf("Image version breaks the rule\n");
return -1;
}
return 0;
}
int light_vimage(int argc, char *const argv[])
{
int ret = 0;
unsigned long vimage_addr = 0;
unsigned int new_img_version = 0;
unsigned int cur_img_version = 0;
char imgname[32] = {0};
if (argc < 3)
char imgname[32] = {0};
if (argc < 3)
return CMD_RET_USAGE;
/* Parse input parameters */
vimage_addr = simple_strtoul(argv[1], NULL, 16);
strcpy(imgname, argv[2]);
/* Retrieve desired information from image header */
new_img_version = get_image_version(vimage_addr);
if (new_img_version == 0) {
printf("get new img version fail\n");
return CMD_RET_FAILURE;
}
if (strcmp(imgname, UBOOT_PART_NAME) == 0) {
new_img_version = (((new_img_version & 0xff )+1) << 8) | ((new_img_version & 0xff00)>>8);
}
if (strcmp(imgname, UBOOT_PART_NAME) == 0) {
new_img_version = (((new_img_version & 0xff )+1) << 8) | ((new_img_version & 0xff00)>>8);
}
printf("Get new image version from image header: v%d.%d\n", (new_img_version & 0xff00)>>8, new_img_version & 0xff);
/* Check image version for ROLLBACK resisance */
/* Check image version for ROLLBACK resisance */
if (strcmp(imgname, TF_PART_NAME) == 0) {
ret = csi_tf_get_image_version(&cur_img_version);
if (ret != 0) {
printf("Get tf img version fail\n");
return CMD_RET_FAILURE;
}
#if LIGHT_NON_COT_BOOT
/* if in non-cot mode, tf and tee will not be signed at first */
if (image_have_head(vimage_addr) == 0 && ((cur_img_version & 0xFF00) >> 8 == 0)) {
return VIMAGE_UPGRADE_NOT_REQUIRED;
}
#endif
} else if (strcmp(imgname, TEE_PART_NAME) == 0){
ret = csi_tee_get_image_version(&cur_img_version);
if (ret != 0) {
printf("Get tee img version fail\n");
return CMD_RET_FAILURE;
}
#if LIGHT_NON_COT_BOOT
/* if in non-cot mode, tf and tee will not be signed at first */
if (image_have_head(vimage_addr) == 0 && ((cur_img_version & 0xFF00) >> 8 == 0)) {
return VIMAGE_UPGRADE_NOT_REQUIRED;
}
#endif
} else if (strcmp(imgname, KERNEL_PART_NAME) == 0){
ret = csi_kernel_get_image_version(&cur_img_version);
if (ret != 0) {
printf("Get kernel img version fail\n");
return CMD_RET_FAILURE;
}
} else if (strcmp(imgname, UBOOT_PART_NAME) == 0) {
} else if (strcmp(imgname, SBMETA_PART_NAME) == 0){
ret = csi_sbmeta_get_image_version(&cur_img_version);
if (ret != 0) {
printf("Get sbmeta img version fail\n");
return CMD_RET_FAILURE;
}
} else if (strcmp(imgname, UBOOT_PART_NAME) == 0) {
ret = csi_uboot_get_image_version(&cur_img_version);
if (ret != 0) {
printf("Get uboot img version fail\n");
return CMD_RET_FAILURE;
}
}
// Check uboot maximization version > 64
if (((new_img_version & 0xFF00) >> 8) > UBOOT_MAX_VER) {
printf("UBOOT Image version has reached to max-version\n");
@@ -541,13 +659,13 @@ int light_vimage(int argc, char *const argv[])
printf("unsupport image file\n");
return CMD_RET_FAILURE;
}
/* Verify image version rule */
ret = verify_image_version_rule(new_img_version, cur_img_version);
if (ret != 0) {
return CMD_RET_FAILURE;
return ret;
}
/* Save new image version to allow caller upgrade image version */
upgrade_image_version = new_img_version;
@@ -561,22 +679,27 @@ int light_vimage(int argc, char *const argv[])
if (strcmp(imgname, TF_PART_NAME) == 0) {
ret = verify_customer_image(T_TF, vimage_addr);
if (ret != 0) {
return CMD_RET_FAILURE;
return VIMAGE_SIGNATRE_VERIFICATION_FAILED;
}
} else if (strcmp(imgname, TEE_PART_NAME) == 0) {
ret = verify_customer_image(T_TEE, vimage_addr);
if (ret != 0) {
return CMD_RET_FAILURE;
return VIMAGE_SIGNATRE_VERIFICATION_FAILED;
}
} else if (strcmp(imgname, KERNEL_PART_NAME) == 0) {
ret = verify_customer_image(T_KRLIMG, vimage_addr);
if (ret != 0) {
return CMD_RET_FAILURE;
return VIMAGE_SIGNATRE_VERIFICATION_FAILED;
}
} else if (strcmp(imgname, UBOOT_PART_NAME) == 0) {
ret = verify_customer_image(T_UBOOT, vimage_addr);
if (ret != 0) {
return CMD_RET_FAILURE;
return VIMAGE_SIGNATRE_VERIFICATION_FAILED;
}
} else if (strcmp(imgname, SBMETA_PART_NAME) == 0) {
ret = verify_customer_image(T_SBMETA, vimage_addr);
if (ret != 0) {
return VIMAGE_SIGNATRE_VERIFICATION_FAILED;
}
} else {
printf("Error: unknow image name\n");
@@ -597,8 +720,8 @@ int light_secboot(int argc, char * const argv[])
printf("\n\n");
printf("Now, we start to verify all trust firmware before boot kernel !\n");
/* Enject RPMB KEY directly in startup */
csi_rpmb_write_access_key();
/* Enject RPMB KEY directly in startup */
csi_rpmb_write_access_key();
/* Initialize secure basis of functions */
ret = csi_sec_init();
@@ -698,21 +821,32 @@ void sec_firmware_version_dump(void)
unsigned int tf_ver = 0;
unsigned int tee_ver = 0;
unsigned int uboot_ver = 0;
unsigned int sbmeta_ver = 0;
unsigned int tf_ver_env = 0;
unsigned int tee_ver_env = 0;
unsigned int sbmeta_ver_env = 0;
csi_uboot_get_image_version(&uboot_ver);
csi_tf_get_image_version(&tf_ver);
csi_tee_get_image_version(&tee_ver);
csi_sbmeta_get_image_version(&sbmeta_ver);
/* Keep sync with version in RPMB, the Following version could be leveraged by OTA client */
tee_ver_env = env_get_hex("tee_version", 0);
tf_ver_env = env_get_hex("tf_version", 0);
sbmeta_ver_env = env_get_hex("sbmeta_version", 0);
if ((tee_ver_env != tee_ver) && (tee_ver != 0)) {
env_set_hex("tee_version", tee_ver);
run_command("saveenv", 0);
}
if ((tf_ver_env != tf_ver) && (tf_ver != 0)) {
env_set_hex("tf_version", tf_ver);
run_command("saveenv", 0);
}
if ((sbmeta_ver_env != sbmeta_ver) && (sbmeta_ver != 0)) {
env_set_hex("sbmeta_version", sbmeta_ver);
run_command("saveenv", 0);
}
printf("\n\n");
@@ -720,217 +854,321 @@ void sec_firmware_version_dump(void)
printf("uboot Firmware v%d.0\n", (uboot_ver & 0xff00) >> 8);
printf("Trust Firmware v%d.%d\n", (tf_ver & 0xff00) >> 8, tf_ver & 0xff);
printf("TEE OS v%d.%d\n", (tee_ver & 0xff00) >> 8, tee_ver & 0xff);
printf("SBMETA v%d.%d\n", (sbmeta_ver & 0xff00) >> 8, sbmeta_ver & 0xff);
printf("\n\n");
}
void sec_upgrade_thread(void)
struct sec_img_upgrade_entry {
const char* filename;
const char* imgtype;
int (*set_version_func)(void);
const char *part_str;
};
static struct sec_img_upgrade_entry sec_img_list[] = {
{"sbmeta.bin", "sbmeta", csi_sbmeta_set_upgrade_version, "sbmeta"},
{"trust_firmware.bin", "tf", csi_tf_set_upgrade_version, "tee"},
{"tee.bin", "tee", csi_tee_set_upgrade_version, "tee"},
{NULL, NULL, NULL, NULL},
};
static struct blk_desc *dev_desc;
static int ab_get_blk(void)
{
struct disk_partition part_info;
dev_desc = blk_get_dev("mmc", CONFIG_FASTBOOT_FLASH_MMC_DEV);
if (dev_desc == NULL) {
printf("Failed to find MMC device\n");
return -1;
}
return 0;
}
static int ab_get_sec_part(const char *part_str, int update_part)
{
struct disk_partition part_info;
char partname[10] = {0};
int part = 0;
if (update_part) {
sprintf(partname, "%s_%s", part_str, update_slot);
} else {
sprintf(partname, "%s_%s", part_str, current_slot);
}
part = part_get_info_by_name(dev_desc, partname, &part_info);
if (part < 0) {
printf("Failed to find MMC device\n");
}
return part;
}
static int single_img_upgrade(struct sec_img_upgrade_entry *sec_img_entry)
{
const unsigned long temp_addr=0x200000;
char runcmd[80];
uint8_t * image_buffer = NULL;
uint8_t * image_malloc_buffer = NULL;
int ret = 0;
unsigned int sec_upgrade_flag = 0;
uint8_t * image_buffer = NULL;
uint8_t * image_malloc_buffer = NULL;
unsigned int upgrade_file_size = 0;
const char *filename = NULL;
int update_part = 0;
int current_part = 0;
int ret = 0;
char *argv[3] = {"vimage", NULL, NULL};
if (sec_img_entry == NULL) {
return -1;
}
update_part = ab_get_sec_part(sec_img_entry->part_str, 1);
if (update_part < 0) {
return -1;
}
filename = sec_img_entry->filename;
/* STEP 1: read upgrade image from storage */
printf("read upgrade image (%s) from storage \n", filename);
sprintf(runcmd, "ext4load mmc ${mmcdev}:%x 0x%p %s", update_part, (void *)temp_addr, filename);
printf("runcmd:%s\n", runcmd);
ret = run_command(runcmd, 0);
if (ret != 0) {
printf("%s upgrade process is terminated due to some reason\n", filename);
return -1;
}
/* Fetch the total file size after read out operation end */
upgrade_file_size = env_get_hex("filesize", 0);
printf("upgrade file size: %d\n", upgrade_file_size);
/*store image to temp buffer as temp_addr may be decrypted*/
image_malloc_buffer = malloc(upgrade_file_size);
if (image_malloc_buffer == NULL) {
image_buffer = (uint8_t*)temp_addr + upgrade_file_size;
} else {
image_buffer = image_malloc_buffer;
}
memcpy(image_buffer, (void*)temp_addr, upgrade_file_size);
/* STEP 2: verify secure image */
sprintf(runcmd, "0x%lx", temp_addr);
argv[1] = runcmd;
argv[2] = sec_img_entry->imgtype;
ret = light_vimage(3, argv);
if (ret == VIMAGE_UPGRADE_NOT_REQUIRED) {
printf("%s Image may not need upgrade\n", sec_img_entry->imgtype);
return 0;
} else if (ret != 0) {
return -1;
}
/* STEP 3: update partition image in another slot */
current_part = ab_get_sec_part(sec_img_entry->part_str, 0);
if (current_part < 0) {
return -1;
}
printf("write upgrade image (%s) into another slot \n", filename);
sprintf(runcmd, "ext4write mmc 0:%x 0x%p /%s 0x%x", current_part, (void *)image_buffer, filename, upgrade_file_size);
printf("runcmd:%s\n", runcmd);
ret = run_command(runcmd, 0);
if (ret != 0) {
printf("%s upgrade process is terminated due to some reason\n", filename);
return -1;
}
/* STEP 4: update secure image version */
sec_img_entry->set_version_func();
printf("\n\n%s image ugprade process is successful\n\n", filename);
return 0;
}
static int sec_img_upgrade(void)
{
int ret = 0;
struct sec_img_upgrade_entry *sec_img_entry = sec_img_list;
ab_get_blk();
while (sec_img_entry->filename != NULL) {
ret = single_img_upgrade(sec_img_entry);
if (ret) {
printf("Fail to upgrade image\n");
return -1;
}
sec_img_entry++;
}
return 0;
}
extern int hibernate_image_cleaned_flag;
extern void clean_hibernate_image_header(char *response);
static char *response[FASTBOOT_RESPONSE_LEN] = {0};
void sec_upgrade_thread(void)
{
const unsigned long temp_addr=0x200000;
char runcmd[80];
int ret = 0;
unsigned int sec_upgrade_flag = 0;
unsigned int upgrade_file_size = 0;
sec_upgrade_flag = env_get_hex("sec_upgrade_mode", 0);
current_slot = env_get("slot_suffix");
update_slot = strcmp(current_slot, "a") == 0 ? "b" : "a";
if (sec_upgrade_flag == 0) {
return;
}
clean_hibernate_image_header(response);
printf("bootstrap: sec_upgrade_flag: %x\n", sec_upgrade_flag);
if (sec_upgrade_flag == UBOOT_SEC_UPGRADE_FLAG) {
unsigned int block_cnt;
struct blk_desc *dev_desc;
const unsigned long uboot_temp_addr=0x80000000;
#define BLOCK_SIZE 512
#define PUBKEY_HEADER_SIZE 0x1000
/* STEP 1: read upgrade image (u-boot-with-spl.bin) from stash partition */
printf("read upgrade image (u-boot-with-spl.bin) from stash partition \n");
sprintf(runcmd, "ext4load mmc 0:4 0x%p u-boot-with-spl.bin", (void *)temp_addr);
printf("runcmd:%s\n", runcmd);
ret = run_command(runcmd, 0);
if (ret != 0) {
printf("UBOOT Upgrade process is terminated due to some reason\n");
goto _upgrade_uboot_exit;
}
/* Fetch the total file size after read out operation end */
upgrade_file_size = env_get_hex("filesize", 0);
printf("uboot upgrade file size: %d\n", upgrade_file_size);
/* STEP 2: verify its authentiticy here */
memmove((void *)uboot_temp_addr, (const void *)temp_addr, upgrade_file_size);
sprintf(runcmd, "vimage 0x%p uboot", (void *)(uboot_temp_addr+PUBKEY_HEADER_SIZE));
printf("runcmd:%s\n", runcmd);
ret = run_command(runcmd, 0);
if (ret != 0) {
printf("UBOOT Image verification fail and upgrade process terminates\n");
goto _upgrade_uboot_exit;
}
/* STEP 3: update uboot partition */
printf("write upgrade image (u-boot-with-spl.bin) into uboot partition \n");
dev_desc = blk_get_dev("mmc", CONFIG_FASTBOOT_FLASH_MMC_DEV);
if (!dev_desc || dev_desc->type == DEV_TYPE_UNKNOWN) {
printf("Invalid mmc device\n");
goto _upgrade_uboot_exit;
}
block_cnt = upgrade_file_size / BLOCK_SIZE;
if (upgrade_file_size % BLOCK_SIZE) {
block_cnt = block_cnt +1;
}
run_command("mmc partconf 0 1 0 1", 0);
sprintf(runcmd, "mmc write 0x%p 0 %x", (void *)temp_addr, block_cnt);
printf("runcmd:%s\n", runcmd);
ret = run_command(runcmd, 0);
run_command("mmc partconf 0 1 0 0", 0);
if (ret != 0) {
printf("UBOOT upgrade process is terminated due to some reason\n");
goto _upgrade_uboot_exit;
}
/* STEP 4: update tee version */
ret = csi_uboot_set_upgrade_version();
if (ret != 0) {
printf("Set uboot upgrade version fail\n");
goto _upgrade_uboot_exit;
}
printf("\n\nUBOOT image ugprade process is successful\n\n");
_upgrade_uboot_exit:
/* set secure upgrade flag to 0 that indicate upgrade over */
run_command("env set sec_upgrade_mode 0", 0);
run_command("saveenv", 0);
run_command("reset", 0);
} else if ((sec_upgrade_flag >> 16) == SEC_IMG_UPGRADE_FLAG) {
ret = sec_img_upgrade();
if (ret) {
printf("secure image upgrade failed\n");
/* if failed, clear upgrade flag, terminate upgradation */
sec_upgrade_flag = 0;
} else {
/* if succeed, clear secure flag */
sec_upgrade_flag = sec_upgrade_flag & 0x0000FFFF;
/* if boot need not update, switch current slot to update slot */
if ((sec_upgrade_flag & 0xFF00) != BOOT_IMG_UPGRADE_FLAG) {
sprintf(runcmd, "env set slot_suffix %s", update_slot);
run_command(runcmd, 0);
}
}
/* set upgrade flag */
sprintf(runcmd, "env set sec_upgrade_mode %x", sec_upgrade_flag);
run_command(runcmd, 0);
run_command("saveenv", 0);
run_command("reset", 0);
} else if (((sec_upgrade_flag & 0xFF00) != BOOT_IMG_UPGRADE_FLAG) &&
((sec_upgrade_flag & 0xFF) != ROOT_IMG_UPGRADE_FLAG)) {
printf("Unknown bootstrap, Force sysem reboot\n");
run_command("env set sec_upgrade_mode 0", 0);
run_command("saveenv", 0);
run_command("reset", 0);
}
}
void nonsec_upgrade_thread(void)
{
unsigned int sec_upgrade_flag;
unsigned long retries;
char runcmd[32] = {0};
sec_upgrade_flag = env_get_hex("sec_upgrade_mode", 0);
if (sec_upgrade_flag == 0)
return;
printf("bootstrap: sec_upgrade_flag: %x\n", sec_upgrade_flag);
if (sec_upgrade_flag == TF_SEC_UPGRADE_FLAG) {
/* STEP 1: read upgrade image (trust_firmware.bin) from stash partition */
printf("read upgrade image (trust_firmware.bin) from stash partition \n");
sprintf(runcmd, "ext4load mmc 0:5 0x%p trust_firmware.bin", (void *)temp_addr);
printf("runcmd:%s\n", runcmd);
ret = run_command(runcmd, 0);
if (ret != 0) {
printf("TF upgrade process is terminated due to some reason\n");
goto _upgrade_tf_exit;
retries = env_get_ulong("retries", 10, 5);
if (sec_upgrade_flag == 0) {
if (retries < 5 && retries > 0) {
printf("boot upgradation is successful!\n");
run_command("env set retries 5", 0);
run_command("env save", 0);
}
/* Fetch the total file size after read out operation end */
upgrade_file_size = env_get_hex("filesize", 0);
printf("upgrade file size: %d\n", upgrade_file_size);
/*store image to temp buffer as temp_addr may be decrypted*/
image_malloc_buffer = malloc(upgrade_file_size);
if ( image_malloc_buffer == NULL ) {
image_buffer = (uint8_t*)temp_addr + upgrade_file_size;
} else {
image_buffer = image_malloc_buffer;
return;
}
memcpy(image_buffer, (void*)temp_addr, upgrade_file_size);
/* STEP 2: verify its authentiticy here */
sprintf(runcmd, "vimage 0x%p tf", (void *)temp_addr);
printf("runcmd:%s\n", runcmd);
ret = run_command(runcmd, 0);
if (ret != 0) {
printf("TF Image verification fail and upgrade process terminates\n");
goto _upgrade_tf_exit;
/* when sec_upgrade_mode != 0 and the first time try to boot. switch current slot to update slot*/
if (retries == 5) {
printf("upgrade images are in slot %s...\n", update_slot);
sprintf(runcmd, "env set slot_suffix %s", update_slot);
run_command(runcmd, 0);
}
/* if ROOT image need upgrade, clear flag */
if ((sec_upgrade_flag & 0xFF) == ROOT_IMG_UPGRADE_FLAG) {
printf("in root image upgrade process...\n");
sec_upgrade_flag = sec_upgrade_flag & 0xFF00;
sprintf(runcmd, "env set sec_upgrade_mode %X", sec_upgrade_flag);
run_command(runcmd, 0);
}
/* if boot image need upgrade, decrement retries */
if ((sec_upgrade_flag & 0xFF00) == BOOT_IMG_UPGRADE_FLAG) {
printf("in boot image upgrade process...\n");
retries--;
printf("remaining retry times: %ld\n", retries);
if (retries == 0 || retries > 5) {
/*
* upgrade failed. Now updated images are in current slot
* switch to original slot
*/
printf("boot images upgrade failed. switch slot to %s...\n", update_slot);
sprintf(runcmd, "env set slot_suffix %s", update_slot);
run_command(runcmd, 0);
run_command("env set sec_upgrade_mode 0", 0);
retries = 5;
}
/* STEP 3: update tf partition */
printf("read upgrade image (trust_firmware.bin) into tf partition \n");
sprintf(runcmd, "ext4write mmc 0:3 0x%p /trust_firmware.bin 0x%x", (void *)image_buffer, upgrade_file_size);
printf("runcmd:%s\n", runcmd);
ret = run_command(runcmd, 0);
if (ret != 0) {
printf("TF upgrade process is terminated due to some reason\n");
goto _upgrade_tf_exit;
}
/* STEP 4: update tf version */
ret = csi_tf_set_upgrade_version();
if (ret != 0) {
printf("Set trustfirmware upgrade version fail\n");
goto _upgrade_tf_exit;
}
printf("\n\nTF image ugprade process is successful\n\n");
_upgrade_tf_exit:
/* set secure upgrade flag to 0 that indicate upgrade over */
run_command("env set sec_upgrade_mode 0", 0);
run_command("saveenv", 0);
run_command("reset", 0);
if ( image_malloc_buffer != NULL ) {
free(image_malloc_buffer);
image_malloc_buffer = NULL;
}
} else if (sec_upgrade_flag == TEE_SEC_UPGRADE_FLAG) {
/* STEP 1: read upgrade image (tee.bin) from stash partition */
printf("read upgrade image (tee.bin) from stash partition \n");
sprintf(runcmd, "ext4load mmc 0:5 0x%p tee.bin", (void *)temp_addr);
printf("runcmd:%s\n", runcmd);
ret = run_command(runcmd, 0);
if (ret != 0) {
printf("TEE Upgrade process is terminated due to some reason\n");
goto _upgrade_tee_exit;
}
/* Fetch the total file size after read out operation end */
upgrade_file_size = env_get_hex("filesize", 0);
printf("TEE upgrade file size: %d\n", upgrade_file_size);
/*store image to temp buffer as temp_addr may be decrypted*/
image_malloc_buffer = malloc(upgrade_file_size);
if ( image_malloc_buffer == NULL ) {
image_buffer = (uint8_t*)temp_addr + upgrade_file_size;
} else {
image_buffer = image_malloc_buffer;
}
memcpy(image_buffer, (void*)temp_addr, upgrade_file_size);
/* STEP 2: verify its authentiticy here */
sprintf(runcmd, "vimage 0x%p tee", (void *)temp_addr);
printf("runcmd:%s\n", runcmd);
ret = run_command(runcmd, 0);
if (ret != 0) {
printf("TEE Image verification fail and upgrade process terminates\n");
goto _upgrade_tee_exit;
}
/* STEP 3: update tee partition */
printf("read upgrade image (tee.bin) into tf partition \n");
sprintf(runcmd, "ext4write mmc 0:4 0x%p /tee.bin 0x%x", (void *)image_buffer, upgrade_file_size);
printf("runcmd:%s\n", runcmd);
ret = run_command(runcmd, 0);
if (ret != 0) {
printf("TEE upgrade process is terminated due to some reason\n");
goto _upgrade_tee_exit;
}
/* STEP 4: update tee version */
ret = csi_tee_set_upgrade_version();
if (ret != 0) {
printf("Set tee upgrade version fail\n");
goto _upgrade_tee_exit;
}
printf("\n\nTEE image ugprade process is successful\n\n");
_upgrade_tee_exit:
/* set secure upgrade flag to 0 that indicate upgrade over */
run_command("env set sec_upgrade_mode 0", 0);
run_command("saveenv", 0);
run_command("reset", 0);
if ( image_malloc_buffer != NULL ) {
free(image_malloc_buffer);
image_malloc_buffer = NULL;
}
} else if (sec_upgrade_flag == UBOOT_SEC_UPGRADE_FLAG) {
unsigned int block_cnt;
struct blk_desc *dev_desc;
const unsigned long uboot_temp_addr=0x80000000;
#define BLOCK_SIZE 512
#define PUBKEY_HEADER_SIZE 0x1000
/* STEP 1: read upgrade image (u-boot-with-spl.bin) from stash partition */
printf("read upgrade image (u-boot-with-spl.bin) from stash partition \n");
sprintf(runcmd, "ext4load mmc 0:5 0x%p u-boot-with-spl.bin", (void *)temp_addr);
printf("runcmd:%s\n", runcmd);
ret = run_command(runcmd, 0);
if (ret != 0) {
printf("UBOOT Upgrade process is terminated due to some reason\n");
goto _upgrade_uboot_exit;
}
/* Fetch the total file size after read out operation end */
upgrade_file_size = env_get_hex("filesize", 0);
printf("uboot upgrade file size: %d\n", upgrade_file_size);
/* STEP 2: verify its authentiticy here */
memmove((void *)uboot_temp_addr, (const void *)temp_addr, upgrade_file_size);
sprintf(runcmd, "vimage 0x%p uboot", (void *)(uboot_temp_addr+PUBKEY_HEADER_SIZE));
printf("runcmd:%s\n", runcmd);
ret = run_command(runcmd, 0);
if (ret != 0) {
printf("UBOOT Image verification fail and upgrade process terminates\n");
goto _upgrade_uboot_exit;
}
/* STEP 3: update uboot partition */
printf("write upgrade image (u-boot-with-spl.bin) into boot partition \n");
dev_desc = blk_get_dev("mmc", CONFIG_FASTBOOT_FLASH_MMC_DEV);
if (!dev_desc || dev_desc->type == DEV_TYPE_UNKNOWN) {
printf("Invalid mmc device\n");
goto _upgrade_uboot_exit;
}
block_cnt = upgrade_file_size / BLOCK_SIZE;
if (upgrade_file_size % BLOCK_SIZE) {
block_cnt = block_cnt +1;
}
run_command("mmc partconf 0 1 0 1", 0);
sprintf(runcmd, "mmc write 0x%p 0 %x", (void *)temp_addr, block_cnt);
printf("runcmd:%s\n", runcmd);
ret = run_command(runcmd, 0);
run_command("mmc partconf 0 1 0 0", 0);
if (ret != 0) {
printf("UBOOT upgrade process is terminated due to some reason\n");
goto _upgrade_uboot_exit;
}
/* STEP 4: update tee version */
ret = csi_uboot_set_upgrade_version();
if (ret != 0) {
printf("Set uboot upgrade version fail\n");
goto _upgrade_uboot_exit;
}
printf("\n\nUBOOT image ugprade process is successful\n\n");
_upgrade_uboot_exit:
/* set secure upgrade flag to 0 that indicate upgrade over */
run_command("env set sec_upgrade_mode 0", 0);
run_command("saveenv", 0);
run_command("reset", 0);
} else {
printf("Unknown bootstrap, Force sysem reboot\n");
run_command("reset", 0);
sprintf(runcmd, "env set retries %ld", retries);
run_command(runcmd, 0);
run_command("env save", 0);
}
}
#endif

9
board/thead/light-c910/clock_config.c
View File

@@ -1146,7 +1146,7 @@ void ap_mipi_dsi1_clk_endisable(bool en)
writel(cfg1, (void __iomem *)AP_DPU1_PLL_CFG1);
}
#if defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_DISCRETE) || defined (CONFIG_TARGET_LIGHT_FM_C910_BEAGLE) || defined (CONFIG_TARGET_LIGHT_FM_C910_B_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_B_POWER) || defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_B) || defined (CONFIG_TARGET_LIGHT_FM_C910_LPI4A)
#if defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_DISCRETE) || defined (CONFIG_TARGET_LIGHT_FM_C910_BEAGLE) || defined (CONFIG_TARGET_LIGHT_FM_C910_B_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_B_POWER) || defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_B)
static void ap_multimedia_div_num_set(enum multimedia_div_type type, unsigned int div_num)
{
unsigned long div_reg;
@@ -1220,7 +1220,7 @@ int clk_config(void)
return -EINVAL;
printf("C910 CPU FREQ: %ldMHz\n", rate / 1000000);
#ifdef PERI_BUS_PLL_FREQ_PRINT
rate = clk_light_get_rate("ahb2_cpusys_hclk", CLK_DEV_MUX);
if (!rate)
return -EINVAL;
@@ -1262,6 +1262,7 @@ int clk_config(void)
return -EINVAL;
printf("DPU1 PLL POSTDIV FREQ: %ldMHZ\n", rate / 1000000);
#endif
#ifdef AUDIO_PLL_FREQ_PRINT
rate = clk_light_get_rate("audio_pll_foutpostdiv", CLK_DEV_PLL);
@@ -1304,9 +1305,9 @@ int clk_config(void)
/* The boards other than the LightA board perform the bus down-speed operation */
#if defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_DISCRETE) || defined (CONFIG_TARGET_LIGHT_FM_C910_BEAGLE) || defined (CONFIG_TARGET_LIGHT_FM_C910_B_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_B_POWER) || defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_B) || defined (CONFIG_TARGET_LIGHT_FM_C910_LPI4A)
#if defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_DISCRETE) || defined (CONFIG_TARGET_LIGHT_FM_C910_BEAGLE) || defined (CONFIG_TARGET_LIGHT_FM_C910_B_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_B_POWER) || defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_B)
ap_multimedia_div_num_set(VI_MIPI_CSI0_DIV, 12); /* Input frquency: 2376MHZ */
ap_multimedia_div_num_set(VI_ISP0_CORE_DIV, 15); /* Input frquency: 2376MHZ */
ap_multimedia_div_num_set(VI_ISP0_CORE_DIV, 12); /* Input frquency: 2376MHZ */
ap_multimedia_div_num_set(VI_ISP1_CORE_DIV, 12); /* Input frquency: 2376MHZ */
ap_multimedia_div_num_set(VI_ISP_RY_CORE_DIV, 12); /* Input frquency: 2376MHZ */
ap_multimedia_div_num_set(VO_DPU_CORE_DIV, 4); /* Input frquency: 2376MHZ */

14
board/thead/light-c910/ddr.c
View File

@@ -12,3 +12,17 @@ void init_ddr(void)
{
writel(0x1ff << 4, (void *)0xffff005000);
}
int fixup_ddr_addrmap(unsigned long size)
{
return 0;
}
int query_ddr_boundary(unsigned long size)
{
return 0;
}
unsigned long get_ddr_density(void)
{
return 0x100000000;
}

480
board/thead/light-c910/light.c
View File

@@ -11,6 +11,15 @@
#include <thead/clock_config.h>
#include <linux/bitops.h>
#include <asm/arch-thead/light-iopmp.h>
#include <memalign.h>
#include <fdt_support.h>
#include <fs.h>
#include <asm/global_data.h>
#ifdef CONFIG_RV_BOOK
#include <memalign.h>
#include <fdt_support.h>
#include <fs.h>
#endif
#define SOC_PIN_AP_RIGHT_TOP (0x0)
#define SOC_PIN_AP_LEFT_TOP (0x1)
@@ -31,6 +40,7 @@
#define GMAC0_APB3S_BADDR 0xffec003000
#define GMAC1_APB3S_BADDR 0xffec004000
static uint64_t apb3s_baddr;
extern int check_image_board_id(uint8_t *image_data);
typedef enum {
UART0_TXD = PAD_GRP_BASE_SET(SOC_PIN_AP_RIGHT_TOP),
@@ -338,6 +348,193 @@ static int light_pinmx_get_mux_base(pin_name_t pin_name, uint32_t** cfg_base)
return 0;
}
#ifdef CONFIG_FASTBOOT_FLASH_MMC
/*
* The SN data is stored in the first 512B of the NV partition. It should be read out
* and updated. In the following situations, the update will fail:
* a. The NV partition cannot be found
* b. The length of the SN is out of range
* c. The value of the SN contains unprintable characters
*/
#define MAX_SN_SIZE (64 + 2) /* extra two bytes is used for magic number */
#define MAX_READ_SIZE 512
#define NV_MAC_OFFSET 128
#define NV_MAC_SIZE 20
static int is_env_setted(const char *env_name)
{
#ifdef U_BUILD_DEBUG
return 0;
#else
const char *env = env_get(env_name);
if(env && *env) {
return 1;
}
return 0;
#endif
}
static void update_sn(void)
{
struct blk_desc *dev_desc;
struct disk_partition part_info;
unsigned char buffer[MAX_READ_SIZE];
int ret;
ulong block_start;
ulong block_count;
ulong n;
size_t length;
unsigned int i;
ret = is_env_setted("serial#");
if (ret) {
printf("serial# has been setted,skip read from nv partition\n");
return;
}
/* Get mmc dev */
dev_desc = blk_get_dev("mmc", CONFIG_FASTBOOT_FLASH_MMC_DEV);
if (dev_desc == NULL) {
printf("Failed to find MMC device\n");
goto err_exit;
}
/* Get the nv partition infomation */
ret = part_get_info_by_name(dev_desc, NV_PARTITION_NAME, &part_info);
if (ret < 0) {
printf("Failed to find '%s' partition\n", NV_PARTITION_NAME);
goto err_exit;
}
/* Read the first MAX_READ_SIZE from NV partition data */
block_start = part_info.start;
block_count = (MAX_READ_SIZE + dev_desc->blksz - 1) / dev_desc->blksz;
n = blk_dread(dev_desc, block_start, block_count, buffer);
if (n != block_count) {
printf("Failed to read data from '%s' partition\n", NV_PARTITION_NAME);
goto err_exit;
}
/* Check the length of SN data */
length = strnlen((char *)buffer, MAX_READ_SIZE);
if ((length > MAX_SN_SIZE)) {
printf("The size of SN data(%zu) is out of range \r\n", length);
goto err_exit;
}
/* Check the magic number of NV */
i = 0;
if ((buffer[i++] != 'N') || (buffer[i++] != 'V')) {
printf("The magic number of NV partition is invalid\r\n");
goto err_exit;
}
/* Check the value of the SN data; the SN value should consist of printable characters*/
for (; i < length; i++) {
if ((buffer[i] < 33) || (buffer[i] > 126)) {
printf("Unprintable character detected[0x%x] @%d \r\n", buffer[i], i);
goto err_exit;
}
}
/* The first two bytes are used for NV magic number */
env_set("serial#", (char *)buffer + 2);
printf("Success to read SN value, update SN: %s to env serial# \r\n", buffer + 2);
ret = run_command("env save",0);
if(ret != 0) {
printf("Failed to update SN to env\r\n");
}
return;
err_exit:
printf("Failed to read the SN value; Using the default value instead\r\n");
return;
}
static void update_mac(void)
{
struct blk_desc *dev_desc;
struct disk_partition part_info;
unsigned char buffer[MAX_READ_SIZE];
int ret;
ulong block_start;
ulong block_count;
ulong n;
size_t length;
unsigned int i;
ret = is_env_setted("ethaddr");
if (ret) {
printf("ethaddr has been setted,skip read from nv partition\n");
return;
}
/* Get mmc dev */
dev_desc = blk_get_dev("mmc", CONFIG_FASTBOOT_FLASH_MMC_DEV);
if (dev_desc == NULL) {
printf("Failed to find MMC device\n");
goto err_exit;
}
/* Get the nv partition infomation */
ret = part_get_info_by_name(dev_desc, NV_PARTITION_NAME, &part_info);
if (ret < 0) {
printf("Failed to find '%s' partition\n", NV_PARTITION_NAME);
goto err_exit;
}
/* Read the first MAX_READ_SIZE from NV partition data */
block_start = part_info.start;
block_count = (MAX_READ_SIZE + dev_desc->blksz - 1) / dev_desc->blksz;
n = blk_dread(dev_desc, block_start, block_count, buffer);
if (n != block_count) {
printf("Failed to read data from '%s' partition\n", NV_PARTITION_NAME);
goto err_exit;
}
/* Check the length of MAC data */
length = strnlen((char *)buffer + NV_MAC_OFFSET, MAX_READ_SIZE);
if (length != NV_MAC_SIZE) {
printf("The size of MAC data(%zu) is out of range\r\n", length);
goto err_exit;
}
/* Check the magic number of MAC */
i = 0;
if ((buffer[NV_MAC_OFFSET + i++] != 'M') || (buffer[NV_MAC_OFFSET + i++] != 'A') || (buffer[NV_MAC_OFFSET + i++] != 'C')) {
printf("The magic number of NV partition is invalid\r\n");
goto err_exit;
}
/* Check the value of the MAC data; the MAC value should consist of printable characters*/
for (; i < length; i++) {
if ((buffer[NV_MAC_OFFSET + i] < 33) || (buffer[i + NV_MAC_OFFSET] > 126)) {
printf("Unprintable character detected\r\n");
goto err_exit;
}
}
/* The first two bytes are used for MAC magic number */
env_set("ethaddr", (char *)buffer + 3 + NV_MAC_OFFSET);
printf("Success to read MAC value, update MAC: %s to env ethaddr \r\n", buffer + 3 + NV_MAC_OFFSET);
return;
err_exit:
printf("Failed to read the MAC value; Using the default value instead\r\n");
return;
}
#else
static void update_sn(void)
{
}
static void update_mac(void)
{
}
#endif
/*******************************************************************************
* function: danica_ioreuse_inital
*
@@ -1408,7 +1605,7 @@ static void light_iopin_init(void)
light_pin_cfg(GMAC0_RXD2, PIN_SPEED_NORMAL, PIN_PN, 0xF);
light_pin_cfg(GMAC0_RXD3, PIN_SPEED_NORMAL, PIN_PN, 0xF);
}
#elif defined (CONFIG_TARGET_LIGHT_FM_C910_LPI4A)
#elif defined (CONFIG_TARGET_LIGHT_FM_C910_LPI4A) || defined(CONFIG_TARGET_LIGHT_FM_C910_RVBOOK)
static void light_iopin_init(void)
{
/* aon-padmux config */
@@ -1421,7 +1618,10 @@ static void light_iopin_init(void)
light_pin_cfg(CPU_JTG_TMS, PIN_SPEED_NORMAL, PIN_PN, 2);
light_pin_mux(CPU_JTG_TDI, 3);
light_pin_cfg(CPU_JTG_TDI, PIN_SPEED_NORMAL, PIN_PN, 2);
#ifdef CONFIG_RV_BOOK
light_pin_mux(CPU_JTG_TRST, 3);
light_pin_cfg(CPU_JTG_TRST, PIN_SPEED_NORMAL, PIN_PN, 2);
#endif
light_pin_mux(AOGPIO_7, 1);
light_pin_mux(AOGPIO_8, 1);
// light_pin_mux(AOGPIO_9, 0);
@@ -1433,7 +1633,7 @@ static void light_iopin_init(void)
// light_pin_mux(AOGPIO_15,0);
light_pin_cfg(AOGPIO_7, PIN_SPEED_NORMAL, PIN_PN, 2); ///NC
light_pin_cfg(AOGPIO_8, PIN_SPEED_NORMAL, PIN_PN, 2); ///NC
// light_pin_cfg(AOGPIO_9,PIN_SPEED_NORMAL,PIN_PN,2);
light_pin_cfg(AOGPIO_9,PIN_SPEED_NORMAL,PIN_PN,2);
light_pin_cfg(AOGPIO_10, PIN_SPEED_NORMAL, PIN_PN, 2);
light_pin_cfg(AOGPIO_11, PIN_SPEED_NORMAL, PIN_PN, 2);
light_pin_cfg(AOGPIO_12, PIN_SPEED_NORMAL, PIN_PN, 2);
@@ -1467,6 +1667,7 @@ static void light_iopin_init(void)
light_pin_cfg(AUDIO_PA29, PIN_SPEED_NORMAL, PIN_PN, 2);
light_pin_mux(AUDIO_PA30, 0);
light_pin_cfg(AUDIO_PA30, PIN_SPEED_NORMAL, PIN_PN, 2);
light_pin_mux(AUDIO_PA30, 3);
// light_pin_mux(AUDIO_PA9,3); ///AUDIO-PA-RESET
// light_pin_cfg(AUDIO_PA9,PIN_SPEED_NORMAL,PIN_PN,2);
@@ -1570,7 +1771,7 @@ static void light_iopin_init(void)
light_pin_mux(CLK_OUT_2, 0);
light_pin_cfg(CLK_OUT_2, PIN_SPEED_NORMAL, PIN_PU, 2);
light_pin_mux(CLK_OUT_3, 0);
light_pin_cfg(CLK_OUT_3, PIN_SPEED_NORMAL, PIN_PU, 2);
light_pin_cfg(CLK_OUT_3, PIN_SPEED_NORMAL, PIN_PU, 2);
// light_pin_mux(GPIO1_21,3);
light_pin_mux(GPIO1_22, 3);
@@ -1590,7 +1791,7 @@ static void light_iopin_init(void)
light_pin_cfg(GPIO1_30, PIN_SPEED_NORMAL, PIN_PN, 2); ///<DBB2LEDDRIVER_EN
light_pin_cfg(UART0_TXD, PIN_SPEED_NORMAL, PIN_PN, 2);
light_pin_cfg(UART0_RXD, PIN_SPEED_NORMAL, PIN_PN, 2);
light_pin_cfg(UART0_RXD, PIN_SPEED_NORMAL, PIN_PN, 2);
/*ap-pdmux on righ/top*/
// light_pin_mux(QSPI0_SCLK,3); ///NC
@@ -1683,16 +1884,19 @@ static void light_iopin_init(void)
light_pin_cfg(GMAC0_CRS, PIN_SPEED_NORMAL, PIN_PU, 2);
}
#else
static void light_iopin_init(void)
{
light_pin_cfg(I2C_AON_SCL,PIN_SPEED_NORMAL,PIN_PN,4);
light_pin_cfg(I2C_AON_SDA,PIN_SPEED_NORMAL,PIN_PN,4);
light_pin_cfg(AOGPIO_8,PIN_SPEED_NORMAL,PIN_PN,2);
light_pin_cfg(AOGPIO_9,PIN_SPEED_NORMAL,PIN_PN,2);
light_pin_cfg(AOGPIO_14, PIN_SPEED_NORMAL, PIN_PN, 2);
light_pin_mux(AOGPIO_10,1);
light_pin_mux(AOGPIO_11,1);
light_pin_mux(AOGPIO_12,1);
light_pin_mux(AOGPIO_13,1);
light_pin_mux(AOGPIO_14, 0);
light_pin_mux(AUDIO_PA30,3);
/*qspi1 cs0 gpio0-1 pad strength and pin-pull mode*/
@@ -1862,10 +2066,18 @@ static void light_usb_boot_check(void)
uchar env_enetaddr[6]={0};
uchar env_enet1addr[6]={0};
int env_ethaddr_flag,env_eth1addr_flag;
int ret = 0;
boot_mode = readl((void *)SOC_OM_ADDRBASE) & 0x7;
if (boot_mode & BIT(2))
return;
/*check board id of uboot image*/
ret = check_image_board_id((uint8_t*)SRAM_BASE_ADDR);
if (ret != 0) {
while(1);
}
#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
env_set("usb_fastboot", "yes");
#endif
@@ -1894,19 +2106,30 @@ static void light_usb_boot_check(void)
run_command("fastboot usb 0", 0);
}
int board_late_init(void)
{
light_usb_boot_check();
#if CONFIG_IS_ENABLED(LIGHT_SEC_UPGRADE)
extern void sec_upgrade_thread(void);
extern void nonsec_upgrade_thread(void);
extern void sec_firmware_version_dump(void);
sec_upgrade_thread();
nonsec_upgrade_thread();
sec_firmware_version_dump();
#endif
light_usb_boot_check();
ap_peri_clk_disable();
#ifdef CONFIG_MCU_HC32fX
mcu_poweron();
#endif
#ifdef CONFIG_DM_CHARGE_DISPLAY
charge_display();
#endif
update_sn();
update_mac();
return 0;
}
@@ -1936,3 +2159,244 @@ U_BOOT_CMD(
"check ethaddrs in environment variables is valid",
""
);
#define PAGE_SIZE 4096
#define HIBERNATE_SIG "S1SUSPEND"
#define HIBERNATE_SIG2 "S1SUSPEN2" //sign for 2nd time load image
static inline int fdt_disabled_node(void *blob,const char *path)
{
int offset;
offset = fdt_path_offset(blob,path);
if (offset < 0) {
printf("ERROR:failed to find %s node in dtb (ret %d)\n",path,offset);
return offset;
}
return fdt_status_disabled(blob,offset);
}
/*First check if path1 exist, if not, alternate to path2*/
static inline int fdt_disabled_node_alt(void *blob,const char *path1, const char *path2)
{
int offset;
offset = fdt_path_offset(blob,path1);
if (offset < 0) {
offset = fdt_path_offset(blob,path2);
if(offset < 0)
{
printf("ERROR:failed to find %s node or %s node in dtb (ret %d)\n",path1,path2,offset);
return offset;
}
}
return fdt_status_disabled(blob,offset);
}
/*First check if alias name *fisrt exist, if not, alternate to alias name *alt*/
static inline int fdt_status_disabled_by_alias_alt(void *blob,const char *fisrt,const char* alt)
{
int ret;
ret = fdt_status_disabled_by_alias(blob,fisrt);
if(ret < 0)
ret = fdt_status_disabled_by_alias(blob,alt);
return ret;
}
static int do_board_check_hibernate(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[])
{
int ret;
char runcmd[128];
ulong addr;
void *blob = NULL;
ulong mask = 0;
int resume_part;
bool fastresume = 0;
#define ON_RET_ERROR(str) if(ret < 0) printf("set node %s status failed %d\n",str,ret)
ALLOC_CACHE_ALIGN_BUFFER(u8,swsusp_header_buf,PAGE_SIZE);
u8 *header = &swsusp_header_buf[0];
struct blk_desc *dev_desc;
struct disk_partition part_info;
dev_desc = blk_get_dev("mmc", CONFIG_FASTBOOT_FLASH_MMC_DEV);
if (dev_desc == NULL) {
printf("Failed to find MMC device\n");
return CMD_RET_FAILURE;
}
resume_part = part_get_info_by_name(dev_desc, "swap", &part_info);
if (resume_part < 0) {
printf("Failed to find swap partition\n");
return CMD_RET_FAILURE;
}
if(argc >= 4) { // is user pass in ,use that
sprintf(runcmd, "read %s %s %s 0 8",
argv[1],argv[2],argv[3]);
header = (u8 *)simple_strtoul(argv[3],NULL,16);
if(argc >= 5)
mask = simple_strtoul(argv[4],NULL,16);
printf("read swsusp_header to %p,dtb disbale mask 0x%lx\n",header,mask);
} else {
sprintf(runcmd, "read mmc 0:%d 0x%lx 0 8",
resume_part,(unsigned long)&header[0]);
}
ret = run_command(runcmd, 0);
if(ret != CMD_RET_SUCCESS)
goto failed;
if(!memcmp(HIBERNATE_SIG, &header[PAGE_SIZE-10], 10) ||
!memcmp(HIBERNATE_SIG2, &header[PAGE_SIZE-10], 10) ) {
printf("found sign\n");
}
else {
sprintf(runcmd, "0:%s",env_get("mmcbootpart"));
if(file_exists("mmc",runcmd,"no_fastresume",FS_TYPE_EXT)) {
printf("do not fastresume\n");
goto default_set;
}
sprintf(runcmd, "read mmc 0:%d 0x%lx 0 8",
resume_part+1,(unsigned long)&header[0]);
ret = run_command(runcmd, 0);
if(ret != CMD_RET_SUCCESS)
goto failed;
if(!memcmp(HIBERNATE_SIG, &header[PAGE_SIZE-10], 10) ||
!memcmp(HIBERNATE_SIG2, &header[PAGE_SIZE-10], 10) ) {
printf("found fastresume sign\n");
resume_part = resume_part+1;
fastresume = true;
}
else {
printf(" not find hibernate sign\n");
goto default_set;
}
}
/*get dtb address*/
if(env_get("dtb_addr") == NULL)
{
printf("Cannot get dtb_addr,check flow !\n");
goto failed;
}
addr = env_get_hex("dtb_addr",0);
sprintf(runcmd, "fdt addr 0x%lx", env_get_hex("dtb_addr",0));
ret = run_command(runcmd, 0);
if(ret != CMD_RET_SUCCESS)
goto failed;
sprintf(runcmd, "fdt resize");
ret = run_command(runcmd, 0);
if(ret != CMD_RET_SUCCESS)
goto failed;
/*set unneed devices node disabled for hibernate resume in kernel dtb*/
blob = (void *)addr;
ret = fdt_status_disabled_by_alias(blob,"i2c0");
ON_RET_ERROR("i2c0");
ret = fdt_status_disabled_by_alias(blob,"i2c1");
ON_RET_ERROR("i2c1");
ret = fdt_status_disabled_by_alias(blob,"i2c2");
ON_RET_ERROR("i2c2");
ret = fdt_status_disabled_by_alias_alt(blob,"audio_i2c0","i2c5");
ON_RET_ERROR("audio_i2c0 or i2c5");
ret = fdt_status_disabled_by_alias_alt(blob,"audio_i2c1","i2c6");
ON_RET_ERROR("audio_i2c1 or i2c6");
ret = fdt_status_disabled_by_alias(blob,"ethernet0");
ON_RET_ERROR("ethernet0");
ret = fdt_status_disabled_by_alias(blob,"ethernet1");
ON_RET_ERROR("ethernet1");
ret = fdt_status_disabled_by_alias(blob,"spi0");
ON_RET_ERROR("spi0");
ret = fdt_status_disabled_by_alias(blob,"spi1");
ON_RET_ERROR("spi1");
ret = fdt_status_disabled_by_alias(blob,"spi2");
ON_RET_ERROR("spi2");
ret = fdt_disabled_node(blob,"/soc/adc");
ON_RET_ERROR("/soc/adc");
//default mask is 0, need set this node disbaled
if(0 == (mask & 0x01)) {
ret = fdt_disabled_node_alt(blob,"/soc/light_i2s","/soc/ap-i2s");
ON_RET_ERROR("/soc/light_i2s or /soc/ap-i2s");
ret = fdt_disabled_node_alt(blob,"/soc/audio_i2s0","/soc/audio-i2s0");
ON_RET_ERROR("/soc/audio_i2s0 or /soc/audio-i2s0");
ret = fdt_disabled_node_alt(blob,"/soc/audio_i2s1","/soc/audio-i2s1");
ON_RET_ERROR("/soc/audio_i2s1 or /soc/audio-i2s1");
ret = fdt_disabled_node_alt(blob,"/soc/audio_i2s2","/soc/audio-i2s2");
ON_RET_ERROR("/soc/audio_i2s2 or /soc/audio-i2s2");
}
if(0 == (mask & 0x02)) {
ret = fdt_disabled_node_alt(blob,"/soc/audio_i2s_8ch_sd0","/soc/i2s-8ch-sd0");
ON_RET_ERROR("/soc/audio_i2s_8ch_sd0 or /soc/i2s-8ch-sd0");
ret = fdt_disabled_node_alt(blob,"/soc/audio_i2s_8ch_sd1","/soc/i2s-8ch-sd1");
ON_RET_ERROR("/soc/audio_i2s_8ch_sd1 or /soc/i2s-8ch-sd1");
ret = fdt_disabled_node_alt(blob,"/soc/audio_i2s_8ch_sd2","/soc/i2s-8ch-sd2");
ON_RET_ERROR("/soc/audio_i2s_8ch_sd2 or /soc/i2s-8ch-sd2");
ret = fdt_disabled_node_alt(blob,"/soc/audio_i2s_8ch_sd3","/soc/i2s-8ch-sd3");
ON_RET_ERROR("/soc/audio_i2s_8ch_sd3 or /soc/i2s-8ch-sd3");
}
/*set resume_bootargs for kernel do fast bootup */
sprintf(runcmd,"resume=/dev/mmcblk0p%d notrace noftrace nopty noclkdebug ",resume_part);
env_set("resume_bootargs",runcmd);
return CMD_RET_SUCCESS;
default_set:
sprintf(runcmd,"resume=/dev/mmcblk0p%d",resume_part);
env_set("resume_bootargs",runcmd);
return CMD_RET_SUCCESS;
failed:
printf("ERROR:runcmd %s failed!\n",runcmd);
sprintf(runcmd,"resume=/dev/mmcblk0p%d",resume_part);
env_set("resume_bootargs",runcmd);
return CMD_RET_FAILURE;
}
U_BOOT_CMD(
chk_hibernate, 6, 0, do_board_check_hibernate,
"check hibernate image sign,if valid set dtb nodes and bootargs for fast boot resume",
" [<interface> <dev[:part]>] [mask]"
);
#ifdef CONFIG_FIXUP_MEMORY_REGION
static int do_fixup_memory_region(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[])
{
ulong addr;
void *blob = NULL;
DECLARE_GLOBAL_DATA_PTR;
u64 base, size;
base = gd->ram_base;
size = gd->ram_size;
/*get dtb address*/
if(env_get("dtb_addr") == NULL)
{
printf("Cannot get dtb_addr,check flow !\n");
return CMD_RET_FAILURE;
}
addr = env_get_hex("dtb_addr",0);
/*set unneed devices node disabled for hibernate resume in kernel dtb*/
blob = (void *)addr;
fdtdec_setup_mem_size_base_fdt(blob);
size -= gd->ram_base;
if (size != gd->ram_size) {
printf("fixup memory region from [0x%09lx ~ 0x%09lx] to [0x%09lx ~ 0x%09lx]\n",
gd->ram_base, gd->ram_base+gd->ram_size, gd->ram_base, gd->ram_base+size);
gd->ram_size = size;
fdt_fixup_memory(blob, gd->ram_base, gd->ram_size);
}
return CMD_RET_SUCCESS;
}
U_BOOT_CMD(
fixup_memory_region, 2, 0, do_fixup_memory_region,
"modify linux memory region via gd->ram_size",
""
);
#endif

6
board/thead/light-c910/lpddr-regu/ddr_regu.c
View File

@@ -136,7 +136,7 @@ static const struct regulator_t g_apcpu_regu_id_list[] = {
REGU_ID_DEF(IIC_IDX_AONIIC,APCPU_REGU_VDDM,0x31,0x39,0,1,800000,600000,3500000,12500,1),
},
};
#elif defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_A_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_B_REF) || (CONFIG_TARGET_LIGHT_FM_C910_BEAGLE) || defined (CONFIG_TARGET_LIGHT_FM_C910_LPI4A)
#elif defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_A_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_B_REF) || (CONFIG_TARGET_LIGHT_FM_C910_BEAGLE) || defined (CONFIG_TARGET_LIGHT_FM_C910_LPI4A) || defined(CONFIG_TARGET_LIGHT_FM_C910_RVBOOK)
/**
* board for ant-ref
*
@@ -794,7 +794,7 @@ static void light_iopmp_config(void)
}
}
int pmic_ddr_regu_init(void)
int aon_local_init(void)
{
#define AON_PADMUX_BASE (0xfffff4a000)
int ret;
@@ -955,7 +955,7 @@ int pmic_reset_apcpu_voltage(void)
return ret;
return 0;
}
#elif defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_A_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_B_REF)|| (CONFIG_TARGET_LIGHT_FM_C910_BEAGLE) || defined (CONFIG_TARGET_LIGHT_FM_C910_LPI4A)
#elif defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_A_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_B_REF)|| (CONFIG_TARGET_LIGHT_FM_C910_BEAGLE) || defined (CONFIG_TARGET_LIGHT_FM_C910_LPI4A) || defined(CONFIG_TARGET_LIGHT_FM_C910_RVBOOK)
int pmic_reset_apcpu_voltage(void)
{
int ret = -1;

2
board/thead/light-c910/lpddr-regu/ddr_regu.h
View File

@@ -9,5 +9,5 @@
#define __DDR_REGU_H__
int pmic_ddr_set_voltage(void);
int pmic_ddr_regu_init(void);
int aon_local_init(void);
#endif

218
board/thead/light-c910/lpddr4/include/aonsys_reg_define.h Normal file
View File

@@ -0,0 +1,218 @@
//------------------------------------------------------------
// DONOT MODIFY THIS FILE
// generated by JISHENGJU automatically
//------------------------------------------------------------
#ifndef AONSYS_SYSREG_REG_OFFSET_DEFINE_H
#define AONSYS_SYSREG_REG_OFFSET_DEFINE_H
#define AONSYS_REG_BASE 0xFFFFF48000
#define REG_AON_CPU_LP_MODE (AONSYS_REG_BASE + 0x0 )
#define REG_AON_CHIP_LP_MODE (AONSYS_REG_BASE + 0x4 )
#define REG_AON_AO_SERAM_TRN (AONSYS_REG_BASE + 0x10 )
#define REG_AON_AO_SERAM_INT (AONSYS_REG_BASE + 0x14 )
#define REG_AON_STR_SERAM_TRN (AONSYS_REG_BASE + 0x18 )
#define REG_AON_STR_SERAM_INT (AONSYS_REG_BASE + 0x1c )
#define REG_AON_STR_INDICATOR_0 (AONSYS_REG_BASE + 0x20 )
#define REG_AON_STR_INDICATOR_1 (AONSYS_REG_BASE + 0x24 )
#define REG_AON_STR_INDICATOR_2 (AONSYS_REG_BASE + 0x28 )
#define REG_AON_STR_INDICATOR_3 (AONSYS_REG_BASE + 0x2c )
#define REG_AON_PVTC_WR_LOCK (AONSYS_REG_BASE + 0x30 )
#define REG_AON_PVTC_TS_ALARM (AONSYS_REG_BASE + 0x34 )
#define REG_AON_PVTC_VM_ALARM (AONSYS_REG_BASE + 0x38 )
#define REG_AON_PVTC_PD_ALARM (AONSYS_REG_BASE + 0x3c )
#define REG_AON_E902_CNT_CLR (AONSYS_REG_BASE + 0x40 )
#define REG_AON_E902_RST_ADDR (AONSYS_REG_BASE + 0x44 )
#define REG_AON_C906_RST_ADDR_L (AONSYS_REG_BASE + 0x48 )
#define REG_AON_C906_RST_ADDR_H (AONSYS_REG_BASE + 0x4c )
#define REG_AON_RESERVED_REG_0 (AONSYS_REG_BASE + 0x50 )
#define REG_AON_RESERVED_REG_1 (AONSYS_REG_BASE + 0x54 )
#define REG_AON_RESERVED_REG_2 (AONSYS_REG_BASE + 0x58 )
#define REG_AON_RESERVED_REG_3 (AONSYS_REG_BASE + 0x5c )
#define REG_AON_AON_AHB_ADEXT (AONSYS_REG_BASE + 0x60 )
#define REG_AON_RC_EN (AONSYS_REG_BASE + 0x70 )
#define REG_AON_RC_FCAL (AONSYS_REG_BASE + 0x74 )
#define REG_AON_RC_MODE (AONSYS_REG_BASE + 0x78 )
#define REG_AON_RC_READY (AONSYS_REG_BASE + 0x7c )
#define REG_AON_ISO_CFG (AONSYS_REG_BASE + 0x80 )
#define REG_AON_OCRAM_ERR (AONSYS_REG_BASE + 0x90 )
#define REG_AON_TIMER_LINK (AONSYS_REG_BASE + 0x100)
#define REG_AON_PD_REQ (AONSYS_REG_BASE + 0x110)
#define REG_AON_PD_ISO_EN_SET (AONSYS_REG_BASE + 0x114)
#define REG_AON_PD_ISO_EN_CLR (AONSYS_REG_BASE + 0x118)
#define REG_AON_PD_SW_EN_SET (AONSYS_REG_BASE + 0x11c)
#define REG_AON_PD_SW_EN_CLR (AONSYS_REG_BASE + 0x120)
#define REG_AON_PD_SW_ACK (AONSYS_REG_BASE + 0x124)
#define REG_AON_PD_SW_CNT_EN (AONSYS_REG_BASE + 0x128)
#define REG_AON_PD_FSM_RST (AONSYS_REG_BASE + 0x12c)
#define REG_AON_PD_INT_MASK (AONSYS_REG_BASE + 0x130)
#define REG_AON_PD_FSM_STS_L (AONSYS_REG_BASE + 0x134)
#define REG_AON_PD_FSM_STS_H (AONSYS_REG_BASE + 0x138)
#define REG_AON_PD_INT_STS (AONSYS_REG_BASE + 0x13c)
#define REG_AON_PD_INT_CLR (AONSYS_REG_BASE + 0x140)
#define REG_AON_PD_BLK0_SW_CNT (AONSYS_REG_BASE + 0x144)
#define REG_AON_PD_BLK1_SW_CNT (AONSYS_REG_BASE + 0x148)
#define REG_AON_PD_BLK2_SW_CNT (AONSYS_REG_BASE + 0x14c)
#define REG_AON_PD_BLK3_SW_CNT (AONSYS_REG_BASE + 0x150)
#define REG_AON_PD_BLK4_SW_CNT (AONSYS_REG_BASE + 0x154)
#define REG_AON_PD_BLK5_SW_CNT (AONSYS_REG_BASE + 0x158)
#define REG_AON_PD_BLK6_SW_CNT (AONSYS_REG_BASE + 0x15c)
#define REG_AON_PD_BLK7_SW_CNT (AONSYS_REG_BASE + 0x160)
#define REG_AON_PD_BLK8_SW_CNT (AONSYS_REG_BASE + 0x164)
#define REG_AON_PD_BLK9_SW_CNT (AONSYS_REG_BASE + 0x168)
#define REG_AON_PD_BLK10_SW_CNT (AONSYS_REG_BASE + 0x16c)
#define REG_AON_PD_BLK0_INTV_CNT (AONSYS_REG_BASE + 0x180)
#define REG_AON_PD_BLK1_INTV_CNT (AONSYS_REG_BASE + 0x184)
#define REG_AON_PD_BLK2_INTV_CNT (AONSYS_REG_BASE + 0x188)
#define REG_AON_PD_BLK3_INTV_CNT (AONSYS_REG_BASE + 0x18c)
#define REG_AON_PD_BLK4_INTV_CNT (AONSYS_REG_BASE + 0x190)
#define REG_AON_PD_BLK5_INTV_CNT (AONSYS_REG_BASE + 0x194)
#define REG_AON_PD_BLK6_INTV_CNT (AONSYS_REG_BASE + 0x198)
#define REG_AON_PD_BLK7_INTV_CNT (AONSYS_REG_BASE + 0x19c)
#define REG_AON_PD_BLK8_INTV_CNT (AONSYS_REG_BASE + 0x1a0)
#define REG_AON_PD_BLK9_INTV_CNT (AONSYS_REG_BASE + 0x1a4)
#define REG_AON_PD_BLK10_INTV_CNT (AONSYS_REG_BASE + 0x1a8)
#define REG_AON_AUDIO_PMU_REQ (AONSYS_REG_BASE + 0x1f8)
#define REG_AON_AUDIO_PMU_STS (AONSYS_REG_BASE + 0x1fc)
#define REG_AON_AUDIO_PMU_INTR (AONSYS_REG_BASE + 0x204)
#define REG_AON_PMU_AUDIO_REQ (AONSYS_REG_BASE + 0x208)
#define REG_AON_PMU_AUDIO_STS (AONSYS_REG_BASE + 0x20c)
#define REG_AON_MEM_LP_MODE (AONSYS_REG_BASE + 0x210)
#define REG_AON_C910_DBG_MASK (AONSYS_REG_BASE + 0x214)
#define REG_AON_C910_L2CACHE (AONSYS_REG_BASE + 0x218)
#define REG_AON_BISR_CTRL (AONSYS_REG_BASE + 0x220)
#define REG_AON_EFUSE_PRELOAD_DONE (AONSYS_REG_BASE + 0x224)
#define REG_AON_GPIO_RTE (AONSYS_REG_BASE + 0x228)
#define REG_AON_PLL_DSKEW_LOCK (AONSYS_REG_BASE + 0x22c)
#define REG_AON_SRAM_AXI_CFG (AONSYS_REG_BASE + 0x230)
#define REG_AON_SRAM_AXI_ST (AONSYS_REG_BASE + 0x234)
#define REG_AON_SRAM_AXI_ERR_STS_0 (AONSYS_REG_BASE + 0x238)
#define REG_AON_SRAM_AXI_ERR_STS_1 (AONSYS_REG_BASE + 0x23c)
#define REG_AON_SRAM_AXI_ERR_STS_2 (AONSYS_REG_BASE + 0x240)
#define REG_AON_SRAM_AXI_ERR_STS_3 (AONSYS_REG_BASE + 0x244)
#define REG_AON_SRAM_AXI_ERR_STS_4 (AONSYS_REG_BASE + 0x248)
#define REG_AON_SE_MUX_LOCK (AONSYS_REG_BASE + 0x24c)
#define REG_AON_CPU_DBG_DIS_LOCK (AONSYS_REG_BASE + 0x270)
#define REG_AON_RESERVED_REG_4 (AONSYS_REG_BASE + 0x300)
#define REG_AON_RESERVED_REG_5 (AONSYS_REG_BASE + 0x304)
#define REG_AON_RESERVED_REG_6 (AONSYS_REG_BASE + 0x308)
#define REG_AON_RESERVED_REG_7 (AONSYS_REG_BASE + 0x30c)
#define REG_AON_RESERVED_REG_8 (AONSYS_REG_BASE + 0x400)
#define REG_AON_RESERVED_REG_9 (AONSYS_REG_BASE + 0x404)
#define REG_AON_RESERVED_REG_10 (AONSYS_REG_BASE + 0x408)
#define REG_AON_RESERVED_REG_11 (AONSYS_REG_BASE + 0x40c)
#define REG_AON_RESERVED_REG_12 (AONSYS_REG_BASE + 0x500)
#define REG_AON_RESERVED_REG_13 (AONSYS_REG_BASE + 0x504)
#define REG_AON_RESERVED_REG_14 (AONSYS_REG_BASE + 0x508)
#define REG_AON_RESERVED_REG_15 (AONSYS_REG_BASE + 0x50c)
#define REG_AON_RESERVED_REG_16 (AONSYS_REG_BASE + 0x600)
#define REG_AON_RESERVED_REG_17 (AONSYS_REG_BASE + 0x604)
#define REG_AON_RESERVED_REG_18 (AONSYS_REG_BASE + 0x608)
#define REG_AON_RESERVED_REG_19 (AONSYS_REG_BASE + 0x60c)
#define CPU_LP_MODE_DFLT_VAL 0x3ff
#define CHIP_LP_MODE_DFLT_VAL 0x0
#define AO_SERAM_TRN_DFLT_VAL 0x0
#define AO_SERAM_INT_DFLT_VAL 0x0
#define STR_SERAM_TRN_DFLT_VAL 0x0
#define STR_SERAM_INT_DFLT_VAL 0x0
#define STR_INDICATOR_0_DFLT_VAL 0x0
#define STR_INDICATOR_1_DFLT_VAL 0x0
#define STR_INDICATOR_2_DFLT_VAL 0x0
#define STR_INDICATOR_3_DFLT_VAL 0x0
#define PVTC_WR_LOCK_DFLT_VAL 0x0
#define PVTC_TS_ALARM_DFLT_VAL 0x0
#define PVTC_VM_ALARM_DFLT_VAL 0x0
#define PVTC_PD_ALARM_DFLT_VAL 0x0
#define E902_CNT_CLR_DFLT_VAL 0x0
#define E902_RST_ADDR_DFLT_VAL 0xffef8000
#define C906_RST_ADDR_L_DFLT_VAL 0xc0000000
#define C906_RST_ADDR_H_DFLT_VAL 0xff
#define RESERVED_REG_0_DFLT_VAL 0x0
#define RESERVED_REG_1_DFLT_VAL 0x0
#define RESERVED_REG_2_DFLT_VAL 0x0
#define RESERVED_REG_3_DFLT_VAL 0x0
#define AON_AHB_ADEXT_DFLT_VAL 0x0
#define RC_EN_DFLT_VAL 0x1
#define RC_FCAL_DFLT_VAL 0x77f
#define RC_MODE_DFLT_VAL 0x1
#define RC_READY_DFLT_VAL 0x0
#define ISO_CFG_DFLT_VAL 0x0
#define OCRAM_ERR_DFLT_VAL 0x0
#define TIMER_LINK_DFLT_VAL 0x0
#define PD_REQ_DFLT_VAL 0x0
#define PD_ISO_EN_SET_DFLT_VAL 0x0
#define PD_ISO_EN_CLR_DFLT_VAL 0x0
#define PD_SW_EN_SET_DFLT_VAL 0x0
#define PD_SW_EN_CLR_DFLT_VAL 0x0
#define PD_SW_ACK_DFLT_VAL 0x3fffff
#define PD_SW_CNT_EN_DFLT_VAL 0x0
#define PD_FSM_RST_DFLT_VAL 0x0
#define PD_INT_MASK_DFLT_VAL 0x3fffff
#define PD_FSM_STS_L_DFLT_VAL 0x0
#define PD_FSM_STS_H_DFLT_VAL 0x0
#define PD_INT_STS_DFLT_VAL 0x0
#define PD_INT_CLR_DFLT_VAL 0x0
#define PD_BLK0_SW_CNT_DFLT_VAL 0xff00ff
#define PD_BLK1_SW_CNT_DFLT_VAL 0xff00ff
#define PD_BLK2_SW_CNT_DFLT_VAL 0xff00ff
#define PD_BLK3_SW_CNT_DFLT_VAL 0xff00ff
#define PD_BLK4_SW_CNT_DFLT_VAL 0xff00ff
#define PD_BLK5_SW_CNT_DFLT_VAL 0xff00ff
#define PD_BLK6_SW_CNT_DFLT_VAL 0xff00ff
#define PD_BLK7_SW_CNT_DFLT_VAL 0xff00ff
#define PD_BLK8_SW_CNT_DFLT_VAL 0xff00ff
#define PD_BLK9_SW_CNT_DFLT_VAL 0xff00ff
#define PD_BLK10_SW_CNT_DFLT_VAL 0xff00ff
#define PD_BLK0_INTV_CNT_DFLT_VAL 0xff0ffff
#define PD_BLK1_INTV_CNT_DFLT_VAL 0xff0ffff
#define PD_BLK2_INTV_CNT_DFLT_VAL 0xff0ffff
#define PD_BLK3_INTV_CNT_DFLT_VAL 0xff0ffff
#define PD_BLK4_INTV_CNT_DFLT_VAL 0xff0ffff
#define PD_BLK5_INTV_CNT_DFLT_VAL 0xff0ffff
#define PD_BLK6_INTV_CNT_DFLT_VAL 0xff0ffff
#define PD_BLK7_INTV_CNT_DFLT_VAL 0xff0ffff
#define PD_BLK8_INTV_CNT_DFLT_VAL 0xff0ffff
#define PD_BLK9_INTV_CNT_DFLT_VAL 0xff0ffff
#define PD_BLK10_INTV_CNT_DFLT_VAL 0xff0ffff
#define AUDIO_PMU_REQ_DFLT_VAL 0x0
#define AUDIO_PMU_STS_DFLT_VAL 0x0
#define AUDIO_PMU_INTR_DFLT_VAL 0x0
#define PMU_AUDIO_REQ_DFLT_VAL 0x0
#define PMU_AUDIO_STS_DFLT_VAL 0x0
#define MEM_LP_MODE_DFLT_VAL 0x0
#define C910_DBG_MASK_DFLT_VAL 0x0
#define C910_L2CACHE_DFLT_VAL 0x0
#define BISR_CTRL_DFLT_VAL 0x0
#define EFUSE_PRELOAD_DONE_DFLT_VAL 0x0
#define GPIO_RTE_DFLT_VAL 0x0
#define PLL_DSKEW_LOCK_DFLT_VAL 0x0
#define SRAM_AXI_CFG_DFLT_VAL 0x0
#define SRAM_AXI_ST_DFLT_VAL 0x0
#define SRAM_AXI_ERR_STS_0_DFLT_VAL 0x0
#define SRAM_AXI_ERR_STS_1_DFLT_VAL 0x0
#define SRAM_AXI_ERR_STS_2_DFLT_VAL 0x0
#define SRAM_AXI_ERR_STS_3_DFLT_VAL 0x0
#define SRAM_AXI_ERR_STS_4_DFLT_VAL 0x0
#define SE_MUX_LOCK_DFLT_VAL 0x0
#define CPU_DBG_DIS_LOCK_DFLT_VAL 0x0
#define RESERVED_REG_4_DFLT_VAL 0x0
#define RESERVED_REG_5_DFLT_VAL 0x0
#define RESERVED_REG_6_DFLT_VAL 0x0
#define RESERVED_REG_7_DFLT_VAL 0x0
#define RESERVED_REG_8_DFLT_VAL 0x0
#define RESERVED_REG_9_DFLT_VAL 0x0
#define RESERVED_REG_10_DFLT_VAL 0x0
#define RESERVED_REG_11_DFLT_VAL 0x0
#define RESERVED_REG_12_DFLT_VAL 0x0
#define RESERVED_REG_13_DFLT_VAL 0x0
#define RESERVED_REG_14_DFLT_VAL 0x0
#define RESERVED_REG_15_DFLT_VAL 0x0
#define RESERVED_REG_16_DFLT_VAL 0x0
#define RESERVED_REG_17_DFLT_VAL 0x0
#define RESERVED_REG_18_DFLT_VAL 0x0
#define RESERVED_REG_19_DFLT_VAL 0x0
#endif

90
board/thead/light-c910/lpddr4/include/aonsys_rstget_reg_define.h Normal file
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@@ -0,0 +1,90 @@
//------------------------------------------------------------
// DONOT MODIFY THIS FILE
// generated by JISHENGJU automatically
//------------------------------------------------------------
#ifndef AONSYS_RSTGEN_REG_OFFSET_DEFINE_H
#define AONSYS_RSTGEN_REG_OFFSET_DEFINE_H
#define AONSYS_RSTGEN_REG_BASE 0xFFFFF44000
#define REG_AON_RST_CNT (AONSYS_RSTGEN_REG_BASE + 0x0 )
#define REG_AON_SYS_RST_CFG (AONSYS_RSTGEN_REG_BASE + 0x10 )
#define REG_AON_RTC_RST_CFG (AONSYS_RSTGEN_REG_BASE + 0x14 )
#define REG_AON_AOGPIO_RST_CFG (AONSYS_RSTGEN_REG_BASE + 0x18 )
#define REG_AON_AOI2C_RST_CFG (AONSYS_RSTGEN_REG_BASE + 0x1c )
#define REG_AON_PVTC_RST_CFG (AONSYS_RSTGEN_REG_BASE + 0x20 )
#define REG_AON_E902_RST_CFG (AONSYS_RSTGEN_REG_BASE + 0x24 )
#define REG_AON_AOTIMER_RST_CFG (AONSYS_RSTGEN_REG_BASE + 0x28 )
#define REG_AON_AOWDT_RST_CFG (AONSYS_RSTGEN_REG_BASE + 0x2c )
#define REG_AON_APSYS_RST_CFG (AONSYS_RSTGEN_REG_BASE + 0x30 )
#define REG_AON_NPUSYS_RST_CFG (AONSYS_RSTGEN_REG_BASE + 0x34 )
#define REG_AON_DDRSYS_RST_CFG (AONSYS_RSTGEN_REG_BASE + 0x38 )
#define REG_AON_AUDIO_RST_CFG (AONSYS_RSTGEN_REG_BASE + 0x3c )
#define REG_AON_BISR_RST_CFG (AONSYS_RSTGEN_REG_BASE + 0x50 )
#define REG_AON_DSP0_RST_CFG (AONSYS_RSTGEN_REG_BASE + 0x54 )
#define REG_AON_DSP1_RST_CFG (AONSYS_RSTGEN_REG_BASE + 0x58 )
#define REG_AON_GPU_RST_CFG (AONSYS_RSTGEN_REG_BASE + 0x5c )
#define REG_AON_VDEC_RST_CFG (AONSYS_RSTGEN_REG_BASE + 0x60 )
#define REG_AON_VENC_RST_CFG (AONSYS_RSTGEN_REG_BASE + 0x64 )
#define REG_AON_ADC_RST_CFG (AONSYS_RSTGEN_REG_BASE + 0x70 )
#define REG_AON_AUDGPIO_RST_CFG (AONSYS_RSTGEN_REG_BASE + 0x74 )
#define REG_AON_AOUART_RST_CFG (AONSYS_RSTGEN_REG_BASE + 0x78 )
#define REG_AON_RST_CLR_0 (AONSYS_RSTGEN_REG_BASE + 0x100 )
#define REG_AON_RST_CLR_1 (AONSYS_RSTGEN_REG_BASE + 0x104 )
#define REG_AON_RST_CLR_2 (AONSYS_RSTGEN_REG_BASE + 0x108 )
#define REG_AON_RST_CLR_3 (AONSYS_RSTGEN_REG_BASE + 0x10c )
#define REG_AON_RST_CLR_4 (AONSYS_RSTGEN_REG_BASE + 0x110 )
#define REG_AON_RST_STS_0 (AONSYS_RSTGEN_REG_BASE + 0x120 )
#define REG_AON_RST_STS_1 (AONSYS_RSTGEN_REG_BASE + 0x124 )
#define REG_AON_RST_STS_2 (AONSYS_RSTGEN_REG_BASE + 0x128 )
#define REG_AON_RST_STS_3 (AONSYS_RSTGEN_REG_BASE + 0x12c )
#define REG_AON_RST_STS_4 (AONSYS_RSTGEN_REG_BASE + 0x130 )
#define REG_AON_RST_REQ_EN_0 (AONSYS_RSTGEN_REG_BASE + 0x140 )
#define REG_AON_RST_REQ_EN_1 (AONSYS_RSTGEN_REG_BASE + 0x144 )
#define REG_AON_RST_REQ_EN_2 (AONSYS_RSTGEN_REG_BASE + 0x148 )
#define REG_AON_RST_REQ_EN_3 (AONSYS_RSTGEN_REG_BASE + 0x14c )
#define REG_AON_SRAM_AXI_RST_CFG (AONSYS_RSTGEN_REG_BASE + 0x11f4)
#define REG_AON_SE_RST_CFG (AONSYS_RSTGEN_REG_BASE + 0x160 )
#define RST_CNT_DFLT_VAL 0xf0f
#define SYS_RST_CFG_DFLT_VAL 0x0
#define RTC_RST_CFG_DFLT_VAL 0x3
#define AOGPIO_RST_CFG_DFLT_VAL 0x3
#define AOI2C_RST_CFG_DFLT_VAL 0x1
#define PVTC_RST_CFG_DFLT_VAL 0x1
#define E902_RST_CFG_DFLT_VAL 0x2
#define AOTIMER_RST_CFG_DFLT_VAL 0x3
#define AOWDT_RST_CFG_DFLT_VAL 0x1
#define APSYS_RST_CFG_DFLT_VAL 0x1
#define NPUSYS_RST_CFG_DFLT_VAL 0x1
#define DDRSYS_RST_CFG_DFLT_VAL 0x1
#define AUDIO_RST_CFG_DFLT_VAL 0x0
#define BISR_RST_CFG_DFLT_VAL 0x3
#define DSP0_RST_CFG_DFLT_VAL 0x1
#define DSP1_RST_CFG_DFLT_VAL 0x1
#define GPU_RST_CFG_DFLT_VAL 0x1
#define VDEC_RST_GEN_RST_CFG_DFLT_VAL 0x1
#define VENC_RST_CFG_DFLT_VAL 0x1
#define ADC_RST_CFG_DFLT_VAL 0x1
#define AUDGPIO_RST_CFG_DFLT_VAL 0x3
#define AOUART_RST_CFG_DFLT_VAL 0x3
#define RST_CLR_0_DFLT_VAL 0x0
#define RST_CLR_1_DFLT_VAL 0x0
#define RST_CLR_2_DFLT_VAL 0x0
#define RST_CLR_3_DFLT_VAL 0x0
#define RST_CLR_4_DFLT_VAL 0x0
#define RST_STS_0_DFLT_VAL 0x0
#define RST_STS_1_DFLT_VAL 0x0
#define RST_STS_2_DFLT_VAL 0x0
#define RST_STS_3_DFLT_VAL 0x0
#define RST_STS_4_DFLT_VAL 0x0
#define RST_REQ_EN_0_DFLT_VAL 0x11100
#define RST_REQ_EN_1_DFLT_VAL 0xbb000000
#define RST_REQ_EN_2_DFLT_VAL 0x0
#define RST_REQ_EN_3_DFLT_VAL 0x0
#define SRAM_AXI_RST_CFG_DFLT_VAL 0x5f
#define SE_RST_CFG_DFLT_VAL 0x1
#endif

2
board/thead/light-c910/lpddr4/include/common_lib.h
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@@ -7,6 +7,8 @@
#include "ddr_reg_define.h"
#include "ddr_sysreg_registers_struct.h"
#include "ddr_sysreg_registers.h"
#include "aonsys_reg_define.h"
#include "aonsys_rstget_reg_define.h"
#include "define_ddr.h"
#include "DWC_ddr_umctl2_c_struct.h"
#include "DWC_ddr_umctl2_header.h"

7
board/thead/light-c910/lpddr4/include/ddr_common_func.h
View File

@@ -15,6 +15,9 @@ enum DDR_BITWIDTH {
unsigned long get_ddr_density(void);
enum DDR_TYPE get_ddr_type(void);
int get_ddr_rank_number(void);
int get_ddr_freq(void);
enum DDR_BITWIDTH get_ddr_bitwidth(void);
void ddr_sysreg_wr(unsigned long int addr,unsigned int wr_data);
unsigned int ddr_sysreg_rd(unsigned long int addr);
@@ -49,4 +52,8 @@ void addrmap(int rank_num, enum DDR_BITWIDTH bits);
void ctrl_en(enum DDR_BITWIDTH bits);
void enable_auto_refresh(void);
void lpddr4_auto_selref(void);
int lpddr4_query_boundary(enum DDR_TYPE type, int rank_num, int speed,
enum DDR_BITWIDTH bits, unsigned long size);
int lpddr4_reinit_ctrl(enum DDR_TYPE type, int rank_num, int speed,
enum DDR_BITWIDTH bits, unsigned long size);
#endif // DDR_COMMON_FUNCE_H

38
board/thead/light-c910/lpddr4/include/ddr_retention.h Normal file
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@@ -0,0 +1,38 @@
#ifndef DDR_RETENTION_H
#define DDR_RETENTION_H
///data structure to store ddr misc register address, value
typedef struct Reg_Misc_Addr_Val {
uint32_t Address; ///< register address
uint32_t Value; ///< register value
} Reg_Misc_Addr_Val_t;
///data structure to store register address, value pairs
typedef struct Reg_Phy_Addr_Val {
uint32_t Address; ///< register address
uint16_t Value0; ///< register value phy0
uint16_t Value1; ///< register value phy1
} Reg_Phy_Addr_Val_t;
/// enumeration of instructions for PhyInit Register Interface
typedef enum {
saveRegs, ///< save(read) tracked register values
restoreRegs, ///< restore (write) saved register values
} regInstr;
// typedef struct Reg_Addr_Value {
// uint32_t reg_num;
// Reg_Addr_Val_t reg[0];
// } Reg_Addr_Value_t;
typedef struct Ddr_Reg_Config {
uint32_t misc_reg_num;
uint32_t phy_reg_num;
uint8_t ddr_rank;
uint8_t reserve[55];
} Ddr_Reg_Config_t;
int dwc_ddrphy_phyinit_regInterface(regInstr myRegInstr);
void dwc_ddr_misc_regu_save(void);
#endif

604
board/thead/light-c910/lpddr4/src/ddr_common_func.c
View File

@@ -2,9 +2,14 @@
#include <linux/sizes.h>
#include "../include/common_lib.h"
#include "../include/ddr_common_func.h"
#include "../include/ddr_retention.h"
DDR_SYSREG_REG_SW_REG_S ddr_sysreg;
#ifdef CONFIG_DDR_MSG
#define DDR_DEBUG(x) printf(x)
#endif
#ifndef CONFIG_DDR_RANK_SIZE
#define CONFIG_DDR_RANK_SIZE SZ_4G
#endif
@@ -14,6 +19,9 @@ unsigned long get_ddr_density() {
#ifdef CONFIG_DDR_DUAL_RANK
mul = 2;
#endif
#ifdef CONFIG_DDR_DDP
mul *= 2;
#endif
#ifdef CONFIG_DDR_H32_MODE
div = 2;
#endif
@@ -31,6 +39,44 @@ enum DDR_TYPE get_ddr_type() {
#endif // #ifdef CONFIG_LPDDR4X
}
int get_ddr_rank_number() {
#ifdef CONFIG_DDR_SINGLE_RANK
return 1;
#elif defined CONFIG_DDR_DUAL_RANK
return 2;
#else
#ifdef CONFIG_DDR_MSG
DDR_DEBUG("unsupported ddr rank type!!!\n");
#endif
return NULL;
#endif
}
int get_ddr_freq() {
#ifdef CONFIG_DDR_4266
return 4266;
#elif CONFIG_DDR_3733
return 3733;
#elif CONFIG_DDR_3200
return 3200;
#elif CONFIG_DDR_2133
return 2133;
#else
printf("unsupport lpddr4 freq!!!\n");
return -1;
#endif
}
enum DDR_BITWIDTH get_ddr_bitwidth() {
#ifdef CONFIG_DDR_H32_MODE
return DDR_BITWIDTH_32;
#elif CONFIG_DDR_H16_MODE
return DDR_BITWIDTH_16;
#else
return DDR_BITWIDTH_64;
#endif
}
void ddr_sysreg_wr(unsigned long int addr,unsigned int wr_data) {
wr(addr+DDR_SYSREG_BADDR,wr_data);
}
@@ -101,75 +147,114 @@ unsigned int ddr_phy_reg_rd(unsigned long int addr) {
void lp4_mrw(int addr, int wdata,int dch,int rank) {
DWC_DDR_UMCTL2_C_STRUCT_REG_S umctl2_reg;
uint32_t val_t0,val_t1;
if(dch==0) {
umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32 = rd(MRCTRL0);
//umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_addr = addr; //do not care for lp4
umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_rank = rank;//rank0 only
umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_type = 0;//write
wr(MRCTRL0,umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32);
while ((rd(MRSTAT) & 0x1) == 0x1);
umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32 = rd(MRCTRL0);
//umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_addr = addr; //do not care for lp4
umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_rank = rank;//rank0 only
umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_type = 0;//write
wr(MRCTRL0, umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32);
umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32 = rd(MRCTRL1);
umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.mr_data = (addr<<8) | (wdata&0xFF);
wr(MRCTRL1,umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32);
umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32 = rd(MRCTRL0);
umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_wr = 1;//trigger wr/rd
wr(MRCTRL0,umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32);
umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32 = rd(MRCTRL1);
umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.mr_data = (addr << 8) | (wdata & 0xFF);
wr(MRCTRL1, umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32);
umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32 = rd(MRCTRL1);
umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.mr_data = (addr << 8) | (wdata & 0xFF);
wr(MRCTRL1, umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32);
umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32 = rd(MRCTRL0);
umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_wr = 1;//trigger wr/rd
wr(MRCTRL0, umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32);
//udelay(10);
//delay 5us
val_t0=rd(0xFFF4D004);
val_t1=rd(0xFFF4D004);
while((val_t0-val_t1)<200){val_t1=rd(0xFFF4D004);};
while ((rd(MRSTAT) & 0x1) == 0x1);
}
else {
umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32 = rd(MRCTRL0_DCH1);
//umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_addr = addr; //do not care for lp4
umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_rank = rank;//rank0 only
umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_type = 0;//write
wr(MRCTRL0_DCH1,umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32);
while ((rd(MRSTAT_DCH1) & 0x1) == 0x1);
umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32 = rd(MRCTRL0_DCH1);
//umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_addr = addr; //do not care for lp4
umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_rank = rank;//rank0 only
umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_type = 0;//write
wr(MRCTRL0_DCH1, umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32);
umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32 = rd(MRCTRL1_DCH1);
umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.mr_data = (addr<<8) | (wdata&0xFF);
wr(MRCTRL1_DCH1,umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32);
umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32 = rd(MRCTRL0_DCH1);
umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_wr = 1;//trigger wr/rd
wr(MRCTRL0_DCH1,umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32);
}
umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32 = rd(MRCTRL1_DCH1);
umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.mr_data = (addr << 8) | (wdata & 0xFF);
wr(MRCTRL1_DCH1, umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32);
umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32 = rd(MRCTRL1_DCH1);
umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.mr_data = (addr << 8) | (wdata & 0xFF);
wr(MRCTRL1_DCH1, umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32);
umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32 = rd(MRCTRL0_DCH1);
umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_wr = 1;//trigger wr/rd
wr(MRCTRL0_DCH1, umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32);
//udelay(10);
//delay 5us
val_t0=rd(0xFFF4D004);
val_t1=rd(0xFFF4D004);
while((val_t0-val_t1)<200){val_t1=rd(0xFFF4D004);};
while ((rd(MRSTAT_DCH1) & 0x1) == 0x1);
}
}
int lp4_mrr(int addr,int dch,int rank) {
DWC_DDR_UMCTL2_C_STRUCT_REG_S umctl2_reg;
if(dch==0) {
umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32 = rd(MRCTRL0);
//umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_addr = addr; //do not care for lp4
umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_rank = rank;//rank0 only
umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_type = 1;//read
wr(MRCTRL0,umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32);
umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32 = rd(MRCTRL0);
//umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_addr = addr; //do not care for lp4
umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_rank = rank;//rank0 only
umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_type = 1;//read
wr(MRCTRL0, umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32);
umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32 = rd(MRCTRL1);
umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.mr_data = addr<<8;
wr(MRCTRL1,umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32);
umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32 = rd(MRCTRL0);
umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_wr = 1;//trigger wr/rd
wr(MRCTRL0,umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32);
umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32 = rd(MRCTRL1);
umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.mr_data = addr << 8;
wr(MRCTRL1, umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32);
umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32 = rd(MRCTRL1);
return (umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.mr_data & 0xFF);
umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32 = rd(MRCTRL1);
umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.mr_data = addr << 8;
wr(MRCTRL1, umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32);
umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32 = rd(MRCTRL0);
umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_wr = 1;//trigger wr/rd
wr(MRCTRL0, umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32);
udelay(20);
while ((rd(MRSTAT) & 0x1) == 0x1);
return ddr_sysreg_rd(MRR_STS_CH0);
}
else {
umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32 = rd(MRCTRL0_DCH1);
//umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_addr = addr; //do not care for lp4
umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_rank = rank;//rank0 only
umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_type = 1;//read
wr(MRCTRL0_DCH1,umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32);
umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32 = rd(MRCTRL0_DCH1);
//umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_addr = addr; //do not care for lp4
umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_rank = rank;//rank0 only
umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_type = 1;//read
wr(MRCTRL0_DCH1, umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32);
umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32 = rd(MRCTRL1_DCH1);
umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.mr_data = addr<<8;
wr(MRCTRL1_DCH1,umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32);
umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32 = rd(MRCTRL0_DCH1);
umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_wr = 1;//trigger wr/rd
wr(MRCTRL0_DCH1,umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32);
umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32 = rd(MRCTRL1_DCH1);
umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.mr_data = addr << 8;
wr(MRCTRL1_DCH1, umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32);
umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32 = rd(MRCTRL1_DCH1);
return (umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.mr_data & 0xFF);
umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32 = rd(MRCTRL1_DCH1);
umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.mr_data = addr << 8;
wr(MRCTRL1_DCH1, umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32);
umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32 = rd(MRCTRL0_DCH1);
umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_wr = 1;//trigger wr/rd
wr(MRCTRL0_DCH1, umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32);
udelay(20);
while ((rd(MRSTAT_DCH1) & 0x1) == 0x1);
return ddr_sysreg_rd(MRR_STS_CH1);
}
}
@@ -233,15 +318,15 @@ unsigned int ddr_phy_reg_rd(unsigned long int addr) {
if(port & 0x4) wr(PCTRL_2,0);
if(port & 0x8) wr(PCTRL_3,0);
if(port & 0x10) wr(PCTRL_4,0);
if(port & 0x1F) { //at least one port is not disabled
wr(DBG1,0);
wr(DBG1_DCH1,0);
while (rd(PSTAT) != 0x0);
if ((port & 0x1F) == 0x1F) { //all ports are disabled
wr(DBG1, 2);
wr(DBG1_DCH1, 2);
}
else { //all ports are disabled
wr(DBG1,3);
wr(DBG1_DCH1,3);
else { //at least one port is not disabled
wr(DBG1, 0);
wr(DBG1_DCH1, 0);
}
}
void enable_axi_port(int port) {
@@ -454,7 +539,7 @@ if(bits==64) {
wr(DFITMG0,0x05a3820e);//[28:24] dft_t_ctrl_delay [22:16] dfi_t_rddate_en=RL-5
#endif
wr(DFITMG1,0x000c0303);
wr(DFILPCFG0,0x0351a001);
wr(DFILPCFG0,0x0351a101); //[8]=1: enable dfi lp mode during selfref
//wr(DFIUPD0,0x00400018); //[31:30]=0 use ctrlupd enable
//wr(DFIUPD1,0x00b700c4);
//wr(DFIUPD2,0x00000000);//[31]=0 disable phy ctrlupdate
@@ -554,7 +639,7 @@ if(bits==64) {
wr(DFITMG0,0x059f820c);//[28:24] dfi_t_ctrl_delay
#endif
wr(DFITMG1,0x000c0303);//dfi_t_wrdata_delay=tctrl+6+BL/2+trainedTdqsdly=24, may need take care cmd pipe
wr(DFILPCFG0,0x0351a001);
wr(DFILPCFG0,0x0351a101); //[8]=1: enable dfi lp mode during selfref
//wr(DFIUPD0,0xc0400018);
//wr(DFIUPD1,0x00b700c4);
//wr(DFIUPD2,0x80000000);
@@ -642,7 +727,7 @@ if(bits==64) {
wr(DFITMG0,0x059b820a); //[22:16] dfi_t_rddate_en=RL-5
#endif
wr(DFITMG1,0x000b0303);
wr(DFILPCFG0,0x0351a001);
wr(DFILPCFG0,0x0351a101); //[8]=1: enable dfi lp mode during selfref
//wr(DFIUPD0,0xc0400018);
//wr(DFIUPD1,0x00b700c4);
//wr(DFIUPD2,0x80000000);
@@ -727,7 +812,7 @@ if(bits==64) {
wr(ZQCTL2,0x00000000);
wr(DFITMG0,0x048f8206);
wr(DFITMG1,0x000b0303);
wr(DFILPCFG0,0x0351a001);
wr(DFILPCFG0,0x0351a101); //[8]=1: enable dfi lp mode during selfref
//wr(DFIUPD0,0xc0400018);
//wr(DFIUPD1,0x00b700c4);
//wr(DFIUPD2,0x80000000);
@@ -853,17 +938,28 @@ if(bits==64) {
#ifdef CONFIG_DDR_MSG
printf("DDR 32bit mode\n");
#endif
wr(ADDRMAP0,0x001f001f); //
if(rank_num==2) {
wr(ADDRMAP0,0x001f0017);//4GB
#ifdef CONFIG_DDR_DDP
wr(ADDRMAP0,0x001f0018);//max 8GB
#else
wr(ADDRMAP0,0x001f0017); //4GB
#endif
}
else {
wr(ADDRMAP0,0x001f001f); //cs_bit0: NULL
}
wr(ADDRMAP1,0x00080808); //bank +2
wr(ADDRMAP2,0x00000000); //col b5+5 ~ col b2 +2
wr(ADDRMAP3,0x00000000); //col b9 ~ col b6
wr(ADDRMAP4,0x00001f1f); //col b11~ col b10
wr(ADDRMAP5,0x070f0707); //row_b11 row b2_10 row b1 row b0 +6
wr(ADDRMAP6,0x07070707); //max row 15
wr(ADDRMAP7,0x00000f0f);
wr(ADDRMAP6,0x07070707); //row 15
wr(ADDRMAP7,0x00000f0f); //row16: NULL
#ifdef CONFIG_DDR_DDP
if(rank_num==2) {
wr(ADDRMAP7,0x00000f07); //max row16
}
#endif
wr(ADDRMAP9,0x07070707);
wr(ADDRMAP10,0x07070707);
wr(ADDRMAP11,0x00000007);
@@ -871,17 +967,25 @@ if(bits==64) {
#ifdef CONFIG_DDR_MSG
printf("DDR 64bit mode, 256B interleaving\n");
#endif
wr(ADDRMAP0,0x0004001f); // +2
wr(ADDRMAP0,0x0004001f); //cs_bit0: NULL
if(rank_num==2) {
wr(ADDRMAP0,0x00040018);//8GB
#ifdef CONFIG_DDR_DDP
wr(ADDRMAP0,0x00040019);//max 16GB
#else
wr(ADDRMAP0,0x00040018);//8GB
#endif
}
wr(ADDRMAP1,0x00090909); //bank +2
wr(ADDRMAP2,0x00000000); //col b5+5 ~ col b2 +2
wr(ADDRMAP3,0x01010101); //col b9 ~ col b6
wr(ADDRMAP4,0x00001f1f); //col b11~ col b10
wr(ADDRMAP5,0x080f0808); //row_b11 row b2_10 row b1 row b0 +6
wr(ADDRMAP6,0x08080808);
wr(ADDRMAP7,0x00000f0f);
wr(ADDRMAP6,0x08080808); //row15
#ifdef CONFIG_DDR_DDP
wr(ADDRMAP7,0x00000f08); //row16
#else
wr(ADDRMAP7,0x00000f0f); //row16: NULL
#endif
wr(ADDRMAP9,0x08080808);
wr(ADDRMAP10,0x08080808);
wr(ADDRMAP11,0x00000008);
@@ -890,6 +994,156 @@ if(bits==64) {
}
}
#define MEMSIZE_MIN_MB (1*1024)
#define MEMSIZE_MAX_MB (16*1024)
#define UNIT_MB (1024*1024)
int lpddr4_query_boundary(enum DDR_TYPE type, int rank_num, int speed,
enum DDR_BITWIDTH bits, unsigned long size)
{
if ((size < (unsigned long)MEMSIZE_MIN_MB*UNIT_MB) ||
(size > (unsigned long)MEMSIZE_MAX_MB*UNIT_MB))
goto err_ret;
if (bits == DDR_BITWIDTH_32) {// only phy0
if (rank_num == 2) {
if (size == 0x80000000) //2GB
goto ret_ok;
else if (size == 0x100000000) //4GB
goto ret_ok;
else if (size == 0x200000000) //8GB
goto ret_ok;
else
goto err_ret;
}
else { // single rank
if (size == 0x40000000) //1GB
goto ret_ok;
else if (size == 0x80000000) //2GB
goto ret_ok;
else if (size == 0x100000000) //4GB
goto ret_ok;
else
goto err_ret;
}
}
else if (bits == DDR_BITWIDTH_64) { // phy0+phy1
if (rank_num == 2) {
if (size == 0x100000000) //4GB
goto ret_ok;
else if (size == 0x200000000) //8GB
goto ret_ok;
else if (size == 0x400000000) //16GB
goto ret_ok;
else
goto err_ret;
}
else { // single rank
if (size == 0x80000000) //2GB
goto ret_ok;
else if (size == 0x100000000) //4GB
goto ret_ok;
else if (size == 0x200000000) //8GB
goto ret_ok;
else
goto err_ret;
}
}
else {
goto err_ret;
}
ret_ok:
return 0;
err_ret:
return -1;
}
int adjust_ddr_addrmap(enum DDR_TYPE type, int rank_num, int speed,
enum DDR_BITWIDTH bits, unsigned long size)
{
if (lpddr4_query_boundary(type, rank_num, speed, bits, size) < 0)
goto err_ret;
if (bits == DDR_BITWIDTH_32) {// only phy0
if (rank_num == 2) {
if (size == 0x80000000) {//2GB
wr(ADDRMAP0,0x001f0016); // cs_bit0: HIF[28]
wr(ADDRMAP6,0x0f070707); // row15: NULL
wr(ADDRMAP7,0x00000f0f); // row16: NULL
}
else if (size == 0x100000000) {//4GB
wr(ADDRMAP0,0x001f0017); // cs_bit0: HIF[29]
wr(ADDRMAP6,0x07070707); // row15: HIF[28]
wr(ADDRMAP7,0x00000f0f); // row16: NULL
}
else if (size == 0x200000000) {//8GB
wr(ADDRMAP0,0x001f0018); // cs_bit0: HIF[30]
wr(ADDRMAP6,0x07070707); // row15: HIF[28]
wr(ADDRMAP7,0x00000f07); // row16: HIF[29]
}
}
else { // single rank
wr(ADDRMAP0,0x001f001f); // cs_bit0: NULL
if (size == 0x40000000) {//1GB
wr(ADDRMAP6,0x0f070707); // row15: NULL
wr(ADDRMAP7,0x00000f0f); // row16: NULL
}
else if (size == 0x80000000) {//2GB
wr(ADDRMAP6,0x07070707); // row15: HIF[28]
wr(ADDRMAP7,0x00000f0f); // row16: NULL
}
else if (size == 0x100000000) {//4GB
wr(ADDRMAP6,0x07070707); // row15: HIF[28]
wr(ADDRMAP7,0x00000f07); // row16: HIF[29]
}
}
}
else if (bits == DDR_BITWIDTH_64) { // phy0+phy1
if (rank_num == 2) {
if (size == 0x100000000) {//4GB
wr(ADDRMAP0,0x00040017); // cs_bit0: HIF[29]
wr(ADDRMAP6,0x0f080808); // row15: NULL
wr(ADDRMAP7,0x00000f0f); // row16: NULL
}
else if (size == 0x200000000) {//8GB
wr(ADDRMAP0,0x00040018); // cs_bit0: HIF[30]
wr(ADDRMAP6,0x08080808); // row15: HIF[29]
wr(ADDRMAP7,0x00000f0f); // row16: NULL
}
else if (size == 0x400000000) {//16GB
wr(ADDRMAP0,0x00040019); // cs_bit0: HIF[31]
wr(ADDRMAP6,0x08080808); // row15: HIF[29]
wr(ADDRMAP7,0x00000f08); // row16: HIF[30]
}
}
else { // single rank
wr(ADDRMAP0,0x0004001f); // cs_bit0: NULL
if (size == 0x80000000) {//2GB
wr(ADDRMAP6,0x0f080808); // row15: NULL
wr(ADDRMAP7,0x00000f0f); // row16: NULL
}
else if (size == 0x100000000) {//4GB
wr(ADDRMAP6,0x08080808); // row15: HIF[29]
wr(ADDRMAP7,0x00000f0f); // row16: NULL
}
else if (size == 0x200000000) {//8GB
wr(ADDRMAP6,0x08080808); // row15: HIF[29]
wr(ADDRMAP7,0x00000f08); // row16: HIF[30]
}
}
}
else {
// nothing
}
return 0;
err_ret:
printf("unsupport memsize %ld\n", size);
return -1;
}
void quasi_reg_write(unsigned long int reg,int wdata) {
DWC_DDR_UMCTL2_C_STRUCT_REG_S umctl2_reg;
@@ -1004,11 +1258,11 @@ void lpddr4_enter_selfrefresh(int pwdn_en,int dis_dram_clk,int mode) {
umctl2_reg.dwc_ddr_umctl2_c_struct_stat.u32 = rd(STAT_DCH1);
if(pwdn_en) {
while( umctl2_reg.dwc_ddr_umctl2_c_struct_stat.selfref_state != 2) //wait sdram enter selfrefresh-powerdown state
umctl2_reg.dwc_ddr_umctl2_c_struct_stat.u32 = rd(STAT);
umctl2_reg.dwc_ddr_umctl2_c_struct_stat.u32 = rd(STAT_DCH1);
}
else {
while( umctl2_reg.dwc_ddr_umctl2_c_struct_stat.selfref_state != 1) //wait sdram enter selfrefresh state
umctl2_reg.dwc_ddr_umctl2_c_struct_stat.u32 = rd(STAT);
umctl2_reg.dwc_ddr_umctl2_c_struct_stat.u32 = rd(STAT_DCH1);
}
#ifdef CONFIG_DDR_MSG
printf("[lpddr4_enter_selfrefresh]: CH1 STAT is :%x after enter selfrefresh state\n",umctl2_reg.dwc_ddr_umctl2_c_struct_stat.u32);
@@ -1044,7 +1298,8 @@ void lpddr4_auto_ps_en(int pwdn_en,int selfref_en,int clock_auto_disable ) {
//ddr_sysreg_wr(DDR_CFG0,0x1ff0);
//ddr_sysreg_wr(DDR_CFG0,0x1ff0);
ddr_sysreg.ddr_sysreg_registers_struct_ddr_cfg0.u32 = ddr_sysreg_rd(DDR_CFG0);
ddr_sysreg.ddr_sysreg_registers_struct_ddr_cfg0.rg_ctl_ddr_usw_rst_reg |= 0x1F2;
//ddr_sysreg.ddr_sysreg_registers_struct_ddr_cfg0.rg_ctl_ddr_usw_rst_reg |= 0x1F2;
ddr_sysreg.ddr_sysreg_registers_struct_ddr_cfg0.rg_ctl_ddr_usw_rst_reg |= 0x1FA;
ddr_sysreg_wr(DDR_CFG0,ddr_sysreg.ddr_sysreg_registers_struct_ddr_cfg0.u32);
}
@@ -1064,7 +1319,7 @@ void dfi_freq_change(int dfi_freq,int skip_dram_init) {
#ifdef CONFIG_DDR_MSG
printf("[dfi_freq_change]: start dfi_freq_change, target dfi_freq is %x \n",dfi_freq);
#endif
wr(DBG1,3);
//wr(DBG1,3);
umctl2_reg.dwc_ddr_umctl2_c_struct_swctl.u32 = rd(SWCTL);
umctl2_reg.dwc_ddr_umctl2_c_struct_swctl.sw_done = 0;
wr(SWCTL,umctl2_reg.dwc_ddr_umctl2_c_struct_swctl.u32);
@@ -1075,7 +1330,6 @@ void dfi_freq_change(int dfi_freq,int skip_dram_init) {
umctl2_reg.dwc_ddr_umctl2_c_struct_dfimisc.u32 = rd(DFIMISC);
umctl2_reg.dwc_ddr_umctl2_c_struct_dfimisc.dfi_frequency = dfi_freq;
umctl2_reg.dwc_ddr_umctl2_c_struct_dfimisc.dfi_init_start = 0x1;
umctl2_reg.dwc_ddr_umctl2_c_struct_dfimisc.dfi_init_complete_en = 0;
wr(DFIMISC,umctl2_reg.dwc_ddr_umctl2_c_struct_dfimisc.u32);
@@ -1086,15 +1340,28 @@ void dfi_freq_change(int dfi_freq,int skip_dram_init) {
while( umctl2_reg.dwc_ddr_umctl2_c_struct_swstat.sw_done_ack == 0)
umctl2_reg.dwc_ddr_umctl2_c_struct_swctl.u32 = rd(SWSTAT);
wr(SWCTL,0x0);
umctl2_reg.dwc_ddr_umctl2_c_struct_dfimisc.u32 = rd(DFIMISC);
umctl2_reg.dwc_ddr_umctl2_c_struct_dfimisc.dfi_init_start = 0x1;
wr(DFIMISC,umctl2_reg.dwc_ddr_umctl2_c_struct_dfimisc.u32);
wr(SWCTL,0x1);
while(rd(SWSTAT)!=0x00000001);
rdata = rd(DFISTAT);
while ((rdata & 0x1) != 0) //wait dfi_init_complete = 0
rdata = rd(DFISTAT);
#ifndef CONFIG_DDR_H32_MODE
rdata = rd(DCH1_DFISTAT);
while((rdata & 0x1) != 0) //wait dfi_init_complete = 0
rdata = rd(DFISTAT);
rdata = rd(DCH1_DFISTAT);
#endif
//change dfi clk freq here
//pull down dfi_init_start
umctl2_reg.dwc_ddr_umctl2_c_struct_swctl.u32 = rd(SWCTL);
umctl2_reg.dwc_ddr_umctl2_c_struct_swctl.sw_done = 0;
wr(SWCTL,umctl2_reg.dwc_ddr_umctl2_c_struct_swctl.u32);
wr(SWCTL, umctl2_reg.dwc_ddr_umctl2_c_struct_swctl.u32);
umctl2_reg.dwc_ddr_umctl2_c_struct_dfimisc.u32 = rd(DFIMISC);
umctl2_reg.dwc_ddr_umctl2_c_struct_dfimisc.dfi_init_start = 0;
wr(DFIMISC,umctl2_reg.dwc_ddr_umctl2_c_struct_dfimisc.u32);
@@ -1108,9 +1375,17 @@ void dfi_freq_change(int dfi_freq,int skip_dram_init) {
umctl2_reg.dwc_ddr_umctl2_c_struct_dfistat.u32 = rd(DFISTAT);
while(umctl2_reg.dwc_ddr_umctl2_c_struct_dfistat.dfi_init_complete == 0)
umctl2_reg.dwc_ddr_umctl2_c_struct_dfistat.u32 = rd(DFISTAT);
wr(DBG1,0);
//wait dfi_init_complete = 1
#ifndef CONFIG_DDR_H32_MODE
umctl2_reg.dwc_ddr_umctl2_c_struct_dfistat.u32 = rd(DCH1_DFISTAT);
while(umctl2_reg.dwc_ddr_umctl2_c_struct_dfistat.dfi_init_complete == 0)
umctl2_reg.dwc_ddr_umctl2_c_struct_dfistat.u32 = rd(DCH1_DFISTAT);
#endif
//wr(DBG1,0);
#ifdef CONFIG_DDR_MSG
printf("[dfi_freq_change]: dfi_freq_change, end \n",dfi_freq);
printf("[dfi_freq_change]: dfi_freq_change, end \n");
#endif
}
@@ -1135,3 +1410,168 @@ void lpddr4_auto_selref(void)
wr(PWRCTL,0x0000000b); //[3] dfi_dram_clk_disable [1] powerdown_en [0]serref_en
wr(DCH1_PWRCTL,0x0000000b);
}
void ctrl_en_lp3_exit(enum DDR_BITWIDTH bits) {
//skip DRAM init, because this has done
wr(SWCTL,0x00000000);
wr(INIT0,0xc0020002);
wr(SWCTL,0x00000001);
while(rd(SWSTAT)!=0x00000001);
//dfi frequency change proto ,to PS0
wr(SWCTL,0x00000000);
wr(DFIMISC,0x00000000);// [5]dfi_freq=0x0
wr(SWCTL,0x00000001);
while(rd(SWSTAT)!=0x00000001);
wr(SWCTL,0x00000000);
wr(DFIMISC,0x00000020);// [5]dfi_init_start=0x1
wr(SWCTL,0x00000001);
while(rd(SWSTAT)!=0x00000001);
while(rd(DFISTAT)!=0x00000001); //polling dfi_init_complete
if(bits==64) {
while(rd(DCH1_DFISTAT)!=0x00000001);
}
wr(SWCTL,0x00000000);
wr(DFIMISC,0x00000000);
wr(SWCTL,0x00000001);
while(rd(SWSTAT)!=0x00000001);
wr(SWCTL,0x00000000);
wr(DFIMISC,0x00000001);
wr(SWCTL,0x00000001);
while(rd(SWSTAT)!=0x00000001);
//for low power,
wr(SWCTL,0x00000000);
wr(PWRCTL,0x0000000a); //[3] dfi_dram_clk_disable [1] powerdown_en
wr(DCH1_PWRCTL,0x0000000a);
wr(SWCTL,0x00000001);
while (rd(SWSTAT) != 0x00000001);
//detect until umctrl into normal state
while (rd(STAT) != 0x00000001);
if(bits==64) {
while(rd(DCH1_STAT) != 0x00000001);
}
//en phy master proto
wr(DFIPHYMSTR,0x14000001);
#ifdef CONFIG_DDR_MSG
DDR_DEBUG("DFIPHYMSTR is %0x \n", rd(DFIPHYMSTR));
DDR_DEBUG("DFIUPD0 is %0x \n", rd(DFIUPD0));
DDR_DEBUG("DFIUPD1 is %0x \n", rd(DFIUPD1));
DDR_DEBUG("ZQCTL0 is %0x \n", rd(ZQCTL0));
DDR_DEBUG("ADDRMAP0 is %0x \n", rd(ADDRMAP0));
DDR_DEBUG("ADDRMAP1 is %0x \n", rd(ADDRMAP1));
#endif
}
int lpddr4_reinit_ctrl(enum DDR_TYPE type, int rank_num, int speed,
enum DDR_BITWIDTH bits, unsigned long size)
{
int ret;
unsigned int rdata;
//a.
ddr_sysreg_wr(DDR_CFG1, 0xa000011f); //remove core clock after xx
wr(PWRCTL, 0x00000000); //[3] dfi_dram_clk_disable [1] powerdown_en [0]serref_en
wr(DCH1_PWRCTL, 0x00000000);
// use phy value stored in spl
//dwc_ddrphy_phyinit_regInterface(saveRegs);
//b.dis axi port
disable_axi_port(0x1f);
while (rd(PSTAT) != 0x0);
#ifdef CONFIG_DDR_MSG
DDR_DEBUG("Axi prot idle\n");
#endif
wr(DFIPHYMSTR, 0x14000000);
//check status.
while ((rd(STAT) & 0x3) == 0x03);
#ifndef CONFIG_DDR_H32_MODE
while ((rd(STAT_DCH1) & 0x3) == 0x03);
#endif
//c.poll cam empty flag
while ((rd(DBGCAM) & 0x36000000) != 0x36000000);
//d.save phy regs
//e.SRE
lpddr4_enter_selfrefresh(1, 0, 0);
//f.LP3 enter
dfi_freq_change(0x1f, 0x3);
//g.PwrOk disassert
rdata = ddr_sysreg_rd(DDR_CFG0);
rdata &= ~(0x1 << 6);
ddr_sysreg_wr(DDR_CFG0, rdata); //Pwrokin dessert
//p.phy reset
rdata = ddr_sysreg_rd(DDR_CFG0);
rdata &= ~(0x1 << 7);
rdata &= 0x0;
ddr_sysreg_wr(DDR_CFG0, rdata); //Phy reset .DDR_CFG0 ALL reset
//r.ddr core reset
rdata = ddr_sysreg_rd(DDR_CFG0);
rdata &= ~(0x1 << 5);
ddr_sysreg_wr(DDR_CFG0, rdata); //ctrl sw reset
//s.pwr ok assert
rdata = ddr_sysreg_rd(DDR_CFG0);
rdata |= (0x1 << 6);
ddr_sysreg_wr(DDR_CFG0, rdata); //Pwrokin dessert
//t.ctrl init
//dwc_umctl_init_skip_traing(type, rank_num, speed, bits);
ddr_sysreg_wr(DDR_CFG0, 0x50); // release apb presetn
ddr_sysreg_wr(DDR_CFG0, 0x50);
ddr_sysreg_wr(DDR_CFG0, 0x50);
if (bits == 32) {
ddr_sysreg_wr(DDR_CFG0, 0x52);
}
ctrl_init(rank_num, speed);
addrmap(rank_num, bits);
ret = adjust_ddr_addrmap(type, rank_num, speed, bits, size);
// msic regu restore for str
dwc_ddr_misc_regu_save();
de_assert_other_reset_ddr(); //after this step, only PwrOk is staill low
dq_pinmux(bits);
//u.phy restor
dwc_ddrphy_phyinit_regInterface(restoreRegs);
//v.ctrl en ,hs
ctrl_en_lp3_exit(bits);
//w.SRE
lpddr4_selfrefresh_exit(0);
//y.en auto refresh
enable_auto_refresh();
//x.en axi port
enable_axi_port(0x1f);
wr(DFIPHYMSTR, 0x14000001);
lpddr4_auto_selref();
if(rd(PSTAT))
{
#ifdef CONFIG_DDR_MSG
DDR_DEBUG("***** DDR busy in LP3 Mode *****\n");
#endif
}else{
#ifdef CONFIG_DDR_MSG
DDR_DEBUG("***** AXI port idle *****\n");
#endif
}
return ret;
}

1080
board/thead/light-c910/lpddr4/src/ddr_retention.c Normal file
View File

File diff suppressed because it is too large Load Diff

26
board/thead/light-c910/lpddr4/src/lpddr4_init.c
View File

@@ -1,6 +1,7 @@
#include "../include/common_lib.h"
#include "../include/pinmux.h"
#include "../include/ddr_common_func.h"
#include "../include/ddr_retention.h"
#include "../include/lpddr4_init.h"
extern void lp4_phy_train1d2d(enum DDR_TYPE type, int speed, enum DDR_BITWIDTH bits);
@@ -26,11 +27,34 @@ void lpddr4_init(enum DDR_TYPE type, int rank_num, int speed, enum DDR_BITWIDTH
lp4_phy_train1d2d(type, speed, bits);
dwc_ddrphy_phyinit_regInterface(saveRegs);
ctrl_en(bits);
enable_axi_port(0x1f);
enable_auto_refresh();
lpddr4_auto_selref();
}
int fixup_ddr_addrmap(unsigned long size)
{
enum DDR_TYPE type = get_ddr_type();
int rank_num = get_ddr_rank_number();
int speed = get_ddr_freq();
enum DDR_BITWIDTH bits = get_ddr_bitwidth();
return lpddr4_reinit_ctrl(type, rank_num, speed, bits, size);
}
int query_ddr_boundary(unsigned long size)
{
enum DDR_TYPE type = get_ddr_type();
int rank_num = get_ddr_rank_number();
int speed = get_ddr_freq();
enum DDR_BITWIDTH bits = get_ddr_bitwidth();
return lpddr4_query_boundary(type, rank_num, speed, bits, size);
}

446
board/thead/light-c910/sbmeta/sbmeta.c Normal file
View File

@@ -0,0 +1,446 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2021 Alibaba Group Holding Limited
*/
#include "sbmeta.h"
#include "sec_crypto_sha.h"
#define LOGLEVEL_ERROR 1
#define LOGLEVEL_INFO 2
#define LOGLEVEL_DEBUG 3
#define SBMETA_LOGLEVEL 1
#define trace_printer(level, fmt,...) printf("%s"fmt, level, ##__VA_ARGS__)
#if (SBMETA_LOGLEVEL < 1)
#define EMSG(...)
#else
#define EMSG(fmt, args...) trace_printer("error: ", fmt, ##args)
#endif
#if (SBMETA_LOGLEVEL < 2)
#define IMSG(...)
#else
#define IMSG(fmt, args...) trace_printer("info: ", fmt, ##args)
#endif
#if (SBMETA_LOGLEVEL < 3)
#define DMSG(...)
#else
#define DMSG(fmt, args...) trace_printer("", fmt, ##args)
#endif
#if CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_VAL_A) || CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_VAL_B) || CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_LPI4A) || CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_RVBOOK)
#if CONFIG_IS_ENABLED(LIGHT_SEC_UPGRADE)
/* digest_size corresponding to digest_scheme specified in sbmeta_info_t */
static const int digest_size[] = {0, 20, 16, 28, 32, 48, 64, 32};
static const char* image_name_s[] = {
"dtb", "kernel", "tf", "aon", "rootfs", "tee", "uboot", "user"
};
/* index to get sc_sha_mode_t value */
static const int sha_idx2ctl[] = {0, 1, 8, 3, 2, 5, 4, 9};
static const unsigned long image_addrs[] = {
LIGHT_DTB_ADDR,
LIGHT_KERNEL_ADDR,
LIGHT_TF_FW_TMP_ADDR,
LIGHT_AON_FW_ADDR,
LIGHT_ROOTFS_ADDR,
LIGHT_TEE_FW_ADDR,
CONFIG_SYS_TEXT_BASE,
};
typedef struct {
int magiccode;
uint8_t dev;
uint8_t part;
uint8_t image_type;
uint8_t digest_scheme;
uint8_t sign_scheme;
uint8_t isencrypted;
uint8_t medium_type;
uint8_t checksum_scheme;
char filename[MAX_NAME_SIZE];
uint8_t digest[MAX_DIGEST_SIZE];
uint32_t relocated_addr;
uint8_t security_level;
uint8_t reserved[15];
} sbmeta_info_t;
static int is_sbmeta_info(uint32_t entry_src_addr)
{
uint32_t *buffer = (uint32_t *)(uintptr_t)entry_src_addr;
/* sbmeta_info_t entry should start with magic code 'S''B''M''T' */
if (*buffer != SBMETA_MAGIC) {
return CMD_RET_FAILURE;
}
return 0;
}
static int dump_sbmeta_info(sbmeta_info_t *sbmeta_info)
{
if (sbmeta_info == NULL) {
return CMD_RET_FAILURE;
}
/* only support emmc now */
if (sbmeta_info->medium_type != 0) {
EMSG("medium type %d is not supported now\r\n", sbmeta_info->medium_type);
return CMD_RET_FAILURE;
}
/* only support dtb, krlimg/tf, sbi, aon, rootfs, tee, uboot and user-defined type */
if (sbmeta_info->image_type > IMAGE_TYPE_NUM || sbmeta_info->image_type < 0) {
EMSG("image type is out of range\r\n");
return CMD_RET_FAILURE;
}
/* only support none, sha1, md5, sha224, sha256, sha384, sha512, sm3 and reserved scheme */
if (sbmeta_info->digest_scheme > DIGEST_TYPE_NUM || sbmeta_info->digest_scheme < 0) {
EMSG("digest type is out of range\r\n");
return CMD_RET_FAILURE;
}
/* only support none, rsa1024, rsa2048, ecc256, ecc160, sm2 and reserved scheme */
if (sbmeta_info->sign_scheme > SIGN_TYPE_NUM || sbmeta_info->sign_scheme < 0) {
EMSG("signature type is out of range\r\n");
return CMD_RET_FAILURE;
}
/* DTB, TF, TEE, Kernel will be loaded from default partitions specified in env */
if (sbmeta_info->image_type != T_ROOTFS && sbmeta_info->image_type != T_USER) {
IMSG("Image has been loaded\r\n");
}
if (sbmeta_info->security_level > SBMETA_SECURITY_LEVEL_SIGN || sbmeta_info->security_level < SBMETA_SECURITY_LEVEL_NONE) {
EMSG("security level is invalid\n");
return CMD_RET_FAILURE;
}
/* dump sbmeta_info_t */
DMSG("image medium type: %d\n", sbmeta_info->medium_type);
DMSG("image load part: mmc %d:%d\n", sbmeta_info->dev, sbmeta_info->part);
DMSG("image type: %d \n", sbmeta_info->image_type);
DMSG("image digest scheme: %d\n", sbmeta_info->digest_scheme);
DMSG("image sign scheme: %d\n", sbmeta_info->sign_scheme);
DMSG("image enable encryption: %s\n", sbmeta_info->isencrypted ? "en" : "dis");
DMSG("image file name: %s\n", sbmeta_info->filename);
DMSG("image digest:");
for (int i = 0; i < digest_size[sbmeta_info->digest_scheme]; i++) {
DMSG("%02X", sbmeta_info->digest[i]);
}
DMSG("\r\n");
DMSG("\n\n");
return 0;
}
static int sbmeta_field_verify(sbmeta_info_t *sbmeta_info, unsigned long img_src_addr)
{
uint8_t digest_scheme = 0;
uint8_t sign_scheme = 0;
uint8_t is_encrypted = 0;
img_header_t *phead = NULL;
if (sbmeta_info == NULL) {
return CMD_RET_FAILURE;
}
if (sbmeta_info->security_level < SBMETA_SECURITY_LEVEL_SIGN) {
return 0;
}
/* if image has secure header, check with sbmeta field */
if (image_have_head(img_src_addr)) {
phead = (img_header_t *)img_src_addr;
digest_scheme = phead->digest_scheme;
sign_scheme = phead->signature_scheme;
is_encrypted = (phead->option_flag & 0x2) >> 1;
}
if (sbmeta_info->digest_scheme != digest_scheme) {
EMSG("digest type %d is not expected: %d\r\n", digest_scheme, sbmeta_info->digest_scheme);
return CMD_RET_FAILURE;
}
/* only support none, rsa1024, rsa2048, ecc256, ecc160, sm2 and reserved scheme */
if (sbmeta_info->sign_scheme != sign_scheme) {
EMSG("signature type %d is not expected: %d\r\n", sign_scheme, sbmeta_info->sign_scheme);
return CMD_RET_FAILURE;
}
if (sbmeta_info->isencrypted != is_encrypted) {
EMSG("encryption %d is not expected: %d\r\n", is_encrypted, sbmeta_info->isencrypted);
return CMD_RET_FAILURE;
}
return 0;
}
static int check_digest(uint8_t *buffer, uint32_t buffer_size, uint8_t digest_scheme, uint8_t *digest)
{
uint32_t len = 0;
uint8_t sum[64];
sc_sha_t sha;
sc_sha_context_t ctx;
int mode = 0;
if (!buffer || digest_scheme > DIGEST_TYPE_NUM) {
EMSG("wrong parameter\r\n");
return CMD_RET_FAILURE;
}
if (digest_scheme == 0) {
return 0;
}
mode = sha_idx2ctl[digest_scheme];
if (sc_sha_init(&sha, 0) != 0) {
EMSG("sha initialize failed\r\n");
return CMD_RET_FAILURE;
}
if (sc_sha_start(&sha, &ctx, mode) != 0) {
EMSG("sha start failed\r\n");
return CMD_RET_FAILURE;
}
if (sc_sha_update(&sha, &ctx, buffer, buffer_size) != 0) {
EMSG("sha update failed\r\n");
return CMD_RET_FAILURE;
}
if (sc_sha_finish(&sha, &ctx, sum, &len) != 0) {
EMSG("sha finish failed\r\n");
return CMD_RET_FAILURE;
}
sc_sha_uninit(&sha);
/* check digest value */
if (memcmp(digest, sum, len) != 0) {
EMSG("check digest failed\r\n");
return CMD_RET_FAILURE;
}
return 0;
}
/* Verify image specified in sbmeta_info_t. The image has been loaded to memory before */
static int sbmeta_verify_image(uint32_t image_load_addr, sbmeta_info_t *sbmeta_info)
{
uint32_t image_size = 0;
const char *image_name;
uint8_t image_type = sbmeta_info->image_type;
uint8_t checksum_scheme = sbmeta_info->checksum_scheme;
uint8_t *digest = sbmeta_info->digest;
uint8_t is_encrypted = sbmeta_info->isencrypted;
uint32_t security_level = sbmeta_info->security_level;
uint32_t filesize = 0;
char buf[64] = {0};
/* check image_type to avoid array index out of bounds */
if (image_type > IMAGE_TYPE_NUM || image_type < 0) {
EMSG("image type is out of range\r\n");
return CMD_RET_FAILURE;
}
image_name = image_name_s[image_type];
/* check tee/tf version if needed */
#ifdef LIGHT_IMG_VERSION_CHECK_IN_BOOT
if (image_have_head(image_load_addr) == 1) {
if (image_type == T_TF) {
IMSG("check TF version in boot \n");
if (check_tf_version_in_boot(LIGHT_TF_FW_TMP_ADDR) != 0) {
return CMD_RET_FAILURE;
}
}
if (image_type == T_TEE) {
IMSG("check TEE version in boot \n");
if (check_tee_version_in_boot(LIGHT_TEE_FW_ADDR) != 0) {
return CMD_RET_FAILURE;
}
}
}
#endif
/* start verifying images */
IMSG("Process %s image verification ...\n", image_name);
if (security_level == SBMETA_SECURITY_LEVEL_SIGN || is_encrypted != 0) {
if (verify_customer_image(image_type, image_load_addr) != 0) {
return CMD_RET_FAILURE;
}
} else if (security_level == SBMETA_SECURITY_LEVEL_HASH) {
if (memcmp(digest, buf, 64) == 0) {
EMSG("sbmeta info doesn't specify digest value in security level 2\r\n");
return CMD_RET_FAILURE;
}
snprintf(buf, sizeof(buf), "ext4size mmc %x:%x %s", sbmeta_info->dev, sbmeta_info->part, sbmeta_info->filename);
if (run_command(buf, 0) != 0) {
EMSG("get file size error\r\n");
return CMD_RET_FAILURE;
}
filesize = env_get_hex("filesize", 0);
if (check_digest((uint8_t *)(uintptr_t)image_load_addr, filesize, checksum_scheme, digest) != 0) {
return CMD_RET_FAILURE;
}
}
/* move image headers always */
if (image_have_head(image_load_addr) == 1) {
image_size = get_image_size(image_load_addr);
IMSG("%s image size: %d\n", image_name, image_size);
if (image_size < 0) {
EMSG("GET %s image size error\n", image_name);
return CMD_RET_FAILURE;
}
if (image_type == T_TF) {
memmove((void *)(uintptr_t)LIGHT_TF_FW_ADDR, (const void *)(uintptr_t)(image_load_addr + HEADER_SIZE), image_size);
} else {
memmove((void *)(uintptr_t)image_load_addr, (const void *)(uintptr_t)(image_load_addr + HEADER_SIZE), image_size);
}
} else {
/* TF should be moved to LIGHT_TF_FW_ADDR all the cases*/
if (image_type == T_TF) {
/* while image_size is unknown, reload the image */
run_command("ext4load mmc 0:3 0x0 trust_firmware.bin", 0);
}
}
return 0;
}
static int light_sbmetaboot(int argc, char *const argv[])
{
int count = 0;
uint32_t sbmeta_size = 0;
uint32_t info_addr = 0;
uint32_t image_load_addr = 0;
char cmd[64] = {0};
sbmeta_info_t *sbmeta_info = NULL;
/* Load sbmeta image to memory */
snprintf(cmd, sizeof(cmd), "ext4load mmc ${mmcdev}:${mmcsbmetapart} 0x%x %s", (void *)(uintptr_t)LIGHT_SBMETA_ADDR, SBMETA_FILENAME);
printf("%s\n",cmd);
if (run_command(cmd, 0) != 0) {
/* if sbmeta doesn't exist, do secboot by default */
IMSG("SBMETA doesn't exist, go to verify tf/tee\r\n");
/*
* Verify tf and tee by command secboot.
* Note that tf and tee has been loaded in "run bootcmd_load"
*/
if (run_command("secboot", 0) != 0) {
return CMD_RET_FAILURE;
}
return 0;
}
/* initialize crypto algorithm interfaces */
if (csi_sec_init() != 0) {
return CMD_RET_FAILURE;
}
/* Check and verify sbmeta image */
if (image_have_head(LIGHT_SBMETA_ADDR) == 1) {
#ifdef LIGHT_IMG_VERSION_CHECK_IN_BOOT
IMSG("check SBMETA version in boot \n");
ret = check_sbmeta_version_in_boot(LIGHT_SBMETA_ADDR);
if (ret != 0) {
return CMD_RET_FAILURE;
}
#endif
IMSG("Process SBMETA image verification...\r\n");
if (verify_customer_image(T_SBMETA, LIGHT_SBMETA_ADDR) != 0) {
return CMD_RET_FAILURE;
}
sbmeta_size = get_image_size(LIGHT_SBMETA_ADDR);
IMSG("sbmeta_size:%d\r\n", sbmeta_size);
if (sbmeta_size != SBMETA_SIZE) {
EMSG("SBMETA header is wrong! Size must equal to %d bytes!\r\n", SBMETA_SIZE);
return CMD_RET_FAILURE;
}
/* move image headers always */
memmove((void *)LIGHT_SBMETA_ADDR, (const void *)(LIGHT_SBMETA_ADDR + HEADER_SIZE), sbmeta_size);
} else {
/* if sbmeta image is not secure, reset */
IMSG("SBMETA image must be with signature\r\n");
return CMD_RET_FAILURE;
}
/* Parse sbmeta_info_t in image sbmeta, then load and verify specified images */
info_addr = LIGHT_SBMETA_ADDR;
for (count = 0; count < MAX_ENTRY_NUM; count++) {
if (is_sbmeta_info(info_addr) == 0) {
/* Dump and check sbmeta info */
sbmeta_info = (sbmeta_info_t *)(uintptr_t)info_addr;
if (dump_sbmeta_info(sbmeta_info) != 0) {
return CMD_RET_FAILURE;
}
info_addr += ENTRY_SIZE;
/*
* If image_type != T_USER, load to address specified in light-c910.h;
* otherwise, load to user-specified address.
*/
if (sbmeta_info->image_type != T_USER) {
image_load_addr = image_addrs[sbmeta_info->image_type];
} else {
image_load_addr = sbmeta_info->relocated_addr;
}
/*
* Load image specified in sbmeta info
* Note: only load images don't exist in env "bootcmd_load"
*/
if (sbmeta_info->image_type == T_ROOTFS || sbmeta_info->image_type == T_USER) {
snprintf(cmd, sizeof(cmd), "ext4load mmc %x:%x %p %s", sbmeta_info->dev,
sbmeta_info->part, \
(void *)(uintptr_t)image_load_addr, sbmeta_info->filename);
if (run_command(cmd, 0) != 0) {
return CMD_RET_FAILURE;
}
}
if (sbmeta_field_verify(sbmeta_info, image_load_addr) != 0) {
return CMD_RET_FAILURE;
}
/* Check and verify user-specified image */
if (sbmeta_verify_image(image_load_addr, sbmeta_info) != 0) {
return CMD_RET_FAILURE;
}
} else {
break;
}
}
/* if sbmeta didn't specify images, reset */
if (count == 0) {
EMSG("SBMETA doesn't specify any images!\r\n");
return CMD_RET_FAILURE;
}
/* Clear sbmeta buffer in memory */
memset((void *)LIGHT_SBMETA_ADDR, 0, PLAIN_SBMETA_TEXT);
return 0;
}
static int do_sbmetaboot(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
{
if (light_sbmetaboot(argc, argv) != 0) {
EMSG("sbmetaboot failed\r\n");
while (1);
return CMD_RET_FAILURE;
}
return 0;
}
U_BOOT_CMD(
sbmetaboot, CONFIG_SYS_MAXARGS, 1, do_sbmetaboot,
"load and verify image sbmeta, then verify image files specified in sbmeta",
""
);
#endif
#endif

33
board/thead/light-c910/sbmeta/sbmeta.h Normal file
View File

@@ -0,0 +1,33 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2021 Alibaba Group Holding Limited
*/
#ifndef _LIGHT_SBMETA_H
#define _LIGHT_SBMETA_H
#include "common.h"
#include "command.h"
#include <asm/arch-thead/boot_mode.h>
#define MAX_NAME_SIZE 32
#define MAX_DIGEST_SIZE 64
#define SBMETA_MAGIC 0x544D4253 /* = {'S', 'B', 'M', 'T'} */
#if CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_VAL_A) || CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_VAL_B) || CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_LPI4A) || CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_RVBOOK)
#define LIGHT_SBMETA_ADDR 0x10000000
#endif
#define ENTRY_SIZE 128
#define PLAIN_SBMETA_TEXT 4096
#define SBMETA_SIZE 4736 /* 4K SMBETA image + 640 footer */
#define MAX_ENTRY_NUM PLAIN_SBMETA_TEXT / ENTRY_SIZE /* 4K/128=32 */
#define IMAGE_TYPE_NUM 7
#define DIGEST_TYPE_NUM 8
#define SIGN_TYPE_NUM 6
#define SBMETA_FILENAME "sbmeta.bin"
#define SBMETA_SECURITY_LEVEL_SIGN 3 /* verify signature and hash */
#define SBMETA_SECURITY_LEVEL_HASH 2 /* verify checksum */
#define SBMETA_SECURITY_LEVEL_NONE 1 /* no verification */
#endif

10
board/thead/light-c910/sec_check.c
View File

@@ -75,7 +75,7 @@ void designware_get_mac_from_fuse(unsigned char *mac)
}
}
#if CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_VAL_A) || CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_VAL_B) || CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_ANT_REF) || CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_LPI4A)
#if CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_VAL_A) || CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_VAL_B) || CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_ANT_REF) || CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_LPI4A) || CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_RVBOOK)
/* Secure function for image verificaiton here */
int get_image_version(unsigned long img_src_addr)
{
@@ -130,16 +130,18 @@ void dump_image_header_info(long addr)
int verify_customer_image(img_type_t type, long addr)
{
int ret;
/* Double check image number */
if (image_have_head(addr) == 0)
if (image_have_head(addr) == 0) {
printf("error: image has no secure header\r\n");
return -1;
}
/* Dump image header information here */
dump_image_header_info(addr);
/* Call customer image verification function */
if ((type == T_TF) || (type == T_TEE) || (type == T_KRLIMG)) {
if ((type == T_TF) || (type == T_TEE) || (type == T_KRLIMG) || (type == T_DTB) || (type == T_SBMETA)) {
ret = csi_sec_custom_image_verify(addr, UBOOT_STAGE_ADDR);
if (ret) {
printf("Image(%d) is verified fail, Please go to check!\n\n", type);

79
board/thead/light-c910/secimg_load.c
View File

@@ -10,12 +10,12 @@
#include "sec_library.h"
#define ENV_SECIMG_LOAD "sec_m_load"
#define VAL_SECIMG_LOAD "ext4load mmc 0:7 $tf_addr trust_firmware.bin; ext4load mmc 0:7 $tee_addr tee.bin"
#define VAL_SECIMG_LOAD "ext4load mmc ${mmcdev}:${mmcteepart} $tf_addr trust_firmware.bin; ext4load mmc ${mmcdev}:${mmcteepart} $tee_addr tee.bin\0"
#define RPMB_BLOCK_SIZE 256
#define RPMB_ROLLBACK_BLOCK_START 1
#ifndef LIGHT_KDF_RPMB_KEYs
#ifndef LIGHT_KDF_RPMB_KEY
static const unsigned char emmc_rpmb_key_sample[32] = {0x33, 0x22, 0x11, 0x00, 0x77, 0x66, 0x55, 0x44, \
0xbb, 0xaa, 0x99, 0x88, 0xff, 0xee, 0xdd, 0xcc, \
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, \
@@ -23,14 +23,15 @@ static const unsigned char emmc_rpmb_key_sample[32] = {0x33, 0x22, 0x11, 0x00, 0
#endif
extern int sprintf(char *buf, const char *fmt, ...);
extern char * get_slot_name_suffix(void);
static int get_rpmb_key(uint8_t key[32])
{
#ifndef LIGHT_KDF_RPMB_KEY
#ifndef LIGHT_KDF_RPMB_KEY
memcpy(key, emmc_rpmb_key_sample, sizeof(emmc_rpmb_key_sample));
return 0;
#else
#else
uint32_t kdf_rpmb_key_length = 0;
int ret = 0;
ret = csi_kdf_gen_hmac_key(key, &kdf_rpmb_key_length);
@@ -46,7 +47,7 @@ static int get_image_file_size(unsigned long img_src_addr)
{
img_header_t *img = (img_header_t *)img_src_addr;
uint8_t magiccode[4] = {0};
magiccode[3] = img->magic_num & 0xff;
magiccode[2] = (img->magic_num & 0xff00) >> 8;
magiccode[1] = (img->magic_num & 0xff0000) >> 16;
@@ -54,7 +55,7 @@ static int get_image_file_size(unsigned long img_src_addr)
if (memcmp(header_magic, magiccode, 4) == 0) {
return -1;
}
return img->image_size;
}
@@ -68,13 +69,13 @@ static int verify_and_load_image(unsigned long image_addr_src, unsigned long ima
if (ret != 0) {
return -1;
}
ret = csi_sec_custom_image_verify(image_addr_src, UBOOT_STAGE_ADDR);
if (ret != 0) {
printf("image verify error\r\n");
return -2;
}
image_size = get_image_file_size(image_addr_src);
if (image_size < 0) {
printf("image get size error\r\n");
@@ -112,16 +113,24 @@ int verify_and_load_tee_tf_image(void)
}
/* In order to use common bootloader for both secure boot and non-secure boot,
we only know the boot type through reading the sec_boot field in efuse. Due to
the efuse is only accessed in lifecycle(DEV/OEM/PRO/RMP), we ensure it must be
we only know the boot type through reading the sec_boot field in efuse. Due to
the efuse is only accessed in lifecycle(DEV/OEM/PRO/RMP), we ensure it must be
non-secure boot in lifecycle(INIT) */
bool get_system_boot_type(void)
{
bool btype = false; /* false: non-secure boot | true: secure boot */
bool btype = true; /* false: non-secure boot | true: secure boot */
#if 0
int lc = 0;
sboot_st_t sb_flag = SECURE_BOOT_DIS;
int ret = 0;
#endif
int sb_emulater = 0;
sb_emulater = env_get_ulong("sb_emulater", 10, 0);
if (sb_emulater == 0) {
btype = false;
}
# if 0
ret = csi_efuse_get_lc(&lc);
/* 0: LC_INIT, 1: LC_DEV, 2: LC_OEM, 3: LC_PRO */
if ((ret == 0) && (lc != 0)) {
@@ -134,7 +143,7 @@ bool get_system_boot_type(void)
csi_efuse_api_uninit();
}
#endif
return btype;
}
@@ -170,7 +179,7 @@ int sec_write_rollback_index(size_t rollback_index_slot, uint64_t rollback_index
}
*(uint64_t*)(blkdata + rpmb_offset) = rollback_index;
if (get_rpmb_key(rpmb_key) != 0) {
return -2;
}
@@ -189,19 +198,37 @@ static int do_secimg_load(cmd_tbl_t *cmdtp, int flag, int argc, char * const arg
bool sb_enable = false;
const char *secimgs_load_str = VAL_SECIMG_LOAD;
int ret = -1;
sb_enable = get_system_boot_type();
if (sb_enable) {
/* By default, the value for ENV-SEC-M-LOAD is always to load opensbi image.
* if secure boot is enable, we force to change the value to load tee image.
* but Never to save it in volatile-RAM
*/
ret = env_set(ENV_SECIMG_LOAD, secimgs_load_str);
if (ret != 0) {
printf("Rewrite ENV (%s) fails\n", ENV_SECIMG_LOAD);
return CMD_RET_FAILURE;
}
}
int teepart = 0;
#ifdef CONFIG_ANDROID_AB
char *slot_suffix = get_slot_name_suffix();
teepart = env_get_ulong("mmcteepart", 10, 8);
if ((strcmp(slot_suffix, "_a") == 0) && (teepart != 8)) {
/* Switch mmcbootpart to "_b" */
env_set_ulong("mmcbootpart", 2);
/* Switch mmcteepart to "_b" */
env_set_ulong("mmcteepart", 8);
} else if ((strcmp(slot_suffix, "_b") == 0) && (teepart != 9)){
/* Switch mmcbootpart to "_b" */
env_set_ulong("mmcbootpart", 3);
/* Switch mmcteepart to "_b" */
env_set_ulong("mmcteepart", 9);
}
#endif
sb_enable = get_system_boot_type();
if (sb_enable) {
/* By default, the value for ENV-SEC-M-LOAD is always to load opensbi image.
* if secure boot is enable, we force to change the value to load tee image.
* but Never to save it in volatile-RAM
*/
ret = env_set(ENV_SECIMG_LOAD, secimgs_load_str);
if (ret != 0) {
printf("Rewrite ENV (%s) fails\n", ENV_SECIMG_LOAD);
return CMD_RET_FAILURE;
}
}
return CMD_RET_SUCCESS;
}

141
board/thead/light-c910/spl.c
View File

@@ -26,6 +26,11 @@
DECLARE_GLOBAL_DATA_PTR;
extern void init_ddr(void);
#ifdef CONFIG_FIXUP_MEMORY_REGION
extern int fixup_ddr_addrmap(unsigned long size);
extern int query_ddr_boundary(unsigned long size);
#endif
extern unsigned long get_ddr_density(void);
extern void cpu_clk_config(int cpu_freq);
extern void sys_clk_config(void);
extern void ddr_clk_config(int ddr_freq);
@@ -93,6 +98,25 @@ void setup_ddr_pmp(void)
sync_is();
}
void clear_ddr_pmp(void)
{
/* restore pmp entry0,entry1 setting in bootrom */
writel(0x0400000000 >> 12, (void *)(PMP_BASE_ADDR + 0x104));
writel(0x0 >> 12, (void *)(PMP_BASE_ADDR + 0x100));
writel(0xffe1000000 >> 12, (void *)(PMP_BASE_ADDR + 0x10c));
writel(0xffe0180000 >> 12, (void *)(PMP_BASE_ADDR + 0x108));
writel(0x4040, (void *)(PMP_BASE_ADDR + 0x000));
sync_is();
}
static inline void _l2cache_ciall(void)
{
asm volatile (".long 0x0170000b");
}
int get_rng(unsigned int *rng, int cnt)
{
int i;
@@ -297,17 +321,113 @@ void setup_ddr_parity(void)
}
}
#ifdef CONFIG_FIXUP_MEMORY_REGION
#define MAGIC_DATA (0xF4240)
#define MAGIC_DATA2 (0x5AA5)
#define MAGIC_DATA3 (0x3C3C)
#define MAGIC_DATA4 (0xF0F0)
/*
return: 0: found boundary;
*/
int boundary_verify(unsigned long boundary) {
phys_addr_t verify_addr = (phys_addr_t)CONFIG_SYS_SDRAM_BASE;
phys_addr_t verify_addr2 = ((phys_addr_t)boundary + CONFIG_SYS_SDRAM_BASE)/4;
phys_addr_t verify_addr3 = ((phys_addr_t)boundary + CONFIG_SYS_SDRAM_BASE)/2;
phys_addr_t verify_addr4 = (phys_addr_t)boundary + CONFIG_SYS_SDRAM_BASE;
// verify data accessing result firstly
writel(MAGIC_DATA2, verify_addr);
invalidate_dcache_range(verify_addr, verify_addr + CONFIG_SYS_CACHELINE_SIZE);
if (readl(verify_addr) != MAGIC_DATA2) {
printf("ddr rw test failed\n");
return -1;
}
writel(MAGIC_DATA, verify_addr); // writing at beginning
invalidate_dcache_range(verify_addr, verify_addr + CONFIG_SYS_CACHELINE_SIZE);
if (readl(verify_addr) != MAGIC_DATA) {
printf("ddr rw test failed\n");
return -1;
}
writel(MAGIC_DATA2, verify_addr2); // writing at one-quarter addr
writel(MAGIC_DATA3, verify_addr3); // writing at half addr
invalidate_dcache_range(verify_addr, verify_addr + CONFIG_SYS_CACHELINE_SIZE);
invalidate_dcache_range(verify_addr2, verify_addr2 + CONFIG_SYS_CACHELINE_SIZE);
invalidate_dcache_range(verify_addr3, verify_addr3 + CONFIG_SYS_CACHELINE_SIZE);
if (boundary == (unsigned long)MAXIMAL_DDR_DENSITY_MB * UNIT_MB) { // boundary by design
if ((readl(verify_addr) == MAGIC_DATA) &&
(readl(verify_addr2) == MAGIC_DATA2) &&
(readl(verify_addr3) == MAGIC_DATA3))
return 0;
}
else {
writel(MAGIC_DATA4, verify_addr4); // writing out of boundary
invalidate_dcache_range(verify_addr4, verify_addr4 + CONFIG_SYS_CACHELINE_SIZE);
if ((readl(verify_addr) == MAGIC_DATA4) && // overwrite by verify_addr4
(readl(verify_addr2) == MAGIC_DATA2) &&
(readl(verify_addr3) == MAGIC_DATA3) &&
(readl(verify_addr4) == MAGIC_DATA4))
return 0;
}
return -1;
}
int setup_ddr_addrmap(void)
{
unsigned long boundary = (unsigned long)MAXIMAL_DDR_DENSITY_MB * UNIT_MB;
// verify data accessing result firstly
writel(MAGIC_DATA, (phys_addr_t)CONFIG_SYS_SDRAM_BASE);
invalidate_dcache_range(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_CACHELINE_SIZE);
if (readl((phys_addr_t)CONFIG_SYS_SDRAM_BASE) != MAGIC_DATA) {
printf("ddr rw test failed\n");
goto addrmap_err;
}
writel(MAGIC_DATA2, (phys_addr_t)CONFIG_SYS_SDRAM_BASE);
invalidate_dcache_range(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_CACHELINE_SIZE);
if (readl((phys_addr_t)CONFIG_SYS_SDRAM_BASE) != MAGIC_DATA2) {
printf("ddr rw test failed\n");
goto addrmap_err;
}
// try to find memory boundary
while (boundary >= (unsigned long)MINIMAL_DDR_DENSITY_MB * UNIT_MB) {
if (query_ddr_boundary(boundary) == 0) {
clear_ddr_pmp();
fixup_ddr_addrmap(boundary);
setup_ddr_pmp();
if (boundary_verify(boundary) == 0) {
gd->ram_size = boundary;
printf("found ddr boundary <0x%lx>\n", boundary);
return 0;
}
}
boundary = boundary >> 1;
}
gd->ram_size = get_ddr_density();
addrmap_err:
printf("failed to setup ddr addrmap\n");
return -1;
}
#endif
void cpu_performance_enable(void)
{
#define CSR_MHINT2_E 0x7cc
#define CSR_MHINT4 0x7ce
csr_write(CSR_SMPEN, 0x1);
csr_write(CSR_MHINT2_E, csr_read(CSR_MHINT2_E) | 0x20000);
csr_write(CSR_MHINT4, csr_read(CSR_MHINT4) | 0x410);
csr_write(CSR_MCCR2, 0xe2490009);
csr_write(CSR_MHCR, 0x117f); // clear bit7 to disable indirect brantch prediction
csr_write(CSR_MXSTATUS, 0x638000);
csr_write(CSR_MHINT, 0x6e30c | (1<<21) | (1<<22)); // set bit21 & bit 22 to close tlb & fence broadcast
// FIXME: Clear bit[12] to disable L0BTB.
csr_write(CSR_MHCR, 0x17f); // clear bit7 to disable indirect brantch prediction
// FIXME set mhint2[22] to enable core icg en
csr_write(CSR_MHINT2_E, csr_read(CSR_MHINT2_E) | 0x420000);
csr_write(CSR_MHINT4, csr_read(CSR_MHINT4) | 0x410);
}
static int bl1_img_have_head(unsigned long img_src_addr)
@@ -369,9 +489,9 @@ void board_init_f(ulong dummy)
preloader_console_init();
#ifdef CONFIG_PMIC_VOL_INIT
ret = pmic_ddr_regu_init();
ret = aon_local_init();
if (ret) {
printf("%s pmic init failed %d \n",__func__,ret);
printf("%s aon local init failed %d \n",__func__,ret);
hang();
}
@@ -386,15 +506,24 @@ void board_init_f(ulong dummy)
printf("%s set apcpu voltage failed \n",__func__);
hang();
}
#endif
ddr_clk_config(0);
#ifdef CONFIG_RV_BOOK
cpu_clk_config(750000000);
#else
cpu_clk_config(0);
#endif
init_ddr();
setup_ddr_scramble();
setup_ddr_parity();
setup_ddr_pmp();
#ifdef CONFIG_FIXUP_MEMORY_REGION
setup_ddr_addrmap();
#else
// update ram_size from board config
gd->ram_size = get_ddr_density();
#endif
printf("ddr initialized, jump to uboot\n");
light_board_init_r(NULL, 0);

113
board/thead/light-c910/sys_clk.c
View File

@@ -20,12 +20,106 @@
#define LIGHT_APSYS_RSTGEN_ADDRBASE 0xffff015000
#define LIGHT_DPU_CLOCK_GATING_CTRL0 0xffef601A28
#define LIGHT_DPU_CLOCK_GATING_CTRL1 0xffef601A2C
#ifdef CONFIG_RV_BOOK
#define LIGHT_CPU_PLL_IDX(x) (x)
#endif
void show_sys_clk(void)
{
/* Do nothing for FPGA */
}
#ifdef CONFIG_RV_BOOK
static int _light_get_pllid(void)
{
unsigned int val;
int ret;
val = readl((void *)LIGHT_APCLK_ADDRBASE + 0x100);
if(val & 0x1)
ret = LIGHT_CPU_PLL_IDX(1);
else
ret = LIGHT_CPU_PLL_IDX(0);
return ret;
}
void update_cpu_freq(uint32_t val)
{
if(_light_get_pllid() == LIGHT_CPU_PLL_IDX(0))
{
/* update cpupll1*/
writel(0x20000000, (void *)LIGHT_APCLK_ADDRBASE + 0x14);
writel(val, (void *)LIGHT_APCLK_ADDRBASE + 0x10);
writel(0x23000000, (void *)LIGHT_APCLK_ADDRBASE + 0x14);
udelay(3);
writel(0x03000000, (void *)LIGHT_APCLK_ADDRBASE + 0x14);
readl((void *)LIGHT_APCLK_ADDRBASE + 0x80);
readl((void *)LIGHT_APCLK_ADDRBASE + 0x80);
while(!(readl((void *)LIGHT_APCLK_ADDRBASE + 0x80) & 0x10));
udelay(11);
}else{
/* update cpupll0*/
writel(0x20000000, (void *)LIGHT_APCLK_ADDRBASE + 0x04);
writel(val, (void *)LIGHT_APCLK_ADDRBASE + 0x00);
writel(0x23000000, (void *)LIGHT_APCLK_ADDRBASE + 0x04);
udelay(3);
writel(0x03000000, (void *)LIGHT_APCLK_ADDRBASE + 0x04);
readl((void *)LIGHT_APCLK_ADDRBASE + 0x80);
readl((void *)LIGHT_APCLK_ADDRBASE + 0x80);
while(!(readl((void *)LIGHT_APCLK_ADDRBASE + 0x80) & 0x02));
udelay(11);
}
}
void cpu_clk_config(int32_t cpu_freq)
{
#ifndef CONFIG_TARGET_LIGHT_FPGA_FM_C910 /* for sillicon */
unsigned int tmp;
switch(cpu_freq){
case 750000000:
{
/* 4. update c910_cclk to 750Mhz */
update_cpu_freq(0x1407d01);
/* config bus: cpu clk ratio to 1:1 */
writel((readl((const volatile void __iomem *)(LIGHT_APCLK_ADDRBASE + 0x100)) & (~(0x7<<8))) | (0x0<<8), (void *)(LIGHT_APCLK_ADDRBASE + 0x100)); // ratio=0
writel(readl((const volatile void __iomem *)(LIGHT_APCLK_ADDRBASE + 0x100)) & (~(0x1<<11)), (void *)(LIGHT_APCLK_ADDRBASE + 0x100)); // sync=0
writel(readl((const volatile void __iomem *)(LIGHT_APCLK_ADDRBASE + 0x100)) | (0x1<<11), (void *)(LIGHT_APCLK_ADDRBASE + 0x100)); // sync=1
printf("cpu frequency to 750\n");
}
break;
case 1500000000:
{
/* 4. update c910_cclk to 1.5Ghz */
update_cpu_freq(0x01207d01);
/* config bus: cpu clk ratio to 1:2 */
writel((readl((const volatile void __iomem *)(LIGHT_APCLK_ADDRBASE + 0x100)) & (~(0x7<<8))) | (0x1<<8), (void *)(LIGHT_APCLK_ADDRBASE + 0x100)); // ratio=0
writel(readl((const volatile void __iomem *)(LIGHT_APCLK_ADDRBASE + 0x100)) & (~(0x1<<11)), (void *)(LIGHT_APCLK_ADDRBASE + 0x100)); // sync=0
writel(readl((const volatile void __iomem *)(LIGHT_APCLK_ADDRBASE + 0x100)) | (0x1<<11), (void *)(LIGHT_APCLK_ADDRBASE + 0x100)); // sync=1
printf("cpu frequency to 1500\n");
}
break;
default:
return;
}
if(_light_get_pllid() == LIGHT_CPU_PLL_IDX(0))
{
/* switch c910_cclk to cpu_pll1_foutpostdiv */
tmp = readl((void *)LIGHT_APCLK_ADDRBASE + 0x100);
tmp |= 0x1;
writel(tmp, (void *)LIGHT_APCLK_ADDRBASE + 0x100);
}else
{
/* switch c910_cclk to cpu_pll0_foutpostdiv */
tmp = readl((void *)LIGHT_APCLK_ADDRBASE + 0x100);
tmp &= ~0x1;
writel(tmp, (void *)LIGHT_APCLK_ADDRBASE + 0x100);
}
udelay(1);
#endif
}
#else
void cpu_clk_config(uint32_t cpu_freq)
{
#ifndef CONFIG_TARGET_LIGHT_FPGA_FM_C910 /* for sillicon */
@@ -54,6 +148,7 @@ void cpu_clk_config(uint32_t cpu_freq)
udelay(1);
#endif
}
#endif
void sys_clk_config(void)
{
@@ -336,6 +431,24 @@ void sys_clk_config(void)
#endif
}
#ifndef CONFIG_SPL_BUILD
static int cpu_switch_freq(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[])
{
cpu_clk_config(1500000000);
return 0;
}
U_BOOT_CMD(
cpufreq_switch,
2,
0,
cpu_switch_freq,
"switch cpu freq to highest",
""
);
#endif
void ddr_clk_config(int ddr_freq)
{
/* Do nothing for FPGA */

1
cmd/Makefile
View File

@@ -137,6 +137,7 @@ obj-$(CONFIG_CMD_TPM) += tpm-common.o
obj-$(CONFIG_CMD_TPM_V1) += tpm-v1.o
obj-$(CONFIG_CMD_TPM_TEST) += tpm_test.o
obj-$(CONFIG_CMD_TPM_V2) += tpm-v2.o
obj-$(CONFIG_CMD_MEASURED_BOOT) += mboot.o
obj-$(CONFIG_CMD_CROS_EC) += cros_ec.o
obj-$(CONFIG_CMD_TSI148) += tsi148.o
obj-$(CONFIG_CMD_UBI) += ubi.o

271
cmd/bootandroid.c
View File

@@ -1,4 +1,3 @@
/*
* (C) Copyright 2018, Linaro Limited
*
@@ -19,8 +18,8 @@
#define ENV_RAMDISK_ADDR "ramdisk_addr"
#define ENV_DTB_ADDR "dtb_addr"
#define DEFAULT_KERNEL_ADDR 0x00200800
#define DEFAULT_RAMDISK_ADDR 0x02000000
#define DEFAULT_DTB_ADDR 0x01f00000
#define DEFAULT_RAMDISK_ADDR LIGHT_ROOTFS_ADDR
#define DEFAULT_DTB_ADDR LIGHT_DTB_ADDR
#define ENV_RAMDISK_SIZE "ramdisk_size"
#define MISC_PARTITION "misc"
#define RECOVERY_PARTITION "recovery"
@@ -33,14 +32,14 @@
/*
* Knowing secure boot is enable or disable dependents on
* Knowing secure boot is enable or disable dependents on
* special data field in efuse and efuse control register.
*/
extern bool get_system_boot_type(void);
/*
* The suffix for partition name is from the value of ENV_BOOTAB
*/
static const char *slot_name_suffix = NULL;;
static const char *slot_name_suffix = NULL;
/*
* BOOT IMAGE HEADER V3/V4 PAGESIZE
@@ -49,7 +48,35 @@ static const char *slot_name_suffix = NULL;;
#define BOOT_IMAGE_HEADER_V3_PAGESIZE 4096
static struct AvbOps *avb_ops = NULL;
static struct bootloader_message* s_bcb = NULL;
static struct bootloader_message_ab *s_bcb = NULL;
static struct bootloader_control *boot_ctl = NULL;
static char *get_boot_partition_name_suffix(void)
{
#ifdef CONFIG_ANDROID_AB
if (boot_ctl != NULL) {
/* index 0 is _a, index 1 is _b*/
if(boot_ctl->slot_info[0].priority < boot_ctl->slot_info[1].priority) {
strcpy(boot_ctl->slot_suffix, "_b");
} else {
strcpy(boot_ctl->slot_suffix, "_a");
}
} else {
printf("get_slot_suffix boot_ctl is null return _a");
return "_a";
}
printf("get_slot_suffix boot_ctl->slot_suffix %s\r\n", boot_ctl->slot_suffix);
return boot_ctl->slot_suffix;
#else
return "";
#endif
}
static void get_partition_name(const char *partion, char *partion_name)
{
strcpy(partion_name, partion);
strcat(partion_name, get_boot_partition_name_suffix());
}
/*
*format 4 chars/bytes to a int number
@@ -71,7 +98,7 @@ static int get_number_of_pages(int image_size, int page_size)
* and append bootconfig to the end of ramdisk(initrd)
* doc:https://www.kernel.org/doc/html/next/translations/zh_CN/admin-guide/bootconfig.html#initrd
*/
static int prepare_data_from_vendor_boot(struct andr_img_hdr *hdr, int dtb_start, uint8_t** buf_bootconfig, int* vendor_bootconfig_size)
static int prepare_data_from_vendor_boot(struct andr_img_hdr *hdr, int dtb_start, uint8_t** buf_bootconfig, int* vendor_bootconfig_size, bool isRecovery)
{
int ret;
disk_partition_t part_info;
@@ -87,8 +114,8 @@ static int prepare_data_from_vendor_boot(struct andr_img_hdr *hdr, int dtb_start
/* if the vendor boot partition name is beyond 32B, arise error */
if ((32 - strlen(VENDOR_BOOT_PARTITION)) < 2)
return -1;
memcpy(vb_part_name, VENDOR_BOOT_PARTITION, strlen(VENDOR_BOOT_PARTITION));
strcat(vb_part_name, slot_name_suffix);
get_partition_name(VENDOR_BOOT_PARTITION, vb_part_name);
printf("blk_get_dev %s\n", vb_part_name);
if (!dev_desc || dev_desc->type == DEV_TYPE_UNKNOWN) {
@@ -102,11 +129,19 @@ static int prepare_data_from_vendor_boot(struct andr_img_hdr *hdr, int dtb_start
return -1;
}
vendor_boot_data = avb_malloc(part_info.size * part_info.blksz);
if (vendor_boot_data == NULL) {
printf("vendor boot data malloc fail \n");
return -1;
}
if (part_info.size * part_info.blksz > CONFIG_FASTBOOT_BUF_SIZE) {
return -1;
}
//vendor_boot_data = (uint8_t*)CONFIG_FASTBOOT_BUF_ADDR;
printf("vendor_boot_data part_info.size = %ld, part_info.blksz = %lu", part_info.size, part_info.blksz);
// reuse kernel start address to load vendor boot data
// because av_malloc(32M) failed in 2G devices
// TODO: why av_malloc failed
// ATTATION: If the vendor_boot partition size > boot partition size, it is error.
// avb_malloc(part_info.size * part_info.blksz);
vendor_boot_data = (uint8_t*)env_get_hex(ENV_KERNEL_ADDR, DEFAULT_KERNEL_ADDR);
ret = blk_dread(dev_desc, part_info.start, part_info.size, vendor_boot_data);
// vendor_boot.img
//* +------------------------+
@@ -170,20 +205,68 @@ static int prepare_data_from_vendor_boot(struct andr_img_hdr *hdr, int dtb_start
*buf_bootconfig = avb_malloc(*vendor_bootconfig_size);
if (*buf_bootconfig == NULL) {
printf("vendor bootconfig malloc fail\n");
if (vendor_boot_data != NULL)
avb_free(vendor_boot_data);
return -1;
}
int bootconfig_offset=vendor_boot_pagesize * (o + p + q + r);
memcpy(*buf_bootconfig, vendor_boot_data + bootconfig_offset, *vendor_bootconfig_size);
if (vendor_boot_data != NULL)
avb_free(vendor_boot_data);
#ifdef CONFIG_ANDROID_AB
char *find_str = NULL;
char *slot_suffix = get_boot_partition_name_suffix();
char *slot_suffx_pre = "androidboot.slot_suffix=";
printf("prepare_data_from_vendor_boot slot_suffix:%s\n", slot_suffix);
printf("prepare_data_from_vendor_boot slot_suffx_pre:%s\n", slot_suffx_pre);
find_str = strstr((char *)*buf_bootconfig, slot_suffx_pre);
if (find_str != NULL) {
memcpy(find_str + strlen(slot_suffx_pre), slot_suffix, strlen(slot_suffix));
}
#endif
if (isRecovery) {
int i = 0;
struct vendor_ramdisk_table_entry *ramdisk_entry = NULL;
int vendor_ramdisk_table_offset = vendor_boot_pagesize * (o + p + q);
int vendor_ramdisk_table_entry_num = byteToInt(vendor_boot_data,2116);//offset 2116
printf("vendor_boot vendor_ramdisk_table_entry_num:%d\n",vendor_ramdisk_table_entry_num);
int vendor_ramdisk_table_entry_size = byteToInt(vendor_boot_data,2120);//offset 2116
printf("vendor_boot vendor_ramdisk_table_entry_size:%d\n",vendor_ramdisk_table_entry_size);
for (i = 0; i < vendor_ramdisk_table_entry_num; i++) {
ramdisk_entry = (struct vendor_ramdisk_table_entry*)(vendor_boot_data + vendor_ramdisk_table_offset
+ ( i * vendor_ramdisk_table_entry_size ));
if (ramdisk_entry->ramdisk_type != VENDOR_RAMDISK_TYPE_RECOVERY) {
continue;
}
printf("find recovery from ramdisk table.\n");
int ramdisk_start = env_get_hex(ENV_RAMDISK_ADDR, DEFAULT_RAMDISK_ADDR);
int recovery_ramdisk_offset = vendor_boot_pagesize * o + ramdisk_entry->ramdisk_offset;
printf("ramdisk_start:%x, ramdisk_size:%x, dtb_start:%x\n", ramdisk_start, ramdisk_entry->ramdisk_size, dtb_start);
if (ramdisk_start + ramdisk_entry->ramdisk_size > dtb_start) {
printf("ramdisk space are overlaped !!!\n");
}
memcpy((void *)(uint64_t)ramdisk_start, vendor_boot_data + recovery_ramdisk_offset,
ramdisk_entry->ramdisk_size);//ramdisk
//get bootconfig form vendor_boot.img and append bootconfig to ramdisk
char* bootconfig_params = (char*)*buf_bootconfig;
int ret = addBootConfigParameters(bootconfig_params, *vendor_bootconfig_size,
ramdisk_start + ramdisk_entry->ramdisk_size , 0);
if (ret == -1) {
printf("\nadd BootConfig Parameters error!!!\n");
} else {
printf("\nramdisk size is changed,new value is:%d\n",ramdisk_entry->ramdisk_size + ret);
//set ramdisk size for bootm
env_set_hex(ENV_RAMDISK_SIZE, ramdisk_entry->ramdisk_size + ret);
}
break;
}
}
return 0;
}
static void prepare_loaded_parttion_data(const uint8_t* data)
static void prepare_loaded_parttion_data(const uint8_t* data, bool isRecovery)
{
struct andr_img_hdr *hdr = (struct andr_img_hdr *)map_sysmem((phys_addr_t)data, 0);
@@ -198,7 +281,7 @@ static void prepare_loaded_parttion_data(const uint8_t* data)
hdr->kernel_size = byteToInt((uint8_t *)data, 8);
hdr->ramdisk_size = byteToInt((uint8_t *)data, 12);
hdr->page_size = BOOT_IMAGE_HEADER_V3_PAGESIZE;
prepare_data_from_vendor_boot(hdr,dtb_start,&buf_bootconfig,&size_bootconfig);
prepare_data_from_vendor_boot(hdr,dtb_start,&buf_bootconfig,&size_bootconfig,isRecovery);
}
int kernel_start = env_get_hex(ENV_KERNEL_ADDR, DEFAULT_KERNEL_ADDR);
@@ -215,18 +298,21 @@ static void prepare_loaded_parttion_data(const uint8_t* data)
printf("Boot image kernel_start:%x, kernel_offset:%x, kernel_size:%d\n", kernel_start, kernel_offset, hdr->kernel_size);
printf("Boot image ramdisk_start:%x, ramdisk_offset:%x, ramdisk_size:%d\n", ramdisk_start, ramdisk_offset, hdr->ramdisk_size);
printf("Boot image page_size:%d\n", hdr->page_size);
printf("dtb_offset:%x, dtb_size:%d\n", dtb_offset, hdr->dtb_size);
printf("dtb_start:%x, dtb_offset:%x, dtb_size:%d\n", dtb_start, dtb_offset, hdr->dtb_size);
if (kernel_start + hdr->kernel_size > ramdisk_start || kernel_start + hdr->kernel_size > dtb_start) {
printf("boot.img kernel space and ramdis space are overlaped !!!\n");
if (kernel_start + hdr->kernel_size > ramdisk_start || kernel_start + hdr->kernel_size > dtb_start || ramdisk_start + hdr->ramdisk_size > dtb_start) {
printf("boot.img kernel space and ramdisk space are overlaped !!!\n");
} else {
memcpy((void *)(uint64_t)kernel_start, data + kernel_offset, hdr->kernel_size);
memcpy((void *)(uint64_t)ramdisk_start, data + ramdisk_offset, hdr->ramdisk_size);
if (!isRecovery) {
memcpy((void *)(uint64_t)ramdisk_start, data + ramdisk_offset, hdr->ramdisk_size);
}
if( hdr->header_version < 3) {
//set ramdisk size for bootm
env_set_hex(ENV_RAMDISK_SIZE, hdr->ramdisk_size);
memcpy((void *)(uint64_t)dtb_start, data + dtb_offset, hdr->dtb_size);
} else {
} else if (!isRecovery) {
//get bootconfig form vendor_boot.img and append bootconfig to ramdisk
char* bootconfig_params=(char*)buf_bootconfig;
int ret = addBootConfigParameters(bootconfig_params, size_bootconfig,
@@ -247,7 +333,7 @@ static void prepare_loaded_parttion_data(const uint8_t* data)
unmap_sysmem(hdr);
}
static int prepare_boot_data(const AvbSlotVerifyData *out_data)
static int prepare_boot_data(const AvbSlotVerifyData *out_data, bool isRecovery)
{
int res = CMD_RET_FAILURE;
int i = 0;
@@ -260,13 +346,13 @@ static int prepare_boot_data(const AvbSlotVerifyData *out_data)
if (loaded_partition->partition_name != NULL) {
printf("partition_name=%s, data_size=%ld\n", \
loaded_partition->partition_name, loaded_partition->data_size);
prepare_loaded_parttion_data(loaded_partition->data);
prepare_loaded_parttion_data(loaded_partition->data, isRecovery);
}
}
return res;
}
static void prepare_partition_data(const char *name)
static void prepare_partition_data(const char *name, bool isRecovery)
{
int ret = 0;
disk_partition_t part_info;
@@ -292,7 +378,7 @@ static void prepare_partition_data(const char *name)
}
ret = blk_dread(dev_desc, part_info.start, part_info.size, data);
prepare_loaded_parttion_data(data);
prepare_loaded_parttion_data(data, isRecovery);
printf("prepare_partition_data %s, read=%d, start:%lx, size:%ld, blksize:%lx\n", \
name, ret, part_info.start, part_info.size, part_info.blksz);
@@ -307,7 +393,7 @@ static void clear_bcb(void)
struct blk_desc *dev_desc = blk_get_dev("mmc", CONFIG_FASTBOOT_FLASH_MMC_DEV);
//bcb clear and store
memset(s_bcb, 0, sizeof(struct bootloader_message));
memset(s_bcb, 0, sizeof(struct bootloader_message_ab));
if (!dev_desc || dev_desc->type == DEV_TYPE_UNKNOWN) {
printf("BootAndriod bcb err: invalid mmc device\n");
@@ -324,22 +410,54 @@ static void clear_bcb(void)
printf("BootAndriod bcb info :clear_bcb write=%d, %ld,%ld,%ld\n", ret, part_info.start, part_info.size, part_info.blksz);
}
static int do_andriod_bcb_business(struct AvbOps *avb_ops, struct bootloader_message* s_bcb)
static int do_andriod_bcb_business(int *boot_recovery)
{
AvbIOResult ret = AVB_IO_RESULT_OK;
size_t bytes_read = 0;
int res = CMD_RET_FAILURE;
s_bcb = avb_malloc(sizeof(struct bootloader_message));
#ifdef CONFIG_ANDROID_AB
char *slot_suffix = "_a";
#else
char *slot_suffix = "";
#endif
if (avb_ops != NULL) {
avb_ops_free(avb_ops);
avb_ops = NULL;
}
avb_ops = avb_ops_alloc(BOOTDEV_DEFAULT);
if (avb_ops == NULL) {
goto _bcb_err;
}
if (s_bcb != NULL) {
avb_free(s_bcb);
s_bcb = NULL;
}
s_bcb = avb_malloc(sizeof(struct bootloader_message_ab));
if (s_bcb == NULL) {
printf("BootAndriod Err: Failed to initialize bcb\n");
goto _bcb_err;
}
if (boot_ctl != NULL) {
avb_free(boot_ctl);
boot_ctl = NULL;
}
boot_ctl = malloc(sizeof(struct bootloader_control));
if (boot_ctl == NULL)
{
ret = -2;
goto _bcb_err;
}
ret = avb_ops->read_from_partition(avb_ops,
MISC_PARTITION,
0,
sizeof(struct bootloader_message),
sizeof(struct bootloader_message_ab),
s_bcb,
&bytes_read);
if (ret != AVB_IO_RESULT_OK) {
@@ -348,39 +466,45 @@ static int do_andriod_bcb_business(struct AvbOps *avb_ops, struct bootloader_mes
}
/* Enter into fastboot mode if bcb string is bootonce or bootrecovery */
if (0 == strncmp(s_bcb->command, BCB_BOOTONCE, strlen(BCB_BOOTONCE))|| \
0 == strncmp(s_bcb->command, BCB_BOOTRECOVERY, strlen(BCB_BOOTRECOVERY))) {
printf("BootAndriod Info: Bcb read %ld bytes, %s\n", bytes_read, s_bcb->command);
if (0 == strncmp(s_bcb->message.command, "bootonce-bootloader", strlen("bootonce-bootloader")))
{
printf("BootAndriod Info: Bcb read %ld bytes, %s\n", bytes_read, s_bcb->message.command);
printf("BootAndriod Info: Enter fastboot mode\n");
clear_bcb();
run_command("fastboot usb 0", 0);
}
else if (0 == strncmp(s_bcb->message.command, "boot-recovery", strlen("boot-recovery")))
{
printf("recovery slot_suffix = %s\n", slot_suffix);
*boot_recovery = 1;
}
memset(boot_ctl, 0, sizeof(struct bootloader_control));
memcpy(boot_ctl, (struct bootloader_control*)s_bcb->slot_suffix, sizeof(struct bootloader_control));
res = CMD_RET_SUCCESS;
_bcb_err:
if (s_bcb != NULL)
avb_free(s_bcb);
if (res != CMD_RET_SUCCESS) {
if (avb_ops != NULL) {
avb_ops_free(avb_ops);
avb_ops = NULL;
}
if (boot_ctl != NULL) {
avb_free(boot_ctl);
boot_ctl = NULL;
}
if (s_bcb != NULL) {
avb_free(s_bcb);
s_bcb = NULL;
}
}
return res;
}
static const char *get_boot_partition_name_suffix(void)
{
#if defined (CONFIG_ANDROID_AB)
char *slot_suffix = "_a";
#else
char *slot_suffix = "";
#endif
char *tmp = NULL;
tmp = env_get("boot_ab");
if (tmp != NULL)
slot_suffix = tmp;
return slot_suffix;
}
static int do_bootandroid(struct cmd_tbl_s *cmdtp, int flag, int argc,
char * const argv[]) {
@@ -391,23 +515,19 @@ static int do_bootandroid(struct cmd_tbl_s *cmdtp, int flag, int argc,
AvbSlotVerifyFlags slotflags = AVB_SLOT_VERIFY_FLAGS_NONE;
AvbHashtreeErrorMode htflags = AVB_HASHTREE_ERROR_MODE_RESTART_AND_INVALIDATE;
int res = CMD_RET_FAILURE;
char bp_name[32] = {0};
int boot_recovery = 0;
res = do_andriod_bcb_business(&boot_recovery);
if (res != CMD_RET_SUCCESS) {
goto exit;
}
/* Retieve boot partition 's name suffix */
slot_name_suffix = get_boot_partition_name_suffix();
/* Start with slot verification in secure boot */
if (get_system_boot_type()) {
avb_ops = avb_ops_alloc(BOOTDEV_DEFAULT);
if (avb_ops == NULL) {
goto _ba_err;
}
res = do_andriod_bcb_business(avb_ops, s_bcb);
if (res != CMD_RET_SUCCESS) {
goto _ba_err;
}
/* Verify boot partition requested in vbmeta.img */
slot_result = avb_slot_verify(avb_ops,
requested_partitions,
@@ -419,7 +539,7 @@ static int do_bootandroid(struct cmd_tbl_s *cmdtp, int flag, int argc,
if (slot_result == AVB_SLOT_VERIFY_RESULT_OK) {
printf("BootAndriod Info: Request Partition are verified successfully\n");
printf("BootAndriod cmdline: slot_data.cmdline:%s\n", slot_data->cmdline);
prepare_boot_data(slot_data);
prepare_boot_data(slot_data, boot_recovery ? true:false);
if (ret == 0) {
if (slot_data != NULL)
avb_slot_verify_data_free(slot_data);
@@ -428,22 +548,21 @@ static int do_bootandroid(struct cmd_tbl_s *cmdtp, int flag, int argc,
/* In case of avb slot verification failure, Force system reset */
run_command("reset", 0);
}
_ba_err:
if (avb_ops)
avb_ops_free(avb_ops);
} else {
/* Go to load BOOT partition directly in non-secure boot */
char bp_name[32] = {0};
strcat(bp_name, BOOT_PARTITION);
strcat(bp_name, slot_name_suffix);
prepare_partition_data(bp_name);
get_partition_name(BOOT_PARTITION, bp_name);
prepare_partition_data(bp_name, boot_recovery ? true:false);
}
exit:
return res;
}
const char * get_slot_name_suffix(void)
{
return slot_name_suffix;
}
U_BOOT_CMD(
bootandroid, 2, 1, do_bootandroid,
"bootandroid - boot android bootimg from device\n",

93
cmd/booti.c
View File

@@ -67,7 +67,6 @@ static int booti_start(cmd_tbl_t *cmdtp, int flag, int argc,
int do_booti(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
int ret;
/* Consume 'booti' */
argc--; argv++;
@@ -119,7 +118,7 @@ U_BOOT_CMD(
#endif
#if CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_VAL_A) || CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_VAL_B) || CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_ANT_REF) || CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_LPI4A)
#if CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_VAL_A) || CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_VAL_B) || CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_ANT_REF) || CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_LPI4A) || CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_RVBOOK)
#if CONFIG_IS_ENABLED(LIGHT_SEC_UPGRADE)
extern int light_secboot(int argc, char * const argv[]);
#endif
@@ -127,18 +126,102 @@ int do_secboot(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
#if CONFIG_IS_ENABLED(LIGHT_SEC_UPGRADE)
if (light_secboot(argc, argv) != 0) {
run_command("reset", 0);
return -1;
}
#endif
return 0;
}
U_BOOT_CMD(
secboot, CONFIG_SYS_MAXARGS, 1, do_secboot,
"verify image file with known pubkey which reside in father image or itself!",
secboot, CONFIG_SYS_MAXARGS, 1, do_secboot,
"verify image file with known pubkey which reside in father image or itself!",
"vimage addr imgname[[tee/tf] - verify specifed image resides in addr\n"
);
/* check whether partition numbers are consistent with the slot suffix */
static int do_light_bootab(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) {
char *slot_suffix = env_get("slot_suffix");
int teepart = env_get_hex("mmcteepart", 3);
struct disk_partition part_info;
struct blk_desc *dev_desc;
int part = 0;
dev_desc = blk_get_dev("mmc", CONFIG_FASTBOOT_FLASH_MMC_DEV);
if (dev_desc == NULL) {
printf("Failed to find MMC device\n");
return 1;
}
if ((strcmp(slot_suffix, "a") == 0) && (teepart != 3)) {
part = part_get_info_by_name(dev_desc, "boot_a", &part_info);
if (part < 0) {
printf("Failed to find MMC device\n");
return 1;
}
env_set_hex("mmcbootpart", part);
part = part_get_info_by_name(dev_desc, "tee_a", &part_info);
if (part < 0) {
printf("Failed to find MMC device\n");
return 1;
}
env_set_hex("mmcteepart", part);
part = part_get_info_by_name(dev_desc, "sbmeta_a", &part_info);
if (part < 0) {
printf("Failed to find MMC device\n");
return 1;
}
env_set_hex("mmcsbmetapart", part);
part = part_get_info_by_name(dev_desc, "root_a", &part_info);
if (part < 0) {
printf("root AB partition is not enabled\n");
} else {
env_set_hex("mmcpart", part);
}
run_command("env save", 0);
} else if ((strcmp(slot_suffix, "b") == 0) && (teepart != 10)) {
part = part_get_info_by_name(dev_desc, "boot_b", &part_info);
if (part < 0) {
printf("Failed to find MMC device\n");
return 1;
}
env_set_hex("mmcbootpart", part);
part = part_get_info_by_name(dev_desc, "tee_b", &part_info);
if (part < 0) {
printf("Failed to find MMC device\n");
return 1;
}
env_set_hex("mmcteepart", part);
part = part_get_info_by_name(dev_desc, "sbmeta_b", &part_info);
if (part < 0) {
printf("Failed to find MMC device\n");
return 1;
}
env_set_hex("mmcsbmetapart", part);
part = part_get_info_by_name(dev_desc, "root_b", &part_info);
if (part < 0) {
printf("root AB partition is not enabled\n");
} else {
env_set_hex("mmcpart", part);
}
run_command("env save", 0);
}
printf("current active slot is:%s\n", slot_suffix);
return CMD_RET_SUCCESS;
}
U_BOOT_CMD(
light_bootab, CONFIG_SYS_MAXARGS, 1, do_light_bootab,
"Light A/B updates",
NULL
);
#endif
#endif

122
cmd/mboot.c Normal file
View File

@@ -0,0 +1,122 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (c) 2018 Bootlin
* Author: Miquel Raynal <miquel.raynal@bootlin.com>
*/
#include <common.h>
#include <dm.h>
#include <log.h>
#include <mapmem.h>
#include <tpm-common.h>
#include <tpm-v2.h>
#include <env.h>
#include <env_internal.h>
#include "tpm-user-utils.h"
#include "sec_library.h"
enum mboot_type {
UBOOT_IMAGE = 0,
KERNEL_IMAGE,
PARTITIONS_STR,
MBOOT_TYPE_MAX,
};
enum pcr_index {
PCR_0 = 0,
PCR_1,
PCR_2,
PCR_3,
PCR_4,
PCR_5,
PCR_6,
PCR_7,
};
static uint8_t image_digest[32] __attribute__((aligned(64))) = { 0 };
#define CHECK_RET_WITH_RET(x, ret) \
do { \
if (!(x)) { \
return ret; \
} \
} while (0)
static uint32_t hash_image_sha256(long image_addr, size_t size, void *digest, uint32_t *digest_len)
{
uint32_t ret;
sc_sha_t sha;
sc_sha_context_t ctx;
CHECK_RET_WITH_RET(ret = csi_sec_library_init(), ret);
CHECK_RET_WITH_RET(ret = sc_sha_init(&sha, 0), ret);
CHECK_RET_WITH_RET(ret = sc_sha_start(&sha, &ctx, SC_SHA_MODE_256), ret);
CHECK_RET_WITH_RET(ret = sc_sha_trans_config(&sha, &ctx, SC_SHA_DMA_MODE), ret);
CHECK_RET_WITH_RET(ret = sc_sha_update(&sha, &ctx, (void *)image_addr, size), ret);
CHECK_RET_WITH_RET(ret = sc_sha_finish(&sha, &ctx, digest, digest_len), ret);
return SC_OK;
}
static int do_measured_boot(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
struct udevice *dev;
struct tpm_chip_priv *priv;
uint32_t index, type;
uint32_t rc;
int ret;
long image_addr = 0;
size_t image_size = 0;
uint32_t image_digest_len = 0;
char *partitions_str = NULL;
if (argc != 1)
return CMD_RET_USAGE;
ret = get_tpm(&dev);
if (ret)
return ret;
tpm_init(dev); /* Initialization TPM2 chip */
rc = tpm2_startup(dev, TPM2_SU_CLEAR); /* Startup TPM2 chip with mode TPM_ST_CLEAR*/
if (rc)
report_return_code(rc);
priv = dev_get_uclass_priv(dev);
if (!priv)
return -EINVAL;
for (type = UBOOT_IMAGE; type < MBOOT_TYPE_MAX; type++) {
if (type == UBOOT_IMAGE) { /*U-BOOT Image */
index = PCR_0;
image_addr = CONFIG_SPL_TEXT_BASE;
image_size = CONFIG_SPL_MAX_SIZE+CONFIG_SYS_MONITOR_LEN;
} else if (type == KERNEL_IMAGE) { /* KERNEL Image */
index = PCR_0;
image_addr = 0x00200000;
if (fs_set_blk_dev("mmc", "0:2", 2))
return -EINVAL;
if (fs_size("Image", &image_size) < 0)
return -EINVAL;
} else if (type == PARTITIONS_STR) { /* PARTITIONS */
index = PCR_5;
partitions_str = env_get("partitions");
image_addr = (long)partitions_str;
image_size = strlen(partitions_str);
}
rc = hash_image_sha256(image_addr, image_size, image_digest, &image_digest_len);
if (rc)
return -EINVAL;
rc = tpm2_pcr_extend(dev, index, image_digest);
if (rc)
break;
}
return report_return_code(rc);
}
U_BOOT_CMD(
measured_boot, CONFIG_SYS_MAXARGS, 1, do_measured_boot,
"extend hash(u-boot), hash(kernel), hash(partitions str) to pcr0 and pcr5",
""
);

19
cmd/net.c
View File

@@ -458,3 +458,22 @@ U_BOOT_CMD(
);
#endif /* CONFIG_CMD_LINK_LOCAL */
/* moved from board_init_r sequence here to save normal boot time */
static int do_eth_init(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[])
{
puts("Net: ");
eth_initialize();
#if defined(CONFIG_RESET_PHY_R)
debug("Reset Ethernet PHY\n");
reset_phy();
#endif
return 0;
}
U_BOOT_CMD(
eth, 6, 1, do_eth_init,
"eth initialize",
""
);

14
common/Kconfig
View File

@@ -962,6 +962,20 @@ config TPL_HASH
and the algorithms it supports are defined in common/hash.c. See
also CMD_HASH for command-line access.
config BOARD_RNG_SEED
bool "Provide /chosen/rng-seed property to the linux kernel"
help
Selecting this option requires the board to define a
board_rng_seed() function, which should return a buffer
which will be used to populate the /chosen/rng-seed property
in the device tree for the OS being booted.
It is up to the board code (and more generally the whole
BSP) where and how to store (or generate) such a seed, how
to ensure a given seed is only used once, how to create a
new seed for use on subsequent boots, and whether or not the
kernel should account any entropy from the given seed.
endmenu
menu "Update support"

13
common/fdt_support.c
View File

@@ -7,6 +7,7 @@
*/
#include <common.h>
#include <abuf.h>
#include <env.h>
#include <mapmem.h>
#include <stdio_dev.h>
@@ -274,6 +275,7 @@ int fdt_initrd(void *fdt, ulong initrd_start, ulong initrd_end)
int fdt_chosen(void *fdt)
{
struct abuf buf = {};
int nodeoffset;
int err;
char *str; /* used to set string properties */
@@ -289,6 +291,17 @@ int fdt_chosen(void *fdt)
if (nodeoffset < 0)
return nodeoffset;
if (IS_ENABLED(CONFIG_BOARD_RNG_SEED) && !board_rng_seed(&buf)) {
err = fdt_setprop(fdt, nodeoffset, "rng-seed",
abuf_data(&buf), abuf_size(&buf));
abuf_uninit(&buf);
if (err < 0) {
printf("WARNING: could not set rng-seed %s.\n",
fdt_strerror(err));
return err;
}
}
str = env_get("bootargs");
if (str) {
err = fdt_setprop(fdt, nodeoffset, "bootargs", str,

4
common/image-fdt.c
View File

@@ -416,7 +416,7 @@ int boot_get_fdt(int flag, int argc, char * const argv[], uint8_t arch,
* FDT blob
*/
debug("* fdt: raw FDT blob\n");
printf("## Flattened Device Tree blob at %08lx\n",
debug("## Flattened Device Tree blob at %08lx\n",
(long)fdt_addr);
}
break;
@@ -425,7 +425,7 @@ int boot_get_fdt(int flag, int argc, char * const argv[], uint8_t arch,
goto no_fdt;
}
printf(" Booting using the fdt blob at %#08lx\n", fdt_addr);
debug(" Booting using the fdt blob at %#08lx\n", fdt_addr);
fdt_blob = map_sysmem(fdt_addr, 0);
} else if (images->legacy_hdr_valid &&
image_check_type(&images->legacy_hdr_os_copy,

7
configs/light_a_val_android_defconfig
View File

@@ -18,6 +18,7 @@ CONFIG_SYS_PROMPT="C910 Light# "
CONFIG_DDR_LP4X_3733_SINGLERANK=y
# CONFIG_DDR_LP4_3733_DUALRANK is not set
CONFIG_DDR_BOARD_CONFIG=y
CONFIG_FIXUP_MEMORY_REGION=n
CONFIG_CMD_BOOT_SLAVE=y
CONFIG_CMD_ERASEENV=y
CONFIG_CMD_GPT=y
@@ -101,10 +102,11 @@ CONFIG_PMIC_VOL_INIT=y
CONFIG_DDR_REGU_0V6=600000
CONFIG_DDR_REGU_0V8=800000
CONFIG_DDR_REGU_1V1=1100000
CONFIG_SPL_TEXT_BASE=0xffe0000800
CONFIG_LIGHT_ANDROID_BOOT_IMAGE_VAL_A=y
# CONFIG_AVB_USE_OEM_KEY is not set
CONFIG_AVB_USE_OEM_KEY=y
# CONFIG_AVB_ROLLBACK_ENABLE is not set
# CONFIG_AVB_HW_ENGINE_ENABLE is not set
CONFIG_AVB_HW_ENGINE_ENABLE=y
CONFIG_ANDROID_BOOT_IMAGE=y
CONFIG_LIBAVB=y
CONFIG_AVB_VERIFY=y
@@ -113,3 +115,4 @@ CONFIG_CMD_BOOTANDROID=y
CONFIG_ANDROID_AB=y
CONFIG_CMD_AB_SELECT=y
CONFIG_XBC=y
CONFIG_BOARD_RNG_SEED=y

8
configs/light_a_val_defconfig
View File

@@ -21,17 +21,18 @@ CONFIG_SYS_PROMPT="C910 Light# "
CONFIG_DDR_LP4X_3733_SINGLERANK=y
# CONFIG_DDR_LP4_3733_DUALRANK is not set
CONFIG_DDR_BOARD_CONFIG=y
CONFIG_FIXUP_MEMORY_REGION=y
CONFIG_CMD_BOOT_SLAVE=y
CONFIG_CMD_ERASEENV=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MTD=y
CONFIG_CMD_USB=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_SPI=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MEMTEST=y
CONFIG_DDR_SCAN=y
CONFIG_DDR_PRBS_TEST=n
# CONFIG_DOS_PARTITION is not set
# CONFIG_ISO_PARTITION is not set
CONFIG_PARTITION_TYPE_GUID=y
CONFIG_OF_EMBED=y
@@ -76,6 +77,9 @@ CONFIG_SPI=y
CONFIG_DESIGNWARE_SPI=y
CONFIG_DESIGNWARE_QSPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_DWC3=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="U-Boot-THEAD"
@@ -103,3 +107,5 @@ CONFIG_PMIC_VOL_INIT=y
CONFIG_DDR_REGU_0V6=600000
CONFIG_DDR_REGU_0V8=800000
CONFIG_DDR_REGU_1V1=1100000
CONFIG_MISC=y
CONFIG_LIGHT_AON_CONF=y

17
configs/light_a_val_sec_defconfig
View File

@@ -18,6 +18,14 @@ CONFIG_SYS_PROMPT="C910 Light# "
CONFIG_DDR_LP4X_3733_SINGLERANK=y
# CONFIG_DDR_LP4_3733_DUALRANK is not set
CONFIG_DDR_BOARD_CONFIG=y
CONFIG_FIXUP_MEMORY_REGION=y
# CONFIG_TPM is not set
# CONFIG_TPM_Z32H330TC_SPI is not set
# CONFIG_TPM_V2 is not set
# CONFIG_CMD_TPM_V2 is not set
# CONFIG_CMD_TPM is not set
# CONFIG_CMD_TPM_TEST is not set
# CONFIG_CMD_MEASURED_BOOT is not set
CONFIG_CMD_BOOT_SLAVE=y
CONFIG_CMD_ERASEENV=y
CONFIG_CMD_GPT=y
@@ -28,7 +36,6 @@ CONFIG_CMD_I2C=y
CONFIG_CMD_MEMTEST=y
CONFIG_DDR_SCAN=y
CONFIG_DDR_PRBS_TEST=n
# CONFIG_DOS_PARTITION is not set
# CONFIG_ISO_PARTITION is not set
CONFIG_PARTITION_TYPE_GUID=y
CONFIG_OF_EMBED=y
@@ -73,6 +80,9 @@ CONFIG_SPI=y
CONFIG_DESIGNWARE_SPI=y
CONFIG_DESIGNWARE_QSPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_DWC3=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="U-Boot-THEAD"
@@ -90,6 +100,7 @@ CONFIG_PHY=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_CMD_BMP=y
CONFIG_CMD_USB=y
CONFIG_VIDEO_BRIDGE=y
CONFIG_DM_PCA953X=y
CONFIG_VIDEO_VS_DPU=y
@@ -102,3 +113,7 @@ CONFIG_PMIC_VOL_INIT=y
CONFIG_DDR_REGU_0V6=600000
CONFIG_DDR_REGU_0V8=800000
CONFIG_DDR_REGU_1V1=1100000
CONFIG_MISC=y
CONFIG_LIGHT_AON_CONF=y
# CONFIG_FASTBOOT_CMD_OEM_NV_OPERATION is not set
# CONFIG_FASTBOOT_ECIES_AUTH is not set

120
configs/light_ant_ref_android_defconfig Normal file
View File

@@ -0,0 +1,120 @@
CONFIG_RISCV=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_OFFSET=0xe0000
CONFIG_NR_DRAM_BANKS=8
CONFIG_SPL=y
CONFIG_SMP=y
CONFIG_TARGET_LIGHT_C910=y
CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_REF=y
CONFIG_ARCH_RV64I=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BUILD_TARGET="u-boot-with-spl.bin"
CONFIG_DISPLAY_CPUINFO=y
CONFIG_DISPLAY_BOARDINFO=y
# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
CONFIG_SPL_RAM_SUPPORT=y
CONFIG_SPL_RAM_DEVICE=y
CONFIG_SYS_PROMPT="C910 Light# "
CONFIG_DDR_LP4X_3200_SINGLERANK=y
CONFIG_DDR_H32_MODE=y
# CONFIG_DDR_LP4_3733_DUALRANK is not set
CONFIG_DDR_BOARD_CONFIG=y
CONFIG_FIXUP_MEMORY_REGION=n
CONFIG_CMD_BOOT_SLAVE=y
CONFIG_CMD_ERASEENV=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MTD=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_SPI=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MEMTEST=y
CONFIG_DDR_SCAN=y
CONFIG_DDR_PRBS_TEST=n
# CONFIG_DOS_PARTITION is not set
# CONFIG_ISO_PARTITION is not set
CONFIG_PARTITION_TYPE_GUID=y
CONFIG_OF_EMBED=y
CONFIG_DEFAULT_DEVICE_TREE="light-ant-ref"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SPL_CLK=y
CONFIG_USB_FUNCTION_FASTBOOT=y
CONFIG_UDP_FUNCTION_FASTBOOT=y
CONFIG_FASTBOOT_BUF_ADDR=0x10000000
CONFIG_FASTBOOT_FLASH=y
CONFIG_FASTBOOT_FLASH_MMC_DEV=0
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
CONFIG_DM_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_DW=y
CONFIG_DWAPB_GPIO=y
# CONFIG_MMC_SPI is not set
CONFIG_MMC_VERBOSE=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_IO_VOLTAGE=y
CONFIG_MMC_UHS_SUPPORT=y
CONFIG_MMC_HS400_SUPPORT=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_SNPS=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SNPS=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_CMD_MMC=y
CONFIG_CMD_MMC_RPMB=y
CONFIG_SUPPORT_EMMC_RPMB=y
CONFIG_DM_MTD=y
CONFIG_MTD_SPI_NAND=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_PHY_REALTEK=y
CONFIG_RTL8211E_PINE64_GIGABIT_FIX=y
CONFIG_RTL8211X_PHY_FORCE_MASTER=y
CONFIG_RTL8211F_PHY_FORCE_EEE_RXC_ON=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DESIGNWARE_SPI=y
CONFIG_DESIGNWARE_QSPI=y
CONFIG_USB=y
CONFIG_USB_DWC3=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="U-Boot-THEAD"
CONFIG_USB_GADGET_VENDOR_NUM=0x1234
CONFIG_USB_GADGET_PRODUCT_NUM=0x8888
# CONFIG_SPL_USE_TINY_PRINTF is not set
# CONFIG_EFI_LOADER is not set
# CONFIG_LIGHT_SEC_UPGRADE is not set
CONFIG_BOARD_LATE_INIT=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_DM_VIDEO=y
CONFIG_PHY=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_CMD_BMP=y
CONFIG_VIDEO_BRIDGE=y
CONFIG_DM_PCA953X=y
CONFIG_VIDEO_VS_DPU=y
CONFIG_VIDEO_LCD_ILITEK_ILI9881C=y
CONFIG_VIDEO_DW_DSI_LIGHT=y
CONFIG_VIDEO_DW_DPHY=y
CONFIG_VIDEO_DW_DSI_HOST=y
CONFIG_SYS_WHITE_ON_BLACK=y
CONFIG_SYS_TEXT_BASE=0x7b000000
CONFIG_PMIC_VOL_INIT=y
CONFIG_DDR_REGU_0V6=600000
CONFIG_DDR_REGU_0V8=800000
CONFIG_DDR_REGU_1V1=1100000
CONFIG_SPL_TEXT_BASE=0xffe0000800
CONFIG_LIGHT_ANDROID_BOOT_IMAGE_ANT_REF=y
CONFIG_AVB_USE_OEM_KEY=y
# CONFIG_AVB_ROLLBACK_ENABLE is not set
CONFIG_AVB_HW_ENGINE_ENABLE=y
CONFIG_ANDROID_BOOT_IMAGE=y
CONFIG_LIBAVB=y
CONFIG_AVB_VERIFY=y
CONFIG_CMD_AVB=y
CONFIG_CMD_BOOTANDROID=y
CONFIG_ANDROID_AB=y
CONFIG_CMD_AB_SELECT=y
CONFIG_XBC=y
CONFIG_BOARD_RNG_SEED=y

1
configs/light_ant_ref_defconfig
View File

@@ -20,6 +20,7 @@ CONFIG_DDR_LP4X_3200_SINGLERANK=y
CONFIG_DDR_H32_MODE=y
# CONFIG_DDR_LP4_3733_DUALRANK is not set
CONFIG_DDR_BOARD_CONFIG=y
CONFIG_FIXUP_MEMORY_REGION=y
CONFIG_CMD_BOOT_SLAVE=y
CONFIG_CMD_ERASEENV=y
CONFIG_CMD_GPT=y

1
configs/light_ant_ref_sec_defconfig
View File

@@ -20,6 +20,7 @@ CONFIG_DDR_LP4X_3200_SINGLERANK=y
CONFIG_DDR_H32_MODE=y
# CONFIG_DDR_LP4_3733_DUALRANK is not set
CONFIG_DDR_BOARD_CONFIG=y
CONFIG_FIXUP_MEMORY_REGION=y
CONFIG_CMD_BOOT_SLAVE=y
CONFIG_CMD_ERASEENV=y
CONFIG_CMD_GPT=y

5
configs/light_b_product_android_defconfig
View File

@@ -20,6 +20,7 @@ CONFIG_DDR_LP4X_3200_SINGLERANK=y
CONFIG_DDR_H32_MODE=y
# CONFIG_DDR_LP4_3733_DUALRANK is not set
CONFIG_DDR_BOARD_CONFIG=y
CONFIG_FIXUP_MEMORY_REGION=n
CONFIG_CMD_BOOT_SLAVE=y
CONFIG_CMD_ERASEENV=y
CONFIG_CMD_GPT=y
@@ -105,8 +106,11 @@ CONFIG_PMIC_VOL_INIT=y
CONFIG_DDR_REGU_0V6=600000
CONFIG_DDR_REGU_0V8=800000
CONFIG_DDR_REGU_1V1=1100000
CONFIG_SPL_TEXT_BASE=0xffe0000800
CONFIG_LIGHT_ANDROID_BOOT_IMAGE_VAL_B=y
CONFIG_AVB_USE_OEM_KEY=y
# CONFIG_AVB_ROLLBACK_ENABLE is not set
CONFIG_AVB_HW_ENGINE_ENABLE=y
CONFIG_ANDROID_BOOT_IMAGE=y
CONFIG_LIBAVB=y
CONFIG_AVB_VERIFY=y
@@ -115,3 +119,4 @@ CONFIG_CMD_BOOTANDROID=y
CONFIG_ANDROID_AB=y
CONFIG_CMD_AB_SELECT=y
CONFIG_XBC=y
CONFIG_BOARD_RNG_SEED=y

3
configs/light_b_product_defconfig
View File

@@ -20,6 +20,7 @@ CONFIG_DDR_LP4X_3200_SINGLERANK=y
CONFIG_DDR_H32_MODE=y
# CONFIG_DDR_LP4_3733_DUALRANK is not set
CONFIG_DDR_BOARD_CONFIG=y
CONFIG_FIXUP_MEMORY_REGION=y
CONFIG_CMD_BOOT_SLAVE=y
CONFIG_CMD_ERASEENV=y
CONFIG_CMD_GPT=y
@@ -104,3 +105,5 @@ CONFIG_PMIC_VOL_INIT=y
CONFIG_DDR_REGU_0V6=600000
CONFIG_DDR_REGU_0V8=800000
CONFIG_DDR_REGU_1V1=1100000
CONFIG_MISC=y
CONFIG_LIGHT_AON_CONF=y

5
configs/light_b_product_sec_defconfig
View File

@@ -20,6 +20,7 @@ CONFIG_DDR_LP4X_3200_SINGLERANK=y
CONFIG_DDR_H32_MODE=y
# CONFIG_DDR_LP4_3733_DUALRANK is not set
CONFIG_DDR_BOARD_CONFIG=y
CONFIG_FIXUP_MEMORY_REGION=y
CONFIG_CMD_BOOT_SLAVE=y
CONFIG_CMD_ERASEENV=y
CONFIG_CMD_GPT=y
@@ -104,3 +105,7 @@ CONFIG_PMIC_VOL_INIT=y
CONFIG_DDR_REGU_0V6=600000
CONFIG_DDR_REGU_0V8=800000
CONFIG_DDR_REGU_1V1=1100000
CONFIG_MISC=y
CONFIG_LIGHT_AON_CONF=y
# CONFIG_FASTBOOT_CMD_OEM_NV_OPERATION is not set
# CONFIG_FASTBOOT_ECIES_AUTH is not set

7
configs/light_beagle_android_defconfig
View File

@@ -19,6 +19,7 @@ CONFIG_SYS_PROMPT="C910 Light# "
CONFIG_DDR_LP4X_3733_SINGLERANK=y
# CONFIG_DDR_LP4_3733_DUALRANK is not set
CONFIG_DDR_BOARD_CONFIG=y
CONFIG_FIXUP_MEMORY_REGION=n
CONFIG_CMD_BOOT_SLAVE=y
CONFIG_CMD_ERASEENV=y
CONFIG_CMD_GPT=y
@@ -101,6 +102,10 @@ CONFIG_PMIC_VOL_INIT=y
CONFIG_DDR_REGU_0V6=600000
CONFIG_DDR_REGU_0V8=800000
CONFIG_DDR_REGU_1V1=1100000
CONFIG_LIGHT_ANDROID_BOOT_IMAGE_VAL_BEAGLE=y
CONFIG_AVB_USE_OEM_KEY=y
# CONFIG_AVB_ROLLBACK_ENABLE is not set
CONFIG_AVB_HW_ENGINE_ENABLE=y
CONFIG_ANDROID_BOOT_IMAGE=y
CONFIG_LIBAVB=y
CONFIG_AVB_VERIFY=y
@@ -109,3 +114,5 @@ CONFIG_CMD_BOOTANDROID=y
CONFIG_ANDROID_AB=y
CONFIG_CMD_AB_SELECT=y
CONFIG_XBC=y
CONFIG_BOARD_RNG_SEED=y
CONFIG_SPL_TEXT_BASE=0xffe0000800

9
configs/light_lpi4a_android_defconfig
View File

@@ -19,6 +19,7 @@ CONFIG_SYS_PROMPT="C910 Light# "
CONFIG_DDR_LP4X_3733_DUALRANK=y
# CONFIG_DDR_LP4_3733_DUALRANK is not set
CONFIG_DDR_BOARD_CONFIG=y
CONFIG_FIXUP_MEMORY_REGION=y
CONFIG_CMD_BOOT_SLAVE=y
CONFIG_CMD_ERASEENV=y
CONFIG_CMD_GPT=y
@@ -92,7 +93,7 @@ CONFIG_CMD_BMP=y
CONFIG_VIDEO_BRIDGE=y
CONFIG_DM_PCA953X=y
CONFIG_VIDEO_VS_DPU=y
CONFIG_VIDEO_LCD_ILITEK_ILI9881C=y
CONFIG_VIDEO_LCD_JD9365DA=y
CONFIG_VIDEO_DW_DSI_LIGHT=y
CONFIG_VIDEO_DW_DPHY=y
CONFIG_VIDEO_DW_DSI_HOST=y
@@ -101,6 +102,11 @@ CONFIG_PMIC_VOL_INIT=y
CONFIG_DDR_REGU_0V6=600000
CONFIG_DDR_REGU_0V8=800000
CONFIG_DDR_REGU_1V1=1100000
CONFIG_SPL_TEXT_BASE=0xffe0000800
CONFIG_LIGHT_ANDROID_BOOT_IMAGE_VAL_LPI4A=y
CONFIG_AVB_USE_OEM_KEY=y
# CONFIG_AVB_ROLLBACK_ENABLE is not set
CONFIG_AVB_HW_ENGINE_ENABLE=y
CONFIG_ANDROID_BOOT_IMAGE=y
CONFIG_LIBAVB=y
CONFIG_AVB_VERIFY=y
@@ -109,3 +115,4 @@ CONFIG_CMD_BOOTANDROID=y
CONFIG_ANDROID_AB=y
CONFIG_CMD_AB_SELECT=y
CONFIG_XBC=y
CONFIG_BOARD_RNG_SEED=y

12
configs/light_lpi4a_defconfig
View File

@@ -22,6 +22,7 @@ CONFIG_SYS_PROMPT="C910 Light# "
CONFIG_DDR_LP4X_3733_DUALRANK=y
# CONFIG_DDR_LP4_3733_DUALRANK is not set
CONFIG_DDR_BOARD_CONFIG=y
CONFIG_FIXUP_MEMORY_REGION=y
CONFIG_CMD_BOOT_SLAVE=y
CONFIG_CMD_ERASEENV=y
CONFIG_CMD_GPT=y
@@ -32,7 +33,6 @@ CONFIG_CMD_I2C=y
CONFIG_CMD_MEMTEST=y
CONFIG_DDR_SCAN=y
CONFIG_DDR_PRBS_TEST=n
# CONFIG_DOS_PARTITION is not set
# CONFIG_ISO_PARTITION is not set
CONFIG_PARTITION_TYPE_GUID=y
CONFIG_OF_EMBED=y
@@ -77,6 +77,9 @@ CONFIG_SPI=y
CONFIG_DESIGNWARE_SPI=y
CONFIG_DESIGNWARE_QSPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_DWC3=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="U-Boot-THEAD"
@@ -92,10 +95,12 @@ CONFIG_PHY=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_CMD_BMP=y
CONFIG_CMD_USB=y
CONFIG_VIDEO_BRIDGE=y
CONFIG_DM_PCA953X=y
CONFIG_VIDEO_VS_DPU=y
CONFIG_VIDEO_LCD_ILITEK_ILI9881C=y
CONFIG_VIDEO_LCD_ILITEK_ILI9881C=n
CONFIG_VIDEO_LCD_JD9365DA=y
CONFIG_VIDEO_LCD_CUSTOM_LOGO=y
CONFIG_VIDEO_DW_DSI_LIGHT=y
CONFIG_VIDEO_DW_DPHY=y
@@ -105,3 +110,6 @@ CONFIG_PMIC_VOL_INIT=y
CONFIG_DDR_REGU_0V6=600000
CONFIG_DDR_REGU_0V8=800000
CONFIG_DDR_REGU_1V1=1100000
CONFIG_MISC=y
CONFIG_LIGHT_AON_CONF=y

13
configs/light_lpi4a_sec_defconfig
View File

@@ -22,6 +22,7 @@ CONFIG_SYS_PROMPT="C910 Light# "
CONFIG_DDR_LP4X_3733_DUALRANK=y
# CONFIG_DDR_LP4_3733_DUALRANK is not set
CONFIG_DDR_BOARD_CONFIG=y
CONFIG_FIXUP_MEMORY_REGION=y
CONFIG_CMD_BOOT_SLAVE=y
CONFIG_CMD_ERASEENV=y
CONFIG_CMD_GPT=y
@@ -32,7 +33,6 @@ CONFIG_CMD_I2C=y
CONFIG_CMD_MEMTEST=y
CONFIG_DDR_SCAN=y
CONFIG_DDR_PRBS_TEST=n
# CONFIG_DOS_PARTITION is not set
# CONFIG_ISO_PARTITION is not set
CONFIG_PARTITION_TYPE_GUID=y
CONFIG_OF_EMBED=y
@@ -77,6 +77,9 @@ CONFIG_SPI=y
CONFIG_DESIGNWARE_SPI=y
CONFIG_DESIGNWARE_QSPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_DWC3=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="U-Boot-THEAD"
@@ -93,10 +96,12 @@ CONFIG_PHY=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_CMD_BMP=y
CONFIG_CMD_USB=y
CONFIG_VIDEO_BRIDGE=y
CONFIG_DM_PCA953X=y
CONFIG_VIDEO_VS_DPU=y
CONFIG_VIDEO_LCD_ILITEK_ILI9881C=y
CONFIG_VIDEO_LCD_ILITEK_ILI9881C=n
CONFIG_VIDEO_LCD_JD9365DA=y
CONFIG_VIDEO_LCD_CUSTOM_LOGO=y
CONFIG_VIDEO_DW_DSI_LIGHT=y
CONFIG_VIDEO_DW_DPHY=y
@@ -106,3 +111,7 @@ CONFIG_PMIC_VOL_INIT=y
CONFIG_DDR_REGU_0V6=600000
CONFIG_DDR_REGU_0V8=800000
CONFIG_DDR_REGU_1V1=1100000
CONFIG_MISC=y
CONFIG_LIGHT_AON_CONF=y
# CONFIG_FASTBOOT_CMD_OEM_NV_OPERATION is not set
# CONFIG_FASTBOOT_ECIES_AUTH is not set

130
configs/light_rvbook_defconfig Normal file
View File

@@ -0,0 +1,130 @@
CONFIG_RV_BOOK=y
CONFIG_RISCV=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_OFFSET=0xe0000
CONFIG_NR_DRAM_BANKS=8
CONFIG_SPL=y
CONFIG_SMP=y
CONFIG_TARGET_LIGHT_C910=y
CONFIG_TARGET_LIGHT_FM_C910_RVBOOK=y
# CONFIG_THEAD_PLIC is not set
# CONFIG_THEAD_LIGHT_TIMER is not set
# CONFIG_THEAD_LIGHT_DIGITAL_SENSOR is not set
CONFIG_ARCH_RV64I=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BUILD_TARGET="u-boot-with-spl.bin"
CONFIG_DISPLAY_CPUINFO=y
CONFIG_DISPLAY_BOARDINFO=y
# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
CONFIG_SPL_RAM_SUPPORT=y
CONFIG_SPL_RAM_DEVICE=y
CONFIG_SYS_PROMPT="C910 Light# "
CONFIG_DDR_LP4X_3733_DUALRANK=y
# CONFIG_DDR_LP4_3733_DUALRANK is not set
CONFIG_DDR_BOARD_CONFIG=y
CONFIG_FIXUP_MEMORY_REGION=y
CONFIG_CMD_BOOT_SLAVE=y
CONFIG_CMD_ERASEENV=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MTD=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_SPI=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MEMTEST=y
CONFIG_DDR_SCAN=y
CONFIG_DDR_PRBS_TEST=n
# CONFIG_DOS_PARTITION is not set
# CONFIG_ISO_PARTITION is not set
CONFIG_PARTITION_TYPE_GUID=y
CONFIG_OF_EMBED=y
CONFIG_DEFAULT_DEVICE_TREE="th1520-rvbook"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SPL_CLK=y
CONFIG_USB_FUNCTION_FASTBOOT=y
CONFIG_UDP_FUNCTION_FASTBOOT=y
CONFIG_FASTBOOT_BUF_ADDR=0x10000000
CONFIG_FASTBOOT_FLASH=y
CONFIG_FASTBOOT_FLASH_MMC_DEV=0
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
CONFIG_DM_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_DW=y
CONFIG_DWAPB_GPIO=y
# CONFIG_MMC_SPI is not set
CONFIG_MMC_VERBOSE=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_IO_VOLTAGE=y
CONFIG_MMC_UHS_SUPPORT=y
CONFIG_MMC_HS400_SUPPORT=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_SNPS=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SNPS=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_CMD_MMC=y
CONFIG_CMD_MMC_RPMB=y
CONFIG_SUPPORT_EMMC_RPMB=y
CONFIG_DM_MTD=y
CONFIG_MTD_SPI_NAND=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_PHY_REALTEK=y
CONFIG_RTL8211E_PINE64_GIGABIT_FIX=y
CONFIG_RTL8211X_PHY_FORCE_MASTER=y
CONFIG_RTL8211F_PHY_FORCE_EEE_RXC_ON=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DESIGNWARE_SPI=y
CONFIG_DESIGNWARE_QSPI=y
CONFIG_USB=y
CONFIG_USB_DWC3=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="U-Boot-THEAD"
CONFIG_USB_GADGET_VENDOR_NUM=0x1234
CONFIG_USB_GADGET_PRODUCT_NUM=0x8888
# CONFIG_SPL_USE_TINY_PRINTF is not set
# CONFIG_EFI_LOADER is not set
# CONFIG_LIGHT_SEC_BOOT is not set
CONFIG_BOARD_LATE_INIT=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_DM_VIDEO=y
CONFIG_PHY=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_CMD_BMP=y
CONFIG_VIDEO_BRIDGE=y
CONFIG_DM_PCA953X=y
CONFIG_VIDEO_VS_DPU=y
CONFIG_VIDEO_LCD_ILITEK_ILI9881C=y
CONFIG_VIDEO_LCD_CUSTOM_LOGO=y
CONFIG_VIDEO_DW_DSI_LIGHT=y
CONFIG_VIDEO_DW_DPHY=y
CONFIG_VIDEO_DW_DSI_HOST=y
CONFIG_SYS_WHITE_ON_BLACK=y
CONFIG_PMIC_VOL_INIT=y
CONFIG_DDR_REGU_0V6=600000
CONFIG_DDR_REGU_0V8=800000
CONFIG_DDR_REGU_1V1=1100000
CONFIG_TPM=y
CONFIG_TPM_V2=y
CONFIG_TPM_Z32H330TC_SPI=y
CONFIG_CMD_TPM=y
CONFIG_CMD_TPM_V2=y
CONFIG_CMD_TPM_TEST=y
CONFIG_DM_CHARGE_DISPLAY=y
CONFIG_CHARGE_ANIMATION=y
CONFIG_DM_FUEL_GAUGE=y
CONFIG_POWER_FG_CW201X=y
CONFIG_CHARGER_BQ25700=y
CONFIG_LED=y
CONFIG_LED_GPIO=y
CONFIG_DM_MCU=y
CONFIG_MCU_HC32fX=y
CONFIG_DM_POWER_DELIVERY=y
CONFIG_TYPEC_TCPM=y
CONFIG_TYPEC_TCPCI=y
CONFIG_TYPEC_HUSB311=y
CONFIG_MISC=y
CONFIG_LIGHT_AON_CONF=y

132
configs/light_rvbook_sec_defconfig Normal file
View File

@@ -0,0 +1,132 @@
CONFIG_RV_BOOK=y
CONFIG_RISCV=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_OFFSET=0xe0000
CONFIG_NR_DRAM_BANKS=8
CONFIG_SPL=y
CONFIG_SMP=y
CONFIG_TARGET_LIGHT_C910=y
# CONFIG_THEAD_PLIC is not set
# CONFIG_THEAD_LIGHT_TIMER is not set
# CONFIG_THEAD_LIGHT_DIGITAL_SENSOR is not set
CONFIG_ARCH_RV64I=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BUILD_TARGET="u-boot-with-spl.bin"
CONFIG_DISPLAY_CPUINFO=y
CONFIG_DISPLAY_BOARDINFO=y
# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
CONFIG_SPL_RAM_SUPPORT=y
CONFIG_SPL_RAM_DEVICE=y
CONFIG_SYS_PROMPT="C910 Light# "
CONFIG_DDR_LP4X_3733_DUALRANK=y
# CONFIG_DDR_LP4_3733_DUALRANK is not set
CONFIG_DDR_BOARD_CONFIG=y
CONFIG_FIXUP_MEMORY_REGION=y
CONFIG_CMD_BOOT_SLAVE=y
CONFIG_CMD_ERASEENV=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MTD=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_SPI=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MEMTEST=y
CONFIG_DDR_SCAN=y
CONFIG_DDR_PRBS_TEST=n
# CONFIG_DOS_PARTITION is not set
# CONFIG_ISO_PARTITION is not set
CONFIG_PARTITION_TYPE_GUID=y
CONFIG_OF_EMBED=y
CONFIG_DEFAULT_DEVICE_TREE="th1520-rvbook"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SPL_CLK=y
CONFIG_USB_FUNCTION_FASTBOOT=y
CONFIG_UDP_FUNCTION_FASTBOOT=y
CONFIG_FASTBOOT_BUF_ADDR=0x10000000
CONFIG_FASTBOOT_FLASH=y
CONFIG_FASTBOOT_FLASH_MMC_DEV=0
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
CONFIG_DM_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_DW=y
CONFIG_DWAPB_GPIO=y
# CONFIG_MMC_SPI is not set
CONFIG_MMC_VERBOSE=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_IO_VOLTAGE=y
CONFIG_MMC_UHS_SUPPORT=y
CONFIG_MMC_HS400_SUPPORT=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_SNPS=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SNPS=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_CMD_MMC=y
CONFIG_CMD_MMC_RPMB=y
CONFIG_SUPPORT_EMMC_RPMB=y
CONFIG_DM_MTD=y
CONFIG_MTD_SPI_NAND=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_PHY_REALTEK=y
CONFIG_RTL8211E_PINE64_GIGABIT_FIX=y
CONFIG_RTL8211X_PHY_FORCE_MASTER=y
CONFIG_RTL8211F_PHY_FORCE_EEE_RXC_ON=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DESIGNWARE_SPI=y
CONFIG_DESIGNWARE_QSPI=y
CONFIG_USB=y
CONFIG_USB_DWC3=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="U-Boot-THEAD"
CONFIG_USB_GADGET_VENDOR_NUM=0x1234
CONFIG_USB_GADGET_PRODUCT_NUM=0x8888
# CONFIG_SPL_USE_TINY_PRINTF is not set
# CONFIG_EFI_LOADER is not set
CONFIG_LIGHT_SEC_BOOT_WITH_VERIFY_RVBOOK=y
CONFIG_LIGHT_SEC_UPGRADE=y
CONFIG_BOARD_LATE_INIT=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_DM_VIDEO=y
CONFIG_PHY=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_CMD_BMP=y
CONFIG_VIDEO_BRIDGE=y
CONFIG_DM_PCA953X=y
CONFIG_VIDEO_VS_DPU=y
CONFIG_VIDEO_LCD_ILITEK_ILI9881C=y
CONFIG_VIDEO_LCD_CUSTOM_LOGO=y
CONFIG_VIDEO_DW_DSI_LIGHT=y
CONFIG_VIDEO_DW_DPHY=y
CONFIG_VIDEO_DW_DSI_HOST=y
CONFIG_SYS_WHITE_ON_BLACK=y
CONFIG_PMIC_VOL_INIT=y
CONFIG_DDR_REGU_0V6=600000
CONFIG_DDR_REGU_0V8=800000
CONFIG_DDR_REGU_1V1=1100000
CONFIG_TPM=y
CONFIG_TPM_V2=y
CONFIG_TPM_Z32H330TC_SPI=y
CONFIG_CMD_TPM=y
CONFIG_CMD_TPM_V2=y
CONFIG_CMD_TPM_TEST=y
CONFIG_DM_CHARGE_DISPLAY=y
CONFIG_CHARGE_ANIMATION=y
CONFIG_DM_FUEL_GAUGE=y
CONFIG_POWER_FG_CW201X=y
CONFIG_CHARGER_BQ25700=y
CONFIG_LED=y
CONFIG_LED_GPIO=y
CONFIG_DM_MCU=y
CONFIG_MCU_HC32fX=y
CONFIG_DM_POWER_DELIVERY=y
CONFIG_TYPEC_TCPM=y
CONFIG_TYPEC_TCPCI=y
CONFIG_TYPEC_HUSB311=y
CONFIG_MISC=y
CONFIG_LIGHT_AON_CONF=y
CONFIG_FASTBOOT_CMD_OEM_NV_OPERATION=y

2
drivers/Kconfig
View File

@@ -130,6 +130,8 @@ source "drivers/w1-eeprom/Kconfig"
source "drivers/watchdog/Kconfig"
source "drivers/mcu/Kconfig"
config PHYS_TO_BUS
bool "Custom physical to bus address mapping"
help

3
drivers/Makefile
View File

@@ -85,6 +85,9 @@ obj-y += misc/
obj-$(CONFIG_MMC) += mmc/
obj-$(CONFIG_NVME) += nvme/
obj-$(CONFIG_PCI_ENDPOINT) += pci_endpoint/
ifdef CONFIG_RV_BOOK
obj-$(CONFIG_DM_POWER_DELIVERY) += power/power_delivery/
endif
obj-y += dfu/
obj-$(CONFIG_PCH) += pch/
obj-y += phy/allwinner/

8
drivers/fastboot/Kconfig
View File

@@ -135,6 +135,14 @@ config FASTBOOT_CMD_OEM_FORMAT
relies on the env variable partitions to contain the list of
partitions as required by the gpt command.
config FASTBOOT_CMD_OEM_NV_OPERATION
bool "Enable the 'oem nv get/set' command"
help
Add support for the "oem get/set" command from a client.
config FASTBOOT_ECIES_AUTH
bool "Enabled ecies fastboot auth"
endif # FASTBOOT
endmenu

2
drivers/fastboot/Makefile
View File

@@ -3,5 +3,7 @@
obj-y += fb_common.o
obj-y += fb_getvar.o
obj-y += fb_command.o
obj-$(CONFIG_FASTBOOT_ECIES_AUTH) += fb_ecies.o
obj-$(CONFIG_FASTBOOT_FLASH_MMC) += fb_mmc.o
obj-$(CONFIG_FASTBOOT_FLASH_NAND) += fb_nand.o
obj-$(CONFIG_FASTBOOT_CMD_OEM_NV_OPERATION) += fb_nv_operation.o

272
drivers/fastboot/fb_command.c
View File

@@ -14,6 +14,7 @@
#include <stdlib.h>
#define BLOCK_SIZE 512
#define BOARD_ID_OFFSET 0x26
/**
* image_size - final fastboot image size
@@ -42,6 +43,20 @@ static void reboot_bootloader(char *, char *);
static void oem_format(char *, char *);
#endif
static void oem_command(char *, char *);
int image_have_head(unsigned long img_src_addr);
#if CONFIG_FASTBOOT_CMD_OEM_NV_OPERATION
void oem_nv_get_proccess(char *cmd_parameter, char *response);
void oem_nv_set_proccess(char *cmd_parameter, char *response);
void oem_nv_factory_recovery_process(char *cmd_parameter, char *response);
static void oem_nv_get(char *cmd_parameter, char *response);
static void oem_nv_set(char *cmd_parameter, char *response);
static void oem_fcty(char *cmd_parameter, char *response);
#endif
#ifdef CONFIG_FASTBOOT_ECIES_AUTH
int ecies_process_data(uint8_t * data, int data_size,char *response);
#endif
static const struct {
const char *command;
@@ -95,6 +110,20 @@ static const struct {
.command = "oem command",
.dispatch = oem_command,
},
#if CONFIG_FASTBOOT_CMD_OEM_NV_OPERATION
[FASTBOOT_COMMAND_OEM_NV_GET] = {
.command = "oem nv get",
.dispatch = oem_nv_get,
},
[FASTBOOT_COMMAND_OEM_NV_SET] = {
.command = "oem nv set",
.dispatch = oem_nv_set,
},
[FASTBOOT_COMMAND_OEM_FCTY] = {
.command = "oem fcty",
.dispatch = oem_fcty,
},
#endif
};
/**
@@ -263,7 +292,119 @@ void fastboot_data_complete(char *response)
fastboot_bytes_received = 0;
}
/**
* check_image_board_id() - check if board id in image matched with board id in env
*
* @image_data: Image data
*
* 0 if success otherwise failed
*/
int check_image_board_id(uint8_t *image_data)
{
char *env_board_id = NULL;
char board_id[3] = {0};
env_board_id = env_get("board#");
/*if current board id is null or image has no header,skip check*/
if (env_board_id == NULL || env_board_id[0] == 0 || image_have_head((unsigned long)image_data) == 0) {
return 0;
}
memcpy(board_id, image_data + BOARD_ID_OFFSET,sizeof(uint16_t));
/*if image board id is null,skip check*/
if (*(uint16_t*)board_id == 0) {
return 0;
}
/*check if current board id match with board id in image*/
if (strncmp(env_board_id, board_id, sizeof(board_id)) != 0) {
printf("U-BOOT image download via fastboot is interrupted due to the U-BOOT for board %s does not work in the board %s\r\n",board_id,env_board_id);
return -1;
}
return 0;
}
int hibernate_image_cleaned_flag = 0;
void clean_hibernate_image_header(char *response)
{
struct blk_desc *dev_desc;
disk_partition_t info;
if(0x03 == hibernate_image_cleaned_flag) //already erased all
{
return;
}
dev_desc = blk_get_dev("mmc", CONFIG_FASTBOOT_FLASH_MMC_DEV);
if (!dev_desc || dev_desc->type == DEV_TYPE_UNKNOWN) {
fastboot_fail("invalid mmc device", response);
return;
}
char * buf = memalign(CONFIG_SYS_CACHELINE_SIZE,4096);
if(!buf) {
printf(" mem alloc for hibernate partition header failed!\n");
return;
}
/* if fastresume partition exists, earse the old image header */
if(part_get_info_by_name(dev_desc, "fastresume", &info)) {
printf(" find fastresume partition , erase the header:\n");
memset(buf,0xff,4096);
if(blk_dwrite(dev_desc, info.start, 4096/info.blksz, buf) != 4096/info.blksz)
{
printf(" fastresume header write failed!\n");
hibernate_image_cleaned_flag = 0;
}
else
{
hibernate_image_cleaned_flag |= 0x1;
}
}
/* if swap partition exists, earse the old image header */
if(part_get_info_by_name(dev_desc, "swap", &info)) {
printf(" find swap partition , erase the header:\n");
memset(buf,0xff,4096);
if(blk_dwrite(dev_desc, info.start, 4096/info.blksz, buf) != 4096/info.blksz)
{
printf(" swap header write failed!\n");
hibernate_image_cleaned_flag = 0;
}
else
{
hibernate_image_cleaned_flag |= 0x2;
}
}
free(buf);
}
#if CONFIG_IS_ENABLED(FASTBOOT_FLASH)
void fasboot_uboot_write_process(void *buf, char *response)
{
char cmdbuf[32];
u32 block_cnt;
struct blk_desc *dev_desc;
int ret = 0;
disk_partition_t info;
ret = check_image_board_id(buf);
if (ret != 0) {
fastboot_fail("U-BOOT image does not match the type of BOARD", response);
return;
}
dev_desc = blk_get_dev("mmc", CONFIG_FASTBOOT_FLASH_MMC_DEV);
if (!dev_desc || dev_desc->type == DEV_TYPE_UNKNOWN) {
fastboot_fail("invalid mmc device", response);
return;
}
run_command("mmc partconf 0 1 0 1", 0);
block_cnt = image_size / BLOCK_SIZE;
if (image_size % BLOCK_SIZE) {
block_cnt = block_cnt +1;
}
sprintf(cmdbuf, "mmc write 0x%p 0 %x", buf, block_cnt);
run_command(cmdbuf, 0);
run_command("mmc partconf 0 1 0 0", 0);
}
/**
* flash() - write the downloaded image to the indicated partition.
*
@@ -277,28 +418,10 @@ static void flash(char *cmd_parameter, char *response)
{
#ifdef THEAD_LIGHT_FASTBOOT
char cmdbuf[32];
u32 block_cnt;
struct blk_desc *dev_desc;
disk_partition_t info;
if (strcmp(cmd_parameter, "uboot") == 0) {
dev_desc = blk_get_dev("mmc", CONFIG_FASTBOOT_FLASH_MMC_DEV);
if (!dev_desc || dev_desc->type == DEV_TYPE_UNKNOWN) {
fastboot_fail("invalid mmc device", response);
return;
}
run_command("mmc partconf 0 1 0 1", 0);
block_cnt = image_size / BLOCK_SIZE;
if (image_size % BLOCK_SIZE) {
block_cnt = block_cnt +1;
}
sprintf(cmdbuf, "mmc write 0x%p 0 %x", fastboot_buf_addr, block_cnt);
run_command(cmdbuf, 0);
run_command("mmc partconf 0 1 0 0", 0);
fasboot_uboot_write_process(fastboot_buf_addr, response);
} else if ((strcmp(cmd_parameter, "fw") == 0)) {
memcpy((void *)LIGHT_FW_ADDR, fastboot_buf_addr, image_size);
} else if ((strcmp(cmd_parameter, "uImage") == 0)) {
@@ -313,7 +436,42 @@ static void flash(char *cmd_parameter, char *response)
memcpy((void *)LIGHT_TF_FW_ADDR, fastboot_buf_addr, image_size);
} else if ((strcmp(cmd_parameter, TEE_PART_NAME) == 0)) {
memcpy((void *)LIGHT_TEE_FW_ADDR, fastboot_buf_addr, image_size);
}
}
#ifdef CONFIG_RV_BOOK
else if ((strcmp(cmd_parameter, "boot") == 0)) {
dev_desc = blk_get_dev("mmc", CONFIG_FASTBOOT_FLASH_MMC_DEV);
if (!dev_desc || dev_desc->type == DEV_TYPE_UNKNOWN) {
fastboot_fail("invalid mmc device", response);
return;
}
/* if fastresume partition exists, earse the old image header */
if(part_get_info_by_name(dev_desc, "fastresume", &info)) {
printf(" find fastresume partition , erase the header:\n");
char * buf = memalign(CONFIG_SYS_CACHELINE_SIZE,4096);
if(!buf) {
printf(" fastresume partition header mem alloc failed\n");
return;
}
memset(buf,0xff,4096);
blk_dwrite(dev_desc, info.start, 4096/info.blksz, buf);
free(buf);
}
}
#endif
#ifdef CONFIG_FASTBOOT_ECIES_AUTH
else if ((strcmp(cmd_parameter, "ecies") == 0)) {
ecies_process_data(fastboot_buf_addr, image_size,response);
return;
}
#endif
//If version is updated, hibernate image may not compatible with current,erase it.
if ((strcmp(cmd_parameter, "boot") == 0)
|| (strcmp(cmd_parameter, "uboot") == 0)
|| (strcmp(cmd_parameter, "root") == 0)) {
clean_hibernate_image_header(response);
}
if(strcmp(cmd_parameter, "uboot") == 0 || (strcmp(cmd_parameter, "fw") == 0) ||
(strcmp(cmd_parameter, "uImage") == 0) || (strcmp(cmd_parameter, "dtb") == 0) ||
@@ -324,38 +482,7 @@ static void flash(char *cmd_parameter, char *response)
#endif
#if CONFIG_IS_ENABLED(LIGHT_SEC_UPGRADE)
if(strcmp(cmd_parameter, TF_IMG_UPD_NAME) == 0) {
#if CONFIG_IS_ENABLED(FASTBOOT_FLASH_MMC)
/* tee/tf/uboot image must be written into stash partition */
sprintf(cmdbuf, "%s", STASH_PART_NAME);
fastboot_mmc_flash_write(cmdbuf, fastboot_buf_addr, image_size, response);
#endif
/* Send ACK to host */
fastboot_okay(NULL, response);
/* set secure upgrade flag to indicate it is TF image upgrade*/
sprintf(cmdbuf,"env set sec_upgrade_mode 0x%x", TF_SEC_UPGRADE_FLAG);
run_command(cmdbuf, 0);
run_command("saveenv", 0);
run_command("reset", 0);
return;
} else if (strcmp(cmd_parameter, TEE_IMG_UPD_NAME) == 0) {
#if CONFIG_IS_ENABLED(FASTBOOT_FLASH_MMC)
/* tee/tf/uboot image must be written into stash partition */
sprintf(cmdbuf, "%s", STASH_PART_NAME);
fastboot_mmc_flash_write(cmdbuf, fastboot_buf_addr, image_size, response);
#endif
/* Send ACK to host */
fastboot_okay(NULL, response);
/* set secure upgrade flag to indicate it is TEE image upgrade*/
sprintf(cmdbuf,"env set sec_upgrade_mode 0x%x", TEE_SEC_UPGRADE_FLAG);
run_command(cmdbuf, 0);
run_command("saveenv", 0);
run_command("reset", 0);
return;
} else if (strcmp(cmd_parameter, UBOOT_IMG_UPD_NAME) == 0) {
if (strcmp(cmd_parameter, UBOOT_IMG_UPD_NAME) == 0) {
#if CONFIG_IS_ENABLED(FASTBOOT_FLASH_MMC)
env_set_hex("ubootupdsize", image_size);
@@ -366,14 +493,14 @@ static void flash(char *cmd_parameter, char *response)
/* Send ACK to host */
fastboot_okay(NULL, response);
/* set secure upgrade flag to indicate it is UBOOT image upgrade*/
sprintf(cmdbuf,"env set sec_upgrade_mode 0x%x", UBOOT_SEC_UPGRADE_FLAG);
run_command(cmdbuf, 0);
run_command("saveenv", 0);
run_command("reset", 0);
return;
}
}
#endif
#if CONFIG_IS_ENABLED(FASTBOOT_FLASH_MMC)
@@ -458,3 +585,38 @@ static void oem_command(char *cmd_parameter, char *response)
else
fastboot_okay(NULL, response);
}
#if CONFIG_FASTBOOT_CMD_OEM_NV_OPERATION
/**
* oem_nv_get() - Execute the OEM NV GET command
*
* @cmd_parameter: Pointer to command parameter
* @response: Pointer to fastboot response buffer
*/
static void oem_nv_get(char *cmd_parameter, char *response)
{
oem_nv_get_proccess(cmd_parameter,response);
}
/**
* oem_nv_set() - Execute the OEM NV Set command
*
* @cmd_parameter: Pointer to command parameter
* @response: Pointer to fastboot response buffer
*/
static void oem_nv_set(char *cmd_parameter, char *response)
{
oem_nv_set_proccess(cmd_parameter,response);
}
/**
* oem_fcty() - Execute the OEM fcty command
*
* @cmd_parameter: Pointer to command parameter
* @response: Pointer to fastboot response buffer
*/
static void oem_fcty(char *cmd_parameter, char *response)
{
oem_nv_factory_recovery_process(cmd_parameter,response);
}
#endif

198
drivers/fastboot/fb_ecies.c Normal file
View File

@@ -0,0 +1,198 @@
#include <sec_ecies_session.h>
#include <common.h>
#include <command.h>
#include <env.h>
#include <fastboot.h>
#include <fastboot-internal.h>
#include <fb_mmc.h>
#include <fb_nand.h>
#include <part.h>
#include <stdlib.h>
#include <csi_sec_img_verify.h>
#if CONFIG_IS_ENABLED(FASTBOOT_FLASH)
extern void fasboot_uboot_write_process(void *buf, char *response);
#define MAX_ECIES_IMAGE_SIZE (9*1024*1024)
#define ECIES_MALLOC_START (MAX_ECIES_IMAGE_SIZE * 2)
typedef struct {
uint32_t magic;
uint32_t file_size;
char partition_name[64];
} __attribute__((__packed__)) send_file_info_t;
static uint32_t ecies_file_pos = 0;
static int slave_init = 0;
static int current_pos = 0;
void *csi_ecies_malloc(uint32_t size)
{
void * ptr = NULL;
if (current_pos + size >= CONFIG_FASTBOOT_BUF_SIZE) {
current_pos = 0;
}
ptr = (void *)(long)(CONFIG_FASTBOOT_BUF_ADDR + ECIES_MALLOC_START + current_pos);
current_pos += size;
return ptr;
};
void csi_ecies_free(void *buffer)
{
return;
};
static int ecies_data_write(uint8_t *buf,uint8_t *data,int data_len)
{
char response[FASTBOOT_RESPONSE_LEN];
if (data_len == 0 || buf == NULL || data == NULL) {
return -1;
}
memcpy(buf + ecies_file_pos,data,data_len);
ecies_file_pos += data_len;
if (ecies_file_pos == sizeof(send_file_info_t) + ((send_file_info_t *)buf)->file_size) {
if (strcmp(((send_file_info_t *)buf)->partition_name, TEE_PART_NAME) == 0) {
memcpy((void *)LIGHT_TEE_FW_ADDR, buf + sizeof(send_file_info_t), ((send_file_info_t *)buf)->file_size);
#if CONFIG_IS_ENABLED(FASTBOOT_FLASH_MMC)
fastboot_mmc_flash_write(((send_file_info_t *)buf)->partition_name, buf + sizeof(send_file_info_t), ((send_file_info_t *)buf)->file_size,
response);
#endif
#if CONFIG_IS_ENABLED(FASTBOOT_FLASH_NAND)
fastboot_nand_flash_write(((send_file_info_t *)buf)->partition_name, buf + sizeof(send_file_info_t), ((send_file_info_t *)buf)->file_size,
response);
#endif
} else if (strcmp(((send_file_info_t *)buf)->partition_name, UBOOT_PART_NAME) == 0) {
fasboot_uboot_write_process(buf + sizeof(send_file_info_t),response);
} else {
printf("unknown partition name\n");
return -2;
}
ecies_file_pos = 0;
} else if(ecies_file_pos > sizeof(send_file_info_t) + ((send_file_info_t *)buf)->file_size) {
return -3;
}
return 0;
}
static void hex_to_str(char *dest, const uint8_t *src, int len)
{
char ddl = 0;
char ddh = 0;
int i = 0;
for (i = 0; i < len; i++) {
ddh = 48 + src[i] / 16;
ddl = 48 + src[i] % 16;
if (ddh > 57) {
ddh = ddh + 7;
}
if (ddl > 57) {
ddl = ddl + 7;
}
dest[i * 2] = ddh;
dest[i * 2 + 1] = ddl;
}
dest[len * 2] = '\0';
}
int ecies_process_data(uint8_t * data, int data_size,char *response)
{
static ecies_session_t ss_slave;
char apduResponse[ECIES_INIT_RESPONSE_LEN] = {0};
uint8_t *plaintext = csi_ecies_malloc(MAX_ECIES_IMAGE_SIZE);
uint32_t plaintextLen = 0;
uint32_t apduResponseLen = 0;
int ret = 0;
uint8_t cla = 0;
uint8_t errcode = 0;
if (plaintext == NULL) {
ret = -1;
goto end;
}
if (!slave_init) {
csi_sec_library_init();
ret = hal_ecies_slave_init(&ss_slave);
if (ret != 0) {
strcpy(response,"hal_ecies_slave_init ERROR");
ret = -2;
goto end;
}
}
ret = hal_ecies_slave_session_comm(&ss_slave, data, data_size, (uint8_t *)apduResponse, &apduResponseLen, plaintext, &plaintextLen);
if (ret != 0) {
ret = hal_ecies_status_get((uint8_t *)apduResponse, apduResponseLen, &cla, &errcode);
if (ret != 0) {
strcpy(response,"hal_ecies_errcode_get ERROR");
ret = -3;
goto end;
}
if (cla == ECIES_CLA_INITIALIZE_UPDATE_RESPONSE && errcode == ECIES_RESPONSE_SESSION_OPENED_ERROR) {
slave_init = 0;
ecies_file_pos = 0;
hal_ecies_slave_uninit(&ss_slave);
ret = hal_ecies_slave_init(&ss_slave);
if (ret != 0) {
strcpy(response,"hal_ecies_slave_init ERROR");
ret = -4;
goto end;
}
ret = hal_ecies_slave_session_comm(&ss_slave, data, data_size, (uint8_t*)apduResponse, &apduResponseLen, plaintext, &plaintextLen);
if (ret != 0) {
strcpy(response,"hal_ecies_slave_session_comm ERROR");
ret = -5;
goto end;
}
} else if(errcode != ECIES_RESPONSE_OK) {
if (errcode == ECIES_CLA_SDATA_SEND_RESPONSE) {
strcpy(response,"ECIES_CLA_SDATA_SEND_RESPONSE ERROR");
ret = -6;
goto end;
} else if (errcode == ECIES_CLA_SESSION_CLOSE) {
strcpy(response,"ECIES_CLA_SESSION_CLOSE ERROR");
ret = -7;
goto end;
} else if (errcode == ECIES_CLA_INITIALIZE_UPDATE) {
strcpy(response,"ECIES_CLA_INITIALIZE_UPDATE ERROR");
ret = -8;
goto end;
}
}
}
if (slave_init && plaintextLen) {
ret = ecies_data_write((uint8_t*)(long)(CONFIG_FASTBOOT_BUF_ADDR + MAX_ECIES_IMAGE_SIZE),plaintext,plaintextLen);
if (ret != 0) {
strcpy(response,"ecies_data_write ERROR");
ret = -8;
goto end;
}
}
slave_init = 1;
strcpy(response,"SUCCESS:");
hex_to_str(response + strlen(response),(uint8_t*)apduResponse,apduResponseLen);
ret = 0;
end:
if (plaintext) {
csi_ecies_free(plaintext);
plaintext = NULL;
}
return ret;
}
#endif

342
drivers/fastboot/fb_nv_operation.c Normal file
View File

@@ -0,0 +1,342 @@
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <common.h>
#include <fb_mmc.h>
#include <command.h>
#include <asm/io.h>
#include <asm/types.h>
#include <configs/light-c910.h>
#include <thead/clock_config.h>
#include <linux/bitops.h>
#include <asm/arch-thead/light-iopmp.h>
#include "../lib/sec_library/include/soc.h"
#define MAX_NV_NUMBER_SIZE 32
#define MAX_NV_DATA_SIZE 128
#define NV_BLOCK_SIZE 512
extern int32_t wj_efuse_get_lc(long unsigned int, int *lc);
typedef enum {
FB_SYS_ACTION_FACTORY_RECOVER,
FB_SYS_ACTION_READ_EFUSE,
} fb_sys_action_t;
static int nv_get(uint8_t *data,int offset,int data_len)
{
struct blk_desc *dev_desc;
struct disk_partition part_info;
ulong block_start;
uint8_t data_nv[NV_BLOCK_SIZE] = {0};
int ret;
int n;
dev_desc = blk_get_dev("mmc", CONFIG_FASTBOOT_FLASH_MMC_DEV);
if (dev_desc == NULL) {
return -1;
}
ret = part_get_info_by_name(dev_desc, NV_PARTITION_NAME, &part_info);
if (ret < 0) {
return -2;
}
if(NV_BLOCK_SIZE != dev_desc->blksz) {
return -4;
}
block_start = part_info.start + offset / dev_desc->blksz;
n = blk_dread(dev_desc, block_start, 1, data_nv);
if (n != 1) {
return -5;
}
memcpy(data,data_nv + offset % NV_BLOCK_SIZE,data_len);
return 0;
}
static int nv_set(uint8_t *data,int offset,int data_len)
{
struct blk_desc *dev_desc;
struct disk_partition part_info;
ulong block_start;
uint8_t data_nv[NV_BLOCK_SIZE] = {0};
int ret;
int n;
dev_desc = blk_get_dev("mmc", CONFIG_FASTBOOT_FLASH_MMC_DEV);
if (dev_desc == NULL) {
return -1;
}
ret = part_get_info_by_name(dev_desc, NV_PARTITION_NAME, &part_info);
if (ret < 0) {
return -2;
}
if (NV_BLOCK_SIZE != dev_desc->blksz) {
return -3;
}
block_start = part_info.start + offset / dev_desc->blksz;
n = blk_dread(dev_desc, block_start, 1, data_nv);
if (n != 1) {
return -4;
}
memcpy(data_nv + offset % NV_BLOCK_SIZE,data,data_len);
n = blk_dwrite(dev_desc, block_start, 1, data_nv);
if (n != 1) {
return -5;
}
return 0;
}
static int factory_recovery(char *response)
{
#if CONFIG_IS_ENABLED(FASTBOOT_FLASH_MMC)
fastboot_mmc_erase("metadata", response);
if (strcmp(response, "OKAY") != 0) {
return -1;
}
fastboot_mmc_erase("misc", response);
if (strcmp(response, "OKAY") != 0) {
return -2;
}
#endif
#if CONFIG_IS_ENABLED(FASTBOOT_FLASH_NAND)
fastboot_nand_erase("metadata", response);
if (strcmp(response, "OKAY") != 0) {
return -3;
}
fastboot_nand_erase("misc", response);
if (strcmp(response, "OKAY") != 0) {
return -4;
}
#endif
strcpy(response,"OKAY");
return 0;
}
static int read_efuse_status(char *response)
{
int ret;
int lc = 0;
ret = wj_efuse_get_lc(WJ_EFUSE_BASE, &lc);
if (ret) {
return -1;
}
if(lc == 0) {
strcpy(response,"LC_INIT");
} else {
strcpy(response,"LC_BLOWNED");
}
return 0;
}
static int sys_action(int flag,char *response)
{
if (flag == FB_SYS_ACTION_FACTORY_RECOVER) {
return factory_recovery(response);
} else if (flag == FB_SYS_ACTION_READ_EFUSE) {
return read_efuse_status(response);
} else {
return -1;
}
return 0;
}
static int toupper(int c)
{
if (c >= 'a' && c <= 'z') {
return c - 32;
}
return c;
}
static void str_to_hex(uint8_t *dest, const char *src, int len)
{
char h1, h2;
unsigned char s1, s2;
for (int i = 0; i < len; i++) {
h1 = src[2 * i];
h2 = src[2 * i + 1];
s1 = toupper(h1) - 48;
s2 = toupper(h2) - 48;
if (s1 > 9) {
s1 = s1 - 7;
}
if (s2 > 9) {
s2 = s2 - 7;
}
dest[i] = s1 * 16 + s2;
}
}
static void hex_to_str(char *dest, const uint8_t *src, int len)
{
char ddl = 0;
char ddh = 0;
int i = 0;
for (i = 0; i < len; i++) {
ddh = 48 + src[i] / 16;
ddl = 48 + src[i] % 16;
if (ddh > 57) {
ddh = ddh + 7;
}
if (ddl > 57) {
ddl = ddl + 7;
}
dest[i * 2] = ddh;
dest[i * 2 + 1] = ddl;
}
dest[len * 2] = '\0';
}
static int char_to_int(char *data,int *out)
{
*out = 0;
while(*data) {
if(*data < '0' || *data > '9')
return -1;
*out = *out * 10 + (*data - '0');
++data;
}
return 0;
}
#if CONFIG_FASTBOOT_CMD_OEM_NV_OPERATION
void oem_nv_factory_recovery_process(char *cmd_parameter, char *response)
{
int ret = 0;
int flag = 0;
ret = char_to_int(cmd_parameter,&flag);
if (ret != 0) {
strcpy(response,"ERROR FLAG INVALID");
return;
}
ret = sys_action(flag,response);
if (ret != 0) {
strcpy(response,"ERROR SYS ACTION FAILED");
return;
}
}
void oem_nv_get_proccess(char *cmd_parameter, char *response)
{
char *sep = NULL;
char offset[MAX_NV_NUMBER_SIZE] = {0};
char len[MAX_NV_NUMBER_SIZE] = {0};
int sep_pos = 0;
uint8_t nv_data[MAX_NV_DATA_SIZE + 32] = {0};
char nv_data_str[MAX_NV_DATA_SIZE * 2 + 1] = {0};
int ret;
int offset_int = 0;
int len_int = 0;
sep = strstr(cmd_parameter, ":");
if (sep == NULL) {
strcpy(response,"ERROR INVALID PARAM");
return;
}
sep_pos = sep - cmd_parameter;
memcpy(offset,cmd_parameter,sep - cmd_parameter);
memcpy(len,cmd_parameter + (sep - cmd_parameter) + 1,strlen(cmd_parameter) - sep_pos - 1);
ret = char_to_int(offset,&offset_int);
if (ret != 0) {
strcpy(response,"ERROR OFFSET INVALID");
return;
}
ret = char_to_int(len,&len_int);
if (ret != 0) {
strcpy(response,"ERROR LEN INVALID");
return;
}
if (len_int > MAX_NV_DATA_SIZE) {
strcpy(response,"ERROR NV SIZE TOO LARGE");
return;
}
ret = nv_get(nv_data, offset_int, len_int);
if (ret != 0) {
printf("nv_get failed:%d\n",ret);
strcpy(response,"ERROR NV GET FAILED");
return;
}
hex_to_str(nv_data_str,nv_data,len_int);
strcpy(response,"SUCCESS:");
strcat(response,nv_data_str);
}
void oem_nv_set_proccess(char *cmd_parameter, char *response)
{
char *sep = NULL;
char offset[MAX_NV_NUMBER_SIZE] = {0};
uint8_t nv_data[MAX_NV_DATA_SIZE + 32] = {0};
char *nv_data_str;
int data_len;
int ret;
int offset_int = 0;
sep = strstr(cmd_parameter, ":");
if (sep == NULL) {
strcpy(response,"ERROR INVALID PARAM");
return;
}
memcpy(offset,cmd_parameter,sep - cmd_parameter);
nv_data_str = cmd_parameter + (sep - cmd_parameter) + 1;
data_len = strlen(nv_data_str) / 2;
ret = char_to_int(offset,&offset_int);
if (ret != 0) {
strcpy(response,"ERROR OFFSET INVALID");
return;
}
if (data_len > MAX_NV_DATA_SIZE) {
strcpy(response,"ERROR NV SIZE TOO LARGE");
return;
}
str_to_hex(nv_data,nv_data_str,data_len);
ret = nv_set(nv_data, offset_int, data_len);
if (ret != 0) {
strcpy(response,"ERROR NV SET FAILED");
return;
}
strcpy(response,"OKAY");
}
#endif

15
drivers/mcu/Kconfig Executable file
View File

@@ -0,0 +1,15 @@
menu "MCU Support"
config DM_MCU
bool "Enable driver model for mcu device support"
depends on DM
help
This adds a simple uclass for mcu device.
config MCU_HC32fX
bool "Enable HC32fX MCU support"
depends on DM_MCU
help
This adds a driver for the HC32fX MCU support.
endmenu

9
drivers/mcu/Makefile Executable file
View File

@@ -0,0 +1,9 @@
#
# Copyright (c) 2015 Google, Inc
# Written by Simon Glass <sjg@chromium.org>
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-$(CONFIG_DM_MCU) += mcu-uclass.o
obj-$(CONFIG_MCU_HC32fX) += mcu_hc32fx.o

65
drivers/mcu/mcu-uclass.c Executable file
View File

@@ -0,0 +1,65 @@
/*
* Copyright (c) 2015 Google, Inc
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <dm.h>
#include <errno.h>
#include <mcu/mcu-uclass.h>
#include <dm/root.h>
#include <dm/uclass-internal.h>
int _mcu_shutdown(struct udevice *dev)
{
struct mcu_ops *ops = dev_get_driver_ops(dev);
if (!ops->shutdown)
return -ENOSYS;
return ops->shutdown(dev);
}
int _mcu_poweron(struct udevice *dev)
{
struct mcu_ops *ops = dev_get_driver_ops(dev);
if (!ops->poweron)
return -ENOSYS;
return ops->poweron(dev);
}
int mcu_poweron(void)
{
struct udevice *mcu;
int ret;
ret = uclass_get_device(UCLASS_MCU, 0, &mcu);
if (ret) {
printf("Get UCLASS_MCU failed, ret=%d\n", ret);
return ret;
}
return _mcu_poweron(mcu);
}
int mcu_shutdown(void)
{
struct udevice *mcu;
int ret;
ret = uclass_get_device(UCLASS_MCU, 0, &mcu);
if (ret) {
printf("Get charge display failed, ret=%d\n", ret);
return ret;
}
return _mcu_shutdown(mcu);
}
UCLASS_DRIVER(mcu) = {
.id = UCLASS_MCU,
.name = "mcu",
};

97
drivers/mcu/mcu_hc32fx.c Executable file
View File

@@ -0,0 +1,97 @@
#include <common.h>
#include <dm.h>
#include <errno.h>
#include <mcu/mcu-uclass.h>
#include <dm/lists.h>
DECLARE_GLOBAL_DATA_PTR;
#define HC32FX_POWEROFF_20 0x20
#define HC32FX_POWERON_30 0x30
#define POWER_OFF 0x55
#define POWER_ON 0x01
struct hc32fx_info {
struct udevice *dev;
};
static u8 hc32fx_read(struct hc32fx_info *hc32fx, u8 reg)
{
u8 val;
int ret;
ret = dm_i2c_read(hc32fx->dev, reg, &val, 1);
if (ret) {
printf("write error to device: %p register: %#x!",
hc32fx->dev, reg);
return ret;
}
return val;
}
static int hc32fx_write(struct hc32fx_info *hc32fx, u8 reg, u8 val)
{
int ret;
ret = dm_i2c_write(hc32fx->dev, reg, &val, 1);
if (ret) {
printf("write error to device: %p register: %#x!",
hc32fx->dev, reg);
return ret;
}
return 0;
}
static int mcu_hc32fx_poweron(struct udevice *dev)
{
struct hc32fx_info *hc32fx = dev_get_priv(dev);
int ret;
ret = hc32fx_write(hc32fx, HC32FX_POWERON_30, POWER_ON);
if(ret)
printf("set mcu POWERON fail\n");
return ret;
}
static int mcu_hc32fx_shutdown(struct udevice *dev)
{
struct hc32fx_info *hc32fx = dev_get_priv(dev);
int ret;
ret = hc32fx_write(hc32fx, HC32FX_POWEROFF_20, POWER_OFF);
if(ret)
printf("set mcu POWEROFF fail\n");
return ret;
}
static int mcu_gpio_probe(struct udevice *dev)
{
struct hc32fx_info *priv = dev_get_priv(dev);
priv->dev = dev;
return 0;
}
static const struct mcu_ops mcu_hc32fx_ops = {
.poweron = mcu_hc32fx_poweron,
.shutdown = mcu_hc32fx_shutdown,
};
static const struct udevice_id hc32fx_ops_ids[] = {
{ .compatible = "mcu_hc32fx" },
{ }
};
U_BOOT_DRIVER(mcu_gpio) = {
.name = "hc32fx-mcu",
.id = UCLASS_MCU,
.of_match = hc32fx_ops_ids,
.ops = &mcu_hc32fx_ops,
.priv_auto_alloc_size = sizeof(struct hc32fx_info),
.probe = mcu_gpio_probe,
};

6
drivers/misc/Kconfig
View File

@@ -439,4 +439,10 @@ config K3_AVS0
optimized voltage from the efuse, so that it can be programmed
to the PMIC on board.
config LIGHT_AON_CONF
bool "Light aon config support"
depends on MISC
help
Select this to enable aon config by dts.
endmenu

1
drivers/misc/Makefile
View File

@@ -68,3 +68,4 @@ obj-$(CONFIG_WINBOND_W83627) += winbond_w83627.o
obj-$(CONFIG_JZ4780_EFUSE) += jz4780_efuse.o
obj-$(CONFIG_MICROCHIP_FLEXCOM) += microchip_flexcom.o
obj-$(CONFIG_K3_AVS0) += k3_avs.o
obj-$(CONFIG_LIGHT_AON_CONF) += light_regu.o

1161
drivers/misc/light_regu.c Normal file
View File

File diff suppressed because it is too large Load Diff

271
drivers/misc/light_regu.h Normal file
View File

@@ -0,0 +1,271 @@
#ifndef __LIGHT_REGU_H__
#define __LIGHT_REGU_H__
typedef enum
{
SOC_DVDD18_AON, /*da9063: ldo-3 */
SOC_AVDD33_USB3, /*da9063: ldo-9 */
SOC_DVDD08_AON, /*da9063: ldo-2 */
SOC_APCPU_DVDD_DVDDM, /*da9063: vbcore1 & vbcore2*/
SOC_DVDD08_DDR, /*da9063: buckperi */
SOC_VDD_DDR_1V8, /*da9063: ldo-4 */
SOC_VDD_DDR_1V1, /*da9063: buckmem & buckio */
SOC_VDD_DDR_0V6, /*da9063: buckpro */
SOC_DVDD18_AP, /*da9063: ldo-11 */
SOC_DVDD08_AP, /*da9121: da9121_ex */
SOC_AVDD08_MIPI_HDMI, /*da9063: ldo-1 */
SOC_AVDD18_MIPI_HDMI, /*da9063: ldo-5 */
SOC_DVDD33_EMMC, /*da9063: ldo-10 */
SOC_DVDD18_EMMC, /*slg51000:ldo-3 */
SOC_DOVDD18_SCAN, /*da9063: ldo-6 */
SOC_VEXT_2V8, /*da9063: ldo-7 */
SOC_DVDD12_SCAN, /*da9063: ldo-8 */
SOC_AVDD28_SCAN_EN, /*da9063: gpio-4,SGM2019-ADJ */
SOC_AVDD28_RGB, /*slg51000:ldo-1 */
SOC_DOVDD18_RGB, /*slg51000:ldo-4 */
SOC_DVDD12_RGB, /*slg51000:ldo-5 */
SOC_AVDD25_IR, /*slg51000:ldo-2 */
SOC_DOVDD18_IR, /*slg51000:ldo-7 */
SOC_DVDD12_IR, /*slg51000:ldo-6 */
SOC_ADC_VREF,
SOC_LCD0_EN,
SOC_VEXT_1V8,
SOC_REGU_INVALID = 0xFF
} soc_virtual_id_en;
#define REGU_DTS_NAME "light-regu-reg"
#define AON_CONF_NAME "aon_pmic_config"
#define PMIC_DEV_DTS_NAME "pmic-dev"
#define PMIC_PARENT_CTRL_NAME "pmic_ctrl_info"
#define REGU_ID_CONF_NAME "regu_config"
#define REGU_ID_NAME "regu_id"
#define COUPLING_ID_INFO_NAME "coupling_info"
#define PMIC_DEV_ENABLE_WDT (1U << 0)
#define PMIC_DEV_ENABLE_ERR_IO (1U << 1)
#define PMIC_DEV_ENABLE_LPM_IO (1U << 2)
#define HW_ID_NO_SOFT_AUTO_ON (0xff)
#define HW_ID_NO_SOFT_AUTO_OFF (0xff)
#define HW_ID_INVALID (0xff)
#define PMIC_ID_INVALID (0xff)
#define REGU_SUB_ID_INVALID (0xff)
#define REGU_EXT_ID_NAME_LEN 30
#define PMIC_DEV_NAME_LEN 20
#define PMIC_DEV_VERSION_LEN 20
#define PMIC_MAX_HW_ID_NUM 3
#define PMIC_MAX_COUPLING_NUM 3
#define AON_WAKEUP_BY_GPIO (1 << 0)
#define AON_WAKEUP_BY_RTC (1 << 1)
#define AON_CONFIG_MAGIC "AON_CONFIG"
#define UBOOT_CONFIG_MAGIC "UBOOT_SET"
#define AON_CONFIG_VERSION "1.0.0"
typedef enum
{
HW_ID_ACTIVATE_HIGH = 0U,
HW_ID_ACTIVATE_LOW = 1U,
} hw_activate_status_en;
typedef struct __packed
{
uint8_t pmic_id;
uint8_t io_hw_id;
uint8_t activate_status;
} pmic_parent_hw_io_ctrl_info_t;
typedef struct __packed
{
uint8_t on_order;
uint8_t on_delay_ms;
uint32_t init_target_uv;
} regu_soft_power_ctrl_on_t;
typedef struct __packed
{
uint8_t off_order;
uint8_t off_delay_ms;
} regu_soft_power_ctrl_off_t;
typedef struct __packed
{
regu_soft_power_ctrl_on_t on_info;
regu_soft_power_ctrl_off_t off_info;
} regu_soft_power_ctrl_t;
typedef struct __packed
{
uint8_t id0;
uint8_t id1;
int8_t max_spread; // mv/10
int8_t min_spread; // mv/10
} coupling_desc_t;
typedef enum
{
GPIO_IRQ_MODE_RISING_EDGE = 0, ///< Interrupt mode for rising edge
GPIO_IRQ_MODE_FALLING_EDGE, ///< Interrupt mode for falling edge
GPIO_IRQ_MODE_BOTH_EDGE, ///< Interrupt mode for both edge
GPIO_IRQ_MODE_LOW_LEVEL, ///< Interrupt mode for low level
GPIO_IRQ_MODE_HIGH_LEVEL, ///< Interrupt mode for high level
} csi_gpio_irq_mode_t;
typedef enum
{
IIC_ADDRESS_7BIT = 0U, ///< 7-bit address mode
IIC_ADDRESS_10BIT ///< 10-bit address mode
} csi_iic_addr_mode_t;
typedef enum
{
IIC_BUS_SPEED_STANDARD = 0U, ///< Standard Speed (<=100kHz)
IIC_BUS_SPEED_FAST, ///< Fast Speed (<=400kHz)
IIC_BUS_SPEED_FAST_PLUS, ///< Fast plus Speed (<= 1MHz)
IIC_BUS_SPEED_HIGH ///< High Speed (<=3.4MHz)
} csi_iic_speed_t;
typedef struct __packed
{
uint8_t pmic_id;
uint8_t hw_id;
uint8_t benable;
pmic_parent_hw_io_ctrl_info_t parent_hw_info;
regu_soft_power_ctrl_t soft_power_ctrl_info;
} pmic_hw_info_t;
typedef struct __packed
{
coupling_desc_t coupling_list[PMIC_MAX_COUPLING_NUM];
pmic_hw_info_t id[PMIC_MAX_HW_ID_NUM]; ///< sub id1 for single-rail or first src of dual-rail
} pmic_hw_id_t;
typedef struct __packed
{
uint8_t regu_ext_id; ///< virtual global regulator id
char regu_ext_id_name[REGU_EXT_ID_NAME_LEN]; ///< vitual regu-id name
pmic_hw_id_t sub; ///< sub id set for dual-rail/single-rail regulator
} csi_regu_id_t;
typedef enum
{
PMIC_CTRL_BY_AON_GPIO = 0U,
PMIC_CTRL_BY_PMIC_GPIO = 1U,
PMIC_CTRL_BY_NOTHINTG = 0xFF,
} pmic_ctrl_info_en;
typedef struct __packed
{
uint8_t gpio_port;
uint8_t pin;
uint8_t activate_status;
} pmic_ctrl_by_aon_info_t;
typedef struct __packed
{
uint8_t pmic_id;
uint8_t io_hw_id;
uint8_t activate_status;
} pmic_ctrl_by_pmic_info_t;
typedef struct __packed
{
uint8_t pmic_ctrl_type;
union
{
pmic_ctrl_by_aon_info_t aon_io;
pmic_ctrl_by_pmic_info_t pmic_io;
} info;
} pmic_parent_ctrl_info_t;
typedef struct __packed
{
uint8_t gpio_port;
uint8_t pin;
uint8_t trigger_mode;
} pmic_interrupt_io_info_t;
typedef struct __packed
{
char device_name[PMIC_DEV_NAME_LEN];
char version_name[PMIC_DEV_VERSION_LEN];
uint8_t pmic_id;
uint8_t addr1;
uint8_t addr2;
uint8_t flag; /*support wdt|errio| lpm io*/
uint8_t slew_rate;
uint32_t wdt_len;
pmic_interrupt_io_info_t err_io_info;
pmic_interrupt_io_info_t lpm_io_info;
pmic_parent_ctrl_info_t ctrl_info;
} pmic_dev_info_t;
typedef struct
{
soc_virtual_id_en id;
char virtual_id_name[REGU_EXT_ID_NAME_LEN];
int min_uv;
int max_uv;
} soc_virtual_id_t;
typedef struct
{
int regu_num;
soc_virtual_id_t *regu_list;
} virtual_regu_list_t;
typedef struct
{
int pmic_num;
pmic_dev_info_t *pmic_list;
} pmic_dev_list_t;
typedef struct
{
int regu_id_num;
csi_regu_id_t *regu_id_list;
} regu_id_list_t;
typedef struct __packed
{
uint8_t iic_id; ///< iic id
uint8_t addr_mode; ///< iic addr_mode ---> csi_iic_addr_mode_t
uint8_t speed; ///< iic speed type ---> csi_iic_speed_t
uint8_t reserved[1];
} csi_pmic_if_config_t;
struct mic_regu_platdata
{
const char *name;
uint32_t wakeup_flag;
csi_pmic_if_config_t iic_config;
virtual_regu_list_t regu_list;
pmic_dev_list_t pmic_list;
regu_id_list_t regu_id_list;
};
typedef struct __packed
{
csi_pmic_if_config_t iic_config;
uint8_t pmic_dev_num;
uint8_t regu_num;
uint32_t pmic_dev_list_offset;
uint32_t regu_id_list_offset;
} aon_pmic_config_t;
typedef struct __packed
{
const char magic[11];
const char version[11];
const char uboot_set_magic[11];
uint8_t max_hw_id_num;
uint64_t aon_config_partition_size;
uint32_t wakeup_flag;
aon_pmic_config_t aon_pmic;
} aon_config_t;
#endif

1
drivers/misc/misc-uclass.c
View File

@@ -13,7 +13,6 @@
* general classes. A set of generic read, write and ioctl methods may
* be used to access the device.
*/
int misc_read(struct udevice *dev, int offset, void *buf, int size)
{
const struct misc_ops *ops = device_get_ops(dev);

4
drivers/mmc/sdhci.c
View File

@@ -38,9 +38,7 @@ static void sdhci_reset(struct sdhci_host *host, u8 mask)
timeout--;
udelay(1000);
}
#ifdef CONFIG_TARGET_LIGHT_C910
mdelay(50);
#endif
}
static void sdhci_cmd_done(struct sdhci_host *host, struct mmc_cmd *cmd)

19
drivers/power/Kconfig
View File

@@ -2,10 +2,22 @@ menu "Power"
source "drivers/power/domain/Kconfig"
source "drivers/power/fuel_gauge/Kconfig"
source "drivers/power/pmic/Kconfig"
source "drivers/power/regulator/Kconfig"
source "drivers/power/charge/Kconfig"
source "drivers/power/power_delivery/Kconfig"
config DM_CHARGE_DISPLAY
bool "Enable driver model for charge display support"
depends on DM
help
This adds a simple uclass for charge display.
choice
prompt "Select Sunxi PMIC Variant"
depends on ARCH_SUNXI
@@ -72,6 +84,13 @@ config SY8106A_POWER
endchoice
config CHARGE_ANIMATION
bool "Enable charge animation"
depends on DM_CHARGE_DISPLAY && DM_FUEL_GAUGE
select ARM_CPU_SUSPEND
help
This adds a simple function for charge animation display.
config AXP_DCDC1_VOLT
int "axp pmic dcdc1 voltage"
depends on AXP221_POWER || AXP809_POWER || AXP818_POWER

2
drivers/power/Makefile
View File

@@ -3,11 +3,13 @@
# Copyright (c) 2009 Wind River Systems, Inc.
# Tom Rix <Tom.Rix at windriver.com>
obj-$(CONFIG_DM_CHARGE_DISPLAY) += charge-display-uclass.o
obj-$(CONFIG_AXP152_POWER) += axp152.o
obj-$(CONFIG_AXP209_POWER) += axp209.o
obj-$(CONFIG_AXP221_POWER) += axp221.o
obj-$(CONFIG_AXP809_POWER) += axp809.o
obj-$(CONFIG_AXP818_POWER) += axp818.o
obj-$(CONFIG_CHARGE_ANIMATION) += charge_animation.o
obj-$(CONFIG_EXYNOS_TMU) += exynos-tmu.o
obj-$(CONFIG_FTPMU010_POWER) += ftpmu010.o
obj-$(CONFIG_SY8106A_POWER) += sy8106a.o

40
drivers/power/charge-display-uclass.c Executable file
View File

@@ -0,0 +1,40 @@
/*
* (C) Copyright 2017 Rockchip Electronics Co., Ltd
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <command.h>
#include <common.h>
#include <dm.h>
#include <power/charge_display.h>
int charge_display_show(struct udevice *dev)
{
const struct dm_charge_display_ops *ops = dev_get_driver_ops(dev);
if (!ops || !ops->show)
return -ENOSYS;
return ops->show(dev);
}
int charge_display(void)
{
struct udevice *dev;
struct udevice *fg_dev;
int ret;
ret = uclass_get_device(UCLASS_CHARGE_DISPLAY, 0, &dev);
if (ret) {
debug("Get charge display failed, ret=%d\n", ret);
return ret;
}
return charge_display_show(dev);
}
UCLASS_DRIVER(charge_display) = {
.id = UCLASS_CHARGE_DISPLAY,
.name = "charge_display",
};

5
drivers/power/charge/Kconfig Executable file
View File

@@ -0,0 +1,5 @@
config CHARGER_BQ25700
bool "BQ25700 charger support"
depends on DM_FUEL_GAUGE
help
This adds support for BQ25700 charger support.

7
drivers/power/charge/Makefile Executable file
View File

@@ -0,0 +1,7 @@
#
# Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-$(CONFIG_CHARGER_BQ25700) += bq25700_charger.o

334
drivers/power/charge/bq25700_charger.c Executable file
View File

@@ -0,0 +1,334 @@
/*
* (C) Copyright 2019 Fuzhou Rockchip Electronics Co., Ltd
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/gpio.h>
#include <dm/device.h>
#include <dm/uclass.h>
#include <power/fuel_gauge.h>
#include <power/pmic.h>
#include <power/power_delivery/power_delivery.h>
DECLARE_GLOBAL_DATA_PTR;
#define BQ25700_ID 0x25700
#define BQ25703_ID 0x25703
#define COMPAT_BQ25700 "ti,bq25700"
#define COMPAT_BQ25703 "ti,bq25703"
#define BQ25700_I2C_SPEED 100000
#define BQ25700_CHARGE_CURRENT_1500MA 0x5C0
#define BQ25700_SDP_INPUT_CURRENT_500MA 0xA00
#define BQ25700_DCP_INPUT_CURRENT_1500MA 0x1E00
#define BQ25700_DCP_INPUT_CURRENT_2000MA 0x2800
#define BQ25700_DCP_INPUT_CURRENT_3000MA 0x3C00
#define WATCHDOG_ENSABLE (0x03 << 13)
#define BQ25700_CHARGEOPTION0_REG 0x12
#define BQ25700_CHARGECURREN_REG 0x14
#define BQ25700_CHARGERSTAUS_REG 0x20
#define BQ25700_INPUTVOLTAGE_REG 0x3D
#define BQ25700_INPUTCURREN_REG 0x3F
#define BQ25703_CHARGEOPTION0_REG 0x00
#define BQ25703_CHARGECURREN_REG 0x02
#define BQ25703_CHARGERSTAUS_REG 0x20
#define BQ25703_INPUTVOLTAGE_REG 0x0A
#define BQ25703_INPUTCURREN_REG 0x0E
#define PD_MUN 2
#define TYPEC0_I2C "i2c@ffe7f20000"
#define TYPEC1_I2C "i2c@ffe7f24000"
enum bq25700_table_ids {
/* range tables */
TBL_ICHG,
TBL_CHGMAX,
TBL_INPUTVOL,
TBL_INPUTCUR,
TBL_SYSVMIN,
TBL_OTGVOL,
TBL_OTGCUR,
TBL_EXTCON,
};
struct bq25700 {
struct udevice *dev;
u32 ichg;
u32 chip_id;
struct udevice *pd[PD_MUN];
};
struct bq25700_range {
u32 min;
u32 max;
u32 step;
};
static int bq25700_read(struct bq25700 *charger, uint reg)
{
u16 val;
int ret;
ret = dm_i2c_read(charger->dev, reg, (u8 *)&val, 2);
if (ret) {
printf("write error to device: %p register: %#x!",
charger->dev, reg);
return ret;
}
return val;
}
static int bq25700_write(struct bq25700 *charger, uint reg, u16 val)
{
int ret;
ret = dm_i2c_write(charger->dev, reg, (u8 *)&val, 2);
if (ret) {
printf("write error to device: %p register: %#x!",
charger->dev, reg);
return ret;
}
return 0;
}
static const union {
struct bq25700_range rt;
} bq25700_tables[] = {
/* range tables */
[TBL_ICHG] = {.rt = {0, 8128000, 64000}},
/* uV */
[TBL_CHGMAX] = {.rt = {0, 19200000, 16000}},
/* uV max charge voltage*/
[TBL_INPUTVOL] = {.rt = {3200000, 19520000, 64000}},
/* uV input charge voltage*/
[TBL_INPUTCUR] = {.rt = {0, 6350000, 50000}},
/*uA input current*/
[TBL_SYSVMIN] = {.rt = {1024000, 16182000, 256000}},
/* uV min system voltage*/
[TBL_OTGVOL] = {.rt = {4480000, 20800000, 64000}},
/*uV OTG volage*/
[TBL_OTGCUR] = {.rt = {0, 6350000, 50000}},
};
static u32 bq25700_find_idx(u32 value, enum bq25700_table_ids id)
{
const struct bq25700_range *rtbl = &bq25700_tables[id].rt;
u32 rtbl_size;
u32 idx;
rtbl_size = (rtbl->max - rtbl->min) / rtbl->step + 1;
for (idx = 1;
idx < rtbl_size && (idx * rtbl->step + rtbl->min <= value);
idx++)
;
return idx - 1;
}
static bool bq25700_charger_status(struct bq25700 *charger)
{
int state_of_charger;
u16 value;
value = bq25700_read(charger, BQ25700_CHARGERSTAUS_REG);
state_of_charger = value >> 15;
return state_of_charger;
}
static bool bq25703_charger_status(struct bq25700 *charger)
{
int state_of_charger;
u16 value;
value = bq25700_read(charger, BQ25703_CHARGERSTAUS_REG);
state_of_charger = value >> 15;
return state_of_charger;
}
static bool bq257xx_charger_status(struct udevice *dev)
{
struct bq25700 *charger = dev_get_priv(dev);
if (charger->chip_id == BQ25700_ID)
return bq25700_charger_status(charger);
else
return bq25703_charger_status(charger);
}
static int bq25700_charger_capability(struct udevice *dev)
{
return FG_CAP_CHARGER;
}
static int bq25700_get_usb_type(void)
{
#ifdef CONFIG_PHY_ROCKCHIP_INNO_USB2
return rockchip_chg_get_type();
#else
return 0;
#endif
}
static int bq25700_get_pd_output_val(struct bq25700 *charger,
int *vol, int *cur)
{
struct power_delivery_data pd_data;
int ret;
if (!charger->pd[0] && !charger->pd[1]) {
return -EINVAL;
}
memset(&pd_data, 0, sizeof(pd_data));
int i = 0;
for (i = 0; i < PD_MUN; i++) {
if (!charger->pd[i]) {
continue;
}
ret = power_delivery_get_data(charger->pd[i], &pd_data);
if (ret) {
continue;
}
if (!pd_data.online || !pd_data.voltage || !pd_data.current) {
continue;
}
*vol = pd_data.voltage;
*cur = pd_data.current;
printf("voltage is %d current is %d\n", *vol, *cur);
goto end;
}
return -EINVAL;
end:
return 0;
}
static void bq25703_charger_current_init(struct bq25700 *charger)
{
u16 charge_current = BQ25700_CHARGE_CURRENT_1500MA;
u16 sdp_inputcurrent = BQ25700_SDP_INPUT_CURRENT_500MA;
u16 dcp_inputcurrent = BQ25700_DCP_INPUT_CURRENT_1500MA;
int pd_inputvol, pd_inputcurrent;
u16 vol_idx = 0, cur_idx;
u16 temp;
temp = bq25700_read(charger, BQ25703_CHARGEOPTION0_REG);
temp &= (~WATCHDOG_ENSABLE);
bq25700_write(charger, BQ25703_CHARGEOPTION0_REG, temp);
if (!bq25700_get_pd_output_val(charger, &pd_inputvol,
&pd_inputcurrent)) {
if (pd_inputvol > 5000000) {
vol_idx = bq25700_find_idx(pd_inputvol - 1280000 - 3200000,
TBL_INPUTVOL);
vol_idx = vol_idx << 6;
}
cur_idx = bq25700_find_idx(pd_inputcurrent,
TBL_INPUTCUR);
cur_idx = cur_idx << 8;
if (pd_inputcurrent != 0)
{
bq25700_write(charger, BQ25703_INPUTCURREN_REG,
cur_idx);
if (vol_idx)
bq25700_write(charger, BQ25703_INPUTVOLTAGE_REG,
vol_idx);
charge_current = bq25700_find_idx(pd_inputcurrent,
TBL_ICHG);
charge_current = charge_current << 6;
}
} else {
bq25700_write(charger, BQ25703_INPUTCURREN_REG,
dcp_inputcurrent);
}
if (bq25703_charger_status(charger)) {
bq25700_write(charger, BQ25703_CHARGECURREN_REG,
charge_current);
}
}
static int bq25700_ofdata_to_platdata(struct udevice *dev)
{
struct bq25700 *charger = dev_get_priv(dev);
const void *blob = gd->fdt_blob;
int node, node1;
charger->dev = dev;
node = fdt_node_offset_by_compatible(blob, 0, COMPAT_BQ25700);
node1 = fdt_node_offset_by_compatible(blob, 0, COMPAT_BQ25703);
if ((node < 0) && (node1 < 0)) {
printf("Can't find dts node for charger bq25700\n");
return -ENODEV;
}
if (node < 0) {
node = node1;
charger->chip_id = BQ25703_ID;
} else {
charger->chip_id = BQ25700_ID;
}
return 0;
}
static int bq25700_probe(struct udevice *dev)
{
struct bq25700 *charger = dev_get_priv(dev);
int ret;
struct udevice *pd_tmp;
struct udevice *dev_tmp;
for (uclass_first_device(UCLASS_PD, &pd_tmp);
pd_tmp;
uclass_next_device(&pd_tmp))
{
dev_tmp = dev_get_parent(pd_tmp);
if (!strncmp(TYPEC0_I2C, dev_tmp->name, strlen(TYPEC0_I2C))) { // Ensure that typec0 has the highest priority
charger->pd[0] = pd_tmp;
} else if (!strncmp(TYPEC1_I2C, dev_tmp->name, strlen(TYPEC1_I2C))) {
charger->pd[1] = pd_tmp;
}
}
if (charger->chip_id == BQ25703_ID) {
bq25703_charger_current_init(charger);
}
return 0;
}
static const struct udevice_id charger_ids[] = {
{.compatible = "ti,bq25700"},
{.compatible = "ti,bq25703"},
{},
{ },
};
static struct dm_fuel_gauge_ops charger_ops = {
.get_chrg_online = bq257xx_charger_status,
.capability = bq25700_charger_capability,
};
U_BOOT_DRIVER(bq25700_charger) = {
.name = "bq25700_charger",
.id = UCLASS_FG,
.probe = bq25700_probe,
.of_match = charger_ids,
.ops = &charger_ops,
.ofdata_to_platdata = bq25700_ofdata_to_platdata,
.priv_auto_alloc_size = sizeof(struct bq25700),
};

366
drivers/power/charge_animation.c Executable file
View File

@@ -0,0 +1,366 @@
/*
* (C) Copyright 2017 Rockchip Electronics Co., Ltd
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <asm/io.h>
#include <asm/gpio.h>
#include <common.h>
#include <console.h>
#include <dm.h>
#include <errno.h>
#include <led.h>
#include <rtc.h>
#include <pwm.h>
#include <power/charge_display.h>
#include <power/charge_animation.h>
#include <power/fuel_gauge.h>
#include <power/pmic.h>
#include <mcu/mcu-uclass.h>
#ifdef CONFIG_IRQ
#include <irq-generic.h>
#include <rk_timer_irq.h>
#endif
DECLARE_GLOBAL_DATA_PTR;
#define IMAGE_RECALC_IDX -1
#define IMAGE_SOC_100_IDX(n) ((n) - 2)
#define IMAGE_LOWPOWER_IDX(n) ((n) - 1)
#define SYSTEM_SUSPEND_DELAY_MS 5000
#define FUEL_GAUGE_POLL_MS 1000
#define LED_CHARGING_NAME "battery_charging"
#define LED_CHARGING_FULL_NAME "battery_full"
#define LED_CHARGING_START_NAME "battery_start"
struct charge_image {
const char *name;
int soc;
int period; /* ms */
};
struct charge_animation_priv {
struct udevice *fg;
struct udevice *charger;
struct udevice *mcu;
#ifdef CONFIG_LED
struct udevice *led_charging;
struct udevice *led_full;
struct udevice *led_start;
#endif
const struct charge_image *image;
int image_num;
int auto_wakeup_key_state;
ulong auto_screen_off_timeout; /* ms */
ulong suspend_delay_timeout; /* ms */
};
struct gpio_desc powerkey_gpio;
static int leds_switch = 0;
#ifdef CONFIG_LED
static int leds_update(struct udevice *dev, int soc)
{
struct charge_animation_priv *priv = dev_get_priv(dev);
static int old_soc = -1;
int ret, ledst;
if (old_soc == soc)
return 0;
old_soc = soc;
if (priv->led_charging) {
ledst = (soc < 100) ? LEDST_ON : LEDST_OFF;
ret = led_set_state(priv->led_charging, ledst);
if (ret) {
printf("set charging led %s failed, ret=%d\n",
(ledst == LEDST_ON) ? "ON" : "OFF", ret);
return ret;
}
}
if (priv->led_full) {
ledst = (soc == 100) ? LEDST_ON : LEDST_OFF;
ret = led_set_state(priv->led_full, ledst);
if (ret) {
printf("set charging full led %s failed, ret=%d\n",
ledst == LEDST_ON ? "ON" : "OFF", ret);
return ret;
}
}
return 0;
}
static int leds_charge_on(struct udevice *dev, int soc)
{
struct charge_animation_priv *priv = dev_get_priv(dev);
int ret, ledst;
ledst = LEDST_ON;
ret = led_set_state(priv->led_full, ledst);
if (ret) {
printf("set charging full led %s failed, ret=%d\n",
ledst == LEDST_ON ? "ON" : "OFF", ret);
return ret;
}
return 0;
}
static int leds_charge_off(struct udevice *dev, int soc)
{
struct charge_animation_priv *priv = dev_get_priv(dev);
int ret, ledst;
ledst = LEDST_OFF;
ret = led_set_state(priv->led_charging, ledst);
if (ret) {
printf("set charging full led %s failed, ret=%d\n",
ledst == LEDST_ON ? "ON" : "OFF", ret);
return ret;
}
ret = led_set_state(priv->led_full, ledst);
if (ret) {
printf("set charging full led %s failed, ret=%d\n",
ledst == LEDST_ON ? "ON" : "OFF", ret);
return ret;
}
return 0;
}
static int leds_charge_update(struct udevice *dev, int soc)
{
struct charge_animation_priv *priv = dev_get_priv(dev);
int ret, ledst;
if (leds_switch > 5){
leds_charge_on(dev, soc);
} else {
leds_charge_off(dev, soc);
}
leds_switch++;
if (leds_switch > 10)
leds_switch = 0;
return 0;
}
#else
static int leds_update(struct udevice *dev, int soc) { return 0; }
static int leds_charge_on(struct udevice *dev, int soc) { return 0; }
static int leds_charge_off(struct udevice *dev, int soc) { return 0; }
static int leds_charge_update(struct udevice *dev, int soc) { return 0; }
#endif
static int charge_animation_ofdata_to_platdata(struct udevice *dev)
{
struct charge_animation_pdata *pdata = dev_get_platdata(dev);
pdata->low_power_voltage =
dev_read_u32_default(dev, "uboot-low-power-voltage", 0);
return 0;
}
static int fg_charger_get_chrg_online(struct udevice *dev)
{
struct charge_animation_priv *priv = dev_get_priv(dev);
struct udevice *charger;
charger = priv->charger ? : priv->fg;
return fuel_gauge_get_chrg_online(charger);
}
static int get_reboot_state(void){
const char *var_name = "battery_charge";
char *value = env_get(var_name);
if (value)
if (strcmp(value, "0") == 0) {
env_set(var_name, "1");
env_save();
return 0;
}
env_set(var_name, "1");
env_save();
return 1;
}
static int charge_animation_show(struct udevice *dev)
{
int soc, voltage, ret, charging = 0;
struct charge_animation_priv *priv = dev_get_priv(dev);
struct charge_animation_pdata *pdata = dev_get_platdata(dev);
struct udevice *fg = priv->fg;
struct udevice *mcu = priv->mcu;
voltage = fuel_gauge_get_voltage(fg);
if (voltage < 0)
return -EINVAL;
while (voltage < pdata->low_power_voltage + 50) {
soc = fuel_gauge_update_get_soc(fg);
if (soc < 0 || soc > 100) {
printf("get soc failed: %d\n", soc);
continue;
} else if (soc >= 1) {
printf("soc is: %d\n", soc);
break;
}
voltage = fuel_gauge_get_voltage(fg);
if (voltage < 0) {
printf("get voltage failed: %d\n", voltage);
continue;
}
ret = leds_update(dev, soc);
if (ret)
printf("update led failed: %d\n", ret);
printf("soc is: %d voltage is :%d\n", soc, voltage);
charging = fg_charger_get_chrg_online(dev);
if (charging <= 0) {
mcu_shutdown(); // shutdown system power
}
mdelay(100);
};
leds_charge_off(dev, soc);
ret = get_reboot_state();
charging = fg_charger_get_chrg_online(dev);
if (!(charging <= 0) && ret != 0)
while(1){
ret = dm_gpio_get_value(&powerkey_gpio);
if (ret == 0){
break;
}
charging = fg_charger_get_chrg_online(dev);
if (charging <= 0) {
mcu_shutdown(); // shutdown system power
}
soc = fuel_gauge_update_get_soc(fg);
if (soc == 100){
leds_charge_on(dev, soc);
}else if (soc < 100){
leds_charge_update(dev, soc);
}
mdelay(300);
}
leds_charge_off(dev, soc);
ret = led_set_state(priv->led_start, LEDST_ON);
if (!ret)
printf("Found Charging-Start LED\n");
return 0;
}
static int fg_charger_get_device(struct udevice **fuel_gauge,
struct udevice **charger)
{
struct udevice *dev;
struct uclass *uc;
int ret, cap;
*fuel_gauge = NULL,
*charger = NULL;
ret = uclass_get(UCLASS_FG, &uc);
if (ret)
return ret;
for (uclass_first_device(UCLASS_FG, &dev);
dev;
uclass_next_device(&dev)) {
cap = fuel_gauge_capability(dev);
if (cap == (FG_CAP_CHARGER | FG_CAP_FUEL_GAUGE)) {
*fuel_gauge = dev;
*charger = NULL;
} else if (cap == FG_CAP_FUEL_GAUGE) {
*fuel_gauge = dev;
} else if (cap == FG_CAP_CHARGER) {
*charger = dev;
}
}
return (*fuel_gauge) ? 0 : -ENODEV;
}
static const struct dm_charge_display_ops charge_animation_ops = {
.show = charge_animation_show,
};
static int charge_animation_probe(struct udevice *dev)
{
struct charge_animation_priv *priv = dev_get_priv(dev);
int ret, soc;
/* Get PMIC: used for power off system */
ret = uclass_get_device(UCLASS_MCU, 0, &priv->mcu);
if (ret) {
if (ret == -ENODEV)
printf("Can't find MCU\n");
else
printf("Get UCLASS MCU failed: %d\n", ret);
}
/* Get fuel gauge and charger(If need) */
ret = fg_charger_get_device(&priv->fg, &priv->charger);
if (ret) {
if (ret == -ENODEV)
debug("Can't find FG\n");
else
debug("Get UCLASS FG failed: %d\n", ret);
// return ret;
}
#ifdef CONFIG_LED
ret = led_get_by_label(LED_CHARGING_NAME, &priv->led_charging);
if (!ret)
printf("Found Charging LED \n");
ret = led_get_by_label(LED_CHARGING_FULL_NAME, &priv->led_full);
if (!ret)
printf("Found Charging-Full LED\n");
ret = led_get_by_label(LED_CHARGING_START_NAME, &priv->led_start);
if (!ret)
printf("Found Charging-Start LED\n");
#endif
ret = gpio_request_by_name(dev, "powerkey-gpio", 0, &powerkey_gpio, 0);
if (dm_gpio_is_valid(&powerkey_gpio)) {
dm_gpio_set_dir_flags(&powerkey_gpio, GPIOD_IS_IN);
}
printf("Enable charge animation display\n");
return 0;
}
static const struct udevice_id charge_animation_ids[] = {
{ .compatible = "rockchip,uboot-charge" },
{ },
};
U_BOOT_DRIVER(charge_animation) = {
.name = "charge-animation",
.id = UCLASS_CHARGE_DISPLAY,
.probe = charge_animation_probe,
.of_match = charge_animation_ids,
.ops = &charge_animation_ops,
.ofdata_to_platdata = charge_animation_ofdata_to_platdata,
.platdata_auto_alloc_size = sizeof(struct charge_animation_pdata),
.priv_auto_alloc_size = sizeof(struct charge_animation_priv),
};

11
drivers/power/fuel_gauge/Kconfig Executable file
View File

@@ -0,0 +1,11 @@
config DM_FUEL_GAUGE
bool "Enable driver model fuel gauge support"
depends on DM
help
This adds a simple uclass for fuel gauge.
config POWER_FG_CW201X
bool "CW201X Fuel gauge support"
depends on DM_FUEL_GAUGE
help
This adds support for CW201X fuel gauge support.

3
drivers/power/fuel_gauge/Makefile
View File

@@ -2,5 +2,6 @@
#
# Copyright (C) 2012 Samsung Electronics
# Lukasz Majewski <l.majewski@samsung.com>
obj-$(CONFIG_$(SPL_)DM_FUEL_GAUGE) += fuel_gauge_uclass.o
obj-$(CONFIG_POWER_FG_MAX17042) += fg_max17042.o
obj-$(CONFIG_POWER_FG_CW201X) += fg_cw201x.o

415
drivers/power/fuel_gauge/fg_cw201x.c Executable file
View File

@@ -0,0 +1,415 @@
/*
* (C) Copyright 2008-2015 Fuzhou Rockchip Electronics Co., Ltd
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/gpio.h>
#include <dm.h>
#include <dm/device.h>
#include <errno.h>
#include <fdtdec.h>
#include <i2c.h>
// #include <linux/usb/phy-rockchip-usb2.h>
#include <malloc.h>
#include <power/battery.h>
#include <power/fuel_gauge.h>
// #include <power/pmic.h>
#include "fg_regs.h"
DECLARE_GLOBAL_DATA_PTR;
#define COMPAT_ROCKCHIP_CW201X "cw201x"
#define REG_VERSION 0x0
#define REG_VCELL 0x2
#define REG_SOC 0x4
#define REG_RRT_ALERT 0x6
#define REG_CONFIG 0x8
#define REG_MODE 0xA
#define REG_BATINFO 0x10
#define MODE_SLEEP_MASK (0x3 << 6)
#define MODE_SLEEP (0x3 << 6)
#define MODE_NORMAL (0x0 << 6)
#define MODE_QUICK_START (0x3 << 4)
#define MODE_RESTART (0xf << 0)
#define CONFIG_UPDATE_FLG (0x1 << 1)
#define ATHD (0x0 << 3)
enum charger_type {
CHARGER_TYPE_NO = 0,
CHARGER_TYPE_USB,
CHARGER_TYPE_AC,
CHARGER_TYPE_DC,
CHARGER_TYPE_UNDEF,
};
struct cw201x_info {
struct udevice *dev;
int capacity;
u32 *cw_bat_config_info;
int divider_res1;
int divider_res2;
int hw_id_check;
struct gpio_desc hw_id0;
struct gpio_desc hw_id1;
int support_dc_adp;
struct gpio_desc dc_det_gpio;
int dc_det_flag;
bool dual_cell;
};
static u8 cw201x_read(struct cw201x_info *cw201x, u8 reg)
{
u8 val;
int ret;
ret = dm_i2c_read(cw201x->dev, reg, &val, 1);
if (ret) {
printf("write error to device: %p register: %#x!",
cw201x->dev, reg);
return ret;
}
return val;
}
static int cw201x_write(struct cw201x_info *cw201x, u8 reg, u8 val)
{
int ret;
ret = dm_i2c_write(cw201x->dev, reg, &val, 1);
if (ret) {
printf("write error to device: %p register: %#x!",
cw201x->dev, reg);
return ret;
}
return 0;
}
static u16 cw201x_read_half_word(struct cw201x_info *cw201x, int reg)
{
u8 vall, valh;
u16 val;
valh = cw201x_read(cw201x, reg);
vall = cw201x_read(cw201x, reg + 1);
val = ((u16)valh << 8) | vall;
return val;
}
static int cw201x_parse_config_info(struct cw201x_info *cw201x)
{
int ret;
int i, len, size;
const u8 *info;
struct udevice *dev = cw201x->dev;
if (dev_read_prop(dev, "bat_config_info", &len)) {
len /= sizeof(u32);
size = sizeof(*cw201x->cw_bat_config_info) * len;
cw201x->cw_bat_config_info = calloc(size, 1);
if (!cw201x->cw_bat_config_info) {
printf("calloc cw_bat_config_info fail\n");
return -EINVAL;
}
ret = dev_read_u32_array(dev, "bat_config_info",
cw201x->cw_bat_config_info, len);
if (ret) {
printf("fdtdec_get cw_bat_config_info fail\n");
return -EINVAL;
}
return 0;
}
if (!dev_read_prop(dev, "cellwise,battery-profile", &len))
return -EINVAL;
size = sizeof(*cw201x->cw_bat_config_info) * len;
cw201x->cw_bat_config_info = calloc(size, 1);
if (!cw201x->cw_bat_config_info) {
printf("calloc cw_bat_config_info fail\n");
return -EINVAL;
}
info = dev_read_u8_array_ptr(dev, "cellwise,battery-profile", len);
if (!info) {
printf("fdtdec_get battery profile fail\n");
return -EINVAL;
}
for (i = 0; i < len; i++) {
cw201x->cw_bat_config_info[i] = info[i];
printf("%#x ", cw201x->cw_bat_config_info[i]);
if ((i+1) % 8 == 0)
printf("\n");
}
return 0;
}
static int cw201x_ofdata_to_platdata(struct udevice *dev)
{
struct cw201x_info *cw201x = dev_get_priv(dev);
int ret;
int hw_id0_val, hw_id1_val;
cw201x->dev = dev;
ret = cw201x_parse_config_info(cw201x);
if (ret)
return ret;
cw201x->dual_cell = dev_read_bool(dev, "cellwise,dual-cell");
ret = gpio_request_by_name_nodev(dev_ofnode(dev), "dc_det_gpio",
0, &cw201x->dc_det_gpio, GPIOD_IS_IN);
if (!ret) {
cw201x->support_dc_adp = 1;
printf("DC is valid\n");
} else {
printf("DC is invalid, ret=%d\n", ret);
}
cw201x->hw_id_check = dev_read_u32_default(dev, "hw_id_check", 0);
if (cw201x->hw_id_check) {
ret = gpio_request_by_name_nodev(dev_ofnode(dev),
"hw_id0_gpio", 0,
&cw201x->hw_id0, GPIOD_IS_IN);
if (ret)
return -EINVAL;
hw_id0_val = dm_gpio_get_value(&cw201x->hw_id0);
ret = gpio_request_by_name_nodev(dev_ofnode(dev),
"hw_id1_gpio", 0,
&cw201x->hw_id1, GPIOD_IS_IN);
if (ret)
return -EINVAL;
hw_id1_val = dm_gpio_get_value(&cw201x->hw_id1);
/* ID1 = 0, ID0 = 1 : Battery */
if (!hw_id0_val || hw_id1_val)
return -EINVAL;
}
cw201x->divider_res1 = dev_read_u32_default(dev, "divider_res1", 0);
cw201x->divider_res2 = dev_read_u32_default(dev, "divider_res2", 0);
return 0;
}
static int cw201x_get_vol(struct cw201x_info *cw201x)
{
u16 value16, value16_1, value16_2, value16_3;
int voltage;
int res1, res2;
int retry = 0;
__retry:
value16 = cw201x_read_half_word(cw201x, REG_VCELL);
if (value16 < 0)
return -1;
value16_1 = cw201x_read_half_word(cw201x, REG_VCELL);
if (value16_1 < 0)
return -1;
value16_2 = cw201x_read_half_word(cw201x, REG_VCELL);
if (value16_2 < 0)
return -1;
if (value16 > value16_1) {
value16_3 = value16;
value16 = value16_1;
value16_1 = value16_3;
}
if (value16_1 > value16_2) {
value16_3 = value16_1;
value16_1 = value16_2;
value16_2 = value16_3;
}
if (value16 > value16_1) {
value16_3 = value16;
value16 = value16_1;
value16_1 = value16_3;
}
voltage = value16_1 * 312 / 1024;
if (voltage <= 0 && retry < 10) {
retry++;
mdelay(20);
goto __retry;
}
if (cw201x->divider_res1 &&
cw201x->divider_res2) {
res1 = cw201x->divider_res1;
res2 = cw201x->divider_res2;
voltage = voltage * (res1 + res2) / res2;
}
if (cw201x->dual_cell)
voltage *= 2;
// printf("the cw201x voltage=%d\n", voltage);
return voltage;
}
static int cw201x_dwc_otg_check_dpdm(void)
{
#if defined(CONFIG_PHY_ROCKCHIP_INNO_USB2) && !defined(CONFIG_SPL_BUILD)
return rockchip_chg_get_type();
#else
printf("rockchip_chg_get_type() is not implement\n");
return CHARGER_TYPE_NO;
#endif
}
static int cw201x_get_usb_state(struct cw201x_info *cw201x)
{
int charger_type;
switch (cw201x_dwc_otg_check_dpdm()) {
case 0:
charger_type = CHARGER_TYPE_NO;
break;
case 1:
case 3:
charger_type = CHARGER_TYPE_USB;
break;
case 2:
charger_type = CHARGER_TYPE_AC;
break;
default:
charger_type = CHARGER_TYPE_NO;
break;
}
return charger_type;
}
static bool cw201x_get_dc_state(struct cw201x_info *cw201x)
{
if (dm_gpio_get_value(&cw201x->dc_det_gpio))
return true;
return false;
}
static bool cw201x_check_charge(struct cw201x_info *cw201x)
{
if (cw201x_get_usb_state(cw201x) != CHARGER_TYPE_NO)
return true;
if (cw201x_get_dc_state(cw201x))
return true;
return false;
}
static int cw201x_get_soc(struct cw201x_info *cw201x)
{
int cap, i = 0;
while (i < 10) {
mdelay(30);
cap = cw201x_read(cw201x, REG_SOC);
if ((cap < 0) || (cap > 100))
cap = cw201x->capacity;
i++;
if (cap)
break;
}
cw201x->capacity = cap;
return cw201x->capacity;
}
static int cw201x_update_get_soc(struct udevice *dev)
{
struct cw201x_info *cw201x = dev_get_priv(dev);
return cw201x_get_soc(cw201x);
}
static int cw201x_update_get_voltage(struct udevice *dev)
{
struct cw201x_info *cw201x = dev_get_priv(dev);
return cw201x_get_vol(cw201x);
}
static int cw201x_update_get_current(struct udevice *dev)
{
return 0;
}
static bool cw201x_update_get_chrg_online(struct udevice *dev)
{
struct cw201x_info *cw201x = dev_get_priv(dev);
return cw201x_check_charge(cw201x);
}
static int cw201x_capability(struct udevice *dev)
{
return FG_CAP_FUEL_GAUGE;
}
static struct dm_fuel_gauge_ops cw201x_fg_ops = {
.capability = cw201x_capability,
.get_soc = cw201x_update_get_soc,
.get_voltage = cw201x_update_get_voltage,
.get_current = cw201x_update_get_current,
.get_chrg_online = cw201x_update_get_chrg_online,
};
static int cw201x_fg_cfg(struct cw201x_info *cw201x)
{
u8 val = MODE_SLEEP;
int i;
if ((val & MODE_SLEEP_MASK) == MODE_SLEEP) {
val = MODE_NORMAL;
cw201x_write(cw201x, REG_MODE, val);
}
for (i = 0; i < 64; i++) {
cw201x_write(cw201x, REG_BATINFO + i,
(u8)cw201x->cw_bat_config_info[i]);
}
return 0;
}
static int cw201x_fg_probe(struct udevice *dev)
{
struct cw201x_info *cw201x = dev_get_priv(dev);
cw201x->dev = dev;
cw201x_fg_cfg(cw201x);
printf("vol: %d, soc: %d\n",
cw201x_get_vol(cw201x), cw201x_get_soc(cw201x));
return 0;
}
static const struct udevice_id cw201x_ids[] = {
{ .compatible = "cw201x" },
{ .compatible = "cellwise,cw2015" },
{ }
};
U_BOOT_DRIVER(cw201x_fg) = {
.name = "cw201x_fg",
.id = UCLASS_FG,
.of_match = cw201x_ids,
.probe = cw201x_fg_probe,
.ofdata_to_platdata = cw201x_ofdata_to_platdata,
.ops = &cw201x_fg_ops,
.priv_auto_alloc_size = sizeof(struct cw201x_info),
};

95
drivers/power/fuel_gauge/fg_regs.h Executable file
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/*
* (C) Copyright 2017 Rockchip Electronics Co., Ltd
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _FG_RK8XX_H_
#define _FG_RK8XX_H_
/* register definition */
#define SECONDS_REG 0X00
#define VB_MON_REG 0x21
#define THERMAL_REG 0x22
#define SUP_STS_REG 0xA0
#define USB_CTRL_REG 0xA1
#define CHRG_CTRL_REG1 0xA3
#define CHRG_CTRL_REG2 0xA4
#define CHRG_CTRL_REG3 0xA5
#define BAT_CTRL_REG 0xA6
#define BAT_HTS_TS_REG 0xA8
#define BAT_LTS_TS_REG 0xA9
#define TS_CTRL_REG 0xAC
#define ADC_CTRL_REG 0xAD
#define GGCON_REG 0xB0
#define GGSTS_REG 0xB1
#define ZERO_CUR_ADC_REGH 0xB2
#define ZERO_CUR_ADC_REGL 0xB3
#define GASCNT_CAL_REG3 0xB4
#define GASCNT_CAL_REG2 0xB5
#define GASCNT_CAL_REG1 0xB6
#define GASCNT_CAL_REG0 0xB7
#define GASCNT_REG3 0xB8
#define GASCNT_REG2 0xB9
#define GASCNT_REG1 0xBA
#define GASCNT_REG0 0xBB
#define BAT_CUR_AVG_REGH 0xBC
#define BAT_CUR_AVG_REGL 0xBD
#define TS_ADC_REGH 0xBE
#define TS_ADC_REGL 0xBF
#define RK818_TS2_ADC_REGH 0xC0
#define RK818_TS2_ADC_REGL 0xC1
#define RK816_USB_ADC_REGH 0xC0
#define RK816_USB_ADC_REGL 0xC1
#define BAT_OCV_REGH 0xC2
#define BAT_OCV_REGL 0xC3
#define BAT_VOL_REGH 0xC4
#define BAT_VOL_REGL 0xC5
#define RELAX_ENTRY_THRES_REGH 0xC6
#define RELAX_ENTRY_THRES_REGL 0xC7
#define RELAX_EXIT_THRES_REGH 0xC8
#define RELAX_EXIT_THRES_REGL 0xC9
#define RELAX_VOL1_REGH 0xCA
#define RELAX_VOL1_REGL 0xCB
#define RELAX_VOL2_REGH 0xCC
#define RELAX_VOL2_REGL 0xCD
#define RELAX_CUR1_REGH 0xCE
#define RELAX_CUR1_REGL 0xCF
#define RELAX_CUR2_REGH 0xD0
#define RELAX_CUR2_REGL 0xD1
#define CAL_OFFSET_REGH 0xD2
#define CAL_OFFSET_REGL 0xD3
#define NON_ACT_TIMER_CNT_REG 0xD4
#define VCALIB0_REGH 0xD5
#define VCALIB0_REGL 0xD6
#define VCALIB1_REGH 0xD7
#define VCALIB1_REGL 0xD8
#define FCC_GASCNT_REG3 0xD9
#define FCC_GASCNT_REG2 0xDA
#define FCC_GASCNT_REG1 0xDB
#define FCC_GASCNT_REG0 0xDC
#define IOFFSET_REGH 0xDD
#define IOFFSET_REGL 0xDE
#define SLEEP_CON_SAMP_CUR_REG 0xDF
#define SOC_REG 0xE0
#define REMAIN_CAP_REG3 0xE1
#define REMAIN_CAP_REG2 0xE2
#define REMAIN_CAP_REG1 0xE3
#define REMAIN_CAP_REG0 0xE4
#define UPDAT_LEVE_REG 0xE5
#define NEW_FCC_REG3 0xE6
#define NEW_FCC_REG2 0xE7
#define NEW_FCC_REG1 0xE8
#define NEW_FCC_REG0 0xE9
#define NON_ACT_TIMER_CNT_SAVE_REG 0xEA
#define OCV_VOL_VALID_REG 0xEB
#define REBOOT_CNT_REG 0xEC
#define POFFSET_REG 0xED
#define MISC_MARK_REG 0xEE
#define HALT_CNT_REG 0xEF
#define DATA15_REG 0xEF
#define DATA16_REG 0xF0
#define DATA17_REG 0xF1
#define DATA18_REG 0xF2
#endif

136
drivers/power/fuel_gauge/fuel_gauge_uclass.c Executable file
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/*
* (C) Copyright 2017 Rockchip Electronics Co., Ltd
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <errno.h>
#include <dm.h>
#include <power/fuel_gauge.h>
DECLARE_GLOBAL_DATA_PTR;
int fuel_gauge_capability(struct udevice *dev)
{
const struct dm_fuel_gauge_ops *ops = dev_get_driver_ops(dev);
if (!ops || !ops->capability)
return (FG_CAP_CHARGER | FG_CAP_FUEL_GAUGE);
return ops->capability(dev);
}
int fuel_gauge_bat_is_exist(struct udevice *dev)
{
const struct dm_fuel_gauge_ops *ops = dev_get_driver_ops(dev);
if (!ops || !ops->bat_is_exist)
return -ENOSYS;
return ops->bat_is_exist(dev);
}
int fuel_gauge_get_current(struct udevice *dev)
{
const struct dm_fuel_gauge_ops *ops = dev_get_driver_ops(dev);
if (!ops || !ops->get_current)
return -ENOSYS;
return ops->get_current(dev);
}
int fuel_gauge_get_voltage(struct udevice *dev)
{
const struct dm_fuel_gauge_ops *ops = dev_get_driver_ops(dev);
if (!ops || !ops->get_voltage)
return -ENOSYS;
return ops->get_voltage(dev);
}
int fuel_gauge_update_get_soc(struct udevice *dev)
{
const struct dm_fuel_gauge_ops *ops = dev_get_driver_ops(dev);
if (!ops || !ops->get_soc)
return -ENOSYS;
return ops->get_soc(dev);
}
bool fuel_gauge_get_chrg_online(struct udevice *dev)
{
const struct dm_fuel_gauge_ops *ops = dev_get_driver_ops(dev);
if (!ops || !ops->get_chrg_online)
return -ENOSYS;
return ops->get_chrg_online(dev);
}
int fuel_gauge_get_temperature(struct udevice *dev, int *temp)
{
const struct dm_fuel_gauge_ops *ops = dev_get_driver_ops(dev);
if (!ops || !ops->get_temperature)
return -ENOSYS;
return ops->get_temperature(dev, temp);
}
int charger_set_charger_voltage(struct udevice *dev, int uV)
{
const struct dm_fuel_gauge_ops *ops = dev_get_driver_ops(dev);
if (!ops || !ops->set_charger_voltage)
return -ENOSYS;
return ops->set_charger_voltage(dev, uV);
}
int charger_set_current(struct udevice *dev, int ichrg_uA)
{
const struct dm_fuel_gauge_ops *ops = dev_get_driver_ops(dev);
if (!ops || !ops->set_charger_current)
return -ENOSYS;
return ops->set_charger_current(dev, ichrg_uA);
}
int charger_set_iprechg_current(struct udevice *dev, int iprechrg_uA)
{
const struct dm_fuel_gauge_ops *ops = dev_get_driver_ops(dev);
if (!ops || !ops->set_iprechg_current)
return -ENOSYS;
return ops->set_iprechg_current(dev, iprechrg_uA);
}
int charger_set_enable(struct udevice *dev)
{
const struct dm_fuel_gauge_ops *ops = dev_get_driver_ops(dev);
if (!ops || !ops->set_charger_enable)
return -ENOSYS;
return ops->set_charger_enable(dev);
}
int charger_set_disable(struct udevice *dev)
{
const struct dm_fuel_gauge_ops *ops = dev_get_driver_ops(dev);
if (!ops || !ops->set_charger_disable)
return -ENOSYS;
return ops->set_charger_disable(dev);
}
UCLASS_DRIVER(fuel_guage) = {
.id = UCLASS_FG,
.name = "fuel_gauge",
};

45
drivers/power/power_delivery/Kconfig Executable file
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# SPDX-License-Identifier: GPL-2.0
config DM_POWER_DELIVERY
bool "Enable driver model power delivery support"
depends on DM
help
This adds a simple uclass for power delivery.
config TYPEC_TCPM
tristate "USB Type-C Port Controller Manager"
depends on DM && DM_POWER_DELIVERY
help
The Type-C Port Controller Manager provides a USB PD and USB Type-C
state machine for use with Type-C Port Controllers.
config TYPEC_TCPCI
tristate "Type-C Port Controller Interface driver"
depends on DM && DM_POWER_DELIVERY && DM_I2C
help
Type-C Port Controller driver for TCPCI-compliant controller.
config RV_BOOK
tristate "RV Book Type-C support"
help
Enable support for rvbook device's Type-C Port Controller.
if TYPEC_TCPCI
config TYPEC_HUSB311
tristate "Hynetek HUSB311 Type-C chip driver"
depends on DM && DM_POWER_DELIVERY && DM_I2C
help
Hynetek HUSB311 Type-C chip driver that works with
Type-C Port Controller Manager to provide USB PD and USB
Type-C functionalities.
endif # TYPEC_TCPCI
config TYPEC_FUSB302
tristate "Fairchild FUSB302 Type-C chip driver"
depends on DM && DM_POWER_DELIVERY && DM_I2C
help
The Fairchild FUSB302 Type-C chip driver that works with
Type-C Port Controller Manager to provide USB PD and USB
Type-C functionalities.

7
drivers/power/power_delivery/Makefile Executable file
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# SPDX-License-Identifier: GPL-2.0
obj-$(CONFIG_$(SPL_)DM_POWER_DELIVERY) += power_delivery_uclass.o
obj-$(CONFIG_TYPEC_TCPM) += tcpm.o
obj-$(CONFIG_TYPEC_FUSB302) += fusb302.o
obj-$(CONFIG_TYPEC_TCPCI) += tcpci.o
obj-$(CONFIG_TYPEC_HUSB311) += tcpci_husb311.o

31
drivers/power/power_delivery/power_delivery_uclass.c Executable file
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@@ -0,0 +1,31 @@
/*
* (C) Copyright 2022 Rockchip Electronics Co., Ltd
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <errno.h>
#include <dm.h>
#include <dm/device-internal.h>
#include <power/power_delivery/power_delivery.h>
DECLARE_GLOBAL_DATA_PTR;
int power_delivery_get_data(struct udevice *dev, struct power_delivery_data *pd_data)
{
const struct dm_power_delivery_ops *ops = dev_get_driver_ops(dev);
if (!ops || !ops->get_current || !ops->get_voltage || !ops->get_online)
return -ENOSYS;
pd_data->voltage = ops->get_voltage(dev);
pd_data->current = ops->get_current(dev);
pd_data->online = ops->get_online(dev);
return 0;
}
UCLASS_DRIVER(power_delivery) = {
.id = UCLASS_PD,
.name = "power_delivery",
};

778
drivers/power/power_delivery/tcpci.c Executable file
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// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2015-2017 Google, Inc
*
* USB Type-C Port Controller Interface.
*/
#include <dm.h>
#include <i2c.h>
#include <asm/gpio.h>
#include <power/power_delivery/pd.h>
#include <power/power_delivery/tcpm.h>
#include <power/power_delivery/typec.h>
#include <power/power_delivery/power_delivery.h>
#include "tcpci.h"
#define PD_RETRY_COUNT 3
#define tcpc_presenting_cc1_rd(reg) \
(!(TCPC_ROLE_CTRL_DRP & (reg)) && \
(((reg) & (TCPC_ROLE_CTRL_CC1_MASK << TCPC_ROLE_CTRL_CC1_SHIFT)) == \
(TCPC_ROLE_CTRL_CC_RD << TCPC_ROLE_CTRL_CC1_SHIFT)))
#define tcpc_presenting_cc2_rd(reg) \
(!(TCPC_ROLE_CTRL_DRP & (reg)) && \
(((reg) & (TCPC_ROLE_CTRL_CC2_MASK << TCPC_ROLE_CTRL_CC2_SHIFT)) == \
(TCPC_ROLE_CTRL_CC_RD << TCPC_ROLE_CTRL_CC2_SHIFT)))
struct tcpci {
struct udevice *dev;
struct tcpm_port *port;
bool controls_vbus;
bool gpio_cc_int_present;
struct tcpc_dev tcpc;
struct tcpci_data *data;
struct gpio_desc gpio_cc_int;
};
struct tcpci_chip {
struct udevice *udev;
struct tcpci *tcpci;
struct tcpci_data data;
};
static inline struct tcpci *tcpc_to_tcpci(struct tcpc_dev *tcpc)
{
return container_of(tcpc, struct tcpci, tcpc);
}
static int tcpci_read16(struct tcpci *tcpci, unsigned int reg, u16 *val)
{
int ret = 0;
u8 buffer[2];
ret = dm_i2c_read(tcpci->dev, reg, buffer, 2);
if (ret) {
printf("%s: cannot read %02x, ret=%d\n",
__func__, reg, ret);
return ret;
}
*val = ((buffer[1] << 8) & 0xFF00) | (buffer[0] & 0xFF);
return ret;
}
static int tcpci_block_read(struct tcpci *tcpci, unsigned int reg,
u8 *data, u8 length)
{
int ret = 0;
ret = dm_i2c_read(tcpci->dev, reg, data, length);
if (ret)
printf("%s: cannot block read 0x%02x, len=%d, ret=%d\n",
__func__, reg, length, ret);
return ret;
}
static int tcpci_write16(struct tcpci *tcpci, unsigned int reg, u16 val)
{
int ret = 0;
u8 buffer[2];
buffer[0] = val & 0xFF;
buffer[1] = (val >> 8) & 0xFF;
ret = dm_i2c_write(tcpci->dev, reg, buffer, 2);
if (ret)
printf("%s: cannot write 0x%02x, ret=%d\n",
__func__, reg, ret);
return ret;
}
static int tcpci_block_write(struct tcpci *tcpci, unsigned int reg,
u8 *data, u8 length)
{
int ret = 0;
ret = dm_i2c_write(tcpci->dev, reg, data, length);
if (ret)
printf("%s: cannot block write 0x%02x, len=%d, ret=%d\n",
__func__, reg, length, ret);
return ret;
}
static int tcpci_set_cc(struct tcpc_dev *tcpc, enum typec_cc_status cc)
{
struct tcpci *tcpci = tcpc_to_tcpci(tcpc);
unsigned int reg;
int ret;
switch (cc) {
case TYPEC_CC_RA:
reg = (TCPC_ROLE_CTRL_CC_RA << TCPC_ROLE_CTRL_CC1_SHIFT) |
(TCPC_ROLE_CTRL_CC_RA << TCPC_ROLE_CTRL_CC2_SHIFT);
break;
case TYPEC_CC_RD:
reg = (TCPC_ROLE_CTRL_CC_RD << TCPC_ROLE_CTRL_CC1_SHIFT) |
(TCPC_ROLE_CTRL_CC_RD << TCPC_ROLE_CTRL_CC2_SHIFT);
break;
case TYPEC_CC_RP_DEF:
reg = (TCPC_ROLE_CTRL_CC_RP << TCPC_ROLE_CTRL_CC1_SHIFT) |
(TCPC_ROLE_CTRL_CC_RP << TCPC_ROLE_CTRL_CC2_SHIFT) |
(TCPC_ROLE_CTRL_RP_VAL_DEF <<
TCPC_ROLE_CTRL_RP_VAL_SHIFT);
break;
case TYPEC_CC_RP_1_5:
reg = (TCPC_ROLE_CTRL_CC_RP << TCPC_ROLE_CTRL_CC1_SHIFT) |
(TCPC_ROLE_CTRL_CC_RP << TCPC_ROLE_CTRL_CC2_SHIFT) |
(TCPC_ROLE_CTRL_RP_VAL_1_5 <<
TCPC_ROLE_CTRL_RP_VAL_SHIFT);
break;
case TYPEC_CC_RP_3_0:
reg = (TCPC_ROLE_CTRL_CC_RP << TCPC_ROLE_CTRL_CC1_SHIFT) |
(TCPC_ROLE_CTRL_CC_RP << TCPC_ROLE_CTRL_CC2_SHIFT) |
(TCPC_ROLE_CTRL_RP_VAL_3_0 <<
TCPC_ROLE_CTRL_RP_VAL_SHIFT);
break;
case TYPEC_CC_OPEN:
default:
reg = (TCPC_ROLE_CTRL_CC_OPEN << TCPC_ROLE_CTRL_CC1_SHIFT) |
(TCPC_ROLE_CTRL_CC_OPEN << TCPC_ROLE_CTRL_CC2_SHIFT);
break;
}
ret = dm_i2c_reg_write(tcpci->dev, TCPC_ROLE_CTRL, reg);
if (ret)
return ret;
return 0;
}
static int tcpci_start_toggling(struct tcpc_dev *tcpc,
enum typec_port_type port_type,
enum typec_cc_status cc)
{
int ret;
struct tcpci *tcpci = tcpc_to_tcpci(tcpc);
unsigned int reg = TCPC_ROLE_CTRL_DRP;
if (port_type != TYPEC_PORT_DRP)
return -EOPNOTSUPP;
/* Handle vendor drp toggling */
if (tcpci->data->start_drp_toggling) {
ret = tcpci->data->start_drp_toggling(tcpci, tcpci->data, cc);
if (ret < 0)
return ret;
}
switch (cc) {
default:
case TYPEC_CC_RP_DEF:
reg |= (TCPC_ROLE_CTRL_RP_VAL_DEF <<
TCPC_ROLE_CTRL_RP_VAL_SHIFT);
break;
case TYPEC_CC_RP_1_5:
reg |= (TCPC_ROLE_CTRL_RP_VAL_1_5 <<
TCPC_ROLE_CTRL_RP_VAL_SHIFT);
break;
case TYPEC_CC_RP_3_0:
reg |= (TCPC_ROLE_CTRL_RP_VAL_3_0 <<
TCPC_ROLE_CTRL_RP_VAL_SHIFT);
break;
}
if (cc == TYPEC_CC_RD)
reg |= (TCPC_ROLE_CTRL_CC_RD << TCPC_ROLE_CTRL_CC1_SHIFT) |
(TCPC_ROLE_CTRL_CC_RD << TCPC_ROLE_CTRL_CC2_SHIFT);
else
reg |= (TCPC_ROLE_CTRL_CC_RP << TCPC_ROLE_CTRL_CC1_SHIFT) |
(TCPC_ROLE_CTRL_CC_RP << TCPC_ROLE_CTRL_CC2_SHIFT);
ret = dm_i2c_reg_write(tcpci->dev, TCPC_ROLE_CTRL, reg);
if (ret < 0)
return ret;
return dm_i2c_reg_write(tcpci->dev, TCPC_COMMAND,
TCPC_CMD_LOOK4CONNECTION);
}
static enum typec_cc_status tcpci_to_typec_cc(unsigned int cc, bool sink)
{
switch (cc) {
case 0x1:
return sink ? TYPEC_CC_RP_DEF : TYPEC_CC_RA;
case 0x2:
return sink ? TYPEC_CC_RP_1_5 : TYPEC_CC_RD;
case 0x3:
if (sink)
return TYPEC_CC_RP_3_0;
/* fall through */
case 0x0:
default:
return TYPEC_CC_OPEN;
}
}
static int tcpci_get_cc(struct tcpc_dev *tcpc,
enum typec_cc_status *cc1, enum typec_cc_status *cc2)
{
struct tcpci *tcpci = tcpc_to_tcpci(tcpc);
unsigned int reg, role_control;
role_control = dm_i2c_reg_read(tcpci->dev, TCPC_ROLE_CTRL);
if (role_control < 0)
return role_control;
reg = dm_i2c_reg_read(tcpci->dev, TCPC_CC_STATUS);
if (reg < 0)
return reg;
*cc1 = tcpci_to_typec_cc((reg >> TCPC_CC_STATUS_CC1_SHIFT) &
TCPC_CC_STATUS_CC1_MASK,
reg & TCPC_CC_STATUS_TERM ||
tcpc_presenting_cc1_rd(role_control));
*cc2 = tcpci_to_typec_cc((reg >> TCPC_CC_STATUS_CC2_SHIFT) &
TCPC_CC_STATUS_CC2_MASK,
reg & TCPC_CC_STATUS_TERM ||
tcpc_presenting_cc2_rd(role_control));
return 0;
}
static int tcpci_set_polarity(struct tcpc_dev *tcpc,
enum typec_cc_polarity polarity)
{
struct tcpci *tcpci = tcpc_to_tcpci(tcpc);
unsigned int reg;
int ret;
enum typec_cc_status cc1, cc2;
/* Obtain Rp setting from role control */
reg = dm_i2c_reg_read(tcpci->dev, TCPC_ROLE_CTRL);
if (reg < 0)
return reg;
ret = tcpci_get_cc(tcpc, &cc1, &cc2);
if (ret < 0)
return ret;
/*
* When port has drp toggling enabled, ROLE_CONTROL would only have the initial
* terminations for the toggling and does not indicate the final cc
* terminations when ConnectionResult is 0 i.e. drp toggling stops and
* the connection is resolbed. Infer port role from TCPC_CC_STATUS based on the
* terminations seen. The port role is then used to set the cc terminations.
*/
if (reg & TCPC_ROLE_CTRL_DRP) {
/* Disable DRP for the OPEN setting to take effect */
reg = reg & ~TCPC_ROLE_CTRL_DRP;
if (polarity == TYPEC_POLARITY_CC2) {
reg &= ~(TCPC_ROLE_CTRL_CC2_MASK << TCPC_ROLE_CTRL_CC2_SHIFT);
/* Local port is source */
if (cc2 == TYPEC_CC_RD)
/* Role control would have the Rp setting when DRP was enabled */
reg |= TCPC_ROLE_CTRL_CC_RP << TCPC_ROLE_CTRL_CC2_SHIFT;
else
reg |= TCPC_ROLE_CTRL_CC_RD << TCPC_ROLE_CTRL_CC2_SHIFT;
} else {
reg &= ~(TCPC_ROLE_CTRL_CC1_MASK << TCPC_ROLE_CTRL_CC1_SHIFT);
/* Local port is source */
if (cc1 == TYPEC_CC_RD)
/* Role control would have the Rp setting when DRP was enabled */
reg |= TCPC_ROLE_CTRL_CC_RP << TCPC_ROLE_CTRL_CC1_SHIFT;
else
reg |= TCPC_ROLE_CTRL_CC_RD << TCPC_ROLE_CTRL_CC1_SHIFT;
}
}
if (polarity == TYPEC_POLARITY_CC2)
reg |= TCPC_ROLE_CTRL_CC_OPEN << TCPC_ROLE_CTRL_CC1_SHIFT;
else
reg |= TCPC_ROLE_CTRL_CC_OPEN << TCPC_ROLE_CTRL_CC2_SHIFT;
ret = dm_i2c_reg_write(tcpci->dev, TCPC_ROLE_CTRL, reg);
if (ret < 0)
return ret;
return dm_i2c_reg_write(tcpci->dev, TCPC_TCPC_CTRL,
(polarity == TYPEC_POLARITY_CC2) ?
TCPC_TCPC_CTRL_ORIENTATION : 0);
}
static int tcpci_set_vconn(struct tcpc_dev *tcpc, bool enable)
{
struct tcpci *tcpci = tcpc_to_tcpci(tcpc);
int ret;
unsigned int reg;
/* Handle vendor set vconn */
if (tcpci->data->set_vconn) {
ret = tcpci->data->set_vconn(tcpci, tcpci->data, enable);
if (ret < 0)
return ret;
}
reg = dm_i2c_reg_read(tcpci->dev, TCPC_POWER_CTRL);
if (reg)
return reg;
reg &= ~TCPC_POWER_CTRL_VCONN_ENABLE;
reg |= enable ? TCPC_POWER_CTRL_VCONN_ENABLE : 0;
return dm_i2c_reg_write(tcpci->dev, TCPC_POWER_CTRL, reg);
}
static int tcpci_set_roles(struct tcpc_dev *tcpc, bool attached,
enum typec_role role, enum typec_data_role data)
{
struct tcpci *tcpci = tcpc_to_tcpci(tcpc);
unsigned int reg;
int ret;
reg = PD_REV20 << TCPC_MSG_HDR_INFO_REV_SHIFT;
if (role == TYPEC_SOURCE)
reg |= TCPC_MSG_HDR_INFO_PWR_ROLE;
if (data == TYPEC_HOST)
reg |= TCPC_MSG_HDR_INFO_DATA_ROLE;
ret = dm_i2c_reg_write(tcpci->dev, TCPC_MSG_HDR_INFO, reg);
if (ret < 0)
return ret;
return 0;
}
static int tcpci_set_pd_rx(struct tcpc_dev *tcpc, bool enable)
{
struct tcpci *tcpci = tcpc_to_tcpci(tcpc);
unsigned int reg = 0;
int ret;
if (enable)
reg = TCPC_RX_DETECT_SOP | TCPC_RX_DETECT_HARD_RESET;
ret = dm_i2c_reg_write(tcpci->dev, TCPC_RX_DETECT, reg);
if (ret < 0)
return ret;
return 0;
}
static int tcpci_get_vbus(struct tcpc_dev *tcpc)
{
struct tcpci *tcpci = tcpc_to_tcpci(tcpc);
unsigned int reg;
reg = dm_i2c_reg_read(tcpci->dev, TCPC_POWER_STATUS);
if (reg < 0)
return reg;
return !!(reg & TCPC_POWER_STATUS_VBUS_PRES);
}
static int tcpci_set_vbus(struct tcpc_dev *tcpc, bool source, bool sink)
{
struct tcpci *tcpci = tcpc_to_tcpci(tcpc);
int ret;
/* Disable both source and sink first before enabling anything */
if (!source) {
ret = dm_i2c_reg_write(tcpci->dev, TCPC_COMMAND,
TCPC_CMD_DISABLE_SRC_VBUS);
if (ret < 0)
return ret;
}
if (!sink) {
ret = dm_i2c_reg_write(tcpci->dev, TCPC_COMMAND,
TCPC_CMD_DISABLE_SINK_VBUS);
if (ret < 0)
return ret;
}
if (source) {
ret = dm_i2c_reg_write(tcpci->dev, TCPC_COMMAND,
TCPC_CMD_SRC_VBUS_DEFAULT);
if (ret < 0)
return ret;
}
if (sink) {
ret = dm_i2c_reg_write(tcpci->dev, TCPC_COMMAND,
TCPC_CMD_SINK_VBUS);
if (ret < 0)
return ret;
}
return 0;
}
static int tcpci_pd_transmit(struct tcpc_dev *tcpc,
enum tcpm_transmit_type type,
const struct pd_message *msg,
unsigned int negotiated_rev)
{
struct tcpci *tcpci = tcpc_to_tcpci(tcpc);
u16 header = msg ? le16_to_cpu(msg->header) : 0;
unsigned int reg, cnt;
int ret;
cnt = msg ? pd_header_cnt(header) * 4 : 0;
ret = dm_i2c_reg_write(tcpci->dev, TCPC_TX_BYTE_CNT, cnt + 2);
if (ret < 0)
return ret;
ret = tcpci_write16(tcpci, TCPC_TX_HDR, header);
if (ret < 0)
return ret;
if (cnt > 0) {
ret = tcpci_block_write(tcpci, TCPC_TX_DATA,
(u8 *)&msg->payload, cnt);
if (ret < 0)
return ret;
}
reg = (PD_RETRY_COUNT << TCPC_TRANSMIT_RETRY_SHIFT) |
(type << TCPC_TRANSMIT_TYPE_SHIFT);
ret = dm_i2c_reg_write(tcpci->dev, TCPC_TRANSMIT, reg);
if (ret < 0)
return ret;
return 0;
}
static int tcpci_init(struct tcpc_dev *tcpc)
{
struct tcpci *tcpci = tcpc_to_tcpci(tcpc);
unsigned int timeout = 0; /* XXX */
unsigned int reg;
int ret;
while (timeout < 100) {
reg = dm_i2c_reg_read(tcpci->dev, TCPC_POWER_STATUS);
if (reg < 0)
return reg;
if (!(reg & TCPC_POWER_STATUS_UNINIT))
break;
timeout++;
udelay(200);
}
if (timeout >= 100)
return -ETIMEDOUT;
/* Handle vendor init */
if (tcpci->data->init) {
ret = tcpci->data->init(tcpci, tcpci->data);
if (ret < 0)
return ret;
}
/* Clear all events */
ret = tcpci_write16(tcpci, TCPC_ALERT, 0xffff);
if (ret < 0)
return ret;
if (tcpci->controls_vbus)
reg = TCPC_POWER_STATUS_VBUS_PRES;
else
reg = 0;
ret = dm_i2c_reg_write(tcpci->dev, TCPC_POWER_STATUS_MASK, reg);
if (ret < 0)
return ret;
/* Enable Vbus detection */
ret = dm_i2c_reg_write(tcpci->dev, TCPC_COMMAND,
TCPC_CMD_ENABLE_VBUS_DETECT);
if (ret < 0)
return ret;
reg = TCPC_ALERT_TX_SUCCESS | TCPC_ALERT_TX_FAILED |
TCPC_ALERT_TX_DISCARDED | TCPC_ALERT_RX_STATUS |
TCPC_ALERT_RX_HARD_RST | TCPC_ALERT_CC_STATUS;
if (tcpci->controls_vbus)
reg |= TCPC_ALERT_POWER_STATUS;
return tcpci_write16(tcpci, TCPC_ALERT_MASK, reg);
}
static void tcpci_poll_event(struct tcpc_dev *tcpc)
{
u16 status;
struct tcpci *tcpci = tcpc_to_tcpci(tcpc);
tcpci_read16(tcpci, TCPC_ALERT, &status);
/*
* Clear alert status for everything except RX_STATUS, which shouldn't
* be cleared until we have successfully retrieved message.
*/
if (status & ~TCPC_ALERT_RX_STATUS)
tcpci_write16(tcpci, TCPC_ALERT,
status & ~TCPC_ALERT_RX_STATUS);
if (status & TCPC_ALERT_CC_STATUS)
tcpm_cc_change(tcpci->port);
if (status & TCPC_ALERT_POWER_STATUS) {
unsigned int reg;
reg = dm_i2c_reg_read(tcpci->dev, TCPC_POWER_STATUS_MASK);
if (reg < 0)
return;
/*
* If power status mask has been reset, then the TCPC
* has reset.
*/
if (reg == 0xff)
tcpm_tcpc_reset(tcpci->port);
else
tcpm_vbus_change(tcpci->port);
}
if (status & TCPC_ALERT_RX_STATUS) {
struct pd_message msg;
unsigned int cnt, payload_cnt;
u16 header;
cnt = dm_i2c_reg_read(tcpci->dev, TCPC_RX_BYTE_CNT);
if (cnt < 0)
return;
/*
* 'cnt' corresponds to READABLE_BYTE_COUNT in section 4.4.14
* of the TCPCI spec [Rev 2.0 Ver 1.0 October 2017] and is
* defined in table 4-36 as one greater than the number of
* bytes received. And that number includes the header. So:
*/
if (cnt > 3)
payload_cnt = cnt - (1 + sizeof(msg.header));
else
payload_cnt = 0;
tcpci_read16(tcpci, TCPC_RX_HDR, &header);
msg.header = cpu_to_le16(header);
if ((payload_cnt > sizeof(msg.payload)))
payload_cnt = sizeof(msg.payload);
if (payload_cnt > 0)
tcpci_block_read(tcpci, TCPC_RX_DATA,
(u8 *)&msg.payload, payload_cnt);
/* Read complete, clear RX status alert bit */
tcpci_write16(tcpci, TCPC_ALERT, TCPC_ALERT_RX_STATUS);
tcpm_pd_receive(tcpci->port, &msg);
}
if (status & TCPC_ALERT_RX_HARD_RST)
tcpm_pd_hard_reset(tcpci->port);
if (status & TCPC_ALERT_TX_SUCCESS)
tcpm_pd_transmit_complete(tcpci->port, TCPC_TX_SUCCESS);
else if (status & TCPC_ALERT_TX_DISCARDED)
tcpm_pd_transmit_complete(tcpci->port, TCPC_TX_DISCARDED);
else if (status & TCPC_ALERT_TX_FAILED)
tcpm_pd_transmit_complete(tcpci->port, TCPC_TX_FAILED);
}
static int tcpci_enter_low_power_mode(struct tcpc_dev *tcpc,
bool attached, bool pd_capable)
{
int ret;
struct tcpci *tcpci = tcpc_to_tcpci(tcpc);
unsigned int reg;
/* Disable chip interrupts before unregistering port */
ret = tcpci_write16(tcpci, TCPC_ALERT_MASK, 0);
if (ret < 0)
return ret;
reg = dm_i2c_reg_read(tcpci->dev, TCPC_BMCIO_CTRL);
if (reg < 0)
return reg;
/*
* For Type-C devices with PD capability, Only disable VBUS detect,
* do not diable 24M oscillator for BMC communication. Otherwise,
* data packets cannot be received.
*/
if (attached && pd_capable)
reg &= ~TCPC_BMCIO_VBUS_DETECT_MASK;
else
reg &= ~(TCPC_BMCIO_VBUS_DETECT_MASK | TCPC_BMCIO_24M_OSC_MASK);
return dm_i2c_reg_write(tcpci->dev, TCPC_BMCIO_CTRL, reg);
}
static int tcpci_parse_config(struct tcpci *tcpci)
{
tcpci->controls_vbus = true; /* XXX */
tcpci->tcpc.connector_node = dev_read_subnode(tcpci->dev, "connector");
if (!ofnode_valid(tcpci->tcpc.connector_node)) {
printf("%s: 'connector' node is not found\n", __func__);
return -EINVAL;
}
return 0;
}
struct tcpci *tcpci_register_port(struct udevice *dev, struct tcpci_data *data)
{
struct tcpci *tcpci;
int err;
tcpci = devm_kzalloc(dev, sizeof(*tcpci), GFP_KERNEL);
if (!tcpci)
return ERR_PTR(-ENOMEM);
err = gpio_request_by_name(dev, "int-n-gpios", 0, &tcpci->gpio_cc_int, GPIOD_IS_IN);
if (err) {
printf("%s: fail to get int GPIO: err=%d\n", __func__, err);
tcpci->gpio_cc_int_present = false;
} else {
printf("%s: success to get int GPIO: err=%d\n", __func__, err);
tcpci->gpio_cc_int_present = true;
}
tcpci->dev = dev;
tcpci->data = data;
tcpci->tcpc.init = tcpci_init;
tcpci->tcpc.get_vbus = tcpci_get_vbus;
tcpci->tcpc.set_vbus = tcpci_set_vbus;
tcpci->tcpc.set_cc = tcpci_set_cc;
tcpci->tcpc.get_cc = tcpci_get_cc;
tcpci->tcpc.set_polarity = tcpci_set_polarity;
tcpci->tcpc.set_vconn = tcpci_set_vconn;
tcpci->tcpc.start_toggling = tcpci_start_toggling;
tcpci->tcpc.set_pd_rx = tcpci_set_pd_rx;
tcpci->tcpc.set_roles = tcpci_set_roles;
tcpci->tcpc.pd_transmit = tcpci_pd_transmit;
tcpci->tcpc.poll_event = tcpci_poll_event;
tcpci->tcpc.enter_low_power_mode = tcpci_enter_low_power_mode;
err = tcpci_parse_config(tcpci);
if (err < 0)
return ERR_PTR(err);
tcpci->port = tcpm_port_init(tcpci->dev, &tcpci->tcpc);
if (IS_ERR(tcpci->port)) {
printf("%s: failed to tcpm port init\n", __func__);
return ERR_CAST(tcpci->port);
}
// tcpm_tcpc_reset(tcpci->port);
tcpm_poll_event(tcpci->port);
return tcpci;
}
EXPORT_SYMBOL_GPL(tcpci_register_port);
void tcpci_unregister_port(struct tcpci *tcpci)
{
tcpm_uninit_port(tcpci->port);
}
EXPORT_SYMBOL_GPL(tcpci_unregister_port);
int tcpci_get_voltage_fun(struct tcpci *tcpci)
{
return tcpm_get_voltage(tcpci->port);
}
EXPORT_SYMBOL_GPL(tcpci_get_voltage_fun);
int tcpci_get_current_fun(struct tcpci *tcpci)
{
return tcpm_get_current(tcpci->port);
}
EXPORT_SYMBOL_GPL(tcpci_get_current_fun);
int tcpci_get_online_fun(struct tcpci *tcpci)
{
return tcpm_get_online(tcpci->port);
}
EXPORT_SYMBOL_GPL(tcpci_get_online_fun);
static int tcpci_probe(struct udevice *dev)
{
struct tcpci_chip *chip = dev_get_priv(dev);
int err;
u16 val = 0;
chip->udev = dev;
/* Disable chip interrupts before requesting irq */
err = tcpci_write16(chip->tcpci, TCPC_ALERT_MASK, val);
if (err < 0)
return err;
chip->tcpci = tcpci_register_port(chip->udev, &chip->data);
if (IS_ERR(chip->tcpci))
return PTR_ERR(chip->tcpci);
return 0;
}
static int tcpci_remove(struct udevice *dev)
{
struct tcpci_chip *chip = dev_get_priv(dev);
int err;
/* Disable chip interrupts before unregistering port */
err = tcpci_write16(chip->tcpci, TCPC_ALERT_MASK, 0);
if (err < 0)
return err;
tcpci_unregister_port(chip->tcpci);
return 0;
}
static int tcpci_get_voltage(struct udevice *dev)
{
struct tcpci_chip *chip = dev_get_priv(dev);
return tcpm_get_voltage(chip->tcpci->port);
}
static int tcpci_get_current(struct udevice *dev)
{
struct tcpci_chip *chip = dev_get_priv(dev);
return tcpm_get_current(chip->tcpci->port);
}
static int tcpci_get_online(struct udevice *dev)
{
struct tcpci_chip *chip = dev_get_priv(dev);
return tcpm_get_online(chip->tcpci->port);
}
static struct dm_power_delivery_ops tcpci_ops = {
.get_voltage = tcpci_get_voltage,
.get_current = tcpci_get_current,
.get_online = tcpci_get_online,
};
static const struct udevice_id tcpci_ids[] = {
{ .compatible = "nxp,ptn5110", },
{},
};
U_BOOT_DRIVER(tcpci) = {
.name = "tcpci",
.id = UCLASS_PD,
.of_match = tcpci_ids,
.ops = &tcpci_ops,
.probe = tcpci_probe,
.remove = tcpci_remove,
.priv_auto_alloc_size = sizeof(struct tcpci_chip),
}
MODULE_DESCRIPTION("USB Type-C Port Controller Interface driver");
MODULE_LICENSE("GPL");

150
drivers/power/power_delivery/tcpci.h Executable file
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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2015-2017 Google, Inc
*
* USB Type-C Port Controller Interface.
*/
#ifndef __LINUX_USB_TCPCI_H
#define __LINUX_USB_TCPCI_H
#define TCPC_VENDOR_ID 0x0
#define TCPC_PRODUCT_ID 0x2
#define TCPC_BCD_DEV 0x4
#define TCPC_TC_REV 0x6
#define TCPC_PD_REV 0x8
#define TCPC_PD_INT_REV 0xa
#define TCPC_ALERT 0x10
#define TCPC_ALERT_VBUS_DISCNCT BIT(11)
#define TCPC_ALERT_RX_BUF_OVF BIT(10)
#define TCPC_ALERT_FAULT BIT(9)
#define TCPC_ALERT_V_ALARM_LO BIT(8)
#define TCPC_ALERT_V_ALARM_HI BIT(7)
#define TCPC_ALERT_TX_SUCCESS BIT(6)
#define TCPC_ALERT_TX_DISCARDED BIT(5)
#define TCPC_ALERT_TX_FAILED BIT(4)
#define TCPC_ALERT_RX_HARD_RST BIT(3)
#define TCPC_ALERT_RX_STATUS BIT(2)
#define TCPC_ALERT_POWER_STATUS BIT(1)
#define TCPC_ALERT_CC_STATUS BIT(0)
#define TCPC_ALERT_MASK 0x12
#define TCPC_POWER_STATUS_MASK 0x14
#define TCPC_FAULT_STATUS_MASK 0x15
#define TCPC_CONFIG_STD_OUTPUT 0x18
#define TCPC_TCPC_CTRL 0x19
#define TCPC_TCPC_CTRL_ORIENTATION BIT(0)
#define TCPC_ROLE_CTRL 0x1a
#define TCPC_ROLE_CTRL_DRP BIT(6)
#define TCPC_ROLE_CTRL_RP_VAL_SHIFT 4
#define TCPC_ROLE_CTRL_RP_VAL_MASK 0x3
#define TCPC_ROLE_CTRL_RP_VAL_DEF 0x0
#define TCPC_ROLE_CTRL_RP_VAL_1_5 0x1
#define TCPC_ROLE_CTRL_RP_VAL_3_0 0x2
#define TCPC_ROLE_CTRL_CC2_SHIFT 2
#define TCPC_ROLE_CTRL_CC2_MASK 0x3
#define TCPC_ROLE_CTRL_CC1_SHIFT 0
#define TCPC_ROLE_CTRL_CC1_MASK 0x3
#define TCPC_ROLE_CTRL_CC_RA 0x0
#define TCPC_ROLE_CTRL_CC_RP 0x1
#define TCPC_ROLE_CTRL_CC_RD 0x2
#define TCPC_ROLE_CTRL_CC_OPEN 0x3
#define TCPC_FAULT_CTRL 0x1b
#define TCPC_POWER_CTRL 0x1c
#define TCPC_POWER_CTRL_VCONN_ENABLE BIT(0)
#define TCPC_CC_STATUS 0x1d
#define TCPC_CC_STATUS_TOGGLING BIT(5)
#define TCPC_CC_STATUS_TERM BIT(4)
#define TCPC_CC_STATUS_CC2_SHIFT 2
#define TCPC_CC_STATUS_CC2_MASK 0x3
#define TCPC_CC_STATUS_CC1_SHIFT 0
#define TCPC_CC_STATUS_CC1_MASK 0x3
#define TCPC_POWER_STATUS 0x1e
#define TCPC_POWER_STATUS_UNINIT BIT(6)
#define TCPC_POWER_STATUS_VBUS_DET BIT(3)
#define TCPC_POWER_STATUS_VBUS_PRES BIT(2)
#define TCPC_FAULT_STATUS 0x1f
#define TCPC_COMMAND 0x23
#define TCPC_CMD_WAKE_I2C 0x11
#define TCPC_CMD_DISABLE_VBUS_DETECT 0x22
#define TCPC_CMD_ENABLE_VBUS_DETECT 0x33
#define TCPC_CMD_DISABLE_SINK_VBUS 0x44
#define TCPC_CMD_SINK_VBUS 0x55
#define TCPC_CMD_DISABLE_SRC_VBUS 0x66
#define TCPC_CMD_SRC_VBUS_DEFAULT 0x77
#define TCPC_CMD_SRC_VBUS_HIGH 0x88
#define TCPC_CMD_LOOK4CONNECTION 0x99
#define TCPC_CMD_RXONEMORE 0xAA
#define TCPC_CMD_I2C_IDLE 0xFF
#define TCPC_DEV_CAP_1 0x24
#define TCPC_DEV_CAP_2 0x26
#define TCPC_STD_INPUT_CAP 0x28
#define TCPC_STD_OUTPUT_CAP 0x29
#define TCPC_MSG_HDR_INFO 0x2e
#define TCPC_MSG_HDR_INFO_DATA_ROLE BIT(3)
#define TCPC_MSG_HDR_INFO_PWR_ROLE BIT(0)
#define TCPC_MSG_HDR_INFO_REV_SHIFT 1
#define TCPC_MSG_HDR_INFO_REV_MASK 0x3
#define TCPC_RX_DETECT 0x2f
#define TCPC_RX_DETECT_HARD_RESET BIT(5)
#define TCPC_RX_DETECT_SOP BIT(0)
#define TCPC_RX_BYTE_CNT 0x30
#define TCPC_RX_BUF_FRAME_TYPE 0x31
#define TCPC_RX_HDR 0x32
#define TCPC_RX_DATA 0x34 /* through 0x4f */
#define TCPC_TRANSMIT 0x50
#define TCPC_TRANSMIT_RETRY_SHIFT 4
#define TCPC_TRANSMIT_RETRY_MASK 0x3
#define TCPC_TRANSMIT_TYPE_SHIFT 0
#define TCPC_TRANSMIT_TYPE_MASK 0x7
#define TCPC_TX_BYTE_CNT 0x51
#define TCPC_TX_HDR 0x52
#define TCPC_TX_DATA 0x54 /* through 0x6f */
#define TCPC_VBUS_VOLTAGE 0x70
#define TCPC_VBUS_SINK_DISCONNECT_THRESH 0x72
#define TCPC_VBUS_STOP_DISCHARGE_THRESH 0x74
#define TCPC_VBUS_VOLTAGE_ALARM_HI_CFG 0x76
#define TCPC_VBUS_VOLTAGE_ALARM_LO_CFG 0x78
#define TCPC_BMCIO_CTRL 0x90
#define TCPC_BMCIO_VBUS_DETECT_MASK BIT(1)
#define TCPC_BMCIO_VBUS_DETECT_ENABLE BIT(1)
#define TCPC_BMCIO_VBUS_DETECT_DISABLE 0
#define TCPC_BMCIO_24M_OSC_MASK BIT(0)
#define TCPC_BMCIO_ENABLE_24M_OSC BIT(0)
#define TCPC_BMCIO_DISABLE_24M_OSC 0
struct tcpci;
struct tcpci_data {
struct regmap *regmap;
int (*init)(struct tcpci *tcpci, struct tcpci_data *data);
int (*set_vconn)(struct tcpci *tcpci, struct tcpci_data *data,
bool enable);
int (*start_drp_toggling)(struct tcpci *tcpci, struct tcpci_data *data,
enum typec_cc_status cc);
};
struct tcpci *tcpci_register_port(struct udevice *dev, struct tcpci_data *data);
void tcpci_unregister_port(struct tcpci *tcpci);
int tcpci_get_voltage_fun(struct tcpci *tcpci);
int tcpci_get_current_fun(struct tcpci *tcpci);
int tcpci_get_online_fun(struct tcpci *tcpci);
irqreturn_t tcpci_irq(struct tcpci *tcpci);
#endif /* __LINUX_USB_TCPCI_H */

229
drivers/power/power_delivery/tcpci_husb311.c Executable file
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// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2021 Rockchip Co.,Ltd.
* Author: Wang Jie <dave.wang@rock-chips.com>
*
* Hynetek Husb311 Type-C Chip Driver
*/
#include <dm.h>
#include <i2c.h>
#include <asm/gpio.h>
#include <power/power_delivery/tcpm.h>
#include <power/power_delivery/power_delivery.h>
#include "tcpci.h"
#define HUSB311_VID 0x2E99
#define HUSB311_PID 0x0311
#define HUSB311_TCPC_I2C_RESET 0x9E
#define HUSB311_TCPC_SOFTRESET 0xA0
#define HUSB311_TCPC_FILTER 0xA1
#define HUSB311_TCPC_TDRP 0xA2
#define HUSB311_TCPC_DCSRCDRP 0xA3
#define HUSB311_I2C_RETRY_MAX_CNT 3
struct husb311_chip {
struct udevice *udev;
struct tcpci_data data;
struct tcpci *tcpci;
};
static int husb311_read16(struct husb311_chip *chip, unsigned int reg)
{
int ret = 0;
u8 buffer[2];
ret = dm_i2c_read(chip->udev, reg, buffer, 2);
if (ret < 0) {
printf("%s: cannot read %02x, ret=%d\n",
__func__, reg, ret);
return ret;
}
ret = ((buffer[1] << 8) & 0xFF00) + (buffer[0] & 0xFF);
return ret;
}
static int husb311_write8(struct husb311_chip *chip, unsigned int reg, u8 val)
{
int ret = 0;
int i;
for (i = 0; i < HUSB311_I2C_RETRY_MAX_CNT; i++) {
ret = dm_i2c_write(chip->udev, reg, &val, 1);
if (!ret)
break;
else
udelay(200);
}
if (ret)
printf("%s: cannot write 0x%02x to 0x%02x, ret=%d\n",
__func__, val, reg, ret);
return ret;
}
static int husb311_write16(struct husb311_chip *chip, unsigned int reg, u16 val)
{
int ret = 0;
u8 buffer[2];
buffer[0] = val & 0xFF;
buffer[1] = (val >> 8) & 0xFF;
ret = dm_i2c_write(chip->udev, reg, buffer, 2);
if (ret)
printf("%s: cannot write 0x%02x, len=%d, ret=%d\n",
__func__, reg, 2, ret);
return ret;
}
static struct husb311_chip *tdata_to_husb311(struct tcpci_data *tdata)
{
return container_of(tdata, struct husb311_chip, data);
}
static int husb311_sw_reset(struct husb311_chip *chip)
{
/* soft reset */
return husb311_write8(chip, HUSB311_TCPC_SOFTRESET, 0x01);
}
static int husb311_init(struct tcpci *tcpci, struct tcpci_data *tdata)
{
int ret;
struct husb311_chip *chip = tdata_to_husb311(tdata);
/* I2C reset : (val + 1) * 12.5ms */
ret = husb311_write8(chip, HUSB311_TCPC_I2C_RESET, 0x8F);
/* tTCPCfilter : (26.7 * val) us */
ret |= husb311_write8(chip, HUSB311_TCPC_FILTER, 0x0F);
/* tDRP : (51.2 + 6.4 * val) ms */
ret |= husb311_write8(chip, HUSB311_TCPC_TDRP, 0x04);
/* dcSRC.DRP : 33% */
ret |= husb311_write16(chip, HUSB311_TCPC_DCSRCDRP, 330);
if (ret)
printf("%s: fail to init registers(%d)\n", __func__, ret);
return ret;
}
static int husb311_check_revision(struct husb311_chip *chip)
{
int ret;
ret = husb311_read16(chip, TCPC_VENDOR_ID);
if (ret < 0) {
printf("%s: fail to read Vendor id(%d)\n", __func__, ret);
return ret;
}
if (ret != HUSB311_VID) {
printf("%s: vid is not correct, 0x%04x\n", __func__, ret);
return -ENODEV;
}
ret = husb311_read16(chip, TCPC_PRODUCT_ID);
if (ret < 0) {
printf("%s: fail to read Product id(%d)\n", __func__, ret);
return ret;
}
if (ret != HUSB311_PID) {
printf("%s: pid is not correct, 0x%04x\n", __func__, ret);
return -ENODEV;
}
return 0;
}
static int husb311_probe(struct udevice *dev)
{
int ret;
struct husb311_chip *chip = dev_get_priv(dev);
chip->udev = dev;
ret = husb311_check_revision(chip);
if (ret < 0) {
printf("%s: check vid/pid fail(%d)\n", __func__, ret);
return ret;
}
ret = husb311_sw_reset(chip);
if (ret) {
printf("%s: fail to soft reset, ret = %d\n", __func__, ret);
return ret;
}
chip->data.init = husb311_init;
chip->tcpci = tcpci_register_port(chip->udev, &chip->data);
if (IS_ERR(chip->tcpci))
return PTR_ERR(chip->tcpci);
return 0;
}
static int husb311_remove(struct udevice *dev)
{
struct husb311_chip *chip = dev_get_priv(dev);
int ret = 0;
printf("PD chip husb311 remove\n");
/* Disable chip interrupts before unregistering port */
ret = husb311_write16(chip, TCPC_ALERT_MASK, 0);
if (ret < 0)
return ret;
tcpci_unregister_port(chip->tcpci);
return 0;
}
static int husb311_get_voltage(struct udevice *dev)
{
struct husb311_chip *chip = dev_get_priv(dev);
return tcpci_get_voltage_fun(chip->tcpci);
}
static int husb311_get_current(struct udevice *dev)
{
struct husb311_chip *chip = dev_get_priv(dev);
return tcpci_get_current_fun(chip->tcpci);
}
static int husb311_get_online(struct udevice *dev)
{
struct husb311_chip *chip = dev_get_priv(dev);
return tcpci_get_online_fun(chip->tcpci);
}
static struct dm_power_delivery_ops husb311_ops = {
.get_voltage = husb311_get_voltage,
.get_current = husb311_get_current,
.get_online = husb311_get_online,
};
static const struct udevice_id husb311_ids[] = {
{ .compatible = "hynetek,husb311" },
{},
};
U_BOOT_DRIVER(husb311) = {
.name = "husb311",
.id = UCLASS_PD,
.of_match = husb311_ids,
.ops = &husb311_ops,
.probe = husb311_probe,
.remove = husb311_remove,
.priv_auto_alloc_size = sizeof(struct husb311_chip),
};
MODULE_AUTHOR("Wang Jie <dave.wang@rock-chips.com>");
MODULE_DESCRIPTION("Husb311 USB Type-C Port Controller Interface Driver");
MODULE_LICENSE("GPL v2");

3520
drivers/power/power_delivery/tcpm.c Executable file
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File diff suppressed because it is too large Load Diff

12
drivers/tpm/Kconfig
View File

@@ -145,6 +145,18 @@ config TPM2_TIS_SPI
to the device using the standard TPM Interface Specification (TIS)
protocol.
config TPM_Z32H330TC_SPI
bool "STMicroelectronics Z32H330TC SPI TPM"
depends on TPM_V2 && DM_SPI
---help---
This driver supports STMicroelectronics TPM devices connected on the SPI bus.
The usual tpm operations and the 'tpm' command can be used to talk
to the device using the standard TPM Interface Specification (TIS)
protocol
config CMD_MEASURED_BOOT
bool "Enable support for measured_boot to bootcmd"
endif # TPM_V2
endmenu

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