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add lightbox to developer's guide
Signed-off-by: Michel-FK <michel.stempin@funkey-project.com>
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Michel-FK
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@ -14,15 +14,15 @@ to the following electronic diagram, featuring 3 main blocks:
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- 1x 420 mAh 402540 LiPo battery, containing an active protection
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circuitry
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{: .lightbox}
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## 3D View
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A 3D rendering of the PCBA done in KiCAD produces the images below:
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{: .lightbox}
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{: .lightbox}
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## BOM
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@ -53,7 +53,7 @@ required to drive the speaker.
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Here is the corresponding schematic:
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{: .lightbox}
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We chose the right headphone channel HPOUTR that is fed to the audio
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amplifier **U2** through a coupling capacitor **C3**.
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@ -76,7 +76,7 @@ when required.
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Here is the corresponding main schematic for the buttons:
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{: .lightbox}
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The main component is of course the I/O expander **U1**, with the
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control signals to the CPU/PMIC on the north side.
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@ -107,7 +107,7 @@ user!
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The other buttons are wired in the same fashion:
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{: .lightbox}
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The "U", "L", "D", "R", "A", "B", "X" and "Y" buttons **S3**, **S4**,
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**S5**, **S6**, **S8**, **S9**, **S10** and **S11** are of the same
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@ -57,7 +57,7 @@ purpose.
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Here is the part of the schematics corresponding to the CPU core:
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{: .lightbox}
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## SoC Blocks
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@ -190,13 +190,13 @@ termination resistors on the data lines DQx.
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DDR2 or DDR3 DRAMs feature merged drivers and dynamic on-chip
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termination like this ("VDDQ/2" is labeled "SVREF" in our schematic):
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{: .lightbox}
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The V3s DDR2 DRAM has an active termination calibration circuitry and
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procedure called "_ZQ Calibration_" requiring an accurate 1% 240 Ω
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resistor **R11** connected internally like this:
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{: .lightbox}
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More information on the DDR2 DRAM ZQ Calibration subject can be found
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in this [Micron Application Note][14].
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@ -27,7 +27,7 @@ Meder MK24][1].
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Here is the corresponding schematics, already covered in the PMIC discussion:
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{: .lightbox}
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The global PMIC chip enable signal N_OE is activated by default
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through a 47kΩ resistor **R17** to GND, but the magnetic Reed switch
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@ -97,7 +97,7 @@ are used for much lower currents and much briefer periods (typically
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The last part of the FunKey schematics merely contains only decoupling
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capacitors:
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{: .lightbox}
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One exception is the Allwinner V3s CPU HPR/HPL circuit which features
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an RC-to-ground circuit between the amplifier and the preamplifier
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@ -19,7 +19,7 @@ Design][2].
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Here is the corresponding DRAM Power schematics:
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{: .lightbox}
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Nothing very fancy here: the SMPS chip **U4** has its required input
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filter capacitor **C37** and output capacitors **C65** and **C73**.
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@ -28,7 +28,7 @@ Their AXP20x products are highly-integrated PMICs that are optimized
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for applications requiring single-cell Li-battery (Li-Ion/Polymer),
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multiple output DC-DC converters and LDOs. Here is a block diagram:
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{: .lightbox}
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The AXP20x features:
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@ -88,7 +88,7 @@ schematics for using an AXP203 to supply the power to a V3s-based
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dashboard camera design. It follows closely the application diagram
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provided in the AXP20x datasheets:
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{: .lightbox}
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More hints are provided in our self-translated [V3s Hardware Design
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Guide][10] (page 7) too.
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@ -110,7 +110,7 @@ S** device only uses 2 out of the 5 integrated LDOs:
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Here are the PMIC schematics:
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{: .lightbox}
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These schematics may look intimidating and complex, but they are in
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fact just a collection of simple basic elements, and it is actually
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@ -82,7 +82,7 @@ a one-time tooling fee of ~ $800.
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The schematic is quite simple:
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{: .lightbox}
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The main component is of course the Hirose screen connector **J3**,
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with the following signals:
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@ -120,7 +120,7 @@ the screen, we need to drive these LEDs "from the high-side",
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i.e. between the +3V3 power supply and the LEDA pin, so a MOSFET-P
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transistor is necessary:
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{: .lightbox}
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As we want the backlight to be on by default, we need to drive it to
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GND by default: this is the role of **R7**. The role of **R5** is then
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@ -26,7 +26,7 @@ But a good summary of the requirements is given in the "[<i>AN10911
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SD(HC)-memory card and MMC Interface conditioning</i>][3]" application
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note from NXP, from which this schematic is taken:
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{: .lightbox}
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!!! Warning
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This schematic does not include details concerning card-supply and
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@ -80,7 +80,7 @@ an open-drain output mode, and its value should be undercut (down to
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The FunKey SD Card interface schematic is the following:
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{: .lightbox}
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{: align=left }
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@ -12,7 +12,7 @@ loging into the system over an UART.
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The Console schematic only requires a minimum of external components:
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{: .lightbox}
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Besides the 3-pin 1.27 mm (0.05") pitch header J1 that will not be
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mounted on standard products, there is only a single series resistor
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@ -22,7 +22,7 @@ user don't pull the chord straight.
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The USB schematic is the following:
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{: .lightbox}
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Before connecting 2 devices using an USB cable, they may be at
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completely different absolute voltages, and during cable insertion,
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