Merge branch 'master' into debugger

source/nec/nec.cpp

@@ -3922,9 +3922,19 @@ int nec_execute(int cycles)
    while(nec_ICount>0)
    {
 #if 0
-      uint8_t op = cpu_readmem20((I.sregs[CS]<<4) + I.ip);
-      printf("[%04x:%04xh] %02xh '%s' - I=%d\n", I.sregs[CS], I.ip,
-            op, instructionsName[op], I.IF);
+
+#define MK_LP(_seg, _off) (((_seg) << 4) + (_off))
+
+      if ( MK_LP(I.sregs[CS], I.ip) == 0x5E820 )
+      {
+         uint8_t op = cpu_readmem20((I.sregs[CS]<<4) + I.ip);
+
+         printf("AX = %04Xh - [%04X:%04Xh] = %04Xh\n", I.regs.w[AW], I.sregs[DS], 0x127f, cpu_readmem20(MK_LP(I.sregs[DS], 0x127f)));
+
+         printf("CS: %04Xh - DS: %04Xh - ES: %04Xh - SS: %04Xh\n", I.sregs[CS], I.sregs[DS], I.sregs[ES], I.sregs[SS]);
+         printf("[%04x:%04xh] %02xh '%s' - I=%d\n", I.sregs[CS], I.ip,
+               op, instructionsName[op], I.IF);
+      }
 #endif
       nec_instruction[FETCHOP]();
 //		nec_ICount++;

source/nec/nec.h

@@ -4,37 +4,6 @@
 
 #include "necintrf.h"
 
-typedef enum { ES, CS, SS, DS } SREGS;
-typedef enum { AW, CW, DW, BW, SP, BP, IX, IY } WREGS;
-typedef enum { AL,AH,CL,CH,DL,DH,BL,BH,SPL,SPH,BPL,BPH,IXL,IXH,IYL,IYH } BREGS;
-
-#pragma pack(1)
-typedef union
-{
-   /* eight general registers */
-   uint16_t w[8];    /* viewed as 16 bits registers */
-   uint8_t  b[16];   /* or as 8 bit registers */
-} necbasicregs;
-typedef struct
-{
-   necbasicregs regs;
-   uint16_t	sregs[4];
-
-   uint16_t	ip;
-
-   int32_t	SignVal;
-   int32_t  AuxVal, OverVal, ZeroVal, CarryVal, ParityVal; /* 0 or non-0 valued flags */
-
-   uint32_t	TF, IF, DF, MF; 	/* 0 or 1 valued flags */	/* OB[19.07.99] added Mode Flag V30 */
-
-   uint32_t	int_vector;
-   uint32_t	pending_irq;
-   uint32_t	nmi_state;
-   uint32_t	irq_state;
-   int     (*irq_callback)(int irqline);
-} nec_Regs;
-#pragma pack()
-
 #define NEC_NMI_INT_VECTOR 2
 
 /* Cpu types, steps of 8 to help the cycle count calculation */

source/nec/necintrf.h

@@ -2,7 +2,36 @@
 #ifndef __NECITRF_H_
 #define __NECITRF_H_
 
+typedef enum { ES, CS, SS, DS } SREGS;
+typedef enum { AW, CW, DW, BW, SP, BP, IX, IY } WREGS;
+typedef enum { AL,AH,CL,CH,DL,DH,BL,BH,SPL,SPH,BPL,BPH,IXL,IXH,IYL,IYH } BREGS;
 
+#pragma pack(1)
+typedef union
+{
+   /* eight general registers */
+   uint16_t w[8];    /* viewed as 16 bits registers */
+   uint8_t  b[16];   /* or as 8 bit registers */
+} necbasicregs;
+typedef struct
+{
+   necbasicregs regs;
+   uint16_t	sregs[4];
+
+   uint16_t	ip;
+
+   int32_t	SignVal;
+   int32_t  AuxVal, OverVal, ZeroVal, CarryVal, ParityVal; /* 0 or non-0 valued flags */
+
+   uint32_t	TF, IF, DF, MF; 	/* 0 or 1 valued flags */	/* OB[19.07.99] added Mode Flag V30 */
+
+   uint32_t	int_vector;
+   uint32_t	pending_irq;
+   uint32_t	nmi_state;
+   uint32_t	irq_state;
+   int     (*irq_callback)(int irqline);
+} nec_Regs;
+#pragma pack()
 
 enum
 {

source/nec/v30debug.cpp

@@ -0,0 +1,2 @@
+/* v30 debugger */
+