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69
files/docs/SNES-Interrupts.txt
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69
files/docs/SNES-Interrupts.txt
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Interrupt Processing Sequence
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The interrupt processing sequence is initiated as the direct result of hard-
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vare Abort, Interrupt Request, Non-Maskable Interrupt, or Reset inputs.
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The interrupt sequence can also be initiated as a result of the Break or
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Co-Processor instructions within the software. The following listings
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describe the function of each cycle in the interrupt processing sequence:
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Hardware Interrupt /ABORT, /IRQ, /NMI, /RES Inputs
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Cycle No.
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E = 0 E = 1 Address Data R/W SYNC VDA VPA VP Description
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1 1 PC X 1 1 1 1 1 Internal Operation
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2 2 PC X 1 0 0 0 1 Internal Operation
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3 [1] S PB 0 0 1 0 1 Write PB to Stack, S-1<>S
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4 3 S PCH [2] 0[3] 0 1 0 1 Write PCH to Stack, S-1<>S
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5 4 S PCL 12] 0[3] 0 1 0 1 Write PCL to Stack, S-1<>S
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6 5 S P [4] 0[3] 0 1 0 1 Write P to Stack, S-1<>S
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7 6 VL (VL) 1 0 1 0 0 Read Vector Low Byte,
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0->PD, 1->P1, OO->PB
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8 7 VH (VH) 1 0 1 0 0 Read Vector High 8yte
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Software Interrupt - BRK, COP Instructions
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Cycle No.
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E = 0 E = 1 Address Data R/W SYNC VDA VPA VP Description
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1 1 PC-2 X 1 1 1 1 1 Opcode
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2 2 PC-1 X 1 0 0 1 1 Signature
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3 111 S PB 0 0 1 0 1 Write PB to Stack, S-1<>S
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4 3 S PCH 0 0 1 0 1 Write PCH to Stack, S-1 - S
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5 4 S PCL 0 0 1 0 1 Write PCL to Stack, S-1<>S
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6 5 S P 0 0 1 0 1 Write P to Stack, S-1<>S
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7 6 VL (VL) 1 0 1 0 0 Read Vector Low Byte,
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0<>Po, 1<>Pl, 00<30>PB
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8 7 VH (VH) 1 0 1 0 0 Read Vector High Byte
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Notes:
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[1] Delete this cycle in Emulation mode.
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[2] Abort writes address of aborted opcode.
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[3] R/W remains in the high state during Reset.
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[4] In Emulation mode, bit 4 written to stack is changed to 0.
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Table 3. Vector Locations
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Emulation Native Priority
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Name Source (E = 1) (E = 0) Level
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ABORT Hardware 00FFF8,9 00FFE8,9 2
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BRK Software 00FFFE,F 00FFE6,7 N/A
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COP Software 00FFF4,5 00FFE4,5 N/A
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IRQ Hardware 00FFFE,F 00FFEE,F 4
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NMI Hardware 00FFFA,B 00FFEA,B 3
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RES Hardware 00FFFC.D 00FFFC,D 1
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161
files/docs/SNES-Memorymap.txt
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161
files/docs/SNES-Memorymap.txt
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SNES Memory Mapping
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by
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Duncanthrax of ShadowCraft
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Version: 1.0
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Date: August 28, 1997
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Introduction:
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This is a little document I'm throwing together as I go. It probably has a few innacuracies, but it's certainly better than nothing.
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I became frustrated with the lack of solid knowledge and documentation regarding memory in the SNES, all the other maps
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were very incomplete. So, since I'm building an emulator at the moment, I figured I'd write all this down for posterity.
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If you find anything in here that is wrong, or if you have an additions or questions, or suggestions... or if you want to help
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with the emulator, mail me at:
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odin@ccs.neu.edu
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Or check out ShadowCraft's web page at:
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http://shadowguild.home.ml.org
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Have fun, and I hope this is helpful.
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*---------------------------------------------------*
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SNES Memory Map in LoROM Mode (Mode 0x20):
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Bank: Address: Purpose:
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----- -------- --------
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00-3F 0000-1FFF Shadow RAM
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2000-5FFF Hardware Registers
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6000-7FFF Expansion RAM
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8000-FFFF 32k ROM Chunk
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40-7C 0000-7FFF 32k ROM Chunk
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8000-FFFF 32k ROM Chunk
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7D 0000-FFFF SRAM
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7E 0000-1FFF Shadow RAM
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2000-FFFF System RAM
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7F 0000-FFFF System RAM
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80-BF 0000-1FFF Shadow RAM
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2000-5FFF Hardware Registers
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6000-7FFF Expansion RAM
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8000-FFFF 32k ROM Chunk
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C0-FC 0000-7FFF 32k ROM Chunk
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8000-FFFF 32k ROM Chunk
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FD 0000-FFFF SRAM
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FE 0000-1FFF Shadow RAM
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2000-FFFF System RAM
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FF 0000-FFxx System RAM
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FFxx-FFFF Reset and NMI Vectors
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SNES Memory Map in HiROM Mode (Mode 0x21):
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Bank: Address: Purpose:
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----- -------- --------
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00-3F 0000-1FFF Shadow RAM
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2000-5FFF Hardware Registers
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6000-7FFF SRAM
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8000-FFFF 32k ROM Chunk
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40-7D 0000-FFFF 64k ROM Chunk
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7E 0000-1FFF Shadow RAM
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2000-FFFF System RAM
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7F 0000-FFFF System RAM
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80-BF 0000-1FFF Shadow RAM
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2000-5FFF Hardware Registers
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6000-7FFF SRAM
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8000-FFFF 32k ROM Chunk
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C0-FE 0000-FFFF 64k ROM Chunk
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FF 0000-FFxx 64k ROM Chunk
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FFxx-FFFF Reset and NMI Vectors
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*--------------------------------------------*
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Now that I've given you the overview of the memory layout, perhaps a little explanation would be in order.
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We'll start at 00.0000 and work our way up... in LoROM first, then HiROM - to avoid confusion.
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00-3F 0000-1FFF Shadow RAM
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What's going on here? Well, this is RAM that is the same in every bank up to and including 7E. It's the first
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8k of System RAM. So, if you write 0x42 to 00.1001, you'll read a 0x42 from 7E.1001. Simple, huh?
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00-3F 2000-5FFF Hardware Registers
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This is where you do graphics hardware calls, BIOS calls, DMA calls, and all that stuff. There are lots and
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lots of documents on this, all of them confusing. I may write one later on that clarifies a bunch of stuff, but
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for now I won't go into greater detail, as this is pretty straightforward... read and write values that interact
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with hardware.
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00-3F 6000-7FFF Expansion RAM
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This is one of those areas in which I draw a blank. I'm not certain where this RAM is supposed to map,
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whether it is part of system RAM or what. Anybody who wants to clarify the purpose of this area of RAM
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can feel free. I've seen at least two cartridges that access this area...
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00-3F 8000-FFFF 32k ROM Chunk
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40-7C 0000-7FFF 32k ROM Chunk
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8000-FFFF 32k ROM Chunk
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This bears a little explanation. When the LoROM is loaded into memory, this is where it is mapped
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(in a real SNES it isn't "loaded" at all - just mapped). The first 64 32k chunks are loaded into the upper half
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of banks 00-3F. Then, you continue at 40, mapping two (2!) 32k chunks in each bank from 40-7C. This
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should take care of an entire LoROM. I know that theoretically a LoROM could be slightly bigger than this,
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but I've never seen one that is...
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7D 0000-FFFF SRAM
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OK, this is pretty obvious. This is where the battery-backed SRAM on cartridges is mapped. Very simple.
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Most have 64kb. DOOM, I've heard, has 256kb. Copiers have 256kb. Simple.
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7E 0000-1FFF Shadow RAM
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2000-FFFF System RAM
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7F 0000-FFFF System RAM
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Also very simple. This is the SNES's 128k of RAM. There, that was easy, right?
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80-FF 0000-FFFF MIRROR!
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The upper area of the SNES's addressing space is for "Fast ROM". Games will use this area instead of
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the lower area (they're mapped exactly the same) when they want to run faster. The SNES gains 1Mhz
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of speed this way.
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The only thing that is different about the upper area is that the vectors for reset and NMI get stored in
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the FF.FFxx last 32 bytes...
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*-------------------------------------------*
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LoROM vs. HiROM!
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OK, this is the most interesting part of SNES mapping, and also the part where I'm most likely to get
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something wrong. As always, if this is incorrect or confusing, let me know!
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00-3F 0000-5FFF Same as LoROM
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00-3F 6000-7FFF 8k SRAM Chunk
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00-3F 8000-FFFF 32k ROM Chunk
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40-7D 0000-FFFF 64k ROM Chunk
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Ok, this is not too hard, with one caveat... the first 64 32k chunks of the HiROM cartridge get loaded
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into 00-3F, and then it REPEATS FROM THE BEGINNING starting at 40.0000, this time going in 64k
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chunks until the end of the file. Now, people are about to start yelling about how this doesn't leave
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room for the last 2 64k chunks of a 32mb ROM. Yes, I know... keep reading.
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7E-7F 0000-FFFF Same as LoROM
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Note 7D is no longer the SRAM, which is now in the expansion ram area.
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80-FD 0000-FFFF Same as LoROM
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FE-FF 0000-FFFF 64k ROM Chunk
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Aha! Here it is... the last two chunks of a 32mb ROM (i.e. Chrono Trigger, etc.) get loaded here.
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Remember as always that the last 16 bytes are for vectors, and you're all set!
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*--------------------------------------------*
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Ok kiddies! That was a quick tour through the SNES memory map. Tune in next time for
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"Dr. Duncanthrax teaches CPU!" - same Bat Time, same Bat Channel!
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99
files/docs/SNES-Memorymap2.txt
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99
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+=-=-=-=-=-=-=-=-=-=-=+
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| SNES Memory Mapping |
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| By: ]SiMKiN[ |
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| v1.0 |
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+=-=-=-=-=-=-=-=-=-=-=+
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<EFBFBD> LoROM: Mode 20
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<EFBFBD> HiROM: Mode 21
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<EFBFBD> FastROM's can execute at 3.58Mhz
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<EFBFBD> SlowROM's can only execute 2.68Mhz
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<20> The SNES lets you access ROM through bank $00 onwards and bank
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$80 onwards such that locations $00:8000 and $80:8000 are congruent,
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(they access the same locations.)
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<20> When accessing bank $00 onwards the 65816 runs at 2.68Mhz. However,
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when accessing bank $80 onwards the 65816 can run at 2.68Mhz or
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3.58Mhz depending on how you set bit 0 of $420D.
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+=========+=============+====================================+=========+
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| Bank | Offset | Definition | Shadow |
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+=========+=============+====================================+=========+
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| $00-$2f | $0000-$1fff | LowRAM, each bank is shadowed | $00-$3f |
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| | | From bank $7e | $7e |
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| | $2000-$2fff | PPU1, APU | $00-$3f |
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| | $3000-$3fff | SFX, DSP, etc. | $00-$3f |
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| | $4000-$41ff | Controller | $00-$3f |
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| | $4200-$5fff | PPU2, DMA, etc. | $00-$3f |
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| | $6000-$7fff | Reserved? | $00-$3f |
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| | $8000-$ffff | (Mode 20, 21 - ROM) | ------- |
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+---------+-------------+------------------------------------+---------+
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| $30-$3f | $0000-$1fff | LowRAM, each bank is shadowed | $00-$3f |
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| | | From bank $7e | $7e |
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| | $2000-$2fff | PPU1, APU | $00-$3f |
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| | $3000-$3fff | SFX, DSP, etc. | $00-$3f |
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| | $4000-$41ff | Controller | $00-$3f |
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| | $4200-$5fff | PPU2, DMA, etc. | $00-$3f |
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| | $6000-$7fff | (Mode 21 - SRAM) 256KBytes | ------- |
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| | $8000-$ffff | (Mode 20, 21 - ROM) | ------- |
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+---------+-------------+------------------------------------+---------+
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| $40-$6f | $0000-$7fff | (Mode 21 - ROM) | ------- |
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| | $8000-$ffff | (Mode 20, 21 - ROM) | ------- |
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+---------+-------------+------------------------------------+---------+
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| $70-$77 | $0000-$ffff | (Mode 20, 21 - SRAM) 256KBytes | ------- |
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+---------+-------------+------------------------------------+---------+
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| $78-$7d | $0000-$ffff | Never Used | ------- |
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+---------+-------------+------------------------------------+---------+
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| $7e | $0000-$1fff | LowRAM | $00-$3f |
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| | | Shadowed to banks $00-$3f | ------- |
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| | $2000-$7fff | HighRAM | ------- |
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| | $8000-$ffff | Expanded Ram | ------- |
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+---------+-------------+------------------------------------+---------+
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| $7f | $0000-$ffff | More Expanded RAM | ------- |
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+---------+-------------+------------------------------------+---------+
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| $80-$ef | $0000-$ffff | Mirror of $00-$6f | $00-$6f |
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+---------+-------------+------------------------------------+---------+
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| $f0-$ff | $0000-$ffff | (Mode 21 - ROM) | ------- |
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+=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-+
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<EFBFBD> ROM: The SNES ROM Image
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<EFBFBD> RAM: The SNES Work Memory (WRAM)
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LowRAM, HighRAM, & Expanded RAM
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All together = 128 Kilo-Bytes
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<EFBFBD> SRAM: Save RAM (Extra RAM added by Cart)
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The SNES only utilizes 256 Kilo-bits
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However 256 Kilo-Bytes are provided.
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<EFBFBD> APU: Audio Processing Unit
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SPC700, Inside which has a DSP
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<EFBFBD> PPU: Picture Processing Unit
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PPU1: 5c77-01
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PPU2: 5c78-03
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<EFBFBD> SFX: Super FX Cart Chip, by Nintendo
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<EFBFBD> DSP: Digital Signal Processing Cart Chip
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a.k.a. 'NEC mUPD77C25'
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<EFBFBD> Shadow: "Congruent Bank". Same meaning as Mirror.
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_________________________________________________
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.o(_Thanx to: Y0SHi, zsKnight, MrGrim, and MintaBoo_)o.
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