o start to do the mmio debug in asm
This commit is contained in:
David Voswinkel
parent
1075795ef4
commit
ef69ab4ab3
143
snes/irqtest/LoadGraphics.asm
Normal file
143
snes/irqtest/LoadGraphics.asm
Normal file
@ -0,0 +1,143 @@
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;============================================================================
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; Macros
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;============================================================================
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;============================================================================
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;LoadPalette - Macro that loads palette information into CGRAM
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;----------------------------------------------------------------------------
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; In: SRC_ADDR -- 24 bit address of source data,
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; START -- Color # to start on,
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; SIZE -- # of COLORS to copy
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;----------------------------------------------------------------------------
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; Out: None
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;----------------------------------------------------------------------------
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; Modifies: A,X
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; Requires: mem/A = 8 bit, X/Y = 16 bit
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;----------------------------------------------------------------------------
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.MACRO LoadPalette
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lda #\2
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sta $2121 ; Start at START color
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lda #:\1 ; Using : before the parameter gets its bank.
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ldx #\1 ; Not using : gets the offset address.
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ldy #(\3 * 2) ; 2 bytes for every color
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jsr DMAPalette
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.ENDM
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;============================================================================
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; LoadBlockToVRAM -- Macro that simplifies calling LoadVRAM to copy data to VRAM
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;----------------------------------------------------------------------------
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; In: SRC_ADDR -- 24 bit address of source data
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; DEST -- VRAM address to write to (WORD address!!)
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; SIZE -- number of BYTEs to copy
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;----------------------------------------------------------------------------
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; Out: None
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;----------------------------------------------------------------------------
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; Modifies: A, X, Y
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;----------------------------------------------------------------------------
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;LoadBlockToVRAM SRC_ADDRESS, DEST, SIZE
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; requires: mem/A = 8 bit, X/Y = 16 bit
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.MACRO LoadBlockToVRAM
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lda #$80
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sta $2115
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ldx #\2 ; DEST
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stx $2116 ; $2116: Word address for accessing VRAM.
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lda #:\1 ; SRCBANK
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ldx #\1 ; SRCOFFSET
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ldy #\3 ; SIZE
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jsr LoadVRAM
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.ENDM
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;============================================================================
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; Routines
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;============================================================================
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.BANK 0
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.ORG 0
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.SECTION "LoadVRAMCode" SEMIFREE
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;============================================================================
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; LoadVRAM -- Load data into VRAM
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;----------------------------------------------------------------------------
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; In: A:X -- points to the data
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; Y -- Number of bytes to copy (0 to 65535) (assumes 16-bit index)
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;----------------------------------------------------------------------------
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; Out: None
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;----------------------------------------------------------------------------
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; Modifies: none
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;----------------------------------------------------------------------------
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; Notes: Assumes VRAM address has been previously set!!
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;----------------------------------------------------------------------------
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LoadVRAM:
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pha
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phx
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phy
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phb
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php ; Preserve Registers
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sep #$20
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stx $4302 ; Store Data offset into DMA source offset
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sta $4304 ; Store data Bank into DMA source bank
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sty $4305 ; Store size of data block
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lda #$01
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sta $4300 ; Set DMA mode (word, normal increment)
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lda #$18 ; Set the destination register (VRAM write register)
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sta $4301
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lda #$01 ; Initiate DMA transfer (channel 1)
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sta $420B
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plp ; restore registers
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plb
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ply
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plx
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pla
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rts ; return
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;============================================================================
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.ENDS
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.BANK 0
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.ORG 0
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.SECTION "DMAPaletteCode" SEMIFREE
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;============================================================================
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; DMAPalette -- Load entire palette using DMA
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;----------------------------------------------------------------------------
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; In: A:X -- points to the data
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; Y -- Size of data
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;----------------------------------------------------------------------------
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; Out: None
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;----------------------------------------------------------------------------
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; Modifies: none
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;----------------------------------------------------------------------------
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DMAPalette:
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pha
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phx
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phb
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php ; Preserve Registers
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sep #$20
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stx $4302 ; Store data offset into DMA source offset
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sta $4304 ; Store data bank into DMA source bank
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sty $4305 ; Store size of data block
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stz $4300 ; Set DMA Mode (byte, normal increment)
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lda #$22 ; Set destination register ($2122 - CGRAM Write)
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sta $4301
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lda #$01 ; Initiate DMA transfer
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sta $420B
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plp ; Restore registers
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plb
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plx
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pla
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rts ; return from subroutine
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;============================================================================
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.ENDS
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33
snes/irqtest/Makefile
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33
snes/irqtest/Makefile
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@ -0,0 +1,33 @@
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#wla-65816 -o %1.asm %1.obj
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#wlalink -vr temp.prj %1.smc
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AS=wla-65816
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LD=wlalink
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OBJS=irqtest.o
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APP=irqtest.smc
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GFX=
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all: clean $(APP)
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run:
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zsnes $(APP)
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linkfile:
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echo "[objects]" > linkerfile.prj
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optixx.inc: optixx.pcx
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wine tools/pcx2snes.exe optixx.pcx -b2 -nOptixx -ooptixx.inc
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%.o: %.asm
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echo "$@" >> linkerfile.prj
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$(AS) -o $? $@
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$(APP): linkfile $(GFX) $(OBJS) $(GFX)
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$(LD) -vr linkerfile.prj $@
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clean:
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rm -vf $(APP) *.prj *.o
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30
snes/irqtest/debug.asm
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30
snes/irqtest/debug.asm
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@ -0,0 +1,30 @@
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.MACRO printf
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REP #$38 ; mem/A = 16 bit, X/Y = 16 bit
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SEP #$20
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lda.w str_NMI
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sta.w debug_pointer
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ldy #0
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jsr do_printf
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REP #$30 ; mem/A = 16 bit, X/Y = 16 bit
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SEP #$20
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.ENDM
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.define debug_pointer $0000
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.BANK 0
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.ORG 0
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.SECTION "debug" SEMIFREE
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do_printf:
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lda (debug_pointer),y ; get ascii text data
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sta $3000
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iny
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cpy #5
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bne do_printf
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rts
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.ENDs
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61
snes/irqtest/header.inc
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61
snes/irqtest/header.inc
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@ -0,0 +1,61 @@
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;------------------------------ Header File ---------------------------------
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; This is basically a combo of MarctheMER's and Neviksti's header files
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; Perhaps reading their's will also help your understanding of the header,
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; but I believe this will be the simplest method of defining your header,
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; as Marc's doesn't provide a full explanation, and Neviksti's can be
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; a bit more difficult for beginners (using the WLA directives is easier).
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;----------------------------------------------------------------------------
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;==LoRom== ; We'll get to HiRom some other time.
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.MEMORYMAP ; Begin describing the system architecture.
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SLOTSIZE $8000 ; The slot is $8000 bytes in size. More details on slots later.
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DEFAULTSLOT 0 ; There's only 1 slot in SNES, there are more in other consoles.
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SLOT 0 $8000 ; Define's Slot 0's starting address.
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.ENDME ; End MemoryMap definition
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.ROMBANKSIZE $8000 ; Every ROM bank is 32 KBytes in size
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.ROMBANKS 8 ; 2 Mbits - Tell WLA we want to use 8 ROM Banks
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.SNESHEADER
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ID "SNES" ; 1-4 letter string, just leave it as "SNES"
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NAME "SNES Tile Demo " ; Program Title - can't be over 21 bytes,
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; "123456789012345678901" ; use spaces for unused bytes of the name.
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SLOWROM
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LOROM
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CARTRIDGETYPE $00 ; $00 = ROM only, see WLA documentation for others
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ROMSIZE $08 ; $08 = 2 Mbits, see WLA doc for more..
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SRAMSIZE $00 ; No SRAM see WLA doc for more..
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COUNTRY $01 ; $01 = U.S. $00 = Japan, that's all I know
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LICENSEECODE $00 ; Just use $00
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VERSION $00 ; $00 = 1.00, $01 = 1.01, etc.
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.ENDSNES
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.SNESNATIVEVECTOR ; Define Native Mode interrupt vector table
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COP EmptyHandler
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BRK EmptyHandler
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ABORT EmptyHandler
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NMI EmptyHandler
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IRQ EmptyHandler
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.ENDNATIVEVECTOR
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.SNESEMUVECTOR ; Define Emulation Mode interrupt vector table
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COP EmptyHandler
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ABORT EmptyHandler
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NMI EmptyHandler
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RESET Start
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IRQBRK EmptyHandler
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.ENDEMUVECTOR
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.BANK 0 SLOT 0 ; Defines the ROM bank and the slot it is inserted in memory.
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.ORG 0 ; .ORG 0 is really $8000, because the slot starts at $8000
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.SECTION "EmptyVectors" SEMIFREE
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EmptyHandler:
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rti
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.ENDS
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.EMPTYFILL $00
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262
snes/irqtest/init.inc
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262
snes/irqtest/init.inc
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@ -0,0 +1,262 @@
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;------------------------------------------------------------------------
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;- Written by: Neviksti
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;- If you use my code, please share your creations with me
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;- as I am always curious :)
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;------------------------------------------------------------------------
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;----------------------------------------------------------------------------
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; InitSNES -- my "standard" initialization of SNES memory and registers
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;----------------------------------------------------------------------------
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.MACRO InitSNES
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sei ;disable interrupts
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clc ;switch to native mode
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xce
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REP #$38 ; mem/A = 16 bit, X/Y = 16 bit
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;decimal mode off
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LDX #$1FFF ;Setup the stack
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TXS ;Transfer Index X to Stack Pointer Register
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;do the rest of the initialization in a routine
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JSL $008000
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SEP #$20 ; mem/A = 8 bit
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.ENDM
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;----------------------------------------------------------------------------
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.BANK 0 SLOT 0
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.ORG 0
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.SECTION "InitializeSNESCode" FORCE
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InitializeSNES:
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PHK ;set Data Bank = Program Bank
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PLB
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LDA #$0000 ;set Direct Page = $0000
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TCD ;Transfer Accumulator to Direct Register
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LDX $1FFD ;we clear all the mem at one point ...
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STX $4372 ;so save the return address in a place that won't get overwritten
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LDX $1FFF
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STX $4374
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SEP #$20 ; mem/A = 8 bit
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REP #$10
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LDA #$8F
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STA $2100 ;turn screen off for now, set brightness to normal
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LDX #$2101
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_Loop00: ;regs $2101-$210C
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STZ $00,X ;set Sprite,Character,Tile sizes to lowest, and set addresses to $0000
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INX
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CPX #$210D
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BNE _Loop00
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_Loop01: ;regs $210D-$2114
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STZ $00,X ;Set all BG scroll values to $0000
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STZ $00,X
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INX
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CPX #$2115
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BNE _Loop01
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LDA #$80 ;reg $2115
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STA $2115 ; Initialize VRAM transfer mode to word-access, increment by 1
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STZ $2116 ;regs $2117-$2117
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STZ $2117 ;VRAM address = $0000
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;reg $2118-$2119
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;VRAM write register... don't need to initialize
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STZ $211A ;clear Mode7 setting
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LDX #$211B
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_Loop02: ;regs $211B-$2120
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STZ $00,X ;clear out the Mode7 matrix values
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STZ $00,X
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INX
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CPX #$2121
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BNE _Loop02
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;reg $2121 - Color address, doesn't need initilaizing
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;reg $2122 - Color data, is initialized later
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LDX #$2123
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_Loop03: ;regs $2123-$2133
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STZ $00,X ;turn off windows, main screens, sub screens, color addition,
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INX ;fixed color = $00, no super-impose (external synchronization),
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CPX #$2134 ;no interlaced mode, normal resolution
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BNE _Loop03
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;regs $2134-$2136 - multiplication result, no initialization needed
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;reg $2137 - software H/V latch, no initialization needed
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;reg $2138 - Sprite data read, no initialization needed
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;regs $2139-$213A - VRAM data read, no initialization needed
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;reg $213B - Color RAM data read, no initialization needed
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;regs $213C-$213D - H/V latched data read, no initialization needed
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STZ $213E ;reg $213E - might not be necesary, but selects PPU master/slave mode
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;reg $213F - PPU status flag, no initialization needed
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;reg $2140-$2143 - APU communication regs, no initialization required
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;reg $2180 - read/write WRAM register, no initialization required
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;reg $2181-$2183 - WRAM address, no initialization required
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;reg $4016-$4017 - serial JoyPad read registers, no need to initialize
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STZ $4200 ;reg $4200 - disable timers, NMI,and auto-joyread
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LDA #$FF
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STA $4201 ;reg $4201 - programmable I/O write port, initalize to allow reading at in-port
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;regs $4202-$4203 - multiplication registers, no initialization required
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;regs $4204-$4206 - division registers, no initialization required
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;regs $4207-$4208 - Horizontal-IRQ timer setting, since we disabled this, it is OK to not init
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;regs $4209-$420A - Vertical-IRQ timer setting, since we disabled this, it is OK to not init
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STZ $420B ;reg $420B - turn off all general DMA channels
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STZ $420C ;reg $420C - turn off all H-MA channels
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STZ $420D ;reg $420D - ROM access time to slow (2.68Mhz)
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LDA $4210 ;reg $4210 - NMI status, reading resets
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;reg $4211 - IRQ status, no need to initialize
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;reg $4212 - H/V blank and JoyRead status, no need to initialize
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;reg $4213 - programmable I/O inport, no need to initialize
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;reg $4214-$4215 - divide results, no need to initialize
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;reg $4216-$4217 - multiplication or remainder results, no need to initialize
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;regs $4218-$421f - JoyPad read registers, no need to initialize
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;regs $4300-$437F
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;no need to intialize because DMA was disabled above
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;also, we're not sure what all of the registers do, so it is better to leave them at
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;their reset state value
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JSR ClearVRAM ;Reset VRAM
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JSR ClearPalette ;Reset colors
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;**** clear Sprite tables ********
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STZ $2102 ;sprites initialized to be off the screen, palette 0, character 0
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STZ $2103
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LDX #$0080
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LDA #$F0
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_Loop08:
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STA $2104 ;set X = 240
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STA $2104 ;set Y = 240
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STZ $2104 ;set character = $00
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STZ $2104 ;set priority=0, no flips
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DEX
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BNE _Loop08
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LDX #$0020
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_Loop09:
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STZ $2104 ;set size bit=0, x MSB = 0
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DEX
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BNE _Loop09
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;**** clear WRAM ********
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STZ $2181 ;set WRAM address to $000000
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STZ $2182
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STZ $2183
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LDX #$8008
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STX $4300 ;Set DMA mode to fixed source, BYTE to $2180
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LDX #wram_fill_byte
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STX $4302 ;Set source offset
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LDA #:wram_fill_byte
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STA $4304 ;Set source bank
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LDX #$0000
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STX $4305 ;Set transfer size to 64k bytes
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LDA #$01
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STA $420B ;Initiate transfer
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LDA #$01 ;now set the next 64k bytes
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STA $420B ;Initiate transfer
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PHK ;make sure Data Bank = Program Bank
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PLB
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CLI ;enable interrupts again
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LDX $4372 ;get our return address...
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STX $1FFD
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LDA $4374
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STA $1FFF
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RTL
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wram_fill_byte:
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.db $00
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;----------------------------------------------------------------------------
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; ClearVRAM -- Sets every byte of VRAM to zero
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; In: None
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; Out: None
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; Modifies: flags
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;----------------------------------------------------------------------------
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ClearVRAM:
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pha
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phx
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php
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REP #$30 ; mem/A = 8 bit, X/Y = 16 bit
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SEP #$20
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LDA #$80
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STA $2115 ;Set VRAM port to word access
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LDX #$1809
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STX $4300 ;Set DMA mode to fixed source, WORD to $2118/9
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LDX #$0000
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STX $2116 ;Set VRAM port address to $0000
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STX $0000 ;Set $00:0000 to $0000 (assumes scratchpad ram)
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STX $4302 ;Set source address to $xx:0000
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LDA #$00
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STA $4304 ;Set source bank to $00
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LDX #$FFFF
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STX $4305 ;Set transfer size to 64k-1 bytes
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LDA #$01
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STA $420B ;Initiate transfer
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STZ $2119 ;clear the last byte of the VRAM
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plp
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plx
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pla
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RTS
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;----------------------------------------------------------------------------
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; ClearPalette -- Reset all palette colors to zero
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; In: None
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; Out: None
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||||
; Modifies: flags
|
||||
;----------------------------------------------------------------------------
|
||||
ClearPalette:
|
||||
PHX
|
||||
PHP
|
||||
REP #$30 ; mem/A = 8 bit, X/Y = 16 bit
|
||||
SEP #$20
|
||||
|
||||
STZ $2121
|
||||
LDX #$0100
|
||||
ClearPaletteLoop:
|
||||
STZ $2122
|
||||
STZ $2122
|
||||
DEX
|
||||
BNE ClearPaletteLoop
|
||||
|
||||
PLP
|
||||
PLX
|
||||
RTS
|
||||
|
||||
.ENDS
|
||||
117
snes/irqtest/irqtest.asm
Normal file
117
snes/irqtest/irqtest.asm
Normal file
@ -0,0 +1,117 @@
|
||||
;============================================================================
|
||||
; Includes
|
||||
;============================================================================
|
||||
|
||||
;== Include MemoryMap, Vector Table, and HeaderInfo ==
|
||||
.INCLUDE "header.inc"
|
||||
|
||||
;== Include SNES Initialization routines ==
|
||||
.INCLUDE "init.inc"
|
||||
.INCLUDE "LoadGraphics.asm"
|
||||
.INCLUDE "debug.asm"
|
||||
|
||||
;============================================================================
|
||||
; Main Code
|
||||
;============================================================================
|
||||
|
||||
.BANK 0 SLOT 0
|
||||
.ORG 0
|
||||
.SECTION "MainCode"
|
||||
|
||||
Start:
|
||||
InitSNES ; Clear registers, etc.
|
||||
|
||||
; Load Palette for our tiles
|
||||
LoadPalette OptixxPalette, 0, 16
|
||||
|
||||
; Load Tile data to VRAM
|
||||
;LoadBlockToVRAM TilesData, $0000, $0020 ; 2 tiles, 2bpp, = 32 bytes
|
||||
;LoadBlockToVRAM OptixxData, $0000, 0xa00 ; 160 tiles, 2bpp, = 2560 bytes
|
||||
;LoadBlockToVRAM OptixxData, $0000, 0x1e00 ; 480 tiles, 2bpp, = 7680 bytes
|
||||
LoadBlockToVRAM OptixxData, $0000, 0x3c00 ; 960 tiles, 2bpp, = 15360 bytes
|
||||
|
||||
lda #$80
|
||||
sta $2115
|
||||
;ldx #$0800 ; 5AF
|
||||
ldx #$4000 ; 5AF
|
||||
stx $2116
|
||||
|
||||
ldx #$0
|
||||
Start_do:
|
||||
stx $2118
|
||||
inx
|
||||
cpx #960
|
||||
bne Start_do
|
||||
|
||||
; Setup Video modes and other stuff, then turn on the screen
|
||||
jsr SetupVideo
|
||||
|
||||
lda #65
|
||||
sta $3000
|
||||
lda #66
|
||||
sta $3000
|
||||
lda #67
|
||||
sta $3000
|
||||
|
||||
printf
|
||||
|
||||
Infinity:
|
||||
jmp Infinity ; bwa hahahahaha
|
||||
|
||||
|
||||
;============================================================================
|
||||
; SetupVideo -- Sets up the video mode and tile-related registers
|
||||
;----------------------------------------------------------------------------
|
||||
; In: None
|
||||
;----------------------------------------------------------------------------
|
||||
; Out: None
|
||||
;----------------------------------------------------------------------------
|
||||
SetupVideo:
|
||||
php
|
||||
|
||||
lda #$00
|
||||
sta $2105 ; Set Video mode 0, 8x8 tiles, 4 color BG1/BG2/BG3/BG4
|
||||
|
||||
;lda #$08 ; Set BG1's Tile Map offset to $0800 (Word address)
|
||||
lda #$40 ; Set BG1's Tile Map offset to $2000 (Word address)
|
||||
sta $2107 ; And the Tile Map size to 32x32
|
||||
|
||||
stz $210B ; Set BG1's Character VRAM offset to $0000 (word address)
|
||||
|
||||
lda #$01 ; Enable BG1
|
||||
sta $212C
|
||||
|
||||
lda #$FF
|
||||
sta $210E
|
||||
sta $210E
|
||||
|
||||
lda #$0F
|
||||
sta $2100 ; Turn on screen, full Brightness
|
||||
|
||||
plp
|
||||
rts
|
||||
|
||||
|
||||
str_COP:
|
||||
.db "COP\n"
|
||||
str_ABORT:
|
||||
.db "ABORT\n"
|
||||
str_NMI:
|
||||
.db "NMI\n"
|
||||
str_RESET:
|
||||
.db "RESET\n"
|
||||
str_IRQBRK:
|
||||
.db "IRQBRK\n"
|
||||
|
||||
|
||||
;============================================================================
|
||||
.ENDS
|
||||
|
||||
;============================================================================
|
||||
; Character Data
|
||||
;============================================================================
|
||||
|
||||
.BANK 0 SLOT 0
|
||||
.SECTION "CharacterData02"
|
||||
.INCLUDE "optixx.inc"
|
||||
.ENDS
|
||||
969
snes/irqtest/optixx.inc
Normal file
969
snes/irqtest/optixx.inc
Normal file
@ -0,0 +1,969 @@
|
||||
; Created with eKid's pcx2snes converter ;
|
||||
|
||||
OptixxData:
|
||||
.db $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00
|
||||
.db $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00
|
||||
.db $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00
|
||||
.db $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00
|
||||
.db $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00
|
||||
.db $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00
|
||||
.db $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00
|
||||
.db $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00
|
||||
.db $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00
|
||||
.db $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00
|
||||
.db $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00
|
||||
.db $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00
|
||||
.db $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00
|
||||
.db $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00
|
||||
.db $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00
|
||||
.db $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00
|
||||
.db $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00
|
||||
.db $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00
|
||||
.db $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00
|
||||
.db $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00
|
||||
.db $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00
|
||||
.db $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00
|
||||
.db $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00
|
||||
.db $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00
|
||||
.db $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00
|
||||
.db $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00
|
||||
.db $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00
|
||||
.db $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00
|
||||
.db $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00
|
||||
.db $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00
|
||||
.db $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00
|
||||
.db $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00
|
||||
.db $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00
|
||||
.db $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00
|
||||
.db $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00
|
||||
.db $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00
|
||||
.db $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00
|
||||
.db $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00
|
||||
.db $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00
|
||||
.db $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00
|
||||
.db $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00
|
||||
.db $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00
|
||||
.db $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00
|
||||
.db $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00
|
||||
.db $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00
|
||||
.db $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00
|
||||
.db $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00
|
||||
.db $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00
|
||||
.db $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00
|
||||
.db $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00
|
||||
.db $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00
|
||||
.db $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00
|
||||
.db $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00
|
||||
.db $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00
|
||||
.db $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00
|
||||
.db $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00
|
||||
.db $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00
|
||||
.db $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00
|
||||
.db $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00
|
||||
.db $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00
|
||||
.db $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00
|
||||
.db $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00
|
||||
.db $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00
|
||||
.db $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00
|
||||
.db $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00
|
||||
.db $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00
|
||||
.db $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00
|
||||
.db $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00
|
||||
.db $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00
|
||||
.db $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00
|
||||
.db $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00
|
||||
.db $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00
|
||||
.db $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00
|
||||
.db $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00
|
||||
.db $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00
|
||||
.db $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00
|
||||
.db $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00
|
||||
.db $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00
|
||||
.db $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00
|
||||
.db $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00
|
||||
.db $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00
|
||||
.db $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00
|
||||
.db $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00
|
||||
.db $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00
|
||||
.db $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00
|
||||
.db $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00
|
||||
.db $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00
|
||||
.db $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00
|
||||
.db $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00
|
||||
.db $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00
|
||||
.db $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00
|
||||
.db $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00
|
||||
.db $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00
|
||||
.db $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00
|
||||
.db $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00
|
||||
.db $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00
|
||||
.db $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00
|
||||
.db $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00
|
||||
.db $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00
|
||||
.db $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00
|
||||
.db $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00
|
||||
.db $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00
|
||||
.db $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00
|
||||
.db $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00
|
||||
.db $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00
|
||||
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|
||||
.db $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00
|
||||
.db $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00
|
||||
.db $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00
|
||||
.db $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00
|
||||
.db $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00
|
||||
.db $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00
|
||||
.db $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00
|
||||
.db $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00
|
||||
.db $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00
|
||||
.db $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00
|
||||
.db $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00
|
||||
.db $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00
|
||||
.db $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00
|
||||
|
||||
OptixxPalette:
|
||||
.db $00, $00, $10, $42, $00, $00, $00, $00
|
||||
|
||||
; 960 tiles (0 spaces)
|
||||
; 15360 bytes
|
||||
BIN
snes/irqtest/optixx.pcx
Normal file
BIN
snes/irqtest/optixx.pcx
Normal file
Binary file not shown.
@ -27,7 +27,7 @@ void int2hex(unsigned long number, char *buf,word size)
|
||||
|
||||
}
|
||||
|
||||
void writeln(char *buffer,word y){
|
||||
void printDebugScreen(char *buffer,word y){
|
||||
char i;
|
||||
waitForVBlank();
|
||||
for(i=0; i<32; i++) {
|
||||
@ -36,6 +36,11 @@ void writeln(char *buffer,word y){
|
||||
}
|
||||
}
|
||||
|
||||
void printf(char *buffer){
|
||||
while(*buffer)
|
||||
*(byte*) 0x3000=*buffer++;
|
||||
}
|
||||
|
||||
void enableDebugScreen(void){
|
||||
VRAMLoad((word) debugFont_pic, 0x5000, 2048);
|
||||
CGRAMLoad((word) debugFont_pal, (byte) 0x00, (word) 16);
|
||||
|
||||
@ -1,5 +1,6 @@
|
||||
void initDebugMap(void);
|
||||
void debug(void);
|
||||
void int2hex(unsigned long i, char *buf,word size);
|
||||
void writeln(char* line,word y);
|
||||
void enableDebugScreen(void);
|
||||
void printDebugScreen(char* line,word y);
|
||||
void enableDebugScreen(void);
|
||||
void printf(char* line);
|
||||
|
||||
@ -29,7 +29,7 @@ void main(void) {
|
||||
word crc01;
|
||||
word crc02;
|
||||
padStatus pad1;
|
||||
char line_header[32] = "OK";
|
||||
char line_header[32] = "OK2";
|
||||
char packet[4] = "TEST";
|
||||
initInternalRegisters();
|
||||
|
||||
@ -39,13 +39,10 @@ void main(void) {
|
||||
*(byte*) 0x2100 = 0x0f; // enable background
|
||||
|
||||
enableDebugScreen();
|
||||
writeln(line_header,0);
|
||||
|
||||
for (i=0;i<4;i++){
|
||||
*(byte*) 0x3000=packet[i];
|
||||
*(byte*) 0x700010=packet[i];
|
||||
}
|
||||
//writeln(line_header,1);
|
||||
printDebugScreen(line_header,0);
|
||||
printf("Debugging console test\n");
|
||||
printf("test me\n");
|
||||
printDebugScreen(line_header,1);
|
||||
|
||||
while(1){
|
||||
while(!pad1.start) {
|
||||
|
||||
@ -22,13 +22,19 @@ void CMMIO::reset() {
|
||||
|
||||
uint8 CMMIO::mmio_read(unsigned addr) {
|
||||
addr &= 0xffff;
|
||||
printf("CMMIO::mmio_read 0x%x",addr);
|
||||
//printf("CMMIO::mmio_read 0x%x",addr);
|
||||
return cpu.regs.mdr;
|
||||
}
|
||||
|
||||
void CMMIO::mmio_write(unsigned addr, uint8 data) {
|
||||
addr &= 0xffff;
|
||||
printf("CMMIO::mmio_write 0x%x 0x%x",addr,data);
|
||||
//printf("CMMIO::mmio_write 0x%04x 0x%02x (%i)\n",addr,data,data);
|
||||
//fflush(stdout);
|
||||
/* debug to stderr */
|
||||
if (addr == 0x3000){
|
||||
fprintf(stderr,"%c",data);
|
||||
fflush(stderr);
|
||||
}
|
||||
}
|
||||
|
||||
CMMIO::CMMIO() {
|
||||
|
||||
@ -483,11 +483,9 @@ void sCPU::mmio_write(unsigned addr, uint8 data) {
|
||||
port_write(addr & 3, data);
|
||||
return;
|
||||
}
|
||||
printf("sCPU::mmio_write 0x%x 0x%x",addr,data);
|
||||
|
||||
/*custom area*/
|
||||
if((addr & 0xff00) == 0x3000) { //$3000-$30ff
|
||||
printf("sCPU::mmio_write 0x%x 0x%x",addr,data);
|
||||
return;
|
||||
}
|
||||
|
||||
|
||||
@ -15,12 +15,12 @@ namespace memory {
|
||||
|
||||
uint8 UnmappedMemory::read(unsigned) { return cpu.regs.mdr; }
|
||||
void UnmappedMemory::write(unsigned addr, uint8 val) {
|
||||
printf("UnmappedMemory::write 0x%x 0x%x\n",addr,val);
|
||||
//printf("UnmappedMemory::write 0x%x 0x%x\n",addr,val);
|
||||
}
|
||||
|
||||
uint8 UnmappedMMIO::mmio_read(unsigned) { return cpu.regs.mdr; }
|
||||
void UnmappedMMIO::mmio_write(unsigned addr, uint8 val) {
|
||||
printf("UnmappedMemory::write 0x%x 0x%x\n",addr,val);
|
||||
//printf("UnmappedMemory::write 0x%x 0x%x\n",addr,val);
|
||||
|
||||
}
|
||||
|
||||
@ -41,7 +41,7 @@ uint8 MMIOAccess::read(unsigned addr) {
|
||||
|
||||
void MMIOAccess::write(unsigned addr, uint8 data) {
|
||||
|
||||
printf("MMIOAccess::write 0x%x %x\n",addr,data);
|
||||
//printf("MMIOAccess::write 0x%x %x\n",addr,data);
|
||||
mmio[(addr - 0x2000) & 0x3fff]->mmio_write(addr, data);
|
||||
}
|
||||
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user