fix timing again
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7b361889be
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150384fba3
@ -131,7 +131,7 @@ int main(void) {
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snes_reset(1);
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uart_init();
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// sei(); // interrupts are bad for now, resets the poor AVR when inserting SD card
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sei(); // suspected to reset the AVR when inserting an SD card
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_delay_ms(100);
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disk_init();
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snes_init();
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@ -193,7 +193,7 @@ parameter STATE_9 = 10'b1000000000;
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reg [9:0] STATE;
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reg [3:0] STATEIDX;
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reg STATE_RESET, CYCLE_RESET, CYCLE_RESET_ACK;
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reg [1:0] CYCLE_RESET;
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reg SRAM_WE_MASK;
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reg SRAM_OE_MASK;
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@ -225,8 +225,7 @@ reg SNES_DATABUS_DIR_BUF;
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assign MODE = !AVR_ENA ? MODE_AVR : MODE_ARRAY[STATEIDX];
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initial begin
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CYCLE_RESET = 0;
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CYCLE_RESET_ACK = 0;
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CYCLE_RESET = 2'b0;
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STATE = STATE_9;
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STATEIDX = 9;
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@ -249,10 +248,10 @@ initial begin
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SRAM_OE_ARRAY[2'b10] = 10'b0000011111;
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SRAM_OE_ARRAY[2'b11] = 10'b0000000000;
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SNES_DATA_TO_MEM_ARRAY[1'b0] = 10'b1000000000;
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SNES_DATA_TO_MEM_ARRAY[1'b0] = 10'b0010000000;
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SNES_DATA_TO_MEM_ARRAY[1'b1] = 10'b0000000000;
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AVR_DATA_TO_MEM_ARRAY[1'b0] = 10'b0000010000;
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AVR_DATA_TO_MEM_ARRAY[1'b0] = 10'b0000100000;
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AVR_DATA_TO_MEM_ARRAY[1'b1] = 10'b0000000000;
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SRAM_DATA_TO_SNES_MEM_ARRAY[1'b0] = 10'b0000000000;
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@ -268,14 +267,12 @@ end
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// the minimum of 6 SNES cycles to get everything done.
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// we have 24 internal cycles to work with. (CLKIN * 4)
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reg [1:0] CYCLE_RESET;
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always @(posedge CLK2) begin
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CYCLE_RESET <= {CYCLE_RESET[0], SNES_RW_start};
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end
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always @(posedge CLK2) begin
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if (CYCLE_RESET[1]) begin
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if (SNES_RW_start) begin
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STATE <= STATE_0;
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SNES_READ_CYCLE <= SNES_READ;
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SNES_WRITE_CYCLE <= SNES_WRITE;
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