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FPGA: Adjust Cx4 timing to new master clock rate

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This commit is contained in:
Maximilian Rehkopf 2012-07-09 02:13:44 +02:00
parent 7df6909266
commit 60d7a08117
1 changed files with 5 additions and 5 deletions
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10
verilog/sd2snes_cx4/cx4.v
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@ -752,21 +752,21 @@ always @(posedge CLK) begin
cpu_op <= cpu_op_w; cpu_op <= cpu_op_w;
casex(cpu_op_w[15:11]) casex(cpu_op_w[15:11])
5'b00x01, 5'b00x10, 5'b00100, 5'b00111: begin 5'b00x01, 5'b00x10, 5'b00100, 5'b00111: begin
cpu_wait <= 8'h08; cpu_wait <= 8'h07;
CPU_STATE <= ST_CPU_4; CPU_STATE <= ST_CPU_4;
end end
5'b01110, 5'b01101, 5'b11101: begin 5'b01110, 5'b01101, 5'b11101: begin
cpu_wait <= 8'h03; cpu_wait <= 8'h03;
CPU_STATE <= ST_CPU_4; CPU_STATE <= ST_CPU_4;
end end
5'b10011: begin /*5'b10011: begin
cpu_wait <= 8'h03; cpu_wait <= 8'h02;
CPU_STATE <= ST_CPU_4; CPU_STATE <= ST_CPU_4;
end end
5'b01000: begin 5'b01000: begin
cpu_wait <= 8'h13; cpu_wait <= 8'h0e;
CPU_STATE <= ST_CPU_4; CPU_STATE <= ST_CPU_4;
end end*/
default: begin default: begin
cpu_wait <= 8'h00; cpu_wait <= 8'h00;
CPU_STATE <= ST_CPU_0; CPU_STATE <= ST_CPU_0;