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Merge branch 'cx4' into develop

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This commit is contained in:
ikari 2011-11-01 22:04:59 +01:00
commit 60efa60bb4
32 changed files with 7585 additions and 44 deletions
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1
src/fpga_spi.h
View File

@ -50,6 +50,7 @@
#define FPGA_SPI_FAST() spi_set_speed(SPI_SPEED_FPGA_FAST)
#define FPGA_SPI_SLOW() spi_set_speed(SPI_SPEED_FPGA_SLOW)
#define FEAT_CX4 (1 << 4)
#define FEAT_MSU1 (1 << 3)
#define FEAT_SRTC (1 << 2)
#define FEAT_ST0010 (1 << 1)

43
src/memory.c
View File

@ -191,7 +191,14 @@ uint32_t load_rom(uint8_t* filename, uint32_t base_addr, uint8_t flags) {
}
filesize = file_handle.fsize;
smc_id(&romprops);
file_close();
/* reconfigure FPGA if necessary */
if(romprops.fpga_conf) {
printf("reconfigure FPGA with %s...\n", romprops.fpga_conf);
fpga_pgm((uint8_t*)romprops.fpga_conf);
}
set_mcu_addr(base_addr);
file_open(filename, FA_READ);
f_lseek(&file_handle, romprops.offset);
for(;;) {
ff_sd_offload=1;
@ -226,18 +233,15 @@ uint32_t load_rom(uint8_t* filename, uint32_t base_addr, uint8_t flags) {
sram_writebyte(0xfc, rombase+0xd5);
set_fpga_time(0x0220110301180530LL);
}
if(romprops.has_dspx) {
printf("DSPx game. Loading firmware image %s...\n", romprops.necdsp_fw);
if(romprops.has_st0010) {
load_dspx(romprops.necdsp_fw, 1);
} else {
load_dspx(romprops.necdsp_fw, 0);
if(file_res && romprops.necdsp_fw == DSPFW_1) {
load_dspx(DSPFW_1B, 0);
}
if(romprops.has_dspx || romprops.has_cx4) {
printf("DSPx game. Loading firmware image %s...\n", romprops.dsp_fw);
load_dspx(romprops.dsp_fw, romprops.fpga_features);
/* fallback to DSP1B firmware if DSP1.bin is not present */
if(file_res && romprops.dsp_fw == DSPFW_1) {
load_dspx(DSPFW_1B, romprops.fpga_features);
}
if(file_res) {
snes_menu_errmsg(MENU_ERR_NODSP, (void*)romprops.necdsp_fw);
snes_menu_errmsg(MENU_ERR_NODSP, (void*)romprops.dsp_fw);
}
}
uint32_t rammask;
@ -494,22 +498,29 @@ uint64_t sram_gettime(uint32_t base_addr) {
return result & 0x00ffffffffffffffLL;
}
void load_dspx(const uint8_t *filename, uint8_t st0010) {
void load_dspx(const uint8_t *filename, uint8_t coretype) {
UINT bytes_read;
DWORD filesize;
uint16_t word_cnt;
uint8_t wordsize_cnt = 0;
uint16_t sector_remaining = 0;
uint16_t sector_cnt = 0;
uint16_t pgmsize = 2048;
uint16_t datsize;
uint16_t pgmsize = 0;
uint16_t datsize = 0;
uint32_t pgmdata = 0;
uint16_t datdata = 0;
if(st0010) {
if(coretype & FEAT_ST0010) {
datsize = 1536;
} else {
pgmsize = 2048;
} else if (coretype & FEAT_DSPX) {
datsize = 1024;
pgmsize = 2048;
} else if (coretype & FEAT_CX4) {
datsize = 0;
pgmsize = 1024; /* Cx4 data ROM */
} else {
printf("load_dspx: unknown core (%02x)!\n", coretype);
}
file_open((uint8_t*)filename, FA_READ);
@ -539,7 +550,7 @@ void load_dspx(const uint8_t *filename, uint8_t st0010) {
}
wordsize_cnt = 0;
if(st0010) {
if(coretype & FEAT_ST0010) {
file_seek(0xc000);
sector_remaining = 0;
}

24
src/smc.c
View File

@ -83,7 +83,9 @@ void smc_id(snes_romprops_t* props) {
props->has_dspx = 0;
props->has_st0010 = 0;
props->has_cx4 = 0;
props->fpga_features = 0;
props->fpga_conf = NULL;
for(uint8_t num = 0; num < 6; num++) {
if(!file_readblock(header, hdr_addr[num], sizeof(snes_header_t))
|| file_res) {
@ -144,39 +146,45 @@ void smc_id(snes_romprops_t* props) {
props->mapper_id = 0;
if(header->map == 0x31 && (header->carttype == 0x03 || header->carttype == 0x05)) {
props->has_dspx = 1;
props->necdsp_fw = DSPFW_1B;
props->dsp_fw = DSPFW_1B;
props->fpga_features |= FEAT_DSPX;
}
break;
case 0x20: /* LoROM */
props->mapper_id = 1;
if ((header->map == 0x20 && header->carttype == 0x03) ||
if (header->map == 0x20 && header->carttype == 0xf3) {
props->has_cx4 = 1;
props->dsp_fw = CX4FW;
props->fpga_conf = FPGA_CX4;
props->fpga_features |= FEAT_CX4;
}
else if ((header->map == 0x20 && header->carttype == 0x03) ||
(header->map == 0x30 && header->carttype == 0x05 && header->licensee != 0xb2)) {
props->has_dspx = 1;
props->fpga_features |= FEAT_DSPX;
// Pilotwings uses DSP1 instead of DSP1B
if(!memcmp(header->name, "PILOTWINGS", 10)) {
props->necdsp_fw = DSPFW_1;
props->dsp_fw = DSPFW_1;
} else {
props->necdsp_fw = DSPFW_1B;
props->dsp_fw = DSPFW_1B;
}
} else if (header->map == 0x20 && header->carttype == 0x05) {
props->has_dspx = 1;
props->necdsp_fw = DSPFW_2;
props->dsp_fw = DSPFW_2;
props->fpga_features |= FEAT_DSPX;
} else if (header->map == 0x30 && header->carttype == 0x05 && header->licensee == 0xb2) {
props->has_dspx = 1;
props->necdsp_fw = DSPFW_3;
props->dsp_fw = DSPFW_3;
props->fpga_features |= FEAT_DSPX;
} else if (header->map == 0x30 && header->carttype == 0x03) {
props->has_dspx = 1;
props->necdsp_fw = DSPFW_4;
props->dsp_fw = DSPFW_4;
props->fpga_features |= FEAT_DSPX;
} else if (header->map == 0x30 && header->carttype == 0xf6 && header->romsize >= 0xa) {
props->has_dspx = 1;
props->has_st0010 = 1;
props->necdsp_fw = DSPFW_ST0010;
props->dsp_fw = DSPFW_ST0010;
props->fpga_features |= FEAT_ST0010;
header->ramsize = 2;
}

7
src/smc.h
View File

@ -33,6 +33,9 @@
#define DSPFW_4 ((const uint8_t*)"/sd2snes/dsp4.bin")
#define DSPFW_1B ((const uint8_t*)"/sd2snes/dsp1b.bin")
#define DSPFW_ST0010 ((const uint8_t*)"/sd2snes/st0010.bin")
#define CX4FW ((const uint8_t*)"/sd2snes/cx4.bin")
#define FPGA_CX4 ((const uint8_t*)"/sd2snes/fpga_cx4.bit")
typedef struct _snes_header {
uint8_t maker[2]; /* 0xB0 */
@ -60,10 +63,12 @@ typedef struct _snes_romprops {
uint32_t expramsize_bytes; /* ExpRAM size in bytes */
uint32_t ramsize_bytes; /* CartRAM size in bytes */
uint32_t romsize_bytes; /* ROM size in bytes (rounded up) */
const uint8_t* necdsp_fw; /* NEC DSP ROM filename */
const uint8_t* dsp_fw; /* DSP (NEC / Hitachi) ROM filename */
const uint8_t* fpga_conf; /* FPGA config file to load (default: base) */
uint8_t has_dspx; /* DSP[1-4] presence flag */
uint8_t has_st0010; /* st0010 presence flag (additional to dspx)*/
uint8_t has_msu1; /* MSU1 presence flag */
uint8_t has_cx4; /* CX4 presence flag */
uint8_t fpga_features; /* feature/peripheral enable bits*/
snes_header_t header; /* original header from ROM image */
} snes_romprops_t;

38
verilog/sd2snes/sd2snes.xise
View File

@ -16,55 +16,55 @@
<files>
<file xil_pn:name="address.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="17"/>
<association xil_pn:name="Implementation" xil_pn:seqID="17"/>
</file>
<file xil_pn:name="bsx.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="16"/>
<association xil_pn:name="Implementation" xil_pn:seqID="16"/>
</file>
<file xil_pn:name="clk_test.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/>
<association xil_pn:name="Implementation" xil_pn:seqID="6"/>
</file>
<file xil_pn:name="dac.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="15"/>
<association xil_pn:name="Implementation" xil_pn:seqID="15"/>
</file>
<file xil_pn:name="dcm.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="14"/>
<association xil_pn:name="Implementation" xil_pn:seqID="14"/>
</file>
<file xil_pn:name="main.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="18"/>
<association xil_pn:name="Implementation" xil_pn:seqID="18"/>
</file>
<file xil_pn:name="mcu_cmd.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="13"/>
<association xil_pn:name="Implementation" xil_pn:seqID="13"/>
</file>
<file xil_pn:name="msu.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="12"/>
<association xil_pn:name="Implementation" xil_pn:seqID="12"/>
</file>
<file xil_pn:name="rtc.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="11"/>
<association xil_pn:name="Implementation" xil_pn:seqID="11"/>
</file>
<file xil_pn:name="sd_dma.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/>
<association xil_pn:name="Implementation" xil_pn:seqID="10"/>
</file>
<file xil_pn:name="spi.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/>
<association xil_pn:name="Implementation" xil_pn:seqID="9"/>
</file>
<file xil_pn:name="srtc.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/>
<association xil_pn:name="Implementation" xil_pn:seqID="8"/>
</file>
<file xil_pn:name="upd77c25.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>
<association xil_pn:name="Implementation" xil_pn:seqID="7"/>
</file>
<file xil_pn:name="main.ucf" xil_pn:type="FILE_UCF">
@ -72,7 +72,7 @@
</file>
<file xil_pn:name="main_tf.v" xil_pn:type="FILE_VERILOG"/>
<file xil_pn:name="updtest_tf.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="19"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="19"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="19"/>
@ -90,11 +90,11 @@
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
</file>
<file xil_pn:name="ipcore_dir/dac_buf.xco" xil_pn:type="FILE_COREGEN">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
<association xil_pn:name="Implementation" xil_pn:seqID="5"/>
</file>
<file xil_pn:name="ipcore_dir/msu_databuf.xco" xil_pn:type="FILE_COREGEN">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
</file>
<file xil_pn:name="ipcore_dir/upd77c25_datram.xise" xil_pn:type="FILE_COREGENISE">
@ -377,8 +377,8 @@
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="work.updtest" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="work.updtest" xil_pn:valueState="default"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-4" xil_pn:valueState="non-default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="12" xil_pn:valueState="non-default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100) Par" xil_pn:value="12" xil_pn:valueState="non-default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="8" xil_pn:valueState="non-default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100) Par" xil_pn:value="8" xil_pn:valueState="non-default"/>
<property xil_pn:name="Structure window" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
@ -433,7 +433,7 @@
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Module|updtest" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Module|main" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="sd2snes" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>

67
verilog/sd2snes_cx4/address.v Normal file
View File

@ -0,0 +1,67 @@
`timescale 1 ns / 1 ns
//////////////////////////////////////////////////////////////////////////////////
// Company: Rehkopf
// Engineer: Rehkopf
//
// Create Date: 01:13:46 05/09/2009
// Design Name:
// Module Name: address
// Project Name:
// Target Devices:
// Tool versions:
// Description: Address logic w/ SaveRAM masking
//
// Dependencies:
//
// Revision:
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module address(
input CLK,
input [2:0] MAPPER, // MCU detected mapper
input [23:0] SNES_ADDR, // requested address from SNES
input SNES_CS, // SNES ROMSEL signal
output [23:0] ROM_ADDR, // Address to request from SRAM0
output ROM_SEL, // enable SRAM0 (active low)
output IS_SAVERAM, // address/CS mapped as SRAM?
output IS_ROM, // address mapped as ROM?
output IS_WRITABLE, // address somehow mapped as writable area?
input [23:0] SAVERAM_MASK,
input [23:0] ROM_MASK,
input use_msu1,
output msu_enable,
output cx4_enable,
output cx4_vect_enable
);
wire [23:0] SRAM_SNES_ADDR;
/* Cx4 mapper:
- LoROM (extended to 00-7d, 80-ff)
- MMIO @ 6000-7fff
*/
assign IS_ROM = SNES_ADDR[15] & ~SNES_CS;
assign SRAM_SNES_ADDR = ({2'b00, SNES_ADDR[22:16], SNES_ADDR[14:0]}
& ROM_MASK);
assign ROM_ADDR = SRAM_SNES_ADDR;
assign ROM_SEL = 1'b0;
wire msu_enable_w = use_msu1 & (!SNES_ADDR[22] && ((SNES_ADDR[15:0] & 16'hfff8) == 16'h2000));
reg [5:0] msu_enable_r;
initial msu_enable_r = 6'b000000;
always @(posedge CLK) msu_enable_r <= {msu_enable_r[4:0], msu_enable_w};
assign msu_enable = &msu_enable_r[5:2];
wire cx4_enable_w = (!SNES_ADDR[22] && (SNES_ADDR[15:13] == 3'b011));
reg [5:0] cx4_enable_r;
initial cx4_enable_r = 6'b000000;
always @(posedge CLK) cx4_enable_r <= {cx4_enable_r[4:0], cx4_enable_w};
assign cx4_enable = &cx4_enable_r[5:2];
assign cx4_vect_enable = &SNES_ADDR[15:5];
endmodule

882
verilog/sd2snes_cx4/cx4.v Normal file
View File

@ -0,0 +1,882 @@
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 23:14:37 10/13/2011
// Design Name:
// Module Name: cx4
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module cx4(
input [7:0] DI,
output [7:0] DO,
input [12:0] ADDR,
input CS,
input SNES_VECT_EN,
input nRD,
input nWR,
input CLK,
input [23:0] DATROM_DI,
input DATROM_WE,
input [9:0] DATROM_ADDR,
input [7:0] BUS_DI,
output [23:0] BUS_ADDR,
output BUS_RRQ,
input BUS_RDY,
output cx4_active
);
reg [2:0] cx4_busy;
parameter BUSY_CACHE = 2'b00;
parameter BUSY_DMA = 2'b01;
parameter BUSY_CPU = 2'b10;
wire datram_enable = CS & (ADDR[11:0] < 12'hc00);
wire mmio_enable = CS & (ADDR[12:5] == 8'b11111010) & (ADDR[4:0] < 5'b10011);
wire status_enable = CS & (ADDR[12:5] == 8'b11111010) & (ADDR[4:0] >= 5'b10011);
wire vector_enable = (CS & (ADDR[12:5] == 8'b11111011)) | (cx4_active & SNES_VECT_EN);
wire gpr_enable = CS & (&(ADDR[12:7]) && ADDR[5:4] != 2'b11);
wire pgmrom_enable = CS & (ADDR[12:5] == 8'b11110000);
wire [7:0] DATRAM_DO;
reg [7:0] MMIO_DOr;
wire [7:0] MMIO_DO;
wire [7:0] STATUS_DO;
wire [7:0] VECTOR_DO;
wire [7:0] GPR_DO;
assign DO = datram_enable ? DATRAM_DO
: mmio_enable ? MMIO_DO
: status_enable ? STATUS_DO
: vector_enable ? VECTOR_DO
: gpr_enable ? GPR_DO
: 8'h00;
/* 0x1f40 - 0x1f52: MMIO
SNES: 8 bits / CX4: various */
reg [23:0] cx4_mmio_dmasrc;
reg [15:0] cx4_mmio_dmalen;
reg [23:0] cx4_mmio_dmatgt;
reg cx4_mmio_cachepage;
reg [23:0] cx4_mmio_pgmoff;
reg [1:0] cx4_mmio_savepage;
reg [14:0] cx4_mmio_pgmpage;
reg [7:0] cx4_mmio_pc;
reg [7:0] cx4_mmio_r1f50;
reg cx4_mmio_r1f51;
reg cx4_mmio_r1f52;
/* 0x1f53 - 0x1f5f: status register */
assign cx4_active = |cx4_busy;
/* 0x1f60 - 0x1f7f: reset vectors */
reg [7:0] vector [31:0];
/* 0x1f80 - 0x1faf (0x1fc0 - 0x1fef): general purpose register file
SNES: 8 bits / CX4: 24 bits */
reg [7:0] gpr [47:0];
wire [47:0] cpu_mul_result;
reg [14:0] cx4_mmio_pagemem[1:0];
reg [23:0] const [15:0];
reg [14:0] cachetag [1:0];
reg [1:0] cachevalid;
reg [14:0] cache_pgmpage;
reg [14:0] cpu_cache_pgmpage;
reg cache_cachepage;
reg cpu_cache_cachepage;
reg cpu_cache_done;
reg [7:0] cpu_pc_stack [7:0];
reg [7:0] cpu_page_stack;
initial begin
cache_pgmpage = 15'b0;
cpu_cache_pgmpage = 15'b0;
cache_cachepage = 1'b0;
cpu_cache_cachepage = 1'b0;
cpu_cache_done = 1'b0;
cachetag[0] = 14'h0000;
cachetag[1] = 14'h0000;
cachevalid = 2'b00;
cx4_busy = 3'b000;
cx4_mmio_pgmoff = 24'h000000;
cx4_mmio_pgmpage = 15'h0000;
cx4_mmio_dmasrc = 24'h000000;
cx4_mmio_dmalen = 16'h0000;
cx4_mmio_dmatgt = 24'h000000;
cx4_mmio_savepage = 2'b00;
const[0] = 24'h000000;
const[1] = 24'hffffff;
const[2] = 24'h00ff00;
const[3] = 24'hff0000;
const[4] = 24'h00ffff;
const[5] = 24'hffff00;
const[6] = 24'h800000;
const[7] = 24'h7fffff;
const[8] = 24'h008000;
const[9] = 24'h007fff;
const[10] = 24'hff7fff;
const[11] = 24'hffff7f;
const[12] = 24'h010000;
const[13] = 24'hfeffff;
const[14] = 24'h000100;
const[15] = 24'h00feff;
cpu_pc_stack[0] = 8'b0;
cpu_pc_stack[1] = 8'b0;
cpu_pc_stack[2] = 8'b0;
cpu_pc_stack[3] = 8'b0;
cpu_pc_stack[4] = 8'b0;
cpu_pc_stack[5] = 8'b0;
cpu_pc_stack[6] = 8'b0;
cpu_pc_stack[7] = 8'b0;
cpu_page_stack = 8'b0;
end
assign MMIO_DO = MMIO_DOr;
assign VECTOR_DO = vector [ADDR[4:0]];
assign GPR_DO = gpr [ADDR[5:0]];
assign STATUS_DO = {1'b0, cx4_active, 4'b0000, ~cx4_active, 1'b0};
reg [7:0] DIr;
always @(posedge CLK) DIr <= DI;
reg [4:0] datram_enable_sreg;
initial datram_enable_sreg = 5'b11111;
always @(posedge CLK) datram_enable_sreg <= {datram_enable_sreg[3:0], datram_enable};
reg [5:0] nWR_sreg;
always @(posedge CLK) nWR_sreg <= {nWR_sreg[4:0], nWR};
wire WR_EN = (nWR_sreg[5:0] == 6'b000001);
wire DATRAM_WR_EN = datram_enable & WR_EN;
wire MMIO_WR_EN = mmio_enable & WR_EN;
wire VECTOR_WR_EN = vector_enable & WR_EN;
wire GPR_WR_EN = gpr_enable & WR_EN;
reg [23:0] cpu_idb; // tmp register for reg file read
/* Need to cache when:
1f48 is written
AND (selected cache page is invalid
OR selected cache page does not contain requested page already)
*/
reg CACHE_TRIG_ENr;
reg CACHE_TRIG_EN2r;
reg cpu_cache_en;
initial begin
CACHE_TRIG_ENr = 1'b0;
CACHE_TRIG_EN2r = 1'b0;
cpu_cache_en = 1'b0;
end
always @(posedge CLK) CACHE_TRIG_EN2r <= CACHE_TRIG_ENr;
wire CACHE_TRIG_EN = CACHE_TRIG_EN2r;
reg DMA_TRIG_ENr;
initial DMA_TRIG_ENr = 1'b0;
wire DMA_TRIG_EN = DMA_TRIG_ENr;
reg CACHE_BUS_RRQr;
reg DMA_BUS_RRQr;
reg cpu_bus_rq;
initial begin
CACHE_BUS_RRQr = 1'b0;
DMA_BUS_RRQr = 1'b0;
cpu_bus_rq = 1'b0;
end
assign BUS_RRQ = CACHE_BUS_RRQr | DMA_BUS_RRQr | cpu_bus_rq;
reg cpu_page;
reg [14:0] cpu_p;
reg [7:0] cpu_pc;
reg [23:0] cpu_a;
reg fl_n;
reg fl_z;
reg fl_c;
reg cpu_go_en_r;
initial cpu_go_en_r = 1'b0;
initial begin
cx4_mmio_r1f50 = 8'h33;
cx4_mmio_r1f51 = 1'b0;
cx4_mmio_r1f52 = 1'b1;
end
always @(posedge CLK) begin
case (ADDR[4:0])
5'h00: MMIO_DOr <= cx4_mmio_dmasrc[7:0]; // 1f40
5'h01: MMIO_DOr <= cx4_mmio_dmasrc[15:8]; // 1f41
5'h02: MMIO_DOr <= cx4_mmio_dmasrc[23:16]; // 1f42
5'h03: MMIO_DOr <= cx4_mmio_dmalen[7:0]; // 1f43
5'h04: MMIO_DOr <= cx4_mmio_dmalen[15:8]; // 1f44
5'h05: MMIO_DOr <= cx4_mmio_dmatgt[7:0]; // 1f45
5'h06: MMIO_DOr <= cx4_mmio_dmatgt[15:8]; // 1f46
5'h07: MMIO_DOr <= cx4_mmio_dmatgt[23:16]; // 1f47
5'h08: MMIO_DOr <= {7'b0, cx4_mmio_cachepage};
5'h09: MMIO_DOr <= cx4_mmio_pgmoff[7:0]; // 1f49
5'h0a: MMIO_DOr <= cx4_mmio_pgmoff[15:8]; // 1f4a
5'h0b: MMIO_DOr <= cx4_mmio_pgmoff[23:16]; // 1f4b
5'h0c: MMIO_DOr <= {6'b0, cx4_mmio_savepage}; // 1f4c
5'h0d: MMIO_DOr <= cx4_mmio_pgmpage[7:0]; // 1f4d
5'h0e: MMIO_DOr <= {1'b0, cx4_mmio_pgmpage[14:8]}; // 1f4e
5'h0f: MMIO_DOr <= cx4_mmio_pc; // 1f4f
5'h10: MMIO_DOr <= cx4_mmio_r1f50; // 1f50
5'h11: MMIO_DOr <= {7'b0, cx4_mmio_r1f51}; // 1f51
5'h12: MMIO_DOr <= {7'b0, cx4_mmio_r1f52}; // 1f52
default: MMIO_DOr <= 8'hff;
endcase
end
always @(posedge CLK) begin
if(MMIO_WR_EN) begin
case(ADDR[4:0])
5'h00: cx4_mmio_dmasrc[7:0] <= DIr; // 1f40
5'h01: cx4_mmio_dmasrc[15:8] <= DIr; // 1f41
5'h02: cx4_mmio_dmasrc[23:16] <= DIr; // 1f42
5'h03: cx4_mmio_dmalen[7:0] <= DIr; // 1f43
5'h04: cx4_mmio_dmalen[15:8] <= DIr; // 1f44
5'h05: cx4_mmio_dmatgt[7:0] <= DIr; // 1f45
5'h06: cx4_mmio_dmatgt[15:8] <= DIr; // 1f46
5'h07: begin
cx4_mmio_dmatgt[23:16] <= DIr; // 1f47
DMA_TRIG_ENr <= 1'b1;
end
5'h08: begin
cx4_mmio_cachepage <= DIr[0]; // 1f48
CACHE_TRIG_ENr <= 1'b1;
end
5'h09: cx4_mmio_pgmoff[7:0] <= DIr; // 1f49
5'h0a: cx4_mmio_pgmoff[15:8] <= DIr; // 1f4a
5'h0b: cx4_mmio_pgmoff[23:16] <= DIr; // 1f4b
5'h0c: begin
cx4_mmio_savepage <= DIr[1:0];
if(DIr[0]) cx4_mmio_pagemem[0] <= cx4_mmio_pgmpage;
if(DIr[1]) cx4_mmio_pagemem[1] <= cx4_mmio_pgmpage;
end
5'h0d: cx4_mmio_pgmpage[7:0] <= DIr; // 1f4d
5'h0e: cx4_mmio_pgmpage[14:8] <= DIr[6:0]; // 1f4e
5'h0f: begin
cx4_mmio_pc <= DIr; // 1f4f
if(cx4_mmio_savepage[0]
&& cx4_mmio_pagemem[0] == cx4_mmio_pgmpage)
cx4_mmio_cachepage <= 1'b0;
else if(cx4_mmio_savepage[1]
&& cx4_mmio_pagemem[1] == cx4_mmio_pgmpage)
cx4_mmio_cachepage <= 1'b1;
cpu_go_en_r <= 1'b1;
end
5'h10: cx4_mmio_r1f50 <= DIr & 8'h77; // 1f50
5'h11: cx4_mmio_r1f51 <= DIr[0]; // 1f51
5'h12: cx4_mmio_r1f52 <= DIr[0]; // 1f52
endcase
end else begin
CACHE_TRIG_ENr <= 1'b0;
DMA_TRIG_ENr <= 1'b0;
cpu_go_en_r <= 1'b0;
end
end
always @(posedge CLK) begin
if(VECTOR_WR_EN) vector[ADDR[4:0]] <= DIr;
end
reg [4:0] CACHE_ST;
parameter ST_CACHE_IDLE = 5'b00001;
parameter ST_CACHE_START = 5'b00010;
parameter ST_CACHE_WAIT = 5'b00100;
parameter ST_CACHE_ADDR = 5'b01000;
parameter ST_CACHE_END = 5'b10000;
initial CACHE_ST = ST_CACHE_IDLE;
reg [4:0] DMA_ST;
parameter ST_DMA_IDLE = 5'b00001;
parameter ST_DMA_START = 5'b00010;
parameter ST_DMA_WAIT = 5'b00100;
parameter ST_DMA_ADDR = 5'b01000;
parameter ST_DMA_END = 5'b10000;
initial DMA_ST = ST_DMA_IDLE;
reg [23:0] CACHE_SRC_ADDRr;
wire [22:0] MAPPED_CACHE_SRC_ADDR = {CACHE_SRC_ADDRr[23:16],CACHE_SRC_ADDRr[14:0]};
reg [23:0] DMA_SRC_ADDRr;
wire [22:0] MAPPED_DMA_SRC_ADDR = {DMA_SRC_ADDRr[23:16],DMA_SRC_ADDRr[14:0]};
wire [22:0] MAPPED_CPU_BUS_ADDR;
assign BUS_ADDR = cx4_busy[BUSY_CACHE] ? MAPPED_CACHE_SRC_ADDR
: cx4_busy[BUSY_DMA] ? MAPPED_DMA_SRC_ADDR
: MAPPED_CPU_BUS_ADDR;
reg cx4_pgmrom_we;
initial cx4_pgmrom_we = 1'b0;
reg [9:0] cx4_pgmrom_addr;
reg [19:0] cache_count;
initial cache_count = 20'b0;
always @(posedge CLK) begin
case(CACHE_ST)
ST_CACHE_IDLE: begin
if(CACHE_TRIG_EN
& (~cachevalid[cx4_mmio_cachepage]
| |(cachetag[cx4_mmio_cachepage] ^ cx4_mmio_pgmpage))) begin
CACHE_ST <= ST_CACHE_START;
cache_pgmpage <= cx4_mmio_pgmpage;
cache_cachepage <= cx4_mmio_cachepage;
end else if(cpu_cache_en
& (~cachevalid[~cpu_page]
| |(cachetag[~cpu_page] ^ cpu_p))) begin
CACHE_ST <= ST_CACHE_START;
cache_pgmpage <= cpu_p;
cache_cachepage <= ~cpu_page;
cx4_busy[BUSY_CACHE] <= 1'b1;
end
else CACHE_ST <= ST_CACHE_IDLE;
end
ST_CACHE_START: begin
cx4_busy[BUSY_CACHE] <= 1'b1;
CACHE_SRC_ADDRr <= cx4_mmio_pgmoff + {cache_pgmpage, 9'b0};
cx4_pgmrom_addr <= {cache_cachepage, 9'b0};
CACHE_ST <= ST_CACHE_WAIT;
cache_count <= 10'b0;
CACHE_BUS_RRQr <= 1'b1;
end
ST_CACHE_WAIT: begin
CACHE_BUS_RRQr <= 1'b0;
if(~CACHE_BUS_RRQr & BUS_RDY) begin
CACHE_ST <= ST_CACHE_ADDR;
cx4_pgmrom_we <= 1'b1;
cache_count <= cache_count + 1;
end else CACHE_ST <= ST_CACHE_WAIT;
end
ST_CACHE_ADDR: begin
cx4_pgmrom_we <= 1'b0;
CACHE_SRC_ADDRr <= CACHE_SRC_ADDRr + 1;
cx4_pgmrom_addr <= cx4_pgmrom_addr + 1;
if(cache_count == 9'h1ff) begin
cx4_busy[BUSY_CACHE] <= 1'b0;
cachetag[cache_cachepage] <= cache_pgmpage;
cachevalid[cache_cachepage] <= 1'b1;
CACHE_ST <= ST_CACHE_IDLE;
end else begin
CACHE_BUS_RRQr <= 1'b1;
CACHE_ST <= ST_CACHE_WAIT;
end
end
endcase
end
reg cx4_dma_datram_we;
reg cx4_cpu_datram_we;
initial cx4_dma_datram_we = 1'b0;
initial cx4_cpu_datram_we = 1'b0;
wire cx4_datram_we = cx4_dma_datram_we | cx4_cpu_datram_we;
reg [11:0] cx4_dma_datram_addr;
reg [11:0] cx4_cpu_datram_addr;
wire [11:0] cx4_datram_addr = cx4_busy[BUSY_DMA] ? cx4_dma_datram_addr : cx4_cpu_datram_addr;
reg [23:0] cx4_cpu_datram_di;
wire [7:0] cx4_datram_di = cx4_busy[BUSY_DMA] ? BUS_DI : cx4_cpu_datram_di;
reg [15:0] dma_count;
initial dma_count = 16'b0;
always @(posedge CLK) begin
case(DMA_ST)
ST_DMA_IDLE: begin
if(DMA_TRIG_EN) begin
DMA_ST <= ST_DMA_START;
end else DMA_ST <= ST_DMA_IDLE;
end
ST_DMA_START: begin
cx4_busy[BUSY_DMA] <= 1'b1;
DMA_SRC_ADDRr <= cx4_mmio_dmasrc;
cx4_dma_datram_addr <= (cx4_mmio_dmatgt & 24'h000fff);
DMA_ST <= ST_DMA_WAIT;
dma_count <= cx4_mmio_dmalen;
DMA_BUS_RRQr <= 1'b1;
end
ST_DMA_WAIT: begin
DMA_BUS_RRQr <= 1'b0;
if(~DMA_BUS_RRQr & BUS_RDY) begin
DMA_ST <= ST_DMA_ADDR;
cx4_dma_datram_we <= 1'b1;
dma_count <= dma_count - 1;
end else DMA_ST <= ST_DMA_WAIT;
end
ST_DMA_ADDR: begin
cx4_dma_datram_we <= 1'b0;
DMA_SRC_ADDRr <= DMA_SRC_ADDRr + 1;
cx4_dma_datram_addr <= cx4_dma_datram_addr + 1;
if(dma_count == 16'h0000) begin
cx4_busy[BUSY_DMA] <= 1'b0;
DMA_ST <= ST_DMA_IDLE;
end else begin
DMA_BUS_RRQr <= 1'b1;
DMA_ST <= ST_DMA_WAIT;
end
end
endcase
end
/***************************
=========== CPU ===========
***************************/
reg [4:0] CPU_STATE;
reg [2:0] cpu_sp;
initial cpu_sp = 3'b000;
wire [15:0] cpu_op_w;
reg [15:0] cpu_op;
reg [23:0] cpu_busdata;
reg [23:0] cpu_romdata;
reg [23:0] cpu_ramdata;
reg [23:0] cpu_busaddr;
assign MAPPED_CPU_BUS_ADDR = {cpu_busaddr[23:16], cpu_busaddr[14:0]};
reg [23:0] cpu_romaddr;
reg [23:0] cpu_ramaddr;
reg [23:0] cpu_acch;
reg [23:0] cpu_accl;
reg [23:0] cpu_mul_src;
reg [24:0] cpu_alu_res;
reg [23:0] cpu_dummy;
reg [23:0] cpu_tmp;
reg [23:0] cpu_sa; // tmp register for shifted accumulator
wire [9:0] cx4_datrom_addr = cpu_a[9:0];
wire [23:0] cx4_datrom_do;
wire [7:0] cx4_datram_do;
parameter ST_CPU_IDLE = 5'b00001;
parameter ST_CPU_0 = 5'b00010;
parameter ST_CPU_1 = 5'b00100;
parameter ST_CPU_2 = 5'b01000;
parameter ST_CPU_3 = 5'b10000;
initial CPU_STATE = ST_CPU_IDLE;
parameter OP_NOP = 5'b00000;
parameter OP_JP = 5'b00001;
parameter OP_SKIP = 5'b00010;
parameter OP_RT = 5'b00011;
parameter OP_LD = 5'b00100;
parameter OP_ST = 5'b00101;
parameter OP_SWP = 5'b00110;
parameter OP_RDROM = 5'b00111;
parameter OP_RDRAM = 5'b01000;
parameter OP_WRRAM = 5'b01001;
parameter OP_ALU = 5'b01010;
parameter OP_MUL = 5'b01011;
parameter OP_WAI = 5'b01100;
parameter OP_BUS = 5'b01101;
parameter OP_CMP = 5'b01110;
parameter OP_SEX = 5'b01111;
parameter OP_HLT = 5'b10000;
wire [6:0] op_id = cpu_op_w[15:10];
reg [7:0] op_param;
reg [4:0] op;
reg [1:0] op_sa;
reg op_imm;
reg op_p;
reg op_call;
reg op_jump;
reg condtrue;
always @(posedge CLK) begin
if(cpu_go_en_r) cx4_busy[BUSY_CPU] <= 1'b1;
else if(op == OP_HLT) cx4_busy[BUSY_CPU] <= 1'b0;
end
always @(posedge CLK) begin
case(op_sa)
2'b00: cpu_sa <= cpu_a;
2'b01: cpu_sa <= cpu_a << 1;
2'b10: cpu_sa <= cpu_a << 8;
2'b11: cpu_sa <= cpu_a << 16;
endcase
end
reg jp_docache;
initial jp_docache = 1'b0;
always @(posedge CLK) begin
case(CPU_STATE)
ST_CPU_IDLE: begin
if(cpu_go_en_r) begin
cpu_pc <= cx4_mmio_pc;
cpu_page <= cx4_mmio_cachepage;
cpu_p <= cx4_mmio_pgmpage;
op <= OP_NOP;
CPU_STATE <= ST_CPU_2;
end
else CPU_STATE <= ST_CPU_IDLE;
end
ST_CPU_0: begin // Phase 0:
cpu_cache_en <= 1'b0;
if(op == OP_HLT) begin
CPU_STATE <= ST_CPU_IDLE;
end
else CPU_STATE <= ST_CPU_1;
case(op)
OP_JP: begin
case(cpu_op[11:10])
2'b10: condtrue <= 1'b1;
2'b11: condtrue <= fl_z;
2'b00: condtrue <= fl_c;
2'b01: condtrue <= fl_n;
endcase
if(op_p && !jp_docache) begin
jp_docache <= 1'b1;
cpu_cache_en <= 1'b1;
end
end
OP_SKIP: begin
case(cpu_op[9:8])
2'b01: condtrue <= (fl_c == cpu_op[0]);
2'b10: condtrue <= (fl_z == cpu_op[0]);
2'b11: condtrue <= (fl_n == cpu_op[0]);
endcase
end
OP_LD, OP_ALU, OP_MUL, OP_CMP, OP_SEX: begin
if(op_imm) cpu_idb <= {16'b0, op_param};
else casex(op_param)
8'h00: cpu_idb <= cpu_a;
8'h01: cpu_idb <= cpu_acch;
8'h02: cpu_idb <= cpu_accl;
8'h03: cpu_idb <= cpu_busdata;
8'h08: cpu_idb <= cpu_romdata;
8'h0c: cpu_idb <= cpu_ramdata;
8'h13: cpu_idb <= cpu_busaddr;
8'h1c: cpu_idb <= cpu_ramaddr;
8'h5x: cpu_idb <= const[op_param[3:0]];
8'h6x: cpu_idb <= {gpr[op_param[3:0]*3+2],
gpr[op_param[3:0]*3+1],
gpr[op_param[3:0]*3]};
default: cpu_idb <= 24'b0;
endcase
end
OP_ST: begin
cpu_idb <= cpu_a;
end
OP_SWP: begin
cpu_idb <= cpu_a;
casex(op_param)
8'h00: cpu_tmp <= cpu_a;
8'h01: cpu_tmp <= cpu_acch;
8'h02: cpu_tmp <= cpu_accl;
8'h03: cpu_tmp <= cpu_busdata;
8'h08: cpu_tmp <= cpu_romdata;
8'h0c: cpu_tmp <= cpu_ramdata;
8'h13: cpu_tmp <= cpu_busaddr;
8'h1c: cpu_tmp <= cpu_ramaddr;
8'h5x: cpu_tmp <= const[op_param[3:0]];
8'h6x: cpu_tmp <= {gpr[op_param[3:0]*3+2],
gpr[op_param[3:0]*3+1],
gpr[op_param[3:0]*3]};
default: cpu_tmp <= 24'b0;
endcase
end
OP_RDRAM, OP_WRRAM: begin
if(op_imm) cx4_cpu_datram_addr <= {16'b0, op_param} + cpu_ramaddr;
else casex(op_param)
8'h00: cx4_cpu_datram_addr <= cpu_a;
8'h01: cx4_cpu_datram_addr <= cpu_acch;
8'h02: cx4_cpu_datram_addr <= cpu_accl;
8'h03: cx4_cpu_datram_addr <= cpu_busdata;
8'h08: cx4_cpu_datram_addr <= cpu_romdata;
8'h0c: cx4_cpu_datram_addr <= cpu_ramdata;
8'h13: cx4_cpu_datram_addr <= cpu_busaddr;
8'h1c: cx4_cpu_datram_addr <= cpu_ramaddr;
8'h5x: cx4_cpu_datram_addr <= const[op_param[3:0]];
8'h6x: cx4_cpu_datram_addr <= {gpr[op_param[3:0]*3+2],
gpr[op_param[3:0]*3+1],
gpr[op_param[3:0]*3]};
default: cx4_cpu_datram_addr <= 24'b0;
endcase
end
OP_BUS: cpu_bus_rq <= 1'b1;
endcase
end
ST_CPU_1: begin
CPU_STATE <= ST_CPU_2;
condtrue <= 1'b0;
case(op)
OP_JP: begin
cpu_cache_en <= 1'b0;
if(!cpu_cache_en && !cx4_busy[BUSY_CACHE]) begin
jp_docache <= 1'b0;
if(condtrue) begin
if(op_call) begin
cpu_page_stack[cpu_sp] <= cpu_page;
cpu_pc_stack[cpu_sp] <= cpu_pc + 1;
cpu_sp <= cpu_sp + 1;
end
cpu_pc <= op_param;
cpu_page <= cpu_page ^ op_p;
end else cpu_pc <= cpu_pc + 1;
end
end
OP_SKIP: begin
if(condtrue) cpu_pc <= cpu_pc + 2;
else cpu_pc <= cpu_pc + 1;
end
OP_RT: begin
cpu_page <= cpu_page_stack[cpu_sp - 1];
cpu_pc <= cpu_pc_stack[cpu_sp - 1];
cpu_sp <= cpu_sp - 1;
end
OP_WAI: if(BUS_RDY) cpu_pc <= cpu_pc + 1;
OP_BUS: begin
cpu_bus_rq <= 1'b0;
cpu_pc <= cpu_pc + 1;
end
default: cpu_pc <= cpu_pc + 1;
endcase
end
ST_CPU_2: begin
CPU_STATE <= ST_CPU_3;
case(op)
OP_LD: begin
casex(cpu_op[11:8])
4'b0x00: cpu_a <= cpu_idb;
4'b0x11: cpu_p <= cpu_idb;
4'b1100: cpu_p[7:0] <= op_param;
4'b1101: cpu_p[14:8] <= op_param;
endcase
end
OP_ST, OP_SWP: begin
casex(op_param)
8'h01: cpu_acch <= cpu_idb;
8'h02: cpu_accl <= cpu_idb;
8'h08: cpu_romdata <= cpu_idb;
8'h0c: cpu_ramdata <= cpu_idb;
8'h13: cpu_busaddr <= cpu_idb;
8'h1c: cpu_ramaddr <= cpu_idb;
endcase
if(op==OP_SWP) cpu_a <= cpu_tmp;
end
OP_RDROM: cpu_romdata <= cx4_datrom_do;
OP_RDRAM: begin
case(cpu_op[9:8])
2'b00: cpu_ramdata[7:0] <= cx4_datram_do;
2'b01: cpu_ramdata[15:8] <= cx4_datram_do;
2'b10: cpu_ramdata[23:16] <= cx4_datram_do;
endcase
end
OP_WRRAM: begin
case(cpu_op[9:8])
2'b00: cx4_cpu_datram_di <= cpu_ramdata[7:0];
2'b01: cx4_cpu_datram_di <= cpu_ramdata[15:8];
2'b10: cx4_cpu_datram_di <= cpu_ramdata[23:16];
endcase
cx4_cpu_datram_we <= 1'b1;
end
OP_CMP: begin
case(cpu_op[15:11])
5'b01001: cpu_alu_res <= cpu_idb - cpu_sa;
5'b01010: cpu_alu_res <= cpu_sa - cpu_idb;
endcase
end
OP_SEX: begin
case(cpu_op[9:8])
2'b01: cpu_alu_res <= {{16{cpu_idb[7]}}, cpu_idb[7:0]};
2'b10: cpu_alu_res <= {{8{cpu_idb[15]}}, cpu_idb[15:0]};
endcase
end
OP_ALU: begin
case(cpu_op[15:11])
5'b10000: cpu_alu_res <= cpu_sa + cpu_idb;
5'b10001: cpu_alu_res <= cpu_idb - cpu_sa;
5'b10010: cpu_alu_res <= cpu_sa - cpu_idb;
5'b10101: cpu_alu_res <= cpu_sa ^ cpu_idb;
5'b10110: cpu_alu_res <= cpu_sa & cpu_idb;
5'b10111: cpu_alu_res <= cpu_sa | cpu_idb;
5'b11000: cpu_alu_res <= cpu_a >> cpu_idb;
5'b11001: cpu_alu_res <= ($signed(cpu_a)) >>> cpu_idb;
5'b11010: {cpu_dummy, cpu_alu_res[23:0]} <= {cpu_a, cpu_a} >> cpu_idb;
5'b11011: cpu_alu_res <= cpu_a << cpu_idb;
endcase
end
endcase
end
ST_CPU_3: begin
CPU_STATE <= ST_CPU_0;
case(op)
OP_BUS: cpu_busaddr <= cpu_busaddr + 1;
OP_WRRAM: cx4_cpu_datram_we <= 1'b0;
OP_CMP: begin
fl_n <= cpu_alu_res[23];
fl_z <= cpu_alu_res[23:0] == 24'b0;
fl_c <= ~cpu_alu_res[24];
end
OP_SEX: cpu_a <= cpu_alu_res[23:0];
OP_ALU: begin
cpu_a <= cpu_alu_res[23:0];
case(cpu_op[15:11])
5'b10000: begin
fl_n <= cpu_alu_res[23];
fl_z <= cpu_alu_res[23:0] == 24'b0;
fl_c <= cpu_alu_res[24];
end
5'b10001, 5'b10010: begin
fl_n <= cpu_alu_res[23];
fl_z <= cpu_alu_res[23:0] == 24'b0;
fl_c <= ~cpu_alu_res[24];
end
default: begin
fl_n <= cpu_alu_res[23];
fl_z <= cpu_alu_res[23:0] == 24'b0;
end
endcase
end
OP_MUL: begin
cpu_acch <= cpu_mul_result[47:24];
cpu_accl <= cpu_mul_result[23:0];
fl_z <= (cpu_mul_result == 48'b0);
fl_n <= cpu_mul_result[47];
end
endcase
cpu_op <= cpu_op_w;
casex(cpu_op_w[15:11])
5'b00000: op <= OP_NOP;
5'b00x01: op <= OP_JP;
5'b00x10: op <= OP_JP;
5'b00100: op <= OP_SKIP;
5'b00111: op <= OP_RT;
5'b01100: op <= OP_LD;
5'b01111: op <= OP_LD;
5'b11100: op <= OP_ST;
5'b11110: op <= OP_SWP;
5'b01110: op <= OP_RDROM;
5'b01101: op <= OP_RDRAM;
5'b11101: op <= OP_WRRAM;
5'b01001: op <= OP_CMP;
5'b01010: op <= OP_CMP;
5'b01011: op <= OP_SEX;
5'b10000: op <= OP_ALU;
5'b10001: op <= OP_ALU;
5'b10010: op <= OP_ALU;
5'b10101: op <= OP_ALU;
5'b10110: op <= OP_ALU;
5'b10111: op <= OP_ALU;
5'b11000: op <= OP_ALU;
5'b11001: op <= OP_ALU;
5'b11010: op <= OP_ALU;
5'b11011: op <= OP_ALU;
5'b10011: op <= OP_MUL;
5'b00011: op <= OP_WAI;
5'b01000: op <= OP_BUS;
5'b11111: op <= OP_HLT;
endcase
op_imm <= cpu_op_w[10];
op_p <= cpu_op_w[9];
op_call <= cpu_op_w[13];
op_param <= cpu_op_w[7:0];
op_sa <= cpu_op_w[9:8];
end
endcase
end
reg[2:0] BUSRD_STATE;
parameter ST_BUSRD_IDLE = 3'b001;
parameter ST_BUSRD_WAIT = 3'b010;
parameter ST_BUSRD_END = 3'b100;
initial BUSRD_STATE = ST_BUSRD_IDLE;
reg cpu_bus_rq2;
always @(posedge CLK) cpu_bus_rq2 <= cpu_bus_rq;
always @(posedge CLK) begin
if(CPU_STATE == ST_CPU_2
&& (op == OP_ST || op == OP_SWP)
&& op_param == 8'h03)
cpu_busdata <= cpu_idb;
else begin
case(BUSRD_STATE)
ST_BUSRD_IDLE: begin
if(cpu_bus_rq2) begin
BUSRD_STATE <= ST_BUSRD_WAIT;
end
end
ST_BUSRD_WAIT: begin
if(BUS_RDY) BUSRD_STATE <= ST_BUSRD_END;
else BUSRD_STATE <= ST_BUSRD_WAIT;
end
ST_BUSRD_END: begin
if(~cpu_busaddr[22]) cpu_busdata <= BUS_DI;
else cpu_busdata <= 8'h00;
end
endcase
end
end
// gpr write, either by CPU or by MMIO
always @(posedge CLK) begin
if(CPU_STATE == ST_CPU_2
&& (op == OP_ST || op == OP_SWP)
&& (op_param[7:4] == 4'h6)) begin
gpr[op_param[3:0]*3+2] <= cpu_idb[23:16];
gpr[op_param[3:0]*3+1] <= cpu_idb[15:8];
gpr[op_param[3:0]*3] <= cpu_idb[7:0];
end
else if(GPR_WR_EN) gpr[ADDR[5:0]] <= DIr;
end
/***************************
=========== MEM ===========
***************************/
cx4_datrom cx4_datrom (
.clka(CLK), // input clka
.wea(DATROM_WE), // input [0 : 0] wea
.addra(DATROM_ADDR), // input [9 : 0] addra
.dina(DATROM_DI), // input [23 : 0] dina
.clkb(CLK), // input clkb
.addrb(cx4_datrom_addr), // input [9 : 0] addrb
.doutb(cx4_datrom_do) // output [23 : 0] doutb
);
cx4_datram cx4_datram (
.clka(CLK), // input clka
.wea(DATRAM_WR_EN), // input [0 : 0] wea
.addra(ADDR[11:0]), // input [11 : 0] addra
.dina(DIr), // input [7 : 0] dina
.douta(DATRAM_DO), // output [7 : 0] douta
.clkb(CLK), // input clkb
.web(cx4_datram_we), // input [0 : 0] web
.addrb(cx4_datram_addr), // input [11 : 0] addrb
.dinb(cx4_datram_di), // input [7 : 0] dinb
.doutb(cx4_datram_do) // output [7 : 0] doutb
);
cx4_pgmrom cx4_pgmrom (
.clka(CLK), // input clka
.wea(cx4_pgmrom_we), // input [0 : 0] wea
.addra(cx4_pgmrom_addr), // input [9 : 0] addra
.dina(BUS_DI), // input [7 : 0] dina
.clkb(CLK), // input clkb
.addrb({cpu_page,cpu_pc}), // input [8 : 0] addrb
.doutb(cpu_op_w) // output [15 : 0] doutb
);
cx4_mul cx4_mul (
.clk(CLK), // input clk
.a(cpu_a), // input [23 : 0] a
.b(cpu_idb), // input [23 : 0] b
.p(cpu_mul_result) // output [47 : 0] p
);
endmodule

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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 19:26:11 07/23/2010
// Design Name:
// Module Name: dac_test
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module dac(
input clkin,
input sysclk,
input we,
input[10:0] pgm_address,
input[7:0] pgm_data,
input[7:0] volume,
input vol_latch,
input play,
input reset,
output sdout,
output lrck,
output mclk,
output DAC_STATUS
);
reg[8:0] dac_address_r;
wire[8:0] dac_address = dac_address_r;
wire[31:0] dac_data;
assign DAC_STATUS = dac_address_r[8];
reg[7:0] vol_reg;
reg[7:0] vol_target_reg;
reg[1:0] vol_latch_reg;
reg vol_valid;
reg[2:0] sysclk_sreg;
wire sysclk_rising = (sysclk_sreg[2:1] == 2'b01);
reg [25:0] interpol_count;
always @(posedge clkin) begin
sysclk_sreg <= {sysclk_sreg[1:0], sysclk};
end
dac_buf snes_dac_buf (
.clka(clkin),
.wea(~we), // Bus [0 : 0]
.addra(pgm_address), // Bus [10 : 0]
.dina(pgm_data), // Bus [7 : 0]
.clkb(clkin),
.addrb(dac_address), // Bus [8 : 0]
.doutb(dac_data)); // Bus [31 : 0]
reg [8:0] cnt;
reg [15:0] smpcnt;
reg [1:0] samples;
reg [15:0] smpshift;
assign mclk = cnt[2]; // mclk = clk/8
assign lrck = cnt[8]; // lrck = mclk/128
wire sclk = cnt[3]; // sclk = lrck*32
reg [2:0] lrck_sreg;
reg [2:0] sclk_sreg;
wire lrck_rising = ({lrck_sreg[2:1]} == 2'b01);
wire lrck_falling = ({lrck_sreg[2:1]} == 2'b10);
wire sclk_rising = ({sclk_sreg[2:1]} == 2'b01);
wire vol_latch_rising = (vol_latch_reg[1:0] == 2'b01);
reg sdout_reg;
assign sdout = sdout_reg;
reg [1:0] reset_sreg;
wire reset_rising = (reset_sreg[1:0] == 2'b01);
reg play_r;
initial begin
cnt = 9'h100;
smpcnt = 16'b0;
lrck_sreg = 2'b11;
sclk_sreg = 1'b0;
dac_address_r = 10'b0;
vol_valid = 1'b0;
vol_latch_reg = 1'b0;
vol_reg = 8'h0;
vol_target_reg = 8'hff;
samples <= 2'b00;
end
always @(posedge clkin) begin
if(reset_rising) begin
dac_address_r <= 0;
interpol_count <= 0;
end else if(sysclk_rising) begin
if(interpol_count > 59378938) begin
interpol_count <= interpol_count + 122500 - 59501439;
dac_address_r <= dac_address_r + play_r;
end else begin
interpol_count <= interpol_count + 122500;
end
end
end
always @(posedge clkin) begin
cnt <= cnt + 1;
lrck_sreg <= {lrck_sreg[1:0], lrck};
sclk_sreg <= {sclk_sreg[1:0], sclk};
vol_latch_reg <= {vol_latch_reg[0], vol_latch};
play_r <= play;
reset_sreg <= {reset_sreg[0], reset};
end
always @(posedge clkin) begin
if (vol_latch_rising) begin
vol_valid <= 1'b1;
end
else if(vol_valid) begin
vol_target_reg <= volume;
vol_valid <= 1'b0;
end
end
// ramp volume only every 4 samples
always @(posedge clkin) begin
if (lrck_rising && &samples[1:0]) begin
if(vol_reg > vol_target_reg)
vol_reg <= vol_reg - 1;
else if(vol_reg < vol_target_reg)
vol_reg <= vol_reg + 1;
end
end
always @(posedge clkin) begin
if (lrck_rising) begin // right channel
smpshift <= (({16'h0, dac_data[31:16]^16'h8000} * vol_reg) >> 8) ^ 16'h8000;
samples <= samples + 1;
end else if (lrck_falling) begin // left channel
smpshift <= (({16'h0, dac_data[15:0]^16'h8000} * vol_reg) >> 8) ^ 16'h8000;
end else begin
if (sclk_rising) begin
smpcnt <= smpcnt + 1;
sdout_reg <= smpshift[15];
smpshift <= {smpshift[14:0], 1'b0};
end
end
end
endmodule

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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 13:06:52 06/28/2009
// Design Name:
// Module Name: dcm
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module my_dcm (
input CLKIN,
output CLKFX,
output LOCKED,
input RST,
output[7:0] STATUS
);
// DCM: Digital Clock Manager Circuit
// Spartan-3
// Xilinx HDL Language Template, version 11.1
DCM #(
.SIM_MODE("SAFE"), // Simulation: "SAFE" vs. "FAST", see "Synthesis and Simulation Design Guide" for details
.CLKDV_DIVIDE(2.0), // Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
// 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
.CLKFX_DIVIDE(1), // Can be any integer from 1 to 32
.CLKFX_MULTIPLY(4), // Can be any integer from 2 to 32
.CLKIN_DIVIDE_BY_2("FALSE"), // TRUE/FALSE to enable CLKIN divide by two feature
.CLKIN_PERIOD(41.667), // Specify period of input clock
.CLKOUT_PHASE_SHIFT("NONE"), // Specify phase shift of NONE, FIXED or VARIABLE
.CLK_FEEDBACK("NONE"), // Specify clock feedback of NONE, 1X or 2X
.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), // SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
// an integer from 0 to 15
.DFS_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for frequency synthesis
.DLL_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for DLL
.DUTY_CYCLE_CORRECTION("TRUE"), // Duty cycle correction, TRUE or FALSE
.FACTORY_JF(16'hFFFF), // FACTORY JF values
// .LOC("DCM_X0Y0"),
.PHASE_SHIFT(0), // Amount of fixed phase shift from -255 to 255
.STARTUP_WAIT("TRUE") // Delay configuration DONE until DCM LOCK, TRUE/FALSE
) DCM_inst (
.CLK0(CLK0), // 0 degree DCM CLK output
.CLK180(CLK180), // 180 degree DCM CLK output
.CLK270(CLK270), // 270 degree DCM CLK output
.CLK2X(CLK2X), // 2X DCM CLK output
.CLK2X180(CLK2X180), // 2X, 180 degree DCM CLK out
.CLK90(CLK90), // 90 degree DCM CLK output
.CLKDV(CLKDV), // Divided DCM CLK out (CLKDV_DIVIDE)
.CLKFX(CLKFX), // DCM CLK synthesis out (M/D)
.CLKFX180(CLKFX180), // 180 degree CLK synthesis out
.LOCKED(LOCKED), // DCM LOCK status output
.PSDONE(PSDONE), // Dynamic phase adjust done output
.STATUS(STATUS), // 8-bit DCM status bits output
.CLKFB(CLKFB), // DCM clock feedback
.CLKIN(CLKIN), // Clock input (from IBUFG, BUFG or DCM)
.PSCLK(PSCLK), // Dynamic phase adjust clock input
.PSEN(PSEN), // Dynamic phase adjust enable input
.PSINCDEC(PSINCDEC), // Dynamic phase adjust increment/decrement
.RST(RST) // DCM asynchronous reset input
);
endmodule

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/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2011 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file cx4_datram.v when simulating
// the core, cx4_datram. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module cx4_datram(
clka,
wea,
addra,
dina,
douta,
clkb,
web,
addrb,
dinb,
doutb
);
input clka;
input [0 : 0] wea;
input [11 : 0] addra;
input [7 : 0] dina;
output [7 : 0] douta;
input clkb;
input [0 : 0] web;
input [11 : 0] addrb;
input [7 : 0] dinb;
output [7 : 0] doutb;
// synthesis translate_off
BLK_MEM_GEN_V6_2 #(
.C_ADDRA_WIDTH(12),
.C_ADDRB_WIDTH(12),
.C_ALGORITHM(1),
.C_AXI_ID_WIDTH(4),
.C_AXI_SLAVE_TYPE(0),
.C_AXI_TYPE(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(1),
.C_DEFAULT_DATA("77"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_FAMILY("spartan3"),
.C_HAS_AXI_ID(0),
.C_HAS_ENA(0),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INIT_FILE_NAME("no_coe_file_loaded"),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INTERFACE_TYPE(0),
.C_LOAD_INIT_FILE(0),
.C_MEM_TYPE(2),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(3072),
.C_READ_DEPTH_B(3072),
.C_READ_WIDTH_A(8),
.C_READ_WIDTH_B(8),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(1),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(3072),
.C_WRITE_DEPTH_B(3072),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(8),
.C_WRITE_WIDTH_B(8),
.C_XDEVICEFAMILY("spartan3")
)
inst (
.CLKA(clka),
.WEA(wea),
.ADDRA(addra),
.DINA(dina),
.DOUTA(douta),
.CLKB(clkb),
.WEB(web),
.ADDRB(addrb),
.DINB(dinb),
.DOUTB(doutb),
.RSTA(),
.ENA(),
.REGCEA(),
.RSTB(),
.ENB(),
.REGCEB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC(),
.S_ACLK(),
.S_ARESETN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.S_AXI_INJECTSBITERR(),
.S_AXI_INJECTDBITERR(),
.S_AXI_SBITERR(),
.S_AXI_DBITERR(),
.S_AXI_RDADDRECC()
);
// synthesis translate_on
endmodule

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##############################################################
#
# Xilinx Core Generator version 13.2
# Date: Sun Oct 16 18:54:12 2011
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# Generated from component: xilinx.com:ip:blk_mem_gen:6.2
#
##############################################################
#
# BEGIN Project Options
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = Verilog
SET device = xc3s400
SET devicefamily = spartan3
SET flowvendor = Other
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = pq208
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -4
SET verilogsim = true
SET vhdlsim = false
# END Project Options
# BEGIN Select
SELECT Block_Memory_Generator xilinx.com:ip:blk_mem_gen:6.2
# END Select
# BEGIN Parameters
CSET additional_inputs_for_power_estimation=false
CSET algorithm=Minimum_Area
CSET assume_synchronous_clk=true
CSET axi_id_width=4
CSET axi_slave_type=Memory_Slave
CSET axi_type=AXI4_Full
CSET byte_size=9
CSET coe_file=no_coe_file_loaded
CSET collision_warnings=ALL
CSET component_name=cx4_datram
CSET disable_collision_warnings=false
CSET disable_out_of_range_warnings=false
CSET ecc=false
CSET ecctype=No_ECC
CSET enable_a=Always_Enabled
CSET enable_b=Always_Enabled
CSET error_injection_type=Single_Bit_Error_Injection
CSET fill_remaining_memory_locations=true
CSET interface_type=Native
CSET load_init_file=false
CSET memory_type=True_Dual_Port_RAM
CSET operating_mode_a=WRITE_FIRST
CSET operating_mode_b=WRITE_FIRST
CSET output_reset_value_a=0
CSET output_reset_value_b=0
CSET pipeline_stages=0
CSET port_a_clock=100
CSET port_a_enable_rate=100
CSET port_a_write_rate=50
CSET port_b_clock=100
CSET port_b_enable_rate=100
CSET port_b_write_rate=50
CSET primitive=8kx2
CSET read_width_a=8
CSET read_width_b=8
CSET register_porta_input_of_softecc=false
CSET register_porta_output_of_memory_core=false
CSET register_porta_output_of_memory_primitives=false
CSET register_portb_output_of_memory_core=false
CSET register_portb_output_of_memory_primitives=false
CSET register_portb_output_of_softecc=false
CSET remaining_memory_locations=77
CSET reset_memory_latch_a=false
CSET reset_memory_latch_b=false
CSET reset_priority_a=CE
CSET reset_priority_b=CE
CSET reset_type=SYNC
CSET softecc=false
CSET use_axi_id=false
CSET use_byte_write_enable=false
CSET use_error_injection_pins=false
CSET use_regcea_pin=false
CSET use_regceb_pin=false
CSET use_rsta_pin=false
CSET use_rstb_pin=false
CSET write_depth_a=3072
CSET write_width_a=8
CSET write_width_b=8
# END Parameters
# BEGIN Extra information
MISC pkg_timestamp=2011-03-11T08:24:14.000Z
# END Extra information
GENERATE
# CRC: a7d60fbd

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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<header>
<!-- ISE source project file created by Project Navigator. -->
<!-- -->
<!-- This file contains project source information including a list of -->
<!-- project source files, project and process properties. This file, -->
<!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. -->
<!-- -->
<!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. -->
</header>
<version xil_pn:ise_version="13.2" xil_pn:schema_version="2"/>
<files>
<file xil_pn:name="cx4_datram.ngc" xil_pn:type="FILE_NGC">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
</file>
<file xil_pn:name="cx4_datram.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
<association xil_pn:name="Implementation" xil_pn:seqID="5"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="5"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="5"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="5"/>
</file>
</files>
<properties>
<property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device" xil_pn:value="xc3s400" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Family" xil_pn:value="Spartan3" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Module|cx4_datram" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="cx4_datram.ngc" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/cx4_datram" xil_pn:valueState="non-default"/>
<property xil_pn:name="Package" xil_pn:value="pq208" xil_pn:valueState="default"/>
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-4" xil_pn:valueState="non-default"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
<property xil_pn:name="PROP_DesignName" xil_pn:value="cx4_datram" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2011-10-16T20:54:53" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="1A4EA94132742A5DE9F22CC590B9E9A7" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
</properties>
<bindings/>
<libraries/>
<autoManagedFiles>
<!-- The following files are identified by `include statements in verilog -->
<!-- source files and are automatically managed by Project Navigator. -->
<!-- -->
<!-- Do not hand-edit this section, as it will be overwritten when the -->
<!-- project is analyzed based on files automatically identified as -->
<!-- include files. -->
</autoManagedFiles>
</project>

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/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2011 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file cx4_datrom.v when simulating
// the core, cx4_datrom. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module cx4_datrom(
clka,
wea,
addra,
dina,
clkb,
addrb,
doutb
);
input clka;
input [0 : 0] wea;
input [9 : 0] addra;
input [23 : 0] dina;
input clkb;
input [9 : 0] addrb;
output [23 : 0] doutb;
// synthesis translate_off
BLK_MEM_GEN_V6_2 #(
.C_ADDRA_WIDTH(10),
.C_ADDRB_WIDTH(10),
.C_ALGORITHM(1),
.C_AXI_ID_WIDTH(4),
.C_AXI_SLAVE_TYPE(0),
.C_AXI_TYPE(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(1),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_FAMILY("spartan3"),
.C_HAS_AXI_ID(0),
.C_HAS_ENA(0),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INIT_FILE_NAME("no_coe_file_loaded"),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INTERFACE_TYPE(0),
.C_LOAD_INIT_FILE(0),
.C_MEM_TYPE(1),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(1024),
.C_READ_DEPTH_B(1024),
.C_READ_WIDTH_A(24),
.C_READ_WIDTH_B(24),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(1024),
.C_WRITE_DEPTH_B(1024),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(24),
.C_WRITE_WIDTH_B(24),
.C_XDEVICEFAMILY("spartan3")
)
inst (
.CLKA(clka),
.WEA(wea),
.ADDRA(addra),
.DINA(dina),
.CLKB(clkb),
.ADDRB(addrb),
.DOUTB(doutb),
.RSTA(),
.ENA(),
.REGCEA(),
.DOUTA(),
.RSTB(),
.ENB(),
.REGCEB(),
.WEB(),
.DINB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC(),
.S_ACLK(),
.S_ARESETN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.S_AXI_INJECTSBITERR(),
.S_AXI_INJECTDBITERR(),
.S_AXI_SBITERR(),
.S_AXI_DBITERR(),
.S_AXI_RDADDRECC()
);
// synthesis translate_on
endmodule

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##############################################################
#
# Xilinx Core Generator version 13.2
# Date: Sun Oct 16 12:57:23 2011
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# Generated from component: xilinx.com:ip:blk_mem_gen:6.2
#
##############################################################
#
# BEGIN Project Options
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = Verilog
SET device = xc3s400
SET devicefamily = spartan3
SET flowvendor = Other
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = pq208
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -4
SET verilogsim = true
SET vhdlsim = false
# END Project Options
# BEGIN Select
SELECT Block_Memory_Generator xilinx.com:ip:blk_mem_gen:6.2
# END Select
# BEGIN Parameters
CSET additional_inputs_for_power_estimation=false
CSET algorithm=Minimum_Area
CSET assume_synchronous_clk=true
CSET axi_id_width=4
CSET axi_slave_type=Memory_Slave
CSET axi_type=AXI4_Full
CSET byte_size=9
CSET coe_file=no_coe_file_loaded
CSET collision_warnings=ALL
CSET component_name=cx4_datrom
CSET disable_collision_warnings=false
CSET disable_out_of_range_warnings=false
CSET ecc=false
CSET ecctype=No_ECC
CSET enable_a=Always_Enabled
CSET enable_b=Always_Enabled
CSET error_injection_type=Single_Bit_Error_Injection
CSET fill_remaining_memory_locations=false
CSET interface_type=Native
CSET load_init_file=false
CSET memory_type=Simple_Dual_Port_RAM
CSET operating_mode_a=WRITE_FIRST
CSET operating_mode_b=WRITE_FIRST
CSET output_reset_value_a=0
CSET output_reset_value_b=0
CSET pipeline_stages=0
CSET port_a_clock=100
CSET port_a_enable_rate=100
CSET port_a_write_rate=50
CSET port_b_clock=100
CSET port_b_enable_rate=100
CSET port_b_write_rate=0
CSET primitive=8kx2
CSET read_width_a=24
CSET read_width_b=24
CSET register_porta_input_of_softecc=false
CSET register_porta_output_of_memory_core=false
CSET register_porta_output_of_memory_primitives=false
CSET register_portb_output_of_memory_core=false
CSET register_portb_output_of_memory_primitives=false
CSET register_portb_output_of_softecc=false
CSET remaining_memory_locations=0
CSET reset_memory_latch_a=false
CSET reset_memory_latch_b=false
CSET reset_priority_a=CE
CSET reset_priority_b=CE
CSET reset_type=SYNC
CSET softecc=false
CSET use_axi_id=false
CSET use_byte_write_enable=false
CSET use_error_injection_pins=false
CSET use_regcea_pin=false
CSET use_regceb_pin=false
CSET use_rsta_pin=false
CSET use_rstb_pin=false
CSET write_depth_a=1024
CSET write_width_a=24
CSET write_width_b=24
# END Parameters
# BEGIN Extra information
MISC pkg_timestamp=2011-03-11T08:24:14.000Z
# END Extra information
GENERATE
# CRC: a25bf9a3

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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<header>
<!-- ISE source project file created by Project Navigator. -->
<!-- -->
<!-- This file contains project source information including a list of -->
<!-- project source files, project and process properties. This file, -->
<!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. -->
<!-- -->
<!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. -->
</header>
<version xil_pn:ise_version="13.2" xil_pn:schema_version="2"/>
<files>
<file xil_pn:name="cx4_datrom.ngc" xil_pn:type="FILE_NGC">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
</file>
<file xil_pn:name="cx4_datrom.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
<association xil_pn:name="Implementation" xil_pn:seqID="5"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="5"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="5"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="5"/>
</file>
</files>
<properties>
<property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device" xil_pn:value="xc3s400" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Family" xil_pn:value="Spartan3" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Module|cx4_datrom" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="cx4_datrom.ngc" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/cx4_datrom" xil_pn:valueState="non-default"/>
<property xil_pn:name="Package" xil_pn:value="pq208" xil_pn:valueState="default"/>
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-4" xil_pn:valueState="non-default"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
<property xil_pn:name="PROP_DesignName" xil_pn:value="cx4_datrom" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2011-10-16T14:58:14" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="3B4E0775D81ACD3D9CCAB1608687B690" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
</properties>
<bindings/>
<libraries/>
<autoManagedFiles>
<!-- The following files are identified by `include statements in verilog -->
<!-- source files and are automatically managed by Project Navigator. -->
<!-- -->
<!-- Do not hand-edit this section, as it will be overwritten when the -->
<!-- project is analyzed based on files automatically identified as -->
<!-- include files. -->
</autoManagedFiles>
</project>

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##############################################################
#
# Xilinx Core Generator version 13.2
# Date: Sun Oct 30 20:22:20 2011
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# Generated from component: xilinx.com:ip:mult_gen:11.2
#
##############################################################
#
# BEGIN Project Options
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = Verilog
SET device = xc3s400
SET devicefamily = spartan3
SET flowvendor = Other
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = pq208
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -4
SET verilogsim = true
SET vhdlsim = false
# END Project Options
# BEGIN Select
SELECT Multiplier xilinx.com:ip:mult_gen:11.2
# END Select
# BEGIN Parameters
CSET ccmimp=Distributed_Memory
CSET clockenable=true
CSET component_name=cx4_mul
CSET constvalue=129
CSET internaluser=0
CSET multiplier_construction=Use_Mults
CSET multtype=Parallel_Multiplier
CSET optgoal=Speed
CSET outputwidthhigh=47
CSET outputwidthlow=0
CSET pipestages=2
CSET portatype=Signed
CSET portawidth=24
CSET portbtype=Signed
CSET portbwidth=24
CSET roundpoint=0
CSET sclrcepriority=SCLR_Overrides_CE
CSET syncclear=false
CSET use_custom_output_width=false
CSET userounding=false
CSET zerodetect=false
# END Parameters
# BEGIN Extra information
MISC pkg_timestamp=2011-06-21T06:26:54.000Z
# END Extra information
GENERATE
# CRC: 4f144c3

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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<header>
<!-- ISE source project file created by Project Navigator. -->
<!-- -->
<!-- This file contains project source information including a list of -->
<!-- project source files, project and process properties. This file, -->
<!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. -->
<!-- -->
<!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. -->
</header>
<version xil_pn:ise_version="13.2" xil_pn:schema_version="2"/>
<files>
<file xil_pn:name="cx4_mul.ngc" xil_pn:type="FILE_NGC">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
</file>
<file xil_pn:name="cx4_mul.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="4"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="4"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="4"/>
</file>
</files>
<properties>
<property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Use Location Constraints" xil_pn:value="Always" xil_pn:valueState="default"/>
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<bindings/>
<libraries/>
<autoManagedFiles>
<!-- The following files are identified by `include statements in verilog -->
<!-- source files and are automatically managed by Project Navigator. -->
<!-- -->
<!-- Do not hand-edit this section, as it will be overwritten when the -->
<!-- project is analyzed based on files automatically identified as -->
<!-- include files. -->
</autoManagedFiles>
</project>

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verilog/sd2snes_cx4/ipcore_dir/cx4_pgmrom.v Normal file
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/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2011 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file cx4_pgmrom.v when simulating
// the core, cx4_pgmrom. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module cx4_pgmrom(
clka,
wea,
addra,
dina,
clkb,
addrb,
doutb
);
input clka;
input [0 : 0] wea;
input [9 : 0] addra;
input [7 : 0] dina;
input clkb;
input [8 : 0] addrb;
output [15 : 0] doutb;
// synthesis translate_off
BLK_MEM_GEN_V6_2 #(
.C_ADDRA_WIDTH(10),
.C_ADDRB_WIDTH(9),
.C_ALGORITHM(1),
.C_AXI_ID_WIDTH(4),
.C_AXI_SLAVE_TYPE(0),
.C_AXI_TYPE(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(1),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_FAMILY("spartan3"),
.C_HAS_AXI_ID(0),
.C_HAS_ENA(0),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INIT_FILE_NAME("cx4_pgmrom.mif"),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INTERFACE_TYPE(0),
.C_LOAD_INIT_FILE(1),
.C_MEM_TYPE(1),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(1024),
.C_READ_DEPTH_B(512),
.C_READ_WIDTH_A(8),
.C_READ_WIDTH_B(16),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(1024),
.C_WRITE_DEPTH_B(512),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(8),
.C_WRITE_WIDTH_B(16),
.C_XDEVICEFAMILY("spartan3")
)
inst (
.CLKA(clka),
.WEA(wea),
.ADDRA(addra),
.DINA(dina),
.CLKB(clkb),
.ADDRB(addrb),
.DOUTB(doutb),
.RSTA(),
.ENA(),
.REGCEA(),
.DOUTA(),
.RSTB(),
.ENB(),
.REGCEB(),
.WEB(),
.DINB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC(),
.S_ACLK(),
.S_ARESETN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.S_AXI_INJECTSBITERR(),
.S_AXI_INJECTDBITERR(),
.S_AXI_SBITERR(),
.S_AXI_DBITERR(),
.S_AXI_RDADDRECC()
);
// synthesis translate_on
endmodule

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##############################################################
#
# Xilinx Core Generator version 13.2
# Date: Sun Oct 23 22:07:47 2011
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# Generated from component: xilinx.com:ip:blk_mem_gen:6.2
#
##############################################################
#
# BEGIN Project Options
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = Verilog
SET device = xc3s400
SET devicefamily = spartan3
SET flowvendor = Other
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = pq208
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -4
SET verilogsim = true
SET vhdlsim = false
# END Project Options
# BEGIN Select
SELECT Block_Memory_Generator xilinx.com:ip:blk_mem_gen:6.2
# END Select
# BEGIN Parameters
CSET additional_inputs_for_power_estimation=false
CSET algorithm=Minimum_Area
CSET assume_synchronous_clk=true
CSET axi_id_width=4
CSET axi_slave_type=Memory_Slave
CSET axi_type=AXI4_Full
CSET byte_size=9
CSET coe_file=/home/ikari/prj/sd2snes/verilog/sd2snes_cx4/cx4_e.coe
CSET collision_warnings=ALL
CSET component_name=cx4_pgmrom
CSET disable_collision_warnings=false
CSET disable_out_of_range_warnings=false
CSET ecc=false
CSET ecctype=No_ECC
CSET enable_a=Always_Enabled
CSET enable_b=Always_Enabled
CSET error_injection_type=Single_Bit_Error_Injection
CSET fill_remaining_memory_locations=false
CSET interface_type=Native
CSET load_init_file=true
CSET memory_type=Simple_Dual_Port_RAM
CSET operating_mode_a=WRITE_FIRST
CSET operating_mode_b=WRITE_FIRST
CSET output_reset_value_a=0
CSET output_reset_value_b=0
CSET pipeline_stages=0
CSET port_a_clock=100
CSET port_a_enable_rate=100
CSET port_a_write_rate=50
CSET port_b_clock=100
CSET port_b_enable_rate=100
CSET port_b_write_rate=0
CSET primitive=8kx2
CSET read_width_a=8
CSET read_width_b=16
CSET register_porta_input_of_softecc=false
CSET register_porta_output_of_memory_core=false
CSET register_porta_output_of_memory_primitives=false
CSET register_portb_output_of_memory_core=false
CSET register_portb_output_of_memory_primitives=false
CSET register_portb_output_of_softecc=false
CSET remaining_memory_locations=0
CSET reset_memory_latch_a=false
CSET reset_memory_latch_b=false
CSET reset_priority_a=CE
CSET reset_priority_b=CE
CSET reset_type=SYNC
CSET softecc=false
CSET use_axi_id=false
CSET use_byte_write_enable=false
CSET use_error_injection_pins=false
CSET use_regcea_pin=false
CSET use_regceb_pin=false
CSET use_rsta_pin=false
CSET use_rstb_pin=false
CSET write_depth_a=1024
CSET write_width_a=8
CSET write_width_b=16
# END Parameters
# BEGIN Extra information
MISC pkg_timestamp=2011-03-11T08:24:14.000Z
# END Extra information
GENERATE
# CRC: a9280b11

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verilog/sd2snes_cx4/ipcore_dir/cx4_pgmrom.xise Normal file
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<header>
<!-- ISE source project file created by Project Navigator. -->
<!-- -->
<!-- This file contains project source information including a list of -->
<!-- project source files, project and process properties. This file, -->
<!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. -->
<!-- -->
<!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. -->
</header>
<version xil_pn:ise_version="13.2" xil_pn:schema_version="2"/>
<files>
<file xil_pn:name="cx4_pgmrom.ngc" xil_pn:type="FILE_NGC">
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<properties>
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<property xil_pn:name="Device" xil_pn:value="xc3s400" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Package" xil_pn:value="pq208" xil_pn:valueState="default"/>
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-4" xil_pn:valueState="non-default"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
<property xil_pn:name="PROP_DesignName" xil_pn:value="cx4_pgmrom" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2011-10-24T00:08:31" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="C14775871011A35EE55463DDAA37D8AF" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
</properties>
<bindings/>
<libraries/>
<autoManagedFiles>
<!-- The following files are identified by `include statements in verilog -->
<!-- source files and are automatically managed by Project Navigator. -->
<!-- -->
<!-- Do not hand-edit this section, as it will be overwritten when the -->
<!-- project is analyzed based on files automatically identified as -->
<!-- include files. -->
</autoManagedFiles>
</project>

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/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2011 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file dac_buf.v when simulating
// the core, dac_buf. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module dac_buf(
clka,
wea,
addra,
dina,
clkb,
addrb,
doutb
);
input clka;
input [0 : 0] wea;
input [10 : 0] addra;
input [7 : 0] dina;
input clkb;
input [8 : 0] addrb;
output [31 : 0] doutb;
// synthesis translate_off
BLK_MEM_GEN_V6_1 #(
.C_ADDRA_WIDTH(11),
.C_ADDRB_WIDTH(9),
.C_ALGORITHM(1),
.C_AXI_ID_WIDTH(4),
.C_AXI_SLAVE_TYPE(0),
.C_AXI_TYPE(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(1),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_FAMILY("spartan3"),
.C_HAS_AXI_ID(0),
.C_HAS_ENA(0),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INIT_FILE_NAME("no_coe_file_loaded"),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INTERFACE_TYPE(0),
.C_LOAD_INIT_FILE(0),
.C_MEM_TYPE(1),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(2048),
.C_READ_DEPTH_B(512),
.C_READ_WIDTH_A(8),
.C_READ_WIDTH_B(32),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(2048),
.C_WRITE_DEPTH_B(512),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(8),
.C_WRITE_WIDTH_B(32),
.C_XDEVICEFAMILY("spartan3")
)
inst (
.CLKA(clka),
.WEA(wea),
.ADDRA(addra),
.DINA(dina),
.CLKB(clkb),
.ADDRB(addrb),
.DOUTB(doutb),
.RSTA(),
.ENA(),
.REGCEA(),
.DOUTA(),
.RSTB(),
.ENB(),
.REGCEB(),
.WEB(),
.DINB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC(),
.S_ACLK(),
.S_ARESETN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.S_AXI_INJECTSBITERR(),
.S_AXI_INJECTDBITERR(),
.S_AXI_SBITERR(),
.S_AXI_DBITERR(),
.S_AXI_RDADDRECC()
);
// synthesis translate_on
endmodule

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##############################################################
#
# Xilinx Core Generator version 13.2
# Date: Mon Oct 10 19:47:34 2011
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# Generated from component: xilinx.com:ip:blk_mem_gen:6.1
#
##############################################################
#
# BEGIN Project Options
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = Verilog
SET device = xc3s400
SET devicefamily = spartan3
SET flowvendor = Foundation_ISE
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = pq208
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -4
SET verilogsim = true
SET vhdlsim = false
# END Project Options
# BEGIN Select
SELECT Block_Memory_Generator xilinx.com:ip:blk_mem_gen:6.1
# END Select
# BEGIN Parameters
CSET additional_inputs_for_power_estimation=false
CSET algorithm=Minimum_Area
CSET assume_synchronous_clk=true
CSET axi_id_width=4
CSET axi_slave_type=Memory_Slave
CSET axi_type=AXI4_Full
CSET byte_size=9
CSET coe_file=no_coe_file_loaded
CSET collision_warnings=ALL
CSET component_name=dac_buf
CSET disable_collision_warnings=false
CSET disable_out_of_range_warnings=false
CSET ecc=false
CSET ecctype=No_ECC
CSET enable_a=Always_Enabled
CSET enable_b=Always_Enabled
CSET error_injection_type=Single_Bit_Error_Injection
CSET fill_remaining_memory_locations=false
CSET interface_type=Native
CSET load_init_file=false
CSET memory_type=Simple_Dual_Port_RAM
CSET operating_mode_a=WRITE_FIRST
CSET operating_mode_b=WRITE_FIRST
CSET output_reset_value_a=0
CSET output_reset_value_b=0
CSET pipeline_stages=0
CSET port_a_clock=100
CSET port_a_enable_rate=100
CSET port_a_write_rate=50
CSET port_b_clock=100
CSET port_b_enable_rate=100
CSET port_b_write_rate=0
CSET primitive=8kx2
CSET read_width_a=8
CSET read_width_b=32
CSET register_porta_input_of_softecc=false
CSET register_porta_output_of_memory_core=false
CSET register_porta_output_of_memory_primitives=false
CSET register_portb_output_of_memory_core=false
CSET register_portb_output_of_memory_primitives=false
CSET register_portb_output_of_softecc=false
CSET remaining_memory_locations=0
CSET reset_memory_latch_a=false
CSET reset_memory_latch_b=false
CSET reset_priority_a=CE
CSET reset_priority_b=CE
CSET reset_type=SYNC
CSET softecc=false
CSET use_axi_id=false
CSET use_byte_write_enable=false
CSET use_error_injection_pins=false
CSET use_regcea_pin=false
CSET use_regceb_pin=false
CSET use_rsta_pin=false
CSET use_rstb_pin=false
CSET write_depth_a=2048
CSET write_width_a=8
CSET write_width_b=32
# END Parameters
# BEGIN Extra information
MISC pkg_timestamp=2011-06-21T06:43:52.000Z
# END Extra information
GENERATE
# CRC: 60863d15

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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<header>
<!-- ISE source project file created by Project Navigator. -->
<!-- -->
<!-- This file contains project source information including a list of -->
<!-- project source files, project and process properties. This file, -->
<!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. -->
<!-- -->
<!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. -->
</header>
<version xil_pn:ise_version="13.2" xil_pn:schema_version="2"/>
<files>
<file xil_pn:name="dac_buf.ngc" xil_pn:type="FILE_NGC">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="dac_buf.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="5"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="5"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="5"/>
</file>
<file xil_pn:name="dac_buf.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="7"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="7"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="7"/>
</file>
</files>
<properties>
<property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device" xil_pn:value="xc3s400" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Family" xil_pn:value="Spartan3" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|dac_buf|dac_buf_a" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="dac_buf.vhd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/dac_buf" xil_pn:valueState="non-default"/>
<property xil_pn:name="Package" xil_pn:value="pq208" xil_pn:valueState="default"/>
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-4" xil_pn:valueState="non-default"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
<property xil_pn:name="PROP_DesignName" xil_pn:value="dac_buf" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2011-06-14T00:12:56" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="014920D0A865D4E8840F795EDFB8F8B9" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
</properties>
<bindings/>
<libraries/>
<autoManagedFiles>
<!-- The following files are identified by `include statements in verilog -->
<!-- source files and are automatically managed by Project Navigator. -->
<!-- -->
<!-- Do not hand-edit this section, as it will be overwritten when the -->
<!-- project is analyzed based on files automatically identified as -->
<!-- include files. -->
</autoManagedFiles>
</project>

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/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2011 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file msu_databuf.v when simulating
// the core, msu_databuf. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module msu_databuf(
clka,
wea,
addra,
dina,
clkb,
addrb,
doutb
);
input clka;
input [0 : 0] wea;
input [13 : 0] addra;
input [7 : 0] dina;
input clkb;
input [13 : 0] addrb;
output [7 : 0] doutb;
// synthesis translate_off
BLK_MEM_GEN_V6_1 #(
.C_ADDRA_WIDTH(14),
.C_ADDRB_WIDTH(14),
.C_ALGORITHM(1),
.C_AXI_ID_WIDTH(4),
.C_AXI_SLAVE_TYPE(0),
.C_AXI_TYPE(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(1),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_FAMILY("spartan3"),
.C_HAS_AXI_ID(0),
.C_HAS_ENA(0),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INIT_FILE_NAME("no_coe_file_loaded"),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INTERFACE_TYPE(0),
.C_LOAD_INIT_FILE(0),
.C_MEM_TYPE(1),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(16384),
.C_READ_DEPTH_B(16384),
.C_READ_WIDTH_A(8),
.C_READ_WIDTH_B(8),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(16384),
.C_WRITE_DEPTH_B(16384),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(8),
.C_WRITE_WIDTH_B(8),
.C_XDEVICEFAMILY("spartan3")
)
inst (
.CLKA(clka),
.WEA(wea),
.ADDRA(addra),
.DINA(dina),
.CLKB(clkb),
.ADDRB(addrb),
.DOUTB(doutb),
.RSTA(),
.ENA(),
.REGCEA(),
.DOUTA(),
.RSTB(),
.ENB(),
.REGCEB(),
.WEB(),
.DINB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC(),
.S_ACLK(),
.S_ARESETN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.S_AXI_INJECTSBITERR(),
.S_AXI_INJECTDBITERR(),
.S_AXI_SBITERR(),
.S_AXI_DBITERR(),
.S_AXI_RDADDRECC()
);
// synthesis translate_on
endmodule

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##############################################################
#
# Xilinx Core Generator version 13.2
# Date: Mon Oct 10 19:48:38 2011
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# Generated from component: xilinx.com:ip:blk_mem_gen:6.1
#
##############################################################
#
# BEGIN Project Options
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = Verilog
SET device = xc3s400
SET devicefamily = spartan3
SET flowvendor = Foundation_ISE
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = pq208
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -4
SET verilogsim = true
SET vhdlsim = false
# END Project Options
# BEGIN Select
SELECT Block_Memory_Generator xilinx.com:ip:blk_mem_gen:6.1
# END Select
# BEGIN Parameters
CSET additional_inputs_for_power_estimation=false
CSET algorithm=Minimum_Area
CSET assume_synchronous_clk=true
CSET axi_id_width=4
CSET axi_slave_type=Memory_Slave
CSET axi_type=AXI4_Full
CSET byte_size=9
CSET coe_file=no_coe_file_loaded
CSET collision_warnings=ALL
CSET component_name=msu_databuf
CSET disable_collision_warnings=false
CSET disable_out_of_range_warnings=false
CSET ecc=false
CSET ecctype=No_ECC
CSET enable_a=Always_Enabled
CSET enable_b=Always_Enabled
CSET error_injection_type=Single_Bit_Error_Injection
CSET fill_remaining_memory_locations=false
CSET interface_type=Native
CSET load_init_file=false
CSET memory_type=Simple_Dual_Port_RAM
CSET operating_mode_a=WRITE_FIRST
CSET operating_mode_b=WRITE_FIRST
CSET output_reset_value_a=0
CSET output_reset_value_b=0
CSET pipeline_stages=0
CSET port_a_clock=100
CSET port_a_enable_rate=100
CSET port_a_write_rate=50
CSET port_b_clock=100
CSET port_b_enable_rate=100
CSET port_b_write_rate=0
CSET primitive=8kx2
CSET read_width_a=8
CSET read_width_b=8
CSET register_porta_input_of_softecc=false
CSET register_porta_output_of_memory_core=false
CSET register_porta_output_of_memory_primitives=false
CSET register_portb_output_of_memory_core=false
CSET register_portb_output_of_memory_primitives=false
CSET register_portb_output_of_softecc=false
CSET remaining_memory_locations=0
CSET reset_memory_latch_a=false
CSET reset_memory_latch_b=false
CSET reset_priority_a=CE
CSET reset_priority_b=CE
CSET reset_type=SYNC
CSET softecc=false
CSET use_axi_id=false
CSET use_byte_write_enable=false
CSET use_error_injection_pins=false
CSET use_regcea_pin=false
CSET use_regceb_pin=false
CSET use_rsta_pin=false
CSET use_rstb_pin=false
CSET write_depth_a=16384
CSET write_width_a=8
CSET write_width_b=8
# END Parameters
# BEGIN Extra information
MISC pkg_timestamp=2011-06-21T06:43:52.000Z
# END Extra information
GENERATE
# CRC: bebc21bb

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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<header>
<!-- ISE source project file created by Project Navigator. -->
<!-- -->
<!-- This file contains project source information including a list of -->
<!-- project source files, project and process properties. This file, -->
<!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. -->
<!-- -->
<!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. -->
</header>
<version xil_pn:ise_version="13.2" xil_pn:schema_version="2"/>
<files>
<file xil_pn:name="msu_databuf.ngc" xil_pn:type="FILE_NGC">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
</file>
<file xil_pn:name="msu_databuf.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
<association xil_pn:name="Implementation" xil_pn:seqID="5"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="5"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="5"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="5"/>
</file>
<file xil_pn:name="msu_databuf.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>
<association xil_pn:name="Implementation" xil_pn:seqID="7"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="7"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="7"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="7"/>
</file>
</files>
<properties>
<property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device" xil_pn:value="xc3s400" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Family" xil_pn:value="Spartan3" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|msu_databuf|msu_databuf_a" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="msu_databuf.vhd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/msu_databuf" xil_pn:valueState="non-default"/>
<property xil_pn:name="Package" xil_pn:value="pq208" xil_pn:valueState="default"/>
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-4" xil_pn:valueState="non-default"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
<property xil_pn:name="PROP_DesignName" xil_pn:value="msu_databuf" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2011-06-14T00:14:59" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="7648B026E1C3D2C8277D0047EFC3229D" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
</properties>
<bindings/>
<libraries/>
<autoManagedFiles>
<!-- The following files are identified by `include statements in verilog -->
<!-- source files and are automatically managed by Project Navigator. -->
<!-- -->
<!-- Do not hand-edit this section, as it will be overwritten when the -->
<!-- project is analyzed based on files automatically identified as -->
<!-- include files. -->
</autoManagedFiles>
</project>

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verilog/sd2snes_cx4/main.v Normal file
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`timescale 1 ns / 1 ns
//////////////////////////////////////////////////////////////////////////////////
// Company: Rehkopf
// Engineer: Rehkopf
//
// Create Date: 01:13:46 05/09/2009
// Design Name:
// Module Name: main
// Project Name:
// Target Devices:
// Tool versions:
// Description: Master Control FSM
//
// Dependencies: address
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module main(
/* input clock */
input CLKIN,
/* SNES signals */
input [23:0] SNES_ADDR,
input SNES_READ,
input SNES_WRITE,
input SNES_CS,
inout [7:0] SNES_DATA,
input SNES_CPU_CLK,
input SNES_REFRESH,
output SNES_IRQ,
output SNES_DATABUS_OE,
output SNES_DATABUS_DIR,
input SNES_SYSCLK,
/* SRAM signals */
/* Bus 1: PSRAM, 128Mbit, 16bit, 70ns */
inout [15:0] ROM_DATA,
output [22:0] ROM_ADDR,
output ROM_CE,
output ROM_OE,
output ROM_WE,
output ROM_BHE,
output ROM_BLE,
/* Bus 2: SRAM, 4Mbit, 8bit, 45ns */
inout [7:0] RAM_DATA,
output [18:0] RAM_ADDR,
output RAM_CE,
output RAM_OE,
output RAM_WE,
/* MCU signals */
input SPI_MOSI,
inout SPI_MISO,
input SPI_SS,
inout SPI_SCK,
input MCU_OVR,
output MCU_RDY,
output DAC_MCLK,
output DAC_LRCK,
output DAC_SDOUT,
/* SD signals */
input [3:0] SD_DAT,
inout SD_CMD,
inout SD_CLK,
/* debug */
output p113_out
);
wire [7:0] spi_cmd_data;
wire [7:0] spi_param_data;
wire [7:0] spi_input_data;
wire [31:0] spi_byte_cnt;
wire [2:0] spi_bit_cnt;
wire [23:0] MCU_ADDR;
wire [2:0] MAPPER;
wire [23:0] SAVERAM_MASK;
wire [23:0] ROM_MASK;
wire [7:0] SD_DMA_SRAM_DATA;
wire [1:0] SD_DMA_TGT;
wire [10:0] SD_DMA_PARTIAL_START;
wire [10:0] SD_DMA_PARTIAL_END;
wire [10:0] dac_addr;
//wire [7:0] dac_volume;
wire [7:0] msu_volumerq_out;
wire [6:0] msu_status_out;
wire [31:0] msu_addressrq_out;
wire [15:0] msu_trackrq_out;
wire [13:0] msu_write_addr;
wire [13:0] msu_ptr_addr;
wire [7:0] MSU_SNES_DATA_IN;
wire [7:0] MSU_SNES_DATA_OUT;
wire [5:0] msu_status_reset_bits;
wire [5:0] msu_status_set_bits;
wire [7:0] CX4_SNES_DATA_IN;
wire [7:0] CX4_SNES_DATA_OUT;
wire [23:0] MAPPED_SNES_ADDR;
wire ROM_ADDR0;
wire [23:0] cx4_datrom_data;
wire [9:0] cx4_datrom_addr;
wire cx4_datrom_we;
sd_dma snes_sd_dma(
.CLK(CLK2),
.SD_DAT(SD_DAT),
.SD_CLK(SD_CLK),
.SD_DMA_EN(SD_DMA_EN),
.SD_DMA_STATUS(SD_DMA_STATUS),
.SD_DMA_SRAM_WE(SD_DMA_SRAM_WE),
.SD_DMA_SRAM_DATA(SD_DMA_SRAM_DATA),
.SD_DMA_NEXTADDR(SD_DMA_NEXTADDR),
.SD_DMA_PARTIAL(SD_DMA_PARTIAL),
.SD_DMA_PARTIAL_START(SD_DMA_PARTIAL_START),
.SD_DMA_PARTIAL_END(SD_DMA_PARTIAL_END)
);
wire SD_DMA_TO_ROM = (SD_DMA_STATUS && (SD_DMA_TGT == 2'b00));
dac snes_dac(
.clkin(CLK2),
.sysclk(SNES_SYSCLK),
.mclk(DAC_MCLK),
.lrck(DAC_LRCK),
.sdout(DAC_SDOUT),
.we(SD_DMA_TGT==2'b01 ? SD_DMA_SRAM_WE : 1'b1),
.pgm_address(dac_addr),
.pgm_data(SD_DMA_SRAM_DATA),
.DAC_STATUS(DAC_STATUS),
.volume(msu_volumerq_out),
.vol_latch(msu_volume_latch_out),
.play(dac_play),
.reset(dac_reset)
);
msu snes_msu (
.clkin(CLK2),
.enable(msu_enable),
.pgm_address(msu_write_addr),
.pgm_data(SD_DMA_SRAM_DATA),
.pgm_we(SD_DMA_TGT==2'b10 ? SD_DMA_SRAM_WE : 1'b1),
.reg_addr(SNES_ADDR[2:0]),
.reg_data_in(MSU_SNES_DATA_IN),
.reg_data_out(MSU_SNES_DATA_OUT),
.reg_oe(SNES_READ),
.reg_we(SNES_WRITE),
.status_out(msu_status_out),
.volume_out(msu_volumerq_out),
.volume_latch_out(msu_volume_latch_out),
.addr_out(msu_addressrq_out),
.track_out(msu_trackrq_out),
.status_reset_bits(msu_status_reset_bits),
.status_set_bits(msu_status_set_bits),
.status_reset_we(msu_status_reset_we),
.msu_address_ext(msu_ptr_addr),
.msu_address_ext_write(msu_addr_reset)
);
spi snes_spi(
.clk(CLK2),
.MOSI(SPI_MOSI),
.MISO(SPI_MISO),
.SSEL(SPI_SS),
.SCK(SPI_SCK),
.cmd_ready(spi_cmd_ready),
.param_ready(spi_param_ready),
.cmd_data(spi_cmd_data),
.param_data(spi_param_data),
.endmessage(spi_endmessage),
.startmessage(spi_startmessage),
.input_data(spi_input_data),
.byte_cnt(spi_byte_cnt),
.bit_cnt(spi_bit_cnt)
);
reg [7:0] MCU_DINr;
wire [7:0] MCU_DOUT;
mcu_cmd snes_mcu_cmd(
.clk(CLK2),
.snes_sysclk(SNES_SYSCLK),
.cmd_ready(spi_cmd_ready),
.param_ready(spi_param_ready),
.cmd_data(spi_cmd_data),
.param_data(spi_param_data),
.mcu_mapper(MAPPER),
.mcu_write(MCU_WRITE),
.mcu_data_in(MCU_DINr),
.mcu_data_out(MCU_DOUT),
.spi_byte_cnt(spi_byte_cnt),
.spi_bit_cnt(spi_bit_cnt),
.spi_data_out(spi_input_data),
.addr_out(MCU_ADDR),
.saveram_mask_out(SAVERAM_MASK),
.rom_mask_out(ROM_MASK),
.SD_DMA_EN(SD_DMA_EN),
.SD_DMA_STATUS(SD_DMA_STATUS),
.SD_DMA_NEXTADDR(SD_DMA_NEXTADDR),
.SD_DMA_SRAM_DATA(SD_DMA_SRAM_DATA),
.SD_DMA_SRAM_WE(SD_DMA_SRAM_WE),
.SD_DMA_TGT(SD_DMA_TGT),
.SD_DMA_PARTIAL(SD_DMA_PARTIAL),
.SD_DMA_PARTIAL_START(SD_DMA_PARTIAL_START),
.SD_DMA_PARTIAL_END(SD_DMA_PARTIAL_END),
.dac_addr_out(dac_addr),
.DAC_STATUS(DAC_STATUS),
// .dac_volume_out(dac_volume),
// .dac_volume_latch_out(dac_vol_latch),
.dac_play_out(dac_play),
.dac_reset_out(dac_reset),
.msu_addr_out(msu_write_addr),
.MSU_STATUS(msu_status_out),
.msu_status_reset_out(msu_status_reset_bits),
.msu_status_set_out(msu_status_set_bits),
.msu_status_reset_we(msu_status_reset_we),
.msu_volumerq(msu_volumerq_out),
.msu_addressrq(msu_addressrq_out),
.msu_trackrq(msu_trackrq_out),
.msu_ptr_out(msu_ptr_addr),
.msu_reset_out(msu_addr_reset),
.mcu_rrq(MCU_RRQ),
.mcu_wrq(MCU_WRQ),
.mcu_rq_rdy(MCU_RDY),
.use_msu1(use_msu1),
.cx4_datrom_addr_out(cx4_datrom_addr),
.cx4_datrom_data_out(cx4_datrom_data),
.cx4_datrom_we_out(cx4_datrom_we),
.cx4_reset_out(cx4_reset)
);
wire [7:0] DCM_STATUS;
// dcm1: dfs 4x
my_dcm snes_dcm(
.CLKIN(CLKIN),
.CLKFX(CLK2),
.LOCKED(DCM_LOCKED),
.RST(DCM_RST),
.STATUS(DCM_STATUS)
);
assign DCM_RST=0;
reg [5:0] SNES_READr;
reg [5:0] SNES_WRITEr;
reg [5:0] SNES_CPU_CLKr;
wire SNES_RD_start = (SNES_READr == 6'b111110);
wire SNES_WR_start = (SNES_WRITEr == 6'b111110);
wire SNES_cycle_start = (SNES_CPU_CLKr[5:0] == 6'b000001);
wire SNES_cycle_end = (SNES_CPU_CLKr[5:0] == 6'b111110);
always @(posedge CLK2) begin
SNES_READr <= {SNES_READr[4:0], SNES_READ};
SNES_WRITEr <= {SNES_WRITEr[4:0], SNES_WRITE};
SNES_CPU_CLKr <= {SNES_CPU_CLKr[4:0], SNES_CPU_CLK};
end
address snes_addr(
.CLK(CLK2),
.MAPPER(MAPPER),
.SNES_ADDR(SNES_ADDR), // requested address from SNES
.SNES_CS(SNES_CS),
.ROM_ADDR(MAPPED_SNES_ADDR), // Address to request from SRAM (active low)
.ROM_SEL(ROM_SEL), // which SRAM unit to access
.IS_SAVERAM(IS_SAVERAM),
.IS_ROM(IS_ROM),
.IS_WRITABLE(IS_WRITABLE),
.SAVERAM_MASK(SAVERAM_MASK),
.ROM_MASK(ROM_MASK),
.use_msu1(use_msu1),
//MSU-1
.msu_enable(msu_enable),
//CX4
.cx4_enable(cx4_enable),
.cx4_vect_enable(cx4_vect_enable)
);
reg [7:0] CX4_DINr;
wire [23:0] CX4_ADDR;
cx4 snes_cx4 (
.DI(CX4_SNES_DATA_IN),
.DO(CX4_SNES_DATA_OUT),
.ADDR(SNES_ADDR[12:0]),
.CS(cx4_enable),
.SNES_VECT_EN(cx4_vect_enable),
.nRD(SNES_READ),
.nWR(SNES_WRITE),
.CLK(CLK2),
.DATROM_DI(cx4_datrom_data),
.DATROM_WE(cx4_datrom_we),
.DATROM_ADDR(cx4_datrom_addr),
.BUS_DI(CX4_DINr),
.BUS_ADDR(CX4_ADDR),
.BUS_RRQ(CX4_RRQ),
.BUS_RDY(CX4_RDY),
.cx4_active(cx4_active)
);
parameter MODE_SNES = 1'b0;
parameter MODE_MCU = 1'b1;
parameter ST_IDLE = 21'b000000000000000000001;
parameter ST_SNES_RD_ADDR = 21'b000000000000000000010;
parameter ST_SNES_RD_WAIT = 21'b000000000000000000100;
parameter ST_SNES_RD_END = 21'b000000000000000001000;
parameter ST_SNES_WR_ADDR = 21'b000000000000000010000;
parameter ST_SNES_WR_WAIT1= 21'b000000000000000100000;
parameter ST_SNES_WR_DATA = 21'b000000000000001000000;
parameter ST_SNES_WR_WAIT2= 21'b000000000000010000000;
parameter ST_SNES_WR_END = 21'b000000000000100000000;
parameter ST_MCU_RD_ADDR = 21'b000000000001000000000;
parameter ST_MCU_RD_WAIT = 21'b000000000010000000000;
parameter ST_MCU_RD_WAIT2 = 21'b000000000100000000000;
parameter ST_MCU_RD_END = 21'b000000001000000000000;
parameter ST_MCU_WR_ADDR = 21'b000000010000000000000;
parameter ST_MCU_WR_WAIT = 21'b000000100000000000000;
parameter ST_MCU_WR_WAIT2 = 21'b000001000000000000000;
parameter ST_MCU_WR_END = 21'b000010000000000000000;
parameter ST_CX4_RD_ADDR = 21'b000100000000000000000;
parameter ST_CX4_RD_WAIT = 21'b001000000000000000000;
parameter ST_CX4_RD_WAIT2 = 21'b010000000000000000000;
parameter ST_CX4_RD_END = 21'b100000000000000000000;
parameter ROM_RD_WAIT = 4'h4;
parameter ROM_RD_WAIT_MCU = 4'h6;
parameter ROM_WR_WAIT1 = 4'h2;
parameter ROM_WR_WAIT2 = 4'h3;
parameter ROM_WR_WAIT_MCU = 4'h6;
parameter ROM_RD_WAIT_CX4 = 4'h6;
reg [20:0] STATE;
initial STATE = ST_IDLE;
assign MSU_SNES_DATA_IN = SNES_DATA;
assign CX4_SNES_DATA_IN = SNES_DATA;
reg [7:0] SNES_DINr;
reg [7:0] ROM_DOUTr;
assign SNES_DATA = (!SNES_READ)
? (msu_enable ? MSU_SNES_DATA_OUT
:cx4_enable ? CX4_SNES_DATA_OUT
:(cx4_active & cx4_vect_enable) ? CX4_SNES_DATA_OUT
: SNES_DINr)
: 8'bZ;
reg [3:0] ST_MEM_DELAYr;
reg MCU_RD_PENDr;
reg MCU_WR_PENDr;
reg CX4_RD_PENDr;
reg [23:0] ROM_ADDRr;
reg NEED_SNES_ADDRr;
always @(posedge CLK2) begin
if(SNES_cycle_end) NEED_SNES_ADDRr <= 1'b1;
else if(STATE & (ST_SNES_RD_END | ST_SNES_WR_END)) NEED_SNES_ADDRr <= 1'b0;
end
wire IS_CART = IS_ROM | IS_SAVERAM | IS_WRITABLE;
wire ASSERT_SNES_ADDR = SNES_CPU_CLK & NEED_SNES_ADDRr & IS_CART & ~cx4_active;
assign ROM_ADDR = (SD_DMA_TO_ROM) ? MCU_ADDR[23:1] : (ASSERT_SNES_ADDR) ? MAPPED_SNES_ADDR[23:1] : ROM_ADDRr[23:1];
assign ROM_ADDR0 = (SD_DMA_TO_ROM) ? MCU_ADDR[0] : (ASSERT_SNES_ADDR) ? MAPPED_SNES_ADDR[0] : ROM_ADDRr[0];
reg ROM_WEr;
initial ROM_WEr = 1'b1;
reg RQ_MCU_RDYr;
initial RQ_MCU_RDYr = 1'b1;
assign MCU_RDY = RQ_MCU_RDYr;
always @(posedge CLK2) begin
if(MCU_RRQ) begin
MCU_RD_PENDr <= 1'b1;
RQ_MCU_RDYr <= 1'b0;
end else if(MCU_WRQ) begin
MCU_WR_PENDr <= 1'b1;
RQ_MCU_RDYr <= 1'b0;
end else if(STATE & (ST_MCU_RD_END | ST_MCU_WR_END)) begin
MCU_RD_PENDr <= 1'b0;
MCU_WR_PENDr <= 1'b0;
RQ_MCU_RDYr <= 1'b1;
end
end
reg RQ_CX4_RDYr;
initial RQ_CX4_RDYr = 1'b1;
assign CX4_RDY = RQ_CX4_RDYr;
always @(posedge CLK2) begin
if(CX4_RRQ) begin
CX4_RD_PENDr <= 1'b1;
RQ_CX4_RDYr <= 1'b0;
end else if(STATE == ST_CX4_RD_WAIT && ST_MEM_DELAYr == 4'h0) begin
CX4_RD_PENDr <= 1'b0;
RQ_CX4_RDYr <= 1'b1;
end
end
reg snes_wr_cycle;
always @(posedge CLK2) begin
if(SNES_cycle_start & IS_CART & ~cx4_active) begin
STATE <= ST_SNES_RD_ADDR;
end else if(SNES_WR_start & IS_CART & ~cx4_active) begin
STATE <= ST_SNES_WR_ADDR;
end else begin
case(STATE)
ST_IDLE: begin
ROM_ADDRr <= MAPPED_SNES_ADDR;
if(CX4_RD_PENDr) begin
STATE <= ST_CX4_RD_WAIT;
ROM_ADDRr <= CX4_ADDR;
ST_MEM_DELAYr <= ROM_RD_WAIT_CX4;
end else if(~cx4_active && ~ASSERT_SNES_ADDR) begin
if(MCU_RD_PENDr) STATE <= ST_MCU_RD_ADDR;
else if(MCU_WR_PENDr) STATE <= ST_MCU_WR_ADDR;
else STATE <= ST_IDLE;
end
else STATE <= ST_IDLE;
end
ST_SNES_RD_ADDR: begin
STATE <= ST_SNES_RD_WAIT;
ST_MEM_DELAYr <= ROM_RD_WAIT;
end
ST_SNES_RD_WAIT: begin
ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1;
if(ST_MEM_DELAYr == 4'h0) STATE <= ST_SNES_RD_END;
else STATE <= ST_SNES_RD_WAIT;
if(ROM_ADDR0) SNES_DINr <= ROM_DATA[7:0];
else SNES_DINr <= ROM_DATA[15:8];
end
ST_SNES_RD_END: begin
STATE <= ST_IDLE;
if(ROM_ADDR0) SNES_DINr <= ROM_DATA[7:0];
else SNES_DINr <= ROM_DATA[15:8];
end
ST_SNES_WR_ADDR: begin
ROM_WEr <= (!IS_WRITABLE);
snes_wr_cycle <= 1'b1;
STATE <= ST_SNES_WR_WAIT1;
ST_MEM_DELAYr <= ROM_WR_WAIT1;
end
ST_SNES_WR_WAIT1: begin
ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1;
if(ST_MEM_DELAYr == 4'h0) STATE <= ST_SNES_WR_DATA;
else STATE <= ST_SNES_WR_WAIT1;
end
ST_SNES_WR_DATA: begin
ROM_DOUTr <= SNES_DATA;
ST_MEM_DELAYr <= ROM_WR_WAIT2;
STATE <= ST_SNES_WR_WAIT2;
end
ST_SNES_WR_WAIT2: begin
ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1;
if(ST_MEM_DELAYr == 4'h0) STATE <= ST_SNES_WR_END;
else STATE <= ST_SNES_WR_WAIT2;
end
ST_SNES_WR_END: begin
STATE <= ST_IDLE;
ROM_WEr <= 1'b1;
snes_wr_cycle <= 1'b0;
end
ST_MCU_RD_ADDR: begin
ROM_ADDRr <= MCU_ADDR;
STATE <= ST_MCU_RD_WAIT;
ST_MEM_DELAYr <= ROM_RD_WAIT_MCU;
end
ST_MCU_RD_WAIT: begin
ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1;
if(ST_MEM_DELAYr == 4'h0) begin
STATE <= ST_MCU_RD_WAIT2;
ST_MEM_DELAYr <= 4'h2;
if(ROM_ADDR0) MCU_DINr <= ROM_DATA[7:0];
else MCU_DINr <= ROM_DATA[15:8];
end
else STATE <= ST_MCU_RD_WAIT;
end
ST_MCU_RD_WAIT2: begin
ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1;
if(ST_MEM_DELAYr == 4'h0) begin
STATE <= ST_MCU_RD_END;
end else STATE <= ST_MCU_RD_WAIT2;
end
ST_MCU_RD_END: begin
STATE <= ST_IDLE;
end
ST_MCU_WR_ADDR: begin
ROM_ADDRr <= MCU_ADDR;
STATE <= ST_MCU_WR_WAIT;
ST_MEM_DELAYr <= ROM_WR_WAIT_MCU;
ROM_DOUTr <= MCU_DOUT;
ROM_WEr <= 1'b0;
end
ST_MCU_WR_WAIT: begin
ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1;
if(ST_MEM_DELAYr == 4'h0) begin
ROM_WEr <= 1'b1;
STATE <= ST_MCU_WR_WAIT2;
ST_MEM_DELAYr <= 4'h2;
end
else STATE <= ST_MCU_WR_WAIT;
end
ST_MCU_WR_WAIT2: begin
ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1;
if(ST_MEM_DELAYr == 4'h0) begin
STATE <= ST_MCU_WR_END;
end else STATE <= ST_MCU_WR_WAIT2;
end
ST_MCU_WR_END: begin
STATE <= ST_IDLE;
end
ST_CX4_RD_ADDR: begin
ROM_ADDRr <= CX4_ADDR;
STATE <= ST_CX4_RD_WAIT;
ST_MEM_DELAYr <= ROM_RD_WAIT_CX4;
end
ST_CX4_RD_WAIT: begin
ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1;
if(ST_MEM_DELAYr == 4'h0) STATE <= ST_IDLE;
else STATE <= ST_CX4_RD_WAIT;
if(ROM_ADDR0) CX4_DINr <= ROM_DATA[7:0];
else CX4_DINr <= ROM_DATA[15:8];
end
ST_CX4_RD_END: begin
STATE <= ST_IDLE;
end
endcase
end
end
assign ROM_DATA[7:0] = ROM_ADDR0
?(SD_DMA_TO_ROM ? (!MCU_WRITE ? MCU_DOUT : 8'bZ)
: (!ROM_WE ? ROM_DOUTr : 8'bZ)
)
:8'bZ;
assign ROM_DATA[15:8] = ROM_ADDR0 ? 8'bZ
:(SD_DMA_TO_ROM ? (!MCU_WRITE ? MCU_DOUT : 8'bZ)
: (!ROM_WE ? ROM_DOUTr : 8'bZ)
);
assign ROM_WE = SD_DMA_TO_ROM
?MCU_WRITE
:ROM_WEr | (ASSERT_SNES_ADDR & ~snes_wr_cycle);
// OE always active. Overridden by WE when needed.
assign ROM_OE = 1'b0;
assign ROM_CE = 1'b0;
assign ROM_BHE = !ROM_WE ? ROM_ADDR0 : 1'b0;
assign ROM_BLE = !ROM_WE ? !ROM_ADDR0 : 1'b0;
assign SNES_DATABUS_OE = msu_enable ? 1'b0 :
cx4_enable ? 1'b0 :
(cx4_active & cx4_vect_enable) ? 1'b0 :
((!IS_ROM & !IS_SAVERAM & !IS_WRITABLE)
|(SNES_READ & SNES_WRITE)
);
assign SNES_DATABUS_DIR = !SNES_READ ? 1'b1 : 1'b0;
assign IRQ_DIR = 1'b0;
assign SNES_IRQ = 1'bZ;
assign p113_out = 1'b0;
endmodule

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verilog/sd2snes_cx4/msu.v Normal file
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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14:55:04 12/14/2010
// Design Name:
// Module Name: msu
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module msu(
input clkin,
input enable,
input [13:0] pgm_address,
input [7:0] pgm_data,
input pgm_we,
input [2:0] reg_addr,
input [7:0] reg_data_in,
output [7:0] reg_data_out,
input reg_oe,
input reg_we,
output [6:0] status_out,
output [7:0] volume_out,
output volume_latch_out,
output [31:0] addr_out,
output [15:0] track_out,
input [5:0] status_reset_bits,
input [5:0] status_set_bits,
input status_reset_we,
input [13:0] msu_address_ext,
input msu_address_ext_write
);
reg [2:0] reg_addr_r [3:0];
always @(posedge clkin) begin
reg_addr_r[3] <= reg_addr_r[2];
reg_addr_r[2] <= reg_addr_r[1];
reg_addr_r[1] <= reg_addr_r[0];
reg_addr_r[0] <= reg_addr;
end
reg [1:0] status_reset_we_r;
always @(posedge clkin) status_reset_we_r = {status_reset_we_r[0], status_reset_we};
wire status_reset_en = (status_reset_we_r == 2'b01);
reg [13:0] msu_address_r;
wire [13:0] msu_address = msu_address_r;
wire [7:0] msu_data;
reg [1:0] msu_address_ext_write_sreg;
always @(posedge clkin)
msu_address_ext_write_sreg <= {msu_address_ext_write_sreg[0], msu_address_ext_write};
wire msu_address_ext_write_rising = (msu_address_ext_write_sreg[1:0] == 2'b01);
reg [4:0] reg_enable_sreg;
initial reg_enable_sreg = 5'b11111;
always @(posedge clkin) reg_enable_sreg <= {reg_enable_sreg[3:0], enable};
reg [5:0] reg_oe_sreg;
always @(posedge clkin) reg_oe_sreg <= {reg_oe_sreg[4:0], reg_oe};
wire reg_oe_rising = reg_enable_sreg[4] && (reg_oe_sreg[5:0] == 6'b000001);
reg [5:0] reg_we_sreg;
always @(posedge clkin) reg_we_sreg <= {reg_we_sreg[4:0], reg_we};
wire reg_we_rising = reg_enable_sreg[4] && (reg_we_sreg[5:0] == 6'b000001);
reg [31:0] addr_out_r;
assign addr_out = addr_out_r;
reg [15:0] track_out_r;
assign track_out = track_out_r;
reg [7:0] volume_r;
assign volume_out = volume_r;
reg volume_start_r;
assign volume_latch_out = volume_start_r;
reg audio_start_r;
reg audio_busy_r;
reg data_start_r;
reg data_busy_r;
reg ctrl_start_r;
reg [1:0] audio_ctrl_r;
reg [1:0] audio_status_r;
initial begin
audio_busy_r <= 1'b1;
data_busy_r <= 1'b1;
end
assign status_out = {msu_address_r[13], // 6
audio_start_r, // 5
data_start_r, // 4
volume_start_r, // 3
audio_ctrl_r, // 2:1
ctrl_start_r}; // 0
initial msu_address_r = 14'h1234;
msu_databuf snes_msu_databuf (
.clka(clkin),
.wea(~pgm_we), // Bus [0 : 0]
.addra(pgm_address), // Bus [13 : 0]
.dina(pgm_data), // Bus [7 : 0]
.clkb(clkin),
.addrb(msu_address), // Bus [13 : 0]
.doutb(msu_data)
); // Bus [7 : 0]
reg [7:0] data_out_r;
assign reg_data_out = data_out_r;
always @(posedge clkin) begin
case(reg_addr_r[3])
3'h0: data_out_r <= {data_busy_r, audio_busy_r, audio_status_r, 4'b0001};
3'h1: data_out_r <= msu_data;
3'h2: data_out_r <= 8'h53;
3'h3: data_out_r <= 8'h2d;
3'h4: data_out_r <= 8'h4d;
3'h5: data_out_r <= 8'h53;
3'h6: data_out_r <= 8'h55;
3'h7: data_out_r <= 8'h31;
endcase
end
always @(posedge clkin) begin
if(reg_we_rising) begin
case(reg_addr_r[3])
3'h0: addr_out_r[7:0] <= reg_data_in;
3'h1: addr_out_r[15:8] <= reg_data_in;
3'h2: addr_out_r[23:16] <= reg_data_in;
3'h3: begin
addr_out_r[31:24] <= reg_data_in;
data_start_r <= 1'b1;
data_busy_r <= 1'b1;
end
3'h4: begin
track_out_r[7:0] <= reg_data_in;
end
3'h5: begin
track_out_r[15:8] <= reg_data_in;
audio_start_r <= 1'b1;
audio_busy_r <= 1'b1;
end
3'h6: begin
volume_r <= reg_data_in;
volume_start_r <= 1'b1;
end
3'h7: begin
if(!audio_busy_r) begin
audio_ctrl_r <= reg_data_in[1:0];
ctrl_start_r <= 1'b1;
end
end
endcase
end else if (status_reset_en) begin
audio_busy_r <= (audio_busy_r | status_set_bits[5]) & ~status_reset_bits[5];
if(status_reset_bits[5]) audio_start_r <= 1'b0;
data_busy_r <= (data_busy_r | status_set_bits[4]) & ~status_reset_bits[4];
if(status_reset_bits[4]) data_start_r <= 1'b0;
// volume_start_r <= (volume_start_r | status_set_bits[3]) & ~status_reset_bits[3];
audio_status_r <= (audio_status_r | status_set_bits[2:1]) & ~status_reset_bits[2:1];
ctrl_start_r <= (ctrl_start_r | status_set_bits[0]) & ~status_reset_bits[0];
end else begin
volume_start_r <= 1'b0;
end
end
always @(posedge clkin) begin
if(msu_address_ext_write_rising)
msu_address_r <= msu_address_ext;
else if(reg_addr_r[3] == 3'h1 && reg_oe_rising) begin
msu_address_r <= msu_address_r + 1;
end
end
endmodule

456
verilog/sd2snes_cx4/sd2snes_cx4.xise Normal file
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@ -0,0 +1,456 @@
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
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<property xil_pn:name="Delay Values To Be Read from SDF ModelSim" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
<property xil_pn:name="Device" xil_pn:value="xc3s400" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Family" xil_pn:value="Spartan3" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
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<property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Fit" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
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<property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Place &amp; Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
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<property xil_pn:name="Other VCOM Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other VLOG Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other VSIM Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Package" xil_pn:value="pq208" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/>
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<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/main/snes_cx4" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Source window" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Specify Top Level Instance Names" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.cx4" xil_pn:valueState="default"/>
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132
verilog/sd2snes_cx4/sd_dma.v Normal file
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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 19:19:08 12/01/2010
// Design Name:
// Module Name: sd_dma
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module sd_dma(
input [3:0] SD_DAT,
inout SD_CLK,
input CLK,
input SD_DMA_EN,
output SD_DMA_STATUS,
output SD_DMA_SRAM_WE,
output SD_DMA_NEXTADDR,
output [7:0] SD_DMA_SRAM_DATA,
input SD_DMA_PARTIAL,
input [10:0] SD_DMA_PARTIAL_START,
input [10:0] SD_DMA_PARTIAL_END
);
reg [10:0] SD_DMA_STARTr;
reg [10:0] SD_DMA_ENDr;
reg SD_DMA_PARTIALr;
always @(posedge CLK) SD_DMA_PARTIALr <= SD_DMA_PARTIAL;
reg SD_DMA_DONEr;
reg[1:0] SD_DMA_DONEr2;
initial begin
SD_DMA_DONEr2 = 2'b00;
SD_DMA_DONEr = 1'b0;
end
always @(posedge CLK) SD_DMA_DONEr2 <= {SD_DMA_DONEr2[0], SD_DMA_DONEr};
wire SD_DMA_DONE_rising = (SD_DMA_DONEr2[1:0] == 2'b01);
reg [1:0] SD_DMA_ENr;
initial SD_DMA_ENr = 2'b00;
always @(posedge CLK) SD_DMA_ENr <= {SD_DMA_ENr[0], SD_DMA_EN};
wire SD_DMA_EN_rising = (SD_DMA_ENr [1:0] == 2'b01);
reg SD_DMA_STATUSr;
assign SD_DMA_STATUS = SD_DMA_STATUSr;
// we need 1042 cycles (startbit + 1024 nibbles + 16 crc + stopbit)
reg [10:0] cyclecnt;
initial cyclecnt = 11'd0;
reg SD_DMA_SRAM_WEr;
initial SD_DMA_SRAM_WEr = 1'b1;
assign SD_DMA_SRAM_WE = (cyclecnt < 1025 && SD_DMA_STATUSr) ? SD_DMA_SRAM_WEr : 1'b1;
reg SD_DMA_NEXTADDRr;
assign SD_DMA_NEXTADDR = (cyclecnt < 1025 && SD_DMA_STATUSr) ? SD_DMA_NEXTADDRr : 1'b0;
reg[7:0] SD_DMA_SRAM_DATAr;
assign SD_DMA_SRAM_DATA = SD_DMA_SRAM_DATAr;
// we have 4 internal cycles per SD clock, 8 per RAM byte write
reg [2:0] clkcnt;
initial clkcnt = 3'b000;
reg SD_CLKr;
always @(posedge CLK) SD_CLKr <= clkcnt[1];
assign SD_CLK = SD_DMA_STATUSr ? SD_CLKr : 1'bZ;
always @(posedge CLK) begin
if(SD_DMA_EN_rising) begin
SD_DMA_STATUSr <= 1'b1;
SD_DMA_STARTr <= (SD_DMA_PARTIALr ? SD_DMA_PARTIAL_START : 11'h0);
SD_DMA_ENDr <= (SD_DMA_PARTIALr ? SD_DMA_PARTIAL_END : 11'd1024);
end
else if (SD_DMA_DONE_rising) SD_DMA_STATUSr <= 1'b0;
end
always @(posedge CLK) begin
if(cyclecnt == 1042) SD_DMA_DONEr <= 1;
else SD_DMA_DONEr <= 0;
end
always @(posedge CLK) begin
if(SD_DMA_EN_rising || !SD_DMA_STATUSr) begin
clkcnt <= 0;
end else begin
if(SD_DMA_STATUSr) begin
clkcnt <= clkcnt + 1;
end
end
end
always @(posedge CLK) begin
if(SD_DMA_EN_rising || !SD_DMA_STATUSr) cyclecnt <= 0;
else if(clkcnt[1:0] == 2'b11) cyclecnt <= cyclecnt + 1;
end
// we have 8 clk cycles to complete one RAM write
// (4 clk cycles per SD_CLK; 2 SD_CLK cycles per byte)
always @(posedge CLK) begin
if(SD_DMA_STATUSr) begin
case(clkcnt[2:0])
3'h0: begin
SD_DMA_SRAM_WEr <= 1'b1;
SD_DMA_SRAM_DATAr[7:4] <= SD_DAT;
if(cyclecnt>SD_DMA_STARTr && cyclecnt <= SD_DMA_ENDr) SD_DMA_NEXTADDRr <= 1'b1;
end
3'h1:
SD_DMA_NEXTADDRr <= 1'b0;
// 3'h2:
3'h3:
if(cyclecnt>=SD_DMA_STARTr && cyclecnt < SD_DMA_ENDr) SD_DMA_SRAM_WEr <= 1'b0;
3'h4:
SD_DMA_SRAM_DATAr[3:0] <= SD_DAT;
// 3'h5:
// 3'h6:
// 3'h7:
endcase
end
end
endmodule

113
verilog/sd2snes_cx4/spi.v Normal file
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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 21:16:09 07/10/2009
// Design Name:
// Module Name: spi
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module spi(
input clk,
input SCK,
input MOSI,
inout MISO,
input SSEL,
output cmd_ready,
output param_ready,
output [7:0] cmd_data,
output [7:0] param_data,
output endmessage,
output startmessage,
input [7:0] input_data,
output [31:0] byte_cnt,
output [2:0] bit_cnt
);
reg [7:0] cmd_data_r;
reg [7:0] param_data_r;
reg [1:0] SSELr; always @(posedge clk) SSELr <= {SSELr[0], SSEL};
wire SSEL_active = ~SSELr[1]; // SSEL is active low
wire SSEL_startmessage = (SSELr[1:0]==2'b10); // message starts at falling edge
wire SSEL_endmessage = (SSELr[1:0]==2'b01); // message stops at rising edge
assign endmessage = SSEL_endmessage;
assign startmessage = SSEL_startmessage;
// bit count for one SPI byte + byte count for the message
reg [2:0] bitcnt;
reg [31:0] byte_cnt_r;
reg byte_received; // high when a byte has been received
reg [7:0] byte_data_received;
assign bit_cnt = bitcnt;
always @(posedge SCK) begin
if(SSEL) bitcnt <= 3'b000;
else begin
bitcnt <= bitcnt + 3'b001;
byte_data_received <= {byte_data_received[6:0], MOSI};
end
if(~SSEL && bitcnt==3'b111) byte_received <= 1'b1;
else byte_received <= 1'b0;
end
reg [1:0] byte_received_r;
always @(posedge clk) byte_received_r <= {byte_received_r[0], byte_received};
wire byte_received_sync = (byte_received_r == 2'b01);
always @(posedge clk) begin
if(~SSEL_active)
byte_cnt_r <= 16'h0000;
else if(byte_received_sync) begin
byte_cnt_r <= byte_cnt_r + 16'h0001;
end
end
reg [7:0] byte_data_sent;
assign MISO = ~SSEL ? input_data[7-bitcnt] : 1'bZ; // send MSB first
reg cmd_ready_r;
reg param_ready_r;
reg cmd_ready_r2;
reg param_ready_r2;
assign cmd_ready = cmd_ready_r;
assign param_ready = param_ready_r;
assign cmd_data = cmd_data_r;
assign param_data = param_data_r;
assign byte_cnt = byte_cnt_r;
always @(posedge clk) cmd_ready_r2 = byte_received_sync && byte_cnt_r == 32'h0;
always @(posedge clk) param_ready_r2 = byte_received_sync && byte_cnt_r > 32'h0;
// fill registers
always @(posedge clk) begin
if (SSEL_startmessage)
cmd_data_r <= 8'h00;
else if(cmd_ready_r2)
cmd_data_r <= byte_data_received;
else if(param_ready_r2)
param_data_r <= byte_data_received;
end
// delay ready signals by one clock
always @(posedge clk) begin
cmd_ready_r <= cmd_ready_r2;
param_ready_r <= param_ready_r2;
end
endmodule