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FPGA: Use internal clock instead of SNES master clock for $213F RMW timing

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This commit is contained in:
Maximilian Rehkopf 2012-07-09 02:18:28 +02:00
parent 968c347986
commit 9fbe61bad1
2 changed files with 8 additions and 8 deletions
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8
verilog/sd2snes/main.v
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@ -675,10 +675,10 @@ always @(posedge CLK2) begin
endcase
end
always @(posedge SYSCLK2) begin
if(SNES_PARD_start & r213f_enable) begin
r213f_forceread <= 1'b1;
r213f_delay <= 3'b001;
always @(posedge CLK2) begin
if(SNES_cycle_end) r213f_forceread <= 1'b1;
else if(SNES_PARD_start & r213f_enable) begin
r213f_delay <= 3'b000;
r213f_state <= 2'b10;
end else if(r213f_state == 2'b10) begin
r213f_delay <= r213f_delay - 1;

8
verilog/sd2snes_cx4/main.v
View File

@ -617,10 +617,10 @@ always @(posedge CLK2) begin
endcase
end
always @(posedge SYSCLK2) begin
if(SNES_PARD_start & r213f_enable) begin
r213f_forceread <= 1'b1;
r213f_delay <= 3'b001;
always @(posedge CLK2) begin
if(SNES_cycle_end) r213f_forceread <= 1'b1;
else if(SNES_PARD_start & r213f_enable) begin
r213f_delay <= 3'b000;
r213f_state <= 2'b10;
end else if(r213f_state == 2'b10) begin
r213f_delay <= r213f_delay - 1;