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FPGA: update clock speed to 88MHz

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This commit is contained in:
Maximilian Rehkopf 2012-07-09 01:54:05 +02:00
parent 8148f5567c
commit a083d80ff9
4 changed files with 5 additions and 6 deletions
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2
verilog/sd2snes/clk_test.v
View File

@ -39,7 +39,7 @@ always @(posedge clk) sysclk_sreg <= {sysclk_sreg[0], sysclk};
wire sysclk_rising = (sysclk_sreg == 2'b01);
always @(posedge clk) begin
if(sysclk_counter < 96000000) begin
if(sysclk_counter < 88000000) begin
sysclk_counter <= sysclk_counter + 1;
if(sysclk_rising) sysclk_value <= sysclk_value + 1;
end else begin

5
verilog/sd2snes/main.ucf
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@ -1,6 +1,5 @@
NET "CLKIN" TNM_NET = "CLKIN";
TIMESPEC TS_CLKIN = PERIOD "CLKIN" 24.05 MHz HIGH 50 %;
//TIMESPEC TS_CLKIN = PERIOD "CLKIN" 21.5 MHz HIGH 50 %;
TIMESPEC TS_CLKIN = PERIOD "CLKIN" 22.05 MHz HIGH 50 %;
NET "p113_out" IOSTANDARD = LVCMOS33;
NET "p113_out" LOC = P113;
@ -8,7 +7,7 @@ NET "p113_out" LOC = P113;
NET "SPI_SCK" LOC = P71;
NET "SPI_SCK" CLOCK_DEDICATED_ROUTE = FALSE;
NET "SPI_SCK" TNM_NET = "SPI_SCK";
TIMESPEC TS_SPI_SCK = PERIOD "SPI_SCK" 48.1MHz HIGH 50 %;
TIMESPEC TS_SPI_SCK = PERIOD "SPI_SCK" 88.2MHz HIGH 50 %;
NET "SPI_SCK" IOSTANDARD = LVCMOS33;
NET "SPI_SCK" DRIVE = 8;

2
verilog/sd2snes/rtc.v
View File

@ -42,7 +42,7 @@ reg [31:0] tick_cnt;
always @(posedge clkin) begin
tick_cnt <= tick_cnt + 1;
if((tick_cnt == 24000000) || pgm_we_rising) tick_cnt <= 0;
if((tick_cnt == 22000000) || pgm_we_rising) tick_cnt <= 0;
end
assign rtc_data = rtc_data_out_r;

2
verilog/sd2sneslite/main.ucf
View File

@ -1,5 +1,5 @@
NET "CLKIN" TNM_NET = "CLKIN";
TIMESPEC TS_CLKIN = PERIOD "CLKIN" 24.05 MHz HIGH 50 %;
TIMESPEC TS_CLKIN = PERIOD "CLKIN" 22.1 MHz HIGH 50 %;
//TIMESPEC TS_CLKIN = PERIOD "CLKIN" 21.5 MHz HIGH 50 %;
NET "p113_out" IOSTANDARD = LVCMOS33;