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new SRAM access (SPI)

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This commit is contained in:
ikari
2009-09-04 10:07:57 +02:00
parent 784b47d7ed
commit ceb5bec774
13 changed files with 184 additions and 150 deletions
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4
src/config.h
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@@ -62,8 +62,8 @@
# error Unknown chip!
# endif
# define SD_CHANGE_VECT INT0_vect
# define SDCARD_WP (PIND & _BV(PD6))
# define SDCARD_WP_SETUP() do { DDRD &= ~ _BV(PD6); PORTD |= _BV(PD6); } while(0)
# define SDCARD_WP (PINB & _BV(PB3))
# define SDCARD_WP_SETUP() do { DDRB &= ~ _BV(PB3); PORTB |= _BV(PB3); } while(0)
# define SD_CHANGE_ICR MCUCR
# define SD_SUPPLY_VOLTAGE (1L<<21)
# define DEVICE_SELECT (8+!(PINA & _BV(PA2))+2*!(PINA & _BV(PA3)))

10
src/fpga.c
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@@ -200,6 +200,12 @@ void set_avr_mapper(uint8_t val) {
}
void set_avr_bank(uint8_t val) {
PORTB &= 0xFC;
PORTB |= val&0x03;
SPI_SS_HIGH();
FPGA_SS_LOW();
spiTransferByte(0x00); // SET ADDRESS
spiTransferByte(val * 0x20); // select chip
spiTransferByte(0x00); // select chip
spiTransferByte(0x00); // select chip
FPGA_SS_HIGH();
SPI_SS_LOW();
}

9
src/led.c
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@@ -46,3 +46,12 @@ void toggle_busy_led(void) {
PORTB &= ~_BV(PB1);
DDRB ^= _BV(PB1);
}
void set_busy_led(uint8_t state) {
PORTB &= ~_BV(PB1);
if(state) {
DDRB |= _BV(PB1);
} else {
DDRB &= ~_BV(PB1);
}
}

11
src/led.h
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@@ -40,16 +40,7 @@ extern volatile uint8_t led_state;
/* Update the LEDs to match the buffer state */
void update_leds(void);
void toggle_busy_led(void);
void set_busy_led(uint8_t);
/* Wrapped in do..while to avoid "ambigious else" warnings */
#ifdef SINGLE_LED
# define set_dirty_led(x) do{if (x) { led_state |= LED_DIRTY; } else { led_state &= (uint8_t)~LED_DIRTY; }}while(0)
# define set_busy_led(x) do{if (x) { led_state |= LED_BUSY ; } else { led_state &= (uint8_t)~LED_BUSY ; }}while(0)
# define set_error_led(x) do{if (x) { led_state |= LED_ERROR; } else { led_state &= (uint8_t)~LED_ERROR; }}while(0)
#else
# define set_dirty_led(x) do{if (x) { DIRTY_LED_ON(); } else { DIRTY_LED_OFF(); }}while(0)
# define set_busy_led(x) do{if (x) { BUSY_LED_ON(); } else { BUSY_LED_OFF(); }}while(0)
# define set_error_led(x) do{if (x) { led_state |= LED_ERROR; } else { led_state &= (uint8_t)~LED_ERROR; update_leds(); }}while(0)
#endif
#endif

42
src/main.c
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@@ -45,6 +45,8 @@
#include "fileops.h"
#include "memory.h"
#include "fpga_spi.h"
#include "spi.h"
#include "avrcompat.h"
char stringbuf[100];
@@ -168,33 +170,49 @@ int main(void) {
load_rom("/test.smc");
uart_putc(')');
/*XXX uart_putc('[');
uart_putc('[');
load_sram("/test.srm");
uart_putc(']');*/
set_avr_mapper(1);
uart_putc(']');
set_busy_led(0);
set_avr_mapper(0);
set_avr_ena(1);
_delay_ms(100);
uart_puts_P(PSTR("SNES GO!"));
snes_reset(0);
_delay_ms(6553.6);
while(1) {
// snes_main_loop();
snes_main_loop();
}
while(1) {
uint8_t data=PINC;
/* HERE BE LIONS */
while(1) {
SPI_SS_HIGH();
FPGA_SS_LOW();
spiTransferByte(0x00);
spiTransferByte(0x00);
spiTransferByte(0x7f);
spiTransferByte(0xc0);
FPGA_SS_HIGH();
FPGA_SS_LOW();
spiTransferByte(0x81); // read w/ increment... hopefully
spiTransferByte(0x00); // 1 dummy read
uart_putcrlf();
for(uint8_t cnt=0; cnt<16; cnt++) {
uint8_t data=spiTransferByte(0x00);
_delay_ms(2);
if(data>=0x20 && data <= 0x7a) {
uart_putc(data);
} else {
uart_putc('.');
// uart_putc('.');
uart_putc("0123456789ABCDEF"[data>>4]);
uart_putc("0123456789ABCDEF"[data&15]);
uart_putc(' ');
}
SET_AVR_NEXTADDR();
CLR_AVR_NEXTADDR();
// set_avr_bank(3);
}
FPGA_SS_HIGH();
}
while(1);
}

66
src/memory.c
View File

@@ -39,10 +39,10 @@ uint32_t load_rom(char* filename) {
SPI_SS_HIGH();
if (file_res || !bytes_read) break;
FPGA_SS_LOW();
_delay_us(1);
spiTransferByte(0x91); // write w/ increment
if(!(count++ % 16)) {
toggle_busy_led();
uart_putc('.');
}
for(int j=0; j<bytes_read; j++) {
spiTransferByte(file_buf[j]);
@@ -51,7 +51,6 @@ uint32_t load_rom(char* filename) {
// _delay_ms(2);
}
spiTransferByte(0x00); // dummy tx for increment+write pulse
_delay_us(10);
FPGA_SS_HIGH();
}
file_close();
@@ -60,47 +59,49 @@ uint32_t load_rom(char* filename) {
uint32_t load_sram(char* filename) {
set_avr_bank(3);
AVR_ADDR_RESET();
SET_AVR_READ();
UINT bytes_read;
DWORD filesize;
file_open(filename, FA_READ);
filesize = file_handle.fsize;
if(file_res) return 0;
for(;;) {
FPGA_SS_HIGH();
SPI_SS_LOW();
bytes_read = file_read();
SPI_SS_HIGH();
if (file_res || !bytes_read) break;
FPGA_SS_LOW();
spiTransferByte(0x91);
for(int j=0; j<bytes_read; j++) {
SET_AVR_DATA(file_buf[j]);
AVR_WRITE();
AVR_NEXTADDR();
spiTransferByte(file_buf[j]);
}
spiTransferByte(0x00); // dummy tx
FPGA_SS_HIGH();
}
file_close();
return (uint32_t)filesize;
}
void save_sram(char* filename, uint32_t sram_size) {
void save_sram(char* filename, uint32_t sram_size, uint32_t base_addr) {
uint32_t count = 0;
uint32_t num = 0;
set_avr_bank(3);
_delay_us(100);
AVR_ADDR_RESET();
CLR_AVR_READ();
SET_AVR_WRITE();
spi_sd();
file_open(filename, FA_CREATE_ALWAYS | FA_WRITE);
if(file_res) {
uart_putc(0x30+file_res);
}
while(count<sram_size) {
set_avr_addr(base_addr+count);
spi_fpga();
spiTransferByte(0x81); // read
spiTransferByte(0); // dummy
for(int j=0; j<sizeof(file_buf); j++) {
_delay_us(5);
file_buf[j] = AVR_DATA;
CLR_AVR_ADDR_EN();
SET_AVR_NEXTADDR();
_delay_us(5);
CLR_AVR_NEXTADDR();
SET_AVR_ADDR_EN();
file_buf[j] = spiTransferByte(0x00);
count++;
}
spi_sd();
num = file_write();
}
file_close();
@@ -109,25 +110,24 @@ void save_sram(char* filename, uint32_t sram_size) {
uint32_t calc_sram_crc(uint32_t size) {
uint8_t data;
set_avr_bank(3);
_delay_us(100);
AVR_ADDR_RESET();
SET_AVR_WRITE();
CLR_AVR_READ();
uint32_t count;
uint16_t crc;
crc=0;
set_avr_bank(3);
SPI_SS_HIGH();
FPGA_SS_HIGH();
FPGA_SS_LOW();
spiTransferByte(0x81);
spiTransferByte(0x00);
for(count=0; count<size; count++) {
_delay_us(5);
data = AVR_DATA;
data = spiTransferByte(0);
/* uart_putc(hex[(data>>4)]);
uart_putc(hex[data&0xf]);
uart_putc(' ');
_delay_ms(2);*/
crc += crc16_update(crc, &data, 1);
CLR_AVR_ADDR_EN();
SET_AVR_NEXTADDR();
_delay_us(5);
CLR_AVR_NEXTADDR();
SET_AVR_ADDR_EN();
}
FPGA_SS_HIGH();
/* uart_putc(hex[(crc>>28)&0xf]);
uart_putc(hex[(crc>>24)&0xf]);
uart_putc(hex[(crc>>20)&0xf]);

2
src/memory.h
View File

@@ -5,6 +5,6 @@
#define MEMORY_H
uint32_t load_rom(char* filename);
uint32_t load_sram(char* filename);
void save_sram(char* filename, uint32_t sram_size);
void save_sram(char* filename, uint32_t sram_size, uint32_t base_addr);
uint32_t calc_sram_crc(uint32_t size);
#endif

8
src/snes.c
View File

@@ -10,12 +10,13 @@
#include "memory.h"
#include "fileops.h"
#include "ff.h"
#include "led.h"
uint8_t initloop=1;
uint32_t sram_crc, sram_crc_old;
uint32_t sram_size = 8192; // sane default
uint32_t sram_base_addr = 0x600000; // chip 3
void snes_init() {
DDRD |= _BV(PD5); // PD5 = RESET_DIR
DDRD |= _BV(PD6); // PD6 = RESET
@@ -46,13 +47,16 @@ void snes_reset(int state) {
void snes_main_loop() {
if(initloop) {
sram_crc_old = calc_sram_crc(sram_size);
save_sram("/test.srm", sram_size, sram_base_addr);
initloop=0;
}
sram_crc = calc_sram_crc(sram_size);
if(sram_crc != sram_crc_old) {
uart_putc('U');
uart_putcrlf();
save_sram("/test.srm", sram_size);
set_busy_led(1);
save_sram("/test.srm", sram_size, sram_base_addr);
set_busy_led(0);
}
sram_crc_old = sram_crc;
uart_putc('.');