lots of wip, tests, incoming redesign
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ikari
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pcb/cart/sd2snes20.brd
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pcb/cart/sd2snes20.brd
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pcb/cart/sd2snes20.sch
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pcb/cart/sd2snes20.sch
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pcb/vfbga48breakout.brd
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pcb/vfbga48breakout.brd
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pcb/vfbga48breakout.sch
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pcb/vfbga48breakout.sch
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@ -33,7 +33,7 @@ BRK_8bit: BRK_16bit:
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COP_8bit: COP_16bit:
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IRQ_8bit:
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NMI_8bit:
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- lda $ABCDEF : bra -
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- wai: lda $ABCDEF : bra -
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*= $C0FFB0
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; Zero the area from $FFB0 - $FFFF
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@ -2,6 +2,9 @@
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#include "dma.i65"
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GAME_MAIN:
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sep #$20 : .as
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lda #$01
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sta $420d ; fast cpu
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sep #$20 : .as
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jsr snes_init
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jsr setup_gfx
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@ -17,6 +20,16 @@ GAME_MAIN:
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sta @AVR_PARAM+2
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jsr menu_init
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sep #$20 : .as
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sep #$20 : .as
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- lda @$C00000
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lda @$D00000
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lda @$E00000
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lda @$F00000
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lda @$400000
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lda @$500000
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lda @$600000
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lda @$700000
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; bra -
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jsr menuloop
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cli
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stz $4200
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@ -13,11 +13,13 @@ read_pad1_cont1
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eor pad1mem
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and pad1mem
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sta pad1trig
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lda #$0010
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lda #$0001
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; lda #$0010
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cmp pad1delay
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bne read_pad1_cont2
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stz pad1mem
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lda #$000d
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lda #$0000
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; lda #$000d
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sta pad1delay
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read_pad1_cont2
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;lda $4218
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15
src/main.c
15
src/main.c
@ -264,7 +264,7 @@ restart:
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uart_putc('(');
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load_rom((uint8_t*)"/sd2snes/menu.bin", SRAM_MENU_ADDR);
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set_rom_mask(0x3fffff); // force mirroring off
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set_avr_mapper(0x7); // menu mapper
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set_avr_mapper(0x7); // menu mapper XXX
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uart_putc(')');
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uart_putcrlf();
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// sram_hexdump(0x7ffff0, 0x10);
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@ -279,8 +279,17 @@ restart:
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_delay_ms(100);
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uart_puts_P(PSTR("SNES GO!\r\n"));
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snes_reset(0);
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// writetest();
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// XXX
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uart_putc(uart_getc());
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/* snes_reset(1);
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set_avr_ena(0);
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led_std();
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set_busy_led(1);
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save_sram((uint8_t*)"/sd2snes/dump", 65536, SRAM_MENU_ADDR);
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set_busy_led(0);
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set_avr_ena(1);
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snes_reset(0); */
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uint8_t cmd = 0;
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while(!sram_reliable());
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@ -192,3 +192,13 @@ NET "SPI_DMA_CTRL" PULLUP;
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NET "SPI_SCK" IOSTANDARD = LVCMOS33;
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NET "SPI_SCK" DRIVE = 16;
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NET "SPI_SCK" PULLUP;
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NET "DBG_P44" LOC = P44;
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NET "DBG_P44" IOSTANDARD = LVCMOS33;
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NET "DBG_P46" LOC = P46;
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NET "DBG_P46" IOSTANDARD = LVCMOS33;
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NET "DBG_P47" LOC = P47;
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NET "DBG_P47" IOSTANDARD = LVCMOS33;
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NET "DBG_P52" LOC = P52;
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NET "DBG_P52" IOSTANDARD = LVCMOS33;
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NET "DBG_P53" LOC = P53;
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NET "DBG_P53" IOSTANDARD = LVCMOS33;
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@ -56,7 +56,14 @@ module main(
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//output DCM_IN_STOPPED,
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//output DCM_FX_STOPPED
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//input DCM_RST
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,
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output DBG_P44,
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output DBG_P46,
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output DBG_P47,
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output DBG_P52,
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output DBG_P53
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);
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wire [7:0] spi_cmd_data;
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wire [7:0] spi_param_data;
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wire [7:0] spi_input_data;
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@ -197,7 +204,7 @@ wire SNES_WRITEs = (SNES_WRITEr == 2'b11);
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wire SNES_CSs = (SNES_CSr == 2'b11);
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wire SNES_CPU_CLKs = SNES_CPU_CLK; // (SNES_CPU_CLKr == 2'b11);
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wire SNES_RW_start = (SNES_RWr == 6'b111110); // falling edge marks beginning of cycle
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wire SNES_cycle_start = (SNES_CPU_CLKr == 6'b000001);
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wire SNES_cycle_start = (SNES_CPU_CLKr == 6'b000011); // slight delay, RD/WR comes after CLK
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wire SNES_ADDRCHG = (SNES_ADDRr != SNES_ADDR_PREVr);
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wire SNES_addr_start = (SNES_ADDRCHGr[0] == 1'b1);
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@ -326,21 +333,34 @@ initial begin
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SRAM_WE_ARRAY[2'b10] = 13'b1_111111_000000;
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SRAM_WE_ARRAY[2'b11] = 13'b1_111111_111111;
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SRAM_OE_ARRAY[2'b00] = 13'b1_111111_111111;
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SRAM_OE_ARRAY[2'b01] = 13'b1_111111_000000;
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SRAM_OE_ARRAY[2'b00] = 13'b0_111111_111111;
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SRAM_OE_ARRAY[2'b01] = 13'b0_111111_000000;
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SRAM_OE_ARRAY[2'b10] = 13'b0_000000_111111;
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SRAM_OE_ARRAY[2'b11] = 13'b0_000000_000000;
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SNES_DATA_TO_MEM_ARRAY[1'b0] = 13'b0_001000_000000; // SNES write
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/* 13'b0001000000000 */
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SNES_DATA_TO_MEM_ARRAY[1'b1] = 13'b0_000000_000000; // SNES read
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AVR_DATA_TO_MEM_ARRAY[1'b0] = 13'b1_111111_111111; // AVR write
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// AVR_DATA_TO_MEM_ARRAY[1'b0] = 13'b0000000001000; // AVR write
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// *************************************************************
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// enable sequences for data path related operations. These
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// control when to take a data value from SNES or AVR to the
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// SRAM bus and vice versa.
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// *************************************************************
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// SNES write. Data cannot be latched earlier because data from
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// the SNES is not valid before ~50ns after falling edge of /WR.
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// This timing is *just* enough to satisfy SRAM's t_SD (Data Setup to
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// write end) _and_ SNES's data valid delay.
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SNES_DATA_TO_MEM_ARRAY[1'b0] = 13'b0_000100_000000;
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// SNES read. No transfers to SRAM.
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SNES_DATA_TO_MEM_ARRAY[1'b1] = 13'b0_000000_000000;
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// AVR write. Data is buffered via the SPI module and has to be
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// used at any given point.
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AVR_DATA_TO_MEM_ARRAY[1'b0] = 13'b1_111111_111111; // AVR write
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// AVR read. No transfers to SRAM.
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AVR_DATA_TO_MEM_ARRAY[1'b1] = 13'b0_000000_000000; // AVR read
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// SNES write. No transfers from SRAM.
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SRAM_DATA_TO_SNES_MEM_ARRAY[1'b0] = 13'b0_000000_000000; // SNES write
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// SNES read. 000001 _should_ work but might get too close to the next edge of CE/BHE/ADDR???
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SRAM_DATA_TO_SNES_MEM_ARRAY[1'b1] = 13'b0_000100_000000; // SNES read
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/* 13'b0000100000000; */
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@ -363,7 +383,7 @@ end
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always @(posedge CLK2) begin
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AVR_READ_CYCLE <= AVR_READ;
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AVR_WRITE_CYCLE <= AVR_WRITE;
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if (SNES_RW_start) begin
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if (SNES_cycle_start) begin
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SNES_READ_CYCLE <= SNES_READ;
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SNES_WRITE_CYCLE <= SNES_WRITE;
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STATE <= STATE_0;
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@ -473,11 +493,14 @@ assign SRAM_WE = !AVR_ENA ? AVR_WRITE
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assign SRAM_OE = !AVR_ENA ? AVR_READ
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: SRAM_OE_ARRAY[{SNES_WRITE_CYCLE, AVR_WRITE_CYCLE}][STATEIDX];
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assign SRAM_BHE = !SRAM_WE ? SRAM_ADDR0 : 1'b0;
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assign SRAM_BLE = !SRAM_WE ? !SRAM_ADDR0 : 1'b0;
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// This crashes after a couple million instructions under rare
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// circumstances. I don't have the slightest.
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//assign SRAM_BHE = SRAM_ADDR0;
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//assign SRAM_BLE = ~SRAM_ADDR0;
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// This works
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assign SRAM_BHE = !SRAM_WE ? SRAM_ADDR0 : 1'b0;
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assign SRAM_BLE = !SRAM_WE ? ~SRAM_ADDR0 : 1'b0;
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// dumb version
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//assign SRAM_OE = !AVR_ENA ? AVR_READ : SNES_READs;
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@ -498,4 +521,15 @@ assign SNES_WRITE_CYCLEw = SNES_WRITE_CYCLE;
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assign IRQ_DIR = 1'b0;
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assign SNES_IRQ = 1'bZ;
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// DEBUG
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assign DBG_P44 = SRAM_DATA[0];
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assign DBG_P46 = SRAM_DATA[1];
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assign DBG_P47 = SRAM_DATA[2];
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assign DBG_P52 = SRAM_OE;
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assign DBG_P53 = SRAM_DATA_TO_SNES_MEM;
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//SNES_ADDR==24'hC0F000 || SNES_ADDR==24'h40F000 || SNES_ADDR==24'h80F000 || SNES_ADDR==24'h00F000;
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endmodule
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