4 Commits

Author SHA1 Message Date
Godzil
1d928e7091 Merge branch 'udev' into develop 2013-10-06 14:52:40 +01:00
Maximilian Rehkopf
7109f9e030 FPGA: add SD clock pullup to test configuration 2012-05-02 10:46:27 +02:00
Maximilian Rehkopf
f5caf21fac FPGA: slightly tighten timing constraints 2012-05-02 10:41:07 +02:00
ikari
dc01edfe9a FPGA: add test suite 2011-12-19 22:26:09 +01:00