Apply my changes for seeed build

PCB: update Rev.E assembly diagrams
FPGA: updated project files
2012-03-05 11:53:09 +01:00 · 2012-01-14 23:35:14 +01:00 · 2012-01-14 23:16:57 +01:00 · 2012-01-14 23:13:38 +01:00 · 2012-01-14 23:12:45 +01:00
34 changed files with 71081 additions and 18672 deletions
--- a/pcb/kicad/RevE/sd2snes-components-back.png
+++ b/pcb/kicad/RevE/sd2snes-components-back.png
--- a/pcb/kicad/RevE/sd2snes-components-front.png
+++ b/pcb/kicad/RevE/sd2snes-components-front.png
--- a/pcb/kicad/RevE/sd2snes.pro
+++ b/pcb/kicad/RevE/sd2snes.pro
@@ -1,6 +1,6 @@
-update=Sat 13 Aug 2011 10:34:31 PM CEST
+update=jeu. 23 févr. 2012 15:31:14 CET
 version=1
-last_client=pcbnew
+last_client=eeschema
 [general]
 version=1
 [cvpcb]
@@ -8,6 +8,39 @@ version=1
 NetIExt=net
 [cvpcb/libraries]
 EquName1=devcms
+[pcbnew]
+version=1
+PadDrlX=0
+PadDimH=79
+PadDimV=690
+BoardThickness=630
+SgPcb45=1
+TxtPcbV=800
+TxtPcbH=600
+TxtModV=600
+TxtModH=600
+TxtModW=120
+VEgarde=40
+DrawLar=70
+EdgeLar=40
+TxtLar=120
+MSegLar=39
+LastNetListRead=sd2snes.net
+[pcbnew/libraries]
+LibDir=../../kicad
+LibName1=sockets
+LibName2=connect
+LibName3=discret
+LibName4=pin_array
+LibName5=divers
+LibName6=libcms
+LibName7=display
+LibName8=valves
+LibName9=led
+LibName10=dip_sockets
+LibName11=libs/mypackages
+LibName12=libs/hai
+LibName13=libs/snescart
 [eeschema]
 version=1
 LibDir=../../kicad
@@ -38,7 +71,11 @@ offY_E=0
 RptD_X=0
 RptD_Y=100
 RptLab=1
+SimCmd=
+UseNetN=0
 LabSize=50
+PrintMonochrome=1
+ShowSheetReferenceAndTitleBlock=1
 [eeschema/libraries]
 LibName1=power
 LibName2=device
@@ -81,36 +118,3 @@ LibName38=libs/cs4344
 LibName39=libs/double_sch_kcom
 LibName40=libs/usb_minib
 LibName41=libs/mic23250
-[pcbnew]
-version=1
-PadDrlX=0
-PadDimH=79
-PadDimV=690
-BoardThickness=630
-SgPcb45=1
-TxtPcbV=800
-TxtPcbH=600
-TxtModV=600
-TxtModH=600
-TxtModW=120
-VEgarde=40
-DrawLar=70
-EdgeLar=40
-TxtLar=120
-MSegLar=39
-LastNetListRead=sd2snes.net
-[pcbnew/libraries]
-LibDir=../../kicad
-LibName1=sockets
-LibName2=connect
-LibName3=discret
-LibName4=pin_array
-LibName5=divers
-LibName6=libcms
-LibName7=display
-LibName8=valves
-LibName9=led
-LibName10=dip_sockets
-LibName11=libs/mypackages
-LibName12=libs/hai
-LibName13=libs/snescart
--- a/pcb/kicad/RevE2/D45146_10x10.zip
+++ b/pcb/kicad/RevE2/D45146_10x10.zip
--- a/pcb/kicad/RevE2/D45146_10x10/D45146_10x10_bottomlayer.gbl
+++ b/pcb/kicad/RevE2/D45146_10x10/D45146_10x10_bottomlayer.gbl
--- a/pcb/kicad/RevE2/D45146_10x10/D45146_10x10_bottommask.gbs
+++ b/pcb/kicad/RevE2/D45146_10x10/D45146_10x10_bottommask.gbs
@@ -0,0 +1,513 @@
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--- a/pcb/kicad/RevE2/D45146_10x10/D45146_10x10_bottomsilk.gbo
+++ b/pcb/kicad/RevE2/D45146_10x10/D45146_10x10_bottomsilk.gbo
--- a/pcb/kicad/RevE2/D45146_10x10/D45146_10x10_drill.txt
+++ b/pcb/kicad/RevE2/D45146_10x10/D45146_10x10_drill.txt
@@ -0,0 +1,557 @@
+M48
+;DRILL file {PCBnew (2010-04-21 BZR 23xx)-stable} date mer. 22 févr. 2012 15:25:41 CET
+;FORMAT={2:4/ absolute / inch / keep zeros}
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--- a/pcb/kicad/RevE2/D45146_10x10/D45146_10x10_toplayer.gtl
+++ b/pcb/kicad/RevE2/D45146_10x10/D45146_10x10_toplayer.gtl
--- a/pcb/kicad/RevE2/D45146_10x10/D45146_10x10_topmask.gts
+++ b/pcb/kicad/RevE2/D45146_10x10/D45146_10x10_topmask.gts
--- a/pcb/kicad/RevE2/D45146_10x10/D45146_10x10_topsilk.gto
+++ b/pcb/kicad/RevE2/D45146_10x10/D45146_10x10_topsilk.gto
--- a/pcb/kicad/RevE2/J101.emp
+++ b/pcb/kicad/RevE2/J101.emp
@@ -0,0 +1,557 @@
+PCBNEW-LibModule-V1  mar. 21 févr. 2012 14:32:20 CET
+$INDEX
+J101
+$EndINDEX
+$MODULE J101
+Po 0 0 0 15 4F439CD9 4F43990D ~~
+Li J101
+Sc 4F43990D
+AR /4B6E16F2/4B6E1766
+Op 0 0 0
+.SolderMask 4
+.SolderPaste -4
+T0 -4134 2953 600 600 0 120 N V 21 N"J101"
+T1 0 2953 600 600 0 120 N V 21 N"SNESCART_EXT"
+DS 18307 -8976 19606 -8976 40 28
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+DS -11811 -2480 -12795 -2480 40 28
+DS -12795 -2480 -12795 1693 40 28
+DS -11535 1969 11535 1969 40 28
+$PAD
+Sh "1" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 50 "/SNES_Slot/SNES_EXT_SYS_CLK"
+Po -16732 197
+$EndPAD
+$PAD
+Sh "2" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 0 ""
+Po -15748 197
+$EndPAD
+$PAD
+Sh "3" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 47 "/SNES_Slot/SNES_EXT_PA6"
+Po -14764 197
+$EndPAD
+$PAD
+Sh "4" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 3 "/SNES_Slot/SNES_EXT_/PARD"
+Po -13780 197
+$EndPAD
+$PAD
+Sh "5" R 787 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 57 "GND"
+Po -10925 197
+$EndPAD
+$PAD
+Sh "6" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 11 "/SNES_Slot/SNES_EXT_A11"
+Po -9843 197
+$EndPAD
+$PAD
+Sh "7" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 10 "/SNES_Slot/SNES_EXT_A10"
+Po -8858 197
+$EndPAD
+$PAD
+Sh "8" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 31 "/SNES_Slot/SNES_EXT_A9"
+Po -7874 197
+$EndPAD
+$PAD
+Sh "9" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 30 "/SNES_Slot/SNES_EXT_A8"
+Po -6890 197
+$EndPAD
+$PAD
+Sh "10" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 29 "/SNES_Slot/SNES_EXT_A7"
+Po -5906 197
+$EndPAD
+$PAD
+Sh "11" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 28 "/SNES_Slot/SNES_EXT_A6"
+Po -4921 197
+$EndPAD
+$PAD
+Sh "12" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 27 "/SNES_Slot/SNES_EXT_A5"
+Po -3937 197
+$EndPAD
+$PAD
+Sh "13" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 26 "/SNES_Slot/SNES_EXT_A4"
+Po -2953 197
+$EndPAD
+$PAD
+Sh "14" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 25 "/SNES_Slot/SNES_EXT_A3"
+Po -1969 197
+$EndPAD
+$PAD
+Sh "15" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 20 "/SNES_Slot/SNES_EXT_A2"
+Po -984 197
+$EndPAD
+$PAD
+Sh "16" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 9 "/SNES_Slot/SNES_EXT_A1"
+Po 0 197
+$EndPAD
+$PAD
+Sh "17" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 8 "/SNES_Slot/SNES_EXT_A0"
+Po 984 197
+$EndPAD
+$PAD
+Sh "18" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 2 "/SNES_Slot/SNES_EXT_/IRQ"
+Po 1969 197
+$EndPAD
+$PAD
+Sh "19" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 33 "/SNES_Slot/SNES_EXT_D0"
+Po 2953 197
+$EndPAD
+$PAD
+Sh "20" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 34 "/SNES_Slot/SNES_EXT_D1"
+Po 3937 197
+$EndPAD
+$PAD
+Sh "21" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 35 "/SNES_Slot/SNES_EXT_D2"
+Po 4921 197
+$EndPAD
+$PAD
+Sh "22" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 36 "/SNES_Slot/SNES_EXT_D3"
+Po 5906 197
+$EndPAD
+$PAD
+Sh "23" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 5 "/SNES_Slot/SNES_EXT_/RD"
+Po 6890 197
+$EndPAD
+$PAD
+Sh "24" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 56 "EXT_CIC_DATA1"
+Po 7874 197
+$EndPAD
+$PAD
+Sh "25" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 54 "CIC_RESET"
+Po 8858 197
+$EndPAD
+$PAD
+Sh "26" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 58 "SNES_/RESET"
+Po 9843 197
+$EndPAD
+$PAD
+Sh "27" R 787 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 1 "+5VL"
+Po 10925 197
+$EndPAD
+$PAD
+Sh "28" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 41 "/SNES_Slot/SNES_EXT_PA0"
+Po 13780 197
+$EndPAD
+$PAD
+Sh "29" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 43 "/SNES_Slot/SNES_EXT_PA2"
+Po 14764 197
+$EndPAD
+$PAD
+Sh "30" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 45 "/SNES_Slot/SNES_EXT_PA4"
+Po 15748 197
+$EndPAD
+$PAD
+Sh "31" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 51 "AUDIO_L"
+Po 16732 197
+$EndPAD
+$PAD
+Sh "32" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 0 ""
+Po -16732 197
+$EndPAD
+$PAD
+Sh "33" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 49 "/SNES_Slot/SNES_EXT_REFRESH"
+Po -15748 197
+$EndPAD
+$PAD
+Sh "34" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 48 "/SNES_Slot/SNES_EXT_PA7"
+Po -14764 197
+$EndPAD
+$PAD
+Sh "35" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 4 "/SNES_Slot/SNES_EXT_/PAWR"
+Po -13780 197
+$EndPAD
+$PAD
+Sh "36" R 787 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 57 "GND"
+Po -10925 197
+$EndPAD
+$PAD
+Sh "37" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 12 "/SNES_Slot/SNES_EXT_A12"
+Po -9843 197
+$EndPAD
+$PAD
+Sh "38" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 13 "/SNES_Slot/SNES_EXT_A13"
+Po -8858 197
+$EndPAD
+$PAD
+Sh "39" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 14 "/SNES_Slot/SNES_EXT_A14"
+Po -7874 197
+$EndPAD
+$PAD
+Sh "40" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 15 "/SNES_Slot/SNES_EXT_A15"
+Po -6890 197
+$EndPAD
+$PAD
+Sh "41" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 16 "/SNES_Slot/SNES_EXT_A16"
+Po -5906 197
+$EndPAD
+$PAD
+Sh "42" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 17 "/SNES_Slot/SNES_EXT_A17"
+Po -4921 197
+$EndPAD
+$PAD
+Sh "43" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 18 "/SNES_Slot/SNES_EXT_A18"
+Po -3937 197
+$EndPAD
+$PAD
+Sh "44" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 19 "/SNES_Slot/SNES_EXT_A19"
+Po -2953 197
+$EndPAD
+$PAD
+Sh "45" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 21 "/SNES_Slot/SNES_EXT_A20"
+Po -1969 197
+$EndPAD
+$PAD
+Sh "46" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 22 "/SNES_Slot/SNES_EXT_A21"
+Po -984 197
+$EndPAD
+$PAD
+Sh "47" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 23 "/SNES_Slot/SNES_EXT_A22"
+Po 0 197
+$EndPAD
+$PAD
+Sh "48" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 24 "/SNES_Slot/SNES_EXT_A23"
+Po 984 197
+$EndPAD
+$PAD
+Sh "49" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 6 "/SNES_Slot/SNES_EXT_/ROMSEL"
+Po 1969 197
+$EndPAD
+$PAD
+Sh "50" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 37 "/SNES_Slot/SNES_EXT_D4"
+Po 2953 197
+$EndPAD
+$PAD
+Sh "51" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 38 "/SNES_Slot/SNES_EXT_D5"
+Po 3937 197
+$EndPAD
+$PAD
+Sh "52" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 39 "/SNES_Slot/SNES_EXT_D6"
+Po 4921 197
+$EndPAD
+$PAD
+Sh "53" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 40 "/SNES_Slot/SNES_EXT_D7"
+Po 5906 197
+$EndPAD
+$PAD
+Sh "54" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 7 "/SNES_Slot/SNES_EXT_/WR"
+Po 6890 197
+$EndPAD
+$PAD
+Sh "55" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 55 "EXT_CIC_DATA0"
+Po 7874 197
+$EndPAD
+$PAD
+Sh "56" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 53 "CIC_CLK"
+Po 8858 197
+$EndPAD
+$PAD
+Sh "57" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 32 "/SNES_Slot/SNES_EXT_CPU_CLK"
+Po 9843 197
+$EndPAD
+$PAD
+Sh "58" R 787 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 1 "+5VL"
+Po 10925 197
+$EndPAD
+$PAD
+Sh "59" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 42 "/SNES_Slot/SNES_EXT_PA1"
+Po 13780 197
+$EndPAD
+$PAD
+Sh "60" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 44 "/SNES_Slot/SNES_EXT_PA3"
+Po 14764 197
+$EndPAD
+$PAD
+Sh "61" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 46 "/SNES_Slot/SNES_EXT_PA5"
+Po 15748 197
+$EndPAD
+$PAD
+Sh "62" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 52 "AUDIO_R"
+Po 16732 197
+$EndPAD
+$PAD
+Sh "" R 4921 3150 0 0 0
+Dr 0 0 0
+At CONN N 00C00000
+Ne 0 ""
+Po -15256 394
+$EndPAD
+$PAD
+Sh "" R 4921 3150 0 0 0
+Dr 0 0 0
+At CONN N 00C00000
+Ne 0 ""
+Po 15256 394
+$EndPAD
+$PAD
+Sh "" R 23622 3150 0 0 0
+Dr 0 0 0
+At CONN N 00C00000
+Ne 0 ""
+Po 0 394
+$EndPAD
+$PAD
+Sh "" R 2362 1969 0 0 0
+Dr 0 0 0
+At CONN N 00400000
+Ne 0 ""
+Po -10945 -3819
+$EndPAD
+$PAD
+Sh "" R 2283 2362 0 0 0
+Dr 0 0 0
+At CONN N 00400000
+Ne 0 ""
+Po 14331 -3780
+$EndPAD
+$EndMODULE  J101
+$EndLIBRARY
--- a/pcb/kicad/RevE2/J101.mdc
+++ b/pcb/kicad/RevE2/J101.mdc
@@ -0,0 +1,3 @@
+PCBNEW-LibDoc----V1  mer. 22 févr. 2012 15:02:30 CET
+#
+$EndLIBDOC
--- a/pcb/kicad/RevE2/J101.mod
+++ b/pcb/kicad/RevE2/J101.mod
@@ -0,0 +1,575 @@
+PCBNEW-LibModule-V1  mer. 22 févr. 2012 15:02:30 CET
+$INDEX
+J101
+986studio
+$EndINDEX
+$MODULE J101
+Po 0 0 0 15 4F439CD9 4F43990D ~~
+Li J101
+Sc 4F43990D
+AR /4B6E16F2/4B6E1766
+Op 0 0 0
+.SolderMask 4
+.SolderPaste -4
+T0 -4134 2953 600 600 0 120 N V 21 N"J101"
+T1 0 2953 600 600 0 120 N V 21 N"SNESCART_EXT"
+DS 18307 -8976 19606 -8976 40 28
+DS 19606 -8976 19606 -24409 40 28
+DS 19606 -24409 19439 -24409 40 28
+DS 19439 -24409 19291 -24409 40 28
+DS 17717 -2205 19587 -2205 40 28
+DS 19606 -2205 19606 -4094 40 28
+DS 19606 -4094 19498 -4094 40 28
+DS 19498 -4094 19291 -4094 40 28
+DS -19724 -12303 -19724 -12244 40 28
+DS -19724 -12244 -18465 -12244 40 28
+DS -18465 -12244 -18465 -12185 40 28
+DS -19724 -12244 -19724 -24409 40 28
+DS -19724 -24409 -19488 -24409 40 28
+DS -19488 -24409 -19488 -24488 40 28
+DS -19646 -8898 -19724 -8898 40 28
+DS -19724 -8898 -19724 -8819 40 28
+DS -19724 -8898 -19449 -8898 40 28
+DS -18465 -4803 -19724 -4803 40 28
+DS -19724 -4803 -19724 -8888 40 28
+DS -19720 -4805 -19725 -4805 40 28
+DS -19488 -27087 -19488 -24409 39 28
+DC 1142 -11378 1929 -11378 79 28
+DC 1142 -11378 1929 -11339 79 28
+DS 19291 -27087 19291 -24409 39 28
+DS 18307 -6890 19291 -6890 39 28
+DS 19291 -8189 19291 -6890 39 28
+DS 18307 -8189 19291 -8189 39 28
+DS 18307 -8976 18307 -8189 39 28
+DS -18465 -11457 -18465 -12244 39 28
+DS -19449 -11457 -18465 -11457 39 28
+DS -19449 -8898 -19449 -11457 39 28
+DA -17441 1693 -17441 1969 900 39 28
+DA -13071 1693 -12795 1693 900 39 28
+DA -11535 1693 -11535 1969 900 39 28
+DA 11535 1693 11811 1693 900 39 28
+DA 13071 1693 13071 1969 900 39 28
+DA 17441 1693 17717 1693 900 39 28
+DS 8622 -29331 19291 -29331 40 28
+DS -8524 -30709 8622 -30709 40 28
+DS -19488 -29331 -8524 -29331 40 28
+DC 2796 -17047 3583 -17047 75 28
+DC 2795 -17047 3582 -17047 75 28
+DS 8622 -29331 8622 -30709 40 28
+DS -8524 -30709 -8524 -29331 40 28
+DS -19488 -29331 -19488 -27756 40 28
+DS -19488 -27756 -18504 -27756 40 28
+DS -18504 -27756 -18504 -27087 40 28
+DS -18504 -27087 -19488 -27087 40 28
+DS -18465 -4803 -18465 -4016 40 28
+DS -18465 -4016 -19449 -4016 40 28
+DS -19449 -4016 -19449 -2205 40 28
+DS -19449 -2205 -17717 -2205 40 28
+DS -17717 -2205 -17717 -2165 40 28
+DS 19291 -27087 18307 -27087 40 28
+DS 18307 -27087 18307 -27756 40 28
+DS 18307 -27756 19291 -27756 40 28
+DS 19291 -27756 19291 -29331 40 28
+DS 17717 1693 17717 -2165 40 28
+DS 17717 -2165 17717 -2205 40 28
+DS 19291 -4094 19291 -6102 40 28
+DS 19291 -6102 18307 -6102 40 28
+DS 18307 -6102 18307 -6890 40 28
+DS 13071 1969 17441 1969 40 28
+DS 11811 1693 11811 -2480 40 28
+DS 11811 -2480 12795 -2480 40 28
+DS 12795 -2480 12795 1693 40 28
+DS -17717 1693 -17717 -2165 40 28
+DS -13071 1969 -17441 1969 40 28
+DS -11811 1693 -11811 -2480 40 28
+DS -11811 -2480 -12795 -2480 40 28
+DS -12795 -2480 -12795 1693 40 28
+DS -11535 1969 11535 1969 40 28
+$PAD
+Sh "1" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 50 "/SNES_Slot/SNES_EXT_SYS_CLK"
+Po -16732 197
+$EndPAD
+$PAD
+Sh "2" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 0 ""
+Po -15748 197
+$EndPAD
+$PAD
+Sh "3" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 47 "/SNES_Slot/SNES_EXT_PA6"
+Po -14764 197
+$EndPAD
+$PAD
+Sh "4" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 3 "/SNES_Slot/SNES_EXT_/PARD"
+Po -13780 197
+$EndPAD
+$PAD
+Sh "5" R 787 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 57 "GND"
+Po -10925 197
+$EndPAD
+$PAD
+Sh "6" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 11 "/SNES_Slot/SNES_EXT_A11"
+Po -9843 197
+$EndPAD
+$PAD
+Sh "7" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 10 "/SNES_Slot/SNES_EXT_A10"
+Po -8858 197
+$EndPAD
+$PAD
+Sh "8" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 31 "/SNES_Slot/SNES_EXT_A9"
+Po -7874 197
+$EndPAD
+$PAD
+Sh "9" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 30 "/SNES_Slot/SNES_EXT_A8"
+Po -6890 197
+$EndPAD
+$PAD
+Sh "10" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 29 "/SNES_Slot/SNES_EXT_A7"
+Po -5906 197
+$EndPAD
+$PAD
+Sh "11" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 28 "/SNES_Slot/SNES_EXT_A6"
+Po -4921 197
+$EndPAD
+$PAD
+Sh "12" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 27 "/SNES_Slot/SNES_EXT_A5"
+Po -3937 197
+$EndPAD
+$PAD
+Sh "13" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 26 "/SNES_Slot/SNES_EXT_A4"
+Po -2953 197
+$EndPAD
+$PAD
+Sh "14" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 25 "/SNES_Slot/SNES_EXT_A3"
+Po -1969 197
+$EndPAD
+$PAD
+Sh "15" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 20 "/SNES_Slot/SNES_EXT_A2"
+Po -984 197
+$EndPAD
+$PAD
+Sh "16" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 9 "/SNES_Slot/SNES_EXT_A1"
+Po 0 197
+$EndPAD
+$PAD
+Sh "17" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 8 "/SNES_Slot/SNES_EXT_A0"
+Po 984 197
+$EndPAD
+$PAD
+Sh "18" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 2 "/SNES_Slot/SNES_EXT_/IRQ"
+Po 1969 197
+$EndPAD
+$PAD
+Sh "19" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 33 "/SNES_Slot/SNES_EXT_D0"
+Po 2953 197
+$EndPAD
+$PAD
+Sh "20" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 34 "/SNES_Slot/SNES_EXT_D1"
+Po 3937 197
+$EndPAD
+$PAD
+Sh "21" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 35 "/SNES_Slot/SNES_EXT_D2"
+Po 4921 197
+$EndPAD
+$PAD
+Sh "22" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 36 "/SNES_Slot/SNES_EXT_D3"
+Po 5906 197
+$EndPAD
+$PAD
+Sh "23" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 5 "/SNES_Slot/SNES_EXT_/RD"
+Po 6890 197
+$EndPAD
+$PAD
+Sh "24" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 56 "EXT_CIC_DATA1"
+Po 7874 197
+$EndPAD
+$PAD
+Sh "25" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 54 "CIC_RESET"
+Po 8858 197
+$EndPAD
+$PAD
+Sh "26" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 58 "SNES_/RESET"
+Po 9843 197
+$EndPAD
+$PAD
+Sh "27" R 787 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 1 "+5VL"
+Po 10925 197
+$EndPAD
+$PAD
+Sh "28" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 41 "/SNES_Slot/SNES_EXT_PA0"
+Po 13780 197
+$EndPAD
+$PAD
+Sh "29" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 43 "/SNES_Slot/SNES_EXT_PA2"
+Po 14764 197
+$EndPAD
+$PAD
+Sh "30" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 45 "/SNES_Slot/SNES_EXT_PA4"
+Po 15748 197
+$EndPAD
+$PAD
+Sh "31" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 51 "AUDIO_L"
+Po 16732 197
+$EndPAD
+$PAD
+Sh "32" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 0 ""
+Po -16732 197
+$EndPAD
+$PAD
+Sh "33" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 49 "/SNES_Slot/SNES_EXT_REFRESH"
+Po -15748 197
+$EndPAD
+$PAD
+Sh "34" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 48 "/SNES_Slot/SNES_EXT_PA7"
+Po -14764 197
+$EndPAD
+$PAD
+Sh "35" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 4 "/SNES_Slot/SNES_EXT_/PAWR"
+Po -13780 197
+$EndPAD
+$PAD
+Sh "36" R 787 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 57 "GND"
+Po -10925 197
+$EndPAD
+$PAD
+Sh "37" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 12 "/SNES_Slot/SNES_EXT_A12"
+Po -9843 197
+$EndPAD
+$PAD
+Sh "38" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 13 "/SNES_Slot/SNES_EXT_A13"
+Po -8858 197
+$EndPAD
+$PAD
+Sh "39" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 14 "/SNES_Slot/SNES_EXT_A14"
+Po -7874 197
+$EndPAD
+$PAD
+Sh "40" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 15 "/SNES_Slot/SNES_EXT_A15"
+Po -6890 197
+$EndPAD
+$PAD
+Sh "41" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 16 "/SNES_Slot/SNES_EXT_A16"
+Po -5906 197
+$EndPAD
+$PAD
+Sh "42" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 17 "/SNES_Slot/SNES_EXT_A17"
+Po -4921 197
+$EndPAD
+$PAD
+Sh "43" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 18 "/SNES_Slot/SNES_EXT_A18"
+Po -3937 197
+$EndPAD
+$PAD
+Sh "44" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 19 "/SNES_Slot/SNES_EXT_A19"
+Po -2953 197
+$EndPAD
+$PAD
+Sh "45" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 21 "/SNES_Slot/SNES_EXT_A20"
+Po -1969 197
+$EndPAD
+$PAD
+Sh "46" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 22 "/SNES_Slot/SNES_EXT_A21"
+Po -984 197
+$EndPAD
+$PAD
+Sh "47" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 23 "/SNES_Slot/SNES_EXT_A22"
+Po 0 197
+$EndPAD
+$PAD
+Sh "48" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 24 "/SNES_Slot/SNES_EXT_A23"
+Po 984 197
+$EndPAD
+$PAD
+Sh "49" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 6 "/SNES_Slot/SNES_EXT_/ROMSEL"
+Po 1969 197
+$EndPAD
+$PAD
+Sh "50" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 37 "/SNES_Slot/SNES_EXT_D4"
+Po 2953 197
+$EndPAD
+$PAD
+Sh "51" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 38 "/SNES_Slot/SNES_EXT_D5"
+Po 3937 197
+$EndPAD
+$PAD
+Sh "52" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 39 "/SNES_Slot/SNES_EXT_D6"
+Po 4921 197
+$EndPAD
+$PAD
+Sh "53" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 40 "/SNES_Slot/SNES_EXT_D7"
+Po 5906 197
+$EndPAD
+$PAD
+Sh "54" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 7 "/SNES_Slot/SNES_EXT_/WR"
+Po 6890 197
+$EndPAD
+$PAD
+Sh "55" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 55 "EXT_CIC_DATA0"
+Po 7874 197
+$EndPAD
+$PAD
+Sh "56" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 53 "CIC_CLK"
+Po 8858 197
+$EndPAD
+$PAD
+Sh "57" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 32 "/SNES_Slot/SNES_EXT_CPU_CLK"
+Po 9843 197
+$EndPAD
+$PAD
+Sh "58" R 787 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 1 "+5VL"
+Po 10925 197
+$EndPAD
+$PAD
+Sh "59" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 42 "/SNES_Slot/SNES_EXT_PA1"
+Po 13780 197
+$EndPAD
+$PAD
+Sh "60" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 44 "/SNES_Slot/SNES_EXT_PA3"
+Po 14764 197
+$EndPAD
+$PAD
+Sh "61" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 46 "/SNES_Slot/SNES_EXT_PA5"
+Po 15748 197
+$EndPAD
+$PAD
+Sh "62" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 52 "AUDIO_R"
+Po 16732 197
+$EndPAD
+$PAD
+Sh "" R 4921 3150 0 0 0
+Dr 0 0 0
+At CONN N 00C00000
+Ne 0 ""
+Po -15256 394
+$EndPAD
+$PAD
+Sh "" R 4921 3150 0 0 0
+Dr 0 0 0
+At CONN N 00C00000
+Ne 0 ""
+Po 15256 394
+$EndPAD
+$PAD
+Sh "" R 23622 3150 0 0 0
+Dr 0 0 0
+At CONN N 00C00000
+Ne 0 ""
+Po 0 394
+$EndPAD
+$PAD
+Sh "" R 2362 1969 0 0 0
+Dr 0 0 0
+At CONN N 00400000
+Ne 0 ""
+Po -10945 -3819
+$EndPAD
+$PAD
+Sh "" R 2283 2362 0 0 0
+Dr 0 0 0
+At CONN N 00400000
+Ne 0 ""
+Po 14331 -3780
+$EndPAD
+$EndMODULE  J101
+$MODULE 986studio
+Po 0 0 0 15 4F44F565 00000000 ~~
+Li 986studio
+Sc 00000000
+AR 
+Op 0 0 0
+T0 0 1350 600 600 0 120 N V 21 N"986studio"
+T1 -118 2126 600 600 0 120 N V 21 N""
+DA 750 -350 700 -750 900 140 21
+DA -700 350 -700 750 900 140 21
+DS 0 0 -700 750 140 21
+DS 0 0 700 -750 140 21
+DC 0 500 0 150 140 21
+DC 0 -500 0 -150 140 21
+DC 350 0 0 0 140 21
+DC -350 0 0 0 140 21
+$EndMODULE  986studio
+$EndLIBRARY
--- a/pcb/kicad/RevE2/SNESCART_EXT2.emp
+++ b/pcb/kicad/RevE2/SNESCART_EXT2.emp
@@ -0,0 +1,552 @@
+PCBNEW-LibModule-V1  20/02/2012 21:49:13
+# encoding utf-8
+$INDEX
+SNESCART_EXT2
+$EndINDEX
+$MODULE SNESCART_EXT2
+Po 0 0 0 15 4F42AC7C 4F42B1B8 ~~
+Li SNESCART_EXT2
+Sc 4F42B1B8
+AR /4B6E16F2/4B6E1766
+Op 0 0 0
+.SolderMask 4
+.SolderPaste -4
+T0 -4134 2953 600 600 0 120 N V 21 N "J101"
+T1 0 2953 600 600 0 120 N V 21 N "SNESCART_EXT"
+DS -19764 -4804 -19764 -24410 40 28
+DS -19764 -24410 -19766 -24410 40 21
+DS -20039 -24409 -20039 -12244 39 28
+DS -19488 -27087 -19488 -24409 39 28
+DC 1142 -11378 1929 -11378 79 20
+DC 1142 -11378 1929 -11339 79 21
+DS 19921 -24409 19921 -8976 39 28
+DS 19291 -27087 19291 -24409 39 28
+DS 19291 -24409 19921 -24409 39 28
+DS 18307 -6890 19291 -6890 39 28
+DS 19291 -8189 19291 -6890 39 28
+DS 18307 -8189 19291 -8189 39 28
+DS 18307 -8976 18307 -8189 39 28
+DS 19921 -8976 18307 -8976 39 28
+DS -20039 -4803 -20039 -8898 39 28
+DS -18465 -12244 -20039 -12244 39 28
+DS -18465 -11457 -18465 -12244 39 28
+DS -19449 -11457 -18465 -11457 39 28
+DS -19449 -8898 -19449 -11457 39 28
+DS -20039 -8898 -19449 -8898 39 28
+DA -17441 1693 -17441 1969 900 39 28
+DA -13071 1693 -12795 1693 900 39 28
+DA -11535 1693 -11535 1969 900 39 28
+DA 11535 1693 11811 1693 900 39 28
+DA 13071 1693 13071 1969 900 39 28
+DA 17441 1693 17717 1693 900 39 28
+DS 8622 -29331 19291 -29331 40 28
+DS -8524 -30709 8622 -30709 40 28
+DS -19488 -29331 -8524 -29331 40 28
+DC 2796 -17047 3583 -17047 75 20
+DC 2795 -17047 3582 -17047 75 21
+DS 8622 -29331 8622 -30709 40 28
+DS -8524 -30709 -8524 -29331 40 28
+DS -19488 -29331 -19488 -27756 40 28
+DS -19488 -27756 -18504 -27756 40 28
+DS -18504 -27756 -18504 -27087 40 28
+DS -18504 -27087 -19488 -27087 40 28
+DS -19488 -24409 -20039 -24409 40 28
+DS -20039 -4803 -18465 -4803 40 28
+DS -18465 -4803 -18465 -4016 40 28
+DS -18465 -4016 -19449 -4016 40 28
+DS -19449 -4016 -19449 -2205 40 28
+DS -19449 -2205 -17717 -2205 40 28
+DS -17717 -2205 -17717 -2165 40 28
+DS 19291 -27087 18307 -27087 40 28
+DS 18307 -27087 18307 -27756 40 28
+DS 18307 -27756 19291 -27756 40 28
+DS 19291 -27756 19291 -29331 40 28
+DS 17717 1693 17717 -2165 40 28
+DS 17717 -2165 17717 -2205 40 28
+DS 17717 -2205 19921 -2205 40 28
+DS 19921 -2205 19921 -4094 40 28
+DS 19921 -4094 19291 -4094 40 28
+DS 19291 -4094 19291 -6102 40 28
+DS 19291 -6102 18307 -6102 40 28
+DS 18307 -6102 18307 -6890 40 28
+DS 13071 1969 17441 1969 40 28
+DS 11811 1693 11811 -2480 40 28
+DS 11811 -2480 12795 -2480 40 28
+DS 12795 -2480 12795 1693 40 28
+DS -17717 1693 -17717 -2165 40 28
+DS -13071 1969 -17441 1969 40 28
+DS -11811 1693 -11811 -2480 40 28
+DS -11811 -2480 -12795 -2480 40 28
+DS -12795 -2480 -12795 1693 40 28
+DS -11535 1969 11535 1969 40 28
+$PAD
+Sh "1" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 50 "/SNES_Slot/SNES_EXT_SYS_CLK"
+Po -16732 197
+$EndPAD
+$PAD
+Sh "2" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 0 ""
+Po -15748 197
+$EndPAD
+$PAD
+Sh "3" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 47 "/SNES_Slot/SNES_EXT_PA6"
+Po -14764 197
+$EndPAD
+$PAD
+Sh "4" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 3 "/SNES_Slot/SNES_EXT_/PARD"
+Po -13780 197
+$EndPAD
+$PAD
+Sh "5" R 787 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 57 "GND"
+Po -10925 197
+$EndPAD
+$PAD
+Sh "6" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 11 "/SNES_Slot/SNES_EXT_A11"
+Po -9843 197
+$EndPAD
+$PAD
+Sh "7" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 10 "/SNES_Slot/SNES_EXT_A10"
+Po -8858 197
+$EndPAD
+$PAD
+Sh "8" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 31 "/SNES_Slot/SNES_EXT_A9"
+Po -7874 197
+$EndPAD
+$PAD
+Sh "9" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 30 "/SNES_Slot/SNES_EXT_A8"
+Po -6890 197
+$EndPAD
+$PAD
+Sh "10" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 29 "/SNES_Slot/SNES_EXT_A7"
+Po -5906 197
+$EndPAD
+$PAD
+Sh "11" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 28 "/SNES_Slot/SNES_EXT_A6"
+Po -4921 197
+$EndPAD
+$PAD
+Sh "12" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 27 "/SNES_Slot/SNES_EXT_A5"
+Po -3937 197
+$EndPAD
+$PAD
+Sh "13" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 26 "/SNES_Slot/SNES_EXT_A4"
+Po -2953 197
+$EndPAD
+$PAD
+Sh "14" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 25 "/SNES_Slot/SNES_EXT_A3"
+Po -1969 197
+$EndPAD
+$PAD
+Sh "15" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 20 "/SNES_Slot/SNES_EXT_A2"
+Po -984 197
+$EndPAD
+$PAD
+Sh "16" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 9 "/SNES_Slot/SNES_EXT_A1"
+Po 0 197
+$EndPAD
+$PAD
+Sh "17" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 8 "/SNES_Slot/SNES_EXT_A0"
+Po 984 197
+$EndPAD
+$PAD
+Sh "18" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 2 "/SNES_Slot/SNES_EXT_/IRQ"
+Po 1969 197
+$EndPAD
+$PAD
+Sh "19" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 33 "/SNES_Slot/SNES_EXT_D0"
+Po 2953 197
+$EndPAD
+$PAD
+Sh "20" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 34 "/SNES_Slot/SNES_EXT_D1"
+Po 3937 197
+$EndPAD
+$PAD
+Sh "21" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 35 "/SNES_Slot/SNES_EXT_D2"
+Po 4921 197
+$EndPAD
+$PAD
+Sh "22" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 36 "/SNES_Slot/SNES_EXT_D3"
+Po 5906 197
+$EndPAD
+$PAD
+Sh "23" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 5 "/SNES_Slot/SNES_EXT_/RD"
+Po 6890 197
+$EndPAD
+$PAD
+Sh "24" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 56 "EXT_CIC_DATA1"
+Po 7874 197
+$EndPAD
+$PAD
+Sh "25" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 54 "CIC_RESET"
+Po 8858 197
+$EndPAD
+$PAD
+Sh "26" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 58 "SNES_/RESET"
+Po 9843 197
+$EndPAD
+$PAD
+Sh "27" R 787 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 1 "+5VL"
+Po 10925 197
+$EndPAD
+$PAD
+Sh "28" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 41 "/SNES_Slot/SNES_EXT_PA0"
+Po 13780 197
+$EndPAD
+$PAD
+Sh "29" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 43 "/SNES_Slot/SNES_EXT_PA2"
+Po 14764 197
+$EndPAD
+$PAD
+Sh "30" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 45 "/SNES_Slot/SNES_EXT_PA4"
+Po 15748 197
+$EndPAD
+$PAD
+Sh "31" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 51 "AUDIO_L"
+Po 16732 197
+$EndPAD
+$PAD
+Sh "32" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 0 ""
+Po -16732 197
+$EndPAD
+$PAD
+Sh "33" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 49 "/SNES_Slot/SNES_EXT_REFRESH"
+Po -15748 197
+$EndPAD
+$PAD
+Sh "34" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 48 "/SNES_Slot/SNES_EXT_PA7"
+Po -14764 197
+$EndPAD
+$PAD
+Sh "35" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 4 "/SNES_Slot/SNES_EXT_/PAWR"
+Po -13780 197
+$EndPAD
+$PAD
+Sh "36" R 787 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 57 "GND"
+Po -10925 197
+$EndPAD
+$PAD
+Sh "37" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 12 "/SNES_Slot/SNES_EXT_A12"
+Po -9843 197
+$EndPAD
+$PAD
+Sh "38" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 13 "/SNES_Slot/SNES_EXT_A13"
+Po -8858 197
+$EndPAD
+$PAD
+Sh "39" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 14 "/SNES_Slot/SNES_EXT_A14"
+Po -7874 197
+$EndPAD
+$PAD
+Sh "40" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 15 "/SNES_Slot/SNES_EXT_A15"
+Po -6890 197
+$EndPAD
+$PAD
+Sh "41" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 16 "/SNES_Slot/SNES_EXT_A16"
+Po -5906 197
+$EndPAD
+$PAD
+Sh "42" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 17 "/SNES_Slot/SNES_EXT_A17"
+Po -4921 197
+$EndPAD
+$PAD
+Sh "43" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 18 "/SNES_Slot/SNES_EXT_A18"
+Po -3937 197
+$EndPAD
+$PAD
+Sh "44" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 19 "/SNES_Slot/SNES_EXT_A19"
+Po -2953 197
+$EndPAD
+$PAD
+Sh "45" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 21 "/SNES_Slot/SNES_EXT_A20"
+Po -1969 197
+$EndPAD
+$PAD
+Sh "46" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 22 "/SNES_Slot/SNES_EXT_A21"
+Po -984 197
+$EndPAD
+$PAD
+Sh "47" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 23 "/SNES_Slot/SNES_EXT_A22"
+Po 0 197
+$EndPAD
+$PAD
+Sh "48" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 24 "/SNES_Slot/SNES_EXT_A23"
+Po 984 197
+$EndPAD
+$PAD
+Sh "49" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 6 "/SNES_Slot/SNES_EXT_/ROMSEL"
+Po 1969 197
+$EndPAD
+$PAD
+Sh "50" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 37 "/SNES_Slot/SNES_EXT_D4"
+Po 2953 197
+$EndPAD
+$PAD
+Sh "51" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 38 "/SNES_Slot/SNES_EXT_D5"
+Po 3937 197
+$EndPAD
+$PAD
+Sh "52" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 39 "/SNES_Slot/SNES_EXT_D6"
+Po 4921 197
+$EndPAD
+$PAD
+Sh "53" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 40 "/SNES_Slot/SNES_EXT_D7"
+Po 5906 197
+$EndPAD
+$PAD
+Sh "54" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 7 "/SNES_Slot/SNES_EXT_/WR"
+Po 6890 197
+$EndPAD
+$PAD
+Sh "55" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 55 "EXT_CIC_DATA0"
+Po 7874 197
+$EndPAD
+$PAD
+Sh "56" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 53 "CIC_CLK"
+Po 8858 197
+$EndPAD
+$PAD
+Sh "57" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 32 "/SNES_Slot/SNES_EXT_CPU_CLK"
+Po 9843 197
+$EndPAD
+$PAD
+Sh "58" R 787 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 1 "+5VL"
+Po 10925 197
+$EndPAD
+$PAD
+Sh "59" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 42 "/SNES_Slot/SNES_EXT_PA1"
+Po 13780 197
+$EndPAD
+$PAD
+Sh "60" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 44 "/SNES_Slot/SNES_EXT_PA3"
+Po 14764 197
+$EndPAD
+$PAD
+Sh "61" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 46 "/SNES_Slot/SNES_EXT_PA5"
+Po 15748 197
+$EndPAD
+$PAD
+Sh "62" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 52 "AUDIO_R"
+Po 16732 197
+$EndPAD
+$PAD
+Sh "" R 4921 3150 0 0 0
+Dr 0 0 0
+At CONN N 00C00000
+Ne 0 ""
+Po -15256 394
+$EndPAD
+$PAD
+Sh "" R 4921 3150 0 0 0
+Dr 0 0 0
+At CONN N 00C00000
+Ne 0 ""
+Po 15256 394
+$EndPAD
+$PAD
+Sh "" R 23622 3150 0 0 0
+Dr 0 0 0
+At CONN N 00C00000
+Ne 0 ""
+Po 0 394
+$EndPAD
+$PAD
+Sh "" R 2362 1969 0 0 0
+Dr 0 0 0
+At CONN N 00400000
+Ne 0 ""
+Po -10945 -3819
+$EndPAD
+$PAD
+Sh "" R 2283 2362 0 0 0
+Dr 0 0 0
+At CONN N 00400000
+Ne 0 ""
+Po 14331 -3780
+$EndPAD
+$EndMODULE  SNESCART_EXT2
+$EndLIBRARY
--- a/pcb/kicad/RevE2/SNESCART_EXT2.mod
+++ b/pcb/kicad/RevE2/SNESCART_EXT2.mod
@@ -0,0 +1,552 @@
+PCBNEW-LibModule-V1  20/02/2012 21:47:15
+# encoding utf-8
+$INDEX
+SNESCART_EXT2
+$EndINDEX
+$MODULE SNESCART_EXT2
+Po 0 0 0 15 4F42AC7C 4F42AD50 ~~
+Li SNESCART_EXT2
+Sc 4F42AD50
+AR /4B6E16F2/4B6E1766
+Op 0 0 0
+.SolderMask 4
+.SolderPaste -4
+T0 -4134 2953 600 600 0 120 N V 21 N "J101"
+T1 0 2953 600 600 0 120 N V 21 N "SNESCART_EXT"
+DS -19764 -4804 -19764 -24410 40 28
+DS -19764 -24410 -19766 -24410 40 21
+DS -20039 -24409 -20039 -12244 39 28
+DS -19488 -27087 -19488 -24409 39 28
+DC 1142 -11378 1929 -11378 79 20
+DC 1142 -11378 1929 -11339 79 21
+DS 19921 -24409 19921 -8976 39 28
+DS 19291 -27087 19291 -24409 39 28
+DS 19291 -24409 19921 -24409 39 28
+DS 18307 -6890 19291 -6890 39 28
+DS 19291 -8189 19291 -6890 39 28
+DS 18307 -8189 19291 -8189 39 28
+DS 18307 -8976 18307 -8189 39 28
+DS 19921 -8976 18307 -8976 39 28
+DS -20039 -4803 -20039 -8898 39 28
+DS -18465 -12244 -20039 -12244 39 28
+DS -18465 -11457 -18465 -12244 39 28
+DS -19449 -11457 -18465 -11457 39 28
+DS -19449 -8898 -19449 -11457 39 28
+DS -20039 -8898 -19449 -8898 39 28
+DA -17441 1693 -17441 1969 900 39 28
+DA -13071 1693 -12795 1693 900 39 28
+DA -11535 1693 -11535 1969 900 39 28
+DA 11535 1693 11811 1693 900 39 28
+DA 13071 1693 13071 1969 900 39 28
+DA 17441 1693 17717 1693 900 39 28
+DS 8622 -29331 19291 -29331 40 28
+DS -8524 -30709 8622 -30709 40 28
+DS -19488 -29331 -8524 -29331 40 28
+DC 2796 -17047 3583 -17047 75 20
+DC 2795 -17047 3582 -17047 75 21
+DS 8622 -29331 8622 -30709 40 28
+DS -8524 -30709 -8524 -29331 40 28
+DS -19488 -29331 -19488 -27756 40 28
+DS -19488 -27756 -18504 -27756 40 28
+DS -18504 -27756 -18504 -27087 40 28
+DS -18504 -27087 -19488 -27087 40 28
+DS -19488 -24409 -20039 -24409 40 28
+DS -20039 -4803 -18465 -4803 40 28
+DS -18465 -4803 -18465 -4016 40 28
+DS -18465 -4016 -19449 -4016 40 28
+DS -19449 -4016 -19449 -2205 40 28
+DS -19449 -2205 -17717 -2205 40 28
+DS -17717 -2205 -17717 -2165 40 28
+DS 19291 -27087 18307 -27087 40 28
+DS 18307 -27087 18307 -27756 40 28
+DS 18307 -27756 19291 -27756 40 28
+DS 19291 -27756 19291 -29331 40 28
+DS 17717 1693 17717 -2165 40 28
+DS 17717 -2165 17717 -2205 40 28
+DS 17717 -2205 19921 -2205 40 28
+DS 19921 -2205 19921 -4094 40 28
+DS 19921 -4094 19291 -4094 40 28
+DS 19291 -4094 19291 -6102 40 28
+DS 19291 -6102 18307 -6102 40 28
+DS 18307 -6102 18307 -6890 40 28
+DS 13071 1969 17441 1969 40 28
+DS 11811 1693 11811 -2480 40 28
+DS 11811 -2480 12795 -2480 40 28
+DS 12795 -2480 12795 1693 40 28
+DS -17717 1693 -17717 -2165 40 28
+DS -13071 1969 -17441 1969 40 28
+DS -11811 1693 -11811 -2480 40 28
+DS -11811 -2480 -12795 -2480 40 28
+DS -12795 -2480 -12795 1693 40 28
+DS -11535 1969 11535 1969 40 28
+$PAD
+Sh "1" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 50 "/SNES_Slot/SNES_EXT_SYS_CLK"
+Po -16732 197
+$EndPAD
+$PAD
+Sh "2" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 0 ""
+Po -15748 197
+$EndPAD
+$PAD
+Sh "3" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 47 "/SNES_Slot/SNES_EXT_PA6"
+Po -14764 197
+$EndPAD
+$PAD
+Sh "4" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 3 "/SNES_Slot/SNES_EXT_/PARD"
+Po -13780 197
+$EndPAD
+$PAD
+Sh "5" R 787 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 57 "GND"
+Po -10925 197
+$EndPAD
+$PAD
+Sh "6" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 11 "/SNES_Slot/SNES_EXT_A11"
+Po -9843 197
+$EndPAD
+$PAD
+Sh "7" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 10 "/SNES_Slot/SNES_EXT_A10"
+Po -8858 197
+$EndPAD
+$PAD
+Sh "8" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 31 "/SNES_Slot/SNES_EXT_A9"
+Po -7874 197
+$EndPAD
+$PAD
+Sh "9" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 30 "/SNES_Slot/SNES_EXT_A8"
+Po -6890 197
+$EndPAD
+$PAD
+Sh "10" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 29 "/SNES_Slot/SNES_EXT_A7"
+Po -5906 197
+$EndPAD
+$PAD
+Sh "11" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 28 "/SNES_Slot/SNES_EXT_A6"
+Po -4921 197
+$EndPAD
+$PAD
+Sh "12" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 27 "/SNES_Slot/SNES_EXT_A5"
+Po -3937 197
+$EndPAD
+$PAD
+Sh "13" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 26 "/SNES_Slot/SNES_EXT_A4"
+Po -2953 197
+$EndPAD
+$PAD
+Sh "14" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 25 "/SNES_Slot/SNES_EXT_A3"
+Po -1969 197
+$EndPAD
+$PAD
+Sh "15" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 20 "/SNES_Slot/SNES_EXT_A2"
+Po -984 197
+$EndPAD
+$PAD
+Sh "16" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 9 "/SNES_Slot/SNES_EXT_A1"
+Po 0 197
+$EndPAD
+$PAD
+Sh "17" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 8 "/SNES_Slot/SNES_EXT_A0"
+Po 984 197
+$EndPAD
+$PAD
+Sh "18" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 2 "/SNES_Slot/SNES_EXT_/IRQ"
+Po 1969 197
+$EndPAD
+$PAD
+Sh "19" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 33 "/SNES_Slot/SNES_EXT_D0"
+Po 2953 197
+$EndPAD
+$PAD
+Sh "20" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 34 "/SNES_Slot/SNES_EXT_D1"
+Po 3937 197
+$EndPAD
+$PAD
+Sh "21" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 35 "/SNES_Slot/SNES_EXT_D2"
+Po 4921 197
+$EndPAD
+$PAD
+Sh "22" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 36 "/SNES_Slot/SNES_EXT_D3"
+Po 5906 197
+$EndPAD
+$PAD
+Sh "23" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 5 "/SNES_Slot/SNES_EXT_/RD"
+Po 6890 197
+$EndPAD
+$PAD
+Sh "24" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 56 "EXT_CIC_DATA1"
+Po 7874 197
+$EndPAD
+$PAD
+Sh "25" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 54 "CIC_RESET"
+Po 8858 197
+$EndPAD
+$PAD
+Sh "26" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 58 "SNES_/RESET"
+Po 9843 197
+$EndPAD
+$PAD
+Sh "27" R 787 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 1 "+5VL"
+Po 10925 197
+$EndPAD
+$PAD
+Sh "28" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 41 "/SNES_Slot/SNES_EXT_PA0"
+Po 13780 197
+$EndPAD
+$PAD
+Sh "29" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 43 "/SNES_Slot/SNES_EXT_PA2"
+Po 14764 197
+$EndPAD
+$PAD
+Sh "30" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 45 "/SNES_Slot/SNES_EXT_PA4"
+Po 15748 197
+$EndPAD
+$PAD
+Sh "31" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 51 "AUDIO_L"
+Po 16732 197
+$EndPAD
+$PAD
+Sh "32" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 0 ""
+Po -16732 197
+$EndPAD
+$PAD
+Sh "33" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 49 "/SNES_Slot/SNES_EXT_REFRESH"
+Po -15748 197
+$EndPAD
+$PAD
+Sh "34" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 48 "/SNES_Slot/SNES_EXT_PA7"
+Po -14764 197
+$EndPAD
+$PAD
+Sh "35" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 4 "/SNES_Slot/SNES_EXT_/PAWR"
+Po -13780 197
+$EndPAD
+$PAD
+Sh "36" R 787 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 57 "GND"
+Po -10925 197
+$EndPAD
+$PAD
+Sh "37" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 12 "/SNES_Slot/SNES_EXT_A12"
+Po -9843 197
+$EndPAD
+$PAD
+Sh "38" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 13 "/SNES_Slot/SNES_EXT_A13"
+Po -8858 197
+$EndPAD
+$PAD
+Sh "39" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 14 "/SNES_Slot/SNES_EXT_A14"
+Po -7874 197
+$EndPAD
+$PAD
+Sh "40" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 15 "/SNES_Slot/SNES_EXT_A15"
+Po -6890 197
+$EndPAD
+$PAD
+Sh "41" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 16 "/SNES_Slot/SNES_EXT_A16"
+Po -5906 197
+$EndPAD
+$PAD
+Sh "42" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 17 "/SNES_Slot/SNES_EXT_A17"
+Po -4921 197
+$EndPAD
+$PAD
+Sh "43" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 18 "/SNES_Slot/SNES_EXT_A18"
+Po -3937 197
+$EndPAD
+$PAD
+Sh "44" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 19 "/SNES_Slot/SNES_EXT_A19"
+Po -2953 197
+$EndPAD
+$PAD
+Sh "45" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 21 "/SNES_Slot/SNES_EXT_A20"
+Po -1969 197
+$EndPAD
+$PAD
+Sh "46" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 22 "/SNES_Slot/SNES_EXT_A21"
+Po -984 197
+$EndPAD
+$PAD
+Sh "47" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 23 "/SNES_Slot/SNES_EXT_A22"
+Po 0 197
+$EndPAD
+$PAD
+Sh "48" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 24 "/SNES_Slot/SNES_EXT_A23"
+Po 984 197
+$EndPAD
+$PAD
+Sh "49" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 6 "/SNES_Slot/SNES_EXT_/ROMSEL"
+Po 1969 197
+$EndPAD
+$PAD
+Sh "50" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 37 "/SNES_Slot/SNES_EXT_D4"
+Po 2953 197
+$EndPAD
+$PAD
+Sh "51" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 38 "/SNES_Slot/SNES_EXT_D5"
+Po 3937 197
+$EndPAD
+$PAD
+Sh "52" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 39 "/SNES_Slot/SNES_EXT_D6"
+Po 4921 197
+$EndPAD
+$PAD
+Sh "53" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 40 "/SNES_Slot/SNES_EXT_D7"
+Po 5906 197
+$EndPAD
+$PAD
+Sh "54" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 7 "/SNES_Slot/SNES_EXT_/WR"
+Po 6890 197
+$EndPAD
+$PAD
+Sh "55" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 55 "EXT_CIC_DATA0"
+Po 7874 197
+$EndPAD
+$PAD
+Sh "56" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 53 "CIC_CLK"
+Po 8858 197
+$EndPAD
+$PAD
+Sh "57" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 32 "/SNES_Slot/SNES_EXT_CPU_CLK"
+Po 9843 197
+$EndPAD
+$PAD
+Sh "58" R 787 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 1 "+5VL"
+Po 10925 197
+$EndPAD
+$PAD
+Sh "59" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 42 "/SNES_Slot/SNES_EXT_PA1"
+Po 13780 197
+$EndPAD
+$PAD
+Sh "60" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 44 "/SNES_Slot/SNES_EXT_PA3"
+Po 14764 197
+$EndPAD
+$PAD
+Sh "61" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 46 "/SNES_Slot/SNES_EXT_PA5"
+Po 15748 197
+$EndPAD
+$PAD
+Sh "62" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 52 "AUDIO_R"
+Po 16732 197
+$EndPAD
+$PAD
+Sh "" R 4921 3150 0 0 0
+Dr 0 0 0
+At CONN N 00C00000
+Ne 0 ""
+Po -15256 394
+$EndPAD
+$PAD
+Sh "" R 4921 3150 0 0 0
+Dr 0 0 0
+At CONN N 00C00000
+Ne 0 ""
+Po 15256 394
+$EndPAD
+$PAD
+Sh "" R 23622 3150 0 0 0
+Dr 0 0 0
+At CONN N 00C00000
+Ne 0 ""
+Po 0 394
+$EndPAD
+$PAD
+Sh "" R 2362 1969 0 0 0
+Dr 0 0 0
+At CONN N 00400000
+Ne 0 ""
+Po -10945 -3819
+$EndPAD
+$PAD
+Sh "" R 2283 2362 0 0 0
+Dr 0 0 0
+At CONN N 00400000
+Ne 0 ""
+Po 14331 -3780
+$EndPAD
+$EndMODULE  SNESCART_EXT2
+$EndLIBRARY
--- a/pcb/kicad/RevE2/fpga.sch
+++ b/pcb/kicad/RevE2/fpga.sch
@@ -1,4 +1,4 @@
-EESchema Schematic File Version 2  date Mon 26 Dec 2011 09:56:14 PM CET
+EESchema Schematic File Version 2  date Mon 02 Jan 2012 11:27:18 PM CET
 LIBS:power
 LIBS:device
 LIBS:transistors
@@ -40,13 +40,14 @@ LIBS:cs4344
 LIBS:double_sch_kcom
 LIBS:usb_minib
 LIBS:mic23250
+LIBS:sd2snes-cache
 EELAYER 25  0
 EELAYER END
 $Descr A3 16535 11700
 encoding utf-8
 Sheet 6 6
 Title "sd2snes Mark II"
-Date "26 dec 2011"
+Date "2 jan 2012"
 Rev "E2"
 Comp "Maximilian Rehkopf"
 Comment1 ""
--- a/pcb/kicad/RevE2/mcu.sch
+++ b/pcb/kicad/RevE2/mcu.sch
@@ -1,4 +1,4 @@
-EESchema Schematic File Version 2  date Mon 26 Dec 2011 09:56:13 PM CET
+EESchema Schematic File Version 2  date Mon 02 Jan 2012 11:27:18 PM CET
 LIBS:power
 LIBS:device
 LIBS:transistors
@@ -40,13 +40,14 @@ LIBS:cs4344
 LIBS:double_sch_kcom
 LIBS:usb_minib
 LIBS:mic23250
+LIBS:sd2snes-cache
 EELAYER 25  0
 EELAYER END
 $Descr A4 11700 8267
 encoding utf-8
 Sheet 4 6
 Title "sd2snes Mark II"
-Date "26 dec 2011"
+Date "2 jan 2012"
 Rev "E2"
 Comp "Maximilian Rehkopf"
 Comment1 ""
@@ -578,7 +579,7 @@ USB_SWCONN
 Text GLabel 2700 4200 0    50   Output ~ 0
 USB_SWCONN
 Text Notes 750  1700 0    50   ~ 0
-or 3000mcd LEDs (10k for R401-403)
+or super bright LEDs (10k for R401-403)\nuse 6.35mm LED spacers
 NoConn ~ 6700 5500
 NoConn ~ 6700 5400
 NoConn ~ 6700 5300
--- a/pcb/kicad/RevE2/memory.sch
+++ b/pcb/kicad/RevE2/memory.sch
@@ -1,4 +1,4 @@
-EESchema Schematic File Version 2  date Mon 26 Dec 2011 09:56:13 PM CET
+EESchema Schematic File Version 2  date Mon 02 Jan 2012 11:27:18 PM CET
 LIBS:power
 LIBS:device
 LIBS:transistors
@@ -40,13 +40,14 @@ LIBS:cs4344
 LIBS:double_sch_kcom
 LIBS:usb_minib
 LIBS:mic23250
+LIBS:sd2snes-cache
 EELAYER 25  0
 EELAYER END
 $Descr A4 11700 8267
 encoding utf-8
 Sheet 3 6
 Title "sd2snes Mark II"
-Date "26 dec 2011"
+Date "2 jan 2012"
 Rev "E2"
 Comp "Maximilian Rehkopf"
 Comment1 ""
--- a/pcb/kicad/RevE2/padreduce.sh
+++ b/pcb/kicad/RevE2/padreduce.sh
@@ -2,9 +2,9 @@ cp "$1" "$1".bak

 sed -e 's/^%ADD\(..\)R/%ADD\1O/g' < "$1" > "$1".tmp1

-grep ^%ADD..O "$1".tmp1 | while read ln; do LS=${ln:0:8}; X=${ln:8:8}; Y=${ln:17:8}; X2=`echo $X-.002 | bc -l`; Y2=`echo $Y-.002 | bc -l`; echo $LS`printf '%01.6f' $X2`X`printf '%01.6f' $Y2`*%; done > "$1".tmp2
+grep ^%ADD..O "$1".tmp1 | while read ln; do LS=${ln:0:8}; X=${ln:8:8}; Y=${ln:17:8}; X2=`echo $X-.001 | bc -l`; Y2=`echo $Y-.001 | bc -l`; echo $LS`printf '%01.6f' $X2`X`printf '%01.6f' $Y2`*%; done > "$1".tmp2

-grep ^%ADD..C "$1".tmp1 | while read ln; do LS=${ln:0:8}; X=${ln:8:8}; X2=`echo $X-.002 | bc -l`; echo $LS`printf '%01.6f' $X2`*%; done >> "$1".tmp2
+grep ^%ADD..C "$1".tmp1 | while read ln; do LS=${ln:0:8}; X=${ln:8:8}; X2=`echo $X-.001 | bc -l`; echo $LS`printf '%01.6f' $X2`*%; done >> "$1".tmp2

 while read ln; do echo "$ln" | grep '^%ADD' >/dev/null && break; echo "$ln"; done < "$1".tmp1 > "$1"

--- a/pcb/kicad/RevE2/pwr_misc.sch
+++ b/pcb/kicad/RevE2/pwr_misc.sch
@@ -1,4 +1,4 @@
-EESchema Schematic File Version 2  date Mon 26 Dec 2011 09:56:13 PM CET
+EESchema Schematic File Version 2  date Mon 02 Jan 2012 11:27:18 PM CET
 LIBS:power
 LIBS:device
 LIBS:transistors
@@ -40,13 +40,14 @@ LIBS:cs4344
 LIBS:double_sch_kcom
 LIBS:usb_minib
 LIBS:mic23250
+LIBS:sd2snes-cache
 EELAYER 25  0
 EELAYER END
 $Descr A4 11700 8267
 encoding utf-8
 Sheet 5 6
 Title "sd2snes Mark II"
-Date "26 dec 2011"
+Date "2 jan 2012"
 Rev "E2"
 Comp "Maximilian Rehkopf"
 Comment1 ""
@@ -79,19 +80,13 @@ Wire Wire Line
 	1750 4250 1750 4050
 Connection ~ 4100 2600
 Wire Wire Line
-	4100 2800 4100 2600
-Wire Wire Line
-	4100 2600 4100 2400
+	4100 2800 4100 2400
 Wire Wire Line
 	3250 2600 3350 2600
 Wire Wire Line
 	1600 3200 1600 3450
 Wire Wire Line
-	1850 2600 1750 2600
-Wire Wire Line
-	1750 2600 1600 2600
-Wire Wire Line
-	1600 2600 1000 2600
+	1850 2600 1000 2600
 Wire Wire Line
 	1000 2600 1000 2400
 Wire Wire Line
@@ -134,17 +129,13 @@ Wire Notes Line
 	4550 500  4550 7750
 Connection ~ 9750 4750
 Wire Wire Line
-	9700 4750 9750 4750
-Wire Wire Line
-	9750 4750 9800 4750
+	9700 4750 9800 4750
 Wire Wire Line
 	9750 5400 9750 5500
 Wire Wire Line
 	9150 5500 9150 5400
 Wire Wire Line
-	9150 4900 9150 4750
-Wire Wire Line
-	9150 4750 9150 4600
+	9150 4900 9150 4600
 Wire Wire Line
 	8300 5000 8300 4750
 Wire Wire Line
@@ -155,9 +146,7 @@ Wire Wire Line
 	10350 3900 10350 3700
 Connection ~ 10350 4400
 Wire Wire Line
-	10350 4500 10350 4400
-Wire Wire Line
-	10350 4400 10350 4300
+	10350 4500 10350 4300
 Connection ~ 10050 3700
 Wire Wire Line
 	9650 3900 9650 3800
@@ -174,9 +163,7 @@ Wire Wire Line
 Wire Wire Line
 	11100 2400 11100 2300
 Wire Wire Line
-	9600 1800 9000 1800
-Wire Wire Line
-	9000 1800 8150 1800
+	9600 1800 8150 1800
 Wire Wire Line
 	6700 2100 6350 2100
 Wire Wire Line
@@ -202,15 +189,9 @@ Wire Wire Line
 Wire Wire Line
 	3950 5300 3950 5500
 Wire Wire Line
-	3950 5500 3500 5500
+	3950 5500 3250 5500
 Wire Wire Line
-	3500 5500 3250 5500
-Wire Wire Line
-	1850 5500 1750 5500
-Wire Wire Line
-	1750 5500 1600 5500
-Wire Wire Line
-	1600 5500 1150 5500
+	1850 5500 1150 5500
 Wire Wire Line
 	1150 5500 1150 5300
 Wire Wire Line
@@ -221,15 +202,9 @@ Connection ~ 1750 5500
 Wire Wire Line
 	1150 6650 1150 6850
 Wire Wire Line
-	1150 6850 1600 6850
+	1150 6850 1850 6850
 Wire Wire Line
-	1600 6850 1750 6850
-Wire Wire Line
-	1750 6850 1850 6850
-Wire Wire Line
-	3250 6850 3500 6850
-Wire Wire Line
-	3500 6850 3950 6850
+	3250 6850 3950 6850
 Wire Wire Line
 	3950 6850 3950 6650
 Wire Wire Line
@@ -248,23 +223,15 @@ Wire Wire Line
 Wire Wire Line
 	6700 1800 6350 1800
 Wire Wire Line
-	8150 1400 9200 1400
-Wire Wire Line
-	9200 1400 9350 1400
-Wire Wire Line
-	9350 1400 9600 1400
+	8150 1400 9600 1400
 Wire Wire Line
 	8150 2100 8600 2100
 Wire Wire Line
 	11100 1900 11100 1800
 Wire Wire Line
-	10150 6350 10150 6450
+	10150 6350 10150 6550
 Wire Wire Line
-	10150 6450 10150 6550
-Wire Wire Line
-	10150 5750 10150 5850
-Wire Wire Line
-	10150 5850 10150 5950
+	10150 5750 10150 5950
 Wire Wire Line
 	6300 7000 6100 7000
 Wire Wire Line
@@ -274,9 +241,7 @@ Wire Wire Line
 Wire Wire Line
 	9650 4300 9650 4500
 Wire Wire Line
-	10350 3700 10050 3700
-Wire Wire Line
-	10050 3700 7250 3700
+	10350 3700 7250 3700
 Wire Wire Line
 	10050 4300 10050 4400
 Wire Wire Line
@@ -288,18 +253,14 @@ Wire Wire Line
 Wire Wire Line
 	9150 4000 9150 4200
 Wire Wire Line
-	7700 4600 7700 4750
-Wire Wire Line
-	7700 4750 7700 4900
+	7700 4600 7700 4900
 Wire Wire Line
 	7750 4750 7700 4750
 Connection ~ 7700 4750
 Wire Wire Line
 	8300 5400 8300 5500
 Wire Wire Line
-	8350 4750 8300 4750
-Wire Wire Line
-	8300 4750 8250 4750
+	8350 4750 8250 4750
 Connection ~ 8300 4750
 Wire Wire Line
 	9200 4750 9150 4750
@@ -362,34 +323,24 @@ Wire Wire Line
 	1600 2800 1600 2600
 Connection ~ 1600 2600
 Wire Wire Line
-	3950 2600 4000 2600
-Wire Wire Line
-	4000 2600 4100 2600
+	3950 2600 4100 2600
 Wire Wire Line
 	1000 3850 1000 4050
 Wire Wire Line
-	1000 4050 1600 4050
-Wire Wire Line
-	1600 4050 1750 4050
-Wire Wire Line
-	1750 4050 1850 4050
+	1000 4050 1850 4050
 Wire Wire Line
 	1600 4050 1600 4250
 Connection ~ 1600 4050
 Wire Wire Line
 	1600 4650 1600 4900
 Wire Wire Line
-	4100 4050 4000 4050
-Wire Wire Line
-	4000 4050 3950 4050
+	3950 4050 4100 4050
 Connection ~ 4100 4050
 Wire Wire Line
 	4000 4250 4000 4050
 Connection ~ 4000 4050
 Wire Wire Line
-	4100 4250 4100 4050
-Wire Wire Line
-	4100 4050 4100 3800
+	4100 4250 4100 3800
 Text Label 3250 4050 0    50   ~ 0
 LX33
 Text Label 3250 2600 0    50   ~ 0
--- a/pcb/kicad/RevE2/sd2snes.brd
+++ b/pcb/kicad/RevE2/sd2snes.brd
--- a/pcb/kicad/RevE2/sd2snes.lst
+++ b/pcb/kicad/RevE2/sd2snes.lst
@@ -0,0 +1,153 @@
+ref	value	footprint
+BT351	Keystone 1059 / KZH20PCB	BT_KEYSTONE_1059_20MM
+C101	100n	SM0805_FIXEDMASK
+C102	100n	SM0805_FIXEDMASK
+C103	100n	SM0805_FIXEDMASK
+C104	100n	SM0805_FIXEDMASK
+C105	100n	SM0805_FIXEDMASK
+C106	100n	SM0805_FIXEDMASK
+C111	100n	SM0805_FIXEDMASK
+C112	100n	SM0805_FIXEDMASK
+C113	100n	SM0805_FIXEDMASK
+C114	100n	SM0805_FIXEDMASK
+C115	100n	SM0805_FIXEDMASK
+C116	100n	SM0805_FIXEDMASK
+C121	10p	SM0805_FIXEDMASK
+C122	10p	SM0805_FIXEDMASK
+C123	10p	SM0805_FIXEDMASK
+C124	10p	SM0805_FIXEDMASK
+C125	10p	SM0805_FIXEDMASK
+C126	10p	SM0805_FIXEDMASK
+C127	10p	SM0805_FIXEDMASK
+C128	10p	SM0805_FIXEDMASK
+C201	100n	SM0805_FIXEDMASK
+C202	100n	SM0805_FIXEDMASK
+C203	100n	SM0805_FIXEDMASK
+C204	100n	SM0805_FIXEDMASK
+C205	100n	SM0805_FIXEDMASK
+C206	100n	SM0805_FIXEDMASK
+C207	100n	SM0805_FIXEDMASK
+C208	100n	SM0805_FIXEDMASK
+C209	100n	SM0805_FIXEDMASK
+C210	100n	SM0805_FIXEDMASK
+C211	100n	SM0805_FIXEDMASK
+C212	100n	SM0805_FIXEDMASK
+C213	100n	SM0805_FIXEDMASK
+C214	100n	SM0805_FIXEDMASK
+C215	100n	SM0805_FIXEDMASK
+C221	100n	SM0805_FIXEDMASK
+C222	100n	SM0805_FIXEDMASK
+C223	100n	SM0805_FIXEDMASK
+C224	100n	SM0805_FIXEDMASK
+C231	100n	SM0805_FIXEDMASK
+C232	100n	SM0805_FIXEDMASK
+C233	100n	SM0805_FIXEDMASK
+C234	100n	SM0805_FIXEDMASK
+C301	4.7u	SM0805_FIXEDMASK
+C302	4.7u	SM0805_FIXEDMASK
+C303	4.7u	SM0805_FIXEDMASK
+C304	4.7u	SM0805_FIXEDMASK
+C311	4.7u	SM0805_FIXEDMASK
+C312	4.7u	SM0805_FIXEDMASK
+C321	4.7u	SM0805_FIXEDMASK
+C322	4.7u	SM0805_FIXEDMASK
+C331	100n	SM0805_FIXEDMASK
+C332	100p	SM0805_FIXEDMASK
+C333	100p	SM0805_FIXEDMASK
+C341	100n	SM0805_FIXEDMASK
+C342	1u	SM0805_FIXEDMASK
+C343	100n	SM0805_FIXEDMASK
+C344	10u	SM0805_FIXEDMASK
+C345	10u	SM0805_FIXEDMASK
+C346	3.3u	SM0805_FIXEDMASK
+C347	10n	SM0805_FIXEDMASK
+C348	3.3u	SM0805_FIXEDMASK
+C349	10n	SM0805_FIXEDMASK
+C401	100n	SM0805_FIXEDMASK
+C402	100n	SM0805_FIXEDMASK
+C403	100n	SM0805_FIXEDMASK
+C404	100n	SM0805_FIXEDMASK
+C405	100n	SM0805_FIXEDMASK
+C406	33p	SM0805_FIXEDMASK
+C407	33p	SM0805_FIXEDMASK
+C408	10p	SM0805_FIXEDMASK
+C409	10p	SM0805_FIXEDMASK
+C411	10u	SM0805_FIXEDMASK
+C412	100n	SM0805_FIXEDMASK
+C501	100n	SM0805_FIXEDMASK
+C502	100n	SM0805_FIXEDMASK
+C511	100n	SM0805_FIXEDMASK
+D401	LED 2mA 1.9V, green	LED-3MM-FIXED
+D402	LED 2mA 1.8V, yellow	LED-3MM-FIXED
+D403	LED 2mA 1.7V, red	LED-3MM-FIXED
+D511	BAT54C	SOT23EBC
+FB341	FILTER	
+FB342	FILTER	
+J101	SNESCART_EXT	SNESCART_EXT
+J411	Hirose DM1AA	
+J421	Molex 54819	USB-MINIB-THT
+JP401	JUMPER	
+JP402	JUMPER	
+L301	4.7uH	
+L302	4.7uH	
+P113	CONN_1	
+P401	CONN_7X2	pin_array_7x2
+P402	CONN_2	PIN_ARRAY_2X1
+P403	CONN_2	PIN_ARRAY_2X1
+P404	CONN_3X2	
+Q101	2N2222A	
+Q301	IRLML6402PbF	
+Q511	2N2222A	SOT23EBC
+R101	270	SM0805_FIXEDMASK
+R102	100k	
+R103	4k7	
+R301	20k	SM0805_FIXEDMASK
+R331	680	SM0805_FIXEDMASK
+R332	680	SM0805_FIXEDMASK
+R333	680	SM0805_FIXEDMASK
+R341	470	SM0805_FIXEDMASK
+R342	10k	SM0805_FIXEDMASK
+R343	470	SM0805_FIXEDMASK
+R344	10k	SM0805_FIXEDMASK
+R401	680	SM0805_FIXEDMASK
+R402	680	SM0805_FIXEDMASK
+R403	680	SM0805_FIXEDMASK
+R404	10k	SM0805_FIXEDMASK
+R405	100	SM0805_FIXEDMASK
+R406	100	SM0805_FIXEDMASK
+R407	10k	SM0805_FIXEDMASK
+R421	33	SM0805_FIXEDMASK
+R422	33	SM0805_FIXEDMASK
+R423	1.5k	SM0805_FIXEDMASK
+R511	20k	SM0805_FIXEDMASK
+R512	4k7	SM0805_FIXEDMASK
+R513	100k	SM0805_FIXEDMASK
+RA101	100	
+RA102	100	
+RA103	FB	
+RA104	FB	
+RA105	100	
+RA106	100	
+RA107	100	
+RA108	100	
+RA109	100	
+RA110	100	
+RA111	100	
+RA112	100	
+RA113	100	
+RA114	100	
+U101	74ALVC164245DGG	TSSOP48
+U102	74ALVC164245DGG	TSSOP48
+U103	74ALVC164245DGG	TSSOP48
+U201	XC3S400-PQ208	PQFP208
+U301	MCP1603T-120I/OS	
+U302	MCP1603T-330I/OS	
+U311	MCP1824-1802E/OT	SOT23-5
+U321	MCP1824-2502E/OT	SOT23-5
+U331	PIC12F629-I/P	SO8N
+U341	CS4344	TSSOP10
+U401	LPC1754	LQFP80-.5
+U501	MT45W8MW16	VFBGA54
+U511	CY62148EV30-ZSXI	
+X401	12MHz	XTAL_SMD_05032
+X402	32.768kHz	XTAL_SMD_05019
--- a/pcb/kicad/RevE2/sd2snes.pro
+++ b/pcb/kicad/RevE2/sd2snes.pro
@@ -1,4 +1,4 @@
-update=Tue 27 Dec 2011 01:22:01 AM CET
+update=jeu. 23 févr. 2012 17:42:34 CET
 version=1
 last_client=pcbnew
 [general]
@@ -38,7 +38,11 @@ offY_E=0
 RptD_X=0
 RptD_Y=100
 RptLab=1
+SimCmd=
+UseNetN=0
 LabSize=50
+PrintMonochrome=1
+ShowSheetReferenceAndTitleBlock=1
 [eeschema/libraries]
 LibName1=power
 LibName2=device
@@ -83,10 +87,11 @@ LibName40=libs/usb_minib
 LibName41=libs/mic23250
 [pcbnew]
 version=1
-PadDrlX=400
-PadDimH=660
-PadDimV=660
+PadDrlX=0
+PadDimH=2362
+PadDimV=1969
 BoardThickness=630
+SgPcb45=1
 TxtPcbV=800
 TxtPcbH=600
 TxtModV=600
@@ -96,7 +101,7 @@ VEgarde=40
 DrawLar=70
 EdgeLar=40
 TxtLar=120
-MSegLar=79
+MSegLar=140
 LastNetListRead=sd2snes.net
 [pcbnew/libraries]
 LibDir=../../kicad
@@ -111,6 +116,7 @@ LibName8=valves
 LibName9=led
 LibName10=dip_sockets
 LibName11=libs/mypackages
-LibName12=libs/hai
-LibName13=libs/snescart
-LibName14=libs/sdcard
+LibName12=libs/snescart
+LibName13=libs/sdcard
+LibName14=libs/snail
+LibName15=J101
--- a/pcb/kicad/RevE2/sd2snes.sch
+++ b/pcb/kicad/RevE2/sd2snes.sch
@@ -1,4 +1,4 @@
-EESchema Schematic File Version 2  date Mon 26 Dec 2011 09:56:13 PM CET
+EESchema Schematic File Version 2  date Mon 02 Jan 2012 11:27:18 PM CET
 LIBS:power
 LIBS:device
 LIBS:transistors
@@ -40,13 +40,14 @@ LIBS:cs4344
 LIBS:double_sch_kcom
 LIBS:usb_minib
 LIBS:mic23250
+LIBS:sd2snes-cache
 EELAYER 25  0
 EELAYER END
 $Descr A4 11700 8267
 encoding utf-8
 Sheet 1 6
 Title "sd2snes Mark II"
-Date "26 dec 2011"
+Date "2 jan 2012"
 Rev "E2"
 Comp "Maximilian Rehkopf"
 Comment1 ""
--- a/pcb/kicad/RevE2/snesslot.sch
+++ b/pcb/kicad/RevE2/snesslot.sch
@@ -1,4 +1,4 @@
-EESchema Schematic File Version 2  date Mon 26 Dec 2011 09:56:13 PM CET
+EESchema Schematic File Version 2  date Mon 02 Jan 2012 11:27:18 PM CET
 LIBS:power
 LIBS:device
 LIBS:transistors
@@ -40,13 +40,14 @@ LIBS:cs4344
 LIBS:double_sch_kcom
 LIBS:usb_minib
 LIBS:mic23250
+LIBS:sd2snes-cache
 EELAYER 25  0
 EELAYER END
 $Descr A3 16535 11700
 encoding utf-8
 Sheet 2 6
 Title "sd2snes Mark II"
-Date "26 dec 2011"
+Date "2 jan 2012"
 Rev "E2"
 Comp "Maximilian Rehkopf"
 Comment1 ""
--- a/pcb/kicad/libs/sdcard.bak
+++ b/pcb/kicad/libs/sdcard.bak
@@ -1,7 +1,8 @@
-PCBNEW-LibModule-V1  Mon 26 Jul 2010 09:33:33 PM CEST
+PCBNEW-LibModule-V1  Tue 27 Dec 2011 01:25:51 AM CET
+# encoding utf-8
 $INDEX
-SD-RSMT-2-MQ-WF
 HRS-DM1AA
+SD-RSMT-2-MQ-WF
 $EndINDEX
 $MODULE SD-RSMT-2-MQ-WF
 Po 0 0 0 15 4C4D74E3 00000000 ~~
@@ -124,13 +125,13 @@ Po 3740 709
 $EndPAD
 $EndMODULE  SD-RSMT-2-MQ-WF
 $MODULE HRS-DM1AA
-Po 0 0 0 15 4C4DE307 00000000 ~~
+Po 0 0 0 15 4EF9108C 00000000 ~~
 Li HRS-DM1AA
 Sc 00000000
-AR 
+AR HRS-DM1AA
 Op 0 0 0
-T0 0 0 300 300 0 60 N V 21 N"HRS-DM1AA"
-T1 0 0 300 300 0 60 N V 21 N"VAL**"
+T0 0 0 300 300 0 60 N V 21 N "HRS-DM1AA"
+T1 0 0 300 300 0 60 N V 21 N "VAL**"
 DS 4134 -5984 5512 -5984 120 21
 DS 5512 6024 -5512 6024 120 21
 DS -5512 -5984 -4685 -5984 120 21
@@ -147,16 +148,16 @@ DS -5512 -5983 -5512 -3779 120 21
 DS -4686 -5983 -4686 -5511 120 21
 DS 4133 -5511 4133 -5983 120 21
 $PAD
-Sh "~" C 512 512 0 0 0
+Sh "~" C 510 510 0 0 0
 Dr 512 0 0
-At STD N 00E0FFFF
+At STD N 0000FFFF
 Ne 0 ""
 Po -4686 -4999
 $EndPAD
 $PAD
-Sh "~" C 512 512 0 0 0
+Sh "~" C 510 510 0 0 0
 Dr 512 0 0
-At STD N 00E0FFFF
+At STD N 0000FFFF
 Ne 0 ""
 Po 4133 -4999
 $EndPAD
--- a/pcb/kicad/libs/sdcard.mod
+++ b/pcb/kicad/libs/sdcard.mod
@@ -1,8 +1,8 @@
-PCBNEW-LibModule-V1  Tue 27 Dec 2011 01:25:51 AM CET
-# encoding utf-8
+PCBNEW-LibModule-V1  mar. 21 févr. 2012 14:42:34 CET
 $INDEX
 HRS-DM1AA
 SD-RSMT-2-MQ-WF
+SNESCART
 $EndINDEX
 $MODULE SD-RSMT-2-MQ-WF
 Po 0 0 0 15 4C4D74E3 00000000 ~~
@@ -148,14 +148,14 @@ DS -5512 -5983 -5512 -3779 120 21
 DS -4686 -5983 -4686 -5511 120 21
 DS 4133 -5511 4133 -5983 120 21
 $PAD
-Sh "~" C 510 510 0 0 0
+Sh "~" C 512 512 0 0 0
 Dr 512 0 0
 At STD N 0000FFFF
 Ne 0 ""
 Po -4686 -4999
 $EndPAD
 $PAD
-Sh "~" C 510 510 0 0 0
+Sh "~" C 512 512 0 0 0
 Dr 512 0 0
 At STD N 0000FFFF
 Ne 0 ""
@@ -274,4 +274,556 @@ Ne 0 ""
 Po -5552 3170
 $EndPAD
 $EndMODULE  HRS-DM1AA
+$MODULE SNESCART
+Po 0 0 0 15 4F439CD9 00000000 ~~
+Li SNESCART
+Sc 00000000
+AR /4B6E16F2/4B6E1766
+Op 0 0 0
+.SolderMask 4
+.SolderPaste -4
+T0 -4134 2953 600 600 0 120 N V 21 N"J101"
+T1 0 2953 600 600 0 120 N V 21 N"SNESCART_EXT"
+DS 18307 -8976 19606 -8976 40 28
+DS 19606 -8976 19606 -24409 40 28
+DS 19606 -24409 19439 -24409 40 28
+DS 19439 -24409 19291 -24409 40 28
+DS 17717 -2205 19587 -2205 40 28
+DS 19606 -2205 19606 -4094 40 28
+DS 19606 -4094 19498 -4094 40 28
+DS 19498 -4094 19291 -4094 40 28
+DS -19724 -12303 -19724 -12244 40 28
+DS -19724 -12244 -18465 -12244 40 28
+DS -18465 -12244 -18465 -12185 40 28
+DS -19724 -12244 -19724 -24409 40 28
+DS -19724 -24409 -19488 -24409 40 28
+DS -19488 -24409 -19488 -24488 40 28
+DS -19646 -8898 -19724 -8898 40 28
+DS -19724 -8898 -19724 -8819 40 28
+DS -19724 -8898 -19449 -8898 40 28
+DS -18465 -4803 -19724 -4803 40 28
+DS -19724 -4803 -19724 -8888 40 28
+DS -19720 -4805 -19725 -4805 40 28
+DS -19488 -27087 -19488 -24409 39 28
+DC 1142 -11378 1929 -11378 79 28
+DC 1142 -11378 1929 -11339 79 28
+DS 19291 -27087 19291 -24409 39 28
+DS 18307 -6890 19291 -6890 39 28
+DS 19291 -8189 19291 -6890 39 28
+DS 18307 -8189 19291 -8189 39 28
+DS 18307 -8976 18307 -8189 39 28
+DS -18465 -11457 -18465 -12244 39 28
+DS -19449 -11457 -18465 -11457 39 28
+DS -19449 -8898 -19449 -11457 39 28
+DA -17441 1693 -17441 1969 900 39 28
+DA -13071 1693 -12795 1693 900 39 28
+DA -11535 1693 -11535 1969 900 39 28
+DA 11535 1693 11811 1693 900 39 28
+DA 13071 1693 13071 1969 900 39 28
+DA 17441 1693 17717 1693 900 39 28
+DS 8622 -29331 19291 -29331 40 28
+DS -8524 -30709 8622 -30709 40 28
+DS -19488 -29331 -8524 -29331 40 28
+DC 2796 -17047 3583 -17047 75 28
+DC 2795 -17047 3582 -17047 75 28
+DS 8622 -29331 8622 -30709 40 28
+DS -8524 -30709 -8524 -29331 40 28
+DS -19488 -29331 -19488 -27756 40 28
+DS -19488 -27756 -18504 -27756 40 28
+DS -18504 -27756 -18504 -27087 40 28
+DS -18504 -27087 -19488 -27087 40 28
+DS -18465 -4803 -18465 -4016 40 28
+DS -18465 -4016 -19449 -4016 40 28
+DS -19449 -4016 -19449 -2205 40 28
+DS -19449 -2205 -17717 -2205 40 28
+DS -17717 -2205 -17717 -2165 40 28
+DS 19291 -27087 18307 -27087 40 28
+DS 18307 -27087 18307 -27756 40 28
+DS 18307 -27756 19291 -27756 40 28
+DS 19291 -27756 19291 -29331 40 28
+DS 17717 1693 17717 -2165 40 28
+DS 17717 -2165 17717 -2205 40 28
+DS 19291 -4094 19291 -6102 40 28
+DS 19291 -6102 18307 -6102 40 28
+DS 18307 -6102 18307 -6890 40 28
+DS 13071 1969 17441 1969 40 28
+DS 11811 1693 11811 -2480 40 28
+DS 11811 -2480 12795 -2480 40 28
+DS 12795 -2480 12795 1693 40 28
+DS -17717 1693 -17717 -2165 40 28
+DS -13071 1969 -17441 1969 40 28
+DS -11811 1693 -11811 -2480 40 28
+DS -11811 -2480 -12795 -2480 40 28
+DS -12795 -2480 -12795 1693 40 28
+DS -11535 1969 11535 1969 40 28
+$PAD
+Sh "1" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 50 "/SNES_Slot/SNES_EXT_SYS_CLK"
+Po -16732 197
+$EndPAD
+$PAD
+Sh "2" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 0 ""
+Po -15748 197
+$EndPAD
+$PAD
+Sh "3" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 47 "/SNES_Slot/SNES_EXT_PA6"
+Po -14764 197
+$EndPAD
+$PAD
+Sh "4" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 3 "/SNES_Slot/SNES_EXT_/PARD"
+Po -13780 197
+$EndPAD
+$PAD
+Sh "5" R 787 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 57 "GND"
+Po -10925 197
+$EndPAD
+$PAD
+Sh "6" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 11 "/SNES_Slot/SNES_EXT_A11"
+Po -9843 197
+$EndPAD
+$PAD
+Sh "7" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 10 "/SNES_Slot/SNES_EXT_A10"
+Po -8858 197
+$EndPAD
+$PAD
+Sh "8" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 31 "/SNES_Slot/SNES_EXT_A9"
+Po -7874 197
+$EndPAD
+$PAD
+Sh "9" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 30 "/SNES_Slot/SNES_EXT_A8"
+Po -6890 197
+$EndPAD
+$PAD
+Sh "10" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 29 "/SNES_Slot/SNES_EXT_A7"
+Po -5906 197
+$EndPAD
+$PAD
+Sh "11" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 28 "/SNES_Slot/SNES_EXT_A6"
+Po -4921 197
+$EndPAD
+$PAD
+Sh "12" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 27 "/SNES_Slot/SNES_EXT_A5"
+Po -3937 197
+$EndPAD
+$PAD
+Sh "13" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 26 "/SNES_Slot/SNES_EXT_A4"
+Po -2953 197
+$EndPAD
+$PAD
+Sh "14" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 25 "/SNES_Slot/SNES_EXT_A3"
+Po -1969 197
+$EndPAD
+$PAD
+Sh "15" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 20 "/SNES_Slot/SNES_EXT_A2"
+Po -984 197
+$EndPAD
+$PAD
+Sh "16" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 9 "/SNES_Slot/SNES_EXT_A1"
+Po 0 197
+$EndPAD
+$PAD
+Sh "17" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 8 "/SNES_Slot/SNES_EXT_A0"
+Po 984 197
+$EndPAD
+$PAD
+Sh "18" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 2 "/SNES_Slot/SNES_EXT_/IRQ"
+Po 1969 197
+$EndPAD
+$PAD
+Sh "19" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 33 "/SNES_Slot/SNES_EXT_D0"
+Po 2953 197
+$EndPAD
+$PAD
+Sh "20" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 34 "/SNES_Slot/SNES_EXT_D1"
+Po 3937 197
+$EndPAD
+$PAD
+Sh "21" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 35 "/SNES_Slot/SNES_EXT_D2"
+Po 4921 197
+$EndPAD
+$PAD
+Sh "22" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 36 "/SNES_Slot/SNES_EXT_D3"
+Po 5906 197
+$EndPAD
+$PAD
+Sh "23" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 5 "/SNES_Slot/SNES_EXT_/RD"
+Po 6890 197
+$EndPAD
+$PAD
+Sh "24" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 56 "EXT_CIC_DATA1"
+Po 7874 197
+$EndPAD
+$PAD
+Sh "25" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 54 "CIC_RESET"
+Po 8858 197
+$EndPAD
+$PAD
+Sh "26" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 58 "SNES_/RESET"
+Po 9843 197
+$EndPAD
+$PAD
+Sh "27" R 787 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 1 "+5VL"
+Po 10925 197
+$EndPAD
+$PAD
+Sh "28" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 41 "/SNES_Slot/SNES_EXT_PA0"
+Po 13780 197
+$EndPAD
+$PAD
+Sh "29" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 43 "/SNES_Slot/SNES_EXT_PA2"
+Po 14764 197
+$EndPAD
+$PAD
+Sh "30" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 45 "/SNES_Slot/SNES_EXT_PA4"
+Po 15748 197
+$EndPAD
+$PAD
+Sh "31" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00008000
+Ne 51 "AUDIO_L"
+Po 16732 197
+$EndPAD
+$PAD
+Sh "32" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 0 ""
+Po -16732 197
+$EndPAD
+$PAD
+Sh "33" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 49 "/SNES_Slot/SNES_EXT_REFRESH"
+Po -15748 197
+$EndPAD
+$PAD
+Sh "34" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 48 "/SNES_Slot/SNES_EXT_PA7"
+Po -14764 197
+$EndPAD
+$PAD
+Sh "35" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 4 "/SNES_Slot/SNES_EXT_/PAWR"
+Po -13780 197
+$EndPAD
+$PAD
+Sh "36" R 787 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 57 "GND"
+Po -10925 197
+$EndPAD
+$PAD
+Sh "37" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 12 "/SNES_Slot/SNES_EXT_A12"
+Po -9843 197
+$EndPAD
+$PAD
+Sh "38" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 13 "/SNES_Slot/SNES_EXT_A13"
+Po -8858 197
+$EndPAD
+$PAD
+Sh "39" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 14 "/SNES_Slot/SNES_EXT_A14"
+Po -7874 197
+$EndPAD
+$PAD
+Sh "40" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 15 "/SNES_Slot/SNES_EXT_A15"
+Po -6890 197
+$EndPAD
+$PAD
+Sh "41" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 16 "/SNES_Slot/SNES_EXT_A16"
+Po -5906 197
+$EndPAD
+$PAD
+Sh "42" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 17 "/SNES_Slot/SNES_EXT_A17"
+Po -4921 197
+$EndPAD
+$PAD
+Sh "43" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 18 "/SNES_Slot/SNES_EXT_A18"
+Po -3937 197
+$EndPAD
+$PAD
+Sh "44" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 19 "/SNES_Slot/SNES_EXT_A19"
+Po -2953 197
+$EndPAD
+$PAD
+Sh "45" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 21 "/SNES_Slot/SNES_EXT_A20"
+Po -1969 197
+$EndPAD
+$PAD
+Sh "46" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 22 "/SNES_Slot/SNES_EXT_A21"
+Po -984 197
+$EndPAD
+$PAD
+Sh "47" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 23 "/SNES_Slot/SNES_EXT_A22"
+Po 0 197
+$EndPAD
+$PAD
+Sh "48" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 24 "/SNES_Slot/SNES_EXT_A23"
+Po 984 197
+$EndPAD
+$PAD
+Sh "49" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 6 "/SNES_Slot/SNES_EXT_/ROMSEL"
+Po 1969 197
+$EndPAD
+$PAD
+Sh "50" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 37 "/SNES_Slot/SNES_EXT_D4"
+Po 2953 197
+$EndPAD
+$PAD
+Sh "51" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 38 "/SNES_Slot/SNES_EXT_D5"
+Po 3937 197
+$EndPAD
+$PAD
+Sh "52" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 39 "/SNES_Slot/SNES_EXT_D6"
+Po 4921 197
+$EndPAD
+$PAD
+Sh "53" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 40 "/SNES_Slot/SNES_EXT_D7"
+Po 5906 197
+$EndPAD
+$PAD
+Sh "54" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 7 "/SNES_Slot/SNES_EXT_/WR"
+Po 6890 197
+$EndPAD
+$PAD
+Sh "55" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 55 "EXT_CIC_DATA0"
+Po 7874 197
+$EndPAD
+$PAD
+Sh "56" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 53 "CIC_CLK"
+Po 8858 197
+$EndPAD
+$PAD
+Sh "57" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 32 "/SNES_Slot/SNES_EXT_CPU_CLK"
+Po 9843 197
+$EndPAD
+$PAD
+Sh "58" R 787 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 1 "+5VL"
+Po 10925 197
+$EndPAD
+$PAD
+Sh "59" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 42 "/SNES_Slot/SNES_EXT_PA1"
+Po 13780 197
+$EndPAD
+$PAD
+Sh "60" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 44 "/SNES_Slot/SNES_EXT_PA3"
+Po 14764 197
+$EndPAD
+$PAD
+Sh "61" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 46 "/SNES_Slot/SNES_EXT_PA5"
+Po 15748 197
+$EndPAD
+$PAD
+Sh "62" R 591 2756 0 0 0
+Dr 0 0 0
+At CONN N 00000001
+Ne 52 "AUDIO_R"
+Po 16732 197
+$EndPAD
+$PAD
+Sh "" R 4921 3150 0 0 0
+Dr 0 0 0
+At CONN N 00C00000
+Ne 0 ""
+Po -15256 394
+$EndPAD
+$PAD
+Sh "" R 4921 3150 0 0 0
+Dr 0 0 0
+At CONN N 00C00000
+Ne 0 ""
+Po 15256 394
+$EndPAD
+$PAD
+Sh "" R 23622 3150 0 0 0
+Dr 0 0 0
+At CONN N 00C00000
+Ne 0 ""
+Po 0 394
+$EndPAD
+$PAD
+Sh "" R 2362 1969 0 0 0
+Dr 0 0 0
+At CONN N 00400000
+Ne 0 ""
+Po -10945 -3819
+$EndPAD
+$PAD
+Sh "" R 2283 2362 0 0 0
+Dr 0 0 0
+At CONN N 00400000
+Ne 0 ""
+Po 14331 -3780
+$EndPAD
+$EndMODULE  SNESCART
 $EndLIBRARY
--- a/pcb/kicad/sd2snes.pro
+++ b/pcb/kicad/sd2snes.pro
@@ -1,4 +1,4 @@
-update=Sat 28 Aug 2010 02:32:58 PM CEST
+update=mar. 21 févr. 2012 14:37:01 CET
 version=1
 last_client=pcbnew
 [general]
@@ -85,24 +85,24 @@ LibName40=libs/usb_minib
 LibName41=libs/mic23250
 [pcbnew]
 version=1
-PadDrlX=433
+PadDrlX=512
 PadDimH=512
 PadDimV=512
-BoardThickness=500
+BoardThickness=630
 SgPcb45=1
-TxtPcbV=300
-TxtPcbH=300
-TxtModV=300
-TxtModH=300
-TxtModW=60
+TxtPcbV=800
+TxtPcbH=600
+TxtModV=600
+TxtModH=600
+TxtModW=120
 VEgarde=40
-DrawLar=59
-EdgeLar=150
-TxtLar=60
-MSegLar=120
+DrawLar=70
+EdgeLar=40
+TxtLar=120
+MSegLar=40
 LastNetListRead=sd2snes.net
 [pcbnew/libraries]
-LibDir=
+LibDir=../../kicad
 LibName1=sockets
 LibName2=connect
 LibName3=discret
@@ -113,8 +113,8 @@ LibName7=display
 LibName8=valves
 LibName9=led
 LibName10=dip_sockets
-LibName11=libs/snescart
-LibName12=libs/mypackages
+LibName11=libs/mypackages
+LibName12=libs/snescart
 LibName13=libs/sdcard
-LibName14=libs/diy_capacitors
-LibName15=snail
+LibName14=libs/snail
+LibName15=J101
--- a/src/sdnative.c
+++ b/src/sdnative.c
@@ -777,6 +777,7 @@ void send_datablock(uint8_t *buf) {
 }

 void read_block(uint32_t address, uint8_t *buf) {
+  DBG_SD printf("read_block addr=%08lx last_addr=%08lx  offld=%d/%d offst=%04x offed=%04x last_off=%04x\n", address, last_block, sd_offload, sd_offload_partial, sd_offload_partial_start, sd_offload_partial_end, last_offset);
  if(during_blocktrans == TRANS_READ && (last_block == address-1)) {
 //uart_putc('r');
 #ifdef CONFIG_SD_DATACRC
--- a/verilog/sd2snes/sd2snes.xise
+++ b/verilog/sd2snes/sd2snes.xise
@@ -16,55 +16,55 @@

  <files>
    <file xil_pn:name="address.v" xil_pn:type="FILE_VERILOG">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="17"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="17"/>
    </file>
    <file xil_pn:name="bsx.v" xil_pn:type="FILE_VERILOG">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="16"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="16"/>
    </file>
    <file xil_pn:name="clk_test.v" xil_pn:type="FILE_VERILOG">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="6"/>
    </file>
    <file xil_pn:name="dac.v" xil_pn:type="FILE_VERILOG">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="15"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="15"/>
    </file>
    <file xil_pn:name="dcm.v" xil_pn:type="FILE_VERILOG">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="14"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="14"/>
    </file>
    <file xil_pn:name="main.v" xil_pn:type="FILE_VERILOG">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="18"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="18"/>
    </file>
    <file xil_pn:name="mcu_cmd.v" xil_pn:type="FILE_VERILOG">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="13"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="13"/>
    </file>
    <file xil_pn:name="msu.v" xil_pn:type="FILE_VERILOG">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="12"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="12"/>
    </file>
    <file xil_pn:name="rtc.v" xil_pn:type="FILE_VERILOG">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="11"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="11"/>
    </file>
    <file xil_pn:name="sd_dma.v" xil_pn:type="FILE_VERILOG">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="10"/>
    </file>
    <file xil_pn:name="spi.v" xil_pn:type="FILE_VERILOG">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="9"/>
    </file>
    <file xil_pn:name="srtc.v" xil_pn:type="FILE_VERILOG">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="8"/>
    </file>
    <file xil_pn:name="upd77c25.v" xil_pn:type="FILE_VERILOG">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="7"/>
    </file>
    <file xil_pn:name="main.ucf" xil_pn:type="FILE_UCF">
@@ -90,11 +90,11 @@
      <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
    </file>
    <file xil_pn:name="ipcore_dir/dac_buf.xco" xil_pn:type="FILE_COREGEN">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="5"/>
    </file>
    <file xil_pn:name="ipcore_dir/msu_databuf.xco" xil_pn:type="FILE_COREGEN">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="4"/>
    </file>
    <file xil_pn:name="ipcore_dir/upd77c25_datram.xise" xil_pn:type="FILE_COREGENISE">
@@ -349,8 +349,8 @@
    <property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
    <property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
-    <property xil_pn:name="Selected Module Instance Name" xil_pn:value="/main" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.main" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Selected Module Instance Name" xil_pn:value="/main/snes_dspx" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.upd77c25" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="work.updtest" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="work.updtest" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="work.updtest" xil_pn:valueState="non-default"/>
@@ -372,13 +372,13 @@
    <property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Specify Search Directories for 'Include" xil_pn:value="../sd2snes" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Specify Top Level Instance Names" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.main" xil_pn:valueState="default"/>
+    <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.upd77c25" xil_pn:valueState="default"/>
    <property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="work.updtest" xil_pn:valueState="default"/>
    <property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="work.updtest" xil_pn:valueState="default"/>
    <property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="work.updtest" xil_pn:valueState="default"/>
    <property xil_pn:name="Speed Grade" xil_pn:value="-4" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="1" xil_pn:valueState="default"/>
-    <property xil_pn:name="Starting Placer Cost Table (1-100) Par" xil_pn:value="1" xil_pn:valueState="default"/>
+    <property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="2" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Starting Placer Cost Table (1-100) Par" xil_pn:value="2" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Structure window" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
    <property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
@@ -416,7 +416,7 @@
    <property xil_pn:name="Use Synchronous Reset" xil_pn:value="Yes" xil_pn:valueState="default"/>
    <property xil_pn:name="Use Synchronous Set" xil_pn:value="Yes" xil_pn:valueState="default"/>
    <property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="User Browsed Strategy Files" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="User Browsed Strategy Files" xil_pn:value="/mnt/store/bin/Xilinx/13.2/ISE_DS/ISE/data/default.xds" xil_pn:valueState="non-default"/>
    <property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
    <property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
    <property xil_pn:name="VHDL Syntax" xil_pn:value="93" xil_pn:valueState="default"/>
@@ -433,7 +433,7 @@
    <!--                                                                                  -->
    <!-- The following properties are for internal use only. These should not be modified.-->
    <!--                                                                                  -->
-    <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Module|main" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Module|upd77c25" xil_pn:valueState="non-default"/>
    <property xil_pn:name="PROP_DesignName" xil_pn:value="sd2snes" xil_pn:valueState="non-default"/>
    <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3" xil_pn:valueState="default"/>
    <property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
--- a/verilog/sd2snes_cx4/ipcore_dir/cx4_mul.xise
+++ b/verilog/sd2snes_cx4/ipcore_dir/cx4_mul.xise
@@ -29,333 +29,27 @@
  </files>

  <properties>
-    <property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
-    <property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Bus Delimiter" xil_pn:value="&lt;>" xil_pn:valueState="default"/>
-    <property xil_pn:name="CLB Pack Factor Percentage" xil_pn:value="100" xil_pn:valueState="default"/>
-    <property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
-    <property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
-    <property xil_pn:name="Change Device Speed To" xil_pn:value="-4" xil_pn:valueState="default"/>
-    <property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-4" xil_pn:valueState="default"/>
-    <property xil_pn:name="Clock Enable" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Collapsing Input Limit (4-40)" xil_pn:value="32" xil_pn:valueState="default"/>
-    <property xil_pn:name="Collapsing Pterm Limit (3-56)" xil_pn:value="28" xil_pn:valueState="default"/>
-    <property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Compile CPLD Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Compile uni9000 (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Configuration Clk (Configuration Pins)" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="Configuration Pin HSWAPEN" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="Configuration Pin M0" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="Configuration Pin M1" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="Configuration Pin M2" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="Configuration Rate" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create IEEE 1532 Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="DCI Update Mode" xil_pn:value="As Required" xil_pn:valueState="default"/>
-    <property xil_pn:name="Decoder Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Default Powerup Value of Registers" xil_pn:value="Low" xil_pn:valueState="default"/>
-    <property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
    <property xil_pn:name="Device" xil_pn:value="xc3s400" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Device Family" xil_pn:value="Spartan3" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-4" xil_pn:valueState="default"/>
-    <property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable Cyclic Redundancy Checking (CRC)" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Evaluation Development Board" xil_pn:value="None Specified" xil_pn:valueState="default"/>
-    <property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Exhaustive Fit Mode" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Extra Effort" xil_pn:value="None" xil_pn:valueState="default"/>
-    <property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/>
-    <property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
-    <property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
-    <property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Function Block Input Limit (4-40)" xil_pn:value="38" xil_pn:valueState="default"/>
-    <property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="Verilog" xil_pn:valueState="default"/>
-    <property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="Verilog" xil_pn:valueState="default"/>
-    <property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="Verilog" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Clock Region Report" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Post-Fit Power Data" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Post-Fit Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Post-Place &amp; Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Post-Place &amp; Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
-    <property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
-    <property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
-    <property xil_pn:name="HDL Equations Style" xil_pn:value="Source" xil_pn:valueState="default"/>
-    <property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
-    <property xil_pn:name="I/O Voltage Standard" xil_pn:value="LVCMOS18" xil_pn:valueState="default"/>
-    <property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
-    <property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Implementation Stop View" xil_pn:value="Structural" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Template" xil_pn:value="Optimize Density" xil_pn:valueState="default"/>
+    <property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Implementation Top" xil_pn:value="Module|cx4_mul" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Implementation Top File" xil_pn:value="cx4_mul.ngc" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/cx4_mul" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Input and tristate I/O Termination Mode" xil_pn:value="Keeper" xil_pn:valueState="default"/>
-    <property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="Verilog" xil_pn:valueState="default"/>
-    <property xil_pn:name="JTAG Pin TCK" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
-    <property xil_pn:name="Keep Hierarchy CPLD" xil_pn:value="Yes" xil_pn:valueState="default"/>
-    <property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
-    <property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Logic Optimization" xil_pn:value="Density" xil_pn:valueState="default"/>
-    <property xil_pn:name="Logical Shifter Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Macro Preserve" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Map Effort Level" xil_pn:value="High" xil_pn:valueState="default"/>
-    <property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Max Fanout" xil_pn:value="500" xil_pn:valueState="default"/>
-    <property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
-    <property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
-    <property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Multiplier Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="Mux Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
-    <property xil_pn:name="Mux Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
-    <property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/>
-    <property xil_pn:name="Number of Clock Buffers" xil_pn:value="8" xil_pn:valueState="default"/>
-    <property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
-    <property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
-    <property xil_pn:name="Optimization Effort" xil_pn:value="Normal" xil_pn:valueState="default"/>
-    <property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
-    <property xil_pn:name="Optimization Strategy (Cover Mode)" xil_pn:value="Area" xil_pn:valueState="default"/>
-    <property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Bitgen Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other CPLD Fitter Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Compiler Options Fit" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Place &amp; Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Programming Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Simulator Commands Fit" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Timing Report Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Output File Name" xil_pn:value="cx4_mul" xil_pn:valueState="default"/>
-    <property xil_pn:name="Output Slew Rate" xil_pn:value="Fast" xil_pn:valueState="default"/>
-    <property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
    <property xil_pn:name="Package" xil_pn:value="pq208" xil_pn:valueState="default"/>
-    <property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Place &amp; Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
-    <property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
-    <property xil_pn:name="Placer Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/>
-    <property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="cx4_mul_map.v" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="cx4_mul_timesim.v" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="cx4_mul_synthesis.v" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="cx4_mul_translate.v" xil_pn:valueState="default"/>
-    <property xil_pn:name="Power Reduction Map" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
-    <property xil_pn:name="Preserve Unused Inputs" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Priority Encoder Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
-    <property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
-    <property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
-    <property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
-    <property xil_pn:name="Register Duplication" xil_pn:value="Off" xil_pn:valueState="default"/>
-    <property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
-    <property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
-    <property xil_pn:name="Rename Top Level Entity to" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Reset DCM if SHUTDOWN &amp; AGHIGH performed" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
-    <property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Router Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/>
-    <property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
-    <property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
-    <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
-    <property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Simulation Model Target" xil_pn:value="Verilog" xil_pn:valueState="default"/>
-    <property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
-    <property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
-    <property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
-    <property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
    <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Slice Packing" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
-    <property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/>
-    <property xil_pn:name="Specify Top Level Instance Names Fit" xil_pn:value="Default" xil_pn:valueState="default"/>
-    <property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
-    <property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
-    <property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
    <property xil_pn:name="Speed Grade" xil_pn:value="-4" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="1" xil_pn:valueState="default"/>
-    <property xil_pn:name="Starting Placer Cost Table (1-100) Par" xil_pn:value="1" xil_pn:valueState="default"/>
    <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
-    <property xil_pn:name="Timing Mode Map" xil_pn:value="Non Timing Driven" xil_pn:valueState="default"/>
-    <property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
-    <property xil_pn:name="Timing Report Format" xil_pn:value="Summary" xil_pn:valueState="default"/>
-    <property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
-    <property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
-    <property xil_pn:name="Unused I/O Pad Termination Mode" xil_pn:value="Keeper" xil_pn:valueState="default"/>
-    <property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Clock Enable" xil_pn:value="Yes" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Project File Fit" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Waveform Configuration File Fit" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Data Gate" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Direct Input for Input Registers" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Global Clocks" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Global Output Enables" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Global Set/Reset" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Location Constraints" xil_pn:value="Always" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Multi-level Logic Optimization" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Synchronous Reset" xil_pn:value="Yes" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Synchronous Set" xil_pn:value="Yes" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Timing Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
-    <property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
-    <property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="WYSIWYG" xil_pn:value="None" xil_pn:valueState="default"/>
-    <property xil_pn:name="Wait for DCI Match (Output Events) virtex2" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="Wait for DLL Lock (Output Events)" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="default"/>
-    <property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="XOR Collapsing" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="XOR Preserve" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
    <!--                                                                                  -->
    <!-- The following properties are for internal use only. These should not be modified.-->
    <!--                                                                                  -->
-    <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="PROP_DesignName" xil_pn:value="cx4_mul" xil_pn:valueState="non-default"/>
    <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_PostFitSimTop" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
    <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2011-10-30T21:22:43" xil_pn:valueState="non-default"/>
    <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="7C4ED2F86A69C26BC7F2AA5B611C709F" xil_pn:valueState="non-default"/>
    <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
--- a/verilog/sd2snes_cx4/main.ucf
+++ b/verilog/sd2snes_cx4/main.ucf
@@ -4,8 +4,6 @@ TIMESPEC TS_CLKIN = PERIOD "CLKIN" 24 MHz HIGH 50 %;
 NET "p113_out" IOSTANDARD = LVCMOS33;
 NET "p113_out" LOC = P113;

-NET "SNES_SYSCLK" LOC = P180;
-NET "SNES_SYSCLK" IOSTANDARD = LVCMOS33;
 NET "SNES_SYSCLK" TNM_NET = "SNES_SYSCLK";
 TIMESPEC TS_SNES_SYSCLK = PERIOD "SNES_SYSCLK" 21.5 MHz HIGH 50 %;

--- a/verilog/sd2snes_cx4/sd2snes_cx4.xise
+++ b/verilog/sd2snes_cx4/sd2snes_cx4.xise
@@ -284,7 +284,7 @@
    <property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="No" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="For Inputs and Outputs" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Package" xil_pn:value="pq208" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Package" xil_pn:value="pq208" xil_pn:valueState="default"/>
    <property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="true" xil_pn:valueState="non-default"/>
@@ -366,8 +366,8 @@
    <property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="work.updtest" xil_pn:valueState="default"/>
    <property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="work.updtest" xil_pn:valueState="default"/>
    <property xil_pn:name="Speed Grade" xil_pn:value="-4" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="5" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Starting Placer Cost Table (1-100) Par" xil_pn:value="5" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="4" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Starting Placer Cost Table (1-100) Par" xil_pn:value="4" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Structure window" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
    <property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
Author	SHA1	Message	Date
Godzil	5920534f61	Apply my changes for seeed build	2012-03-05 11:53:09 +01:00
ikari	8c0ca0ea05	PCB: update Rev.E assembly diagrams	2012-01-14 23:35:14 +01:00
ikari	f0a2e85c65	FPGA: updated project files	2012-01-14 23:16:57 +01:00
ikari	86a81bfa82	PCB: Rev.E2 WIP	2012-01-14 23:13:38 +01:00
ikari	cb859f3bfb	Firmware: add SD debugging message	2012-01-14 23:12:45 +01:00