Maximilian Rehkopf 39b07df47e Correct LoROM SRAM mapping for smaller ROMs ...

SRAM is sometimes mapped not just to 70:0000-7fff but also to
70:8000-ffff if ROM size permits it (i.e. the ROM is small enough
to avoid overlap).
Map SRAM to 8000-ffff if the ROM mask denotes a ROM <= 16 MBits.

2013-06-30 23:42:28 +02:00

..

ipcore_dir

FPGA: update project files (ISE 13.2)

2011-10-07 22:10:02 +02:00

address.v

Correct LoROM SRAM mapping for smaller ROMs

2013-06-30 23:42:28 +02:00

bsx.v

FPGA: more accurate BS-X memory map

2012-09-24 22:49:54 +02:00

clk_test.v

FPGA: update clock speed to 88MHz

2012-07-09 01:54:05 +02:00

dac.v

FPGA: Adjust DAC I²S signal timing

2012-07-09 01:41:47 +02:00

dcm.v

FPGA: rework shared memory access

2011-10-07 22:06:43 +02:00

main_tf.v

FPGA: add test fixtures

2011-06-11 23:57:06 +02:00

main.ucf

FPGA: update clock speed to 88MHz

2012-07-09 01:54:05 +02:00

main.v

FPGA: slow down bus timing

2012-11-07 22:32:33 +01:00

mcu_cmd.v

FPGA/SPI: detect end of byte via MSB toggle instead of constant compare of async input

2012-07-09 02:17:01 +02:00

msu.v

FPGA: implement MSU1 "audio error" status bit

2012-07-09 02:20:13 +02:00

rtc.v

FPGA: update clock speed to 88MHz

2012-07-09 01:54:05 +02:00

sd2snes.xise

FPGA: adjust menu memory mapping to make more room for file database

2012-06-10 20:07:45 +02:00

sd_dma.v

FPGA/SDDMA: fix clock glitch, adjust RAM write timings

2012-07-09 02:22:07 +02:00

spi.v

FPGA/SPI: detect end of byte via MSB toggle instead of constant compare of async input

2012-07-09 02:17:01 +02:00

srtc.v

FPGA/SRTC: buffer register/address input

2012-07-09 02:22:57 +02:00

upd77c25.v

FPGA/DSPx: buffer register input

2012-07-09 02:23:57 +02:00

updtest_tf.v

FPGA: fix ST0010 glitches

2011-06-23 00:55:29 +02:00