Maximilian Rehkopf effa2a6972 FPGA/SDDMA: fix clock glitch, adjust RAM write timings

2012-07-09 02:22:07 +02:00

..

ipcore_dir

FPGA: updated project files

2012-01-14 23:16:57 +01:00

address.v

FPGA: simple SNES address input filtering

2012-07-09 01:37:57 +02:00

cx4.v

FPGA: Adjust Cx4 timing to new master clock rate

2012-07-09 02:13:44 +02:00

dac.v

FPGA: Adjust DAC I²S signal timing

2012-07-09 01:41:47 +02:00

dcm.v

FPGA/cx4: initial commit

2011-10-23 04:10:55 +02:00

main.ucf

FPGA: simple SNES address input filtering

2012-07-09 01:37:57 +02:00

main.v

FPGA: Use internal clock instead of SNES master clock for $213F RMW timing

2012-07-09 02:18:28 +02:00

msu.v

FPGA: implement MSU1 "audio error" status bit

2012-07-09 02:20:13 +02:00

sd2snes_cx4.xise

FPGA/cx4: adjust Cx4 CPU timing

2012-05-19 18:07:13 +02:00

sd_dma.v

FPGA/SDDMA: fix clock glitch, adjust RAM write timings

2012-07-09 02:22:07 +02:00

spi.v

FPGA/SPI: detect end of byte via MSB toggle instead of constant compare of async input

2012-07-09 02:17:01 +02:00