Maximilian Rehkopf 9fbe61bad1 FPGA: Use internal clock instead of SNES master clock for $213F RMW timing

2012-07-09 02:18:28 +02:00

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sd2snes

FPGA: Use internal clock instead of SNES master clock for $213F RMW timing

2012-07-09 02:18:28 +02:00

sd2snes_cx4

FPGA: Use internal clock instead of SNES master clock for $213F RMW timing

2012-07-09 02:18:28 +02:00

sd2snes_test

FPGA: add SD clock pullup to test configuration

2012-05-02 10:46:27 +02:00

sd2sneslite

FPGA/SPI: detect end of byte via MSB toggle instead of constant compare of async input

2012-07-09 02:17:01 +02:00