Downclock all design to 50 Mhz

vhdl/SDRAM_Controller.vhd

@@ -343,7 +343,7 @@ main_proc: process(clk)
                   -- Start the refresh cycle. 
                   -- This tasks tRFC (66ns), so 6 idle cycles are needed @ 100MHz
                   ------------------------------------------------------------------------
-                  state       <= s_idle_in_6;
+                  state       <= s_idle_in_3;
                   iob_command <= CMD_REFRESH;
                   startup_refresh_count <= startup_refresh_count - cycles_per_refresh+1;
                elsif got_transaction = '1' then
@@ -351,7 +351,7 @@ main_proc: process(clk)
                   -- Start the read or write cycle. 
                   -- First task is to open the row
                   --------------------------------
-                  state       <= s_open_in_2;
+                  state       <= s_open_in_1;
                   iob_command <= CMD_ACTIVE;
                   iob_address <= save_row;
                   iob_bank    <= save_bank;

vhdl/pll.vhd

@@ -158,11 +158,11 @@ BEGIN
 		bandwidth_type => "AUTO",
 		clk0_divide_by => 1,
 		clk0_duty_cycle => 50,
-		clk0_multiply_by => 2,
+		clk0_multiply_by => 1,
-		clk0_phase_shift => "-1500",
+		clk0_phase_shift => "-3000",
 		clk1_divide_by => 1,
 		clk1_duty_cycle => 50,
-		clk1_multiply_by => 2,
+		clk1_multiply_by => 1,
 		clk1_phase_shift => "0",
 		clk2_divide_by => 1,
 		clk2_duty_cycle => 50,

vhdl/top_level.vhd

@@ -61,7 +61,7 @@ entity top_level is
 end top_level;
 
 architecture Behavioral of top_level is
-    constant clk_freq_mhz        : natural := 100; -- this is the frequency which the PLL outputs, in MHz.
+    constant clk_freq_mhz        : natural := 50; -- this is the frequency which the PLL outputs, in MHz.
 
     -- SDRAM configuration
     constant sdram_address_width : natural := 24;