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https://github.com/revyos/thead-kernel.git
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toolchains: fix mainline toolchain build
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
This commit is contained in:
@@ -50,10 +50,15 @@ endif
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# ISA string setting
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riscv-march-$(CONFIG_ARCH_RV32I) := rv32ima
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riscv-march-$(CONFIG_ARCH_RV64I) := rv64ima
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riscv-march-$(CONFIG_FPU) := $(riscv-march-y)fd
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riscv-march-$(CONFIG_FPU) := $(riscv-march-y)fd
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riscv-march-$(CONFIG_RISCV_ISA_C) := $(riscv-march-y)c
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riscv-march-$(CONFIG_VECTOR) := $(riscv-march-y)v0p7
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riscv-march-$(CONFIG_THEAD_ISA) := $(riscv-march-y)_xtheadc
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# Fix mainline build
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toolchain-have-v0p7 := $(call cc-option-yn, -march=$(riscv-march-y)v0p7)
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riscv-march-$(toolchain-have-v0p7) := $(riscv-march-y)v0p7
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toolchain-have-xtheadc := $(call cc-option-yn, -march=$(riscv-march-y)_xtheadc)
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riscv-march-$(toolchain-have-xtheadc) := $(riscv-march-y)_xtheadc
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# Newer binutils versions default to ISA spec version 20191213 which moves some
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# instructions from the I extension to the Zicsr and Zifencei extensions.
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