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feat: update gpu to Linux_SDK_V1.2.1

Browse Source 
This version update involves a lot of content, so the previous version
has been deleted and the new version has been re-merged into the kernel.

The configuration file for the GPU driver originates from a previous
version.

Signed-off-by: Mingzheng Xing <xingmingzheng@iscas.ac.cn>
This commit is contained in:
Mingzheng Xing
2023-08-30 21:19:50 +08:00
committed by Han Gao
parent 807db9d981
commit f72e7cd077
250 changed files with 10635 additions and 7697 deletions
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34
drivers/gpu/drm/img-rogue/include/rogue/rgx_fwif_hwperf.h
View File

@@ -68,6 +68,20 @@ typedef struct
IMG_UINT32 aui32SelectedCountersIDs[RGX_HWPERF_MAX_CUSTOM_CNTRS];
} RGXFW_HWPERF_SELECT;
/* Structure used to hold a Direct-Addressable block's parameters for passing
* between the BG context and the IRQ context when applying a configuration
* request. RGX_FEATURE_HWPERF_OCEANIC use only.
*/
typedef struct
{
IMG_UINT32 uiEnabled;
IMG_UINT32 uiNumCounters;
IMG_UINT32 eBlockID;
RGXFWIF_DEV_VIRTADDR psModel;
IMG_UINT32 aui32Counters[RGX_CNTBLK_COUNTERS_MAX];
} RGXFWIF_HWPERF_DA_BLK;
/* Structure to hold the whole configuration request details for all blocks
* The block masks and counts are used to optimise reading of this data. */
typedef struct
@@ -77,8 +91,8 @@ typedef struct
IMG_UINT32 ui32SelectedCountersBlockMask;
RGXFW_HWPERF_SELECT RGXFW_ALIGN SelCntr[RGX_HWPERF_MAX_CUSTOM_BLKS];
IMG_UINT32 ui32EnabledBlksCount;
RGXFWIF_HWPERF_CTL_BLK RGXFW_ALIGN sBlkCfg[RGX_HWPERF_MAX_DEFINED_BLKS];
IMG_UINT32 ui32EnabledMUXBlksCount;
RGXFWIF_HWPERF_CTL_BLK RGXFW_ALIGN sBlkCfg[RGX_HWPERF_MAX_MUX_BLKS];
} UNCACHED_ALIGN RGXFWIF_HWPERF_CTL;
/* NOTE: The switch statement in this function must be kept in alignment with
@@ -90,7 +104,7 @@ typedef struct
#ifdef INLINE_IS_PRAGMA
#pragma inline(rgxfw_hwperf_get_block_ctl)
#endif
static INLINE RGXFWIF_HWPERF_CTL_BLK* rgxfw_hwperf_get_block_ctl(
static INLINE RGXFWIF_HWPERF_CTL_BLK *rgxfw_hwperf_get_block_ctl(
RGX_HWPERF_CNTBLK_ID eBlockID, RGXFWIF_HWPERF_CTL *psHWPerfInitData)
{
IMG_UINT32 ui32Idx;
@@ -221,4 +235,18 @@ static INLINE RGXFWIF_HWPERF_CTL_BLK* rgxfw_hwperf_get_block_ctl(
return &psHWPerfInitData->sBlkCfg[ui32Idx];
}
/* Stub routine for rgxfw_hwperf_get_da_block_ctl() for non
* RGX_FEATURE_HWPERF_OCEANIC systems. Just return a NULL.
*/
#ifdef INLINE_IS_PRAGMA
#pragma inline(rgxfw_hwperf_get_da_block_ctl)
#endif
static INLINE RGXFWIF_HWPERF_DA_BLK* rgxfw_hwperf_get_da_block_ctl(
RGX_HWPERF_CNTBLK_ID eBlockID, RGXFWIF_HWPERF_CTL *psHWPerfInitData)
{
PVR_UNREFERENCED_PARAMETER(eBlockID);
PVR_UNREFERENCED_PARAMETER(psHWPerfInitData);
return NULL;
}
#endif

340
drivers/gpu/drm/img-rogue/include/rogue/rgx_fwif_km.h
View File

@@ -109,21 +109,21 @@ typedef struct {
#define RGXFWIF_LOG_ENABLED_GROUPS_LIST_PFSPEC "%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s"
/* Used in a print statement to display log group state, one per group */
#define RGXFWIF_LOG_ENABLED_GROUPS_LIST(types) (((types) & RGXFWIF_LOG_TYPE_GROUP_MAIN) ?("main ") :("")), \
(((types) & RGXFWIF_LOG_TYPE_GROUP_MTS) ?("mts ") :("")), \
(((types) & RGXFWIF_LOG_TYPE_GROUP_CLEANUP) ?("cleanup ") :("")), \
(((types) & RGXFWIF_LOG_TYPE_GROUP_CSW) ?("csw ") :("")), \
(((types) & RGXFWIF_LOG_TYPE_GROUP_BIF) ?("bif ") :("")), \
(((types) & RGXFWIF_LOG_TYPE_GROUP_PM) ?("pm ") :("")), \
(((types) & RGXFWIF_LOG_TYPE_GROUP_RTD) ?("rtd ") :("")), \
(((types) & RGXFWIF_LOG_TYPE_GROUP_SPM) ?("spm ") :("")), \
(((types) & RGXFWIF_LOG_TYPE_GROUP_POW) ?("pow ") :("")), \
(((types) & RGXFWIF_LOG_TYPE_GROUP_HWR) ?("hwr ") :("")), \
(((types) & RGXFWIF_LOG_TYPE_GROUP_HWP) ?("hwp ") :("")), \
(((types) & RGXFWIF_LOG_TYPE_GROUP_RPM) ?("rpm ") :("")), \
(((types) & RGXFWIF_LOG_TYPE_GROUP_DMA) ?("dma ") :("")), \
(((types) & RGXFWIF_LOG_TYPE_GROUP_MISC) ?("misc ") :("")), \
(((types) & RGXFWIF_LOG_TYPE_GROUP_DEBUG) ?("debug ") :(""))
#define RGXFWIF_LOG_ENABLED_GROUPS_LIST(types) ((((types) & RGXFWIF_LOG_TYPE_GROUP_MAIN) != 0U) ?("main ") :("")), \
((((types) & RGXFWIF_LOG_TYPE_GROUP_MTS) != 0U) ?("mts ") :("")), \
((((types) & RGXFWIF_LOG_TYPE_GROUP_CLEANUP) != 0U) ?("cleanup ") :("")), \
((((types) & RGXFWIF_LOG_TYPE_GROUP_CSW) != 0U) ?("csw ") :("")), \
((((types) & RGXFWIF_LOG_TYPE_GROUP_BIF) != 0U) ?("bif ") :("")), \
((((types) & RGXFWIF_LOG_TYPE_GROUP_PM) != 0U) ?("pm ") :("")), \
((((types) & RGXFWIF_LOG_TYPE_GROUP_RTD) != 0U) ?("rtd ") :("")), \
((((types) & RGXFWIF_LOG_TYPE_GROUP_SPM) != 0U) ?("spm ") :("")), \
((((types) & RGXFWIF_LOG_TYPE_GROUP_POW) != 0U) ?("pow ") :("")), \
((((types) & RGXFWIF_LOG_TYPE_GROUP_HWR) != 0U) ?("hwr ") :("")), \
((((types) & RGXFWIF_LOG_TYPE_GROUP_HWP) != 0U) ?("hwp ") :("")), \
((((types) & RGXFWIF_LOG_TYPE_GROUP_RPM) != 0U) ?("rpm ") :("")), \
((((types) & RGXFWIF_LOG_TYPE_GROUP_DMA) != 0U) ?("dma ") :("")), \
((((types) & RGXFWIF_LOG_TYPE_GROUP_MISC) != 0U) ?("misc ") :("")), \
((((types) & RGXFWIF_LOG_TYPE_GROUP_DEBUG) != 0U) ?("debug ") :(""))
/************************************************************************
@@ -156,20 +156,31 @@ typedef struct
IMG_UINT32 ui32LineNum;
} UNCACHED_ALIGN RGXFWIF_FILE_INFO_BUF;
/*!
* @Defgroup SRVAndFWTracing Services and Firmware Tracing data interface
* @Brief The document groups/lists the data structures and the interfaces related to Services and Firmware Tracing
* @{
*/
/*!
* @Brief Firmware trace buffer details
*/
typedef struct
{
IMG_UINT32 ui32TracePointer;
IMG_UINT32 ui32TracePointer; /*!< Trace pointer (write index into Trace Buffer)*/
#if defined(RGX_FIRMWARE)
IMG_UINT32 *pui32RGXFWIfTraceBuffer; /* To be used by firmware for writing into trace buffer */
IMG_UINT32 *pui32RGXFWIfTraceBuffer; /*!< Trace buffer address (FW address), to be used by firmware for writing into trace buffer */
#else
RGXFWIF_DEV_VIRTADDR pui32RGXFWIfTraceBuffer;
RGXFWIF_DEV_VIRTADDR pui32RGXFWIfTraceBuffer; /*!< Trace buffer address (FW address)*/
#endif
IMG_PUINT32 pui32TraceBuffer; /* To be used by host when reading from trace buffer */
IMG_PUINT32 pui32TraceBuffer; /*!< Trace buffer address (Host address), to be used by host when reading from trace buffer */
RGXFWIF_FILE_INFO_BUF sAssertBuf;
RGXFWIF_FILE_INFO_BUF sAssertBuf;
} UNCACHED_ALIGN RGXFWIF_TRACEBUF_SPACE;
/*! @} End of Defgroup SRVAndFWTracing */
#define RGXFWIF_FWFAULTINFO_MAX (8U) /* Total number of FW fault logs stored */
typedef struct
@@ -229,14 +240,12 @@ typedef IMG_UINT32 RGXFWIF_HWR_STATEFLAGS;
#define RGXFWIF_DM_STATE_GPU_ECC_HWR (IMG_UINT32_C(0x1) << 10) /*!< DM was forced into HWR due to an uncorrected GPU ECC error */
/* Firmware's connection state */
typedef enum
{
RGXFW_CONNECTION_FW_OFFLINE = 0, /*!< Firmware is offline */
RGXFW_CONNECTION_FW_READY, /*!< Firmware is initialised */
RGXFW_CONNECTION_FW_ACTIVE, /*!< Firmware connection is fully established */
RGXFW_CONNECTION_FW_OFFLOADING, /*!< Firmware is clearing up connection data */
RGXFW_CONNECTION_FW_STATE_COUNT
} RGXFWIF_CONNECTION_FW_STATE;
typedef IMG_UINT32 RGXFWIF_CONNECTION_FW_STATE;
#define RGXFW_CONNECTION_FW_OFFLINE 0U /*!< Firmware is offline */
#define RGXFW_CONNECTION_FW_READY 1U /*!< Firmware is initialised */
#define RGXFW_CONNECTION_FW_ACTIVE 2U /*!< Firmware connection is fully established */
#define RGXFW_CONNECTION_FW_OFFLOADING 3U /*!< Firmware is clearing up connection data */
#define RGXFW_CONNECTION_FW_STATE_COUNT 4U
/* OS' connection state */
typedef enum
@@ -259,7 +268,7 @@ typedef struct
typedef IMG_UINT32 RGXFWIF_HWR_RECOVERYFLAGS;
#if defined(PVRSRV_STALLED_CCB_ACTION)
#define PVR_SLR_LOG_ENTRIES 10
#define PVR_SLR_LOG_ENTRIES 10U
#define PVR_SLR_LOG_STRLEN 30 /*!< MAX_CLIENT_CCB_NAME not visible to this header */
typedef struct
@@ -271,14 +280,17 @@ typedef struct
} UNCACHED_ALIGN RGXFWIF_SLR_ENTRY;
#endif
/* firmware trace control data */
/*!
* @InGroup SRVAndFWTracing
* @Brief Firmware trace control data
*/
typedef struct
{
IMG_UINT32 ui32LogType;
RGXFWIF_TRACEBUF_SPACE sTraceBuf[RGXFW_THREAD_NUM];
IMG_UINT32 ui32TraceBufSizeInDWords; /*!< Member initialised only when sTraceBuf is actually allocated
* (in RGXTraceBufferInitOnDemandResources) */
IMG_UINT32 ui32TracebufFlags; /*!< Compatibility and other flags */
IMG_UINT32 ui32LogType; /*!< FW trace log group configuration */
RGXFWIF_TRACEBUF_SPACE sTraceBuf[RGXFW_THREAD_NUM]; /*!< FW Trace buffer */
IMG_UINT32 ui32TraceBufSizeInDWords; /*!< FW Trace buffer size in dwords, Member initialised only when sTraceBuf is actually allocated
(in RGXTraceBufferInitOnDemandResources) */
IMG_UINT32 ui32TracebufFlags; /*!< Compatibility and other flags */
} UNCACHED_ALIGN RGXFWIF_TRACEBUF;
/*! @Brief Firmware system data shared with the Host driver */
@@ -320,6 +332,7 @@ typedef struct
RGXFWIF_HWR_STATEFLAGS ui32HWRStateFlags; /*!< Firmware's Current HWR state */
RGXFWIF_HWR_RECOVERYFLAGS aui32HWRRecoveryFlags[RGXFWIF_DM_MAX]; /*!< Each DM's HWR state */
IMG_UINT32 ui32FwSysDataFlags; /*!< Compatibility and other flags */
IMG_UINT32 ui32McConfig; /*!< Identify whether MC config is P-P or P-S */
} UNCACHED_ALIGN RGXFWIF_SYSDATA;
/*!
@@ -533,18 +546,13 @@ typedef struct
#define RGXFWIF_INICFG_FBCDC_V3_1_EN (IMG_UINT32_C(0x1) << 6)
#define RGXFWIF_INICFG_CHECK_MLIST_EN (IMG_UINT32_C(0x1) << 7)
#define RGXFWIF_INICFG_DISABLE_CLKGATING_EN (IMG_UINT32_C(0x1) << 8)
#define RGXFWIF_INICFG_POLL_COUNTERS_EN (IMG_UINT32_C(0x1) << 9)
#define RGXFWIF_INICFG_VDM_CTX_STORE_MODE_SHIFT (10)
#define RGXFWIF_INICFG_VDM_CTX_STORE_MODE_INDEX ((IMG_UINT32)RGX_CR_VDM_CONTEXT_STORE_MODE_MODE_INDEX << RGXFWIF_INICFG_VDM_CTX_STORE_MODE_SHIFT)
#define RGXFWIF_INICFG_VDM_CTX_STORE_MODE_INSTANCE ((IMG_UINT32)RGX_CR_VDM_CONTEXT_STORE_MODE_MODE_INSTANCE << RGXFWIF_INICFG_VDM_CTX_STORE_MODE_SHIFT)
#define RGXFWIF_INICFG_VDM_CTX_STORE_MODE_LIST ((IMG_UINT32)RGX_CR_VDM_CONTEXT_STORE_MODE_MODE_LIST << RGXFWIF_INICFG_VDM_CTX_STORE_MODE_SHIFT)
#define RGXFWIF_INICFG_VDM_CTX_STORE_MODE_MASK (RGXFWIF_INICFG_VDM_CTX_STORE_MODE_INDEX |\
RGXFWIF_INICFG_VDM_CTX_STORE_MODE_INSTANCE |\
RGXFWIF_INICFG_VDM_CTX_STORE_MODE_LIST)
/* 9 unused */
/* 10 unused */
/* 11 unused */
#define RGXFWIF_INICFG_REGCONFIG_EN (IMG_UINT32_C(0x1) << 12)
#define RGXFWIF_INICFG_ASSERT_ON_OUTOFMEMORY (IMG_UINT32_C(0x1) << 13)
#define RGXFWIF_INICFG_HWP_DISABLE_FILTER (IMG_UINT32_C(0x1) << 14)
#define RGXFWIF_INICFG_CUSTOM_PERF_TIMER_EN (IMG_UINT32_C(0x1) << 15)
/* 15 unused */
#define RGXFWIF_INICFG_CTXSWITCH_PROFILE_SHIFT (16)
#define RGXFWIF_INICFG_CTXSWITCH_PROFILE_FAST (RGXFWIF_CTXSWITCH_PROFILE_FAST_EN << RGXFWIF_INICFG_CTXSWITCH_PROFILE_SHIFT)
#define RGXFWIF_INICFG_CTXSWITCH_PROFILE_MEDIUM (RGXFWIF_CTXSWITCH_PROFILE_MEDIUM_EN << RGXFWIF_INICFG_CTXSWITCH_PROFILE_SHIFT)
@@ -575,7 +583,12 @@ typedef struct
/* Extended Flag definitions affecting the firmware globally */
#define RGXFWIF_INICFG_EXT_TFBC_CONTROL_SHIFT (0)
#define RGXFWIF_INICFG_EXT_TFBC_CONTROL_MASK (IMG_UINT32_C(0x7F)) /* RGX_CR_TFBC_COMPRESSION_CONTROL_MASKFULL */
/* [7] YUV10 override
* [6:4] Quality
* [3] Quality enable
* [2:1] Compression scheme
* [0] Lossy group */
#define RGXFWIF_INICFG_EXT_TFBC_CONTROL_MASK (IMG_UINT32_C(0xFF)) /* RGX_CR_TFBC_COMPRESSION_CONTROL_MASKFULL */
#define RGXFWIF_INICFG_EXT_ALL (RGXFWIF_INICFG_EXT_TFBC_CONTROL_MASK)
#define RGXFWIF_INICFG_SYS_CTXSWITCH_CLRMSK ~(RGXFWIF_INICFG_CTXSWITCH_MODE_RAND | \
@@ -599,7 +612,7 @@ typedef struct
#define RGXFWIF_INICFG_OS_LOW_PRIO_CS_3D (IMG_UINT32_C(0x1) << 6)
#define RGXFWIF_INICFG_OS_LOW_PRIO_CS_CDM (IMG_UINT32_C(0x1) << 7)
#define RGXFWIF_INICFG_OS_ALL (0xFF)
#define RGXFWIF_INICFG_OS_ALL (0xFFU)
#define RGXFWIF_INICFG_OS_CTXSWITCH_DM_ALL (RGXFWIF_INICFG_OS_CTXSWITCH_GEOM_EN | \
RGXFWIF_INICFG_OS_CTXSWITCH_3D_EN | \
@@ -617,12 +630,10 @@ typedef struct
#define RGXFWIF_FILTCFG_TRUNCATE_INT (IMG_UINT32_C(0x1) << 2)
#define RGXFWIF_FILTCFG_NEW_FILTER_MODE (IMG_UINT32_C(0x1) << 1)
typedef enum
{
RGX_ACTIVEPM_FORCE_OFF = 0,
RGX_ACTIVEPM_FORCE_ON = 1,
RGX_ACTIVEPM_DEFAULT = 2
} RGX_ACTIVEPM_CONF;
typedef IMG_UINT32 RGX_ACTIVEPM_CONF;
#define RGX_ACTIVEPM_FORCE_OFF 0U
#define RGX_ACTIVEPM_FORCE_ON 1U
#define RGX_ACTIVEPM_DEFAULT 2U
typedef enum
{
@@ -675,6 +686,7 @@ typedef RGXFWIF_DEV_VIRTADDR PRGXFWIF_GPU_UTIL_FWCB;
typedef RGXFWIF_DEV_VIRTADDR PRGXFWIF_REG_CFG;
typedef RGXFWIF_DEV_VIRTADDR PRGXFWIF_HWPERF_CTL;
typedef RGXFWIF_DEV_VIRTADDR PRGX_HWPERF_CONFIG_MUX_CNTBLK;
typedef RGXFWIF_DEV_VIRTADDR PRGX_HWPERF_CONFIG_CNTBLK;
typedef RGXFWIF_DEV_VIRTADDR PRGX_HWPERF_SELECT_CUSTOM_CNTRS;
typedef RGXFWIF_DEV_VIRTADDR PRGXFWIF_CCB_CTL;
typedef RGXFWIF_DEV_VIRTADDR PRGXFWIF_CCB;
@@ -701,7 +713,7 @@ typedef RGXFWIF_DEV_VIRTADDR PRGXFWIF_RF_CMD;
/*!
* This number is used to represent unallocated page catalog base register
*/
#define RGXFW_BIF_INVALID_PCREG 0xFFFFFFFFU
#define RGXFW_BIF_INVALID_PCSET 0xFFFFFFFFU
/*!
Firmware memory context.
@@ -709,7 +721,7 @@ typedef RGXFWIF_DEV_VIRTADDR PRGXFWIF_RF_CMD;
typedef struct
{
IMG_DEV_PHYADDR RGXFW_ALIGN sPCDevPAddr; /*!< device physical address of context's page catalogue */
IMG_UINT32 uiPageCatBaseRegID; /*!< associated page catalog base register (RGXFW_BIF_INVALID_PCREG == unallocated) */
IMG_UINT32 uiPageCatBaseRegSet; /*!< associated page catalog base register (RGXFW_BIF_INVALID_PCSET == unallocated) */
IMG_UINT32 uiBreakpointAddr; /*!< breakpoint address */
IMG_UINT32 uiBPHandlerAddr; /*!< breakpoint handler address */
IMG_UINT32 uiBreakpointCtl; /*!< DM and enable control for BP */
@@ -728,6 +740,7 @@ typedef struct
#define RGXFWIF_CONTEXT_FLAGS_NEED_RESUME (0x00000001U)
#define RGXFWIF_CONTEXT_FLAGS_MC_NEED_RESUME_MASKFULL (0x000000FFU)
#define RGXFWIF_CONTEXT_FLAGS_TDM_HEADER_STALE (0x00000100U)
#define RGXFWIF_CONTEXT_FLAGS_LAST_KICK_SECURE (0x00000200U)
/*!
* @InGroup ContextSwitching
@@ -738,11 +751,14 @@ typedef struct
/* FW-accessible TA state which must be written out to memory on context store */
IMG_UINT64 RGXFW_ALIGN uTAReg_VDM_CALL_STACK_POINTER; /*!< VDM control stream stack pointer, to store in mid-TA */
IMG_UINT64 RGXFW_ALIGN uTAReg_VDM_CALL_STACK_POINTER_Init; /*!< Initial value of VDM control stream stack pointer (in case is 'lost' due to a lock-up) */
IMG_UINT64 RGXFW_ALIGN uTAReg_VBS_SO_PRIM0;
IMG_UINT64 RGXFW_ALIGN uTAReg_VBS_SO_PRIM1;
IMG_UINT64 RGXFW_ALIGN uTAReg_VBS_SO_PRIM2;
IMG_UINT64 RGXFW_ALIGN uTAReg_VBS_SO_PRIM3;
IMG_UINT32 uTAReg_VBS_SO_PRIM[4];
IMG_UINT16 ui16TACurrentIdx;
} UNCACHED_ALIGN RGXFWIF_TACTX_STATE_PER_GEOM;
typedef struct
{
/* FW-accessible TA state which must be written out to memory on context store */
RGXFWIF_TACTX_STATE_PER_GEOM asGeomCore[RGX_NUM_GEOM_CORES];
} UNCACHED_ALIGN RGXFWIF_TACTX_STATE;
/*!
@@ -761,7 +777,7 @@ typedef struct
IMG_UINT32 au3DReg_ISP_STORE[]; /*!< ISP state (per-pipe) */
} UNCACHED_ALIGN RGXFWIF_3DCTX_STATE;
static_assert(sizeof(RGXFWIF_3DCTX_STATE) <= 16,
static_assert(sizeof(RGXFWIF_3DCTX_STATE) <= 16U,
"Size of structure RGXFWIF_3DCTX_STATE exceeds maximum expected size.");
#define RGXFWIF_CTX_USING_BUFFER_A (0)
@@ -788,7 +804,7 @@ typedef struct RGXFWIF_FWCOMMONCONTEXT_
/* Flags e.g. for context switching */
IMG_UINT32 ui32FWComCtxFlags;
IMG_UINT32 ui32Priority; /*!< Priority level */
IMG_INT32 i32Priority; /*!< Priority level */
IMG_UINT32 ui32PrioritySeqNum;
/* Framework state */
@@ -823,7 +839,7 @@ typedef struct RGXFWIF_FWCOMMONCONTEXT_
} UNCACHED_ALIGN RGXFWIF_FWCOMMONCONTEXT;
static_assert(sizeof(RGXFWIF_FWCOMMONCONTEXT) <= 256,
static_assert(sizeof(RGXFWIF_FWCOMMONCONTEXT) <= 256U,
"Size of structure RGXFWIF_FWCOMMONCONTEXT exceeds maximum expected size.");
typedef IMG_UINT64 RGXFWIF_TRP_CHECKSUM_TQ[RGX_TRP_MAX_NUM_CORES][1];
@@ -846,6 +862,10 @@ typedef struct
IMG_UINT32 ui32FwRenderCtxFlags; /*!< Compatibility and other flags */
#if defined(SUPPORT_TRP)
RGXFWIF_TRP_CHECKSUM_3D aui64TRPChecksums3D;
RGXFWIF_TRP_CHECKSUM_GEOM aui64TRPChecksumsGeom;
#endif
} UNCACHED_ALIGN RGXFWIF_FWRENDERCONTEXT;
/*!
@@ -935,7 +955,11 @@ typedef struct
#if !defined(RGX_FEATURE_SLC_VIVT)
#define RGXFWIF_MMUCACHEDATA_FLAGS_PMTLB (0x10U) /* can't use PM_TLB0 bit from BIFPM_CTRL reg because it collides with PT bit from BIF_CTRL reg */
#if !defined(RGX_FEATURE_XE_ARCHITECTURE) || (RGX_FEATURE_XE_ARCHITECTURE < 2)
#define RGXFWIF_MMUCACHEDATA_FLAGS_TLB (RGXFWIF_MMUCACHEDATA_FLAGS_PMTLB | 0x8U) /* BIF_CTRL_INVAL_TLB1_EN */
#else
#define RGXFWIF_MMUCACHEDATA_FLAGS_TLB (RGXFWIF_MMUCACHEDATA_FLAGS_PMTLB)
#endif
#define RGXFWIF_MMUCACHEDATA_FLAGS_CTX_ALL (0x0U) /* not used */
#else /* RGX_FEATURE_SLC_VIVT */
@@ -1106,6 +1130,12 @@ typedef struct
PRGX_HWPERF_CONFIG_MUX_CNTBLK sBlockConfigs; /*!< Address of the RGX_HWPERF_CONFIG_MUX_CNTBLK array */
} RGXFWIF_HWPERF_CONFIG_ENABLE_BLKS;
typedef struct
{
IMG_UINT32 ui32NumBlocks; /*!< Number of RGX_HWPERF_CONFIG_CNTBLK in the array */
PRGX_HWPERF_CONFIG_CNTBLK sBlockConfigs; /*!< Address of the RGX_HWPERF_CONFIG_CNTBLK array */
} RGXFWIF_HWPERF_CONFIG_DA_BLKS;
/*!
* @Brief Command data for \ref RGXFWIF_KCCB_CMD_CORECLKSPEEDCHANGE type command
*/
@@ -1151,6 +1181,13 @@ typedef struct
IMG_UINT32 ui32RegAddr;
IMG_UINT64 RGXFW_ALIGN ui64RegVal;
} RGXFWIF_RGXREG_DATA;
typedef struct
{
IMG_UINT64 ui64BaseAddress;
PRGXFWIF_FWCOMMONCONTEXT psContext;
IMG_UINT32 ui32Size;
} RGXFWIF_GPUMAP_DATA;
#endif
/*!
@@ -1340,6 +1377,10 @@ typedef enum
RGXFWIF_KCCB_CMD_COUNTER_DUMP = 216U | RGX_CMD_MAGIC_DWORD_SHIFTED, /*!< Controls counter dumping in the FW */
RGXFWIF_KCCB_CMD_HWPERF_CONFIG_ENABLE_BLKS = 217U | RGX_CMD_MAGIC_DWORD_SHIFTED, /*!< Configure, clear and enable multiple HWPerf blocks */
RGXFWIF_KCCB_CMD_HWPERF_SELECT_CUSTOM_CNTRS = 218U | RGX_CMD_MAGIC_DWORD_SHIFTED, /*!< Configure the custom counters for HWPerf */
#if defined(SUPPORT_VALIDATION)
RGXFWIF_KCCB_CMD_GPUMAP = 219U | RGX_CMD_MAGIC_DWORD_SHIFTED, /*!< Request a FW GPU mapping which is written into by the FW with a pattern */
#endif
RGXFWIF_KCCB_CMD_HWPERF_CONFIG_BLKS = 220U | RGX_CMD_MAGIC_DWORD_SHIFTED, /*!< Configure directly addressable counters for HWPerf */
} RGXFWIF_KCCB_CMD_TYPE;
#define RGXFWIF_LAST_ALLOWED_GUEST_KCCB_CMD (RGXFWIF_KCCB_CMD_REGCONFIG - 1)
@@ -1366,7 +1407,8 @@ typedef struct
RGXFWIF_HWPERF_CTRL sHWPerfCtrl; /*!< Data for HWPerf control command */
RGXFWIF_HWPERF_CONFIG_ENABLE_BLKS sHWPerfCfgEnableBlks; /*!< Data for HWPerf configure, clear and enable performance counter block command */
RGXFWIF_HWPERF_CTRL_BLKS sHWPerfCtrlBlks; /*!< Data for HWPerf enable or disable performance counter block commands */
RGXFWIF_HWPERF_SELECT_CUSTOM_CNTRS sHWPerfSelectCstmCntrs; /*!< Data for HWPerf configure the custom counters to read */
RGXFWIF_HWPERF_SELECT_CUSTOM_CNTRS sHWPerfSelectCstmCntrs; /*!< Data for HWPerf configure the custom counters to read */
RGXFWIF_HWPERF_CONFIG_DA_BLKS sHWPerfCfgDABlks; /*!< Data for HWPerf configure Directly Addressable blocks */
RGXFWIF_CORECLKSPEEDCHANGE_DATA sCoreClkSpeedChangeData;/*!< Data for core clock speed change */
RGXFWIF_ZSBUFFER_BACKING_DATA sZSBufferBackingData; /*!< Feedback for Z/S Buffer backing/unbacking */
RGXFWIF_FREELIST_GS_DATA sFreeListGSData; /*!< Feedback for Freelist grow/shrink */
@@ -1381,6 +1423,7 @@ typedef struct
RGXFWIF_KCCB_CMD_FORCE_UPDATE_DATA sForceUpdateData; /*!< Data for signalling all unmet fences for a given CCB */
#if defined(SUPPORT_VALIDATION)
RGXFWIF_RGXREG_DATA sFwRgxData; /*!< Data for reading off an RGX register */
RGXFWIF_GPUMAP_DATA sGPUMapData; /*!< Data for requesting a FW GPU mapping which is written into by the FW with a pattern */
#endif
} UNCACHED_ALIGN uCmdData;
} UNCACHED_ALIGN RGXFWIF_KCCB_CMD;
@@ -1664,7 +1707,7 @@ typedef struct
/*! @Brief Command data for \ref RGXFWIF_CCB_CMD_TYPE_PRIORITY type client CCB command */
typedef struct
{
IMG_UINT32 ui32Priority; /*!< Priority level */
IMG_INT32 i32Priority; /*!< Priority level */
} RGXFWIF_CMD_PRIORITY;
/*! @} End of ClientCCBTypes */
@@ -1721,7 +1764,7 @@ typedef struct
do { \
(name).ui32LayoutVersion = RGXFWIF_COMPCHECKS_LAYOUT_VERSION; \
(name).ui64BVNC = 0; \
} while (0)
} while (false)
typedef struct
{
@@ -1831,8 +1874,6 @@ typedef enum
FW_PERF_CONF_NONE = 0,
FW_PERF_CONF_ICACHE = 1,
FW_PERF_CONF_DCACHE = 2,
FW_PERF_CONF_POLLS = 3,
FW_PERF_CONF_CUSTOM_TIMER = 4,
FW_PERF_CONF_JTLB_INSTR = 5,
FW_PERF_CONF_INSTRUCTIONS = 6
} FW_PERF_CONF;
@@ -1915,6 +1956,9 @@ typedef struct
IMG_DEV_VIRTADDR RGXFW_ALIGN sPDSExecBase; /*!< PDS execution base */
IMG_DEV_VIRTADDR RGXFW_ALIGN sUSCExecBase; /*!< USC execution base */
IMG_DEV_VIRTADDR RGXFW_ALIGN sFBCDCStateTableBase; /*!< FBCDC bindless texture state table base */
IMG_DEV_VIRTADDR RGXFW_ALIGN sFBCDCLargeStateTableBase;
IMG_DEV_VIRTADDR RGXFW_ALIGN sTextureHeapBase; /*!< Texture state base */
IMG_UINT64 RGXFW_ALIGN ui64HWPerfFilter; /*! Event filter for Firmware events */
@@ -2002,10 +2046,11 @@ typedef struct
/* Value to write into RGX_CR_TFBC_COMPRESSION_CONTROL */
IMG_UINT32 ui32TFBCCompressionControl;
} UNCACHED_ALIGN RGXFWIF_SYSINIT;
#if defined(SUPPORT_AUTOVZ)
IMG_UINT32 ui32VzWdgPeriod;
#endif
static_assert(sizeof(RGXFWIF_SYSINIT) <= 792,
"Size of structure RGXFW_SYSINIT exceeds maximum expected size.");
} UNCACHED_ALIGN RGXFWIF_SYSINIT;
#if defined(SUPPORT_GPUVIRT_VALIDATION)
#define RGXFWIF_KICK_TEST_ENABLED_BIT 0x1
@@ -2134,67 +2179,33 @@ typedef struct
IMG_UINT32 ui32RTACtlFlags; /* Compatibility and other flags */
} UNCACHED_ALIGN RGXFWIF_RTA_CTL;
/*! @Brief Firmware Freelist holding usage state of the Parameter Buffers */
/*!
* @InGroup RenderTarget
* @Brief Firmware Freelist holding usage state of the Parameter Buffers
*/
typedef struct
{
IMG_DEV_VIRTADDR RGXFW_ALIGN psFreeListDevVAddr;
IMG_UINT64 RGXFW_ALIGN ui64CurrentDevVAddr;
IMG_UINT32 ui32CurrentStackTop;
IMG_UINT32 ui32MaxPages;
IMG_UINT32 ui32GrowPages;
IMG_UINT32 ui32CurrentPages; /* HW pages */
IMG_UINT32 ui32AllocatedPageCount;
IMG_UINT32 ui32AllocatedMMUPageCount;
IMG_DEV_VIRTADDR RGXFW_ALIGN psFreeListDevVAddr; /*!< Freelist page table base */
IMG_UINT64 RGXFW_ALIGN ui64CurrentDevVAddr;/*!< Freelist page table entry for current free page */
IMG_UINT32 ui32CurrentStackTop; /*!< Freelist current free page */
IMG_UINT32 ui32MaxPages; /*!< Max no. of pages can be added to the freelist */
IMG_UINT32 ui32GrowPages; /*!< No pages to add in each freelist grow */
IMG_UINT32 ui32CurrentPages; /*!< Total no. of pages made available to the PM HW */
IMG_UINT32 ui32AllocatedPageCount; /*!< No. of pages allocated by PM HW */
IMG_UINT32 ui32AllocatedMMUPageCount; /*!< No. of pages allocated for GPU MMU for PM*/
#if defined(SUPPORT_SHADOW_FREELISTS)
IMG_UINT32 ui32HWRCounter;
IMG_UINT32 ui32HWRCounter;
PRGXFWIF_FWMEMCONTEXT psFWMemContext;
#endif
IMG_UINT32 ui32FreeListID;
IMG_BOOL bGrowPending;
IMG_UINT32 ui32ReadyPages; /* Pages that should be used only when OOM is reached */
IMG_UINT32 ui32FreelistFlags; /* Compatibility and other flags */
IMG_UINT32 ui32FreeListID; /*!< Unique Freelist ID */
IMG_BOOL bGrowPending; /*!< Freelist grow is pending */
IMG_UINT32 ui32ReadyPages; /*!< Reserved pages to be used only on PM OOM event */
IMG_UINT32 ui32FreelistFlags; /*!< Compatibility and other flags */
#if defined(SUPPORT_AGP)
IMG_UINT32 ui32PmGlobalPb; /*!< PM Global PB on which Freelist is loaded */
#endif
} UNCACHED_ALIGN RGXFWIF_FREELIST;
/*!
******************************************************************************
* Parameter Management (PM) control data for RGX
*****************************************************************************/
/* Used only by Firmware but defined here for similarity with Volcanic where it's required for SW TRP */
typedef enum
{
RGXFW_SPM_STATE_NONE = 0,
RGXFW_SPM_STATE_PR_BLOCKED,
RGXFW_SPM_STATE_WAIT_FOR_GROW,
RGXFW_SPM_STATE_WAIT_FOR_HW,
RGXFW_SPM_STATE_PR_RUNNING,
RGXFW_SPM_STATE_PR_AVOIDED,
RGXFW_SPM_STATE_PR_EXECUTED,
} RGXFW_SPM_STATE;
/*!
******************************************************************************
* @Brief RGX firmware SPM Control Data:
* This structure holds all the internal SPM control Data of the firmware.
*****************************************************************************/
typedef struct
{
RGXFW_SPM_STATE eSPMState; /*!< Current state of TA OOM event */
RGXFWIF_UFO sPartialRenderTA3DFence; /*!< TA/3D fence object holding the value to let through the 3D partial command */
#if defined(RGX_FIRMWARE)
RGXFWIF_FWCOMMONCONTEXT *ps3dContext; /*!< Pointer to the 3D Context holding the partial render */
RGXFWIF_PRBUFFER *apsPRBuffer[RGXFWIF_PRBUFFER_MAXSUPPORTED]; /*!< Array of pointers to PR Buffers which may be used if partial render is needed */
#else
RGXFWIF_DEV_VIRTADDR ps3dContext; /*!< Pointer to the 3D Context holding the partial render */
RGXFWIF_DEV_VIRTADDR apsPRBuffer[RGXFWIF_PRBUFFER_MAXSUPPORTED]; /*!< Array of pointers to PR Buffers which may be used if partial render is needed */
#endif
IMG_UINT32 ui32CmdOffset; /*!< CCCB offset of the command holding the partial render */
bool b3DMemFreeDetected; /*!< Indicates if a 3D Memory Free has been detected, which resolves OOM */
} RGXFW_ALIGN_DCACHEL RGXFW_SPMCTL;
static_assert(sizeof(RGXFW_SPMCTL) <= 64,
"Size of structure RGXFW_SPMCTL exceeds maximum expected size.");
/*!
******************************************************************************
* HWRTData
@@ -2202,12 +2213,19 @@ static_assert(sizeof(RGXFW_SPMCTL) <= 64,
/* HWRTData flags */
/* Deprecated flags 1:0 */
#define HWRTDATA_HAS_LAST_TA (1U << 2)
#define HWRTDATA_PARTIAL_RENDERED (1U << 3)
#define HWRTDATA_DISABLE_TILE_REORDERING (1U << 4)
#define HWRTDATA_NEED_BRN65101_BLIT (1U << 5)
#define HWRTDATA_FIRST_BRN65101_STRIP (1U << 6)
#define HWRTDATA_NEED_BRN67182_2ND_RENDER (1U << 7)
#define HWRTDATA_HAS_LAST_TA (1UL << 2)
#define HWRTDATA_PARTIAL_RENDERED (1UL << 3)
#define HWRTDATA_DISABLE_TILE_REORDERING (1UL << 4)
#define HWRTDATA_NEED_BRN65101_BLIT (1UL << 5)
#define HWRTDATA_FIRST_BRN65101_STRIP (1UL << 6)
#define HWRTDATA_NEED_BRN67182_2ND_RENDER (1UL << 7)
#if defined(SUPPORT_AGP)
#define HWRTDATA_GLOBAL_PB_NUMBER_BIT0 (1UL << 8)
#if defined(SUPPORT_AGP4)
#define HWRTDATA_GLOBAL_PB_NUMBER_BIT1 (1UL << 9)
#endif
#define HWRTDATA_GEOM_NEEDS_RESUME (1UL << 10)
#endif
typedef enum
{
@@ -2251,51 +2269,55 @@ typedef struct
IMG_UINT32 ui32ISPMtileSize;
} UNCACHED_ALIGN RGXFWIF_HWRTDATA_COMMON;
/*! @Brief Firmware Render Target data i.e. HWRTDATA used to hold the PM context */
/*!
* @InGroup RenderTarget
* @Brief Firmware Render Target data i.e. HWRTDATA used to hold the PM context
*/
typedef struct
{
IMG_DEV_VIRTADDR RGXFW_ALIGN psPMMListDevVAddr; /*!< MList Data Store */
IMG_DEV_VIRTADDR RGXFW_ALIGN psPMMListDevVAddr; /*!< MList Data Store */
IMG_UINT64 RGXFW_ALIGN ui64VCECatBase[4];
IMG_UINT64 RGXFW_ALIGN ui64VCELastCatBase[4];
IMG_UINT64 RGXFW_ALIGN ui64TECatBase[4];
IMG_UINT64 RGXFW_ALIGN ui64TELastCatBase[4];
IMG_UINT64 RGXFW_ALIGN ui64AlistCatBase;
IMG_UINT64 RGXFW_ALIGN ui64AlistLastCatBase;
IMG_UINT64 RGXFW_ALIGN ui64VCECatBase[4]; /*!< VCE Page Catalogue base */
IMG_UINT64 RGXFW_ALIGN ui64VCELastCatBase[4];
IMG_UINT64 RGXFW_ALIGN ui64TECatBase[4]; /*!< TE Page Catalogue base */
IMG_UINT64 RGXFW_ALIGN ui64TELastCatBase[4];
IMG_UINT64 RGXFW_ALIGN ui64AlistCatBase; /*!< Alist Page Catalogue base */
IMG_UINT64 RGXFW_ALIGN ui64AlistLastCatBase;
IMG_UINT64 RGXFW_ALIGN ui64PMAListStackPointer;
IMG_UINT32 ui32PMMListStackPointer;
IMG_UINT64 RGXFW_ALIGN ui64PMAListStackPointer; /*!< Freelist page table entry for current Mlist page */
IMG_UINT32 ui32PMMListStackPointer; /*!< Current Mlist page */
RGXFWIF_DEV_VIRTADDR sHWRTDataCommonFwAddr;
RGXFWIF_DEV_VIRTADDR sHWRTDataCommonFwAddr; /*!< Render target dimension dependent data */
IMG_UINT32 ui32HWRTDataFlags;
RGXFWIF_RTDATA_STATE eState;
IMG_UINT32 ui32HWRTDataFlags;
RGXFWIF_RTDATA_STATE eState; /*!< Current workload processing state of HWRTDATA */
PRGXFWIF_FREELIST RGXFW_ALIGN apsFreeLists[RGXFW_MAX_FREELISTS];
IMG_UINT32 aui32FreeListHWRSnapshot[RGXFW_MAX_FREELISTS];
PRGXFWIF_FREELIST RGXFW_ALIGN apsFreeLists[RGXFW_MAX_FREELISTS]; /*!< Freelist to use */
IMG_UINT32 aui32FreeListHWRSnapshot[RGXFW_MAX_FREELISTS];
IMG_DEV_VIRTADDR RGXFW_ALIGN psVHeapTableDevVAddr;
IMG_DEV_VIRTADDR RGXFW_ALIGN psVHeapTableDevVAddr; /*!< VHeap table base */
RGXFWIF_CLEANUP_CTL sCleanupState;
RGXFWIF_CLEANUP_CTL sCleanupState; /*!< Render target clean up state */
RGXFWIF_RTA_CTL sRTACtl;
RGXFWIF_RTA_CTL sRTACtl; /*!< Render target array data */
IMG_DEV_VIRTADDR RGXFW_ALIGN sTailPtrsDevVAddr;
IMG_DEV_VIRTADDR RGXFW_ALIGN sMacrotileArrayDevVAddr;
IMG_DEV_VIRTADDR RGXFW_ALIGN sRgnHeaderDevVAddr;
IMG_DEV_VIRTADDR RGXFW_ALIGN sRTCDevVAddr;
IMG_DEV_VIRTADDR RGXFW_ALIGN sTailPtrsDevVAddr; /*!< Tail pointers base */
IMG_DEV_VIRTADDR RGXFW_ALIGN sMacrotileArrayDevVAddr; /*!< Macrotiling array base */
IMG_DEV_VIRTADDR RGXFW_ALIGN sRgnHeaderDevVAddr; /*!< Region headers base */
IMG_DEV_VIRTADDR RGXFW_ALIGN sRTCDevVAddr; /*!< Render target cache base */
#if defined(RGX_FIRMWARE)
struct RGXFWIF_FWCOMMONCONTEXT_* RGXFW_ALIGN psOwnerGeom;
struct RGXFWIF_FWCOMMONCONTEXT_* RGXFW_ALIGN psOwnerGeom;
#else
RGXFWIF_DEV_VIRTADDR RGXFW_ALIGN pui32OwnerGeomNotUsedByHost;
RGXFWIF_DEV_VIRTADDR RGXFW_ALIGN pui32OwnerGeomNotUsedByHost;
#endif
#if defined(SUPPORT_TRP)
IMG_UINT32 ui32KickFlagsCopy;
IMG_UINT32 ui32TRPState;
RGXFWIF_TRP_CHECKSUM_3D aui64TRPChecksums3D;
RGXFWIF_TRP_CHECKSUM_GEOM aui64TRPChecksumsGeom;
IMG_UINT32 ui32TEPageCopy;
IMG_UINT32 ui32VCEPageCopy;
IMG_UINT32 ui32KickFlagsCopy;
IMG_UINT32 ui32TRPState;
IMG_UINT32 ui32TEPageCopy;
IMG_UINT32 ui32VCEPageCopy;
#endif
#if defined(SUPPORT_AGP)
IMG_BOOL bTACachesNeedZeroing;
#endif
} UNCACHED_ALIGN RGXFWIF_HWRTDATA;

44
drivers/gpu/drm/img-rogue/include/rogue/rgx_fwif_shared.h
View File

@@ -51,7 +51,17 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#include "powervr/mem_types.h"
/* Indicates the number of RTDATAs per RTDATASET */
#define RGXMKIF_NUM_RTDATAS 2U
#if defined(SUPPORT_AGP)
#define RGXMKIF_NUM_RTDATAS 4U
#define RGXMKIF_NUM_GEOMDATAS 4U
#define RGXMKIF_NUM_RTDATA_FREELISTS 12U /* RGXMKIF_NUM_RTDATAS * RGXFW_MAX_FREELISTS */
#define RGX_NUM_GEOM_CORES (2U)
#else
#define RGXMKIF_NUM_RTDATAS 2U
#define RGXMKIF_NUM_GEOMDATAS 1U
#define RGXMKIF_NUM_RTDATA_FREELISTS 2U /* RGXMKIF_NUM_RTDATAS * RGXFW_MAX_FREELISTS */
#define RGX_NUM_GEOM_CORES (1U)
#endif
/* Maximum number of UFOs in a CCB command.
* The number is based on having 32 sync prims (as originally), plus 32 sync
@@ -121,13 +131,17 @@ typedef enum
RGXFWIF_PRBUFFER_UNBACKING_PENDING,
}RGXFWIF_PRBUFFER_STATE;
/*!
* @InGroup RenderTarget
* @Brief OnDemand Z/S/MSAA Buffers
*/
typedef struct
{
IMG_UINT32 ui32BufferID; /*!< Buffer ID*/
IMG_BOOL bOnDemand; /*!< Needs On-demand Z/S/MSAA Buffer allocation */
RGXFWIF_PRBUFFER_STATE eState; /*!< Z/S/MSAA -Buffer state */
RGXFWIF_CLEANUP_CTL sCleanupState; /*!< Cleanup state */
IMG_UINT32 ui32PRBufferFlags; /*!< Compatibility and other flags */
IMG_UINT32 ui32BufferID; /*!< Buffer ID*/
IMG_BOOL bOnDemand; /*!< Needs On-demand Z/S/MSAA Buffer allocation */
RGXFWIF_PRBUFFER_STATE eState; /*!< Z/S/MSAA -Buffer state */
RGXFWIF_CLEANUP_CTL sCleanupState; /*!< Cleanup state */
IMG_UINT32 ui32PRBufferFlags; /*!< Compatibility and other flags */
} UNCACHED_ALIGN RGXFWIF_PRBUFFER;
/*
@@ -188,7 +202,15 @@ typedef struct
* Points to commands not ready, i.e.
* fence dependencies are not met. */
IMG_UINT32 ui32WrapMask; /*!< Offset wrapping mask, total capacity
* in bytes of the CCB-1 */
in bytes of the CCB-1 */
#if defined(SUPPORT_AGP)
IMG_UINT32 ui32ReadOffset2;
#if defined(SUPPORT_AGP4)
IMG_UINT32 ui32ReadOffset3;
IMG_UINT32 ui32ReadOffset4;
#endif
#endif
} UNCACHED_ALIGN RGXFWIF_CCCB_CTL;
@@ -196,7 +218,13 @@ typedef IMG_UINT32 RGXFW_FREELIST_TYPE;
#define RGXFW_LOCAL_FREELIST IMG_UINT32_C(0)
#define RGXFW_GLOBAL_FREELIST IMG_UINT32_C(1)
#if defined(SUPPORT_AGP)
#define RGXFW_GLOBAL2_FREELIST IMG_UINT32_C(2)
#define RGXFW_MAX_FREELISTS (RGXFW_GLOBAL2_FREELIST + 1U)
#else
#define RGXFW_MAX_FREELISTS (RGXFW_GLOBAL_FREELIST + 1U)
#endif
#define RGXFW_MAX_HWFREELISTS (2U)
/*!
* @Defgroup ContextSwitching Context switching data interface
@@ -256,7 +284,7 @@ typedef struct
*/
typedef struct
{
RGXFWIF_TAREGISTERS_CSWITCH RGXFW_ALIGN sCtxSwitch_Regs; /*!< Geom registers for ctx switch */
RGXFWIF_TAREGISTERS_CSWITCH RGXFW_ALIGN asCtxSwitch_GeomRegs[RGX_NUM_GEOM_CORES]; /*!< Geom registers for ctx switch */
} RGXFWIF_STATIC_RENDERCONTEXT_STATE;
#define RGXFWIF_STATIC_RENDERCONTEXT_SIZE sizeof(RGXFWIF_STATIC_RENDERCONTEXT_STATE)

1
drivers/gpu/drm/img-rogue/include/rogue/rgx_heaps.h
View File

@@ -54,6 +54,7 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define RGX_VK_CAPT_REPLAY_HEAP_IDENT "Vulkan Capture Replay" /*!< RGX Vulkan capture replay buffer Heap Identifier */
#define RGX_SIGNALS_HEAP_IDENT "Signals" /*!< Signals Heap Identifier */
#define RGX_FBCDC_HEAP_IDENT "FBCDC" /*!< RGX FBCDC State Table Heap Identifier */
#define RGX_FBCDC_LARGE_HEAP_IDENT "Large FBCDC" /*!< RGX Large FBCDC State Table Heap Identifier */
#define RGX_CMP_MISSION_RMW_HEAP_IDENT "Compute Mission RMW" /*!< Compute Mission RMW Heap Identifier */
#define RGX_CMP_SAFETY_RMW_HEAP_IDENT "Compute Safety RMW" /*!< Compute Safety RMW Heap Identifier */
#define RGX_TEXTURE_STATE_HEAP_IDENT "Texture State" /*!< Texture State Heap Identifier */

524
drivers/gpu/drm/img-rogue/include/rogue/rgx_hwperf.h
View File

@@ -60,6 +60,7 @@ extern "C" {
#include "img_defs.h"
#include "rgx_common.h"
#include "rgx_hwperf_common.h"
#include "pvrsrv_tlcommon.h"
#include "pvrsrv_sync_km.h"
@@ -141,404 +142,8 @@ static_assert(RGX_FEATURE_NUM_CLUSTERS <= 16U, "Cluster count too large for HWPe
/*! The number of counters supported in each non-mux counter block */
#define RGX_HWPERF_MAX_CUSTOM_CNTRS 8U
/*! The number of non-mux counter blocks supported */
#if defined(SUPPORT_VALIDATION)
#define RGX_CNTBLK_COUNTERS_MAX 64U
#else
#define RGX_CNTBLK_COUNTERS_MAX 12U
#endif
/******************************************************************************
* Packet Event Type Enumerations
*****************************************************************************/
/*! Type used to encode the event that generated the packet.
* NOTE: When this type is updated the corresponding hwperfbin2json tool
* source needs to be updated as well. The RGX_HWPERF_EVENT_MASK_* macros will
* also need updating when adding new types.
*
* @par
* The event type values are incrementing integers for use as a shift ordinal
* in the event filtering process at the point events are generated.
* This scheme thus implies a limit of 63 event types.
*/
typedef IMG_UINT32 RGX_HWPERF_EVENT_TYPE;
#define RGX_HWPERF_INVALID 0x00U /*!< Invalid. Reserved value. */
/*! FW types 0x01..0x06 */
#define RGX_HWPERF_FW_EVENT_RANGE_FIRST_TYPE 0x01U
#define RGX_HWPERF_FW_BGSTART 0x01U /*!< Background task processing start */
#define RGX_HWPERF_FW_BGEND 0x02U /*!< Background task end */
#define RGX_HWPERF_FW_IRQSTART 0x03U /*!< IRQ task processing start */
#define RGX_HWPERF_FW_IRQEND 0x04U /*!< IRQ task end */
#define RGX_HWPERF_FW_DBGSTART 0x05U /*!< Debug event start */
#define RGX_HWPERF_FW_DBGEND 0x06U /*!< Debug event end */
#define RGX_HWPERF_FW_EVENT_RANGE_LAST_TYPE 0x06U
/*! HW types 0x07..0x19 */
#define RGX_HWPERF_HW_EVENT_RANGE0_FIRST_TYPE 0x07U
#define RGX_HWPERF_HW_PMOOM_TAPAUSE 0x07U /*!< TA Pause at PM Out of Memory */
#define RGX_HWPERF_HW_TAKICK 0x08U /*!< TA task started */
#define RGX_HWPERF_HW_TAFINISHED 0x09U /*!< TA task finished */
#define RGX_HWPERF_HW_3DTQKICK 0x0AU /*!< 3D TQ started */
#define RGX_HWPERF_HW_3DKICK 0x0BU /*!< 3D task started */
#define RGX_HWPERF_HW_3DFINISHED 0x0CU /*!< 3D task finished */
#define RGX_HWPERF_HW_CDMKICK 0x0DU /*!< CDM task started */
#define RGX_HWPERF_HW_CDMFINISHED 0x0EU /*!< CDM task finished */
#define RGX_HWPERF_HW_TLAKICK 0x0FU /*!< TLA task started */
#define RGX_HWPERF_HW_TLAFINISHED 0x10U /*!< TLS task finished */
#define RGX_HWPERF_HW_3DSPMKICK 0x11U /*!< 3D SPM task started */
#define RGX_HWPERF_HW_PERIODIC 0x12U /*!< Periodic event with updated HW counters */
#define RGX_HWPERF_HW_RTUKICK 0x13U /*!< Reserved, future use */
#define RGX_HWPERF_HW_RTUFINISHED 0x14U /*!< Reserved, future use */
#define RGX_HWPERF_HW_SHGKICK 0x15U /*!< Reserved, future use */
#define RGX_HWPERF_HW_SHGFINISHED 0x16U /*!< Reserved, future use */
#define RGX_HWPERF_HW_3DTQFINISHED 0x17U /*!< 3D TQ finished */
#define RGX_HWPERF_HW_3DSPMFINISHED 0x18U /*!< 3D SPM task finished */
#define RGX_HWPERF_HW_PMOOM_TARESUME 0x19U /*!< TA Resume after PM Out of Memory */
/*! HW_EVENT_RANGE0 used up. Use next empty range below to add new hardware events */
#define RGX_HWPERF_HW_EVENT_RANGE0_LAST_TYPE 0x19U
/*! other types 0x1A..0x1F */
#define RGX_HWPERF_CLKS_CHG 0x1AU /*!< Clock speed change in GPU */
#define RGX_HWPERF_GPU_STATE_CHG 0x1BU /*!< GPU work state change */
/*! power types 0x20..0x27 */
#define RGX_HWPERF_PWR_EST_RANGE_FIRST_TYPE 0x20U
#define RGX_HWPERF_PWR_EST_REQUEST 0x20U /*!< Power estimate requested (via GPIO) */
#define RGX_HWPERF_PWR_EST_READY 0x21U /*!< Power estimate inputs ready */
#define RGX_HWPERF_PWR_EST_RESULT 0x22U /*!< Power estimate result calculated */
#define RGX_HWPERF_PWR_EST_RANGE_LAST_TYPE 0x22U
#define RGX_HWPERF_PWR_CHG 0x23U /*!< Power state change */
/*! HW_EVENT_RANGE1 0x28..0x2F, for accommodating new hardware events */
#define RGX_HWPERF_HW_EVENT_RANGE1_FIRST_TYPE 0x28U
#define RGX_HWPERF_HW_TDMKICK 0x28U /*!< TDM task started */
#define RGX_HWPERF_HW_TDMFINISHED 0x29U /*!< TDM task finished */
#define RGX_HWPERF_HW_NULLKICK 0x2AU /*!< NULL event */
#define RGX_HWPERF_HW_EVENT_RANGE1_LAST_TYPE 0x2AU
/*! context switch types 0x30..0x31 */
#define RGX_HWPERF_CSW_START 0x30U /*!< HW context store started */
#define RGX_HWPERF_CSW_FINISHED 0x31U /*!< HW context store finished */
/*! DVFS events */
#define RGX_HWPERF_DVFS 0x32U /*!< Dynamic voltage/frequency scaling events */
/*! firmware misc 0x38..0x39 */
#define RGX_HWPERF_UFO 0x38U /*!< FW UFO Check / Update */
#define RGX_HWPERF_FWACT 0x39U /*!< FW Activity notification */
/*! last */
#define RGX_HWPERF_LAST_TYPE 0x3BU
/*! This enumeration must have a value that is a power of two as it is
* used in masks and a filter bit field (currently 64 bits long).
*/
#define RGX_HWPERF_MAX_TYPE 0x40U
static_assert(RGX_HWPERF_LAST_TYPE < RGX_HWPERF_MAX_TYPE, "Too many HWPerf event types");
/*! Macro used to check if an event type ID is present in the known set of hardware type events */
#define HWPERF_PACKET_IS_HW_TYPE(_etype) (((_etype) >= RGX_HWPERF_HW_EVENT_RANGE0_FIRST_TYPE && (_etype) <= RGX_HWPERF_HW_EVENT_RANGE0_LAST_TYPE) || \
((_etype) >= RGX_HWPERF_HW_EVENT_RANGE1_FIRST_TYPE && (_etype) <= RGX_HWPERF_HW_EVENT_RANGE1_LAST_TYPE))
/*! Macro used to check if an event type ID is present in the known set of firmware type events */
#define HWPERF_PACKET_IS_FW_TYPE(_etype) \
((_etype) >= RGX_HWPERF_FW_EVENT_RANGE_FIRST_TYPE && \
(_etype) <= RGX_HWPERF_FW_EVENT_RANGE_LAST_TYPE)
typedef enum {
RGX_HWPERF_HOST_INVALID = 0x00, /*!< Invalid, do not use. */
RGX_HWPERF_HOST_ENQ = 0x01, /*!< ``0x01`` Kernel driver has queued GPU work.
See RGX_HWPERF_HOST_ENQ_DATA */
RGX_HWPERF_HOST_UFO = 0x02, /*!< ``0x02`` UFO updated by the driver.
See RGX_HWPERF_HOST_UFO_DATA */
RGX_HWPERF_HOST_ALLOC = 0x03, /*!< ``0x03`` Resource allocated.
See RGX_HWPERF_HOST_ALLOC_DATA */
RGX_HWPERF_HOST_CLK_SYNC = 0x04, /*!< ``0x04`` GPU / Host clocks correlation data.
See RGX_HWPERF_HOST_CLK_SYNC_DATA */
RGX_HWPERF_HOST_FREE = 0x05, /*!< ``0x05`` Resource freed,
See RGX_HWPERF_HOST_FREE_DATA */
RGX_HWPERF_HOST_MODIFY = 0x06, /*!< ``0x06`` Resource modified / updated.
See RGX_HWPERF_HOST_MODIFY_DATA */
RGX_HWPERF_HOST_DEV_INFO = 0x07, /*!< ``0x07`` Device Health status.
See RGX_HWPERF_HOST_DEV_INFO_DATA */
RGX_HWPERF_HOST_INFO = 0x08, /*!< ``0x08`` Device memory usage information.
See RGX_HWPERF_HOST_INFO_DATA */
RGX_HWPERF_HOST_SYNC_FENCE_WAIT = 0x09, /*!< ``0x09`` Wait for sync event.
See RGX_HWPERF_HOST_SYNC_FENCE_WAIT_DATA */
RGX_HWPERF_HOST_SYNC_SW_TL_ADVANCE = 0x0A, /*!< ``0x0A`` Software timeline advanced.
See RGX_HWPERF_HOST_SYNC_SW_TL_ADV_DATA */
/*! last */
RGX_HWPERF_HOST_LAST_TYPE,
/*! This enumeration must have a value that is a power of two as it is
* used in masks and a filter bit field (currently 32 bits long).
*/
RGX_HWPERF_HOST_MAX_TYPE = 0x20
} RGX_HWPERF_HOST_EVENT_TYPE;
/*!< The event type values are incrementing integers for use as a shift ordinal
* in the event filtering process at the point events are generated.
* This scheme thus implies a limit of 31 event types.
*/
static_assert(RGX_HWPERF_HOST_LAST_TYPE < RGX_HWPERF_HOST_MAX_TYPE, "Too many HWPerf host event types");
/******************************************************************************
* Packet Header Format Version 2 Types
*****************************************************************************/
/*! Major version number of the protocol in operation
*/
#define RGX_HWPERF_V2_FORMAT 2
/*! Signature ASCII pattern 'HWP2' found in the first word of a HWPerfV2 packet
*/
#define HWPERF_PACKET_V2_SIG 0x48575032
/*! Signature ASCII pattern 'HWPA' found in the first word of a HWPerfV2a packet
*/
#define HWPERF_PACKET_V2A_SIG 0x48575041
/*! Signature ASCII pattern 'HWPB' found in the first word of a HWPerfV2b packet
*/
#define HWPERF_PACKET_V2B_SIG 0x48575042
#define HWPERF_PACKET_ISVALID(_ptr) (((_ptr) == HWPERF_PACKET_V2_SIG) || ((_ptr) == HWPERF_PACKET_V2A_SIG)|| ((_ptr) == HWPERF_PACKET_V2B_SIG))
/*!< Checks that the packet signature is one of the supported versions */
/*! Type defines the HWPerf packet header common to all events. */
typedef struct
{
IMG_UINT32 ui32Sig; /*!< Always the value HWPERF_PACKET_SIG */
IMG_UINT32 ui32Size; /*!< Overall packet size in bytes */
IMG_UINT32 eTypeId; /*!< Event type information field */
IMG_UINT32 ui32Ordinal; /*!< Sequential number of the packet */
IMG_UINT64 ui64Timestamp; /*!< Event timestamp */
} RGX_HWPERF_V2_PACKET_HDR, *RGX_PHWPERF_V2_PACKET_HDR;
#ifndef __CHECKER__
RGX_FW_STRUCT_OFFSET_ASSERT(RGX_HWPERF_V2_PACKET_HDR, ui64Timestamp);
RGX_FW_STRUCT_SIZE_ASSERT(RGX_HWPERF_V2_PACKET_HDR);
#endif
/*! Mask for use with the IMG_UINT32 ui32Size header field */
#define RGX_HWPERF_SIZE_MASK 0xFFFFU
/*! This macro defines an upper limit to which the size of the largest variable
* length HWPerf packet must fall within, currently 3KB. This constant may be
* used to allocate a buffer to hold one packet.
* This upper limit is policed by packet producing code.
*/
#define RGX_HWPERF_MAX_PACKET_SIZE 0xC00U
/*! Defines an upper limit to the size of a variable length packet payload.
*/
#define RGX_HWPERF_MAX_PAYLOAD_SIZE ((IMG_UINT32)(RGX_HWPERF_MAX_PACKET_SIZE-\
sizeof(RGX_HWPERF_V2_PACKET_HDR)))
/*! Macro which takes a structure name and provides the packet size for
* a fixed size payload packet, rounded up to 8 bytes to align packets
* for 64 bit architectures. */
#define RGX_HWPERF_MAKE_SIZE_FIXED(_struct) ((IMG_UINT32)(RGX_HWPERF_SIZE_MASK&(sizeof(RGX_HWPERF_V2_PACKET_HDR)+PVR_ALIGN(sizeof(_struct), PVRSRVTL_PACKET_ALIGNMENT))))
/*! Macro which takes the number of bytes written in the data payload of a
* packet for a variable size payload packet, rounded up to 8 bytes to
* align packets for 64 bit architectures. */
#define RGX_HWPERF_MAKE_SIZE_VARIABLE(_size) ((IMG_UINT32)(RGX_HWPERF_SIZE_MASK&(sizeof(RGX_HWPERF_V2_PACKET_HDR)+PVR_ALIGN((_size), PVRSRVTL_PACKET_ALIGNMENT))))
/*! Macro to obtain the size of the packet */
#define RGX_HWPERF_GET_SIZE(_packet_addr) ((IMG_UINT16)(((_packet_addr)->ui32Size) & RGX_HWPERF_SIZE_MASK))
/*! Macro to obtain the size of the packet data */
#define RGX_HWPERF_GET_DATA_SIZE(_packet_addr) (RGX_HWPERF_GET_SIZE(_packet_addr) - sizeof(RGX_HWPERF_V2_PACKET_HDR))
/*! Masks for use with the IMG_UINT32 eTypeId header field */
#define RGX_HWPERF_TYPEID_MASK 0x0007FFFFU
#define RGX_HWPERF_TYPEID_EVENT_MASK 0x00007FFFU
#define RGX_HWPERF_TYPEID_THREAD_MASK 0x00008000U
#define RGX_HWPERF_TYPEID_STREAM_MASK 0x00070000U
#define RGX_HWPERF_TYPEID_META_DMA_MASK 0x00080000U
#define RGX_HWPERF_TYPEID_M_CORE_MASK 0x00100000U
#define RGX_HWPERF_TYPEID_OSID_MASK 0x07000000U
/*! Meta thread macros for encoding the ID into the type field of a packet */
#define RGX_HWPERF_META_THREAD_SHIFT 15U
#define RGX_HWPERF_META_THREAD_ID0 0x0U /*!< Meta Thread 0 ID */
#define RGX_HWPERF_META_THREAD_ID1 0x1U /*!< Meta Thread 1 ID */
/*! Obsolete, kept for source compatibility */
#define RGX_HWPERF_META_THREAD_MASK 0x1U
/*! Stream ID macros for encoding the ID into the type field of a packet */
#define RGX_HWPERF_STREAM_SHIFT 16U
/*! Meta DMA macro for encoding how the packet was generated into the type field of a packet */
#define RGX_HWPERF_META_DMA_SHIFT 19U
/*! Bit-shift macro used for encoding multi-core data into the type field of a packet */
#define RGX_HWPERF_M_CORE_SHIFT 20U
/*! OSID bit-shift macro used for encoding OSID into type field of a packet */
#define RGX_HWPERF_OSID_SHIFT 24U
typedef enum {
RGX_HWPERF_STREAM_ID0_FW, /*!< Events from the Firmware/GPU */
RGX_HWPERF_STREAM_ID1_HOST, /*!< Events from the Server host driver component */
RGX_HWPERF_STREAM_ID2_CLIENT, /*!< Events from the Client host driver component */
RGX_HWPERF_STREAM_ID_LAST,
} RGX_HWPERF_STREAM_ID;
/* Checks if all stream IDs can fit under RGX_HWPERF_TYPEID_STREAM_MASK. */
static_assert(((IMG_UINT32)RGX_HWPERF_STREAM_ID_LAST - 1U) < (RGX_HWPERF_TYPEID_STREAM_MASK >> RGX_HWPERF_STREAM_SHIFT),
"Too many HWPerf stream IDs.");
/*! Compile-time value used to seed the Multi-Core (MC) bit in the typeID field.
* Only set by RGX_FIRMWARE builds.
*/
#if defined(RGX_FIRMWARE)
# if defined(RGX_FEATURE_GPU_MULTICORE_SUPPORT)
#define RGX_HWPERF_M_CORE_VALUE 1U /*!< 1 => Multi-core supported */
# else
#define RGX_HWPERF_M_CORE_VALUE 0U /*!< 0 => Multi-core not supported */
# endif
#else
#define RGX_HWPERF_M_CORE_VALUE 0U /*!< 0 => Multi-core not supported */
#endif
/*! Macros used to set the packet type and encode meta thread ID (0|1),
* HWPerf stream ID, multi-core capability and OSID within the typeID */
#define RGX_HWPERF_MAKE_TYPEID(_stream, _type, _thread, _metadma, _osid)\
((IMG_UINT32) ((RGX_HWPERF_TYPEID_STREAM_MASK&((IMG_UINT32)(_stream) << RGX_HWPERF_STREAM_SHIFT)) | \
(RGX_HWPERF_TYPEID_THREAD_MASK & ((IMG_UINT32)(_thread) << RGX_HWPERF_META_THREAD_SHIFT)) | \
(RGX_HWPERF_TYPEID_EVENT_MASK & (IMG_UINT32)(_type)) | \
(RGX_HWPERF_TYPEID_META_DMA_MASK & ((IMG_UINT32)(_metadma) << RGX_HWPERF_META_DMA_SHIFT)) | \
(RGX_HWPERF_TYPEID_OSID_MASK & ((IMG_UINT32)(_osid) << RGX_HWPERF_OSID_SHIFT)) | \
(RGX_HWPERF_TYPEID_M_CORE_MASK & ((IMG_UINT32)(RGX_HWPERF_M_CORE_VALUE) << RGX_HWPERF_M_CORE_SHIFT))))
/*! Obtains the event type that generated the packet */
#define RGX_HWPERF_GET_TYPE(_packet_addr) (((_packet_addr)->eTypeId) & RGX_HWPERF_TYPEID_EVENT_MASK)
/*! Obtains the META Thread number that generated the packet */
#define RGX_HWPERF_GET_THREAD_ID(_packet_addr) (((((_packet_addr)->eTypeId) & RGX_HWPERF_TYPEID_THREAD_MASK) >> RGX_HWPERF_META_THREAD_SHIFT))
/*! Determines if the packet generated contains multi-core data */
#define RGX_HWPERF_GET_M_CORE(_packet_addr) (((_packet_addr)->eTypeId & RGX_HWPERF_TYPEID_M_CORE_MASK) >> RGX_HWPERF_M_CORE_SHIFT)
/*! Obtains the guest OSID which resulted in packet generation */
#define RGX_HWPERF_GET_OSID(_packet_addr) (((_packet_addr)->eTypeId & RGX_HWPERF_TYPEID_OSID_MASK) >> RGX_HWPERF_OSID_SHIFT)
/*! Obtain stream id */
#define RGX_HWPERF_GET_STREAM_ID(_packet_addr) (((((_packet_addr)->eTypeId) & RGX_HWPERF_TYPEID_STREAM_MASK) >> RGX_HWPERF_STREAM_SHIFT))
/*! Obtain information about how the packet was generated, which might affect payload total size */
#define RGX_HWPERF_GET_META_DMA_INFO(_packet_addr) (((((_packet_addr)->eTypeId) & RGX_HWPERF_TYPEID_META_DMA_MASK) >> RGX_HWPERF_META_DMA_SHIFT))
/*! Obtains a typed pointer to a packet given a buffer address */
#define RGX_HWPERF_GET_PACKET(_buffer_addr) ((RGX_HWPERF_V2_PACKET_HDR *)(void *) (_buffer_addr))
/*! Obtains a typed pointer to a data structure given a packet address */
#define RGX_HWPERF_GET_PACKET_DATA_BYTES(_packet_addr) (IMG_OFFSET_ADDR((_packet_addr), sizeof(RGX_HWPERF_V2_PACKET_HDR)))
/*! Obtains a typed pointer to the next packet given a packet address */
#define RGX_HWPERF_GET_NEXT_PACKET(_packet_addr) ((RGX_HWPERF_V2_PACKET_HDR *) (IMG_OFFSET_ADDR((_packet_addr), RGX_HWPERF_SIZE_MASK&((_packet_addr)->ui32Size))))
/*! Obtains a typed pointer to a packet header given the packet data address */
#define RGX_HWPERF_GET_PACKET_HEADER(_packet_addr) ((RGX_HWPERF_V2_PACKET_HDR *) (IMG_OFFSET_ADDR((_packet_addr), -(IMG_INT32)sizeof(RGX_HWPERF_V2_PACKET_HDR))))
/******************************************************************************
* Other Common Defines
*****************************************************************************/
/*! This macro is not a real array size, but indicates the array has a variable
* length only known at run-time but always contains at least 1 element. The
* final size of the array is deduced from the size field of a packet header.
*/
#define RGX_HWPERF_ONE_OR_MORE_ELEMENTS 1U
/*! This macro is not a real array size, but indicates the array is optional
* and if present has a variable length only known at run-time. The final
* size of the array is deduced from the size field of a packet header. */
#define RGX_HWPERF_ZERO_OR_MORE_ELEMENTS 1U
/*! Masks for use with the IMG_UINT32 ui32BlkInfo field */
#define RGX_HWPERF_BLKINFO_BLKCOUNT_MASK 0xFFFF0000U
#define RGX_HWPERF_BLKINFO_BLKOFFSET_MASK 0x0000FFFFU
/*! Shift for the NumBlocks and counter block offset field in ui32BlkInfo */
#define RGX_HWPERF_BLKINFO_BLKCOUNT_SHIFT 16U
#define RGX_HWPERF_BLKINFO_BLKOFFSET_SHIFT 0U
/*! Macro used to set the block info word as a combination of two 16-bit integers */
#define RGX_HWPERF_MAKE_BLKINFO(_numblks, _blkoffset) ((IMG_UINT32) ((RGX_HWPERF_BLKINFO_BLKCOUNT_MASK&((_numblks) << RGX_HWPERF_BLKINFO_BLKCOUNT_SHIFT)) | (RGX_HWPERF_BLKINFO_BLKOFFSET_MASK&((_blkoffset) << RGX_HWPERF_BLKINFO_BLKOFFSET_SHIFT))))
/*! Macro used to obtain the number of counter blocks present in the packet */
#define RGX_HWPERF_GET_BLKCOUNT(_blkinfo) (((_blkinfo) & RGX_HWPERF_BLKINFO_BLKCOUNT_MASK) >> RGX_HWPERF_BLKINFO_BLKCOUNT_SHIFT)
/*! Obtains the offset of the counter block stream in the packet */
#define RGX_HWPERF_GET_BLKOFFSET(_blkinfo) (((_blkinfo) & RGX_HWPERF_BLKINFO_BLKOFFSET_MASK) >> RGX_HWPERF_BLKINFO_BLKOFFSET_SHIFT)
/*! This macro gets the number of blocks depending on the packet version */
#define RGX_HWPERF_GET_NUMBLKS(_sig, _packet_data, _numblocks) \
do { \
if (HWPERF_PACKET_V2B_SIG == (_sig)) \
{ \
(_numblocks) = RGX_HWPERF_GET_BLKCOUNT((_packet_data)->ui32BlkInfo);\
} \
else \
{ \
IMG_UINT32 ui32VersionOffset = (((_sig) == HWPERF_PACKET_V2_SIG) ? 1 : 3);\
(_numblocks) = *(IMG_UINT16 *)(IMG_OFFSET_ADDR(&(_packet_data)->ui32WorkTarget, ui32VersionOffset)); \
} \
} while (0)
/*! This macro gets the counter stream pointer depending on the packet version */
#define RGX_HWPERF_GET_CNTSTRM(_sig, _hw_packet_data, _cntstream_ptr) \
{ \
if (HWPERF_PACKET_V2B_SIG == (_sig)) \
{ \
(_cntstream_ptr) = (IMG_UINT32 *)(IMG_OFFSET_ADDR((_hw_packet_data), RGX_HWPERF_GET_BLKOFFSET((_hw_packet_data)->ui32BlkInfo))); \
} \
else \
{ \
IMG_UINT32 ui32BlkStreamOffsetInWords = (((_sig) == HWPERF_PACKET_V2_SIG) ? 6 : 8); \
(_cntstream_ptr) = (IMG_UINT32 *)(IMG_OFFSET_ADDR_DW((_hw_packet_data), ui32BlkStreamOffsetInWords)); \
} \
}
/*! Masks for use with the RGX_HWPERF_UFO_EV eEvType field */
#define RGX_HWPERF_UFO_STREAMSIZE_MASK 0xFFFF0000U
#define RGX_HWPERF_UFO_STREAMOFFSET_MASK 0x0000FFFFU
/*! Shift for the UFO count and data stream fields */
#define RGX_HWPERF_UFO_STREAMSIZE_SHIFT 16U
#define RGX_HWPERF_UFO_STREAMOFFSET_SHIFT 0U
/*! Macro used to set UFO stream info word as a combination of two 16-bit integers */
#define RGX_HWPERF_MAKE_UFOPKTINFO(_ssize, _soff) \
((IMG_UINT32) ((RGX_HWPERF_UFO_STREAMSIZE_MASK&((_ssize) << RGX_HWPERF_UFO_STREAMSIZE_SHIFT)) | \
(RGX_HWPERF_UFO_STREAMOFFSET_MASK&((_soff) << RGX_HWPERF_UFO_STREAMOFFSET_SHIFT))))
/*! Macro used to obtain UFO count*/
#define RGX_HWPERF_GET_UFO_STREAMSIZE(_streaminfo) \
(((_streaminfo) & RGX_HWPERF_UFO_STREAMSIZE_MASK) >> RGX_HWPERF_UFO_STREAMSIZE_SHIFT)
/*! Obtains the offset of the UFO stream in the packet */
#define RGX_HWPERF_GET_UFO_STREAMOFFSET(_streaminfo) \
(((_streaminfo) & RGX_HWPERF_UFO_STREAMOFFSET_MASK) >> RGX_HWPERF_UFO_STREAMOFFSET_SHIFT)
/*! The number of directly-addressable counters allowed in non-mux counter blocks */
#define RGX_CNTBLK_COUNTERS_MAX ((IMG_UINT32)PVRSRV_HWPERF_COUNTERS_PERBLK + 0U)
/******************************************************************************
@@ -565,18 +170,20 @@ typedef enum {
RGX_HWPERF_DM_INVALID = 0x1FFFFFFF
} RGX_HWPERF_DM;
/*! Enum containing bit position for 32bit feature flags used in hwperf and api */
typedef enum {
RGX_HWPERF_FEATURE_PERFBUS_FLAG = 0x001,
RGX_HWPERF_FEATURE_S7_TOP_INFRASTRUCTURE_FLAG = 0x002,
RGX_HWPERF_FEATURE_XT_TOP_INFRASTRUCTURE_FLAG = 0x004,
RGX_HWPERF_FEATURE_PERF_COUNTER_BATCH_FLAG = 0x008,
RGX_HWPERF_FEATURE_ROGUEXE_FLAG = 0x010,
RGX_HWPERF_FEATURE_DUST_POWER_ISLAND_S7_FLAG = 0x020,
RGX_HWPERF_FEATURE_PBE2_IN_XE_FLAG = 0x040,
RGX_HWPERF_FEATURE_WORKLOAD_ESTIMATION = 0x080,
RGX_HWPERF_FEATURE_MULTICORE_FLAG = 0x100
} RGX_HWPERF_FEATURE_FLAGS;
/*! Define containing bit position for 32bit feature flags used in hwperf and api */
typedef IMG_UINT32 RGX_HWPERF_FEATURE_FLAGS;
#define RGX_HWPERF_FEATURE_PERFBUS_FLAG 0x0001U
#define RGX_HWPERF_FEATURE_S7_TOP_INFRASTRUCTURE_FLAG 0x0002U
#define RGX_HWPERF_FEATURE_XT_TOP_INFRASTRUCTURE_FLAG 0x0004U
#define RGX_HWPERF_FEATURE_PERF_COUNTER_BATCH_FLAG 0x0008U
#define RGX_HWPERF_FEATURE_ROGUEXE_FLAG 0x0010U
#define RGX_HWPERF_FEATURE_DUST_POWER_ISLAND_S7_FLAG 0x0020U
#define RGX_HWPERF_FEATURE_PBE2_IN_XE_FLAG 0x0040U
#define RGX_HWPERF_FEATURE_WORKLOAD_ESTIMATION 0x0080U
#define RGX_HWPERF_FEATURE_MULTICORE_FLAG 0x0100U
#define RGX_HWPERF_FEATURE_VOLCANIC_FLAG 0x0800U
#define RGX_HWPERF_FEATURE_ROGUE_FLAG 0x1000U
#define RGX_HWPERF_FEATURE_OCEANIC_FLAG 0x2000U
/*! This structure holds the data of a firmware packet. */
typedef struct
@@ -606,11 +213,14 @@ typedef struct
IMG_UINT32 ui32WorkCtx; /*!< Work context: Render Context for TA/3D; RayTracing Context for RTU/SHG; 0x0 otherwise */
IMG_UINT32 ui32CtxPriority; /*!< Context priority */
IMG_UINT32 ui32GPUIdMask; /*!< GPU IDs active within this event */
IMG_UINT32 aui32CountBlksStream[RGX_HWPERF_ZERO_OR_MORE_ELEMENTS]; /*!< Counter data */
IMG_UINT32 ui32Padding2; /*!< Reserved. To ensure correct alignment */
IMG_UINT32 ui32KickInfo; /*!< <31..8> Reserved <7..0> GPU Pipeline DM kick ID, 0 if not using Pipeline DMs */
IMG_UINT32 ui32Padding; /*!< Reserved. To ensure correct alignment */
IMG_UINT32 aui32CountBlksStream[RGX_HWPERF_ZERO_OR_MORE_ELEMENTS]; /*!< Optional variable length Counter data */
IMG_UINT32 ui32Padding2; /*!< Reserved. To ensure correct alignment (not written in the packet) */
} RGX_HWPERF_HW_DATA;
RGX_FW_STRUCT_SIZE_ASSERT(RGX_HWPERF_HW_DATA);
RGX_FW_STRUCT_OFFSET_ASSERT(RGX_HWPERF_HW_DATA, aui32CountBlksStream);
typedef struct
{
@@ -914,6 +524,26 @@ typedef struct
RGX_FW_STRUCT_SIZE_ASSERT(RGX_HWPERF_BVNC);
/*! Performance Counter Configuration data element. */
typedef struct
{
IMG_UINT32 ui32BlockID; /*!< Counter Block ID. See RGX_HWPERF_CNTBLK_ID */
IMG_UINT32 ui32NumCounters; /*!< Number of counters configured */
IMG_UINT32 ui32CounterVals[RGX_CNTBLK_COUNTERS_MAX]; /*!< Counters configured (ui32NumCounters worth of entries) */
} RGX_HWPERF_COUNTER_CFG_DATA_EL;
RGX_FW_STRUCT_SIZE_ASSERT(RGX_HWPERF_COUNTER_CFG_DATA_EL);
/*! Performance Counter Configuration data. */
typedef struct
{
IMG_UINT32 ui32EnabledBlocks; /*!< Number of Enabled Blocks. */
RGX_HWPERF_COUNTER_CFG_DATA_EL uData; /*!< Start of variable length data. See RGX_HWPERF_COUNTER_CFG_DATA_EL */
IMG_UINT32 ui32Padding; /*!< reserved */
} RGX_HWPERF_COUNTER_CFG;
RGX_FW_STRUCT_SIZE_ASSERT(RGX_HWPERF_COUNTER_CFG);
/*! Sub-event's data. */
typedef union
{
@@ -930,7 +560,7 @@ typedef union
IMG_UINT32 ui32EvMaskLo; /*!< Low order 32 bits of Filter Mask */
IMG_UINT32 ui32EvMaskHi; /*!< High order 32 bits of Filter Mask */
} sEvMsk; /*!< HW Filter Mask */
RGX_HWPERF_COUNTER_CFG sPCC; /*!< Performance Counter Config. See RGX_HWPERF_COUNTER_CFG */
} RGX_HWPERF_FWACT_DETAIL;
RGX_FW_STRUCT_SIZE_ASSERT(RGX_HWPERF_FWACT_DETAIL);
@@ -1456,6 +1086,49 @@ typedef struct
static_assert((sizeof(RGX_HWPERF_HOST_SYNC_SW_TL_ADV_DATA) & (PVRSRVTL_PACKET_ALIGNMENT-1U)) == 0U,
"sizeof(RGX_HWPERF_HOST_SYNC_SW_TL_ADV_DATA) must be a multiple PVRSRVTL_PACKET_ALIGNMENT");
typedef enum
{
RGX_HWPERF_HOST_CLIENT_INFO_TYPE_INVALID = 0, /*!< Invalid */
RGX_HWPERF_HOST_CLIENT_INFO_TYPE_PROCESS_NAME, /*!< Process Name */
RGX_HWPERF_HOST_CLIENT_INFO_TYPE_LAST, /*!< Do not use */
} RGX_HWPERF_HOST_CLIENT_INFO_TYPE;
typedef struct
{
IMG_PID uiClientPID; /*!< Client process identifier */
IMG_UINT32 ui32Length; /*!< Number of bytes present in ``acName`` */
IMG_CHAR acName[RGX_HWPERF_ONE_OR_MORE_ELEMENTS]; /*!< Process name string, null terminated */
} RGX_HWPERF_HOST_CLIENT_PROC_NAME;
#define RGX_HWPERF_HOST_CLIENT_PROC_NAME_SIZE(ui32NameLen) \
((IMG_UINT32)(offsetof(RGX_HWPERF_HOST_CLIENT_PROC_NAME, acName) + (ui32NameLen)))
typedef union
{
struct
{
IMG_UINT32 ui32Count; /*!< Number of elements in ``asProcNames`` */
RGX_HWPERF_HOST_CLIENT_PROC_NAME asProcNames[RGX_HWPERF_ONE_OR_MORE_ELEMENTS];
} sProcName;
} RGX_HWPERF_HOST_CLIENT_INFO_DETAIL;
typedef struct
{
IMG_UINT32 uiReserved1; /*!< Reserved. Align structure size to 8 bytes */
RGX_HWPERF_HOST_CLIENT_INFO_TYPE eType;
/*!< Type of the subevent, see
RGX_HWPERF_HOST_CLIENT_INFO_TYPE */
RGX_HWPERF_HOST_CLIENT_INFO_DETAIL uDetail;
/*!< Union of structures. Size of data
varies with union member that is present,
check ``eType`` value to decode */
} RGX_HWPERF_HOST_CLIENT_INFO_DATA;
static_assert((sizeof(RGX_HWPERF_HOST_CLIENT_INFO_DATA) & (PVRSRVTL_PACKET_ALIGNMENT-1U)) == 0U,
"sizeof(RGX_HWPERF_HOST_CLIENT_INFO_DATA) must be a multiple PVRSRVTL_PACKET_ALIGNMENT");
typedef enum
{
RGX_HWPERF_RESOURCE_CAPTURE_TYPE_NONE,
@@ -1581,6 +1254,9 @@ typedef union
events ``0x09`` (Host) */
RGX_HWPERF_HOST_SYNC_SW_TL_ADV_DATA sSWTLADV; /*!< Host SW-timeline advance
data, events ``0x0A`` (Host) */
RGX_HWPERF_HOST_CLIENT_INFO_DATA sHClientInfo; /*!< Host client info,
events ``0x0B`` (Host) */
} RGX_HWPERF_V2_PACKET_DATA, *RGX_PHWPERF_V2_PACKET_DATA;
RGX_FW_STRUCT_SIZE_ASSERT(RGX_HWPERF_V2_PACKET_DATA);
@@ -1612,7 +1288,11 @@ typedef IMG_UINT32 RGX_HWPERF_CNTBLK_ID;
#define RGX_CNTBLK_ID_HUB 0x0002U /*!< Non-cluster grouping cores */
#define RGX_CNTBLK_ID_TORNADO 0x0003U /*!< XT cores */
#define RGX_CNTBLK_ID_JONES 0x0004U /*!< S7 cores */
#if defined(RGX_FEATURE_HWPERF_OCEANIC)
#define RGX_CNTBLK_ID_DIRECT_LAST 0x0003U /*!< Indirect blocks start from here */
#else
#define RGX_CNTBLK_ID_DIRECT_LAST 0x0005U /*!< Indirect blocks start from here */
#endif /* defined(RGX_FEATURE_HWPERF_OCEANIC) */
#define RGX_CNTBLK_ID_BF_DEPRECATED 0x0005U /*!< Doppler unit (DEPRECATED) */
#define RGX_CNTBLK_ID_BT_DEPRECATED 0x0006U /*!< Doppler unit (DEPRECATED) */
@@ -1747,6 +1427,19 @@ typedef IMG_UINT32 RGX_HWPERF_CNTBLK_ID;
/*! The number of layout blocks defined with configurable multiplexed
* performance counters, hence excludes custom counter blocks.
*/
#if defined(RGX_FEATURE_HWPERF_OCEANIC)
#define RGX_HWPERF_MAX_MUX_BLKS (\
(IMG_UINT32)RGX_CNTBLK_ID_DIRECT_LAST +\
RGX_CNTBLK_INDIRECT_COUNT(PBE, 0) )
#define RGX_HWPERF_MAX_DA_BLKS (\
(IMG_UINT32)RGX_CNTBLK_INDIRECT_COUNT(TPU_MCU, 0)+\
RGX_CNTBLK_INDIRECT_COUNT(USC, 0) )
#define RGX_HWPERF_MAX_DEFINED_BLKS (\
(IMG_UINT32)RGX_HWPERF_MAX_MUX_BLKS +\
RGX_HWPERF_MAX_DA_BLKS )
#else
#define RGX_HWPERF_MAX_DEFINED_BLKS (\
(IMG_UINT32)RGX_CNTBLK_ID_DIRECT_LAST +\
RGX_CNTBLK_INDIRECT_COUNT(TPU_MCU, 7)+\
@@ -1755,12 +1448,15 @@ typedef IMG_UINT32 RGX_HWPERF_CNTBLK_ID;
RGX_CNTBLK_INDIRECT_COUNT(RASTER, 3)+\
RGX_CNTBLK_INDIRECT_COUNT(BLACKPEARL, 3)+\
RGX_CNTBLK_INDIRECT_COUNT(PBE, 15) )
#define RGX_HWPERF_MAX_MUX_BLKS (\
RGX_HWPERF_MAX_DEFINED_BLKS )
#endif
static_assert(
((RGX_CNTBLK_ID_DIRECT_LAST + ((RGX_CNTBLK_ID_LAST & RGX_CNTBLK_ID_GROUP_MASK) >> RGX_CNTBLK_ID_GROUP_SHIFT)) <= RGX_HWPERF_MAX_BVNC_BLOCK_LEN),
"RGX_HWPERF_MAX_BVNC_BLOCK_LEN insufficient");
#define RGX_HWPERF_EVENT_MASK_VALUE(e) (IMG_UINT64_C(1) << (e))
#define RGX_HWPERF_EVENT_MASK_VALUE(e) (IMG_UINT64_C(1) << (IMG_UINT32)(e))
#define RGX_CUSTOM_FW_CNTRS \
X(TA_LOCAL_FL_SIZE, 0x0, RGX_HWPERF_EVENT_MASK_VALUE(RGX_HWPERF_HW_TAKICK) | \

9
drivers/gpu/drm/img-rogue/include/rogue/rgxheapconfig.h
View File

@@ -231,8 +231,13 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define RGX_FBCDC_HEAP_BASE IMG_UINT64_C(0xEC00000000)
#define RGX_FBCDC_HEAP_SIZE RGX_HEAP_SIZE_2MiB
/* 0xEC_0020_0000 - 0xED_FFFF_FFFF **/
/* 945 GiB to 952 GiB, size of 7 GiB : RESERVED VOLCANIC **/
/* 0xEC_4000_0000 - 0xEC_401F_FFFF **/
/* 945 GiB to 946 GiB, size 2 MiB : FBCDC_LARGE_HEAP **/
#define RGX_FBCDC_LARGE_HEAP_BASE IMG_UINT64_C(0xEC40000000)
#define RGX_FBCDC_LARGE_HEAP_SIZE RGX_HEAP_SIZE_2MiB
/* 0xEC_8000_0000 - 0xED_FFFF_FFFF **/
/* 946 GiB to 952 GiB, size of 6 GiB : RESERVED VOLCANIC **/
/* 0xEE_0000_0000 - 0xEE_3FFF_FFFF **/
/* 952 GiB to 953 GiB, size of 1 GiB : CMP_MISSION_RMW_HEAP **/