Linux_SDK_V1.3.3

Signed-off-by: thead_admin <occ_thead@service.alibaba.com>

Documentation/devicetree/bindings/arm/msm/qcom,idle-state.txt

@@ -81,4 +81,4 @@ Example:
 		};
 	};
 
-[1]. Documentation/devicetree/bindings/arm/idle-states.yaml
+[1]. Documentation/devicetree/bindings/cpu/idle-states.yaml

Documentation/devicetree/bindings/arm/psci.yaml

@@ -101,7 +101,7 @@ properties:
       bindings in [1]) must specify this property.
 
       [1] Kernel documentation - ARM idle states bindings
-        Documentation/devicetree/bindings/arm/idle-states.yaml
+        Documentation/devicetree/bindings/cpu/idle-states.yaml
 
 patternProperties:
   "^power-domain-":

Documentation/devicetree/bindings/cpu/idle-states.yaml

@@ -1,25 +1,30 @@
 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
 %YAML 1.2
 ---
-$id: http://devicetree.org/schemas/arm/idle-states.yaml#
+$id: http://devicetree.org/schemas/cpu/idle-states.yaml#
 $schema: http://devicetree.org/meta-schemas/core.yaml#
 
-title: ARM idle states binding description
+title: Idle states binding description
 
 maintainers:
   - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
+  - Anup Patel <anup@brainfault.org>
 
 description: |+
   ==========================================
   1 - Introduction
   ==========================================
 
-  ARM systems contain HW capable of managing power consumption dynamically,
+  ARM and RISC-V systems contain HW capable of managing power consumption
-  where cores can be put in different low-power states (ranging from simple wfi
+  dynamically, where cores can be put in different low-power states (ranging
-  to power gating) according to OS PM policies. The CPU states representing the
+  from simple wfi to power gating) according to OS PM policies. The CPU states
-  range of dynamic idle states that a processor can enter at run-time, can be
+  representing the range of dynamic idle states that a processor can enter at
-  specified through device tree bindings representing the parameters required to
+  run-time, can be specified through device tree bindings representing the
-  enter/exit specific idle states on a given processor.
+  parameters required to enter/exit specific idle states on a given processor.
+
+  ==========================================
+  2 - ARM idle states
+  ==========================================
 
   According to the Server Base System Architecture document (SBSA, [3]), the
   power states an ARM CPU can be put into are identified by the following list:
@@ -43,8 +48,23 @@ description: |+
   The device tree binding definition for ARM idle states is the subject of this
   document.
 
+  ==========================================
+  3 - RISC-V idle states
+  ==========================================
+
+  On RISC-V systems, the HARTs (or CPUs) [6] can be put in platform specific
+  suspend (or idle) states (ranging from simple WFI, power gating, etc). The
+  RISC-V SBI v0.3 (or higher) [7] hart state management extension provides a
+  standard mechanism for OS to request HART state transitions.
+
+  The platform specific suspend (or idle) states of a hart can be either
+  retentive or non-rententive in nature. A retentive suspend state will
+  preserve HART registers and CSR values for all privilege modes whereas
+  a non-retentive suspend state will not preserve HART registers and CSR
+  values.
+
   ===========================================
-  2 - idle-states definitions
+  4 - idle-states definitions
   ===========================================
 
   Idle states are characterized for a specific system through a set of
@@ -211,10 +231,10 @@ description: |+
   properties specification that is the subject of the following sections.
 
   ===========================================
-  3 - idle-states node
+  5 - idle-states node
   ===========================================
 
-  ARM processor idle states are defined within the idle-states node, which is
+  The processor idle states are defined within the idle-states node, which is
   a direct child of the cpus node [1] and provides a container where the
   processor idle states, defined as device tree nodes, are listed.
 
@@ -223,7 +243,7 @@ description: |+
   just supports idle_standby, an idle-states node is not required.
 
   ===========================================
-  4 - References
+  6 - References
   ===========================================
 
   [1] ARM Linux Kernel documentation - CPUs bindings
@@ -238,9 +258,15 @@ description: |+
   [4] ARM Architecture Reference Manuals
       http://infocenter.arm.com/help/index.jsp
 
-  [6] ARM Linux Kernel documentation - Booting AArch64 Linux
+  [5] ARM Linux Kernel documentation - Booting AArch64 Linux
       Documentation/arm64/booting.rst
 
+  [6] RISC-V Linux Kernel documentation - CPUs bindings
+      Documentation/devicetree/bindings/riscv/cpus.yaml
+
+  [7] RISC-V Supervisor Binary Interface (SBI)
+      http://github.com/riscv/riscv-sbi-doc/riscv-sbi.adoc
+
 properties:
   $nodename:
     const: idle-states
@@ -253,7 +279,7 @@ properties:
       On ARM 32-bit systems this property is optional
 
       This assumes that the "enable-method" property is set to "psci" in the cpu
-      node[6] that is responsible for setting up CPU idle management in the OS
+      node[5] that is responsible for setting up CPU idle management in the OS
       implementation.
     const: psci
 
@@ -265,8 +291,8 @@ patternProperties:
       as follows.
 
       The idle state entered by executing the wfi instruction (idle_standby
-      SBSA,[3][4]) is considered standard on all ARM platforms and therefore
+      SBSA,[3][4]) is considered standard on all ARM and RISC-V platforms and
-      must not be listed.
+      therefore must not be listed.
 
       In addition to the properties listed above, a state node may require
       additional properties specific to the entry-method defined in the
@@ -275,7 +301,27 @@ patternProperties:
 
     properties:
       compatible:
-        const: arm,idle-state
+        enum:
+          - arm,idle-state
+          - riscv,idle-state
+
+      arm,psci-suspend-param:
+        $ref: /schemas/types.yaml#/definitions/uint32
+        description: |
+          power_state parameter to pass to the ARM PSCI suspend call.
+
+          Device tree nodes that require usage of PSCI CPU_SUSPEND function
+          (i.e. idle states node with entry-method property is set to "psci")
+          must specify this property.
+
+      riscv,sbi-suspend-param:
+        $ref: /schemas/types.yaml#/definitions/uint32
+        description: |
+          suspend_type parameter to pass to the RISC-V SBI HSM suspend call.
+
+          This property is required in idle state nodes of device tree meant
+          for RISC-V systems. For more details on the suspend_type parameter
+          refer the SBI specifiation v0.3 (or higher) [7].
 
       local-timer-stop:
         description:
@@ -317,6 +363,8 @@ patternProperties:
         description:
           A string used as a descriptive name for the idle state.
 
+    additionalProperties: false
+
     required:
       - compatible
       - entry-latency-us
@@ -658,4 +706,150 @@ examples:
         };
     };
 
+  - |
+    // Example 3 (RISC-V 64-bit, 4-cpu systems, two clusters):
+
+    cpus {
+        #size-cells = <0>;
+        #address-cells = <1>;
+
+        cpu@0 {
+            device_type = "cpu";
+            compatible = "riscv";
+            reg = <0x0>;
+            riscv,isa = "rv64imafdc";
+            mmu-type = "riscv,sv48";
+            cpu-idle-states = <&CPU_RET_0_0 &CPU_NONRET_0_0
+                            &CLUSTER_RET_0 &CLUSTER_NONRET_0>;
+
+            cpu_intc0: interrupt-controller {
+                #interrupt-cells = <1>;
+                compatible = "riscv,cpu-intc";
+                interrupt-controller;
+            };
+        };
+
+        cpu@1 {
+            device_type = "cpu";
+            compatible = "riscv";
+            reg = <0x1>;
+            riscv,isa = "rv64imafdc";
+            mmu-type = "riscv,sv48";
+            cpu-idle-states = <&CPU_RET_0_0 &CPU_NONRET_0_0
+                            &CLUSTER_RET_0 &CLUSTER_NONRET_0>;
+
+            cpu_intc1: interrupt-controller {
+                #interrupt-cells = <1>;
+                compatible = "riscv,cpu-intc";
+                interrupt-controller;
+            };
+        };
+
+        cpu@10 {
+            device_type = "cpu";
+            compatible = "riscv";
+            reg = <0x10>;
+            riscv,isa = "rv64imafdc";
+            mmu-type = "riscv,sv48";
+            cpu-idle-states = <&CPU_RET_1_0 &CPU_NONRET_1_0
+                            &CLUSTER_RET_1 &CLUSTER_NONRET_1>;
+
+            cpu_intc10: interrupt-controller {
+                #interrupt-cells = <1>;
+                compatible = "riscv,cpu-intc";
+                interrupt-controller;
+            };
+        };
+
+        cpu@11 {
+            device_type = "cpu";
+            compatible = "riscv";
+            reg = <0x11>;
+            riscv,isa = "rv64imafdc";
+            mmu-type = "riscv,sv48";
+            cpu-idle-states = <&CPU_RET_1_0 &CPU_NONRET_1_0
+                            &CLUSTER_RET_1 &CLUSTER_NONRET_1>;
+
+            cpu_intc11: interrupt-controller {
+                #interrupt-cells = <1>;
+                compatible = "riscv,cpu-intc";
+                interrupt-controller;
+            };
+        };
+
+        idle-states {
+            CPU_RET_0_0: cpu-retentive-0-0 {
+                compatible = "riscv,idle-state";
+                riscv,sbi-suspend-param = <0x10000000>;
+                entry-latency-us = <20>;
+                exit-latency-us = <40>;
+                min-residency-us = <80>;
+            };
+
+            CPU_NONRET_0_0: cpu-nonretentive-0-0 {
+                compatible = "riscv,idle-state";
+                riscv,sbi-suspend-param = <0x90000000>;
+                entry-latency-us = <250>;
+                exit-latency-us = <500>;
+                min-residency-us = <950>;
+            };
+
+            CLUSTER_RET_0: cluster-retentive-0 {
+                compatible = "riscv,idle-state";
+                riscv,sbi-suspend-param = <0x11000000>;
+                local-timer-stop;
+                entry-latency-us = <50>;
+                exit-latency-us = <100>;
+                min-residency-us = <250>;
+                wakeup-latency-us = <130>;
+            };
+
+            CLUSTER_NONRET_0: cluster-nonretentive-0 {
+                compatible = "riscv,idle-state";
+                riscv,sbi-suspend-param = <0x91000000>;
+                local-timer-stop;
+                entry-latency-us = <600>;
+                exit-latency-us = <1100>;
+                min-residency-us = <2700>;
+                wakeup-latency-us = <1500>;
+            };
+
+            CPU_RET_1_0: cpu-retentive-1-0 {
+                compatible = "riscv,idle-state";
+                riscv,sbi-suspend-param = <0x10000010>;
+                entry-latency-us = <20>;
+                exit-latency-us = <40>;
+                min-residency-us = <80>;
+            };
+
+            CPU_NONRET_1_0: cpu-nonretentive-1-0 {
+                compatible = "riscv,idle-state";
+                riscv,sbi-suspend-param = <0x90000010>;
+                entry-latency-us = <250>;
+                exit-latency-us = <500>;
+                min-residency-us = <950>;
+            };
+
+            CLUSTER_RET_1: cluster-retentive-1 {
+                compatible = "riscv,idle-state";
+                riscv,sbi-suspend-param = <0x11000010>;
+                local-timer-stop;
+                entry-latency-us = <50>;
+                exit-latency-us = <100>;
+                min-residency-us = <250>;
+                wakeup-latency-us = <130>;
+            };
+
+            CLUSTER_NONRET_1: cluster-nonretentive-1 {
+                compatible = "riscv,idle-state";
+                riscv,sbi-suspend-param = <0x91000010>;
+                local-timer-stop;
+                entry-latency-us = <600>;
+                exit-latency-us = <1100>;
+                min-residency-us = <2700>;
+                wakeup-latency-us = <1500>;
+            };
+        };
+    };
+
 ...

Documentation/devicetree/bindings/riscv/cpus.yaml

@@ -87,6 +87,12 @@ properties:
       - compatible
       - interrupt-controller
 
+  cpu-idle-states:
+    $ref: '/schemas/types.yaml#/definitions/phandle-array'
+    description: |
+      List of phandles to idle state nodes supported
+      by this hart (see ./idle-states.yaml).
+
 required:
   - riscv,isa
   - interrupt-controller

MAINTAINERS

@@ -4614,6 +4614,20 @@ S:	Supported
 F:	drivers/cpuidle/cpuidle-psci.h
 F:	drivers/cpuidle/cpuidle-psci-domain.c
 
+CPUIDLE DRIVER - DT IDLE PM DOMAIN
+M:	Ulf Hansson <ulf.hansson@linaro.org>
+L:	linux-pm@vger.kernel.org
+S:	Supported
+F:	drivers/cpuidle/dt_idle_genpd.c
+F:	drivers/cpuidle/dt_idle_genpd.h
+
+CPUIDLE DRIVER - RISC-V SBI
+M:	Anup Patel <anup@brainfault.org>
+L:	linux-pm@vger.kernel.org
+L:	linux-riscv@lists.infradead.org
+S:	Maintained
+F:	drivers/cpuidle/cpuidle-riscv-sbi.c
+
 CRAMFS FILESYSTEM
 M:	Nicolas Pitre <nico@fluxnic.net>
 S:	Maintained

arch/riscv/Kconfig

@@ -21,7 +21,6 @@ config RISCV
 	select ARCH_HAS_GCOV_PROFILE_ALL
 	select ARCH_HAS_GIGANTIC_PAGE
 	select ARCH_HAS_KCOV
-	select ARCH_HAS_MMIOWB
 	select ARCH_HAS_PTE_SPECIAL
 	select ARCH_HAS_SET_DIRECT_MAP
 	select ARCH_HAS_SET_MEMORY
@@ -32,15 +31,18 @@ config RISCV
 	select ARCH_HAS_SYNC_DMA_FOR_DEVICE
 	select ARCH_HAS_DMA_WRITE_COMBINE
 	select ARCH_HAS_DMA_MMAP_PGPROT
+	select ARCH_KEEP_MEMBLOCK
 	select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX
 	select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT
+	select ARCH_USE_QUEUED_SPINLOCKS
+	select ARCH_USE_QUEUED_RWLOCKS
 	select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU
 	select ARCH_WANT_FRAME_POINTERS
 	select ARCH_WANT_HUGE_PMD_SHARE if 64BIT
 	select CLONE_BACKWARDS
 	select CLINT_TIMER if !MMU
 	select COMMON_CLK
-	select CPU_PM if (SUSPEND || CPU_IDLE)
+	select CPU_PM if CPU_IDLE
 	select COMPAT_BINFMT_ELF if BINFMT_ELF && COMPAT
 	select EDAC_SUPPORT
 	select DMA_DIRECT_REMAP
@@ -360,6 +362,8 @@ config RISCV_ISA_C
 
 config NO_SFENCE_VMA
 	bool "Replace sfence.vma with CSR_SMCIR operation"
+	depends on !SMP
+	default y
 
 config RISCV_SWIOTLB
 	bool "Enable SWIOTLB"
@@ -571,5 +575,11 @@ config ARCH_SUSPEND_POSSIBLE
 
 endmenu
 
+menu "CPU Power Management"
+
+source "drivers/cpuidle/Kconfig"
+
+endmenu
+
 source "arch/riscv/kvm/Kconfig"
 source "drivers/firmware/Kconfig"

arch/riscv/Kconfig.socs

@@ -19,6 +19,9 @@ config SOC_VIRT
 	select GOLDFISH
 	select RTC_DRV_GOLDFISH if RTC_CLASS
 	select SIFIVE_PLIC
+	select PM_GENERIC_DOMAINS if PM
+	select PM_GENERIC_DOMAINS_OF if PM && OF
+	select RISCV_SBI_CPUIDLE if CPU_IDLE
 	help
 	  This enables support for QEMU Virt Machine.
 

arch/riscv/boot/dts/thead/Makefile

@@ -4,7 +4,7 @@ dtb-$(CONFIG_SOC_THEAD) += light-fm-emu.dtb light_mpw.dtb
 dtb-$(CONFIG_SOC_THEAD) += light-fm-emu-npu-fce.dtb
 dtb-$(CONFIG_SOC_THEAD) += light-fm-emu-gpu.dtb
 dtb-$(CONFIG_SOC_THEAD) += light-fm-emu-dsp.dtb
-dtb-$(CONFIG_SOC_THEAD) += light-fm-emu-audio.dtb
+dtb-$(CONFIG_SOC_THEAD) += light-fm-emu-audio.dtb light-a-val-audio-hdmi.dtb
 dtb-$(CONFIG_SOC_THEAD) += light-fm-emu-hdmi.dtb
 dtb-$(CONFIG_SOC_THEAD) += light-fm-emu-dsi0-hdmi.dtb
 dtb-$(CONFIG_SOC_THEAD) += light-a-val.dtb light-a-val-sv.dtb
@@ -12,24 +12,31 @@ dtb-$(CONFIG_SOC_THEAD) += light-a-val-ddr2G.dtb light-a-val-ddr1G.dtb
 dtb-$(CONFIG_SOC_THEAD) += light-a-val-npu-fce.dtb
 dtb-$(CONFIG_SOC_THEAD) += light-a-val-iso7816.dtb
 dtb-$(CONFIG_SOC_THEAD) += light-a-val-nand.dtb
-dtb-$(CONFIG_SOC_THEAD) += light-a-val-audio.dtb
+dtb-$(CONFIG_SOC_THEAD) += light-a-val-audio.dtb light-a-val-audio-i2s-8ch.dtb
-dtb-$(CONFIG_SOC_THEAD) += light-a-val-dsi0.dtb light-a-val-dsi1.dtb light-a-val-hdmi.dtb light-a-val-dsi0-dsi1.dtb light-a-val-dsi0-hdmi.dtb light-a-val-dpi0.dtb light-a-val-dpi0-dpi1.dtb
+dtb-$(CONFIG_SOC_THEAD) += light-a-val-audio-tdm.dtb
+dtb-$(CONFIG_SOC_THEAD) += light-a-val-audio-spdif.dtb
+dtb-$(CONFIG_SOC_THEAD) += light-a-val-dsi0.dtb light-a-val-dsi1.dtb light-a-val-hdmi.dtb light-a-val-dsi0-dsi1.dtb light-a-val-dsi0-hdmi.dtb light-a-val-dsi0-hdmi-audio.dtb light-a-val-dpi0.dtb light-a-val-dpi0-dpi1.dtb
 dtb-$(CONFIG_SOC_THEAD) += light-a-val-wcn.dtb
 dtb-$(CONFIG_SOC_THEAD) += light-a-val-gpio-keys.dtb
 dtb-$(CONFIG_SOC_THEAD) += light-a-val-khv.dtb
 dtb-$(CONFIG_SOC_THEAD) += light-a-val-sec.dtb
 dtb-$(CONFIG_SOC_THEAD) += light-a-val-miniapp-hdmi.dtb
 dtb-$(CONFIG_SOC_THEAD) += light-a-product.dtb
-dtb-$(CONFIG_SOC_THEAD) += light-b-product.dtb
+dtb-$(CONFIG_SOC_THEAD) += light-b-product.dtb light-b-product-sec.dtb
 dtb-$(CONFIG_SOC_THEAD) += light-b-product-ddr1G.dtb
 dtb-$(CONFIG_SOC_THEAD) += light-b-product-miniapp-hdmi.dtb
 dtb-$(CONFIG_SOC_THEAD) += light-a-val-full.dtb
 dtb-$(CONFIG_SOC_THEAD) += light-ant-ref.dtb
 dtb-$(CONFIG_SOC_THEAD) += light-ant-discrete.dtb
 dtb-$(CONFIG_SOC_THEAD) += light-beagle.dtb
+dtb-$(CONFIG_SOC_THEAD) += light-lpi4a.dtb light-lpi4a-ddr2G.dtb
 dtb-$(CONFIG_SOC_THEAD) += light-a-ref.dtb light-a-ref-dsi0.dtb light-a-ref-dsi0-hdmi.dtb
 dtb-$(CONFIG_SOC_THEAD) += light-b-ref.dtb
-dtb-$(CONFIG_SOC_THEAD) += light-a-val-crash.dtb light-b-product-crash.dtb light-ant-ref-crash.dtb light-ant-discrete-crash.dtb
+dtb-$(CONFIG_SOC_THEAD) += light-a-val-crash.dtb light-b-product-crash.dtb light-ant-ref-crash.dtb light-ant-discrete-crash.dtb light-lpi4a-crash.dtb light-lpi4a-camera-tuning.dtb light-lpi4a-hdmi.dtb
 dtb-$(CONFIG_SOC_THEAD) += light-b-power.dtb
 
 dtb-$(CONFIG_SOC_THEAD) += light-a-val-android.dtb
+
+dtb-$(CONFIG_SOC_THEAD) += fire-emu.dtb fire-emu-crash.dtb
+dtb-$(CONFIG_SOC_THEAD) += fire-emu-soc-base.dtb fire-emu-soc-c910x4.dtb fire-emu-gpu-dpu-dsi0.dtb fire-emu-vi-dsp-vo.dtb fire-emu-vi-vp-vo.dtb
+dtb-$(CONFIG_SOC_THEAD) += fire-emu-soc-base-sec.dtb

arch/riscv/boot/dts/thead/fire-crash.dts

@@ -0,0 +1,847 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2021-2022 Alibaba Group Holding Limited.
+ */
+
+/dts-v1/;
+
+#include "fire.dtsi"
+#include <dt-bindings/input/linux-event-codes.h>
+#include <dt-bindings/gpio/gpio.h>
+#include "light-vi-devices.dtsi"
+
+/ {
+	model = "T-HEAD fire fpga board";
+	compatible = "thead,fire-emu", "thead,fire";
+
+	chosen {
+		bootargs = "console=ttyS0,115200 earlycon";
+		stdout-path = "serial0:115200n8";
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		status = "disabled";
+		led0 {
+			label = "SYS_STATUS";
+			gpios = <&gpio1_porta 15 0>;	/* GPIO_ACTIVE_HIGH: 0 */
+			default-state = "off";
+		};
+	};
+
+	display-subsystem {
+		status = "okay";
+	};
+
+	lcd0_backlight: pwm-backlight@0 {
+		status = "disabled";
+		compatible = "pwm-backlight";
+		pwms = <&pwm 0 5000000>;
+		brightness-levels = <0 4 8 16 32 64 128 255>;
+		default-brightness-level = <7>;
+	};
+
+	light_iopmp: iopmp {
+		status = "disabled";
+		compatible = "thead,light-iopmp";
+
+		/* config#1: multiple valid regions */
+		iopmp_emmc: IOPMP_EMMC {
+			regions = <0x000000 0x100000>,
+				  <0x100000 0x200000>;
+			attr = <0xFFFFFFFF>;
+			dummy_slave= <0x800000>;
+		};
+
+		/* config#2: iopmp bypass */
+		iopmp_sdio0: IOPMP_SDIO0 {
+			bypass_en;
+		};
+
+		/* config#3: iopmp default region set */
+		iopmp_sdio1: IOPMP_SDIO1 {
+			attr = <0xFFFFFFFF>;
+			is_default_region;
+		};
+
+		iopmp_usb0: IOPMP_USB0 {
+			attr = <0xFFFFFFFF>;
+			is_default_region;
+		};
+
+		iopmp_ao: IOPMP_AO {
+			is_default_region;
+		};
+
+		iopmp_aud: IOPMP_AUD {
+			is_default_region;
+		};
+
+		iopmp_chip_dbg: IOPMP_CHIP_DBG {
+			is_default_region;
+		};
+
+		iopmp_eip120i: IOPMP_EIP120I {
+			is_default_region;
+		};
+
+		iopmp_eip120ii: IOPMP_EIP120II {
+			is_default_region;
+		};
+
+		iopmp_eip120iii: IOPMP_EIP120III {
+			is_default_region;
+		};
+
+		iopmp_isp0: IOPMP_ISP0 {
+			is_default_region;
+		};
+
+		iopmp_isp1: IOPMP_ISP1 {
+			is_default_region;
+		};
+
+		iopmp_dw200: IOPMP_DW200 {
+			is_default_region;
+		};
+
+		iopmp_vipre: IOPMP_VIPRE {
+			is_default_region;
+		};
+
+		iopmp_venc: IOPMP_VENC {
+			is_default_region;
+		};
+
+		iopmp_vdec: IOPMP_VDEC {
+			is_default_region;
+		};
+
+		iopmp_g2d: IOPMP_G2D {
+			is_default_region;
+		};
+
+		iopmp0_dpu: IOPMP0_DPU {
+			bypass_en;
+		};
+
+		iopmp1_dpu: IOPMP1_DPU {
+			bypass_en;
+		};
+
+		iopmp_gpu: IOPMP_GPU {
+			is_default_region;
+		};
+
+		iopmp_gmac1: IOPMP_GMAC1 {
+			is_default_region;
+		};
+
+		iopmp_gmac2: IOPMP_GMAC2 {
+			is_default_region;
+		};
+
+		iopmp_dmac: IOPMP_DMAC {
+			is_default_region;
+		};
+
+		iopmp_tee_dmac: IOPMP_TEE_DMAC {
+			is_default_region;
+		};
+
+		iopmp_dsp0: IOPMP_DSP0 {
+			is_default_region;
+		};
+
+		iopmp_dsp1: IOPMP_DSP1 {
+			is_default_region;
+		};
+	};
+
+	mbox_910t_client1: mbox_910t_client1 {
+		compatible = "thead,light-mbox-client";
+		mbox-names = "902";
+		mboxes = <&mbox_910t 1 0>;
+		status = "disabled";
+	};
+
+
+	mbox_910t_client2: mbox_910t_client2 {
+		compatible = "thead,light-mbox-client";
+		mbox-names = "906";
+		mboxes = <&mbox_910t 2 0>;
+		status = "disabled";
+	};
+
+	lightsound: lightsound@1 {
+		compatible = "simple-audio-card";
+		simple-audio-card,name = "Light-Sound-Card";
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		status = "disabled";
+	};
+
+	dummy_codec: dummy_codec {
+		#sound-dai-cells = <1>;
+		compatible = "linux,bt-sco";
+		status = "okay";
+	};
+
+
+	wcn_wifi: wireless-wlan {
+		compatible = "wlan-platdata";
+		clock-names = "clk_wifi";
+		ref-clock-frequency = <24000000>;
+		keep_wifi_power_on;
+		pinctrl-names = "default";
+		wifi_chip_type = "rtl8723ds";
+		WIFI,poweren_gpio = <&gpio2_porta 26 0>;
+		WIFI,reset_n = <&gpio2_porta 28 0>;
+		status = "disabled";
+	};
+
+	wcn_bt: wireless-bluetooth {
+		compatible = "bluetooth-platdata";
+		pinctrl-names = "default", "rts_gpio";
+		BT,power_gpio    = <&gpio2_porta 29 0>;
+		status = "disabled";
+	};
+
+	gpio_keys: gpio_keys{
+		compatible = "gpio-keys";
+		pinctrl-names = "default";
+		status = "disabled";
+		key-volumedown {
+			label = "Volume Down Key";
+			linux,code = <KEY_1>;
+			debounce-interval = <2>;
+			gpios = <&ao_gpio_porta 4 GPIO_ACTIVE_LOW>;
+		};
+		key-volumeup {
+			label = "Volume Up Key";
+			linux,code = <KEY_2>;
+			debounce-interval = <2>;
+			gpios = <&ao_gpio_porta 5 GPIO_ACTIVE_LOW>;
+		};
+	};
+
+	aon: light-aon {
+		compatible = "thead,light-aon";
+		mbox-names = "aon";
+		mboxes = <&mbox_910t 1 0>;
+		status = "disabled";
+
+		pd: light-aon-pd {
+			compatible = "thead,light-aon-pd";
+			#power-domain-cells = <1>;
+			status = "disabled";
+		};
+
+		aon_reg_dialog: light-dialog-reg {
+			compatible = "thead,light-dialog-pmic";
+			status = "disabled";
+		};
+
+		c910_cpufreq {
+			compatible = "thead,light-mpw-cpufreq";
+			status = "disabled";
+		};
+
+		test: light-aon-test {
+			compatible = "thead,light-aon-test";
+			status = "disabled";
+		};
+	};
+};
+
+&resmem {
+	#address-cells = <2>;
+	#size-cells = <2>;
+	ranges;
+
+	tee_mem: memory@1a000000 {
+		reg = <0x0 0x1a000000 0 0x4000000>;
+		no-map;
+	};
+	dsp0_mem: memory@20000000 {			/**0x2000_0000~0x2040_0000 4M**/
+		reg = <0x0 0x20000000 0x0 0x00280000	/* DSP FW code&data section 2.5M*/
+		       0x0 0x20280000 0x0 0x00001000	/* DSP communication area 4K*/
+		       0x0 0x20281000 0x0 0x00007000	/* Panic/log page 28K */
+		       0x0 0x20288000 0x0 0x00178000>;	/* DSP shared memory 1.5M-32K*/
+		no-map;
+	};
+	dsp1_mem: memory@20400000 {			/**0x2040_0000~0x2080_0000 4M**/
+		reg = <0x0 0x20400000 0x0 0x00280000	/* DSP FW code&data section */
+		       0x0 0x20680000 0x0 0x00001000	/* DSP communication area */
+		       0x0 0x20681000 0x0 0x00007000	/* Panic/log page*/
+		       0x0 0x20688000 0x0 0x00178000>;	/* DSP shared memory */
+		no-map;
+	};
+    vi_mem: framebuffer@0f800000 {
+		reg = <0x0 0x0F800000 0x0 0x05400000	/* vi_mem_pool_region[0]  84 MB (default) */
+		       0x0 0x14C00000 0x0 0x01D00000	/* vi_mem_pool_region[1]  29 MB */
+		       0x0 0x16900000 0x0 0x03200000>;	/* vi_mem_pool_region[2]  50 MB */
+		no-map;
+	};
+	facelib_mem: memory@22000000 {
+		reg = <0x0 0x22000000 0x0 0x10000000>;
+		no-map;
+	};
+
+};
+
+&clk {
+	status = "disabled";
+};
+
+&i2c0 {
+	clock-frequency = <400000>;
+	status = "okay";
+
+	eeprom@50 {
+		compatible = "atmel,24c32";
+		reg = <0x50>;
+		pagesize = <32>;
+	};
+
+       touch@5d {
+               #gpio-cells = <2>;
+               compatible = "goodix,gt911";
+			   status = "disabled";
+               reg = <0x5d>;
+               interrupt-parent = <&gpio1_porta>;
+               interrupts = <8 0>;
+               irq-gpios = <&gpio1_porta 8 0>;
+               reset-gpios = <&gpio1_porta 7 0>;
+               touchscreen-size-x = <800>;
+               touchscreen-size-y = <1280>;
+       };
+};
+
+&audio_i2c0 {
+        clock-frequency = <100000>;
+        status = "disabled";
+
+       es8156_audio_codec: es8156@8 {
+               #sound-dai-cells = <0>;
+               compatible = "everest,es8156";
+               reg = <0x08>;
+       };
+
+        es7210_audio_codec: es7210@40 {
+                #sound-dai-cells = <0>;
+                compatible = "MicArray_0";
+                reg = <0x40>;
+        };
+};
+
+&i2c1 {
+        clock-frequency = <400000>;
+        status = "disabled";
+        touch1@5d {
+                #gpio-cells = <2>;
+                compatible = "goodix,gt911";
+                reg = <0x5d>;
+                interrupt-parent = <&gpio1_porta>;
+                interrupts = <12 0>;
+                irq-gpios = <&gpio1_porta 12 0>;
+                reset-gpios = <&gpio1_porta 11 0>;
+                touchscreen-size-x = <800>;
+                touchscreen-size-y = <1280>;
+        };
+};
+
+&spi0 {
+	num-cs = <1>;
+	cs-gpios = <&gpio2_porta 15 0>; // GPIO_ACTIVE_HIGH: 0
+	rx-sample-delay-ns = <10>;
+	status = "okay";
+
+	spi_norflash@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "winbond,w25q64jwm", "jedec,spi-nor";
+		reg = <0>;
+		spi-max-frequency = <50000000>;
+		w25q,fast-read;
+		status = "disabled";
+	};
+
+	spidev@1 {
+		compatible = "spidev";
+		#address-cells = <0x1>;
+		#size-cells = <0x1>;
+		reg = <0x1>;
+		spi-max-frequency = <50000000>;
+	};
+};
+
+&qspi0 {
+	num-cs = <1>;
+	cs-gpios = <&gpio2_porta 3 0>;
+	rx-sample-dly = <4>;
+	status = "disabled";
+
+	spi-flash@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "spi-nand";
+		spi-max-frequency = <100000000>;
+		spi-tx-bus-width = <4>;
+		spi-rx-bus-width = <4>;
+		reg = <0>;
+
+		partition@0 {
+			label = "ubi1";
+			reg = <0x00000000 0x08000000>;
+		};
+	};
+};
+
+&qspi1 {
+	num-cs = <1>;
+	cs-gpios = <&gpio0_porta 1 0>;
+	status = "disabled";
+
+	spi-flash@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "spi-nand";
+		spi-max-frequency = <66000000>;
+		spi-tx-bus-width = <4>;
+		spi-rx-bus-width = <4>;
+		reg = <0>;
+
+		partition@0 {
+			label = "ubi2";
+			reg = <0x00000000 0x08000000>;
+		};
+	};
+};
+
+&gmac0 {
+	phy-mode = "rgmii-id";
+	rx-clk-delay = <0x00>; /* for RGMII */
+	tx-clk-delay = <0x00>; /* for RGMII */
+	phy-handle = <&phy_88E1111_0>;
+	status = "okay";
+
+	mdio0 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "snps,dwmac-mdio";
+
+		phy_88E1111_0: ethernet-phy@0 {
+			reg = <0x1>;
+		};
+
+		phy_88E1111_1: ethernet-phy@1 {
+			reg = <0x2>;
+		};
+	};
+};
+
+&emmc {
+	max-frequency = <198000000>;
+	non-removable;
+	mmc-hs400-1_8v;
+	io_fixed_1v8;
+	is_emmc;
+	no-sdio;
+	no-sd;
+	pull_up;
+	bus-width = <8>;
+	status = "okay";
+};
+
+&sdhci0 {
+	max-frequency = <198000000>;
+	bus-width = <4>;
+	pull_up;
+	wprtn_ignore;
+	status = "okay";
+};
+
+&sdhci1 {
+	max-frequency = <100000000>;
+	bus-width = <4>;
+	pull_up;
+	no-sd;
+	no-mmc;
+	non-removable;
+	io_fixed_1v8;
+	post-power-on-delay-ms = <50>;
+	wprtn_ignore;
+	cap-sd-highspeed;
+	keep-power-in-suspend;
+	wakeup-source;
+	status = "disabled";
+};
+
+&padctrl0_apsys { /* right-pinctrl */
+	light-evb-padctrl0 {
+			/*
+			 * Pin Configuration Node:
+			 * Format: <pin_id mux_node config>
+			 */
+			pinctrl_uart0: uart0grp {
+				thead,pins = <
+					FM_UART0_TXD	0x0	0x72
+					FM_UART0_RXD	0x0	0x72
+				>;
+			};
+
+			pinctrl_spi0: spi0grp {
+				thead,pins = <
+					FM_SPI_CSN	0x3	0x20a
+					FM_SPI_SCLK	0x0	0x20a
+					FM_SPI_MISO	0x0	0x23a
+					FM_SPI_MOSI	0x0	0x23a
+				>;
+			};
+
+			pinctrl_qspi0: qspi0grp {
+				thead,pins = <
+					FM_QSPI0_SCLK    0x0    0x20f
+					FM_QSPI0_CSN0    0x3    0x20f
+					FM_QSPI0_CSN1    0x0    0x20f
+					FM_QSPI0_D0_MOSI 0x0    0x23f
+					FM_QSPI0_D1_MISO 0x0    0x23f
+					FM_QSPI0_D2_WP   0x0    0x23f
+					FM_QSPI0_D3_HOLD 0x0    0x23f
+				>;
+			};
+
+			pinctrl_light_i2s0: i2s0grp {
+				thead,pins = <
+					FM_QSPI0_SCLK    0x2    0x208
+					FM_QSPI0_CSN0    0x2    0x238
+					FM_QSPI0_CSN1    0x2    0x208
+					FM_QSPI0_D0_MOSI 0x2    0x238
+					FM_QSPI0_D1_MISO 0x2    0x238
+					FM_QSPI0_D2_WP   0x2    0x238
+					FM_QSPI0_D3_HOLD 0x2    0x238
+				>;
+			};
+
+			pinctrl_pwm: pwmgrp {
+				thead,pins = <
+					FM_GPIO3_2	0x1	0x208	/* pwm0 */
+					FM_GPIO3_3	0x1	0x208	/* pwm1 */
+				>;
+			};
+		};
+};
+
+&padctrl1_apsys { /* left-pinctrl */
+	light-evb-padctrl1 {
+			/*
+			 * Pin Configuration Node:
+			 * Format: <pin_id mux_node config>
+			 */
+			pinctrl_uart3: uart3grp {
+				thead,pins = <
+					FM_UART3_TXD	0x0	0x72
+					FM_UART3_RXD	0x0	0x72
+				>;
+			};
+
+			pinctrl_uart4: uart4grp {
+				thead,pins = <
+					FM_UART4_TXD	0x0	0x72
+					FM_UART4_RXD	0x0	0x72
+					FM_UART4_CTSN	0x0	0x72
+					FM_UART4_RTSN	0x0	0x72
+				>;
+			};
+
+			pinctrl_qspi1: qspi1grp {
+				thead,pins = <
+					FM_QSPI1_SCLK    0x0    0x20a
+					FM_QSPI1_CSN0    0x3    0x20a
+					FM_QSPI1_D0_MOSI 0x0    0x23a
+					FM_QSPI1_D1_MISO 0x0    0x23a
+					FM_QSPI1_D2_WP   0x0    0x23a
+					FM_QSPI1_D3_HOLD 0x0    0x23a
+				>;
+			};
+
+
+			pinctrl_iso7816: iso7816grp {
+				thead,pins = <
+					FM_QSPI1_SCLK		0x1	0x208
+					FM_QSPI1_D0_MOSI	0x1	0x238
+					FM_QSPI1_D1_MISO	0x1	0x238
+					FM_QSPI1_D2_WP		0x1	0x238
+					FM_QSPI1_D3_HOLD	0x1	0x238
+				>;
+			};
+
+		};
+};
+
+&i2c2 {
+    clock-frequency = <400000>;
+	status = "okay";
+	eeprom@50 {
+		compatible = "atmel,24c32";
+		reg = <0x50>;
+		pagesize = <32>;
+	};
+};
+
+&i2c3 {
+    clock-frequency = <400000>;
+	status = "okay";
+	eeprom@50 {
+		compatible = "atmel,24c32";
+		reg = <0x50>;
+		pagesize = <32>;
+	};
+};
+
+&i2c4 {
+    clock-frequency = <400000>;
+	status = "okay";
+	eeprom@50 {
+		compatible = "atmel,24c32";
+		reg = <0x50>;
+		pagesize = <32>;
+	};
+
+	pcal6408ahk_a: gpio@20 {
+		compatible = "nxp,pcal9554b";
+		reg = <0x20>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+};
+
+&isp0 {
+	status = "disabled";
+};
+
+&isp1 {
+	status = "disabled";
+};
+
+&isp_ry0 {
+	status = "disabled";
+};
+
+&dewarp {
+	status = "disabled";
+};
+
+&dec400_isp0 {
+	status = "disabled";
+};
+
+&dec400_isp1 {
+	status = "disabled";
+};
+
+&dec400_isp2 {
+	status = "disabled";
+};
+
+&bm_visys {
+	status = "disabled";
+};
+
+&bm_csi0 {
+	status = "disabled";
+};
+
+&bm_csi1 {
+	status = "disabled";
+};
+
+&bm_csi2 {
+	status = "disabled";
+};
+
+&vi_pre {
+	//vi_pre_irq_en = <1>;
+	status = "disabled";
+};
+
+&xtensa_dsp {
+	status = "disabled";
+};
+
+&xtensa_dsp0 {
+	status = "disabled";
+    memory-region = <&dsp0_mem>;
+};
+
+&xtensa_dsp1{
+    status = "disabled";
+    memory-region = <&dsp1_mem>;
+};
+
+&vvcam_flash_led0{
+    flash_led_name = "aw36413_aw36515";
+	floodlight_i2c_bus = /bits/ 8 <2>;
+	floodlight_en_pin = <&gpio1_porta 25 0>;
+	//projection_i2c_bus = /bits/ 8 <2>;
+	flash_led_touch_pin = <&gpio1_porta 27 0>; //flash led touch pin
+	status = "disabled";
+};
+
+&vvcam_sensor1 {
+	status = "disabled";
+};
+
+&vvcam_sensor2 {
+	status = "disabled";
+};
+
+&vvcam_sensor3 {
+	status = "disabled";
+};
+
+&vvcam_sensor4 {
+    status = "disabled";
+};
+
+&vvcam_sensor5 {
+    status = "disabled";
+};
+
+&video0{
+	status = "disabled";
+};
+
+
+&video1{
+	status = "disabled";
+};
+
+&video2{
+	status = "disabled";
+};
+
+&video3{
+	status = "disabled";
+};
+
+&video4{
+	status = "disabled";
+};
+
+&video5{
+	status = "disabled";
+};
+
+&video6{
+	status = "disabled";
+};
+
+&video7{
+	status = "disabled";
+};
+
+
+&video8{
+	status = "disabled";
+};
+
+&video9{
+	status = "disabled";
+};
+
+
+&video10{
+	status = "disabled";
+};
+
+&video11{
+	status = "disabled";
+};
+
+&video12{
+	status = "disabled";
+};
+
+&trng {
+	status = "disabled";
+};
+
+&eip_28 {
+	status = "disabled";
+};
+
+&vdec {
+	status = "disabled";
+};
+
+&venc {
+	status = "disabled";
+};
+
+&isp_venc_shake {
+	status = "disabled";
+};
+
+&vidmem {
+	status = "disabled";
+};
+
+&gpu {
+	status = "disabled";
+};
+
+&dpu_enc0 {
+	status = "disabled";
+};
+
+&dpu_enc1 {
+	status = "disabled";
+};
+
+&dpu {
+        status = "disabled";
+};
+
+&dsi0 {
+        status = "disabled";
+};
+
+&dhost_0 {
+	status = "disabled";
+};
+
+&disp1_out {
+	status = "disabled";
+};
+
+&hdmi_tx {
+	status = "disabled";
+};
+
+&lightsound {
+        status = "disabled";
+};
+
+&light_i2s {
+        status = "disabled";
+};
+
+&i2s0 {
+        status = "disabled";
+};
+
+&i2s1 {
+        status = "disabled";
+};
+
+&i2s3 {
+        status = "disabled";
+};
+
+&khvhost {
+	status = "disabled";
+};

arch/riscv/boot/dts/thead/fire-emu-crash.dts

@@ -0,0 +1,98 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2021 Alibaba Group Holding Limited.
+ */
+
+#include "fire-crash.dts"
+
+&aon {
+	aon_reg_dialog: light-dialog-reg {
+		compatible = "thead,light-dialog-pmic";
+		status = "disabled";
+
+		dvdd_cpu_reg: appcpu_dvdd {
+			regulator-name = "appcpu_dvdd";
+			regulator-min-microvolt = <600000>;
+			regulator-max-microvolt = <1500000>;
+			regulator-boot-on;
+			regulator-always-on;
+		};
+
+		dvddm_cpu_reg: appcpu_dvddm {
+			regulator-name = "appcpu_dvddm";
+			regulator-min-microvolt = <600000>;
+			regulator-max-microvolt = <1500000>;
+			regulator-boot-on;
+			regulator-always-on;
+		};
+	};
+};
+
+&cpus {
+	c910_0: cpu@0 {
+		operating-points = <
+			/* kHz    uV */
+			300000	600000
+			800000	700000
+			1500000	800000
+			1848000 1000000
+		>;
+		light,dvddm-operating-points = <
+			/* kHz   uV */
+			300000	800000
+			800000	800000
+			1500000	800000
+			1848000 1000000
+		>;
+	};
+	c910_1: cpu@1 {
+		operating-points = <
+			/* kHz    uV */
+			300000	600000
+			800000	700000
+			1500000	800000
+			1848000 1000000
+		>;
+		light,dvddm-operating-points = <
+			/* kHz   uV */
+			300000	800000
+			800000	800000
+			1500000	800000
+			1848000 1000000
+		>;
+	};
+	c910_2: cpu@2 {
+
+		operating-points = <
+			/* kHz    uV */
+			300000	600000
+			800000	700000
+			1500000	800000
+			1848000 1000000
+		>;
+		light,dvddm-operating-points = <
+			/* kHz   uV */
+			300000	800000
+			800000	800000
+			1500000	800000
+			1848000 1000000
+		>;
+	};
+	c910_3: cpu@3 {
+
+		operating-points = <
+			/* kHz    uV */
+			300000	600000
+			800000	700000
+			1500000	800000
+			1848000 1000000
+		>;
+		light,dvddm-operating-points = <
+			/* kHz   uV */
+			300000	800000
+			800000	800000
+			1500000	800000
+			1848000 1000000
+		>;
+	};
+};

arch/riscv/boot/dts/thead/fire-emu-gpu-dpu-dsi0.dts

@@ -0,0 +1,107 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2021-2022 Alibaba Group Holding Limited.
+ */
+
+/dts-v1/;
+
+#include "fire-emu.dts"
+
+&gpu {
+	status = "okay";
+};
+
+&vosys_reg {
+	status = "okay";
+};
+
+&display_subsystem {
+	status = "okay";
+};
+
+&dpu_enc0 {
+	status = "okay";
+
+	ports {
+		/* output */
+		port@1 {
+			reg = <1>;
+
+			enc0_out: endpoint {
+				remote-endpoint = <&dsi0_in>;
+			};
+		};
+	};
+};
+
+&dpu {
+	status = "okay";
+};
+
+
+&dsi0 {
+	status = "okay";
+};
+
+&dhost_0 {
+	ports {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		port@0 {
+			reg = <0>;
+
+			dsi0_in: endpoint {
+				remote-endpoint = <&enc0_out>;
+			};
+		};
+
+		port@1 {
+			reg = <1>;
+
+			dsi0_out: endpoint {
+				remote-endpoint = <&panel0_in>;
+			};
+		};
+	};
+
+	panel0@0 {
+		compatible = "hlt,hpk070h275";
+		reg = <0>;
+
+		port {
+			panel0_in: endpoint {
+				remote-endpoint = <&dsi0_out>;
+			};
+		};
+	};
+};
+
+&aon {
+	status = "okay";
+};
+
+&mbox_910t {
+	status = "okay";
+};
+
+&mbox_910t_client1 {
+	status = "okay";
+};
+
+&mbox_910t_client2 {
+	status = "okay";
+};
+
+&dmac1 {
+	status = "okay";
+};
+
+&lightsound {
+	status = "okay";
+};
+
+&dmac2 {
+    status = "disabled";
+};
+

arch/riscv/boot/dts/thead/fire-emu-soc-base-sec.dts

@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2021 Alibaba Group Holding Limited.
+ */
+
+/dts-v1/;
+
+/* #include "fire-emu.dts" */
+#include "fire-emu-soc-base.dts"
+
+&light_iopmp {
+        status = "disabled";
+};

arch/riscv/boot/dts/thead/fire-emu-soc-base.dts

@@ -0,0 +1,89 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2021-2022 Alibaba Group Holding Limited.
+ */
+
+/dts-v1/;
+
+#include "fire-emu.dts"
+
+&sdhci0 {
+	status = "okay";
+};
+
+&usb3_drd {
+	status = "okay";
+};
+
+&usb {
+	status = "okay";
+};
+
+&spi0 {
+	num-cs = <1>;
+	cs-gpios = <&gpio2_porta 15 0>; // GPIO_ACTIVE_HIGH: 0
+	rx-sample-delay-ns = <10>;
+	status = "okay";
+
+	spi_norflash@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "winbond,w25q64jwm", "jedec,spi-nor";
+		reg = <0>;
+		spi-max-frequency = <50000000>;
+		w25q,fast-read;
+		status = "okay";
+	};
+
+	spidev@1 {
+		compatible = "spidev";
+		#address-cells = <0x1>;
+		#size-cells = <0x1>;
+		reg = <0x1>;
+		spi-max-frequency = <50000000>;
+	};
+};
+
+&qspi0 {
+	num-cs = <1>;
+	cs-gpios = <&gpio2_porta 3 0>;
+	rx-sample-dly = <4>;
+	status = "okay";
+
+	spi-flash@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "spi-nand";
+		spi-max-frequency = <100000000>;
+		spi-tx-bus-width = <4>;
+		spi-rx-bus-width = <4>;
+		reg = <0>;
+
+		partition@0 {
+			label = "ubi1";
+			reg = <0x00000000 0x08000000>;
+		};
+	};
+};
+
+&qspi1 {
+	num-cs = <1>;
+	cs-gpios = <&gpio0_porta 1 0>;
+	status = "okay";
+
+	spi-flash@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "spi-nand";
+		spi-max-frequency = <66000000>;
+		spi-tx-bus-width = <4>;
+		spi-rx-bus-width = <4>;
+		reg = <0>;
+
+		partition@0 {
+			label = "ubi2";
+			reg = <0x00000000 0x08000000>;
+		};
+	};
+};
+

arch/riscv/boot/dts/thead/fire-emu-soc-c910x4.dts

@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2021-2022 Alibaba Group Holding Limited.
+ */
+
+#include "fire-emu.dts"
+
+&c910_1 {
+	status = "okay";
+};
+
+&c910_2 {
+	status = "okay";
+};
+
+&c910_3 {
+	status = "okay";
+};
+

arch/riscv/boot/dts/thead/fire-emu-vi-dsp-vo.dts

@@ -0,0 +1,57 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2021-2022 Alibaba Group Holding Limited.
+ */
+
+/dts-v1/;
+
+#include "fire-emu.dts"
+
+&c910_1 {
+	status = "okay";
+};
+
+&vi_pre {
+	status = "okay";
+};
+
+&dewarp {
+	status = "okay";
+};
+
+&xtensa_dsp {
+	status = "okay";
+};
+
+&xtensa_dsp0 {
+	status = "okay";
+};
+
+&xtensa_dsp1 {
+	status = "okay";
+};
+
+&vosys_reg {
+	status = "okay";
+};
+
+&display_subsystem {
+	status = "okay";
+};
+
+&dpu {
+	status = "okay";
+};
+
+&hdmi_tx {
+	status = "okay";
+};
+
+&dsi0 {
+	status = "okay";
+};
+
+&dpu_enc0 {
+	status = "okay";
+};
+

arch/riscv/boot/dts/thead/fire-emu-vi-vp-vo.dts

@@ -0,0 +1,119 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2021-2022 Alibaba Group Holding Limited.
+ */
+
+/dts-v1/;
+
+#include "fire-emu.dts"
+
+&c910_1 {
+	status = "okay";
+};
+
+&vi_pre {
+	status = "okay";
+};
+
+&dewarp {
+	status = "okay";
+};
+
+&venc {
+	status = "okay";
+};
+
+&vdec {
+	status = "okay";
+};
+
+&g2d {
+	status = "okay";
+};
+
+&vosys_reg {
+	status = "okay";
+};
+
+&display_subsystem {
+	status = "okay";
+};
+
+&dpu_enc0 {
+	status = "okay";
+
+	ports {
+		/* output */
+		port@1 {
+			reg = <1>;
+
+			enc0_out: endpoint {
+				remote-endpoint = <&dsi0_in>;
+			};
+		};
+	};
+};
+
+&dsi0 {
+	status = "okay";
+};
+
+&dhost_0 {
+	ports {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		port@0 {
+			reg = <0>;
+
+			dsi0_in: endpoint {
+				remote-endpoint = <&enc0_out>;
+			};
+		};
+
+		port@1 {
+			reg = <1>;
+
+			dsi0_out: endpoint {
+				remote-endpoint = <&panel0_in>;
+			};
+		};
+	};
+
+	panel0@0 {
+		compatible = "hlt,hpk070h275";
+		reg = <0>;
+
+		port {
+			panel0_in: endpoint {
+				remote-endpoint = <&dsi0_out>;
+			};
+		};
+	};
+};
+
+&dpu_enc1 {
+	ports {
+		/delete-node/ port@0;
+	};
+};
+
+&disp1_out {
+	remote-endpoint = <&hdmi_tx_in>;
+};
+
+&dpu {
+	status = "okay";
+};
+
+&hdmi_tx {
+	status = "okay";
+
+	port@0 {
+		/* input */
+		hdmi_tx_in: endpoint {
+			remote-endpoint = <&disp1_out>;
+		};
+	};
+};
+

arch/riscv/boot/dts/thead/fire-emu.dts

@@ -0,0 +1,876 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2021-2022 Alibaba Group Holding Limited.
+ */
+
+/dts-v1/;
+
+#include "fire.dtsi"
+#include <dt-bindings/input/linux-event-codes.h>
+#include <dt-bindings/gpio/gpio.h>
+#include "light-vi-devices.dtsi"
+
+/ {
+	model = "T-HEAD fire fpga board";
+	compatible = "thead,fire-emu", "thead,fire";
+
+	chosen {
+		bootargs = "console=ttyS0,115200 crashkernel=256M-:128M earlycon clk_ignore_unused sram=0xffe0000000,0x180000";
+		stdout-path = "serial0:115200n8";
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		led0 {
+			label = "SYS_STATUS";
+			gpios = <&gpio1_porta 15 0>;	/* GPIO_ACTIVE_HIGH: 0 */
+			default-state = "off";
+		};
+	};
+
+	lcd0_backlight: pwm-backlight@0 {
+		compatible = "pwm-backlight";
+		pwms = <&pwm 0 5000000>;
+		brightness-levels = <0 4 8 16 32 64 128 255>;
+		default-brightness-level = <7>;
+	};
+
+	lcd1_backlight: pwm-backlight@1 {
+		compatible = "pwm-backlight";
+		pwms = <&pwm 1 5000000>;
+		brightness-levels = <0 4 8 16 32 64 128 255>;
+		default-brightness-level = <7>;
+	};
+
+	light_iopmp: iopmp {
+		compatible = "thead,light-iopmp";
+
+		/* config#1: multiple valid regions */
+		iopmp_emmc: IOPMP_EMMC {
+			regions = <0x000000 0x100000>,
+				  <0x100000 0x200000>;
+			attr = <0xFFFFFFFF>;
+			dummy_slave= <0x800000>;
+		};
+
+		/* config#2: iopmp bypass */
+		iopmp_sdio0: IOPMP_SDIO0 {
+			bypass_en;
+		};
+
+		/* config#3: iopmp default region set */
+		iopmp_sdio1: IOPMP_SDIO1 {
+			attr = <0xFFFFFFFF>;
+			is_default_region;
+		};
+
+		iopmp_usb0: IOPMP_USB0 {
+			attr = <0xFFFFFFFF>;
+			is_default_region;
+		};
+
+		iopmp_ao: IOPMP_AO {
+			is_default_region;
+		};
+
+		iopmp_aud: IOPMP_AUD {
+			is_default_region;
+		};
+
+		iopmp_chip_dbg: IOPMP_CHIP_DBG {
+			is_default_region;
+		};
+
+		iopmp_eip120i: IOPMP_EIP120I {
+			is_default_region;
+		};
+
+		iopmp_eip120ii: IOPMP_EIP120II {
+			is_default_region;
+		};
+
+		iopmp_eip120iii: IOPMP_EIP120III {
+			is_default_region;
+		};
+
+		iopmp_isp0: IOPMP_ISP0 {
+			is_default_region;
+		};
+
+		iopmp_isp1: IOPMP_ISP1 {
+			is_default_region;
+		};
+
+		iopmp_dw200: IOPMP_DW200 {
+			is_default_region;
+		};
+
+		iopmp_vipre: IOPMP_VIPRE {
+			is_default_region;
+		};
+
+		iopmp_venc: IOPMP_VENC {
+			is_default_region;
+		};
+
+		iopmp_vdec: IOPMP_VDEC {
+			is_default_region;
+		};
+
+		iopmp_g2d: IOPMP_G2D {
+			is_default_region;
+		};
+
+		iopmp0_dpu: IOPMP0_DPU {
+			bypass_en;
+		};
+
+		iopmp1_dpu: IOPMP1_DPU {
+			bypass_en;
+		};
+
+		iopmp_gpu: IOPMP_GPU {
+			is_default_region;
+		};
+
+		iopmp_gmac1: IOPMP_GMAC1 {
+			is_default_region;
+		};
+
+		iopmp_gmac2: IOPMP_GMAC2 {
+			is_default_region;
+		};
+
+		iopmp_dmac: IOPMP_DMAC {
+			is_default_region;
+		};
+
+		iopmp_tee_dmac: IOPMP_TEE_DMAC {
+			is_default_region;
+		};
+
+		iopmp_dsp0: IOPMP_DSP0 {
+			is_default_region;
+		};
+
+		iopmp_dsp1: IOPMP_DSP1 {
+			is_default_region;
+		};
+	};
+
+	mbox_910t_client1: mbox_910t_client1 {
+		compatible = "thead,light-mbox-client";
+		mbox-names = "902";
+		mboxes = <&mbox_910t 1 0>;
+		status = "disabled";
+	};
+
+
+	mbox_910t_client2: mbox_910t_client2 {
+		compatible = "thead,light-mbox-client";
+		mbox-names = "906";
+		mboxes = <&mbox_910t 2 0>;
+		status = "disabled";
+	};
+
+	lightsound: lightsound@1 {
+		compatible = "simple-audio-card";
+		simple-audio-card,name = "Light-Sound-Card";
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		status = "disabled";
+	};
+
+	dummy_codec: dummy_codec {
+		#sound-dai-cells = <1>;
+		compatible = "linux,bt-sco";
+		status = "okay";
+	};
+
+
+	wcn_wifi: wireless-wlan {
+		compatible = "wlan-platdata";
+		clock-names = "clk_wifi";
+		ref-clock-frequency = <24000000>;
+		keep_wifi_power_on;
+		pinctrl-names = "default";
+		wifi_chip_type = "rtl8723ds";
+		WIFI,poweren_gpio = <&gpio2_porta 26 0>;
+		WIFI,reset_n = <&gpio2_porta 28 0>;
+		status = "disabled";
+	};
+
+	wcn_bt: wireless-bluetooth {
+		compatible = "bluetooth-platdata";
+		pinctrl-names = "default", "rts_gpio";
+		BT,power_gpio    = <&gpio2_porta 29 0>;
+		status = "disabled";
+	};
+
+	gpio_keys: gpio_keys{
+		compatible = "gpio-keys";
+		pinctrl-names = "default";
+		status = "disabled";
+		key-volumedown {
+			label = "Volume Down Key";
+			linux,code = <KEY_1>;
+			debounce-interval = <2>;
+			gpios = <&ao_gpio_porta 4 GPIO_ACTIVE_LOW>;
+		};
+		key-volumeup {
+			label = "Volume Up Key";
+			linux,code = <KEY_2>;
+			debounce-interval = <2>;
+			gpios = <&ao_gpio_porta 5 GPIO_ACTIVE_LOW>;
+		};
+	};
+
+	aon: light-aon {
+		compatible = "thead,light-aon";
+		mbox-names = "aon";
+		mboxes = <&mbox_910t 1 0>;
+		status = "disabled";
+
+		pd: light-aon-pd {
+			compatible = "thead,light-aon-pd";
+			#power-domain-cells = <1>;
+			status = "disabled";
+		};
+
+		aon_reg_dialog: light-dialog-reg {
+			compatible = "thead,light-dialog-pmic";
+			status = "disabled";
+		};
+
+		c910_cpufreq {
+			compatible = "thead,light-mpw-cpufreq";
+			status = "disabled";
+		};
+
+		test: light-aon-test {
+			compatible = "thead,light-aon-test";
+			status = "disabled";
+		};
+	};
+};
+
+&cmamem {
+	alloc-ranges = <0 0xe4000000 0 0x14000000>; // [0xE400_0000 ~ 0xF800_0000]
+};
+
+&resmem {
+	#address-cells = <2>;
+	#size-cells = <2>;
+	ranges;
+
+	tee_mem: memory@1a000000 {
+		reg = <0x0 0x1a000000 0 0x4000000>;
+		no-map;
+	};
+	dsp0_mem: memory@20000000 {			/**0x2000_0000~0x2040_0000 4M**/
+		reg = <0x0 0x20000000 0x0 0x00280000	/* DSP FW code&data section 2.5M*/
+		       0x0 0x20280000 0x0 0x00001000	/* DSP communication area 4K*/
+		       0x0 0x20281000 0x0 0x00007000	/* Panic/log page 28K */
+		       0x0 0x20288000 0x0 0x00178000>;	/* DSP shared memory 1.5M-32K*/
+		no-map;
+	};
+	dsp1_mem: memory@20400000 {			/**0x2040_0000~0x2080_0000 4M**/
+		reg = <0x0 0x20400000 0x0 0x00280000	/* DSP FW code&data section */
+		       0x0 0x20680000 0x0 0x00001000	/* DSP communication area */
+		       0x0 0x20681000 0x0 0x00007000	/* Panic/log page*/
+		       0x0 0x20688000 0x0 0x00178000>;	/* DSP shared memory */
+		no-map;
+	};
+    vi_mem: framebuffer@0f800000 {
+		reg = <0x0 0x0F800000 0x0 0x05400000	/* vi_mem_pool_region[0]  84 MB (default) */
+		       0x0 0x14C00000 0x0 0x01D00000	/* vi_mem_pool_region[1]  29 MB */
+		       0x0 0x16900000 0x0 0x03200000>;	/* vi_mem_pool_region[2]  50 MB */
+		no-map;
+	};
+	facelib_mem: memory@22000000 {
+		reg = <0x0 0x22000000 0x0 0x10000000>;
+		no-map;
+	};
+
+};
+
+&clk {
+	status = "disabled";
+};
+
+&i2c0 {
+	clock-frequency = <400000>;
+	status = "okay";
+
+	eeprom@50 {
+		compatible = "atmel,24c32";
+		reg = <0x50>;
+		pagesize = <32>;
+	};
+
+       touch@5d {
+               #gpio-cells = <2>;
+               compatible = "goodix,gt911";
+			   status = "disabled";
+               reg = <0x5d>;
+               interrupt-parent = <&gpio1_porta>;
+               interrupts = <8 0>;
+               irq-gpios = <&gpio1_porta 8 0>;
+               reset-gpios = <&gpio1_porta 7 0>;
+               touchscreen-size-x = <800>;
+               touchscreen-size-y = <1280>;
+       };
+};
+
+&audio_i2c0 {
+        clock-frequency = <100000>;
+        status = "disabled";
+
+        es8156_audio_codec: es8156@8 {
+               #sound-dai-cells = <0>;
+               compatible = "everest,es8156";
+               reg = <0x08>;
+               status = "disabled";
+        };
+
+        es7210_audio_codec: es7210@40 {
+                #sound-dai-cells = <0>;
+                compatible = "MicArray_0";
+                reg = <0x40>;
+                status = "disabled";
+        };
+};
+
+&i2c1 {
+        clock-frequency = <400000>;
+        status = "disabled";
+        touch1@5d {
+                #gpio-cells = <2>;
+                compatible = "goodix,gt911";
+                reg = <0x5d>;
+                interrupt-parent = <&gpio1_porta>;
+                interrupts = <12 0>;
+                irq-gpios = <&gpio1_porta 12 0>;
+                reset-gpios = <&gpio1_porta 11 0>;
+                touchscreen-size-x = <800>;
+                touchscreen-size-y = <1280>;
+        };
+};
+
+&spi0 {
+	num-cs = <1>;
+	cs-gpios = <&gpio2_porta 15 0>; // GPIO_ACTIVE_HIGH: 0
+	rx-sample-delay-ns = <10>;
+	status = "okay";
+
+	spi_norflash@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "winbond,w25q64jwm", "jedec,spi-nor";
+		reg = <0>;
+		spi-max-frequency = <50000000>;
+		w25q,fast-read;
+		status = "disabled";
+	};
+
+	spidev@1 {
+		compatible = "spidev";
+		#address-cells = <0x1>;
+		#size-cells = <0x1>;
+		reg = <0x1>;
+		spi-max-frequency = <50000000>;
+	};
+};
+
+&qspi0 {
+	status = "disabled";
+};
+
+&qspi1 {
+	status = "disabled";
+};
+&gmac0 {
+	max-speed = <100>;
+	phy-mode = "mii";
+	phy-handle = <&phy_88E1111_0>;
+	status = "okay";
+
+	mdio0 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "snps,dwmac-mdio";
+
+		phy_88E1111_0: ethernet-phy@0 {
+			reg = <0x0>;
+		};
+
+	};
+};
+
+&emmc {
+	max-frequency = <198000000>;
+	non-removable;
+	/*mmc-hs400-1_8v;*/
+	io_fixed_1v8;
+	is_emmc;
+	no-sdio;
+	no-sd;
+	pull_up;
+	bus-width = <8>;
+	status = "okay";
+};
+
+&sdhci0 {
+	max-frequency = <198000000>;
+	bus-width = <4>;
+	pull_up;
+	wprtn_ignore;
+	status = "disabled";
+};
+
+&sdhci1 {
+	max-frequency = <100000000>;
+	bus-width = <4>;
+	pull_up;
+	no-sd;
+	no-mmc;
+	non-removable;
+	io_fixed_1v8;
+	post-power-on-delay-ms = <50>;
+	wprtn_ignore;
+	cap-sd-highspeed;
+	keep-power-in-suspend;
+	wakeup-source;
+	status = "disabled";
+};
+
+&padctrl0_apsys { /* right-pinctrl */
+	light-evb-padctrl0 {
+			/*
+			 * Pin Configuration Node:
+			 * Format: <pin_id mux_node config>
+			 */
+			pinctrl_uart0: uart0grp {
+				thead,pins = <
+					FM_UART0_TXD	0x0	0x72
+					FM_UART0_RXD	0x0	0x72
+				>;
+			};
+
+			pinctrl_spi0: spi0grp {
+				thead,pins = <
+					FM_SPI_CSN	0x3	0x20a
+					FM_SPI_SCLK	0x0	0x20a
+					FM_SPI_MISO	0x0	0x23a
+					FM_SPI_MOSI	0x0	0x23a
+				>;
+			};
+
+			pinctrl_qspi0: qspi0grp {
+				thead,pins = <
+					FM_QSPI0_SCLK    0x0    0x20f
+					FM_QSPI0_CSN0    0x3    0x20f
+					FM_QSPI0_CSN1    0x0    0x20f
+					FM_QSPI0_D0_MOSI 0x0    0x23f
+					FM_QSPI0_D1_MISO 0x0    0x23f
+					FM_QSPI0_D2_WP   0x0    0x23f
+					FM_QSPI0_D3_HOLD 0x0    0x23f
+				>;
+			};
+
+			pinctrl_light_i2s0: i2s0grp {
+				thead,pins = <
+					FM_QSPI0_SCLK    0x2    0x208
+					FM_QSPI0_CSN0    0x2    0x238
+					FM_QSPI0_CSN1    0x2    0x208
+					FM_QSPI0_D0_MOSI 0x2    0x238
+					FM_QSPI0_D1_MISO 0x2    0x238
+					FM_QSPI0_D2_WP   0x2    0x238
+					FM_QSPI0_D3_HOLD 0x2    0x238
+				>;
+			};
+
+			pinctrl_pwm: pwmgrp {
+				thead,pins = <
+					FM_GPIO3_2	0x1	0x208	/* pwm0 */
+					FM_GPIO3_3	0x1	0x208	/* pwm1 */
+				>;
+			};
+		};
+};
+
+&padctrl1_apsys { /* left-pinctrl */
+	light-evb-padctrl1 {
+			/*
+			 * Pin Configuration Node:
+			 * Format: <pin_id mux_node config>
+			 */
+			pinctrl_uart3: uart3grp {
+				thead,pins = <
+					FM_UART3_TXD	0x0	0x72
+					FM_UART3_RXD	0x0	0x72
+				>;
+			};
+
+			pinctrl_uart4: uart4grp {
+				thead,pins = <
+					FM_UART4_TXD	0x0	0x72
+					FM_UART4_RXD	0x0	0x72
+					FM_UART4_CTSN	0x0	0x72
+					FM_UART4_RTSN	0x0	0x72
+				>;
+			};
+
+			pinctrl_qspi1: qspi1grp {
+				thead,pins = <
+					FM_QSPI1_SCLK    0x0    0x20a
+					FM_QSPI1_CSN0    0x3    0x20a
+					FM_QSPI1_D0_MOSI 0x0    0x23a
+					FM_QSPI1_D1_MISO 0x0    0x23a
+					FM_QSPI1_D2_WP   0x0    0x23a
+					FM_QSPI1_D3_HOLD 0x0    0x23a
+				>;
+			};
+
+
+			pinctrl_iso7816: iso7816grp {
+				thead,pins = <
+					FM_QSPI1_SCLK		0x1	0x208
+					FM_QSPI1_D0_MOSI	0x1	0x238
+					FM_QSPI1_D1_MISO	0x1	0x238
+					FM_QSPI1_D2_WP		0x1	0x238
+					FM_QSPI1_D3_HOLD	0x1	0x238
+				>;
+			};
+
+		};
+};
+
+&i2c2 {
+    clock-frequency = <400000>;
+	status = "okay";
+	eeprom@50 {
+		compatible = "atmel,24c32";
+		reg = <0x50>;
+		pagesize = <32>;
+	};
+};
+
+&i2c3 {
+    clock-frequency = <400000>;
+	status = "okay";
+	eeprom@50 {
+		compatible = "atmel,24c32";
+		reg = <0x50>;
+		pagesize = <32>;
+	};
+};
+
+&i2c4 {
+    clock-frequency = <400000>;
+	status = "okay";
+	eeprom@50 {
+		compatible = "atmel,24c32";
+		reg = <0x50>;
+		pagesize = <32>;
+	};
+
+	pcal6408ahk_a: gpio@20 {
+		compatible = "nxp,pcal9554b";
+		reg = <0x20>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+};
+
+&isp0 {
+	status = "disabled";
+};
+
+&isp1 {
+	status = "disabled";
+};
+
+&isp_ry0 {
+	status = "disabled";
+};
+
+&dewarp {
+	status = "disabled";
+};
+
+&dec400_isp0 {
+	status = "disabled";
+};
+
+&dec400_isp1 {
+	status = "disabled";
+};
+
+&dec400_isp2 {
+	status = "disabled";
+};
+
+&bm_visys {
+	status = "disabled";
+};
+
+&bm_csi0 {
+	status = "disabled";
+};
+
+&bm_csi1 {
+	status = "disabled";
+};
+
+&bm_csi2 {
+	status = "disabled";
+};
+
+&vi_pre {
+	//vi_pre_irq_en = <1>;
+	status = "disabled";
+};
+
+&xtensa_dsp {
+	status = "disabled";
+};
+
+&xtensa_dsp0 {
+	status = "disabled";
+    memory-region = <&dsp0_mem>;
+};
+
+&xtensa_dsp1{
+    status = "disabled";
+    memory-region = <&dsp1_mem>;
+};
+
+&vvcam_flash_led0{
+    flash_led_name = "aw36413_aw36515";
+	floodlight_i2c_bus = /bits/ 8 <2>;
+	floodlight_en_pin = <&gpio1_porta 25 0>;
+	//projection_i2c_bus = /bits/ 8 <2>;
+	flash_led_touch_pin = <&gpio1_porta 27 0>; //flash led touch pin
+	status = "disabled";
+};
+
+&trng {
+	status = "disabled";
+};
+
+&eip_28 {
+	status = "okay";
+};
+
+&vdec {
+	status = "disabled";
+};
+
+&venc {
+	status = "disabled";
+};
+
+&isp_venc_shake {
+	status = "disabled";
+};
+
+&vidmem {
+	status = "okay";
+	memory-region = <&vi_mem>;
+};
+
+&gpu {
+	status = "disabled";
+};
+
+&cpus {
+	c910_0: cpu@0 {
+		operating-points = <
+			/* kHz    uV */
+			300000	650000
+			800000	700000
+			1500000	800000
+			1848000	1000000
+		>;
+		light,dvddm-operating-points = <
+			/* kHz   uV */
+			300000	800000
+			800000	800000
+			1500000	800000
+			1848000	1000000
+		>;
+	};
+	c910_1: cpu@1 {
+		status = "disabled";
+		operating-points = <
+			/* kHz    uV */
+			300000	650000
+			800000	700000
+			1500000	800000
+			1848000	1000000
+		>;
+		light,dvddm-operating-points = <
+			/* kHz   uV */
+			300000	800000
+			800000	800000
+			1500000	800000
+			1848000	1000000
+		>;
+	};
+	c910_2: cpu@2 {
+		status = "disabled";
+		operating-points = <
+			/* kHz    uV */
+			300000	650000
+			800000	700000
+			1500000	800000
+			1848000	1000000
+		>;
+		light,dvddm-operating-points = <
+			/* kHz   uV */
+			300000	800000
+			800000	800000
+			1500000	800000
+			1848000	1000000
+		>;
+	};
+	c910_3: cpu@3 {
+		status = "disabled";
+		operating-points = <
+			/* kHz    uV */
+			300000	650000
+			800000	700000
+			1500000	800000
+			1848000	1000000
+		>;
+		light,dvddm-operating-points = <
+			/* kHz   uV */
+			300000	800000
+			800000	800000
+			1500000	800000
+			1848000	1000000
+		>;
+	};
+};
+
+&thermal_zones {
+	cpu-thermal-zone {
+		status = "disabled";
+	};
+};
+
+&dummy_clock_apb {
+	clock-frequency = <50000000>;
+};
+
+&uart0 {
+	clocks = <&dummy_clock_apb>;
+};
+&uart1 {
+	clocks = <&dummy_clock_apb>;
+};
+&uart2 {
+	clocks = <&dummy_clock_apb>;
+};
+&uart3 {
+	clocks = <&dummy_clock_apb>;
+};
+&uart4 {
+	clocks = <&dummy_clock_apb>;
+};
+&uart5 {
+	clocks = <&dummy_clock_apb>;
+};
+
+&usb3_drd {
+	status = "disabled";
+};
+
+&usb {
+	status = "disabled";
+};
+
+&dspsys_reg {
+	status = "disabled";
+};
+
+&audio_ioctrl {
+	status = "disabled";
+};
+
+&audio_cpr {
+	status = "disabled";
+};
+
+&timer0 {
+	clock-frequency = <50000000>;
+};
+
+&timer1 {
+	clock-frequency = <50000000>;
+};
+
+&timer2 {
+	clock-frequency = <50000000>;
+};
+
+&timer3 {
+	clock-frequency = <50000000>;
+};
+
+&g2d {
+	status = "disabled";
+};
+
+&vosys_reg {
+	status = "disabled";
+};
+
+&dmac2 {
+    status = "disabled";
+};
+
+&sdhci1 {
+	status = "disabled";
+};
+
+&pvt {
+	status = "disabled";
+};
+
+&audio_i2c0 {
+	status = "disabled";
+};
+
+&csia_reg {
+	status = "disabled";
+};
+
+&visys_clk_gate { /* VI_SYSREG_R */
+	status = "disabled";
+};
+
+&vpsys_clk_gate { /* VP_SYSREG_R */
+	status = "disabled";
+};
+
+&vosys_clk_gate { /* VO_SYSREG_R */
+	status = "disabled";
+};
+
+&dspsys_clk_gate {
+	status = "disabled";
+};
+
+&watchdog0 {
+	status = "disabled";
+};
+
+&watchdog1 {
+	status = "disabled";
+};
+

arch/riscv/boot/dts/thead/light-a-product.dts

@@ -162,6 +162,14 @@
 		iopmp_dsp1: IOPMP_DSP1 {
 			is_default_region;
 		};
+
+		iopmp_audio0: IOPMP_AUDIO0 {
+			is_default_region;
+		};
+
+		iopmp_audio1: IOPMP_AUDIO1 {
+			is_default_region;
+		};
 	};
 
 	mbox_910t_client1: mbox_910t_client1 {
@@ -517,15 +525,6 @@
 		pagesize = <32>;
 	};
 
-	codec: wm8960@1a {
-		#sound-dai-cells = <0>;
-		compatible = "wlf,wm8960";
-		reg = <0x1a>;
-		wlf,shared-lrclk;
-		wlf,hp-cfg = <3 2 3>;
-		wlf,gpio-cfg = <1 3>;
-	};
-
        touch@5d {
                #gpio-cells = <2>;
                compatible = "goodix,gt911";
@@ -535,7 +534,7 @@
                irq-gpios = <&gpio1_porta 8 0>;
                reset-gpios = <&gpio1_porta 7 0>;
                AVDD28-supply = <&reg_tp_pwr_en>;
-               touchscreen-size-x = <720>;
+               touchscreen-size-x = <800>;
                touchscreen-size-y = <1280>;
        };
 };
@@ -552,7 +551,7 @@
                 irq-gpios = <&gpio1_porta 12 0>;
                 reset-gpios = <&gpio1_porta 11 0>;
                 AVDD28-supply = <&reg_tp1_pwr_en>;
-                touchscreen-size-x = <720>;
+                touchscreen-size-x = <800>;
                 touchscreen-size-y = <1280>;
         };
 };
@@ -687,6 +686,7 @@
 	no-mmc;
 	non-removable;
 	io_fixed_1v8;
+	rxclk-sample-delay = <80>;
 	post-power-on-delay-ms = <50>;
 	wprtn_ignore;
 	cap-sd-highspeed;
@@ -729,7 +729,7 @@
 				>;
 			};
 
-			pinctrl_audio_i2s0: i2s0grp {
+			pinctrl_light_i2s0: i2s0grp {
 				thead,pins = <
 					FM_QSPI0_SCLK    0x2    0x208
 					FM_QSPI0_CSN0    0x2    0x238
@@ -973,8 +973,8 @@
 
 &video0{
 	status = "okay";
-    piplane0 {
+    channel0 {
-		pipline_id = <0>;
+		channel_id = <0>;
 		status = "okay";
 		sensor0 {
 			subdev_name = "vivcam";
@@ -998,8 +998,8 @@
 
 &video1{
 	status = "okay";
-	piplane0 { // VSE0
+	channel0 { // VSE0
-		pipline_id = <0>;
+		channel_id = <0>;
 		status = "okay";
 		sensor0 {
 			subdev_name = "vivcam";
@@ -1023,8 +1023,8 @@
 
 &video2{
 	status = "okay";
-	piplane0 {
+	channel0 {
-		pipline_id = <0>;
+		channel_id = <0>;
 		status = "okay";
         sensor0 {
 			subdev_name = "vivcam";
@@ -1044,8 +1044,8 @@
 			path_type = "DSP_PATH_VIPRE_ODD";
 		};
 	};
-    piplane1 {
+    channel1 {
-		pipline_id = <1>;
+		channel_id = <1>;
 		status = "okay";
         sensor0 {
 			subdev_name = "vivcam";

arch/riscv/boot/dts/thead/light-a-val-android.dts

@@ -31,39 +31,36 @@
 &lightsound {
 	status = "okay";
 
-	simple-audio-card,widgets =
+        simple-audio-card,dai-link@0 {          /* I2S - AUDIO SYS CODEC 8156*/
-		"Microphone", "Mic Jack",
-		"Speaker", "Speaker",
-		"Headphone", "Headphone Jack";
-	simple-audio-card,routing =
-		"Headphone Jack", "HP_L",
-		"Headphone Jack", "HP_R",
-		"Speaker", "SPK_LP",
-		"Speaker", "SPK_LN",
-		"Speaker", "SPK_RP",
-		"Speaker", "SPK_RN",
-		"Mic Jack","MICB",
-		"LINPUT1", "Mic Jack",
-		"LINPUT3", "Mic Jack";
-
-	simple-audio-card,dai-link@0 {          /* I2S - CODEC */
                 reg = <0>;
                 format = "i2s";
                 cpu {
-			sound-dai = <&light_i2s 0>;
+                        sound-dai = <&i2s0 0>;
                 };
                 codec {
-			sound-dai = <&codec>;
+                        sound-dai = <&es8156_audio_codec>;
                 };
         };
-	simple-audio-card,dai-link@1 {          /* I2S - HDMI */
+
+        simple-audio-card,dai-link@1 {          /* I2S - AUDIO SYS CODEC 7210*/
                 reg = <1>;
                 format = "i2s";
+                cpu {
+                        sound-dai = <&i2s_8ch_sd2 2>;
+                };
+                codec {
+                        sound-dai = <&es7210_audio_codec_adc0>;
+                };
+        };
+
+	simple-audio-card,dai-link@2 {          /* I2S - HDMI */
+		reg = <2>;
+		format = "i2s";
 		cpu {
 			sound-dai = <&light_i2s 1>;
 		};
 		codec {
-                        sound-dai = <&dummy_codec 2>;
+			sound-dai = <&dummy_codec>;
 		};
 	};
 };
@@ -72,6 +69,18 @@
 	status = "okay";
 };
 
+&i2s0 {
+        status = "okay";
+};
+
+&i2s_8ch_sd2 {
+        status = "okay";
+};
+
+&es7210_audio_codec_adc0 {
+        status = "okay";
+};
+
 &hdmi_tx {
 	status = "okay";
 

arch/riscv/boot/dts/thead/light-a-val-audio-hdmi.dts

@@ -0,0 +1,58 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2021 Alibaba Group Holding Limited.
+ */
+
+/dts-v1/;
+
+#include "light-a-val-audio.dts"
+
+/ {
+	display-subsystem {
+		status = "okay";
+	};
+};
+
+&dpu_enc1 {
+	ports {
+		/delete-node/ port@0;
+	};
+};
+
+&disp1_out {
+	remote-endpoint = <&hdmi_tx_in>;
+};
+
+&dpu {
+	status = "okay";
+};
+
+&hdmi_tx {
+	status = "okay";
+
+	port@0 {
+		/* input */
+		hdmi_tx_in: endpoint {
+			remote-endpoint = <&disp1_out>;
+		};
+	};
+};
+
+&lightsound {
+	status = "okay";
+	
+	simple-audio-card,dai-link@2 {          /* I2S - HDMI */
+		reg = <2>;
+		format = "i2s";
+		cpu {
+			sound-dai = <&light_i2s 1>;
+		};
+		codec {
+			sound-dai = <&dummy_codec>;
+		};
+	};
+};
+
+&light_i2s {
+        status = "okay";
+};

arch/riscv/boot/dts/thead/light-a-val-audio-i2s-8ch.dts

@@ -0,0 +1,100 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2021 Alibaba Group Holding Limited.
+ */
+
+#include "light-a-val-audio.dts"
+
+/ {
+	model = "T-HEAD Light FM Audio VAL board";
+	compatible = "thead,light-val-audio-i2s-8ch", "thead,light";
+};
+
+
+&lightsound {
+        status = "okay";
+
+	simple-audio-card,dai-link@1 {          /* I2S - AUDIO SYS CODEC 7210*/
+                reg = <1>;
+                format = "i2s";
+                cpu {
+                        sound-dai = <&i2s_8ch_sd2 2>;
+                };
+                codec {
+                        mclk-fs = <512>;
+                        sound-dai = <&es7210_audio_codec_adc0>;
+                };
+        };
+
+	simple-audio-card,dai-link@2 {          /* I2S - AUDIO SYS CODEC 7210*/
+                reg = <2>;
+                format = "i2s";
+                cpu {
+                        sound-dai = <&i2s_8ch_sd3 3>;
+                };
+                codec {
+                        mclk-fs = <512>;
+                        sound-dai = <&es7210_audio_codec_adc0>;
+                };
+        };
+
+        simple-audio-card,dai-link@3 {          /* I2S - AUDIO SYS CODEC 7210_1*/
+                reg = <3>;
+                format = "i2s";
+                cpu {
+                        sound-dai = <&i2s_8ch_sd0 0>;
+                };
+                codec {
+                        mclk-fs = <512>;
+                        sound-dai = <&es7210_audio_codec_adc1>;
+                };
+        };
+
+        simple-audio-card,dai-link@4 {          /* I2S - AUDIO SYS CODEC 7210_1*/
+                reg = <4>;
+                format = "i2s";
+                cpu {
+                        sound-dai = <&i2s_8ch_sd1 1>;
+                };
+                codec {
+                        mclk-fs = <512>;
+                        sound-dai = <&es7210_audio_codec_adc1>;
+                };
+        };
+};
+
+&i2s_8ch_sd0 {
+        status = "okay";
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_audiopa4>,
+                    <&pinctrl_audio_i2s_8ch_sd0>,
+                    <&pinctrl_audiopa2>,
+                    <&pinctrl_audiopa3>,
+                    <&pinctrl_audiopa8>,
+                    <&pinctrl_audio_i2s_8ch_bus>;
+};
+
+&i2s_8ch_sd1 {
+        status = "okay";
+};
+
+&i2s_8ch_sd2 {
+        status = "okay";
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_audiopa0>,
+                    <&pinctrl_audio_i2s_8ch_sd2>;
+};
+
+&i2s_8ch_sd3 {
+        status = "okay";
+};
+
+&es7210_audio_codec_adc0 {
+        status = "okay";
+        channels-max = <8>;
+};
+
+&es7210_audio_codec_adc1 {
+        status = "okay";
+        channels-max = <8>;
+};

arch/riscv/boot/dts/thead/light-a-val-audio-spdif.dts

@@ -0,0 +1,42 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2021 Alibaba Group Holding Limited.
+ */
+
+#include "light-a-val.dts"
+
+&spdif0 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_audio_spdif0>;
+	status = "okay";
+};
+
+&spdif1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_audio_spdif1>;
+	status = "okay";
+};
+
+&lightsound {
+        status = "okay";
+        simple-audio-card,dai-link@0 {          /* SPDIF0 */
+                reg = <1>;
+                format = "i2s";
+                cpu {
+                        sound-dai = <&spdif0>;
+                };
+                codec {
+                        sound-dai = <&dummy_codec>;
+                };
+        };
+        simple-audio-card,dai-link@1 {          /* SPDIF1 */
+                reg = <1>;
+                format = "i2s";
+                cpu {
+                        sound-dai = <&spdif1>;
+                };
+                codec {
+                        sound-dai = <&dummy_codec>;
+                };
+        };
+};

arch/riscv/boot/dts/thead/light-a-val-audio-tdm.dts

@@ -0,0 +1,182 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2021 Alibaba Group Holding Limited.
+ */
+
+#include "light-a-val.dts"
+
+&tdm_slot1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_audio_tdm>;
+	status = "okay";
+};
+
+&tdm_slot2 {
+	status = "okay";
+};
+
+&tdm_slot3 {
+	status = "okay";
+};
+
+&tdm_slot4 {
+	status = "okay";
+};
+
+&tdm_slot5 {
+	status = "okay";
+};
+
+&tdm_slot6 {
+	status = "okay";
+};
+
+&tdm_slot7 {
+	status = "okay";
+};
+
+&tdm_slot8 {
+	status = "okay";
+};
+
+&audio_i2c0 {
+        clock-frequency = <100000>;
+        status = "okay";
+
+        es7210_adc2: es7210@42 {
+                #sound-dai-cells = <0>;
+                compatible = "MicArray_0";
+                reg = <0x42>;
+                work-mode = "ES7210_TDM_1LRCK_DSPB";
+                channels-max = <8>;
+                sound-name-prefix = "ES7210_ADC2";
+                MVDD-supply = <&soc_aud_adc_3v3_en_reg>;
+                AVDD-supply = <&soc_aud_adc_3v3_en_reg>;
+                DVDD-supply = <&soc_dvdd18_aon_reg>;
+                PVDD-supply = <&soc_dvdd18_aon_reg>;
+        };
+
+        es7210_adc3: es7210@43 {
+                #sound-dai-cells = <0>;
+                compatible = "MicArray_1";
+                reg = <0x43>;
+                work-mode = "ES7210_TDM_1LRCK_DSPB";
+                channels-max = <8>;
+                sound-name-prefix = "ES7210_ADC3";
+                MVDD-supply = <&soc_aud_adc_3v3_en_reg>;
+                AVDD-supply = <&soc_aud_adc_3v3_en_reg>;
+                DVDD-supply = <&soc_dvdd18_aon_reg>;
+                PVDD-supply = <&soc_dvdd18_aon_reg>;
+        };
+};
+
+&lightsound {
+        status = "okay";
+        simple-audio-card,widgets = "Speaker", "Speaker";
+        simple-audio-card,routing = 
+        	"AW87519 IN", "ES8156 ROUT",
+        	"Speaker", "AW87519 VO";
+        simple-audio-card,aux-devs = <&audio_aw87519_pa>;
+        simple-audio-card,dai-link@0 {          /* I2S - AUDIO SYS CODEC 8156*/
+                reg = <0>;
+                format = "i2s";
+                cpu {
+                        sound-dai = <&i2s0 0>;
+                };
+                codec {
+                        sound-dai = <&es8156_audio_codec>;
+                };
+        };
+
+        simple-audio-card,dai-link@1 {          /* TDM - AUDIO SYS CODEC 7210*/
+                reg = <1>;
+                format = "dsp_b";
+                cpu {
+                        sound-dai = <&tdm_slot1>;
+                };
+                codec {
+                        sound-dai = <&es7210_adc2>;
+                };
+        };
+
+        simple-audio-card,dai-link@2 {
+                reg = <1>;
+                format = "dsp_b";
+                cpu {
+                        sound-dai = <&tdm_slot2>;
+                };
+                codec {
+                        sound-dai = <&es7210_adc2>;
+                };
+        };
+
+        simple-audio-card,dai-link@3 {
+                reg = <1>;
+                format = "dsp_b";
+                cpu {
+                        sound-dai = <&tdm_slot3>;
+                };
+                codec {
+                        sound-dai = <&es7210_adc2>;
+                };
+        };
+
+        simple-audio-card,dai-link@4 {
+                reg = <1>;
+                format = "dsp_b";
+                cpu {
+                        sound-dai = <&tdm_slot4>;
+                };
+                codec {
+                        sound-dai = <&es7210_adc2>;
+                };
+        };
+
+        simple-audio-card,dai-link@5 {
+                reg = <1>;
+                format = "dsp_b";
+                cpu {
+                        sound-dai = <&tdm_slot5>;
+                };
+                codec {
+                        sound-dai = <&es7210_adc2>;
+                };
+        };
+
+        simple-audio-card,dai-link@6 {
+                reg = <1>;
+                format = "dsp_b";
+                cpu {
+                        sound-dai = <&tdm_slot6>;
+                };
+                codec {
+                        sound-dai = <&es7210_adc2>;
+                };
+        };
+
+        simple-audio-card,dai-link@7 {
+                reg = <1>;
+                format = "dsp_b";
+                cpu {
+                        sound-dai = <&tdm_slot7>;
+                };
+                codec {
+                        sound-dai = <&es7210_adc2>;
+                };
+        };
+
+        simple-audio-card,dai-link@8 {
+                reg = <1>;
+                format = "dsp_b";
+                cpu {
+                        sound-dai = <&tdm_slot8>;
+                };
+                codec {
+                        sound-dai = <&es7210_adc2>;
+                };
+        };
+};
+
+&i2s0 {
+        status = "okay";
+};

arch/riscv/boot/dts/thead/light-a-val-audio.dts

@@ -12,7 +12,11 @@
 
 &lightsound {
         status = "okay";
-
+        simple-audio-card,widgets = "Speaker", "Speaker";
+        simple-audio-card,routing = 
+        	"Speaker", "AW87519 VO",
+        	"AW87519 IN", "ES8156 ROUT";
+        simple-audio-card,aux-devs = <&audio_aw87519_pa>;
         simple-audio-card,dai-link@0 {          /* I2S - AUDIO SYS CODEC 8156*/
                 reg = <0>;
                 format = "i2s";
@@ -28,22 +32,24 @@
                 reg = <1>;
                 format = "i2s";
                 cpu {
-                        sound-dai = <&i2s3 0>;
+                        sound-dai = <&i2s_8ch_sd2 2>;
                 };
                 codec {
-                        sound-dai = <&es7210_audio_codec>;
+                        sound-dai = <&es7210_audio_codec_adc0>;
                 };
         };
 };
 
-&light_i2s {
-	status = "okay";
-};
-
 &i2s0 {
         status = "okay";
 };
 
-&i2s3 {
+&i2s_8ch_sd2 {
         status = "okay";
 };
+
+&es7210_audio_codec_adc0 {
+        status = "okay";
+};
+
+

arch/riscv/boot/dts/thead/light-a-val-ddr1G.dts

@@ -11,7 +11,7 @@
 
 	memory@0 {
 		device_type = "memory";
-		reg = <0x0 0x00000000 0x0 0x40000000>;
+		reg = <0x0 0x200000 0x0 0x3fe00000>;
 	};
 };
 

arch/riscv/boot/dts/thead/light-a-val-ddr2G.dts

@@ -11,7 +11,7 @@
 
 	memory@0 {
 		device_type = "memory";
-		reg = <0x0 0x00000000 0x0 0x80000000>;
+		reg = <0x0 0x200000 0x0 0x7fe00000>;
 	};
 };
 

arch/riscv/boot/dts/thead/light-a-val-dsi0-hdmi-audio.dts

@@ -0,0 +1,64 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2021 Alibaba Group Holding Limited.
+ */
+
+/dts-v1/;
+
+#include "light-a-val-dsi0-hdmi.dts"
+
+&lightsound {
+        status = "okay";
+        simple-audio-card,widgets = "Speaker", "Speaker";
+        simple-audio-card,routing = 
+        	"Speaker", "AW87519 VO",
+        	"AW87519 IN", "ES8156 ROUT";
+        simple-audio-card,aux-devs = <&audio_aw87519_pa>;
+        simple-audio-card,dai-link@0 {          /* I2S - AUDIO SYS CODEC 8156*/
+                reg = <0>;
+                format = "i2s";
+                cpu {
+                        sound-dai = <&i2s0 0>;
+                };
+                codec {
+                        sound-dai = <&es8156_audio_codec>;
+                };
+        };
+
+        simple-audio-card,dai-link@1 {          /* I2S - AUDIO SYS CODEC 7210*/
+                reg = <1>;
+                format = "i2s";
+                cpu {
+                        sound-dai = <&i2s_8ch_sd2 2>;
+                };
+                codec {
+                        sound-dai = <&es7210_audio_codec_adc0>;
+                };
+        };
+        simple-audio-card,dai-link@2 {          /* I2S - HDMI */
+                reg = <2>;
+                format = "i2s";
+                cpu {
+                        sound-dai = <&light_i2s 1>;
+                };
+                codec {
+                        sound-dai = <&dummy_codec>;
+                };
+        };
+};
+
+&light_i2s {
+	status = "okay";
+};
+
+&i2s0 {
+        status = "okay";
+};
+
+&i2s_8ch_sd2 {
+        status = "okay";
+};
+
+&es7210_audio_codec_adc0 {
+        status = "okay";
+};

arch/riscv/boot/dts/thead/light-a-val-full.dts

@@ -95,7 +95,11 @@
 
 &lightsound {
         status = "okay";
-
+        simple-audio-card,widgets = "Speaker", "Speaker";
+        simple-audio-card,routing = 
+        	"Speaker", "AW87519 VO",
+        	"AW87519 IN", "ES8156 ROUT";
+        simple-audio-card,aux-devs = <&audio_aw87519_pa>;
         simple-audio-card,dai-link@0 {          /* I2S - AUDIO SYS CODEC 8156*/
                 reg = <0>;
                 format = "i2s";
@@ -111,10 +115,10 @@
                 reg = <1>;
                 format = "i2s";
                 cpu {
-                        sound-dai = <&i2s3 0>;
+                        sound-dai = <&i2s_8ch_sd2 2>;
                 };
                 codec {
-                        sound-dai = <&es7210_audio_codec>;
+                        sound-dai = <&es7210_audio_codec_adc0>;
                 };
         };
 };
@@ -127,7 +131,11 @@
         status = "okay";
 };
 
-&i2s3 {
+&i2s_8ch_sd2 {
+        status = "okay";
+};
+ 
+&es7210_audio_codec_adc0 {
         status = "okay";
 };
 

arch/riscv/boot/dts/thead/light-a-val-hdmi.dts

@@ -48,7 +48,7 @@
 			sound-dai = <&light_i2s 1>;
 		};
 		codec {
-			sound-dai = <&dummy_codec 2>;
+			sound-dai = <&dummy_codec>;
 		};
 	};
 };

arch/riscv/boot/dts/thead/light-a-val-miniapp-dsi0.dts

@@ -74,6 +74,26 @@
 	};
 };
 
+&padctrl_audiosys {
+	status = "okay";
+
+	light-audio-padctrl {
+			/*
+			 * Pin Configuration Node:
+			 * Format: <pin_id mux_node config>
+			 */
+
+			pinctrl_audio_i2s_8ch: audio_i2s_8ch_grp {
+				thead,pins = <
+					FM_AUDIO_IO_PA0	  0x2 0x008
+					FM_AUDIO_IO_PA2	  0x2 0x008
+					FM_AUDIO_IO_PA3   0x2 0x008
+					FM_AUDIO_IO_PA8   0x2 0x008
+				>;
+			};
+	};
+};
+
 &lightsound {
 	status = "okay";
 
@@ -92,15 +112,14 @@
                 reg = <1>;
                 format = "i2s";
                 cpu {
-                        sound-dai = <&i2s3 0>;
+                        sound-dai = <&i2s_8ch_sd2 2>;
                 };
                 codec {
-                        sound-dai = <&es7210_audio_codec>;
+                        sound-dai = <&es7210_audio_codec_adc0>;
                 };
         };
 };
 
-
 &light_i2s {
 	status = "okay";
 };
@@ -109,7 +128,11 @@
         status = "okay";
 };
 
-&i2s3 {
+&i2s_8ch_sd2 {
+        status = "okay";
+};
+
+&es7210_audio_codec_adc0 {
         status = "okay";
 };
 

arch/riscv/boot/dts/thead/light-a-val-miniapp-hdmi.dts

@@ -56,10 +56,10 @@
                 reg = <1>;
                 format = "i2s";
                 cpu {
-                        sound-dai = <&i2s3 0>;
+                        sound-dai = <&i2s_8ch_sd2 2>;
                 };
                 codec {
-                        sound-dai = <&es7210_audio_codec>;
+                        sound-dai = <&es7210_audio_codec_adc0>;
                 };
         };
 };
@@ -73,7 +73,11 @@
         status = "okay";
 };
 
-&i2s3 {
+&i2s_8ch_sd2 {
+        status = "okay";
+};
+
+&es7210_audio_codec_adc0 {
         status = "okay";
 };
 

arch/riscv/boot/dts/thead/light-a-val-sec.dts

@@ -5,9 +5,16 @@
 
 /dts-v1/;
 
-#include "light-a-val-dsi0-hdmi.dts"
+#include "light-a-val-audio-hdmi.dts"
 
 
 &light_iopmp {
         status = "disabled";
 };
+&qspi1 {
+        status = "disabled";
+};
+
+&eip_28 {
+        status = "disabled";
+};

arch/riscv/boot/dts/thead/light-ant-discrete.dts

@@ -15,7 +15,7 @@
 
 	memory@0 {
 		device_type = "memory";
-		reg = <0x0 0x00000000 0x0 0x80000000>;
+		reg = <0x0 0x200000 0x0 0x7fe00000>;
 	};
 
 	chosen {
@@ -194,9 +194,10 @@
 	};
 
 	dummy_codec: dummy_codec {
-		#sound-dai-cells = <1>;
+		#sound-dai-cells = <0>;
-		compatible = "linux,bt-sco";
+		compatible = "thead,light-dummy-pcm";
 		status = "okay";
+		sound-name-prefix = "DUMMY";
 	};
 
 	reg_vref_1v8: regulator-adc-verf {
@@ -571,7 +572,7 @@
                irq-gpios = <&gpio1_porta 8 0>;
                reset-gpios = <&gpio1_porta 7 0>;
                AVDD28-supply = <&reg_tp_pwr_en>;
-               touchscreen-size-x = <720>;
+               touchscreen-size-x = <800>;
                touchscreen-size-y = <1280>;
        };
 
@@ -585,18 +586,25 @@
                 #sound-dai-cells = <0>;
                 compatible = "everest,es8156";
                 reg = <0x08>;
+                sound-name-prefix = "ES8156";
+                AVDD-supply = <&soc_aud_3v3_en_reg>;
+                DVDD-supply = <&soc_aud_1v8_en_reg>;
+                PVDD-supply = <&soc_aud_1v8_en_reg>;
         };
 
         es7210_audio_codec: es7210@40 {
                 #sound-dai-cells = <0>;
                 compatible = "MicArray_0";
                 reg = <0x40>;
+                sound-name-prefix = "ES7210";
+                status = "disabled";
         };
 
-	audio_aw87519_pa@58 {
+        audio_aw87519_pa: amp@58 {
                 compatible = "awinic,aw87519_pa";
                 reg = <0x58>;
                 reset-gpio = <&ao_gpio4_porta 9 0x1>;
+                sound-name-prefix = "AW87519";
                 status = "okay";
         };
 };
@@ -731,6 +739,7 @@
 	no-mmc;
 	non-removable;
 	io_fixed_1v8;
+	rxclk-sample-delay = <80>;
 	post-power-on-delay-ms = <50>;
 	wprtn_ignore;
 	cap-sd-highspeed;
@@ -773,7 +782,7 @@
 				>;
 			};
 
-			pinctrl_audio_i2s0: i2s0grp {
+			pinctrl_light_i2s0: i2s0grp {
 				thead,pins = <
 					FM_QSPI0_SCLK    0x2    0x208
 					FM_QSPI0_CSN0    0x2    0x238
@@ -1034,7 +1043,7 @@
 
 &video0{
     vi_mem_pool_region = <2>;	// vi_mem: framebuffer, region[2]
-    pipline0 {
+    channel0 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <2>; //<2>=vivcam2 : gc5035
@@ -1061,7 +1070,7 @@
 			};
 		};
 	};
-	pipline1 {
+	channel1 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <2>; //<2>=vivcam2 : gc5035
@@ -1088,7 +1097,7 @@
 			};
 		};
 	};
-	pipline2 {
+	channel2 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <2>; //<2>=vivcam2 : gc5035
@@ -1120,7 +1129,7 @@
 
 &video1{
     vi_mem_pool_region = <2>;	// vi_mem: framebuffer, region[2]
-    pipline0 {
+    channel0 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <2>; //<2>=vivcam2 : gc5035
@@ -1153,7 +1162,7 @@
 			dw_dst_depth = <2>;
 		};
 	};
-	pipline1 {
+	channel1 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <2>; //<2>=vivcam2 : gc5035
@@ -1186,7 +1195,7 @@
 			dw_dst_depth = <2>;
 		};
 	};
-	pipline2 {
+	channel2 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <2>; //<2>=vivcam2 : gc5035
@@ -1223,7 +1232,7 @@
 
 &video2{
     vi_mem_pool_region = <0>;	// vi_mem: framebuffer, region[0]
-    pipline0 {
+    channel0 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <0>; //vivcam0 sc2310
@@ -1243,7 +1252,7 @@
 			};
 		};
 	};
-	pipline1 {
+	channel1 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <0>; //vivcam0 sc2310
@@ -1263,7 +1272,7 @@
 			};
 		};
 	};
-	pipline2 {
+	channel2 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <0>; //vivcam0 sc2310
@@ -1287,7 +1296,7 @@
 
 &video3{
     vi_mem_pool_region = <0>;	// vi_mem: framebuffer, region[0]
-    pipline0 {
+    channel0 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <0>; //vivcam0 sc2310
@@ -1313,7 +1322,7 @@
 			dw_dst_depth = <2>;
 		};
 	};
-	pipline1 {
+	channel1 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <0>; //vivcam0 sc2310
@@ -1339,7 +1348,7 @@
 			dw_dst_depth = <2>;
 		};
 	};
-	pipline2 {
+	channel2 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <0>; //vivcam0 sc2310
@@ -1369,7 +1378,7 @@
 
 &video4{
     vi_mem_pool_region = <0>;	// vi_mem: framebuffer, region[0]
-    pipline0 {
+    channel0 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <0>; //vivcam0 sc2310
@@ -1411,7 +1420,7 @@
 			};
 		};
 	};
-	pipline1 {
+	channel1 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <0>; //vivcam0 sc2310
@@ -1453,7 +1462,7 @@
 			};
 		};
 	};
-	pipline2 {
+	channel2 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <0>; //vivcam0 sc2310
@@ -1499,7 +1508,7 @@
 
 &video5{
     vi_mem_pool_region = <0>;	// vi_mem: framebuffer, region[0]
-    pipline0 {
+    channel0 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <0>; //vivcam0 sc2310
@@ -1547,7 +1556,7 @@
 			dw_dst_depth = <2>;
 		};
 	};
-	pipline1 {
+	channel1 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <0>; //vivcam0 sc2310
@@ -1595,7 +1604,7 @@
 			dw_dst_depth = <2>;
 		};
 	};
-	pipline2 {
+	channel2 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <0>; //vivcam0 sc2310
@@ -1647,7 +1656,7 @@
 
 &video6{
 	vi_mem_pool_region = <1>;	// vi_mem: framebuffer, region[1]
-    pipline0 {
+    channel0 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <1>; // vivcam1 sc132gs
@@ -1665,7 +1674,7 @@
 			};
 		};
 	};
-	pipline1 {
+	channel1 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <1>; //vivcam1 sc132gs
@@ -1687,7 +1696,7 @@
 };
 
 &video7{
-	pipline0 {
+	channel0 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <2>; //<2>=vivcam2 : gc5035
@@ -1742,7 +1751,7 @@
 			dw_dst_depth = <2>;
 		};
 	};
-	pipline1 {
+	channel1 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <2>; //<2>=vivcam2 : gc5035
@@ -1797,7 +1806,7 @@
 			dw_dst_depth = <2>;
 		};
 	};
-	pipline2 {
+	channel2 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <2>; //<2>=vivcam2 : gc5035
@@ -1857,7 +1866,7 @@
 
 &video8{
 	vi_mem_pool_region = <1>;	// vi_mem: framebuffer, region[1]
-	pipline0 {
+	channel0 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <2>; //<2>=vivcam2 : gc5035
@@ -1887,7 +1896,7 @@
 };
 
 &video9{
-	pipline0 {
+	channel0 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <1>; //vivcam1 sc132gs
@@ -1908,7 +1917,7 @@
 
 
 &video10{ // TUNINGTOOL
-	pipline0 {
+	channel0 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <2>; //<2>=vivcam2 : gc5035
@@ -1929,8 +1938,8 @@
 };
 
 &video11{
-	pipline0 { 
+	channel0 { 
-		pipline_id = <0>;
+		channel_id = <0>;
 		status = "okay";
 		sensor0 {
 			subdev_name = "vivcam";
@@ -1955,7 +1964,7 @@
 };
 
 &video12{ // TUNINGTOOL
-	pipline0 { // CSI2
+	channel0 { // CSI2
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <0>; //sc2310
@@ -2091,6 +2100,11 @@
 
 &lightsound {
         status = "okay";
+        simple-audio-card,widgets = "Speaker", "Speaker";
+        simple-audio-card,routing = 
+        	"Speaker", "AW87519 VO",
+        	"AW87519 IN", "ES8156 ROUT";
+        simple-audio-card,aux-devs = <&audio_aw87519_pa>;
         simple-audio-card,dai-link@0 {          /* I2S - AUDIO SYS CODEC 8156*/
                 reg = <0>;
                 format = "i2s";
@@ -2105,7 +2119,7 @@
                 reg = <1>;
                 format = "i2s";
                 cpu {
-                        sound-dai = <&i2s3 0>;
+                        sound-dai = <&i2s_8ch_sd2 2>;
                 };
                 codec {
                         sound-dai = <&es7210_audio_codec>;
@@ -2118,7 +2132,7 @@
                         sound-dai = <&light_i2s 1>;
                 };
                 codec {
-                        sound-dai = <&dummy_codec 2>;
+                        sound-dai = <&dummy_codec>;
                 };
         };
 };
@@ -2135,7 +2149,7 @@
         status = "okay";
 };
 
-&i2s3 {
+&i2s_8ch_sd2 {
         status = "okay";
 };
 

arch/riscv/boot/dts/thead/light-ant-ref.dts

@@ -15,7 +15,7 @@
 
 	memory@0 {
 		device_type = "memory";
-		reg = <0x0 0x00000000 0x0 0x80000000>;
+		reg = <0x0 0x200000 0x0 0x7fe00000>;
 	};
 
 	chosen {
@@ -166,6 +166,14 @@
 		iopmp_dsp1: IOPMP_DSP1 {
 			is_default_region;
 		};
+
+		iopmp_audio0: IOPMP_AUDIO0 {
+			is_default_region;
+		};
+
+		iopmp_audio1: IOPMP_AUDIO1 {
+			is_default_region;
+		};
 	};
 
 	mbox_910t_client1: mbox_910t_client1 {
@@ -194,9 +202,10 @@
 	};
 
 	dummy_codec: dummy_codec {
-		#sound-dai-cells = <1>;
+		#sound-dai-cells = <0>;
-		compatible = "linux,bt-sco";
+		compatible = "thead,light-dummy-pcm";
 		status = "okay";
+		sound-name-prefix = "DUMMY";
 	};
 
 	reg_vref_1v8: regulator-adc-verf {
@@ -238,7 +247,8 @@
 
 	gpio-keys {
 		compatible = "gpio-keys";
-		pinctrl-0 = <&pinctrl_volume>;
+		pinctrl-0 = <&pinctrl_volume_up
+				&pinctrl_volume_down>;
 		pinctrl-names = "default";
 		key-volumedown {
 			label = "Volume Down Key";
@@ -578,7 +588,7 @@
                irq-gpios = <&gpio1_porta 8 0>;
                reset-gpios = <&gpio1_porta 7 0>;
                AVDD28-supply = <&reg_tp_pwr_en>;
-               touchscreen-size-x = <720>;
+               touchscreen-size-x = <800>;
                touchscreen-size-y = <1280>;
        };
 
@@ -592,18 +602,25 @@
                 #sound-dai-cells = <0>;
                 compatible = "everest,es8156";
                 reg = <0x08>;
+                sound-name-prefix = "ES8156";
+                AVDD-supply = <&soc_aud_3v3_en_reg>;
+                DVDD-supply = <&soc_aud_1v8_en_reg>;
+                PVDD-supply = <&soc_aud_1v8_en_reg>;
         };
 
         es7210_audio_codec: es7210@40 {
                 #sound-dai-cells = <0>;
                 compatible = "MicArray_0";
                 reg = <0x40>;
+                sound-name-prefix = "ES7210";
+                status = "disabled";
         };
 
-	audio_aw87519_pa@58 {
+        audio_aw87519_pa: amp@58 {
                 compatible = "awinic,aw87519_pa";
                 reg = <0x58>;
                 reset-gpio = <&ao_gpio4_porta 9 0x1>;
+                sound-name-prefix = "AW87519";
                 status = "okay";
         };
 };
@@ -738,6 +755,7 @@
 	no-mmc;
 	non-removable;
 	io_fixed_1v8;
+	rxclk-sample-delay = <80>;
 	post-power-on-delay-ms = <50>;
 	wprtn_ignore;
 	cap-sd-highspeed;
@@ -780,7 +798,7 @@
 				>;
 			};
 
-			pinctrl_audio_i2s0: i2s0grp {
+			pinctrl_light_i2s0: i2s0grp {
 				thead,pins = <
 					FM_QSPI0_SCLK    0x2    0x208
 					FM_QSPI0_CSN0    0x2    0x238
@@ -797,6 +815,12 @@
 					FM_GPIO3_2	0x1	0x208	/* pwm0 */
 				>;
 			};
+
+			pinctrl_volume_up: volume_up_grp {
+				thead,pins = <
+					FM_GPIO2_25   0x0     0x238
+				>;
+			};
 		};
 };
 
@@ -842,9 +866,9 @@
 				>;
 			};
 
-			pinctrl_volume: volume_grp {
+			pinctrl_volume_down: volume_down_grp {
 				thead,pins = <
-					FM_CLK_OUT_2  0x3     0x208
+					FM_CLK_OUT_2  0x3     0x238
 				>;
 			};
 		};
@@ -1008,6 +1032,7 @@
 &vvcam_sensor2 {
 	sensor_name = "GC5035";
 	sensor_regulators = "DOVDD18_SCAN", "DVDD12_SCAN", "AVDD28_SCAN";
+	sensor_regulator_voltage_uV = <1800000 1200000 2800000>;
 	sensor_regulator_timing_us = <100 50 0>;
 	sensor_pdn = <&gpio1_porta 30 0>; //powerdown pin / shutdown pin 
 	sensor_rst = <&gpio1_porta 29 0>;
@@ -1025,6 +1050,7 @@
 &vvcam_sensor3 {
 	sensor_name = "GC02M1B";
 	sensor_regulators = "DOVDD18_SCAN", "DVDD12_SCAN", "AVDD28_SCAN";
+	sensor_regulator_voltage_uV = <1800000 1800000 2800000>;
 	sensor_regulator_timing_us = <100 50 0>;
 	sensor_pdn = <&gpio1_porta 30 0>; //powerdown pin / shutdown pin 
 	sensor_rst = <&gpio1_porta 29 0>;
@@ -1041,7 +1067,7 @@
 
 &video0{
     vi_mem_pool_region = <2>;	// vi_mem: framebuffer, region[2]
-    pipline0 {
+    channel0 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <2>; //<2>=vivcam2 : gc5035
@@ -1071,7 +1097,7 @@
 			};
 		};
 	};
-	pipline1 {
+	channel1 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <2>; //<2>=vivcam2 : gc5035
@@ -1101,7 +1127,7 @@
 			};
 		};
 	};
-	pipline2 {
+	channel2 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <2>; //<2>=vivcam2 : gc5035
@@ -1136,7 +1162,7 @@
 
 &video1{
     vi_mem_pool_region = <2>;	// vi_mem: framebuffer, region[2]
-    pipline0 {
+    channel0 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <2>; //<2>=vivcam2 : gc5035
@@ -1173,7 +1199,7 @@
 			dw_dst_depth = <2>;
 		};
 	};
-	pipline1 {
+	channel1 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <2>; //<2>=vivcam2 : gc5035
@@ -1210,7 +1236,7 @@
 			dw_dst_depth = <2>;
 		};
 	};
-	pipline2 {
+	channel2 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <2>; //<2>=vivcam2 : gc5035
@@ -1251,7 +1277,7 @@
 
 &video2{
     vi_mem_pool_region = <0>;	// vi_mem: framebuffer, region[0]
-    pipline0 {
+    channel0 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <0>; //vivcam0 sc2310
@@ -1274,7 +1300,7 @@
 			};
 		};
 	};
-	pipline1 {
+	channel1 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <0>; //vivcam0 sc2310
@@ -1297,7 +1323,7 @@
 			};
 		};
 	};
-	pipline2 {
+	channel2 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <0>; //vivcam0 sc2310
@@ -1324,7 +1350,7 @@
 
 &video3{
     vi_mem_pool_region = <0>;	// vi_mem: framebuffer, region[0]
-    pipline0 {
+    channel0 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <0>; //vivcam0 sc2310
@@ -1353,7 +1379,7 @@
 			dw_dst_depth = <2>;
 		};
 	};
-	pipline1 {
+	channel1 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <0>; //vivcam0 sc2310
@@ -1382,7 +1408,7 @@
 			dw_dst_depth = <2>;
 		};
 	};
-	pipline2 {
+	channel2 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <0>; //vivcam0 sc2310
@@ -1415,7 +1441,7 @@
 
 &video4{
     vi_mem_pool_region = <0>;	// vi_mem: framebuffer, region[0]
-    pipline0 {
+    channel0 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <0>; //vivcam0 sc2310
@@ -1460,7 +1486,7 @@
 			};
 		};
 	};
-	pipline1 {
+	channel1 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <0>; //vivcam0 sc2310
@@ -1505,7 +1531,7 @@
 			};
 		};
 	};
-	pipline2 {
+	channel2 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <0>; //vivcam0 sc2310
@@ -1554,7 +1580,7 @@
 
 &video5{
     vi_mem_pool_region = <0>;	// vi_mem: framebuffer, region[0]
-    pipline0 {
+    channel0 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <0>; //vivcam0 sc2310
@@ -1605,7 +1631,7 @@
 			dw_dst_depth = <2>;
 		};
 	};
-	pipline1 {
+	channel1 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <0>; //vivcam0 sc2310
@@ -1656,7 +1682,7 @@
 			dw_dst_depth = <2>;
 		};
 	};
-	pipline2 {
+	channel2 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <0>; //vivcam0 sc2310
@@ -1711,7 +1737,7 @@
 
 &video6{
 	vi_mem_pool_region = <1>;	// vi_mem: framebuffer, region[1]
-    pipline0 {
+    channel0 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <1>; // vivcam1 sc132gs
@@ -1729,7 +1755,7 @@
 			};
 		};
 	};
-	pipline1 {
+	channel1 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <1>; //vivcam1 sc132gs
@@ -1751,7 +1777,7 @@
 };
 
 &video7{
-	pipline0 {
+	channel0 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <2>; //<2>=vivcam2 : gc5035
@@ -1810,7 +1836,7 @@
 			dw_dst_depth = <2>;
 		};
 	};
-	pipline1 {
+	channel1 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <2>; //<2>=vivcam2 : gc5035
@@ -1869,7 +1895,7 @@
 			dw_dst_depth = <2>;
 		};
 	};
-	pipline2 {
+	channel2 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <2>; //<2>=vivcam2 : gc5035
@@ -1933,7 +1959,7 @@
 
 &video8{
 	vi_mem_pool_region = <1>;	// vi_mem: framebuffer, region[1]
-	pipline0 {
+	channel0 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <2>; //<2>=vivcam2 : gc5035
@@ -1966,7 +1992,7 @@
 };
 
 &video9{
-	pipline0 {
+	channel0 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <1>; //vivcam1 sc132gs
@@ -1987,7 +2013,7 @@
 
 
 &video10{ // TUNINGTOOL
-	pipline0 {
+	channel0 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <2>; //<2>=vivcam2 : gc5035
@@ -2011,8 +2037,8 @@
 };
 
 &video11{
-	pipline0 { 
+	channel0 { 
-		pipline_id = <0>;
+		channel_id = <0>;
 		status = "okay";
 		sensor0 {
 			subdev_name = "vivcam";
@@ -2037,7 +2063,7 @@
 };
 
 &video12{ // TUNINGTOOL
-	pipline0 { // CSI2
+	channel0 { // CSI2
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <0>; //sc2310
@@ -2046,25 +2072,18 @@
 			path_type = "SENSOR_1920X1088_30FPS_RAW12_LINER";
 			skip_init = <1>;
 		};
-		sensor1 {
-			subdev_name = "vivcam";
-			idx = <6>; //gc02m1b
-			csi_idx = <1>; //<1>=CSI2_B
-			mode_idx = <0>;
-			path_type = "SENSOR_1600x1200_RAW10_LINER";
-			skip_init = <1>;
-		};
-	};
 		dma {
 				path_type = "VIPRE_CSI1_ISP0";
 		};
+	};
+
 };
 
 &video13{
     status = "okay";
     //vi_mem_pool_region = <0>;
-    pipline0 {
+    channel0 {
-        pipline_id = <0>;
+        channel_id = <0>;
         status = "okay";
         sensor0 {
             subdev_name = "vivcam";
@@ -2095,8 +2114,8 @@
 &video14{
     vi_mem_pool_region = <2>;   // vi_mem: framebuffer, region[0]
     status = "okay";
-    pipline0 {
+    channel0 {
-        pipline_id = <0>;
+        channel_id = <0>;
         status = "okay";
         sensor0 {
             subdev_name = "vivcam";
@@ -2128,8 +2147,8 @@
 &video15{
     status = "okay";
     //vi_mem_pool_region = <0>;
-    pipline0 {
+    channel0 {
-        pipline_id = <0>;
+        channel_id = <0>;
         status = "okay";
         sensor0 {
             subdev_name = "vivcam";
@@ -2260,6 +2279,9 @@
 &hdmi_tx {
 	status = "okay";
 
+	max_width = /bits/ 16 <1280>;
+	max_height = /bits/ 16 <720>;
+
 	port@0 {
 		/* input */
 		hdmi_tx_in: endpoint {
@@ -2270,6 +2292,11 @@
 
 &lightsound {
         status = "okay";
+        simple-audio-card,widgets = "Speaker", "Speaker";
+        simple-audio-card,routing = 
+        	"Speaker", "AW87519 VO",
+        	"AW87519 IN", "ES8156 ROUT";
+        simple-audio-card,aux-devs = <&audio_aw87519_pa>;
         simple-audio-card,dai-link@0 {          /* I2S - AUDIO SYS CODEC 8156*/
                 reg = <0>;
                 format = "i2s";
@@ -2284,7 +2311,7 @@
                 reg = <1>;
                 format = "i2s";
                 cpu {
-                        sound-dai = <&i2s3 0>;
+                        sound-dai = <&i2s_8ch_sd2 2>;
                 };
                 codec {
                         sound-dai = <&es7210_audio_codec>;
@@ -2297,7 +2324,7 @@
                         sound-dai = <&light_i2s 1>;
                 };
                 codec {
-                        sound-dai = <&dummy_codec 2>;
+                        sound-dai = <&dummy_codec>;
                 };
         };
 };
@@ -2314,7 +2341,7 @@
         status = "okay";
 };
 
-&i2s3 {
+&i2s_8ch_sd2 {
         status = "okay";
 };
 

arch/riscv/boot/dts/thead/light-b-product-ddr1G.dts

@@ -11,7 +11,7 @@
 
 	memory@0 {
 		device_type = "memory";
-		reg = <0x0 0x00000000 0x0 0x40000000>;
+		reg = <0x0 0x200000 0x0 0x3fe00000>;
 	};
 };
 

arch/riscv/boot/dts/thead/light-b-product-sec.dts

@@ -5,7 +5,7 @@
 
 /dts-v1/;
 
-#include "light-b-product.dts"
+#include "light-b-audio-hdmi.dts"
 
 
 

arch/riscv/boot/dts/thead/light-b-product.dts

@@ -15,7 +15,7 @@
 
 	memory@0 {
 		device_type = "memory";
-		reg = <0x0 0x00000000 0x0 0x80000000>;
+		reg = <0x0 0x200000 0x0 0x7fe00000>;
 	};
 
 	chosen {
@@ -166,6 +166,14 @@
 		iopmp_dsp1: IOPMP_DSP1 {
 			is_default_region;
 		};
+
+		iopmp_audio0: IOPMP_AUDIO0 {
+			is_default_region;
+		};
+
+		iopmp_audio1: IOPMP_AUDIO1 {
+			is_default_region;
+		};
 	};
 
 	mbox_910t_client1: mbox_910t_client1 {
@@ -180,7 +188,8 @@
 		compatible = "thead,light-mbox-client";
 		mbox-names = "906";
 		mboxes = <&mbox_910t 2 0>;
-		status = "disabled";
+		audio-mbox-regmap = <&audio_mbox>;
+        status = "okay";
 	};
 
 	lightsound: lightsound@1 {
@@ -193,11 +202,26 @@
 		status = "disabled";
 	};
 
-	dummy_codec: dummy_codec {
+	light_rpmsg: light_rpmsg {
-		#sound-dai-cells = <1>;
+		compatible = "light,rpmsg-bus", "simple-bus";
-		compatible = "linux,bt-sco";
+		memory-region = <&rpmsgmem>;
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+		rpmsg: rpmsg{
+			vdev-nums = <1>;
+            reg = <0x0 0x1E000000 0 0x10000>;
+			compatible = "light,light-rpmsg";
 			status = "okay";
 		};
+	};
+
+	dummy_codec: dummy_codec {
+		#sound-dai-cells = <0>;
+		compatible = "thead,light-dummy-pcm";
+		status = "okay";
+		sound-name-prefix = "DUMMY";
+	};
 
 	reg_vref_1v8: regulator-adc-verf {
 			compatible = "regulator-fixed";
@@ -223,6 +247,7 @@
 		ref-clock-frequency = <24000000>;
 		keep_wifi_power_on;
 		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_wifi>;
 		wifi_chip_type = "rtl8723ds";
 		WIFI,poweren_gpio = <&gpio2_porta 29 0>;
 		WIFI,reset_n = <&gpio2_porta 24 0>;
@@ -231,7 +256,8 @@
 
 	wcn_bt: wireless-bluetooth {
 		compatible = "bluetooth-platdata";
-		pinctrl-names = "default", "rts_gpio";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_bt>;
 		BT,power_gpio    = <&gpio2_porta 25 0>;
 		status = "okay";
 	};
@@ -242,12 +268,14 @@
 		pinctrl-names = "default";
 		key-volumedown {
 			label = "Volume Down Key";
+			wakeup-source;
 			linux,code = <KEY_VOLUMEDOWN>;
 			debounce-interval = <1>;
 			gpios = <&ao_gpio_porta 11 0x1>;
 		};
 		key-volumeup {
 			label = "Volume Up Key";
+			wakeup-source;
 			linux,code = <KEY_VOLUMEUP>;
 			debounce-interval = <1>;
 			gpios = <&ao_gpio_porta 10 0x1>;
@@ -270,6 +298,8 @@
 			regulator-name = "soc_aud_3v3_en";
 			regulator-min-microvolt = <3300000>;
 			regulator-max-microvolt = <3300000>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_audio_3v3_en>;
 			gpio = <&ao_gpio_porta 7 1>;
 			enable-active-high;
 			regulator-always-on;
@@ -280,6 +310,8 @@
 			regulator-name = "soc_aud_1v8_en";
 			regulator-min-microvolt = <1800000>;
 			regulator-max-microvolt = <1800000>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_audio_1v8_en>;
 			gpio = <&ao_gpio_porta 8 1>;
 			enable-active-high;
 			regulator-always-on;
@@ -569,7 +601,14 @@
 		reg = <0x0 0x17000000 0 0x02000000>;
 		no-map;
 	};
-
+	audio_mem: memory@32000000 {
+		reg = <0x0 0x32000000 0x0 0x6400000>;
+		no-map;
+    };
+	rpmsgmem: memory@1E000000 {
+		reg = <0x0 0x1E000000 0x0 0x10000>;
+		no-map;
+	};
 
 };
 
@@ -591,7 +630,7 @@
                irq-gpios = <&gpio1_porta 8 0>;
                reset-gpios = <&gpio1_porta 7 0>;
                AVDD28-supply = <&reg_tp_pwr_en>;
-               touchscreen-size-x = <720>;
+               touchscreen-size-x = <800>;
                touchscreen-size-y = <1280>;
        };
 
@@ -600,23 +639,43 @@
 &audio_i2c0 {
         clock-frequency = <100000>;
         status = "okay";
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_audiopa6>,
+                    <&pinctrl_audiopa7>,
+                    <&pinctrl_audio_i2c0>;
 
         es8156_audio_codec: es8156@8 {
                 #sound-dai-cells = <0>;
                 compatible = "everest,es8156";
                 reg = <0x08>;
+                sound-name-prefix = "ES8156";
+                AVDD-supply = <&soc_aud_3v3_en_reg>;
+                DVDD-supply = <&soc_aud_1v8_en_reg>;
+                PVDD-supply = <&soc_aud_1v8_en_reg>;
+                mclk-sclk-ratio = <4>;
         };
 
         es7210_audio_codec: es7210@40 {
                 #sound-dai-cells = <0>;
                 compatible = "MicArray_0";
                 reg = <0x40>;
+                work-mode = "ES7210_NORMAL_I2S";
+                channels-max = <2>;
+				mclk-sclk-ratio = <4>;
+                sound-name-prefix = "ES7210_ADC0";
+                MVDD-supply = <&soc_aud_3v3_en_reg>;
+                AVDD-supply = <&soc_aud_3v3_en_reg>;
+                DVDD-supply = <&soc_aud_1v8_en_reg>;
+                PVDD-supply = <&soc_aud_1v8_en_reg>;
         };
 
-	audio_aw87519_pa@58 {
+	audio_aw87519_pa: amp@58 {
 		compatible = "awinic,aw87519_pa";
 		reg = <0x58>;
+		pingctrl-names = "default";
+		pinctrl-0 = <&pinctrl_audio_pa_rst0>;
 		reset-gpio = <&ao_gpio4_porta 9 0x1>;
+		sound-name-prefix = "AW87519";
 		status = "okay";
 	};
 };
@@ -652,6 +711,23 @@
 
 &uart0 {
 	clock-frequency = <100000000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart0>;
+};
+
+&uart1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart1>;
+};
+
+&uart3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart3>;
+};
+
+&uart4 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart4>;
 };
 
 &qspi0 {
@@ -697,6 +773,8 @@
 	tx-clk-delay = <0x00>; /* for RGMII */
 	phy-handle = <&phy_88E1111_0>;
 	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_gmac0>;
 
 	mdio0 {
 		#address-cells = <1>;
@@ -740,6 +818,8 @@
 	pull_up;
 	wprtn_ignore;
 	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_sdio0>;
 };
 
 &sdhci1 {
@@ -750,6 +830,7 @@
 	no-mmc;
 	non-removable;
 	io_fixed_1v8;
+	rxclk-sample-delay = <80>;
 	post-power-on-delay-ms = <50>;
 	wprtn_ignore;
 	cap-sd-highspeed;
@@ -766,17 +847,8 @@
 			 */
 			pinctrl_uart0: uart0grp {
 				thead,pins = <
-					FM_UART0_TXD	0x0	0x72
+					FM_UART0_TXD	0x0	0x234
-					FM_UART0_RXD	0x0	0x72
+					FM_UART0_RXD	0x0	0x234
-				>;
-			};
-
-			pinctrl_spi0: spi0grp {
-				thead,pins = <
-					FM_SPI_CSN	0x3	0x20a
-					FM_SPI_SCLK	0x0	0x20a
-					FM_SPI_MISO	0x0	0x23a
-					FM_SPI_MOSI	0x0	0x23a
 				>;
 			};
 
@@ -792,7 +864,7 @@
 				>;
 			};
 
-			pinctrl_audio_i2s0: i2s0grp {
+			pinctrl_light_i2s0: i2s0grp {
 				thead,pins = <
 					FM_QSPI0_SCLK    0x2    0x208
 					FM_QSPI0_CSN0    0x2    0x238
@@ -804,9 +876,81 @@
 				>;
 			};
 
+			pinctrl_i2c2: i2c2grp {
+				thead,pins = <
+					FM_I2C2_SCL	0x0	0x204
+					FM_I2C2_SDA	0x0	0x204
+				>;
+			};
+
+			pinctrl_i2c3: i2c3grp {
+				thead,pins = <
+					FM_I2C3_SCL	0x0	0x204
+					FM_I2C3_SDA	0x0	0x204
+				>;
+			};	
+
+			pinctrl_spi0: spi0grp {
+				thead,pins = <
+					FM_SPI_CSN	0x3	0x20a
+					FM_SPI_SCLK	0x0	0x20a
+					FM_SPI_MISO	0x0	0x23a
+					FM_SPI_MOSI	0x0	0x23a
+				>;
+			};
+
+			pinctrl_wifi: wifi_grp {
+				thead,pins = <
+					FM_GPIO2_22	0x0	0x202
+					FM_GPIO2_24	0x0	0x202
+				>;
+			};
+
+			pinctrl_bt: bt_grp {
+				thead,pins = <
+					FM_GPIO2_23	0x0	0x202
+					FM_GPIO2_25	0x0	0x202
+				>;
+			};
+
+			pinctrl_sdio0: sdio0grp {
+				thead,pins = <
+					FM_SDIO0_DETN	0x0	0x208
+				>;
+			};
+
 			pinctrl_pwm: pwmgrp {
 				thead,pins = <
-					FM_GPIO3_2	0x1	0x208	/* pwm0 */
+					FM_GPIO3_2	0x1	0x20f	/* pwm0 */
+				>;
+			};
+
+			pinctrl_hdmi: hdmigrp {
+				thead,pins = <
+					FM_HDMI_SCL	0x0	0x208
+					FM_HDMI_SDA	0x0	0x208
+					FM_HDMI_CEC	0x0	0x208
+				>;
+			};
+
+			pinctrl_gmac0: gmac0grp {
+				thead,pins = <
+					FM_GMAC0_TX_CLK	0x0	0x20f	/*	GMAC0_TX_CLK  */
+					FM_GMAC0_RX_CLK	0x0	0x20f	/*	GMAC0_RX_CLK  */
+					FM_GMAC0_TXEN	0x0	0x20f	/*	GMAC0_TXEN  */
+					FM_GMAC0_TXD0	0x0	0x20f	/*	GMAC0_TXD0  */
+					FM_GMAC0_TXD1	0x0	0x20f	/*	GMAC0_TXD1  */
+					FM_GMAC0_TXD2	0x0	0x20f	/*	GMAC0_TXD2  */
+					FM_GMAC0_TXD3	0x0	0x20f	/*	GMAC0_TXD3  */
+					FM_GMAC0_RXDV	0x0	0x20f	/*	GMAC0_RXDV  */
+					FM_GMAC0_RXD0	0x0	0x20f	/*	GMAC0_RXD0  */
+					FM_GMAC0_RXD1	0x0	0x20f	/*	GMAC0_RXD1  */
+					FM_GMAC0_RXD2	0x0	0x20f	/*	GMAC0_RXD2  */
+					FM_GMAC0_RXD3	0x0	0x20f	/*	GMAC0_RXD3  */
+					FM_GMAC0_MDC	0x0 0x208	/*	GMAC0_MDC  */
+					FM_GMAC0_MDIO	0x0 0x208	/*	GMAC0_MDIO  */
+					FM_GMAC0_COL	0x3	0x232	/*	PHY0_nRST  */
+					FM_GMAC0_CRS	0x3	0x232	/*	PHY0_nINT  */
 				>;
 			};
 		};
@@ -818,22 +962,6 @@
 			 * Pin Configuration Node:
 			 * Format: <pin_id mux_node config>
 			 */
-			pinctrl_uart3: uart3grp {
-				thead,pins = <
-					FM_UART3_TXD	0x0	0x72
-					FM_UART3_RXD	0x0	0x72
-				>;
-			};
-
-			pinctrl_uart4: uart4grp {
-				thead,pins = <
-					FM_UART4_TXD	0x0	0x72
-					FM_UART4_RXD	0x0	0x72
-					FM_UART4_CTSN	0x0	0x72
-					FM_UART4_RTSN	0x0	0x72
-				>;
-			};
-
 			pinctrl_qspi1: qspi1grp {
 				thead,pins = <
 					FM_QSPI1_SCLK    0x0    0x20a
@@ -845,7 +973,6 @@
 				>;
 			};
 
-
 			pinctrl_iso7816: iso7816grp {
 				thead,pins = <
 					FM_QSPI1_SCLK		0x1	0x208
@@ -856,6 +983,49 @@
 				>;
 			};
 
+			pinctrl_i2c0: i2c0grp {
+				thead,pins = <
+					FM_I2C0_SCL	0x0	0x204
+					FM_I2C0_SDA	0x0	0x204
+				>;
+			};
+
+			pinctrl_i2c1: i2c1grp {
+				thead,pins = <
+					FM_I2C1_SCL	0x0	0x204
+					FM_I2C1_SDA	0x0	0x204
+				>;
+			};
+
+			pinctrl_uart1: uart1grp {
+ 				thead,pins = <
+					FM_UART1_TXD	0x0	0x234
+					FM_UART1_RXD	0x0	0x234
+				>;
+			};
+
+			pinctrl_uart4: uart4grp {
+				thead,pins = <
+					FM_UART4_TXD	0x0	0x208
+					FM_UART4_RXD	0x0	0x208
+					FM_UART4_CTSN	0x0	0x208
+					FM_UART4_RTSN	0x0	0x208
+				>;
+			};
+
+			pinctrl_uart3: uart3grp {
+				thead,pins = <
+					FM_UART3_TXD	0x1	0x202
+					FM_UART3_RXD	0x1	0x202
+				>;
+			};
+
+			pinctrl_i2c4: i2c4grp {
+				thead,pins = <
+					FM_GPIO0_18	0x1	0x204	/*	I2C4_SCL  */
+					FM_GPIO0_19	0x1	0x204	/*	I2C4_SDA  */
+				>;
+			};
 		};
 };
 
@@ -866,50 +1036,136 @@
 			 * Format: <pin_id mux_node config>
 			 */
 
-			pinctrl_audiopa1: audiopa1_grp {
+			pinctrl_audiopa0: audiopa0 {
-				thead,pins = <
+				thead,pins = < FM_AUDIO_PA0 LIGHT_PIN_FUNC_0 0x000 >;
-					FM_AUDIO_PA1	0x3	0x72
-				>;
 			};
-
+			pinctrl_audiopa1: audiopa1 {
-			pinctrl_audiopa2: audiopa2_grp {
+				thead,pins = < FM_AUDIO_PA1 LIGHT_PIN_FUNC_0 0x000 >;
-				thead,pins = <
+			};
-					FM_AUDIO_PA2	0x0	0x72
+			pinctrl_audiopa2: audiopa2 {
-				>;
+				thead,pins = < FM_AUDIO_PA2 LIGHT_PIN_FUNC_0 0x000 >;
+			};
+			pinctrl_audiopa3: audiopa3 {
+				thead,pins = < FM_AUDIO_PA3 LIGHT_PIN_FUNC_0 0x000 >;
+			};
+			pinctrl_audiopa6: audiopa6 {
+				thead,pins = < FM_AUDIO_PA6 LIGHT_PIN_FUNC_0 0x000 >;
+			};
+			pinctrl_audiopa7: audiopa7 {
+				thead,pins = < FM_AUDIO_PA7 LIGHT_PIN_FUNC_0 0x000 >;
+			};
+			pinctrl_audiopa8: audiopa8 {
+				thead,pins = < FM_AUDIO_PA8 LIGHT_PIN_FUNC_0 0x000 >;
+			};
+			pinctrl_audio_pa_rst0: audio_pa_rst0 {
+				thead,pins = < FM_AUDIO_PA9 LIGHT_PIN_FUNC_3 0x000 >;
+			};
+			pinctrl_audiopa13: audiopa13 {
+				thead,pins = < FM_AUDIO_PA13 LIGHT_PIN_FUNC_0 0x000 >;
+			};
+			pinctrl_audiopa14: audiopa14 {
+				thead,pins = < FM_AUDIO_PA14 LIGHT_PIN_FUNC_0 0x000 >;
+			};
+			pinctrl_audiopa15: audiopa15 {
+				thead,pins = < FM_AUDIO_PA15 LIGHT_PIN_FUNC_0 0x000 >;
+			};
+			pinctrl_audiopa17: audiopa17 {
+				thead,pins = < FM_AUDIO_PA17 LIGHT_PIN_FUNC_0 0x000 >;
+			};
+			pinctrl_audio_3v3_en: audio_3v3_en {
+				thead,pins = < FM_AOGPIO_7 LIGHT_PIN_FUNC_3 0x008 >;
+			};
+			pinctrl_audio_1v8_en: audio_1v8_en {
+				thead,pins = < FM_AOGPIO_8 LIGHT_PIN_FUNC_3 0x008 >;
 			};
 
 			pinctrl_volume: volume_grp {
 				thead,pins = <
-					FM_AOGPIO_11  0x0     0x208
+					FM_AOGPIO_11  0x0     0x238
-					FM_AOGPIO_10  0x3     0x208
+					FM_AOGPIO_10  0x3     0x238
 				>;
 			};
 	};
 };
 
+&padctrl_audiosys {
+
+	status = "okay";
+
+	light-audio-padctrl {
+			/*
+			 * Pin Configuration Node:
+			 * Format: <pin_id mux_node config>
+			 */
+
+			pinctrl_audio_i2c0: audio_i2c0_grp {
+				thead,pins = <
+					FM_AUDIO_IO_PA6		LIGHT_PIN_FUNC_0 0x004
+					FM_AUDIO_IO_PA7		LIGHT_PIN_FUNC_0 0x004
+				>;
+			};
+			pinctrl_audio_i2s1: audio_i2s1_grp {
+				thead,pins = <
+					FM_AUDIO_IO_PA13   LIGHT_PIN_FUNC_0 0x008
+					FM_AUDIO_IO_PA14   LIGHT_PIN_FUNC_0 0x008
+					FM_AUDIO_IO_PA15   LIGHT_PIN_FUNC_0 0x008
+					FM_AUDIO_IO_PA17   LIGHT_PIN_FUNC_0 0x008
+				>;
+			};
+			pinctrl_audio_i2s_8ch_bus: audio_i2s_8ch_bus_grp {
+				thead,pins = <
+					FM_AUDIO_IO_PA2	  LIGHT_PIN_FUNC_3 0x008
+					FM_AUDIO_IO_PA3   LIGHT_PIN_FUNC_3 0x008
+					FM_AUDIO_IO_PA8   LIGHT_PIN_FUNC_3 0x008
+				>;
+			};
+			pinctrl_audio_i2s_8ch_sd2: audio_i2s_8ch_sd2_grp {
+				thead,pins = <
+					FM_AUDIO_IO_PA0	  LIGHT_PIN_FUNC_3 0x008
+				>;
+			};
+			pinctrl_audio_i2s_8ch_sd3: audio_i2s_8ch_sd3_grp {
+				thead,pins = <
+					FM_AUDIO_IO_PA1   LIGHT_PIN_FUNC_3 0x008
+				>;
+			};
+	};
+};
+
+
 &i2c0 {
 	clock-frequency = <400000>;
 	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c0>;
 };
 
 &i2c1 {
 	clock-frequency = <400000>;
 	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c1>;
 };
 
 &i2c2 {
 	clock-frequency = <400000>;
 	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c2>;
 };
 
 &i2c3 {
 	clock-frequency = <400000>;
 	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c3>;
 };
 
 &i2c4 {
 	clock-frequency = <400000>;
 	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c4>;
 };
 
 &isp0 {
@@ -1000,31 +1256,22 @@
 	status = "okay";
 };
 
-/*
+&vvcam_sensor1 {
-&vvcam_sensor0 {
+       sensor_name = "OV5693";
-	sensor_name = "IMX334";
        sensor_regulators = "DOVDD18_RGB", "DVDD12_RGB", "AVDD28_RGB";
+       sensor_regulator_voltage_uV = <1800000 1200000 2800000>;
        sensor_regulator_timing_us = <70 50 20>;
        sensor_rst = <&gpio1_porta 16 0>;
-	sensor_pdn_delay_us = <1000>; //powerdown pin / shutdown pin actived till I2C ready
+       sensor_pdn_delay_us = <4000>; //powerdown pin / shutdown pin actived till I2C ready
        DOVDD18_RGB-supply = <&soc_dovdd18_rgb_reg>;
        DVDD12_RGB-supply = <&soc_dvdd12_rgb_reg>;
        AVDD28_RGB-supply = <&soc_avdd28_rgb_reg>;
     i2c_reg_width = /bits/ 8 <2>;
     i2c_data_width = /bits/ 8 <1>;
-    i2c_addr = /bits/ 8 <0x1a>;
+    i2c_addr = /bits/ 8 <0x36>;
        i2c_bus = /bits/ 8 <3>;
        status = "okay";
 };
-*/
-
-&vvcam_sensor1 {
-	sensor_name = "OV5693";
-	i2c_bus = /bits/ 8 <3>;
-	i2c_reg_width = /bits/ 8 <1>;
-	i2c_data_width = /bits/ 8 <1>;
-	status = "disabled";
-};
 
 &vvcam_sensor2 {
 	sensor_name = "GC5035";
@@ -1054,6 +1301,9 @@
 	DVDD12_SCAN-supply = <&soc_dvdd12_scan_reg>;
 	AVDD28_SCAN-supply = <&soc_avdd28_scan_en_reg>;
 	i2c_bus = /bits/ 8 <4>;
+    i2c_reg_width = /bits/ 8 <2>;
+    i2c_data_width = /bits/ 8 <1>;
+    i2c_addr = /bits/ 8 <0x30>;
 	status = "okay";
 };
 
@@ -1105,9 +1355,26 @@
 	status = "okay";
 };
 
+&vvcam_sensor7 {
+    sensor_name = "IMX334";
+    sensor_regulators = "DOVDD18_RGB", "DVDD12_RGB", "AVDD28_RGB";
+    sensor_regulator_timing_us = <70 50 20>;
+    sensor_rst = <&gpio1_porta 16 0>;
+    sensor_pdn_delay_us = <1000>; //powerdown pin / shutdown pin actived till I2C ready
+    DOVDD18_RGB-supply = <&soc_dovdd18_rgb_reg>;
+    DVDD12_RGB-supply = <&soc_dvdd12_rgb_reg>;
+    AVDD28_RGB-supply = <&soc_avdd28_rgb_reg>;
+	i2c_reg_width = /bits/ 8 <2>;
+    i2c_data_width = /bits/ 8 <1>;
+    i2c_addr = /bits/ 8 <0x1a>;
+    i2c_bus = /bits/ 8 <3>;
+    status = "okay";
+};
+
 &video0{
+	status = "okay";
 	vi_mem_pool_region = <2>;	// vi_mem: framebuffer, region[2]
-	pipline0 {
+	channel0 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <2>; //<2>=vivcam2 : gc5035
@@ -1134,7 +1401,7 @@
 			};
 		};
 	};
-	pipline1 {
+	channel1 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <2>; //<2>=vivcam2 : gc5035
@@ -1161,7 +1428,7 @@
 			};
 		};
 	};
-	pipline2 {
+	channel2 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <2>; //<2>=vivcam2 : gc5035
@@ -1192,8 +1459,9 @@
 
 
 &video1{
+	status = "okay";
 	vi_mem_pool_region = <2>;	// vi_mem: framebuffer, region[2]
-	pipline0 {
+	channel0 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <2>; //<2>=vivcam2 : gc5035
@@ -1226,7 +1494,7 @@
 			dw_dst_depth = <2>;
 		};
 	};
-	pipline1 {
+	channel1 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <2>; //<2>=vivcam2 : gc5035
@@ -1259,7 +1527,7 @@
 			dw_dst_depth = <2>;
 		};
 	};
-	pipline2 {
+	channel2 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <2>; //<2>=vivcam2 : gc5035
@@ -1295,8 +1563,9 @@
 };
 
 &video2{
+	status = "okay";
     vi_mem_pool_region = <0>;	// vi_mem: framebuffer, region[0]
-	pipline0 {
+	channel0 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <0>; //sc2310
@@ -1323,7 +1592,7 @@
 			};
 		};
 	};
-	pipline1 {
+	channel1 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <0>; //sc2310
@@ -1350,7 +1619,7 @@
 			};
 		};
 	};
-	pipline2 {
+	channel2 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <0>; //sc2310
@@ -1380,8 +1649,9 @@
 };
 
 &video3{
+	status = "okay";
     vi_mem_pool_region = <0>;	// vi_mem: framebuffer, region[0]
-	pipline0 {
+	channel0 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <0>; //sc2310
@@ -1414,7 +1684,7 @@
 			dw_dst_depth = <2>;
 		};
 	};
-	pipline1 {
+	channel1 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <0>; //sc2310
@@ -1447,7 +1717,7 @@
 			dw_dst_depth = <2>;
 		};
 	};
-	pipline2 {
+	channel2 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <0>; //sc2310
@@ -1483,8 +1753,9 @@
 };
 
 &video4{
+	status = "okay";
     vi_mem_pool_region = <0>;	// vi_mem: framebuffer, region[0]
-	pipline0 {
+	channel0 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <0>; //sc2310
@@ -1533,7 +1804,7 @@
 			};
 		};
 	};
-	pipline1 {
+	channel1 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <0>; //sc2310
@@ -1582,7 +1853,7 @@
 			};
 		};
 	};
-	pipline2 {
+	channel2 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <0>; //sc2310
@@ -1634,8 +1905,9 @@
 };
 
 &video5{
+	status = "okay";
 	vi_mem_pool_region = <0>;	// vi_mem: framebuffer, region[0]
-	pipline0 {
+	channel0 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <0>; //sc2310
@@ -1690,7 +1962,7 @@
 			dw_dst_depth = <2>;
 		};
 	};
-	pipline1 {
+	channel1 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <0>; //sc2310
@@ -1745,7 +2017,7 @@
 			dw_dst_depth = <2>;
 		};
 	};
-	pipline2 {
+	channel2 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <0>; //sc2310
@@ -1803,8 +2075,9 @@
 };
 
 &video6{
+	status = "okay";
 	vi_mem_pool_region = <1>;	// vi_mem: framebuffer, region[1]
-	pipline0 {
+	channel0 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <4>; //sc132gs
@@ -1822,7 +2095,7 @@
 			};
 		};
 	};
-	pipline1 {
+	channel1 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <4>; //sc132gs
@@ -1844,7 +2117,8 @@
 };
 
 &video7{
-	pipline0 {
+	status = "okay";
+	channel0 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <2>; //<2>=vivcam2 : gc5035
@@ -1899,7 +2173,7 @@
 			dw_dst_depth = <2>;
 		};
 	};
-	pipline1 {
+	channel1 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <2>; //<2>=vivcam2 : gc5035
@@ -1954,7 +2228,7 @@
 			dw_dst_depth = <2>;
 		};
 	};
-	pipline2 {
+	channel2 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <2>; //<2>=vivcam2 : gc5035
@@ -2013,8 +2287,9 @@
 
 
 &video8{
+	status = "okay";
 	vi_mem_pool_region = <1>;	// vi_mem: framebuffer, region[1]
-    pipline0 {
+    channel0 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <2>; //<2>=vivcam2 : gc5035
@@ -2044,7 +2319,8 @@
 };
 
 &video9{
-	pipline0 {
+	status = "okay";
+	channel0 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <4>; //sc132gs
@@ -2065,7 +2341,8 @@
 
 
 &video10{ // TUNINGTOOL
-	pipline0 {
+	status = "okay";
+	channel0 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <2>; //<2>=vivcam2 : gc5035
@@ -2086,8 +2363,9 @@
 };
 
 &video11{
-	pipline0 { 
+	status = "okay";
-		pipline_id = <0>;
+	channel0 { 
+		channel_id = <0>;
 		status = "okay";
 		sensor0 {
 			subdev_name = "vivcam";
@@ -2112,7 +2390,8 @@
 };
 
 &video12{ // TUNINGTOOL
-	pipline0 { // CSI2
+	status = "okay";
+	channel0 { // CSI2
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <0>; //sc2310
@@ -2133,10 +2412,11 @@
 };
 
 &video14{
+	status = "okay";
     vi_mem_pool_region = <2>;	// vi_mem: framebuffer, region[0]
 	status = "okay";
-	pipline0 {
+	channel0 {
-		pipline_id = <0>;
+		channel_id = <0>;
 		status = "okay";
         sensor0 {
 			subdev_name = "vivcam";
@@ -2168,8 +2448,8 @@
 &video15{
 	status = "okay";
 	//vi_mem_pool_region = <0>;
-	pipline0 {
+	channel0 {
-		pipline_id = <0>;
+		channel_id = <0>;
 		status = "okay";
         sensor0 {
 			subdev_name = "vivcam";
@@ -2299,6 +2579,8 @@
 
 &hdmi_tx {
 	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_hdmi>;
 
 	port@0 {
 		/* input */
@@ -2310,6 +2592,11 @@
 
 &lightsound {
         status = "okay";
+        simple-audio-card,widgets = "Speaker", "Speaker";
+        simple-audio-card,routing = 
+        	"Speaker", "AW87519 VO",
+        	"AW87519 IN", "ES8156 ROUT";
+        simple-audio-card,aux-devs = <&audio_aw87519_pa>;
         simple-audio-card,dai-link@0 {          /* I2S - AUDIO SYS CODEC 8156*/
                 reg = <0>;
                 format = "i2s";
@@ -2324,7 +2611,7 @@
                 reg = <1>;
                 format = "i2s";
                 cpu {
-                        sound-dai = <&i2s3 0>;
+                        sound-dai = <&i2s_8ch_sd2 2>;
                 };
                 codec {
                         sound-dai = <&es7210_audio_codec>;
@@ -2337,7 +2624,7 @@
                         sound-dai = <&light_i2s 1>;
                 };
                 codec {
-                        sound-dai = <&dummy_codec 2>;
+                        sound-dai = <&dummy_codec>;
                 };
         };
 };
@@ -2352,10 +2639,29 @@
 
 &i2s1 {
         status = "okay";
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_audiopa13>,
+                    <&pinctrl_audiopa14>,
+                    <&pinctrl_audiopa15>,
+                    <&pinctrl_audiopa17>,
+                    <&pinctrl_audio_i2s1>;
 };
 
-&i2s3 {
+&i2s_8ch_sd2 {
         status = "okay";
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_audiopa0>,
+                    <&pinctrl_audio_i2s_8ch_sd2>,
+                    <&pinctrl_audiopa2>,
+                    <&pinctrl_audiopa3>,
+                    <&pinctrl_audiopa8>,
+                    <&pinctrl_audio_i2s_8ch_bus>;
+};
+
+&i2s_8ch_sd3 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_audiopa1>,
+                    <&pinctrl_audio_i2s_8ch_sd3>;
 };
 
 &cpus {

arch/riscv/boot/dts/thead/light-beagle.dts

@@ -5,7 +5,7 @@
 
 /dts-v1/;
 
-#include "light-ant-ref.dts"
+#include "light-beagle-ref.dts"
 
 &vvcam_sensor4 { // beagle board J5 CSI0 connector
 	sensor_name = "IMX219";
@@ -30,13 +30,13 @@
 };
 
 /*
-sensor imx219 mounted on beagle board J4
+sensor imx219 mounted on beagle board J4 CSI1 (=light CSI2X2_A+CSI2X2_B   /   CSI2X2_A only)
 video0: sensor-vipre-isp0
 video1: sensor-vipre-isp0-dw
 video7: sensor-vipre-isp0-dsp1-ry-dw
 video10: tuningtool
 
-sensor imx219 mounted on beagle board J5
+sensor imx219 mounted on beagle board J5 CSI0 (=light CSI2)
 video2: sensor-vipre-isp1   
 video3: sensor-vipre-isp1-dw   
 video4: sensor-vipre-isp1-dsp0-ry
@@ -44,11 +44,108 @@ video5: sensor-vipre-isp1-dsp0-ry-dw
 video12: tuningtool
 */
 
+&video0{
+    vi_mem_pool_region = <0xFFFFFFFF>;	// vi_mem: framebuffer, region[2]
+    channel0 {
+		sensor0 {
+			subdev_name = "vivcam";
+			idx = <5>; // imx219
+			csi_idx = <2>; //<2>=CSI2X2_A
+			mode_idx = <0>;
+			path_type = "SENSOR_1080P_RAW10_LINER";
+		};
+		sensor1 {
+			subdev_name = "vivcam";
+			idx = <0xff>; // invalid
+			csi_idx = <0xff>;
+			path_type = "SENSOR_VGA_RAW10_LINER";
+		};
+        dma {
+			subdev_name = "vipre";
+			idx = <0>;
+			path_type = "VIPRE_CSI2_ISP0";
+		};
+		isp {
+			subdev_name = "isp";
+			idx = <0>;
+			path_type = "ISP_MI_PATH_MP";
+			output {
+				max_width = <1920>;
+				max_height = <1088>;
+				bit_per_pixel = <16>;
+				frame_count = <3>;
+			};
+		};
+	};
+	channel1 {
+		sensor0 {
+			subdev_name = "vivcam";
+			idx = <5>; // imx219
+			csi_idx = <2>; //<2>=CSI2X2_A
+			mode_idx = <0>;
+			path_type = "SENSOR_1080P_RAW10_LINER";
+		};
+		sensor1 {
+			subdev_name = "vivcam";
+			idx = <0xff>; // invalid
+			csi_idx = <0xff>;
+			path_type = "SENSOR_VGA_RAW10_LINER";
+		};
+        dma {
+			subdev_name = "vipre";
+			idx = <0>;
+			path_type = "VIPRE_CSI2_ISP0";
+		};
+		isp {
+			subdev_name = "isp";
+			idx = <0>;
+			path_type = "ISP_MI_PATH_SP";
+			output {
+				max_width = <1920>;
+				max_height = <1088>;
+				bit_per_pixel = <16>;
+				frame_count = <3>;
+			};
+		};
+	};
+	channel2 {
+		sensor0 {
+			subdev_name = "vivcam";
+			idx = <5>; // imx219
+			csi_idx = <2>; //<2>=CSI2X2_A
+			mode_idx = <0>;
+			path_type = "SENSOR_1080P_RAW10_LINER";
+		};
+		sensor1 {
+			subdev_name = "vivcam";
+			idx = <0xff>; // invalid
+			csi_idx = <0xff>;
+			path_type = "SENSOR_VGA_RAW10_LINER";
+		};
+        dma {
+			subdev_name = "vipre";
+			idx = <0>;
+			path_type = "VIPRE_CSI2_ISP0";
+		};
+		isp {
+			subdev_name = "isp";
+			idx = <0>;
+			path_type = "ISP_MI_PATH_SP2_BP";
+			output {
+				max_width = <1920>;
+				max_height = <1088>;
+				bit_per_pixel = <16>;
+				frame_count = <3>;
+			};
+		};
+	};
+};
+
 &video2 {
     vi_mem_pool_region = <0>;	// vi_mem: framebuffer, region[0]
 	status = "okay";
-	pipline0 {
+	channel0 {
-		pipline_id = <0>;
+		channel_id = <0>;
 		status = "okay";
 		sensor0 {
 			subdev_name = "vivcam";
@@ -80,8 +177,8 @@ video12: tuningtool
 			};
 		};
 	};
-	pipline1 {
+	channel1 {
-		pipline_id = <1>;
+		channel_id = <1>;
 		status = "okay";
 		sensor0 {
 			subdev_name = "vivcam";
@@ -113,8 +210,8 @@ video12: tuningtool
 			};
 		};
 	};
-	pipline2 {
+	channel2 {
-		pipline_id = <2>;
+		channel_id = <2>;
 		status = "okay";
 		sensor0 {
 			subdev_name = "vivcam";
@@ -150,7 +247,7 @@ video12: tuningtool
 
 &video3{
     vi_mem_pool_region = <0>;	// vi_mem: framebuffer, region[0]
-	pipline0 {
+	channel0 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <4>; // imx219
@@ -187,7 +284,7 @@ video12: tuningtool
 			dw_dst_depth = <2>;
 		};
 	};
-	pipline1 {
+	channel1 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <4>; // imx219
@@ -224,7 +321,7 @@ video12: tuningtool
 			dw_dst_depth = <2>;
 		};
 	};
-	pipline2 {
+	channel2 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <4>; // imx219
@@ -265,7 +362,7 @@ video12: tuningtool
 
 &video4{
     vi_mem_pool_region = <0>;	// vi_mem: framebuffer, region[0]
-	pipline0 {
+	channel0 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <4>; // imx219
@@ -318,7 +415,7 @@ video12: tuningtool
 			};
 		};
 	};
-	pipline1 {
+	channel1 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <4>; // imx219
@@ -371,7 +468,7 @@ video12: tuningtool
 			};
 		};
 	};
-	pipline2 {
+	channel2 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <4>; // imx219
@@ -428,7 +525,7 @@ video12: tuningtool
 
 &video5{
 	vi_mem_pool_region = <0>;	// vi_mem: framebuffer, region[0]
-	pipline0 {
+	channel0 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <4>; // imx219
@@ -487,7 +584,7 @@ video12: tuningtool
 			dw_dst_depth = <2>;
 		};
 	};
-	pipline1 {
+	channel1 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <4>; // imx219
@@ -546,7 +643,7 @@ video12: tuningtool
 			dw_dst_depth = <2>;
 		};
 	};
-	pipline2 {
+	channel2 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <4>; // imx219

arch/riscv/boot/dts/thead/light-crash.dts

@@ -163,6 +163,14 @@
 		iopmp_dsp1: IOPMP_DSP1 {
 			is_default_region;
 		};
+
+		iopmp_audio0: IOPMP_AUDIO0 {
+			is_default_region;
+		};
+
+		iopmp_audio1: IOPMP_AUDIO1 {
+			is_default_region;
+		};
 	};
 
 	mbox_910t_client1: mbox_910t_client1 {
@@ -191,8 +199,9 @@
 	};
 
 	dummy_codec: dummy_codec {
-		#sound-dai-cells = <1>;
+		#sound-dai-cells = <0>;
-		compatible = "linux,bt-sco";
+		compatible = "thead,light-dummy-pcm";
+		sound-name-prefix = "DUMMY";
 		status = "okay";
 	};
 
@@ -327,7 +336,7 @@
                irq-gpios = <&gpio1_porta 8 0>;
                reset-gpios = <&gpio1_porta 7 0>;
                AVDD28-supply = <&reg_tp_pwr_en>;
-               touchscreen-size-x = <720>;
+               touchscreen-size-x = <800>;
                touchscreen-size-y = <1280>;
        };
 
@@ -341,18 +350,23 @@
                #sound-dai-cells = <0>;
                compatible = "everest,es8156";
                reg = <0x08>;
+               sound-name-prefix = "ES8156";
+               status = "disabled";
        };
 
         es7210_audio_codec: es7210@40 {
                 #sound-dai-cells = <0>;
                 compatible = "MicArray_0";
                 reg = <0x40>;
+                sound-name-prefix = "ES7210";
+                status = "disabled";
         };
 
-	audio_aw87519_pa@58 {
+	audio_aw87519_pa: amp@58 {
 		compatible = "awinic,aw87519_pa";
 		reg = <0x58>;
 		reset-gpio = <&ao_gpio4_porta 9 0x1>;
+		sound-name-prefix = "AW87519";
 		status = "okay";
 	};
 };
@@ -456,7 +470,7 @@
 	rx-clk-delay = <0x00>; /* for RGMII */
 	tx-clk-delay = <0x00>; /* for RGMII */
 	phy-handle = <&phy_88E1111_1>;
-	status = "disabled";
+	status = "okay";
 };
 
 &emmc {
@@ -488,6 +502,7 @@
 	no-mmc;
 	non-removable;
 	io_fixed_1v8;
+	rxclk-sample-delay = <80>;
 	post-power-on-delay-ms = <50>;
 	wprtn_ignore;
 	cap-sd-highspeed;
@@ -530,7 +545,7 @@
 				>;
 			};
 
-			pinctrl_audio_i2s0: i2s0grp {
+			pinctrl_light_i2s0: i2s0grp {
 				thead,pins = <
 					FM_QSPI0_SCLK    0x2    0x208
 					FM_QSPI0_CSN0    0x2    0x238
@@ -862,22 +877,6 @@
         status = "disabled";
 };
 
-&light_i2s {
-        status = "okay";
-};
-
-&i2s0 {
-        status = "okay";
-};
-
-&i2s1 {
-        status = "okay";
-};
-
-&i2s3 {
-        status = "okay";
-};
-
 &khvhost {
 	status = "disabled";
 };

arch/riscv/boot/dts/thead/light-emu.dtsi

@@ -309,7 +309,7 @@
 			entry-cnt = <4>;
 			control-reg = <0xff 0xff015004>;
 			control-val = <0x1c>;
-			csr-copy = <0x7f3 0x7c0 0x7c1 0x7c2 0x7c3 0x7c5 0x7cc>;
+			csr-copy = <0x7f3 0x7c0 0x7c1 0x7c2 0x7c3 0x7c5 0x7cc 0x7ce>;
 		};
 
 		clint0: clint@ffdc000000 {

arch/riscv/boot/dts/thead/light-evb.dtsi

@@ -318,7 +318,7 @@
 			entry-cnt = <4>;
 			control-reg = <0xff 0xff015004>;
 			control-val = <0x1c>;
-			csr-copy = <0x7f3 0x7c0 0x7c1 0x7c2 0x7c3 0x7c5 0x7cc>;
+			csr-copy = <0x7f3 0x7c0 0x7c1 0x7c2 0x7c3 0x7c5 0x7cc 0x7ce>;
 		};
 
 		clint0: clint@ffdc000000 {
@@ -1193,8 +1193,7 @@
 
 		emmc: sdhci@ffe7080000 {
 			compatible = "snps,dwcmshc-sdhci";
-			reg = <0xff 0xe7080000 0x0 0x10000
+			reg = <0xff 0xe7080000 0x0 0x10000>;
-			       0xff 0xef014060 0x0 0x4>;
 			interrupt-parent = <&intc>;
 			interrupts = <62>;
 			interrupt-names = "sdhciirq";
@@ -1204,8 +1203,7 @@
 
 		sdhci0: sd@ffe7090000 {
 			compatible = "snps,dwcmshc-sdhci";
-			reg = <0xff 0xe7090000 0x0 0x10000
+			reg = <0xff 0xe7090000 0x0 0x10000>;
-			       0xff 0xef014064 0x0 0x4>;
 			interrupt-parent = <&intc>;
 			interrupts = <64>;
 			interrupt-names = "sdhci0irq";
@@ -1215,8 +1213,7 @@
 
 		sdhci1: sd@ffe70a0000 {
 		        compatible = "snps,dwcmshc-sdhci";
-		        reg = <0xff 0xe70a0000 0x0 0x10000
+		        reg = <0xff 0xe70a0000 0x0 0x10000>;
-		               0xff 0xef014064 0x0 0x4>;
 		        interrupt-parent = <&intc>;
 		        interrupts = <71>;
 		        interrupt-names = "sdhci1irq";
@@ -1302,7 +1299,7 @@
 			compatible = "light,light-i2s";
 			reg = <0xff 0xe7034000 0x0 0x4000>;
 			pinctrl-names = "default";
-			pinctrl-0 = <&pinctrl_audio_i2s0>;
+			pinctrl-0 = <&pinctrl_light_i2s0>;
 			light,mode = "i2s-master";
 			interrupt-parent = <&intc>;
 			interrupts = <70>;

arch/riscv/boot/dts/thead/light-fm-emu.dts

@@ -185,7 +185,7 @@
 				sound-dai = <&light_i2s 0>;
 			};
 			codec {
-				sound-dai = <&dummy_codec 2>;
+				sound-dai = <&dummy_codec>;
 			};
 		};
 
@@ -196,7 +196,7 @@
 				sound-dai = <&light_i2s 1>;
 			};
 			codec {
-				sound-dai = <&dummy_codec 2>;
+				sound-dai = <&dummy_codec>;
 			};
 		};
 	};
@@ -451,8 +451,8 @@
 
 &video{
 	status = "okay";
-	piplane0 {
+	channel0 {
-				pipline_id = <0>;
+				channel_id = <0>;
 				status = "okay";
 				sensor0 {
 					subdev_name = "vivcam";

arch/riscv/boot/dts/thead/light-lpi4a-camera-tuning.dts

@@ -0,0 +1,53 @@
+/* SPDX-License-Identifier: GPL-2.0 */	
+/*
+ * Copyright (C) 2021 Alibaba Group Holding Limited.
+ */
+
+/dts-v1/;
+
+#include "light-lpi4a.dts"
+
+
+
+&video10{ // TUNINGTOOL
+	status = "okay";
+	channel0 {
+		sensor1 {
+			subdev_name = "vivcam";
+			idx = <3>;
+			csi_idx = <0>;
+			mode_idx = <1>; // 0=640 480 1=2592x1944
+			path_type = "SENSOR_2592x1944_LINER";
+		};
+        dma {
+			path_type = "VIPRE_CSI0_ISP0";
+		};
+	};
+};
+
+&video15{
+    status = "okay";
+    vi_mem_pool_region = <0>;	// vi_mem: framebuffer, region[0]
+    channel0 {
+        status = "okay";
+		sensor0 {
+			subdev_name = "vivcam";
+			idx = <0>;
+			csi_idx = <0>;
+			mode_idx = <0>;
+			path_type = "SENSOR_VGA_RAW12_LINER";
+		};
+		sensor1 {
+			subdev_name = "vivcam";
+			idx = <3>;
+			csi_idx = <0>;
+			mode_idx = <1>;
+			path_type = "SENSOR_2592x1944_LINER";
+		};
+		dma {
+			subdev_name = "vipre";
+			idx = <0>;
+			path_type = "VIPRE_CSI0_DDR";
+		};
+    };
+};

arch/riscv/boot/dts/thead/light-lpi4a-crash.dts

@@ -0,0 +1,98 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2023 Alibaba Group Holding Limited.
+ */
+
+#include "light-crash.dts"
+
+&aon {
+	aon_reg_dialog: light-dialog-reg {
+		compatible = "thead,light-dialog-pmic-ant";
+		status = "okay";
+
+		dvdd_cpu_reg: appcpu_dvdd {
+			regulator-name = "appcpu_dvdd";
+			regulator-min-microvolt = <300000>;
+			regulator-max-microvolt = <1570000>;
+			regulator-boot-on;
+			regulator-always-on;
+		};
+
+		dvddm_cpu_reg: appcpu_dvddm {
+			regulator-name = "appcpu_dvddm";
+			regulator-min-microvolt = <300000>;
+			regulator-max-microvolt = <1570000>;
+			regulator-boot-on;
+			regulator-always-on;
+		};
+	};
+};
+
+&cpus {
+	c910_0: cpu@0 {
+		operating-points = <
+			/* kHz    uV */
+			300000	600000
+			800000	700000
+			1500000	800000
+			1848000 1000000
+		>;
+		light,dvddm-operating-points = <
+			/* kHz   uV */
+			300000	800000
+			800000	800000
+			1500000	800000
+			1848000 1000000
+		>;
+	};
+	c910_1: cpu@1 {
+		operating-points = <
+			/* kHz    uV */
+			300000	600000
+			800000	700000
+			1500000	800000
+			1848000 1000000
+		>;
+		light,dvddm-operating-points = <
+			/* kHz   uV */
+			300000	800000
+			800000	800000
+			1500000	800000
+			1848000 1000000
+		>;
+	};
+	c910_2: cpu@2 {
+
+		operating-points = <
+			/* kHz    uV */
+			300000	600000
+			800000	700000
+			1500000	800000
+			1848000 1000000
+		>;
+		light,dvddm-operating-points = <
+			/* kHz   uV */
+			300000	800000
+			800000	800000
+			1500000	800000
+			1848000 1000000
+		>;
+	};
+	c910_3: cpu@3 {
+
+		operating-points = <
+			/* kHz    uV */
+			300000	600000
+			800000	700000
+			1500000	800000
+			1848000 1000000
+		>;
+		light,dvddm-operating-points = <
+			/* kHz   uV */
+			300000	800000
+			800000	800000
+			1500000	800000
+			1848000 1000000
+		>;
+	};
+};

arch/riscv/boot/dts/thead/light-lpi4a-ddr2G.dts

@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2022 Alibaba Group Holding Limited.
+ */
+
+#include "light-lpi4a.dts"
+
+/ {
+	model = "T-HEAD Light Lichee Pi 4A configuration for 2GB DDR board";
+	compatible = "thead,light-val", "thead,light-lpi4a-ddr2G", "thead,light";
+
+	memory@0 {
+		device_type = "memory";
+		reg = <0x0 0x200000 0x0 0x7fe00000>;
+	};
+};
+
+&cmamem {
+	alloc-ranges = <0 0x64000000 0 0x14000000>; // [0x6400_0000 ~ 0x7800_0000]
+};

arch/riscv/boot/dts/thead/light-lpi4a-hdmi.dts

@@ -0,0 +1,50 @@
+/* SPDX-License-Identifier: GPL-2.0 */	
+/*
+ * Copyright (C) 2021 Alibaba Group Holding Limited.
+ */
+
+/dts-v1/;
+
+#include "light-lpi4a.dts"
+
+&lightsound {
+        status = "okay";
+        simple-audio-card,dai-link@0 {          /* I2S - HDMI*/
+                reg = <0>;
+                format = "i2s";
+                cpu {
+                        sound-dai = <&light_i2s 1>;
+                };
+                codec {
+                        sound-dai = <&dummy_codec>;
+                };
+        };
+        simple-audio-card,dai-link@1 {          /* I2S - AUDIO SYS CODEC 7210*/
+                reg = <1>;
+                format = "i2s";
+                cpu {
+                        sound-dai = <&i2s1 0>;
+                };
+                codec {
+                        sound-dai = <&es7210_audio_codec>;
+                };
+        };
+        simple-audio-card,dai-link@2 {          /* I2S - AUDIO SYS CODEC 8156*/
+                reg = <2>;
+                format = "i2s";
+                cpu {
+                        sound-dai = <&i2s1 0>;
+                };
+                codec {
+                        sound-dai = <&es8156_audio_codec>;
+                };
+        };
+};
+
+&dpu_enc0 {
+        status = "disabled";
+};
+
+&dsi0 {
+        status = "disabled";
+};

arch/riscv/boot/dts/thead/light-lpi4a-hx8279.dts

@@ -0,0 +1,60 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2022-2023 Alibaba Group Holding Limited.
+ */
+
+#include "light-lpi4a-ref.dts"
+
+/ {
+	model = "T-HEAD Light Lichee Pi 4A configuration for 8GB DDR board";
+	compatible = "thead,light-val", "thead,light-lpi4a", "thead,light";
+
+	memory@0 {
+		device_type = "memory";
+		reg = <0x0 0x200000 0x1 0xffe00000>;
+	};
+};
+
+&cmamem {
+	size = <0 0x20000000>; // 512MB on lpi4a (SOM)
+	alloc-ranges = <0 0xd8000000 0 0x20000000>; // [0x0D800_0000 ~ 0x0F800_0000]
+};
+
+&i2c3 {
+	touch@14 {
+                #gpio-cells = <2>;
+                compatible = "goodix,gt9271";
+                reg = <0x14>;
+                interrupt-parent = <&ao_gpio_porta>;
+                interrupts = <3 0>;
+                irq-gpios = <&ao_gpio_porta 3 0>;
+                reset-gpios = <&pcal6408ahk_d 0 0>;
+                AVDD28-supply = <&reg_tp_pwr_en>;
+                touchscreen-size-x = <1200>;
+                touchscreen-size-y = <1920>;
+                tp-size = <9271>;
+                status = "okay";
+        };
+};
+
+&dsi0 {
+        status = "okay";
+};
+
+
+&dhost_0 {
+	panel0@0 {
+                compatible = "himax,hx8279";
+                reg = <0>;
+                backlight = <&lcd0_backlight>;
+                reset-gpio = <&pcal6408ahk_d 7 0>; /* active low */
+                hsvcc-supply = <&soc_vdd18_lcd0_en_reg>;
+                vspn3v3-supply = <&soc_vdd33_lcd0_en_reg>;
+
+                port {
+                        panel0_in: endpoint {
+                                remote-endpoint = <&dsi0_out>;
+                        };
+                };
+        };
+};

arch/riscv/boot/dts/thead/light-lpi4a-sec.dts

@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2021 Alibaba Group Holding Limited.
+ */
+
+/dts-v1/;
+
+#include "light-lpi4a-hdmi.dts"
+
+
+&light_iopmp {
+        status = "disabled";
+};
+
+&qspi1 {
+        status = "disabled";
+};
+

arch/riscv/boot/dts/thead/light-lpi4a.dts

@@ -0,0 +1,59 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2022-2023 Alibaba Group Holding Limited.
+ */
+
+#include "light-lpi4a-ref.dts"
+
+/ {
+	model = "T-HEAD Light Lichee Pi 4A configuration for 8GB DDR board";
+	compatible = "thead,light-val", "thead,light-lpi4a", "thead,light";
+
+	memory@0 {
+		device_type = "memory";
+		reg = <0x0 0x200000 0x1 0xffe00000>;
+	};
+};
+
+&cmamem {
+	size = <0 0x20000000>; // 512MB on lpi4a (SOM)
+	alloc-ranges = <0 0xd8000000 0 0x20000000>; // [0x0D800_0000 ~ 0x0F800_0000]
+};
+
+&i2c3 {
+        touch@14 {
+                #gpio-cells = <2>;
+                compatible = "goodix,gt9271";
+                reg = <0x14>;
+                interrupt-parent = <&ao_gpio_porta>;
+                interrupts = <3 0>;
+                irq-gpios = <&ao_gpio_porta 3 0>;
+                reset-gpios = <&pcal6408ahk_d 0 0>;
+                AVDD28-supply = <&reg_tp_pwr_en>;
+                touchscreen-size-x = <800>;
+                touchscreen-size-y = <1200>;
+                tp-size = <9271>;
+                status = "okay";
+        };
+};
+
+&dsi0 {
+        status = "okay";
+};
+
+&dhost_0 {
+        panel0@0 {
+		compatible = "chongzhou,cz101b4001", "jadard,jd9365da-h3";
+                reg = <0>;
+                backlight = <&lcd0_backlight>;
+                reset-gpio = <&pcal6408ahk_d 7 0>; /* active low */
+                hsvcc-supply = <&soc_vdd18_lcd0_en_reg>;
+                vspn3v3-supply = <&soc_vdd33_lcd0_en_reg>;
+
+                port {
+                        panel0_in: endpoint {
+                                remote-endpoint = <&dsi0_out>;
+                        };
+                };
+        };
+};

arch/riscv/boot/dts/thead/light-vi-devices.dtsi

@@ -4,9 +4,9 @@
  */
 
 &video0{
-	status = "okay";
+	status = "disabled";
-	pipline0 {
+	channel0 {
-		pipline_id = <0>;
+		channel_id = <0>;
 		status = "okay";
 		sensor0 {
 			subdev_name = "vivcam";
@@ -31,8 +31,8 @@
 			path_type = "ISP_MI_PATH_MP";
 		};
 	};
-	pipline1 {
+	channel1 {
-		pipline_id = <1>;
+		channel_id = <1>;
 		status = "okay";
 		sensor0 {
 			subdev_name = "vivcam";
@@ -57,8 +57,8 @@
 			path_type = "ISP_MI_PATH_SP";
 		};
 	};
-	pipline2 {
+	channel2 {
-		pipline_id = <2>;
+		channel_id = <2>;
 		status = "okay";
 		sensor0 {
 			subdev_name = "vivcam";
@@ -86,9 +86,9 @@
 };
 
 &video1{
-	status = "okay";
+	status = "disabled";
-	pipline0 { // VSE0
+	channel0 { // VSE0
-		pipline_id = <0>;
+		channel_id = <0>;
 		status = "okay";
 		sensor0 {
 			subdev_name = "vivcam";
@@ -118,8 +118,8 @@
 			path_type = "DW_DWE_VSE0";
 		};
 	};
-	pipline1 { // VSE1
+	channel1 { // VSE1
-		pipline_id = <1>;
+		channel_id = <1>;
 		status = "okay";
 		sensor0 {
 			subdev_name = "vivcam";
@@ -149,8 +149,8 @@
 			path_type = "DW_DWE_VSE1";
 		};
 	};
-	pipline2 { // VSE2
+	channel2 { // VSE2
-		pipline_id = <2>;
+		channel_id = <2>;
 		status = "okay";
 		sensor0 {
 			subdev_name = "vivcam";
@@ -183,9 +183,9 @@
 };
 
 &video2 {
-	status = "okay";
+	status = "disabled";
-	pipline0 {
+	channel0 {
-		pipline_id = <0>;
+		channel_id = <0>;
 		status = "okay";
 		sensor0 {
 			subdev_name = "vivcam";
@@ -199,6 +199,12 @@
 			csi_idx = <0xff>;
 			path_type = "SENSOR_VGA_RAW10_LINER";
 		};
+		sensor2 {
+			subdev_name = "vivcam";
+			idx = <0xff>; // invalid
+			csi_idx = <0xff>;
+			path_type = "SENSOR_VGA_RAW10_LINER";
+		};
 		dma {
 			subdev_name = "vipre";
 			idx = <0>;
@@ -210,8 +216,8 @@
 			path_type = "ISP_MI_PATH_MP";
 		};
 	};
-	pipline1 {
+	channel1 {
-		pipline_id = <1>;
+		channel_id = <1>;
 		status = "okay";
 		sensor0 {
 			subdev_name = "vivcam";
@@ -236,8 +242,8 @@
 			path_type = "ISP_MI_PATH_SP";
 		};
 	};
-	pipline2 {
+	channel2 {
-		pipline_id = <2>;
+		channel_id = <2>;
 		status = "okay";
 		sensor0 {
 			subdev_name = "vivcam";
@@ -266,9 +272,9 @@
 };
 
 &video3 {
-	status = "okay";
+	status = "disabled";
-		pipline0 {
+		channel0 {
-		pipline_id = <0>;
+		channel_id = <0>;
 		status = "okay";
 		sensor0 {
 			subdev_name = "vivcam";
@@ -298,8 +304,8 @@
 			path_type = "DW_DWE_VSE0";
 		};
 	};
-	pipline1 {
+	channel1 {
-		pipline_id = <1>;
+		channel_id = <1>;
 		status = "okay";
 		sensor0 {
 			subdev_name = "vivcam";
@@ -330,8 +336,8 @@
 			path_type = "DW_DWE_VSE1";
 		};
 	};
-	pipline2 {
+	channel2 {
-		pipline_id = <2>;
+		channel_id = <2>;
 		status = "okay";
 		sensor0 {
 			subdev_name = "vivcam";
@@ -364,9 +370,9 @@
 };
 
 &video4 {
-	status = "okay";
+	status = "disabled";
-	pipline0 {
+	channel0 {
-		pipline_id = <0>;
+		channel_id = <0>;
 		status = "okay";
 		sensor0 {
 			subdev_name = "vivcam";
@@ -402,8 +408,8 @@
 			path_type = "ISP_RY_MI_PATH_MP";
 		};
 	};
-	pipline1 {
+	channel1 {
-		pipline_id = <1>;
+		channel_id = <1>;
 		status = "okay";
 		sensor0 {
 			subdev_name = "vivcam";
@@ -438,8 +444,8 @@
 			path_type = "ISP_RY_MI_PATH_SP";
 		};
 	};
-	pipline2 {
+	channel2 {
-		pipline_id = <2>;
+		channel_id = <2>;
 		status = "okay";
 		sensor0 {
 			subdev_name = "vivcam";
@@ -477,9 +483,9 @@
 };
 
 &video5 {
-	status = "okay";
+	status = "disabled";
-	pipline0 {
+	channel0 {
-		pipline_id = <0>;
+		channel_id = <0>;
 		status = "okay";
 		sensor0 {
 			subdev_name = "vivcam";
@@ -520,8 +526,8 @@
 			path_type = "DW_DWE_VSE0";
 		};
 	};
-	pipline1 {
+	channel1 {
-		pipline_id = <1>;
+		channel_id = <1>;
 		status = "okay";
 		sensor0 {
 			subdev_name = "vivcam";
@@ -561,8 +567,8 @@
 			path_type = "DW_DWE_VSE1";
 		};
 	};
-	pipline2 {
+	channel2 {
-		pipline_id = <2>;
+		channel_id = <2>;
 		status = "okay";
 		sensor0 {
 			subdev_name = "vivcam";
@@ -606,9 +612,9 @@
 
 
 &video6 {
-	status = "okay";
+	status = "disabled";
-	pipline0 {
+	channel0 {
-		pipline_id = <0>;
+		channel_id = <0>;
 		status = "okay";
 		sensor0 {
 			subdev_name = "vivcam";
@@ -633,8 +639,8 @@
 			path_type = "DSP_PATH_VIPRE_ODD";
 		};
 	};
-	pipline1 {
+	channel1 {
-		pipline_id = <1>;
+		channel_id = <1>;
 		status = "okay";
 		sensor0 {
 			subdev_name = "vivcam";
@@ -663,9 +669,9 @@
 
 
 &video7{
-	status = "okay";
+	status = "disabled";
-	pipline0 {
+	channel0 {
-		pipline_id = <0>;
+		channel_id = <0>;
 		status = "okay";
 		sensor0 {
 			subdev_name = "vivcam";
@@ -706,8 +712,8 @@
 		};
 
 	};
-	pipline1 {
+	channel1 {
-		pipline_id = <1>;
+		channel_id = <1>;
 		status = "okay";
 		sensor0 {
 			subdev_name = "vivcam";
@@ -747,8 +753,8 @@
 			path_type = "DW_DWE_VSE1";
 		};
 	};
-	pipline2 {
+	channel2 {
-		pipline_id = <2>;
+		channel_id = <2>;
 		status = "okay";
 		sensor0 {
 			subdev_name = "vivcam";
@@ -792,9 +798,9 @@
 
 
 &video8{
-	status = "okay";
+	status = "disabled";
-	pipline0 {
+	channel0 {
-		pipline_id = <0>;
+		channel_id = <0>;
 		status = "okay";
 		sensor0 {
 			subdev_name = "vivcam";
@@ -823,9 +829,9 @@
 
 
 &video9 { //IR debug
-	status = "okay";
+	status = "disabled";
-	pipline0 {
+	channel0 {
-		pipline_id = <0>;
+		channel_id = <0>;
 		status = "okay";
 		sensor0 {
 			subdev_name = "vivcam";
@@ -856,8 +862,8 @@
 
 
 &video10{ // TUNING TOOL
-	status = "okay";
+	status = "disabled";
-	pipline0 { // CSI2X2_B
+	channel0 { // CSI2X2_B
 		status = "okay";
 		sensor0 {
 			subdev_name = "vivcam";
@@ -883,9 +889,9 @@
 
 
 &video11{
-	status = "okay";
+	status = "disabled";
-	pipline0 {
+	channel0 {
-		pipline_id = <0>;
+		channel_id = <0>;
 		status = "okay";
 		sensor0 {
 			subdev_name = "vivcam";
@@ -914,8 +920,8 @@
 
 
 &video12{ // TUNING TOOL
-	status = "okay";
+	status = "disabled";
-	pipline0 { // CSI2
+	channel0 { // CSI2
 		status = "okay";
 		sensor0 {
 			subdev_name = "vivcam";

arch/riscv/boot/dts/thead/light.dtsi

@@ -6,12 +6,16 @@
 #include <dt-bindings/pinctrl/light-fm-left-pinctrl.h>
 #include <dt-bindings/pinctrl/light-fm-right-pinctrl.h>
 #include <dt-bindings/pinctrl/light-fm-aon-pinctrl.h>
+#include <dt-bindings/pinctrl/light-fm-audio-pinctrl.h>
+#include <dt-bindings/pinctrl/light-fm-pinctrl-def.h>
 #include <dt-bindings/clock/light-fm-ap-clock.h>
 #include <dt-bindings/clock/light-vpsys.h>
 #include <dt-bindings/clock/light-vosys.h>
 #include <dt-bindings/clock/light-visys.h>
 #include <dt-bindings/clock/light-dspsys.h>
+#include <dt-bindings/clock/light-audiosys.h>
 #include <dt-bindings/firmware/thead/rsrc.h>
+#include <dt-bindings/clock/light-miscsys.h>
 #include <dt-bindings/soc/thead,light-iopmp.h>
 #include <dt-bindings/thermal/thermal.h>
 #include <dt-bindings/reset/light-reset.h>
@@ -34,6 +38,7 @@
 		i2c3 = &i2c3;
 		i2c4 = &i2c4;
 		audio_i2c0 = &audio_i2c0;
+        audio_i2c1 = &audio_i2c1;
 		mmc0 = &emmc;
 		mmc1 = &sdhci0;
 		serial0 = &uart0;
@@ -54,6 +59,7 @@
 		vivcam4 = &vvcam_sensor4;
 		vivcam5 = &vvcam_sensor5;
         vivcam6 = &vvcam_sensor6;
+        vivcam7 = &vvcam_sensor7;
 
         viv_video0 =  &video0;
         viv_video1 =  &video1;
@@ -93,6 +99,11 @@
 		};
 	};
 
+    aon_iram: aon-iram@ffffef8000 {
+            compatible = "syscon";
+            reg = <0xff 0xffef8000 0x0 0x10000>;
+    };
+
 	thermal-zones {
 		cpu-thermal-zone {
 			polling-delay-passive = <250>;
@@ -175,6 +186,7 @@
 				interrupt-controller;
 			};
 		};
+
 		c910_1: cpu@1 {
 			device_type = "cpu";
 			reg = <1>;
@@ -313,6 +325,44 @@
 				interrupt-controller;
 			};
 		};
+
+		idle_states: idle-states {
+		    CPU_RET_0_0: cpu-retentive-0-0 {
+			compatible = "riscv,idle-state";
+			riscv,sbi-suspend-param = <0x10000000>;
+			entry-latency-us = <20>;
+			exit-latency-us = <40>;
+			min-residency-us = <80>;
+		    };
+
+		    CPU_NONRET_0_0: cpu-nonretentive-0-0 {
+			compatible = "riscv,idle-state";
+			riscv,sbi-suspend-param = <0x90000000>;
+			entry-latency-us = <250>;
+			exit-latency-us = <500>;
+			min-residency-us = <950>;
+		    };
+
+		    CLUSTER_RET_0: cluster-retentive-0 {
+			compatible = "riscv,idle-state";
+			riscv,sbi-suspend-param = <0x11000000>;
+			local-timer-stop;
+			entry-latency-us = <50>;
+			exit-latency-us = <100>;
+			min-residency-us = <250>;
+			wakeup-latency-us = <130>;
+		    };
+
+		    CLUSTER_NONRET_0: cluster-nonretentive-0 {
+			compatible = "riscv,idle-state";
+			riscv,sbi-suspend-param = <0x91000000>;
+			local-timer-stop;
+			entry-latency-us = <600>;
+			exit-latency-us = <1100>;
+			min-residency-us = <2700>;
+			wakeup-latency-us = <1500>;
+		    };
+		};
 	};
 
 	display-subsystem {
@@ -382,7 +432,7 @@
 			entry-cnt = <4>;
 			control-reg = <0xff 0xff015004>;
 			control-val = <0x1c>;
-			csr-copy = <0x7f3 0x7c0 0x7c1 0x7c2 0x7c3 0x7c5 0x7cc>;
+			csr-copy = <0x7f3 0x7c0 0x7c1 0x7c2 0x7c3 0x7c5 0x7cc 0x7ce>;
 		};
 
 		clint0: clint@ffdc000000 {
@@ -621,6 +671,18 @@
 			status = "okay";
 		};
 
+		miscsys_reg: miscsys-reg@ffec02c000 {
+			compatible = "thead,light-miscsys-reg", "syscon";
+			reg = <0xff 0xec02c000 0x0 0x1000>;
+			status = "okay";
+		};
+ 
+		tee_miscsys_reg: tee_miscsys-reg@fffc02d000 {
+			compatible = "thead,light-miscsys-reg", "syscon";
+			reg = <0xff 0xfc02d000 0x0 0x1000>;
+			status = "okay";
+		};
+ 
 		audio_ioctrl: audio_ioctrl@ffcb01d000 {
 			compatible = "thead,light-audio-ioctrl-reg", "syscon";
 			reg = <0xff 0xcb01d000 0x0 0x1000>;
@@ -633,12 +695,20 @@
 			status = "okay";
 		};
 
+		audio_mbox: audio_mbox@0xffefc48000 {
+			compatible = "thead,light-audio-mbox-reg", "syscon";
+			reg = <0xff 0xefc48000 0x0 0x1000>;
+			status = "okay";
+		};
+
 		nvmem_controller: efuse@ffff210000 {
 			compatible = "thead,light-fm-efuse", "syscon";
 			reg = <0xff 0xff210000 0x0 0x10000>;
 			thead,teesys = <&teesys_syscon>;
 			#address-cells = <1>;
 			#size-cells = <1>;
+			clocks = <&miscsys_clk_gate CLKGEN_MISCSYS_EFUSE_PCLK>;
+			clock-names = "pclk";
 
 			gmac0_mac_address: mac-address@176 {
 				reg = <0xb0 6>;
@@ -666,7 +736,9 @@
 			reg = <0xff 0xec005000 0x0 0x1000>;
 			#address-cells = <1>;
 			#size-cells = <0>;
-
+            clocks = <&clk CLKGEN_GPIO0_PCLK>,
+            <&clk CLKGEN_GPIO0_DBCLK>;
+			clock-names = "bus", "db";
 			gpio0_porta: gpio0-controller@0 {
 				compatible = "snps,dw-apb-gpio-port";
 				gpio-controller;
@@ -686,7 +758,9 @@
 			reg = <0xff 0xec006000 0x0 0x1000>;
 			#address-cells = <1>;
 			#size-cells = <0>;
-
+			clocks = <&clk CLKGEN_GPIO1_PCLK>,
+			         <&clk CLKGEN_GPIO1_DBCLK>;
+			clock-names = "bus", "db";
 			gpio1_porta: gpio1-controller@0 {
 				compatible = "snps,dw-apb-gpio-port";
 				gpio-controller;
@@ -706,7 +780,9 @@
 			reg = <0xff 0xe7f34000 0x0 0x1000>;
 			#address-cells = <1>;
 			#size-cells = <0>;
-
+			clocks = <&clk CLKGEN_GPIO2_PCLK>,
+			         <&clk CLKGEN_GPIO2_DBCLK>;
+			clock-names = "bus", "db";
 			gpio2_porta: gpio2-controller@0 {
 				compatible = "snps,dw-apb-gpio-port";
 				gpio-controller;
@@ -726,7 +802,9 @@
 			reg = <0xff 0xe7f38000 0x0 0x1000>;
 			#address-cells = <1>;
 			#size-cells = <0>;
-
+			clocks = <&clk CLKGEN_GPIO3_PCLK>,
+			         <&clk CLKGEN_GPIO3_DBCLK>;
+			clock-names = "bus", "db";
 			gpio3_porta: gpio3-controller@0 {
 				compatible = "snps,dw-apb-gpio-port";
 				gpio-controller;
@@ -781,15 +859,19 @@
 			};
 		};
 
-		padctrl1_apsys: pinctrl1-apsys@ffe7f3c000 {
+		padctrl1_apsys: padctrl1-apsys@ffe7f3c000 {
 			compatible = "thead,light-fm-left-pinctrl";
 			reg = <0xff 0xe7f3c000 0x0 0x1000>;
+			clocks = <&clk CLKGEN_PADCTRL1_APSYS_PCLK>;
+			clock-names = "pclk";
 			status = "okay";
 		};
 
 		padctrl0_apsys: padctrl0-apsys@ffec007000 {
 			compatible = "thead,light-fm-right-pinctrl";
 			reg = <0xff 0xec007000 0x0 0x1000>;
+			clocks = <&clk CLKGEN_PADCTRL0_APSYS_PCLK>;
+			clock-names = "pclk";
 			status = "okay";
 		};
 
@@ -854,6 +936,12 @@
 			status = "okay";
 		};
 
+		padctrl_audiosys: padctrl-audiosys@ffcb01d000 {
+			compatible = "thead,light-fm-audio-pinctrl";
+			reg = <0xff 0xcb01d000 0x0 0x1000>;
+			status = "disabled";
+		};
+
 		timer4: timer@ffffc33000 {
 			compatible = "snps,dw-apb-timer";
 			reg = <0xff 0xffc33000 0x0 0x14>;
@@ -899,7 +987,7 @@
 		};
 
 		uart0: serial@ffe7014000 { /* Normal serial, for C910 log */
-			compatible = "snps,dw-apb-uart";
+                        compatible = "snps,dw-apb-uart", "light,uart0";
 			reg = <0xff 0xe7014000 0x0 0x4000>;
 			interrupt-parent = <&intc>;
 			interrupts = <36>;
@@ -994,7 +1082,9 @@
 			pinctrl-0 = <&pinctrl_spi0>;
 			interrupt-parent = <&intc>;
 			interrupts = <54>;
-			clocks = <&dummy_clock_spi>;
+            clocks = <&clk CLKGEN_SPI_SSI_CLK>,
+                     <&clk CLKGEN_SPI_PCLK>;
+            clock-names = "sclk", "pclk";
 			num-cs = <2>;
 			#address-cells = <1>;
 			#size-cells = <0>;
@@ -1007,7 +1097,9 @@
 			pinctrl-0 = <&pinctrl_qspi0>;
 			interrupt-parent = <&intc>;
 			interrupts = <52>;
-			clocks = <&dummy_clock_qspi>;
+            clocks = <&clk CLKGEN_QSPI0_SSI_CLK>,
+                     <&clk CLKGEN_QSPI0_PCLK>;
+            clock-names = "sclk", "pclk";
 			#address-cells = <1>;
 			#size-cells = <0>;
 		};
@@ -1019,7 +1111,9 @@
 			pinctrl-0 = <&pinctrl_qspi1>;
 			interrupt-parent = <&intc>;
 			interrupts = <53>;
-			clocks = <&dummy_clock_spi>;
+            clocks = <&clk CLKGEN_QSPI1_SSI_CLK>,
+                     <&clk CLKGEN_QSPI1_PCLK>;
+            clock-names = "sclk", "pclk";
 			#address-cells = <1>;
 			#size-cells = <0>;
 		};
@@ -1117,9 +1211,8 @@
 			clocks = <&vosys_clk_gate LIGHT_CLKGEN_HDMI_PCLK>,
 				 <&vosys_clk_gate LIGHT_CLKGEN_HDMI_SFR_CLK>,
 				 <&vosys_clk_gate LIGHT_CLKGEN_HDMI_CEC_CLK>,
-				 <&vosys_clk_gate LIGHT_CLKGEN_HDMI_PIXCLK>,
+				 <&vosys_clk_gate LIGHT_CLKGEN_HDMI_PIXCLK>;
-				 <&vosys_clk_gate LIGHT_CLKGEN_HDMI_I2S_CLK>;
+			clock-names = "iahb", "isfr", "cec", "pixclk";
-			clock-names = "iahb", "isfr", "cec", "pixclk", "i2s";
 			reg-io-width = <4>;
 			phy_version = <301>;
 			/* TODO: add phy property */
@@ -1135,6 +1228,7 @@
 			      <0xff 0xef630010 0x0 0x60>;
 			interrupt-parent = <&intc>;
 			interrupts = <93>;
+			vosys-regmap = <&vosys_reg>;
 			clocks = <&vosys_clk_gate LIGHT_CLKGEN_DPU_CCLK>,
 				 <&vosys_clk_gate LIGHT_CLKGEN_DPU_PIXCLK0>,
 				 <&vosys_clk_gate LIGHT_CLKGEN_DPU_PIXCLK1>,
@@ -1196,6 +1290,7 @@
 			interrupts = <74>;
 			clocks = <&dummy_clock_rtc>;
 			clock-names = "rtc";
+			wakeup-source;
 			status = "okay";
 		};
 
@@ -1203,6 +1298,11 @@
 			compatible = "thead,dwc3";
 			usb3-misc-regmap = <&misc_sysreg>;
 			usb3-drd-regmap = <&usb3_drd>;
+			clocks = <&miscsys_clk_gate CLKGEN_MISCSYS_USB3_DRD_CLK>,
+					<&miscsys_clk_gate CLKGEN_MISCSYS_USB3_DRD_CTRL_REF_CLK>,
+					<&miscsys_clk_gate CLKGEN_MISCSYS_USB3_DRD_PHY_REF_CLK>,
+					<&miscsys_clk_gate CLKGEN_MISCSYS_USB3_DRD_SUSPEND_CLK>;
+			clock-names = "drd", "ctrl", "phy", "suspend";
 			#address-cells = <2>;
 			#size-cells = <2>;
 			ranges;
@@ -1212,8 +1312,6 @@
 				reg = <0xff 0xe7040000 0x0 0x10000>;
 				interrupt-parent = <&intc>;
 				interrupts = <68>;
-				clocks = <&dummy_clock_ref>, <&dummy_clock_apb>, <&dummy_clock_suspend>;
-				clock-names = "ref", "bus_early", "suspend";
 				reg-shift = <2>;
 				reg-io-width = <4>;
 				maximum-speed = "super-speed";
@@ -1247,6 +1345,13 @@
 			status = "okay";
 		};
 
+		vpsys_rst: vpsys-reset-controller@ffecc30000 {
+			compatible = "thead,light-vpsys-reset-src","syscon";
+			reg = <0xff 0xecc30000 0x0 0x1000>;
+			#reset-cells = <1>;
+			status = "okay";
+		};
+
 		sys_reg: sys_reg@ffef010100 {
 			compatible = "thead,light_sys_reg";
 			reg = <0xff 0xef010100 0x0 0x100>;
@@ -1258,7 +1363,7 @@
 			reg = <0xff 0xefc00000 0x0 0x1000>;
 			interrupt-parent = <&intc>;
 			interrupts = <27>;
-			clocks = <&dummy_clock_apb>, <&dummy_clock_apb>;
+			clocks = <&clk CLKGEN_DMAC_CPUSYS_ACLK>, <&clk CLKGEN_DMAC_CPUSYS_HCLK>;
 			clock-names = "core-clk", "cfgr-clk";
 			#dma-cells = <1>;
 			dma-channels = <4>;
@@ -1275,7 +1380,7 @@
 			reg = <0xff 0xff340000 0x0 0x1000>;
 			interrupt-parent = <&intc>;
 			interrupts = <150>;
-			clocks = <&dummy_clock_apb>, <&dummy_clock_apb>;
+			clocks = <&clk CLKGEN_DMAC_CPUSYS_ACLK>, <&clk CLKGEN_DMAC_CPUSYS_HCLK>;
 			clock-names = "core-clk", "cfgr-clk";
 			#dma-cells = <1>;
 			dma-channels = <4>;
@@ -1292,7 +1397,7 @@
                         reg = <0xff 0xc8000000 0x0 0x2000>;
                         interrupt-parent = <&intc>;
                         interrupts = <167>;
-                        clocks = <&dummy_clock_apb>, <&dummy_clock_apb>;
+						clocks = <&clk CLKGEN_DMAC_CPUSYS_ACLK>, <&clk CLKGEN_DMAC_CPUSYS_HCLK>;
                         clock-names = "core-clk", "cfgr-clk";
                         #dma-cells = <1>;
                         dma-channels = <16>;
@@ -1300,7 +1405,7 @@
                                           65536 65536 65536 65536
                                           65536 65536 65536 65536
                                           65536 65536 65536 65536>;
-                        snps,priority = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>;
+                        snps,priority = <0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0>; // <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>;
                         snps,dma-masters = <1>;
                         snps,data-width = <4>;
                         snps,axi-max-burst-len = <16>;
@@ -1323,8 +1428,11 @@
 			interrupt-parent = <&intc>;
 			interrupts = <66>;
 			interrupt-names = "macirq";
-			clocks = <&clk CLKGEN_GMAC0_CCLK>;
+			clocks = <&clk CLKGEN_GMAC0_CCLK>,
-			clock-names = "gmac_pll_clk";
+					 <&clk CLKGEN_GMAC0_PCLK>,
+					 <&clk CLKGEN_GMAC_AXI_ACLK>,
+					 <&clk CLKGEN_GMAC_AXI_PCLK>;
+			clock-names = "gmac_pll_clk","pclk","axi_aclk","axi_pclk";
 			snps,pbl = <32>;
 			snps,fixed-burst;
 			snps,axi-config = <&stmmac_axi_setup>;
@@ -1342,8 +1450,11 @@
 			interrupt-parent = <&intc>;
 			interrupts = <67>;
 			interrupt-names = "macirq";
-			clocks = <&clk CLKGEN_GMAC1_CCLK>;
+			clocks = <&clk CLKGEN_GMAC1_CCLK>,
-			clock-names = "gmac_pll_clk";
+					 <&clk CLKGEN_GMAC1_PCLK>,
+					 <&clk CLKGEN_GMAC_AXI_ACLK>,
+					 <&clk CLKGEN_GMAC_AXI_PCLK>;
+			clock-names = "gmac_pll_clk","pclk","axi_aclk","axi_pclk";
 			snps,pbl = <32>;
 			snps,fixed-burst;
 			snps,axi-config = <&stmmac_axi_setup>;
@@ -1353,35 +1464,35 @@
 
 		emmc: sdhci@ffe7080000 {
 			compatible = "snps,dwcmshc-sdhci";
-			reg = <0xff 0xe7080000 0x0 0x10000
+			reg = <0xff 0xe7080000 0x0 0x10000>;
-			       0xff 0xef014060 0x0 0x4>;
 			interrupt-parent = <&intc>;
 			interrupts = <62>;
 			interrupt-names = "sdhciirq";
-			clocks = <&dummy_clock_sdhci>;
+			clocks = <&clk CLKGEN_EMMC_SDIO_REF_CLK>,
-			clock-names = "core";
+					 <&miscsys_clk_gate CLKGEN_MISCSYS_EMMC_CLK>;
+			clock-names = "core", "bus";
 		};
 
 		sdhci0: sd@ffe7090000 {
 			compatible = "snps,dwcmshc-sdhci";
-			reg = <0xff 0xe7090000 0x0 0x10000
+			reg = <0xff 0xe7090000 0x0 0x10000>;
-			       0xff 0xef014064 0x0 0x4>;
 			interrupt-parent = <&intc>;
 			interrupts = <64>;
 			interrupt-names = "sdhci0irq";
-			clocks = <&dummy_clock_sdhci>;
+			clocks = <&clk CLKGEN_EMMC_SDIO_REF_CLK>,
-			clock-names = "core";
+					 <&miscsys_clk_gate CLKGEN_MISCSYS_EMMC_CLK>;
+			clock-names = "core", "bus";
 		};
 
 		sdhci1: sd@ffe70a0000 {
 			compatible = "snps,dwcmshc-sdhci";
-		        reg = <0xff 0xe70a0000 0x0 0x10000
+			reg = <0xff 0xe70a0000 0x0 0x10000>;
-		               0xff 0xef014064 0x0 0x4>;
 			interrupt-parent = <&intc>;
 			interrupts = <71>;
 			interrupt-names = "sdhci1irq";
-		        clocks = <&dummy_clock_sdhci>;
+			clocks = <&clk CLKGEN_EMMC_SDIO_REF_CLK>,
-		        clock-names = "core";
+					 <&miscsys_clk_gate CLKGEN_MISCSYS_EMMC_CLK>;
+			clock-names = "core", "bus";
 		};
 
 		hwspinlock: hwspinlock@ffefc10000 {
@@ -1402,7 +1513,8 @@
 			clock-names = "pclk", "aclk";
 			vha_clk_rate = <1000000000>;
 			ldo_vha-supply = <&npu>;
-			dma-mask = <0xf 0xffffffff>;
+			dma-mask = <0xff 0xffffffff>;
+			resets = <&rst LIGHT_RESET_NPU>;
 			status = "disabled";
 		};
 
@@ -1431,6 +1543,7 @@
 			clocks = <&vpsys_clk_gate LIGHT_VPSYS_FCE_ACLK>,
 				<&vpsys_clk_gate LIGHT_VPSYS_FCE_PCLK>;
 			clock-names = "aclk", "pclk";
+			resets = <&vpsys_rst LIGHT_RESET_FCE>;
 			dma-mask = <0xf 0xffffffff>;
 			status = "disabled";
 		};
@@ -1479,8 +1592,6 @@
 			#sound-dai-cells = <1>;
 			compatible = "light,light-i2s";
 			reg = <0xff 0xe7034000 0x0 0x4000>;
-			pinctrl-names = "default";
-			pinctrl-0 = <&pinctrl_audio_i2s0>;
 			light,mode = "i2s-master";
 			light,sel = "ap_i2s";
 			interrupt-parent = <&intc>;
@@ -1489,7 +1600,7 @@
 			dma-names = "tx", "rx";
 			light,dma_maxburst = <4>;
 			#dma-cells = <1>;
-			clocks = <&dummy_clock_apb>;
+			clocks = <&vosys_clk_gate LIGHT_CLKGEN_HDMI_I2S_CLK>;
 			clock-names = "pclk";
 			status = "disabled";
 		};
@@ -1505,11 +1616,11 @@
 			light,sel = "i2s0";
 			interrupt-parent = <&intc>;
 			interrupts = <174>;
-			dmas = <&dmac2 9>, <&dmac2 16>;
+			dmas = <&dmac2 9>, <&dmac2 8>;
 			dma-names = "tx", "rx";
 			light,dma_maxburst = <4>;
 			#dma-cells = <1>;
-			clocks = <&dummy_clock_apb>;
+			clocks = <&audiosys_clk_gate LIGHT_CLKGEN_AUDIO_I2S0>;
 			clock-names = "pclk";
 			status = "disabled";
 		};
@@ -1525,33 +1636,317 @@
 			light,sel = "i2s1";
 			interrupt-parent = <&intc>;
 			interrupts = <175>;
-			dmas = <&dmac2 11>, <&dmac2 17>;
+			dmas = <&dmac2 11>, <&dmac2 10>;
 			dma-names = "tx", "rx";
 			light,dma_maxburst = <4>;
 			#dma-cells = <1>;
-			clocks = <&dummy_clock_apb>;
+			clocks = <&audiosys_clk_gate LIGHT_CLKGEN_AUDIO_I2S1>;
 			clock-names = "pclk";
 			status = "disabled";
 		};
 
-		i2s3: audio_i2s3@0xffcb017000 {
+		i2s2: audio_i2s2@0xffcb016000 {
 			#sound-dai-cells = <1>;
 			compatible = "light,light-i2s";
-			reg = <0xff 0xcb017000 0x0 0x1000>;
+			reg = <0xff 0xcb016000 0x0 0x1000>;
+			audio-pin-regmap = <&audio_ioctrl>;
+			audio-cpr-regmap = <&audio_cpr>;
 			pinctrl-names = "default";
 			light,mode = "i2s-master";
-			light,sel = "i2s3";
+			light,sel = "i2s2";
 			interrupt-parent = <&intc>;
-			interrupts = <177>;
+			interrupts = <176>;
-			dmas = <&dmac2 14>, <&dmac2 16>;
+			dmas = <&dmac2 13>, <&dmac2 12>;
 			dma-names = "tx", "rx";
 			light,dma_maxburst = <4>;
 			#dma-cells = <1>;
-			clocks = <&dummy_clock_apb>;
+			clocks = <&audiosys_clk_gate LIGHT_CLKGEN_AUDIO_I2S2>;
 			clock-names = "pclk";
 			status = "disabled";
 		};
 
+		i2s_8ch_sd0: audio_i2s_8ch_sd0@0xffcb017000 {
+			#sound-dai-cells = <1>;
+			compatible = "light,light-i2s-8ch";
+			reg = <0xff 0xcb017000 0x0 0x1000>;
+			audio-cpr-regmap = <&audio_cpr>;
+			pinctrl-names = "default";
+			light,mode = "i2s-master";
+			light,sel = "i2s_8ch_sd0";
+			interrupt-parent = <&intc>;
+			interrupts = <177>;
+			dmas = <&dmac2 36>, <&dmac2 14>;
+			dma-names = "tx", "rx";
+			light,dma_maxburst = <4>;
+			#dma-cells = <1>;
+			clocks = <&audiosys_clk_gate LIGHT_CLKGEN_AUDIO_I2S8CH>;
+			clock-names = "pclk";
+			status = "disabled";
+		};
+
+		i2s_8ch_sd1: audio_i2s_8ch_sd1@0xffcb017000 {
+			#sound-dai-cells = <1>;
+			compatible = "light,light-i2s-8ch";
+			reg = <0xff 0xcb017000 0x0 0x1000>;
+			audio-cpr-regmap = <&audio_cpr>;
+			pinctrl-names = "default";
+			light,mode = "i2s-master";
+			light,sel = "i2s_8ch_sd1";
+			interrupt-parent = <&intc>;
+			interrupts = <177>;
+			dmas = <&dmac2 37>, <&dmac2 15>;
+			dma-names = "tx", "rx";
+			light,dma_maxburst = <4>;
+			#dma-cells = <1>;
+			clocks = <&audiosys_clk_gate LIGHT_CLKGEN_AUDIO_I2S8CH>;
+			clock-names = "pclk";
+			status = "disabled";
+		};
+
+		i2s_8ch_sd2: audio_i2s_8ch_sd2@0xffcb017000 {
+			#sound-dai-cells = <1>;
+			compatible = "light,light-i2s-8ch";
+			reg = <0xff 0xcb017000 0x0 0x1000>;
+			audio-cpr-regmap = <&audio_cpr>;
+			pinctrl-names = "default";
+			light,mode = "i2s-master";
+			light,sel = "i2s_8ch_sd2";
+			interrupt-parent = <&intc>;
+			interrupts = <177>;
+			dmas = <&dmac2 38>, <&dmac2 16>;
+			dma-names = "tx", "rx";
+			light,dma_maxburst = <4>;
+			#dma-cells = <1>;
+			clocks = <&audiosys_clk_gate LIGHT_CLKGEN_AUDIO_I2S8CH>;
+			clock-names = "pclk";
+			status = "disabled";
+		};
+
+		i2s_8ch_sd3: audio_i2s_8ch_sd3@0xffcb017000 {
+			#sound-dai-cells = <1>;
+			compatible = "light,light-i2s-8ch";
+			reg = <0xff 0xcb017000 0x0 0x1000>;
+			audio-cpr-regmap = <&audio_cpr>;
+			pinctrl-names = "default";
+			light,mode = "i2s-master";
+			light,sel = "i2s_8ch_sd3";
+			interrupt-parent = <&intc>;
+			interrupts = <177>;
+			dmas = <&dmac2 39>, <&dmac2 17>;
+			dma-names = "tx", "rx";
+			light,dma_maxburst = <4>;
+			#dma-cells = <1>;
+			clocks = <&audiosys_clk_gate LIGHT_CLKGEN_AUDIO_I2S8CH>;
+			clock-names = "pclk";
+			status = "disabled";
+		};
+
+		tdm_slot1: audio_tdm_slot1@0xffcb012000 {
+			#sound-dai-cells = <0>;
+			compatible = "light,light-tdm";
+			reg = <0xff 0xcb012000 0x0 0x1000>;
+			audio-pin-regmap = <&audio_ioctrl>;
+			audio-cpr-regmap = <&audio_cpr>;
+			pinctrl-names = "default";
+			light,mode = "i2s-master";
+			light,tdm_slots = <8>;
+			light,tdm_slot_num = <1>;
+			interrupt-parent = <&intc>;
+			interrupts = <178>;
+			dmas = <&dmac2 28>;
+			dma-names = "rx";
+			light,dma_maxburst = <4>;
+			#dma-cells = <1>;
+			clocks = <&audiosys_clk_gate LIGHT_CLKGEN_AUDIO_TDM>;
+			clock-names = "pclk";
+			status = "disabled";
+		};
+
+		tdm_slot2: audio_tdm_slot2@0xffcb012000 {
+			#sound-dai-cells = <0>;
+			compatible = "light,light-tdm";
+			reg = <0xff 0xcb012000 0x0 0x1000>;
+			audio-pin-regmap = <&audio_ioctrl>;
+			audio-cpr-regmap = <&audio_cpr>;
+			pinctrl-names = "default";
+			light,mode = "i2s-master";
+			light,tdm_slots = <8>;
+			light,tdm_slot_num = <2>;
+			interrupt-parent = <&intc>;
+			interrupts = <178>;
+			dmas = <&dmac2 29>;
+			dma-names = "rx";
+			light,dma_maxburst = <4>;
+			#dma-cells = <1>;
+			clocks = <&audiosys_clk_gate LIGHT_CLKGEN_AUDIO_TDM>;
+			clock-names = "pclk";
+			status = "disabled";
+		};
+
+		tdm_slot3: audio_tdm_slot3@0xffcb012000 {
+			#sound-dai-cells = <0>;
+			compatible = "light,light-tdm";
+			reg = <0xff 0xcb012000 0x0 0x1000>;
+			audio-pin-regmap = <&audio_ioctrl>;
+			audio-cpr-regmap = <&audio_cpr>;
+			pinctrl-names = "default";
+			light,mode = "i2s-master";
+			light,tdm_slots = <8>;
+			light,tdm_slot_num = <3>;
+			interrupt-parent = <&intc>;
+			interrupts = <178>;
+			dmas = <&dmac2 30>;
+			dma-names = "rx";
+			light,dma_maxburst = <4>;
+			#dma-cells = <1>;
+			clocks = <&audiosys_clk_gate LIGHT_CLKGEN_AUDIO_TDM>;
+			clock-names = "pclk";
+			status = "disabled";
+		};
+
+		tdm_slot4: audio_tdm_slot4@0xffcb012000 {
+			#sound-dai-cells = <0>;
+			compatible = "light,light-tdm";
+			reg = <0xff 0xcb012000 0x0 0x1000>;
+			audio-pin-regmap = <&audio_ioctrl>;
+			audio-cpr-regmap = <&audio_cpr>;
+			pinctrl-names = "default";
+			light,mode = "i2s-master";
+			light,tdm_slots = <8>;
+			light,tdm_slot_num = <4>;
+			interrupt-parent = <&intc>;
+			interrupts = <178>;
+			dmas = <&dmac2 31>;
+			dma-names = "rx";
+			light,dma_maxburst = <4>;
+			#dma-cells = <1>;
+			clocks = <&audiosys_clk_gate LIGHT_CLKGEN_AUDIO_TDM>;
+			clock-names = "pclk";
+			status = "disabled";
+		};
+
+		tdm_slot5: audio_tdm_slot5@0xffcb012000 {
+			#sound-dai-cells = <0>;
+			compatible = "light,light-tdm";
+			reg = <0xff 0xcb012000 0x0 0x1000>;
+			audio-pin-regmap = <&audio_ioctrl>;
+			audio-cpr-regmap = <&audio_cpr>;
+			pinctrl-names = "default";
+			light,mode = "i2s-master";
+			light,tdm_slots = <8>;
+			light,tdm_slot_num = <5>;
+			interrupt-parent = <&intc>;
+			interrupts = <178>;
+			dmas = <&dmac2 32>;
+			dma-names = "rx";
+			light,dma_maxburst = <4>;
+			#dma-cells = <1>;
+			clocks = <&audiosys_clk_gate LIGHT_CLKGEN_AUDIO_TDM>;
+			clock-names = "pclk";
+			status = "disabled";
+		};
+
+		tdm_slot6: audio_tdm_slot6@0xffcb012000 {
+			#sound-dai-cells = <0>;
+			compatible = "light,light-tdm";
+			reg = <0xff 0xcb012000 0x0 0x1000>;
+			audio-pin-regmap = <&audio_ioctrl>;
+			audio-cpr-regmap = <&audio_cpr>;
+			pinctrl-names = "default";
+			light,mode = "i2s-master";
+			light,tdm_slots = <8>;
+			light,tdm_slot_num = <6>;
+			interrupt-parent = <&intc>;
+			interrupts = <178>;
+			dmas = <&dmac2 33>;
+			dma-names = "rx";
+			light,dma_maxburst = <4>;
+			#dma-cells = <1>;
+			clocks = <&audiosys_clk_gate LIGHT_CLKGEN_AUDIO_TDM>;
+			clock-names = "pclk";
+			status = "disabled";
+		};
+
+		tdm_slot7: audio_tdm_slot7@0xffcb012000 {
+			#sound-dai-cells = <0>;
+			compatible = "light,light-tdm";
+			reg = <0xff 0xcb012000 0x0 0x1000>;
+			audio-pin-regmap = <&audio_ioctrl>;
+			audio-cpr-regmap = <&audio_cpr>;
+			pinctrl-names = "default";
+			light,mode = "i2s-master";
+			light,tdm_slots = <8>;
+			light,tdm_slot_num = <7>;
+			interrupt-parent = <&intc>;
+			interrupts = <178>;
+			dmas = <&dmac2 34>;
+			dma-names = "rx";
+			light,dma_maxburst = <4>;
+			#dma-cells = <1>;
+			clocks = <&audiosys_clk_gate LIGHT_CLKGEN_AUDIO_TDM>;
+			clock-names = "pclk";
+			status = "disabled";
+		};
+
+		tdm_slot8: audio_tdm_slot8@0xffcb012000 {
+			#sound-dai-cells = <0>;
+			compatible = "light,light-tdm";
+			reg = <0xff 0xcb012000 0x0 0x1000>;
+			audio-pin-regmap = <&audio_ioctrl>;
+			audio-cpr-regmap = <&audio_cpr>;
+			pinctrl-names = "default";
+			light,mode = "i2s-master";
+			light,tdm_slots = <8>;
+			light,tdm_slot_num = <8>;
+			interrupt-parent = <&intc>;
+			interrupts = <178>;
+			dmas = <&dmac2 35>;
+			dma-names = "rx";
+			light,dma_maxburst = <4>;
+			#dma-cells = <1>;
+			clocks = <&audiosys_clk_gate LIGHT_CLKGEN_AUDIO_TDM>;
+			clock-names = "pclk";
+			status = "disabled";
+		};
+
+		spdif0: audio_spdif0@0xffcb018000 {
+			#sound-dai-cells = <0>;
+			compatible = "light,light-spdif";
+			reg = <0xff 0xcb018000 0x0 0x1000>;
+			audio-pin-regmap = <&audio_ioctrl>;
+			audio-cpr-regmap = <&audio_cpr>;
+			pinctrl-names = "default";
+			interrupt-parent = <&intc>;
+			interrupts = <179>;
+			dmas = <&dmac2 25>, <&dmac2 24>;
+			dma-names = "tx", "rx";
+			light,dma_maxburst = <4>;
+			#dma-cells = <1>;
+			clocks = <&audiosys_clk_gate LIGHT_CLKGEN_AUDIO_SPDIF0>;
+			clock-names = "pclk";
+			id = <0>;
+			status = "disabled";
+		};
+
+		spdif1: audio_spdif1@0xffcb019000 {
+			#sound-dai-cells = <0>;
+			compatible = "light,light-spdif";
+			reg = <0xff 0xcb019000 0x0 0x1000>;
+			audio-pin-regmap = <&audio_ioctrl>;
+			audio-cpr-regmap = <&audio_cpr>;
+			pinctrl-names = "default";
+			interrupt-parent = <&intc>;
+			interrupts = <180>;
+			dmas = <&dmac2 27>, <&dmac2 26>;
+			dma-names = "tx", "rx";
+			light,dma_maxburst = <4>;
+			#dma-cells = <1>;
+			clocks = <&audiosys_clk_gate LIGHT_CLKGEN_AUDIO_SPDIF1>;
+			clock-names = "pclk";
+			id = <1>;
+			status = "disabled";
+		};
+
 		pvt: pvt@fffff4e000 {
 		    compatible = "moortec,mr75203";
 		    reg = <0xff 0xfff4e000 0x0 0x80>,
@@ -1569,8 +1964,13 @@
 			reg = <0xff 0xe7f20000 0x0 0x4000>;
 			interrupt-parent = <&intc>;
 			interrupts = <44>;
-			clocks = <&dummy_clock_apb>;
+			clocks = <&clk CLKGEN_I2C0_PCLK>;
+			clock-names = "pclk";
 			clock-frequency = <100000>;
+            i2c_mode = "dma";
+			dmas = <&dmac0 12>, <&dmac0 13>;
+			dma-names = "tx", "rx";
+			#dma-cells = <1>;
 			ss_hcnt = /bits/ 16 <0x104>;
 			ss_lcnt = /bits/ 16 <0xec>;
 			fs_hcnt = /bits/ 16 <0x37>;
@@ -1588,8 +1988,13 @@
 			reg = <0xff 0xe7f24000 0x0 0x4000>;
 			interrupt-parent = <&intc>;
 			interrupts = <45>;
-			clocks = <&dummy_clock_apb>;
+			clocks = <&clk CLKGEN_I2C1_PCLK>;
+			clock-names = "pclk";
 			clock-frequency = <100000>;
+            i2c_mode = "dma";
+			dmas = <&dmac0 14>, <&dmac0 15>;
+			dma-names = "tx", "rx";
+			#dma-cells = <1>;
 			ss_hcnt = /bits/ 16 <0x104>;
 			ss_lcnt = /bits/ 16 <0xec>;
 			fs_hcnt = /bits/ 16 <0x37>;
@@ -1607,8 +2012,13 @@
 			reg = <0xff 0xec00c000 0x0 0x4000>;
 			interrupt-parent = <&intc>;
 			interrupts = <46>;
-			clocks = <&dummy_clock_apb>;
+			clocks = <&clk CLKGEN_I2C2_PCLK>;
+			clock-names = "pclk";
 			clock-frequency = <100000>;
+            i2c_mode = "dma";
+			dmas = <&dmac0 16>, <&dmac0 17>;
+			dma-names = "tx", "rx";
+			#dma-cells = <1>;
 			ss_hcnt = /bits/ 16 <0x104>;
 			ss_lcnt = /bits/ 16 <0xec>;
 			fs_hcnt = /bits/ 16 <0x37>;
@@ -1628,8 +2038,13 @@
 			reg = <0xff 0xec014000 0x0 0x4000>;
 			interrupt-parent = <&intc>;
 			interrupts = <47>;
-			clocks = <&dummy_clock_apb>;
+			clocks = <&clk CLKGEN_I2C3_PCLK>;
+			clock-names = "pclk";
 			clock-frequency = <100000>;
+            i2c_mode = "dma";
+			dmas = <&dmac0 18>, <&dmac0 19>;
+			dma-names = "tx", "rx";
+			#dma-cells = <1>;
 			ss_hcnt = /bits/ 16 <0x104>;
 			ss_lcnt = /bits/ 16 <0xec>;
 			fs_hcnt = /bits/ 16 <0x37>;
@@ -1649,8 +2064,13 @@
 			reg = <0xff 0xe7f28000 0x0 0x4000>;
 			interrupt-parent = <&intc>;
 			interrupts = <48>;
-			clocks = <&dummy_clock_apb>;
+			clocks = <&clk CLKGEN_I2C4_PCLK>;
+			clock-names = "pclk";
 			clock-frequency = <100000>;
+            i2c_mode = "dma";
+			dmas = <&dmac0 20>, <&dmac0 21>;
+			dma-names = "tx", "rx";
+			#dma-cells = <1>;
 			ss_hcnt = /bits/ 16 <0x104>;
 			ss_lcnt = /bits/ 16 <0xec>;
 			fs_hcnt = /bits/ 16 <0x37>;
@@ -1672,6 +2092,10 @@
 			interrupts = <182>;
 			clocks = <&dummy_clock_apb>;
 			clock-frequency = <100000>;
+            i2c_mode = "dma";
+			dmas = <&dmac2 21>, <&dmac2 20>;
+			dma-names = "tx", "rx";
+			#dma-cells = <1>;
 			ss_hcnt = /bits/ 16 <0x82>;
 			ss_lcnt = /bits/ 16 <0x78>;
 			fs_hcnt = /bits/ 16 <0x37>;
@@ -1684,6 +2108,31 @@
 			#size-cells = <0>;
 		};
 
+        audio_i2c1: i2c@0xffcb01b000 {
+                compatible = "snps,designware-i2c";
+                reg = <0xff 0xcb01b000 0x0 0x1000>;
+                interrupt-parent = <&intc>;
+                interrupts = <183>;
+                clocks = <&dummy_clock_apb>;
+                clock-frequency = <100000>;
+                i2c_mode = "dma";
+			    dmas = <&dmac2 23>, <&dmac2 22>;
+			    dma-names = "tx", "rx";
+			    #dma-cells = <1>;
+                ss_hcnt = /bits/ 16 <0x82>;
+                ss_lcnt = /bits/ 16 <0x78>;
+                fs_hcnt = /bits/ 16 <0x37>;
+                fs_lcnt = /bits/ 16 <0x42>;
+                fp_hcnt = /bits/ 16 <0x14>;
+                fp_lcnt = /bits/ 16 <0x1a>;
+                hs_hcnt = /bits/ 16 <0x5>;
+                hs_lcnt = /bits/ 16 <0x15>;
+                status = "disabled";
+
+                #address-cells = <1>;
+                #size-cells = <0>;
+        };
+
 		isp0: isp@ffe4100000 {
 			compatible = "thead,light-isp";
 			reg = <0xff 0xe4100000 0x0 0x10000>;
@@ -1769,10 +2218,8 @@
 		    sysreg_mipi_csi_ctrl = <0x140>;
 		    clocks = <&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI0_PCLK>,
 		             <&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI0_PIXCLK>,
-				 <&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI0_CFG_CLK>,
+		             <&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI0_CFG_CLK>;
-				 <&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI1_CFG_CLK>,
+		    clock-names = "pclk", "pixclk", "cfg_clk";
-				 <&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI2_CFG_CLK>;
-				clock-names = "pclk", "pixclk", "cfg_clk0", "cfg_clk1", "cfg_clk2";
 		    phy_name = "CSI_4LANE";
 		    status = "disabled";
 		};
@@ -1794,10 +2241,8 @@
 		    csia-regmap = <&csia_reg>;
 		    clocks = <&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI1_PCLK>,
 		             <&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI1_PIXCLK>,
-				 <&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI0_CFG_CLK>,
+		             <&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI1_CFG_CLK>;
-				 <&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI1_CFG_CLK>,
+		    clock-names = "pclk", "pixclk", "cfg_clk";
-				 <&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI2_CFG_CLK>;
-			clock-names = "pclk", "pixclk", "cfg_clk0", "cfg_clk1", "cfg_clk2";
 		    phy_name = "CSI_B";
 		    status = "disabled";
 		};
@@ -1811,15 +2256,12 @@
 		    sysreg_mipi_csi_ctrl = <0x144>;
 		    clocks = <&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI2_PCLK>,
 		             <&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI2_PIXCLK>,
-				 <&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI0_CFG_CLK>,
-				 <&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI1_CFG_CLK>,
 		             <&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI2_CFG_CLK>;
-			clock-names = "pclk", "pixclk", "cfg_clk0", "cfg_clk1", "cfg_clk2";
+		    clock-names = "pclk", "pixclk", "cfg_clk";
 		    phy_name = "CSI_A";
 		    status = "disabled";
 		};
 
-
 		bm_isp0: bm_isp@ffe4100000 {
 			compatible = "thead,light-bm-isp";
 			reg = <0xff 0xe4100000 0x0 0x10000>;
@@ -1970,6 +2412,11 @@
 			status = "disabled";
 		};
 
+		vvcam_sensor7: vvcam_sensor@7 {
+			compatible = "thead,light-vvcam-sensor";
+			status = "disabled";
+		};
+
 		xtensa_dsp: dsp@01{
 			compatible = "thead,dsp-hw-common";
 			reg = <0xff 0xef040000 0x0 0x001000 >;   /*DSP_SYSREG(0x0000-0xFFF) */
@@ -2109,7 +2556,11 @@
 			reg = <0xff 0xff300000 0x0 0x40000>;
 			interrupt-parent = <&intc>;
 			interrupts = <144>,<145>,<146>,<147>;
-			clocks = <&dummy_clock_eip>;
+			clocks = <&miscsys_clk_gate CLKGEN_MISCSYS_EIP120SI_CLK>,
+					<&miscsys_clk_gate CLKGEN_MISCSYS_EIP120SII_CLK>,
+					<&miscsys_clk_gate CLKGEN_MISCSYS_EIP120SIII_CLK>,
+					<&miscsys_clk_gate CLKGEN_MISCSYS_EIP150B_HCLK>;
+			clock-names = "120si_clk","120sii_clk","120siii_clk","hclk";
 			status = "disabled";
 		};
 
@@ -2119,6 +2570,17 @@
 			interrupts = <215>; /* TEE INT SRC_7 */
 		};
 
+        light_event: light-event {
+                compatible = "thead,light-event";
+                aon-iram-regmap = <&aon_iram>;
+                status = "okay";
+        };
+
+		aon_suspend_ctrl: aon_suspend_ctrl {
+		        compatible = "thead,light-aon-suspend-ctrl";
+		        status = "okay";
+		};
+
 		visys_clk_gate: visys-clk-gate { /* VI_SYSREG_R */
 			compatible = "thead,visys-gate-controller";
 			visys-regmap = <&visys_reg>;
@@ -2146,6 +2608,22 @@
 			#clock-cells = <1>;
 			status = "okay";
 		};
+
+		audiosys_clk_gate: audiosys-clk-gate {
+			compatible = "thead,audiosys-gate-controller";
+			audiosys-regmap = <&audio_cpr>;
+			#clock-cells = <1>;
+			status = "okay";
+		};
+
+		miscsys_clk_gate: miscsys-clk-gate {
+			compatible = "thead,miscsys-gate-controller";
+			miscsys-regmap = <&miscsys_reg>;
+			tee-miscsys-regmap = <&tee_miscsys_reg>;
+			#clock-cells = <1>;
+			status = "okay";
+		};
+
 	};
 
 };

arch/riscv/configs/defconfig

@@ -17,6 +17,12 @@ CONFIG_PERF_EVENTS=y
 CONFIG_SOC_THEAD=y
 CONFIG_SMP=y
 CONFIG_VECTOR=y
+CONFIG_HOTPLUG_CPU=y
+CONFIG_PM=y
+CONFIG_CPU_IDLE=y
+CONFIG_VIRTUALIZATION=y
+CONFIG_KVM=m
+CONFIG_JUMP_LABEL=y
 CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
 CONFIG_PARTITION_ADVANCED=y
@@ -183,6 +189,5 @@ CONFIG_DEBUG_INFO=y
 CONFIG_MAGIC_SYSRQ=y
 CONFIG_DEBUG_FS=y
 CONFIG_DETECT_HUNG_TASK=y
-CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=60
 CONFIG_DEBUG_ATOMIC_SLEEP=y
 # CONFIG_RCU_TRACE is not set

arch/riscv/configs/fire_defconfig

@@ -0,0 +1,311 @@
+CONFIG_SYSVIPC=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_NO_HZ_IDLE=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_PREEMPT=y
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_CGROUPS=y
+CONFIG_NAMESPACES=y
+CONFIG_USER_NS=y
+CONFIG_CHECKPOINT_RESTORE=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_EXPERT=y
+# CONFIG_BUG is not set
+CONFIG_BPF_SYSCALL=y
+CONFIG_PERF_EVENTS=y
+CONFIG_FORCE_MAX_ZONEORDER=15
+CONFIG_SOC_SIFIVE=y
+CONFIG_SOC_THEAD=y
+CONFIG_SMP=y
+CONFIG_VECTOR=y
+CONFIG_VECTOR_0_7=y
+CONFIG_KEXEC=y
+CONFIG_CRASH_DUMP=y
+CONFIG_VIRTUALIZATION=y
+CONFIG_KVM=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_CMA=y
+CONFIG_CMA_DEBUGFS=y
+CONFIG_CMA_AREAS=16
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_ADVANCED_ROUTER=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_IP_PNP_RARP=y
+CONFIG_BRIDGE=y
+CONFIG_VSOCKETS=y
+# CONFIG_VSOCKETS_LOOPBACK is not set
+CONFIG_VIRTIO_VSOCKETS=y
+CONFIG_NETLINK_DIAG=y
+CONFIG_BT=y
+CONFIG_BT_RFCOMM=y
+CONFIG_BT_RFCOMM_TTY=y
+CONFIG_BT_BNEP=y
+CONFIG_BT_HIDP=y
+CONFIG_BT_HCIUART=y
+CONFIG_BT_HCIUART_H4=y
+CONFIG_BT_HCIUART_RTL3WIRE=y
+CONFIG_CFG80211=y
+CONFIG_RFKILL=y
+CONFIG_NET_9P=y
+CONFIG_NET_9P_VIRTIO=y
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+CONFIG_MTD=y
+CONFIG_MTD_TESTS=m
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_SLRAM=m
+CONFIG_MTD_PHRAM=m
+CONFIG_MTD_SPI_NAND=y
+CONFIG_MTD_SPI_NOR=y
+CONFIG_MTD_UBI=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_VIRTIO_BLK=y
+CONFIG_LIGHT_DSMART_CARD=y
+CONFIG_EEPROM_AT24=y
+CONFIG_SCSI=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_NETDEVICES=y
+CONFIG_TUN=y
+CONFIG_VIRTIO_NET=y
+CONFIG_MACB=y
+CONFIG_STMMAC_ETH=y
+CONFIG_DWMAC_LIGHT=y
+CONFIG_MICROSEMI_PHY=y
+CONFIG_REALTEK_PHY=y
+CONFIG_MARVELL_PHY=y
+CONFIG_USB_USBNET=m
+# CONFIG_USB_NET_AX8817X is not set
+# CONFIG_USB_NET_AX88179_178A is not set
+# CONFIG_USB_NET_NET1080 is not set
+CONFIG_RTL8723DS=y
+CONFIG_INPUT_MOUSEDEV=y
+CONFIG_INPUT_EVDEV=y
+CONFIG_KEYBOARD_GPIO=y
+# CONFIG_INPUT_MOUSE is not set
+CONFIG_INPUT_TOUCHSCREEN=y
+CONFIG_TOUCHSCREEN_GOODIX=y
+CONFIG_INPUT_MISC=y
+CONFIG_INPUT_UINPUT=y
+CONFIG_SERIAL_8250=y
+# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_NR_UARTS=6
+CONFIG_SERIAL_8250_RUNTIME_UARTS=6
+CONFIG_SERIAL_8250_DW=y
+CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_SERIAL_EARLYCON_RISCV_SBI=y
+CONFIG_VIRTIO_CONSOLE=y
+CONFIG_HW_RANDOM=y
+CONFIG_HW_RANDOM_VIRTIO=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_DESIGNWARE_PLATFORM=y
+CONFIG_SPI=y
+CONFIG_SPI_DW_QUAD=y
+CONFIG_SPI_DESIGNWARE=y
+CONFIG_SPI_DW_MMIO=y
+CONFIG_SPI_SPIDEV=y
+# CONFIG_PTP_1588_CLOCK is not set
+CONFIG_PINCTRL=y
+CONFIG_GPIOLIB=y
+CONFIG_GPIO_SYSFS=y
+CONFIG_GPIO_DWAPB=y
+CONFIG_GPIO_PCA953X=y
+CONFIG_GPIO_PCA953X_IRQ=y
+CONFIG_POWER_SUPPLY=y
+CONFIG_SENSORS_MR75203=y
+CONFIG_THERMAL=y
+CONFIG_CPU_THERMAL=y
+CONFIG_THERMAL_EMULATION=y
+CONFIG_WATCHDOG=y
+CONFIG_DW_WATCHDOG=y
+CONFIG_LIGHT_PMIC_WATCHDOG=y
+CONFIG_WATCHDOG_PRETIMEOUT_GOV=y
+CONFIG_WATCHDOG_PRETIMEOUT_GOV_SEL=m
+CONFIG_WATCHDOG_PRETIMEOUT_GOV_PANIC=y
+#CONFIG_WATCHDOG_PRETIMEOUT_DEFAULT_GOV_PANIC=y
+CONFIG_WATCHDOG_PRETIMEOUT_DEFAULT_GOV_NOOP=y
+CONFIG_WATCHDOG_OPEN_TIMEOUT=32
+CONFIG_ABX500_CORE=y
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+CONFIG_MEDIA_SUPPORT=y
+# CONFIG_MEDIA_ANALOG_TV_SUPPORT is not set
+# CONFIG_MEDIA_DIGITAL_TV_SUPPORT is not set
+CONFIG_MEDIA_USB_SUPPORT=y
+CONFIG_USB_VIDEO_CLASS=m
+CONFIG_V4L_PLATFORM_DRIVERS=y
+CONFIG_VIDEO_ASPEED=y
+CONFIG_V4L_MEM2MEM_DRIVERS=y
+# CONFIG_MEDIA_TUNER_SIMPLE is not set
+# CONFIG_MEDIA_TUNER_TDA18250 is not set
+# CONFIG_MEDIA_TUNER_TDA8290 is not set
+# CONFIG_MEDIA_TUNER_TDA827X is not set
+# CONFIG_MEDIA_TUNER_TDA18271 is not set
+# CONFIG_MEDIA_TUNER_TDA9887 is not set
+# CONFIG_MEDIA_TUNER_TEA5761 is not set
+# CONFIG_MEDIA_TUNER_TEA5767 is not set
+# CONFIG_MEDIA_TUNER_MSI001 is not set
+# CONFIG_MEDIA_TUNER_MT20XX is not set
+# CONFIG_MEDIA_TUNER_MT2060 is not set
+# CONFIG_MEDIA_TUNER_MT2063 is not set
+# CONFIG_MEDIA_TUNER_MT2266 is not set
+# CONFIG_MEDIA_TUNER_MT2131 is not set
+# CONFIG_MEDIA_TUNER_QT1010 is not set
+# CONFIG_MEDIA_TUNER_XC2028 is not set
+# CONFIG_MEDIA_TUNER_XC5000 is not set
+# CONFIG_MEDIA_TUNER_XC4000 is not set
+# CONFIG_MEDIA_TUNER_MXL5005S is not set
+# CONFIG_MEDIA_TUNER_MXL5007T is not set
+# CONFIG_MEDIA_TUNER_MC44S803 is not set
+# CONFIG_MEDIA_TUNER_MAX2165 is not set
+# CONFIG_MEDIA_TUNER_TDA18218 is not set
+# CONFIG_MEDIA_TUNER_FC0011 is not set
+# CONFIG_MEDIA_TUNER_FC0012 is not set
+# CONFIG_MEDIA_TUNER_FC0013 is not set
+# CONFIG_MEDIA_TUNER_TDA18212 is not set
+# CONFIG_MEDIA_TUNER_E4000 is not set
+# CONFIG_MEDIA_TUNER_FC2580 is not set
+# CONFIG_MEDIA_TUNER_M88RS6000T is not set
+# CONFIG_MEDIA_TUNER_TUA9001 is not set
+# CONFIG_MEDIA_TUNER_SI2157 is not set
+# CONFIG_MEDIA_TUNER_IT913X is not set
+# CONFIG_MEDIA_TUNER_R820T is not set
+# CONFIG_MEDIA_TUNER_MXL301RF is not set
+# CONFIG_MEDIA_TUNER_QM1D1C0042 is not set
+# CONFIG_MEDIA_TUNER_QM1D1B0004 is not set
+CONFIG_DRM=y
+CONFIG_DRM_PANEL_SIMPLE=y
+CONFIG_DRM_PANEL_ILITEK_ILI9881C=y
+CONFIG_DRM_PANEL_ILI9881D=y
+CONFIG_DRM_VERISILICON=y
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+CONFIG_BACKLIGHT_PWM=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+CONFIG_LOGO=y
+CONFIG_SOUND=y
+CONFIG_SND=y
+CONFIG_SND_USB_AUDIO=m
+CONFIG_SND_SOC=y
+CONFIG_SND_SOC_THEAD_LIGHT=y
+CONFIG_SND_SOC_AW87519=y
+CONFIG_SND_SOC_BT_SCO=y
+CONFIG_SND_SOC_ES7210=y
+CONFIG_SND_SOC_ES8156=y
+CONFIG_SND_SOC_WM8960=y
+CONFIG_SND_SIMPLE_CARD=y
+CONFIG_SND_AUDIO_GRAPH_CARD=y
+CONFIG_UHID=y
+CONFIG_HID_PID=y
+CONFIG_USB_HIDDEV=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_PLATFORM=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_STORAGE_SDDR09=y
+CONFIG_USB_STORAGE_SDDR55=y
+CONFIG_USB_DWC3=m
+# CONFIG_USB_DWC3_OF_SIMPLE is not set
+CONFIG_USB_GADGET=y
+CONFIG_USB_CONFIGFS=y
+CONFIG_USB_CONFIGFS_F_FS=y
+CONFIG_USB_CONFIGFS_F_ACC=y
+CONFIG_USB_ZERO=m
+CONFIG_USB_ETH=m
+CONFIG_USB_ETH_EEM=y
+CONFIG_USB_G_NCM=m
+CONFIG_USB_MASS_STORAGE=m
+CONFIG_USB_G_SERIAL=m
+CONFIG_USB_G_MULTI=m
+CONFIG_USB_G_MULTI_CDC=y
+CONFIG_USB_ROLE_SWITCH=m
+CONFIG_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_MMC_SDHCI_OF_DWCMSHC=y
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+CONFIG_LEDS_GPIO=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_XGENE=y
+CONFIG_DMADEVICES=y
+CONFIG_DW_AXI_DMAC=y
+CONFIG_DMATEST=y
+CONFIG_SW_SYNC=y
+CONFIG_UDMABUF=y
+CONFIG_DMABUF_SELFTESTS=m
+CONFIG_VIRTIO_MMIO=y
+CONFIG_VIRTIO_KHV_MMIO=y
+CONFIG_VHOST_NET=y
+CONFIG_VHOST_VSOCK=y
+CONFIG_CLK_LIGHT_FM=y
+CONFIG_HWSPINLOCK=y
+CONFIG_HWSPINLOCK_LIGHT=y
+CONFIG_HWSPINLOCK_LIGHT_TEST=m
+CONFIG_MAILBOX=y
+CONFIG_EXTCON=y
+CONFIG_IIO=y
+CONFIG_IIO_SW_DEVICE=y
+CONFIG_PWM=y
+CONFIG_PWM_LIGHT=y
+CONFIG_NVMEM_THEAD_LIGHT_EFUSE=y
+CONFIG_TEE=y
+CONFIG_OPTEE=y
+CONFIG_OPTEE_BENCHMARK=y
+CONFIG_LIGHT_GPU_VIV=m
+# CONFIG_LIGHT_NET is not set
+CONFIG_EXT4_FS=y
+CONFIG_EXT4_FS_POSIX_ACL=y
+CONFIG_AUTOFS4_FS=y
+CONFIG_FUSE_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_TMPFS=y
+CONFIG_TMPFS_POSIX_ACL=y
+CONFIG_HUGETLBFS=y
+CONFIG_JFFS2_FS=y
+CONFIG_UBIFS_FS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V4=y
+CONFIG_NFS_V4_1=y
+CONFIG_NFS_V4_2=y
+CONFIG_ROOT_NFS=y
+CONFIG_9P_FS=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_CRYPTO_AUTHENC=y
+CONFIG_CRYPTO_DH=y
+CONFIG_CRYPTO_CURVE25519=y
+CONFIG_CRYPTO_CHACHA20POLY1305=y
+CONFIG_CRYPTO_OFB=y
+CONFIG_CRYPTO_MD5=y
+CONFIG_CRYPTO_SHA512=y
+CONFIG_CRYPTO_SHA3=y
+CONFIG_CRYPTO_SM3=y
+CONFIG_CRYPTO_DES=y
+CONFIG_CRYPTO_USER_API_HASH=y
+CONFIG_DMA_CMA=y
+CONFIG_DMA_PERNUMA_CMA=y
+CONFIG_CMA_SIZE_MBYTES=32
+CONFIG_PRINTK_TIME=y
+CONFIG_DYNAMIC_DEBUG=y
+CONFIG_DEBUG_INFO=y
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_DEBUG_FS=y
+CONFIG_DETECT_HUNG_TASK=y
+CONFIG_DEBUG_ATOMIC_SLEEP=y
+# CONFIG_RCU_TRACE is not set
+CONFIG_OVERLAY_FS=y
+CONFIG_LOCKUP_DETECTOR=y
+CONFIG_SOFTLOCKUP_DETECTOR=y
+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
+# CONFIG_SUSPEND is not set
+# CONFIG_PM_SLEEP is not set

arch/riscv/configs/fire_emu_defconfig

@@ -0,0 +1,312 @@
+CONFIG_SYSVIPC=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_NO_HZ_IDLE=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_PREEMPT=y
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_CGROUPS=y
+CONFIG_NAMESPACES=y
+CONFIG_USER_NS=y
+CONFIG_CHECKPOINT_RESTORE=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_EXPERT=y
+# CONFIG_BUG is not set
+CONFIG_BPF_SYSCALL=y
+CONFIG_PERF_EVENTS=y
+CONFIG_FORCE_MAX_ZONEORDER=15
+CONFIG_SOC_SIFIVE=y
+CONFIG_SOC_THEAD=y
+CONFIG_SOC_THEAD_LIGHT_EMU=y
+CONFIG_SMP=y
+CONFIG_VECTOR=y
+CONFIG_VECTOR_0_7=y
+CONFIG_KEXEC=y
+CONFIG_CRASH_DUMP=y
+CONFIG_VIRTUALIZATION=y
+CONFIG_KVM=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_CMA=y
+CONFIG_CMA_DEBUGFS=y
+CONFIG_CMA_AREAS=16
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_ADVANCED_ROUTER=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_IP_PNP_RARP=y
+CONFIG_BRIDGE=y
+CONFIG_VSOCKETS=y
+# CONFIG_VSOCKETS_LOOPBACK is not set
+CONFIG_VIRTIO_VSOCKETS=y
+CONFIG_NETLINK_DIAG=y
+CONFIG_BT=y
+CONFIG_BT_RFCOMM=y
+CONFIG_BT_RFCOMM_TTY=y
+CONFIG_BT_BNEP=y
+CONFIG_BT_HIDP=y
+CONFIG_BT_HCIUART=y
+CONFIG_BT_HCIUART_H4=y
+CONFIG_BT_HCIUART_RTL3WIRE=y
+CONFIG_CFG80211=y
+CONFIG_RFKILL=y
+CONFIG_NET_9P=y
+CONFIG_NET_9P_VIRTIO=y
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+CONFIG_MTD=y
+CONFIG_MTD_TESTS=m
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_SLRAM=m
+CONFIG_MTD_PHRAM=m
+CONFIG_MTD_SPI_NAND=y
+CONFIG_MTD_SPI_NOR=y
+CONFIG_MTD_UBI=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_VIRTIO_BLK=y
+CONFIG_LIGHT_DSMART_CARD=y
+CONFIG_EEPROM_AT24=y
+CONFIG_SCSI=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_NETDEVICES=y
+CONFIG_TUN=y
+CONFIG_VIRTIO_NET=y
+CONFIG_MACB=y
+CONFIG_STMMAC_ETH=y
+CONFIG_DWMAC_LIGHT=y
+CONFIG_MICROSEMI_PHY=y
+CONFIG_REALTEK_PHY=y
+CONFIG_MARVELL_PHY=y
+CONFIG_USB_USBNET=m
+# CONFIG_USB_NET_AX8817X is not set
+# CONFIG_USB_NET_AX88179_178A is not set
+# CONFIG_USB_NET_NET1080 is not set
+CONFIG_RTL8723DS=y
+CONFIG_INPUT_MOUSEDEV=y
+CONFIG_INPUT_EVDEV=y
+CONFIG_KEYBOARD_GPIO=y
+# CONFIG_INPUT_MOUSE is not set
+CONFIG_INPUT_TOUCHSCREEN=y
+CONFIG_TOUCHSCREEN_GOODIX=y
+CONFIG_INPUT_MISC=y
+CONFIG_INPUT_UINPUT=y
+CONFIG_SERIAL_8250=y
+# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_NR_UARTS=6
+CONFIG_SERIAL_8250_RUNTIME_UARTS=6
+CONFIG_SERIAL_8250_DW=y
+CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_SERIAL_EARLYCON_RISCV_SBI=y
+CONFIG_VIRTIO_CONSOLE=y
+CONFIG_HW_RANDOM=y
+CONFIG_HW_RANDOM_VIRTIO=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_DESIGNWARE_PLATFORM=y
+CONFIG_SPI=y
+CONFIG_SPI_DW_QUAD=y
+CONFIG_SPI_DESIGNWARE=y
+CONFIG_SPI_DW_MMIO=y
+CONFIG_SPI_SPIDEV=y
+# CONFIG_PTP_1588_CLOCK is not set
+CONFIG_PINCTRL=y
+CONFIG_GPIOLIB=y
+CONFIG_GPIO_SYSFS=y
+CONFIG_GPIO_DWAPB=y
+CONFIG_GPIO_PCA953X=y
+CONFIG_GPIO_PCA953X_IRQ=y
+CONFIG_POWER_SUPPLY=y
+CONFIG_SENSORS_MR75203=y
+CONFIG_THERMAL=y
+CONFIG_CPU_THERMAL=y
+CONFIG_THERMAL_EMULATION=y
+CONFIG_WATCHDOG=y
+CONFIG_DW_WATCHDOG=y
+CONFIG_LIGHT_PMIC_WATCHDOG=y
+CONFIG_WATCHDOG_PRETIMEOUT_GOV=y
+CONFIG_WATCHDOG_PRETIMEOUT_GOV_SEL=m
+CONFIG_WATCHDOG_PRETIMEOUT_GOV_PANIC=y
+#CONFIG_WATCHDOG_PRETIMEOUT_DEFAULT_GOV_PANIC=y
+CONFIG_WATCHDOG_PRETIMEOUT_DEFAULT_GOV_NOOP=y
+CONFIG_WATCHDOG_OPEN_TIMEOUT=32
+CONFIG_ABX500_CORE=y
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+CONFIG_MEDIA_SUPPORT=y
+# CONFIG_MEDIA_ANALOG_TV_SUPPORT is not set
+# CONFIG_MEDIA_DIGITAL_TV_SUPPORT is not set
+CONFIG_MEDIA_USB_SUPPORT=y
+CONFIG_USB_VIDEO_CLASS=m
+CONFIG_V4L_PLATFORM_DRIVERS=y
+CONFIG_VIDEO_ASPEED=y
+CONFIG_V4L_MEM2MEM_DRIVERS=y
+# CONFIG_MEDIA_TUNER_SIMPLE is not set
+# CONFIG_MEDIA_TUNER_TDA18250 is not set
+# CONFIG_MEDIA_TUNER_TDA8290 is not set
+# CONFIG_MEDIA_TUNER_TDA827X is not set
+# CONFIG_MEDIA_TUNER_TDA18271 is not set
+# CONFIG_MEDIA_TUNER_TDA9887 is not set
+# CONFIG_MEDIA_TUNER_TEA5761 is not set
+# CONFIG_MEDIA_TUNER_TEA5767 is not set
+# CONFIG_MEDIA_TUNER_MSI001 is not set
+# CONFIG_MEDIA_TUNER_MT20XX is not set
+# CONFIG_MEDIA_TUNER_MT2060 is not set
+# CONFIG_MEDIA_TUNER_MT2063 is not set
+# CONFIG_MEDIA_TUNER_MT2266 is not set
+# CONFIG_MEDIA_TUNER_MT2131 is not set
+# CONFIG_MEDIA_TUNER_QT1010 is not set
+# CONFIG_MEDIA_TUNER_XC2028 is not set
+# CONFIG_MEDIA_TUNER_XC5000 is not set
+# CONFIG_MEDIA_TUNER_XC4000 is not set
+# CONFIG_MEDIA_TUNER_MXL5005S is not set
+# CONFIG_MEDIA_TUNER_MXL5007T is not set
+# CONFIG_MEDIA_TUNER_MC44S803 is not set
+# CONFIG_MEDIA_TUNER_MAX2165 is not set
+# CONFIG_MEDIA_TUNER_TDA18218 is not set
+# CONFIG_MEDIA_TUNER_FC0011 is not set
+# CONFIG_MEDIA_TUNER_FC0012 is not set
+# CONFIG_MEDIA_TUNER_FC0013 is not set
+# CONFIG_MEDIA_TUNER_TDA18212 is not set
+# CONFIG_MEDIA_TUNER_E4000 is not set
+# CONFIG_MEDIA_TUNER_FC2580 is not set
+# CONFIG_MEDIA_TUNER_M88RS6000T is not set
+# CONFIG_MEDIA_TUNER_TUA9001 is not set
+# CONFIG_MEDIA_TUNER_SI2157 is not set
+# CONFIG_MEDIA_TUNER_IT913X is not set
+# CONFIG_MEDIA_TUNER_R820T is not set
+# CONFIG_MEDIA_TUNER_MXL301RF is not set
+# CONFIG_MEDIA_TUNER_QM1D1C0042 is not set
+# CONFIG_MEDIA_TUNER_QM1D1B0004 is not set
+CONFIG_DRM=y
+CONFIG_DRM_PANEL_SIMPLE=y
+CONFIG_DRM_PANEL_ILITEK_ILI9881C=y
+CONFIG_DRM_PANEL_ILI9881D=y
+CONFIG_DRM_VERISILICON=y
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+CONFIG_BACKLIGHT_PWM=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+CONFIG_LOGO=y
+CONFIG_SOUND=y
+CONFIG_SND=y
+CONFIG_SND_USB_AUDIO=m
+CONFIG_SND_SOC=y
+CONFIG_SND_SOC_THEAD_LIGHT=y
+CONFIG_SND_SOC_AW87519=y
+CONFIG_SND_SOC_BT_SCO=y
+CONFIG_SND_SOC_ES7210=y
+CONFIG_SND_SOC_ES8156=y
+CONFIG_SND_SOC_WM8960=y
+CONFIG_SND_SIMPLE_CARD=y
+CONFIG_SND_AUDIO_GRAPH_CARD=y
+CONFIG_UHID=y
+CONFIG_HID_PID=y
+CONFIG_USB_HIDDEV=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_PLATFORM=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_STORAGE_SDDR09=y
+CONFIG_USB_STORAGE_SDDR55=y
+CONFIG_USB_DWC3=m
+# CONFIG_USB_DWC3_OF_SIMPLE is not set
+CONFIG_USB_GADGET=y
+CONFIG_USB_CONFIGFS=y
+CONFIG_USB_CONFIGFS_F_FS=y
+CONFIG_USB_CONFIGFS_F_ACC=y
+CONFIG_USB_ZERO=m
+CONFIG_USB_ETH=m
+CONFIG_USB_ETH_EEM=y
+CONFIG_USB_G_NCM=m
+CONFIG_USB_MASS_STORAGE=m
+CONFIG_USB_G_SERIAL=m
+CONFIG_USB_G_MULTI=m
+CONFIG_USB_G_MULTI_CDC=y
+CONFIG_USB_ROLE_SWITCH=m
+CONFIG_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_MMC_SDHCI_OF_DWCMSHC=y
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+CONFIG_LEDS_GPIO=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_XGENE=y
+CONFIG_DMADEVICES=y
+CONFIG_DW_AXI_DMAC=y
+CONFIG_DMATEST=y
+CONFIG_SW_SYNC=y
+CONFIG_UDMABUF=y
+CONFIG_DMABUF_SELFTESTS=m
+CONFIG_VIRTIO_MMIO=y
+CONFIG_VIRTIO_KHV_MMIO=y
+CONFIG_VHOST_NET=y
+CONFIG_VHOST_VSOCK=y
+CONFIG_CLK_LIGHT_FM=y
+CONFIG_HWSPINLOCK=y
+CONFIG_HWSPINLOCK_LIGHT=y
+CONFIG_HWSPINLOCK_LIGHT_TEST=m
+CONFIG_MAILBOX=y
+CONFIG_EXTCON=y
+CONFIG_IIO=y
+CONFIG_IIO_SW_DEVICE=y
+CONFIG_PWM=y
+CONFIG_PWM_LIGHT=y
+CONFIG_NVMEM_THEAD_LIGHT_EFUSE=y
+CONFIG_TEE=y
+CONFIG_OPTEE=y
+CONFIG_OPTEE_BENCHMARK=y
+CONFIG_LIGHT_GPU_VIV=m
+# CONFIG_LIGHT_NET is not set
+CONFIG_EXT4_FS=y
+CONFIG_EXT4_FS_POSIX_ACL=y
+CONFIG_AUTOFS4_FS=y
+CONFIG_FUSE_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_TMPFS=y
+CONFIG_TMPFS_POSIX_ACL=y
+CONFIG_HUGETLBFS=y
+CONFIG_JFFS2_FS=y
+CONFIG_UBIFS_FS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V4=y
+CONFIG_NFS_V4_1=y
+CONFIG_NFS_V4_2=y
+CONFIG_ROOT_NFS=y
+CONFIG_9P_FS=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_CRYPTO_AUTHENC=y
+CONFIG_CRYPTO_DH=y
+CONFIG_CRYPTO_CURVE25519=y
+CONFIG_CRYPTO_CHACHA20POLY1305=y
+CONFIG_CRYPTO_OFB=y
+CONFIG_CRYPTO_MD5=y
+CONFIG_CRYPTO_SHA512=y
+CONFIG_CRYPTO_SHA3=y
+CONFIG_CRYPTO_SM3=y
+CONFIG_CRYPTO_DES=y
+CONFIG_CRYPTO_USER_API_HASH=y
+CONFIG_DMA_CMA=y
+CONFIG_DMA_PERNUMA_CMA=y
+CONFIG_CMA_SIZE_MBYTES=32
+CONFIG_PRINTK_TIME=y
+CONFIG_DYNAMIC_DEBUG=y
+CONFIG_DEBUG_INFO=y
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_DEBUG_FS=y
+CONFIG_DETECT_HUNG_TASK=y
+CONFIG_DEBUG_ATOMIC_SLEEP=y
+# CONFIG_RCU_TRACE is not set
+CONFIG_OVERLAY_FS=y
+CONFIG_LOCKUP_DETECTOR=y
+CONFIG_SOFTLOCKUP_DETECTOR=y
+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
+# CONFIG_SUSPEND is not set
+# CONFIG_PM_SLEEP is not set

arch/riscv/configs/ice_defconfig

@@ -180,6 +180,5 @@ CONFIG_DEBUG_INFO=y
 CONFIG_MAGIC_SYSRQ=y
 CONFIG_DEBUG_FS=y
 CONFIG_DETECT_HUNG_TASK=y
-CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=60
 CONFIG_DEBUG_ATOMIC_SLEEP=y
 # CONFIG_RCU_TRACE is not set

arch/riscv/configs/light-android_defconfig

@@ -561,7 +561,6 @@ CONFIG_DYNAMIC_DEBUG=y
 CONFIG_DEBUG_FS=y
 CONFIG_PANIC_TIMEOUT=5
 CONFIG_DETECT_HUNG_TASK=y
-CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=60
 CONFIG_SCHEDSTATS=y
 CONFIG_DEBUG_ATOMIC_SLEEP=y
 # CONFIG_GCC_PLUGINS is not set

arch/riscv/configs/light_defconfig

@@ -3,6 +3,10 @@ CONFIG_POSIX_MQUEUE=y
 CONFIG_NO_HZ_IDLE=y
 CONFIG_HIGH_RES_TIMERS=y
 CONFIG_PREEMPT=y
+CONFIG_TASKSTATS=y
+CONFIG_TASK_DELAY_ACCT=y
+CONFIG_TASK_XACCT=y
+CONFIG_TASK_IO_ACCOUNTING=y
 CONFIG_IKCONFIG=y
 CONFIG_IKCONFIG_PROC=y
 CONFIG_CGROUPS=y
@@ -91,6 +95,7 @@ CONFIG_TUN=y
 CONFIG_VIRTIO_NET=y
 CONFIG_MACB=y
 CONFIG_STMMAC_ETH=y
+CONFIG_STMMAC_RX_ZERO_COPY=y
 CONFIG_DWMAC_LIGHT=y
 CONFIG_MICROSEMI_PHY=y
 CONFIG_REALTEK_PHY=y
@@ -105,6 +110,7 @@ CONFIG_KEYBOARD_GPIO=y
 # CONFIG_INPUT_MOUSE is not set
 CONFIG_INPUT_TOUCHSCREEN=y
 CONFIG_TOUCHSCREEN_GOODIX=y
+CONFIG_TOUCHSCREEN_GT9XX=y
 CONFIG_INPUT_MISC=y
 CONFIG_INPUT_UINPUT=y
 CONFIG_SERIAL_8250=y
@@ -197,6 +203,10 @@ CONFIG_V4L_MEM2MEM_DRIVERS=y
 CONFIG_DRM=y
 CONFIG_DRM_PANEL_SIMPLE=y
 CONFIG_DRM_PANEL_ILITEK_ILI9881C=y
+CONFIG_DRM_PANEL_ILI9881D=y
+CONFIG_DRM_PANEL_HX8394=y
+CONFIG_DRM_PANEL_JADARD_JD9365DA_H3=y
+CONFIG_DRM_PANEL_HX8279=y
 CONFIG_DRM_VERISILICON=y
 CONFIG_BACKLIGHT_CLASS_DEVICE=y
 CONFIG_BACKLIGHT_PWM=y
@@ -263,6 +273,11 @@ CONFIG_HWSPINLOCK=y
 CONFIG_HWSPINLOCK_LIGHT=y
 CONFIG_HWSPINLOCK_LIGHT_TEST=m
 CONFIG_MAILBOX=y
+CONFIG_RPMSG=y
+CONFIG_RPMSG_CHAR=y
+CONFIG_RPMSG_VIRTIO=y
+CONFIG_RPMSG_THEAD_LIGHT=y
+CONFIG_EXTCON=y
 CONFIG_IIO=y
 CONFIG_IIO_SW_DEVICE=y
 CONFIG_PWM=y
@@ -296,13 +311,21 @@ CONFIG_CRYPTO_AUTHENC=y
 CONFIG_CRYPTO_DH=y
 CONFIG_CRYPTO_CURVE25519=y
 CONFIG_CRYPTO_CHACHA20POLY1305=y
+CONFIG_CRYPTO_CBC=y
+CONFIG_CRYPTO_CTR=y
 CONFIG_CRYPTO_OFB=y
 CONFIG_CRYPTO_MD5=y
 CONFIG_CRYPTO_SHA512=y
 CONFIG_CRYPTO_SHA3=y
 CONFIG_CRYPTO_SM3=y
 CONFIG_CRYPTO_DES=y
+CONFIG_CRYPTO_SM4=y
+CONFIG_CRYPTO_USER=y
 CONFIG_CRYPTO_USER_API_HASH=y
+CONFIG_CRYPTO_USER_API_SKCIPHER=y
+CONFIG_CRYPTO_USER_API_RNG=y
+# CONFIG_CRYPTO_USER_API_RNG_CAVP is not set
+CONFIG_CRYPTO_USER_API_AEAD=y
 CONFIG_DMA_CMA=y
 CONFIG_DMA_PERNUMA_CMA=y
 CONFIG_CMA_SIZE_MBYTES=32
@@ -312,13 +335,21 @@ CONFIG_DEBUG_INFO=y
 CONFIG_MAGIC_SYSRQ=y
 CONFIG_DEBUG_FS=y
 CONFIG_DETECT_HUNG_TASK=y
-CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=60
 CONFIG_DEBUG_ATOMIC_SLEEP=y
 # CONFIG_RCU_TRACE is not set
 CONFIG_OVERLAY_FS=y
 CONFIG_LOCKUP_DETECTOR=y
 CONFIG_SOFTLOCKUP_DETECTOR=y
 CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
+CONFIG_SCHED_INFO=y
 CONFIG_PM=y
 # CONFIG_SUSPEND is not set
 # CONFIG_PM_SLEEP is not set
+CONFIG_PM_DEVFREQ=y
+CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y
+CONFIG_DEVFREQ_GOV_PERFORMANCE=y
+CONFIG_DEVFREQ_GOV_POWERSAVE=y
+CONFIG_DEVFREQ_GOV_USERSPACE=y
+CONFIG_DEVFREQ_GOV_PASSIVE=y
+CONFIG_PM_DEVFREQ_EVENT=y
+

arch/riscv/configs/light_emu_defconfig

@@ -189,7 +189,6 @@ CONFIG_DYNAMIC_DEBUG=y
 CONFIG_DEBUG_INFO=y
 CONFIG_DEBUG_FS=y
 CONFIG_DETECT_HUNG_TASK=y
-CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=60
 CONFIG_DEBUG_ATOMIC_SLEEP=y
 # CONFIG_RCU_TRACE is not set
 CONFIG_FORCE_MAX_ZONEORDER=15

arch/riscv/configs/rv32_defconfig

@@ -18,6 +18,11 @@ CONFIG_SOC_SIFIVE=y
 CONFIG_SOC_VIRT=y
 CONFIG_ARCH_RV32I=y
 CONFIG_SMP=y
+CONFIG_HOTPLUG_CPU=y
+CONFIG_PM=y
+CONFIG_CPU_IDLE=y
+CONFIG_VIRTUALIZATION=y
+CONFIG_KVM=m
 CONFIG_JUMP_LABEL=y
 CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y

arch/riscv/configs/vector_0_7_defconfig

@@ -184,6 +184,5 @@ CONFIG_DEBUG_INFO=y
 CONFIG_MAGIC_SYSRQ=y
 CONFIG_DEBUG_FS=y
 CONFIG_DETECT_HUNG_TASK=y
-CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=60
 CONFIG_DEBUG_ATOMIC_SLEEP=y
 # CONFIG_RCU_TRACE is not set

arch/riscv/include/asm/Kbuild

@@ -3,5 +3,8 @@ generic-y += early_ioremap.h
 generic-y += extable.h
 generic-y += flat.h
 generic-y += kvm_para.h
+generic-y += mcs_spinlock.h
+generic-y += qspinlock.h
+generic-y += qrwlock.h
 generic-y += user.h
 generic-y += vmlinux.lds.h

arch/riscv/include/asm/asm.h

@@ -66,4 +66,31 @@
 #error "Unexpected __SIZEOF_SHORT__"
 #endif
 
+#ifdef __ASSEMBLY__
+
+/* Common assembly source macros */
+
+#ifdef CONFIG_XIP_KERNEL
+.macro XIP_FIXUP_OFFSET reg
+	REG_L t0, _xip_fixup
+	add \reg, \reg, t0
+.endm
+.macro XIP_FIXUP_FLASH_OFFSET reg
+	la t1, __data_loc
+	li t0, XIP_OFFSET_MASK
+	and t1, t1, t0
+	li t1, XIP_OFFSET
+	sub t0, t0, t1
+	sub \reg, \reg, t0
+.endm
+_xip_fixup: .dword CONFIG_PHYS_RAM_BASE - CONFIG_XIP_PHYS_ADDR - XIP_OFFSET
+#else
+.macro XIP_FIXUP_OFFSET reg
+.endm
+.macro XIP_FIXUP_FLASH_OFFSET reg
+.endm
+#endif /* CONFIG_XIP_KERNEL */
+
+#endif /* __ASSEMBLY__ */
+
 #endif /* _ASM_RISCV_ASM_H */

arch/riscv/include/asm/cmpxchg.h

@@ -11,12 +11,36 @@
 #include <asm/barrier.h>
 #include <asm/fence.h>
 
+static inline ulong __xchg16_relaxed(ulong new, void *ptr)
+{
+       ulong ret, tmp;
+       ulong shif = ((ulong)ptr & 2) ? 16 : 0;
+       ulong mask = 0xffff << shif;
+       ulong *__ptr = (ulong *)((ulong)ptr & ~2);
+
+       __asm__ __volatile__ (
+               "0:     lr.w %0, %2\n"
+               "       and  %1, %0, %z3\n"
+               "       or   %1, %1, %z4\n"
+               "       sc.w %1, %1, %2\n"
+               "       bnez %1, 0b\n"
+               : "=&r" (ret), "=&r" (tmp), "+A" (*__ptr)
+               : "rJ" (~mask), "rJ" (new << shif)
+               : "memory");
+
+       return (ulong)((ret & mask) >> shif);
+}
+
 #define __xchg_relaxed(ptr, new, size)					\
 ({									\
 	__typeof__(ptr) __ptr = (ptr);					\
 	__typeof__(new) __new = (new);					\
 	__typeof__(*(ptr)) __ret;					\
 	switch (size) {							\
+        case 2: {                                                       \
+                __ret = (__typeof__(*(ptr)))                            \
+                         __xchg16_relaxed((ulong)__new, __ptr);         \
+                break;}                                                 \
 	case 4:								\
 		__asm__ __volatile__ (					\
 			"	amoswap.w %0, %2, %1\n"			\

arch/riscv/include/asm/cpu_ops_sbi.h

@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2021 by Rivos Inc.
+ */
+#ifndef __ASM_CPU_OPS_SBI_H
+#define __ASM_CPU_OPS_SBI_H
+
+#ifndef __ASSEMBLY__
+#include <linux/init.h>
+#include <linux/sched.h>
+#include <linux/threads.h>
+
+/**
+ * struct sbi_hart_boot_data - Hart specific boot used during booting and
+ *			       cpu hotplug.
+ * @task_ptr: A pointer to the hart specific tp
+ * @stack_ptr: A pointer to the hart specific sp
+ */
+struct sbi_hart_boot_data {
+	void *task_ptr;
+	void *stack_ptr;
+};
+#endif
+
+#endif /* ifndef __ASM_CPU_OPS_SBI_H */

arch/riscv/include/asm/csr.h

@@ -143,11 +143,6 @@
 #define CSR_VTYPE		0xc21
 #define CSR_VLENB		0xc22
 
-#define CSR_SMIR		0x9c0
-#define CSR_SMEL		0x9c1
-#define CSR_SMEH		0x9c2
-#define CSR_SMCIR		0x9c3
-
 #ifdef CONFIG_RISCV_M_MODE
 # define CSR_STATUS	CSR_MSTATUS
 # define CSR_IE		CSR_MIE

arch/riscv/include/asm/io.h

@@ -13,7 +13,6 @@
 
 #include <linux/types.h>
 #include <linux/pgtable.h>
-#include <asm/mmiowb.h>
 #include <asm/early_ioremap.h>
 
 /*

arch/riscv/include/asm/mmio.h

@@ -133,7 +133,7 @@ static inline u64 __raw_readq(const volatile void __iomem *addr)
 #define __io_br()	do {} while (0)
 #define __io_ar(v)	__asm__ __volatile__ ("fence i,r" : : : "memory")
 #define __io_bw()	__asm__ __volatile__ ("fence w,o" : : : "memory")
-#define __io_aw()	mmiowb_set_pending()
+#define __io_aw()	__asm__ __volatile__ ("fence o,w" : : : "memory")
 
 #define readb(c)	({ u8  __v; __io_br(); __v = readb_cpu(c); __io_ar(__v); __v; })
 #define readw(c)	({ u16 __v; __io_br(); __v = readw_cpu(c); __io_ar(__v); __v; })

arch/riscv/include/asm/mmiowb.h

@@ -1,15 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-
-#ifndef _ASM_RISCV_MMIOWB_H
-#define _ASM_RISCV_MMIOWB_H
-
-/*
- * "o,w" is sufficient to ensure that all writes to the device have completed
- * before the write to the spinlock is allowed to commit.
- */
-#define mmiowb()	__asm__ __volatile__ ("fence o,w" : : : "memory");
-
-#include <linux/smp.h>
-#include <asm-generic/mmiowb.h>
-
-#endif	/* _ASM_RISCV_MMIOWB_H */

arch/riscv/include/asm/pgtable.h

@@ -446,7 +446,7 @@ static inline pgprot_t pgprot_writecombine(pgprot_t _prot)
 
 	return __pgprot(prot);
 }
-
+#define pgprot_dmacoherent   pgprot_writecombine
 /*
  * Encode and decode a swap entry
  *

arch/riscv/include/asm/sbi.h

@@ -61,13 +61,45 @@ enum sbi_ext_hsm_fid {
 	SBI_EXT_HSM_HART_START = 0,
 	SBI_EXT_HSM_HART_STOP,
 	SBI_EXT_HSM_HART_STATUS,
+	SBI_EXT_HSM_HART_SUSPEND,
 };
 
-enum sbi_hsm_hart_status {
+enum sbi_hsm_hart_state {
-	SBI_HSM_HART_STATUS_STARTED = 0,
+	SBI_HSM_STATE_STARTED = 0,
-	SBI_HSM_HART_STATUS_STOPPED,
+	SBI_HSM_STATE_STOPPED,
-	SBI_HSM_HART_STATUS_START_PENDING,
+	SBI_HSM_STATE_START_PENDING,
-	SBI_HSM_HART_STATUS_STOP_PENDING,
+	SBI_HSM_STATE_STOP_PENDING,
+	SBI_HSM_STATE_SUSPENDED,
+	SBI_HSM_STATE_SUSPEND_PENDING,
+	SBI_HSM_STATE_RESUME_PENDING,
+};
+
+#define SBI_HSM_SUSP_BASE_MASK			0x7fffffff
+#define SBI_HSM_SUSP_NON_RET_BIT		0x80000000
+#define SBI_HSM_SUSP_PLAT_BASE			0x10000000
+
+#define SBI_HSM_SUSPEND_RET_DEFAULT		0x00000000
+#define SBI_HSM_SUSPEND_RET_PLATFORM		SBI_HSM_SUSP_PLAT_BASE
+#define SBI_HSM_SUSPEND_RET_LAST		SBI_HSM_SUSP_BASE_MASK
+#define SBI_HSM_SUSPEND_NON_RET_DEFAULT		SBI_HSM_SUSP_NON_RET_BIT
+#define SBI_HSM_SUSPEND_NON_RET_PLATFORM	(SBI_HSM_SUSP_NON_RET_BIT | \
+						 SBI_HSM_SUSP_PLAT_BASE)
+#define SBI_HSM_SUSPEND_NON_RET_LAST		(SBI_HSM_SUSP_NON_RET_BIT | \
+						 SBI_HSM_SUSP_BASE_MASK)
+
+enum sbi_ext_srst_fid {
+	SBI_EXT_SRST_RESET = 0,
+};
+
+enum sbi_srst_reset_type {
+	SBI_SRST_RESET_TYPE_SHUTDOWN = 0,
+	SBI_SRST_RESET_TYPE_COLD_REBOOT,
+	SBI_SRST_RESET_TYPE_WARM_REBOOT,
+};
+
+enum sbi_srst_reset_reason {
+	SBI_SRST_RESET_REASON_NONE = 0,
+	SBI_SRST_RESET_REASON_SYS_FAILURE,
 };
 
 #define SBI_SPEC_VERSION_DEFAULT	0x1

arch/riscv/include/asm/spinlock.h

@@ -1,135 +1,9 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
+/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (C) 2015 Regents of the University of California
- * Copyright (C) 2017 SiFive
- */
 
-#ifndef _ASM_RISCV_SPINLOCK_H
+#ifndef __ASM_GENERIC_SPINLOCK_H
-#define _ASM_RISCV_SPINLOCK_H
+#define __ASM_GENERIC_SPINLOCK_H
 
-#include <linux/kernel.h>
+#include <asm-generic/qspinlock.h>
-#include <asm/current.h>
+#include <asm/qrwlock.h>
-#include <asm/fence.h>
 
-/*
+#endif /* __ASM_GENERIC_SPINLOCK_H */
- * Simple spin lock operations.  These provide no fairness guarantees.
- */
-
-/* FIXME: Replace this with a ticket lock, like MIPS. */
-
-#define arch_spin_is_locked(x)	(READ_ONCE((x)->lock) != 0)
-
-static inline void arch_spin_unlock(arch_spinlock_t *lock)
-{
-	smp_store_release(&lock->lock, 0);
-}
-
-static inline int arch_spin_trylock(arch_spinlock_t *lock)
-{
-	int tmp = 1, busy;
-
-	__asm__ __volatile__ (
-		"	amoswap.w %0, %2, %1\n"
-		RISCV_ACQUIRE_BARRIER
-		: "=r" (busy), "+A" (lock->lock)
-		: "r" (tmp)
-		: "memory");
-
-	return !busy;
-}
-
-static inline void arch_spin_lock(arch_spinlock_t *lock)
-{
-	while (1) {
-		if (arch_spin_is_locked(lock))
-			continue;
-
-		if (arch_spin_trylock(lock))
-			break;
-	}
-}
-
-/***********************************************************/
-
-static inline void arch_read_lock(arch_rwlock_t *lock)
-{
-	int tmp;
-
-	__asm__ __volatile__(
-		"1:	lr.w	%1, %0\n"
-		"	bltz	%1, 1b\n"
-		"	addi	%1, %1, 1\n"
-		"	sc.w	%1, %1, %0\n"
-		"	bnez	%1, 1b\n"
-		RISCV_ACQUIRE_BARRIER
-		: "+A" (lock->lock), "=&r" (tmp)
-		:: "memory");
-}
-
-static inline void arch_write_lock(arch_rwlock_t *lock)
-{
-	int tmp;
-
-	__asm__ __volatile__(
-		"1:	lr.w	%1, %0\n"
-		"	bnez	%1, 1b\n"
-		"	li	%1, -1\n"
-		"	sc.w	%1, %1, %0\n"
-		"	bnez	%1, 1b\n"
-		RISCV_ACQUIRE_BARRIER
-		: "+A" (lock->lock), "=&r" (tmp)
-		:: "memory");
-}
-
-static inline int arch_read_trylock(arch_rwlock_t *lock)
-{
-	int busy;
-
-	__asm__ __volatile__(
-		"1:	lr.w	%1, %0\n"
-		"	bltz	%1, 1f\n"
-		"	addi	%1, %1, 1\n"
-		"	sc.w	%1, %1, %0\n"
-		"	bnez	%1, 1b\n"
-		RISCV_ACQUIRE_BARRIER
-		"1:\n"
-		: "+A" (lock->lock), "=&r" (busy)
-		:: "memory");
-
-	return !busy;
-}
-
-static inline int arch_write_trylock(arch_rwlock_t *lock)
-{
-	int busy;
-
-	__asm__ __volatile__(
-		"1:	lr.w	%1, %0\n"
-		"	bnez	%1, 1f\n"
-		"	li	%1, -1\n"
-		"	sc.w	%1, %1, %0\n"
-		"	bnez	%1, 1b\n"
-		RISCV_ACQUIRE_BARRIER
-		"1:\n"
-		: "+A" (lock->lock), "=&r" (busy)
-		:: "memory");
-
-	return !busy;
-}
-
-static inline void arch_read_unlock(arch_rwlock_t *lock)
-{
-	__asm__ __volatile__(
-		RISCV_RELEASE_BARRIER
-		"	amoadd.w x0, %1, %0\n"
-		: "+A" (lock->lock)
-		: "r" (-1)
-		: "memory");
-}
-
-static inline void arch_write_unlock(arch_rwlock_t *lock)
-{
-	smp_store_release(&lock->lock, 0);
-}
-
-#endif /* _ASM_RISCV_SPINLOCK_H */

arch/riscv/include/asm/spinlock_types.h

@@ -1,25 +1,9 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
+/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (C) 2015 Regents of the University of California
- */
 
-#ifndef _ASM_RISCV_SPINLOCK_TYPES_H
+#ifndef __ASM_GENERIC_SPINLOCK_TYPES_H
-#define _ASM_RISCV_SPINLOCK_TYPES_H
+#define __ASM_GENERIC_SPINLOCK_TYPES_H
 
-#ifndef __LINUX_SPINLOCK_TYPES_H
+#include <asm-generic/qspinlock_types.h>
-# error "please don't include this file directly"
+#include <asm-generic/qrwlock_types.h>
-#endif
 
-typedef struct {
+#endif /* __ASM_GENERIC_SPINLOCK_TYPES_H */
-	volatile unsigned int lock;
-} arch_spinlock_t;
-
-#define __ARCH_SPIN_LOCK_UNLOCKED	{ 0 }
-
-typedef struct {
-	volatile unsigned int lock;
-} arch_rwlock_t;
-
-#define __ARCH_RW_LOCK_UNLOCKED		{ 0 }
-
-#endif /* _ASM_RISCV_SPINLOCK_TYPES_H */

arch/riscv/include/asm/suspend.h

@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2021 Western Digital Corporation or its affiliates.
+ * Copyright (c) 2022 Ventana Micro Systems Inc.
+ */
+
+#ifndef _ASM_RISCV_SUSPEND_H
+#define _ASM_RISCV_SUSPEND_H
+
+#include <asm/ptrace.h>
+
+struct suspend_context {
+	/* Saved and restored by low-level functions */
+	struct pt_regs regs;
+	/* Saved and restored by high-level functions */
+	unsigned long scratch;
+	unsigned long tvec;
+	unsigned long ie;
+#ifdef CONFIG_MMU
+	unsigned long satp;
+#endif
+};
+
+/* Low-level CPU suspend entry function */
+int __cpu_suspend_enter(struct suspend_context *context);
+
+/* High-level CPU suspend which will save context and call finish() */
+int cpu_suspend(unsigned long arg,
+		int (*finish)(unsigned long arg,
+			      unsigned long entry,
+			      unsigned long context));
+
+/* Low-level CPU resume entry function */
+int __cpu_resume_enter(unsigned long hartid, unsigned long context);
+
+#endif

arch/riscv/include/asm/tlbflush.h

@@ -14,7 +14,7 @@
 static inline void local_flush_tlb_all(void)
 {
 #ifdef CONFIG_NO_SFENCE_VMA
-	csr_write(CSR_SMCIR, 1 << 26);
+	csr_write(0x9c3, 1 << 26);
 #else
 	__asm__ __volatile__ ("sfence.vma" : : : "memory");
 #endif
@@ -24,7 +24,7 @@ static inline void local_flush_tlb_all(void)
 static inline void local_flush_tlb_page(unsigned long addr)
 {
 #ifdef CONFIG_NO_SFENCE_VMA
-	csr_write(CSR_SMCIR, 1 << 26);
+	csr_write(0x9c3, 1 << 26);
 #else
 	__asm__ __volatile__ ("sfence.vma %0" : : "r" (addr) : "memory");
 #endif
@@ -58,23 +58,7 @@ static inline void flush_tlb_range(struct vm_area_struct *vma,
 static inline void flush_tlb_kernel_range(unsigned long start,
 	unsigned long end)
 {
-#ifdef CONFIG_NO_SFENCE_VMA
-	csr_write(CSR_SMCIR, 1 << 26);
-#else
-	start &= PAGE_MASK;
-	end   += PAGE_SIZE - 1;
-	end   &= PAGE_MASK;
-
-	if ((end - start) > SZ_1M) {
 	flush_tlb_all();
-		return;
-	}
-
-	while (start < end) {
-		__asm__ __volatile__ ("sfence.vma %0" : : "r" (start) : "memory");
-		start += PAGE_SIZE;
-	}
-#endif
 }
 
 #endif /* _ASM_RISCV_TLBFLUSH_H */

arch/riscv/kernel/Makefile

@@ -48,6 +48,8 @@ obj-$(CONFIG_SMP)		+= cpu_ops_spinwait.o
 obj-$(CONFIG_MODULES)		+= module.o
 obj-$(CONFIG_MODULE_SECTIONS)	+= module-sections.o
 
+obj-$(CONFIG_CPU_PM)		+= suspend_entry.o suspend.o
+
 obj-$(CONFIG_FUNCTION_TRACER)	+= mcount.o ftrace.o
 obj-$(CONFIG_DYNAMIC_FTRACE)	+= mcount-dyn.o
 

arch/riscv/kernel/asm-offsets.c

@@ -10,6 +10,10 @@
 #include <linux/sched.h>
 #include <asm/thread_info.h>
 #include <asm/ptrace.h>
+#include <asm/cpu_ops_sbi.h>
+#include <asm/suspend.h>
+
+void asm_offsets(void);
 
 void asm_offsets(void)
 {
@@ -149,6 +153,162 @@ void asm_offsets(void)
 	OFFSET(PT_BADADDR, pt_regs, badaddr);
 	OFFSET(PT_CAUSE, pt_regs, cause);
 
+	OFFSET(SUSPEND_CONTEXT_REGS, suspend_context, regs);
+#if 0
+	OFFSET(KVM_ARCH_GUEST_ZERO, kvm_vcpu_arch, guest_context.zero);
+	OFFSET(KVM_ARCH_GUEST_RA, kvm_vcpu_arch, guest_context.ra);
+	OFFSET(KVM_ARCH_GUEST_SP, kvm_vcpu_arch, guest_context.sp);
+	OFFSET(KVM_ARCH_GUEST_GP, kvm_vcpu_arch, guest_context.gp);
+	OFFSET(KVM_ARCH_GUEST_TP, kvm_vcpu_arch, guest_context.tp);
+	OFFSET(KVM_ARCH_GUEST_T0, kvm_vcpu_arch, guest_context.t0);
+	OFFSET(KVM_ARCH_GUEST_T1, kvm_vcpu_arch, guest_context.t1);
+	OFFSET(KVM_ARCH_GUEST_T2, kvm_vcpu_arch, guest_context.t2);
+	OFFSET(KVM_ARCH_GUEST_S0, kvm_vcpu_arch, guest_context.s0);
+	OFFSET(KVM_ARCH_GUEST_S1, kvm_vcpu_arch, guest_context.s1);
+	OFFSET(KVM_ARCH_GUEST_A0, kvm_vcpu_arch, guest_context.a0);
+	OFFSET(KVM_ARCH_GUEST_A1, kvm_vcpu_arch, guest_context.a1);
+	OFFSET(KVM_ARCH_GUEST_A2, kvm_vcpu_arch, guest_context.a2);
+	OFFSET(KVM_ARCH_GUEST_A3, kvm_vcpu_arch, guest_context.a3);
+	OFFSET(KVM_ARCH_GUEST_A4, kvm_vcpu_arch, guest_context.a4);
+	OFFSET(KVM_ARCH_GUEST_A5, kvm_vcpu_arch, guest_context.a5);
+	OFFSET(KVM_ARCH_GUEST_A6, kvm_vcpu_arch, guest_context.a6);
+	OFFSET(KVM_ARCH_GUEST_A7, kvm_vcpu_arch, guest_context.a7);
+	OFFSET(KVM_ARCH_GUEST_S2, kvm_vcpu_arch, guest_context.s2);
+	OFFSET(KVM_ARCH_GUEST_S3, kvm_vcpu_arch, guest_context.s3);
+	OFFSET(KVM_ARCH_GUEST_S4, kvm_vcpu_arch, guest_context.s4);
+	OFFSET(KVM_ARCH_GUEST_S5, kvm_vcpu_arch, guest_context.s5);
+	OFFSET(KVM_ARCH_GUEST_S6, kvm_vcpu_arch, guest_context.s6);
+	OFFSET(KVM_ARCH_GUEST_S7, kvm_vcpu_arch, guest_context.s7);
+	OFFSET(KVM_ARCH_GUEST_S8, kvm_vcpu_arch, guest_context.s8);
+	OFFSET(KVM_ARCH_GUEST_S9, kvm_vcpu_arch, guest_context.s9);
+	OFFSET(KVM_ARCH_GUEST_S10, kvm_vcpu_arch, guest_context.s10);
+	OFFSET(KVM_ARCH_GUEST_S11, kvm_vcpu_arch, guest_context.s11);
+	OFFSET(KVM_ARCH_GUEST_T3, kvm_vcpu_arch, guest_context.t3);
+	OFFSET(KVM_ARCH_GUEST_T4, kvm_vcpu_arch, guest_context.t4);
+	OFFSET(KVM_ARCH_GUEST_T5, kvm_vcpu_arch, guest_context.t5);
+	OFFSET(KVM_ARCH_GUEST_T6, kvm_vcpu_arch, guest_context.t6);
+	OFFSET(KVM_ARCH_GUEST_SEPC, kvm_vcpu_arch, guest_context.sepc);
+	OFFSET(KVM_ARCH_GUEST_SSTATUS, kvm_vcpu_arch, guest_context.sstatus);
+	OFFSET(KVM_ARCH_GUEST_HSTATUS, kvm_vcpu_arch, guest_context.hstatus);
+	OFFSET(KVM_ARCH_GUEST_SCOUNTEREN, kvm_vcpu_arch, guest_csr.scounteren);
+
+	OFFSET(KVM_ARCH_HOST_ZERO, kvm_vcpu_arch, host_context.zero);
+	OFFSET(KVM_ARCH_HOST_RA, kvm_vcpu_arch, host_context.ra);
+	OFFSET(KVM_ARCH_HOST_SP, kvm_vcpu_arch, host_context.sp);
+	OFFSET(KVM_ARCH_HOST_GP, kvm_vcpu_arch, host_context.gp);
+	OFFSET(KVM_ARCH_HOST_TP, kvm_vcpu_arch, host_context.tp);
+	OFFSET(KVM_ARCH_HOST_T0, kvm_vcpu_arch, host_context.t0);
+	OFFSET(KVM_ARCH_HOST_T1, kvm_vcpu_arch, host_context.t1);
+	OFFSET(KVM_ARCH_HOST_T2, kvm_vcpu_arch, host_context.t2);
+	OFFSET(KVM_ARCH_HOST_S0, kvm_vcpu_arch, host_context.s0);
+	OFFSET(KVM_ARCH_HOST_S1, kvm_vcpu_arch, host_context.s1);
+	OFFSET(KVM_ARCH_HOST_A0, kvm_vcpu_arch, host_context.a0);
+	OFFSET(KVM_ARCH_HOST_A1, kvm_vcpu_arch, host_context.a1);
+	OFFSET(KVM_ARCH_HOST_A2, kvm_vcpu_arch, host_context.a2);
+	OFFSET(KVM_ARCH_HOST_A3, kvm_vcpu_arch, host_context.a3);
+	OFFSET(KVM_ARCH_HOST_A4, kvm_vcpu_arch, host_context.a4);
+	OFFSET(KVM_ARCH_HOST_A5, kvm_vcpu_arch, host_context.a5);
+	OFFSET(KVM_ARCH_HOST_A6, kvm_vcpu_arch, host_context.a6);
+	OFFSET(KVM_ARCH_HOST_A7, kvm_vcpu_arch, host_context.a7);
+	OFFSET(KVM_ARCH_HOST_S2, kvm_vcpu_arch, host_context.s2);
+	OFFSET(KVM_ARCH_HOST_S3, kvm_vcpu_arch, host_context.s3);
+	OFFSET(KVM_ARCH_HOST_S4, kvm_vcpu_arch, host_context.s4);
+	OFFSET(KVM_ARCH_HOST_S5, kvm_vcpu_arch, host_context.s5);
+	OFFSET(KVM_ARCH_HOST_S6, kvm_vcpu_arch, host_context.s6);
+	OFFSET(KVM_ARCH_HOST_S7, kvm_vcpu_arch, host_context.s7);
+	OFFSET(KVM_ARCH_HOST_S8, kvm_vcpu_arch, host_context.s8);
+	OFFSET(KVM_ARCH_HOST_S9, kvm_vcpu_arch, host_context.s9);
+	OFFSET(KVM_ARCH_HOST_S10, kvm_vcpu_arch, host_context.s10);
+	OFFSET(KVM_ARCH_HOST_S11, kvm_vcpu_arch, host_context.s11);
+	OFFSET(KVM_ARCH_HOST_T3, kvm_vcpu_arch, host_context.t3);
+	OFFSET(KVM_ARCH_HOST_T4, kvm_vcpu_arch, host_context.t4);
+	OFFSET(KVM_ARCH_HOST_T5, kvm_vcpu_arch, host_context.t5);
+	OFFSET(KVM_ARCH_HOST_T6, kvm_vcpu_arch, host_context.t6);
+	OFFSET(KVM_ARCH_HOST_SEPC, kvm_vcpu_arch, host_context.sepc);
+	OFFSET(KVM_ARCH_HOST_SSTATUS, kvm_vcpu_arch, host_context.sstatus);
+	OFFSET(KVM_ARCH_HOST_HSTATUS, kvm_vcpu_arch, host_context.hstatus);
+	OFFSET(KVM_ARCH_HOST_SSCRATCH, kvm_vcpu_arch, host_sscratch);
+	OFFSET(KVM_ARCH_HOST_STVEC, kvm_vcpu_arch, host_stvec);
+	OFFSET(KVM_ARCH_HOST_SCOUNTEREN, kvm_vcpu_arch, host_scounteren);
+
+	OFFSET(KVM_ARCH_TRAP_SEPC, kvm_cpu_trap, sepc);
+	OFFSET(KVM_ARCH_TRAP_SCAUSE, kvm_cpu_trap, scause);
+	OFFSET(KVM_ARCH_TRAP_STVAL, kvm_cpu_trap, stval);
+	OFFSET(KVM_ARCH_TRAP_HTVAL, kvm_cpu_trap, htval);
+	OFFSET(KVM_ARCH_TRAP_HTINST, kvm_cpu_trap, htinst);
+
+	/* F extension */
+
+	OFFSET(KVM_ARCH_FP_F_F0, kvm_cpu_context, fp.f.f[0]);
+	OFFSET(KVM_ARCH_FP_F_F1, kvm_cpu_context, fp.f.f[1]);
+	OFFSET(KVM_ARCH_FP_F_F2, kvm_cpu_context, fp.f.f[2]);
+	OFFSET(KVM_ARCH_FP_F_F3, kvm_cpu_context, fp.f.f[3]);
+	OFFSET(KVM_ARCH_FP_F_F4, kvm_cpu_context, fp.f.f[4]);
+	OFFSET(KVM_ARCH_FP_F_F5, kvm_cpu_context, fp.f.f[5]);
+	OFFSET(KVM_ARCH_FP_F_F6, kvm_cpu_context, fp.f.f[6]);
+	OFFSET(KVM_ARCH_FP_F_F7, kvm_cpu_context, fp.f.f[7]);
+	OFFSET(KVM_ARCH_FP_F_F8, kvm_cpu_context, fp.f.f[8]);
+	OFFSET(KVM_ARCH_FP_F_F9, kvm_cpu_context, fp.f.f[9]);
+	OFFSET(KVM_ARCH_FP_F_F10, kvm_cpu_context, fp.f.f[10]);
+	OFFSET(KVM_ARCH_FP_F_F11, kvm_cpu_context, fp.f.f[11]);
+	OFFSET(KVM_ARCH_FP_F_F12, kvm_cpu_context, fp.f.f[12]);
+	OFFSET(KVM_ARCH_FP_F_F13, kvm_cpu_context, fp.f.f[13]);
+	OFFSET(KVM_ARCH_FP_F_F14, kvm_cpu_context, fp.f.f[14]);
+	OFFSET(KVM_ARCH_FP_F_F15, kvm_cpu_context, fp.f.f[15]);
+	OFFSET(KVM_ARCH_FP_F_F16, kvm_cpu_context, fp.f.f[16]);
+	OFFSET(KVM_ARCH_FP_F_F17, kvm_cpu_context, fp.f.f[17]);
+	OFFSET(KVM_ARCH_FP_F_F18, kvm_cpu_context, fp.f.f[18]);
+	OFFSET(KVM_ARCH_FP_F_F19, kvm_cpu_context, fp.f.f[19]);
+	OFFSET(KVM_ARCH_FP_F_F20, kvm_cpu_context, fp.f.f[20]);
+	OFFSET(KVM_ARCH_FP_F_F21, kvm_cpu_context, fp.f.f[21]);
+	OFFSET(KVM_ARCH_FP_F_F22, kvm_cpu_context, fp.f.f[22]);
+	OFFSET(KVM_ARCH_FP_F_F23, kvm_cpu_context, fp.f.f[23]);
+	OFFSET(KVM_ARCH_FP_F_F24, kvm_cpu_context, fp.f.f[24]);
+	OFFSET(KVM_ARCH_FP_F_F25, kvm_cpu_context, fp.f.f[25]);
+	OFFSET(KVM_ARCH_FP_F_F26, kvm_cpu_context, fp.f.f[26]);
+	OFFSET(KVM_ARCH_FP_F_F27, kvm_cpu_context, fp.f.f[27]);
+	OFFSET(KVM_ARCH_FP_F_F28, kvm_cpu_context, fp.f.f[28]);
+	OFFSET(KVM_ARCH_FP_F_F29, kvm_cpu_context, fp.f.f[29]);
+	OFFSET(KVM_ARCH_FP_F_F30, kvm_cpu_context, fp.f.f[30]);
+	OFFSET(KVM_ARCH_FP_F_F31, kvm_cpu_context, fp.f.f[31]);
+	OFFSET(KVM_ARCH_FP_F_FCSR, kvm_cpu_context, fp.f.fcsr);
+
+	/* D extension */
+
+	OFFSET(KVM_ARCH_FP_D_F0, kvm_cpu_context, fp.d.f[0]);
+	OFFSET(KVM_ARCH_FP_D_F1, kvm_cpu_context, fp.d.f[1]);
+	OFFSET(KVM_ARCH_FP_D_F2, kvm_cpu_context, fp.d.f[2]);
+	OFFSET(KVM_ARCH_FP_D_F3, kvm_cpu_context, fp.d.f[3]);
+	OFFSET(KVM_ARCH_FP_D_F4, kvm_cpu_context, fp.d.f[4]);
+	OFFSET(KVM_ARCH_FP_D_F5, kvm_cpu_context, fp.d.f[5]);
+	OFFSET(KVM_ARCH_FP_D_F6, kvm_cpu_context, fp.d.f[6]);
+	OFFSET(KVM_ARCH_FP_D_F7, kvm_cpu_context, fp.d.f[7]);
+	OFFSET(KVM_ARCH_FP_D_F8, kvm_cpu_context, fp.d.f[8]);
+	OFFSET(KVM_ARCH_FP_D_F9, kvm_cpu_context, fp.d.f[9]);
+	OFFSET(KVM_ARCH_FP_D_F10, kvm_cpu_context, fp.d.f[10]);
+	OFFSET(KVM_ARCH_FP_D_F11, kvm_cpu_context, fp.d.f[11]);
+	OFFSET(KVM_ARCH_FP_D_F12, kvm_cpu_context, fp.d.f[12]);
+	OFFSET(KVM_ARCH_FP_D_F13, kvm_cpu_context, fp.d.f[13]);
+	OFFSET(KVM_ARCH_FP_D_F14, kvm_cpu_context, fp.d.f[14]);
+	OFFSET(KVM_ARCH_FP_D_F15, kvm_cpu_context, fp.d.f[15]);
+	OFFSET(KVM_ARCH_FP_D_F16, kvm_cpu_context, fp.d.f[16]);
+	OFFSET(KVM_ARCH_FP_D_F17, kvm_cpu_context, fp.d.f[17]);
+	OFFSET(KVM_ARCH_FP_D_F18, kvm_cpu_context, fp.d.f[18]);
+	OFFSET(KVM_ARCH_FP_D_F19, kvm_cpu_context, fp.d.f[19]);
+	OFFSET(KVM_ARCH_FP_D_F20, kvm_cpu_context, fp.d.f[20]);
+	OFFSET(KVM_ARCH_FP_D_F21, kvm_cpu_context, fp.d.f[21]);
+	OFFSET(KVM_ARCH_FP_D_F22, kvm_cpu_context, fp.d.f[22]);
+	OFFSET(KVM_ARCH_FP_D_F23, kvm_cpu_context, fp.d.f[23]);
+	OFFSET(KVM_ARCH_FP_D_F24, kvm_cpu_context, fp.d.f[24]);
+	OFFSET(KVM_ARCH_FP_D_F25, kvm_cpu_context, fp.d.f[25]);
+	OFFSET(KVM_ARCH_FP_D_F26, kvm_cpu_context, fp.d.f[26]);
+	OFFSET(KVM_ARCH_FP_D_F27, kvm_cpu_context, fp.d.f[27]);
+	OFFSET(KVM_ARCH_FP_D_F28, kvm_cpu_context, fp.d.f[28]);
+	OFFSET(KVM_ARCH_FP_D_F29, kvm_cpu_context, fp.d.f[29]);
+	OFFSET(KVM_ARCH_FP_D_F30, kvm_cpu_context, fp.d.f[30]);
+	OFFSET(KVM_ARCH_FP_D_F31, kvm_cpu_context, fp.d.f[31]);
+	OFFSET(KVM_ARCH_FP_D_FCSR, kvm_cpu_context, fp.d.fcsr);
+#endif
 	/*
 	 * THREAD_{F,X}* might be larger than a S-type offset can handle, but
 	 * these are used in performance-sensitive assembly so we can't resort
@@ -500,4 +660,9 @@ void asm_offsets(void)
 	 * ensures the alignment is sane.
 	 */
 	DEFINE(PT_SIZE_ON_STACK, ALIGN(sizeof(struct pt_regs), STACK_ALIGN));
+#if 0
+	OFFSET(KERNEL_MAP_VIRT_ADDR, kernel_mapping, virt_addr);
+#endif
+	OFFSET(SBI_HART_BOOT_TASK_PTR_OFFSET, sbi_hart_boot_data, task_ptr);
+	OFFSET(SBI_HART_BOOT_STACK_PTR_OFFSET, sbi_hart_boot_data, stack_ptr);
 }

arch/riscv/kernel/cpu_ops_sbi.c

@@ -7,13 +7,22 @@
 
 #include <linux/init.h>
 #include <linux/mm.h>
+#include <linux/sched/task_stack.h>
 #include <asm/cpu_ops.h>
+#include <asm/cpu_ops_sbi.h>
 #include <asm/sbi.h>
 #include <asm/smp.h>
 
 extern char secondary_start_sbi[];
 const struct cpu_operations cpu_ops_sbi;
 
+/*
+ * Ordered booting via HSM brings one cpu at a time. However, cpu hotplug can
+ * be invoked from multiple threads in parallel. Define a per cpu data
+ * to handle that.
+ */
+DEFINE_PER_CPU(struct sbi_hart_boot_data, boot_data);
+
 static int sbi_hsm_hart_start(unsigned long hartid, unsigned long saddr,
 			      unsigned long priv)
 {
@@ -55,14 +64,19 @@ static int sbi_hsm_hart_get_status(unsigned long hartid)
 
 static int sbi_cpu_start(unsigned int cpuid, struct task_struct *tidle)
 {
-	int rc;
 	unsigned long boot_addr = __pa_symbol(secondary_start_sbi);
 	int hartid = cpuid_to_hartid_map(cpuid);
+	unsigned long hsm_data;
+	struct sbi_hart_boot_data *bdata = &per_cpu(boot_data, cpuid);
 
-	cpu_update_secondary_bootdata(cpuid, tidle);
+	/* Make sure tidle is updated */
-	rc = sbi_hsm_hart_start(hartid, boot_addr, 0);
+	smp_mb();
-
+	bdata->task_ptr = tidle;
-	return rc;
+	bdata->stack_ptr = task_stack_page(tidle) + THREAD_SIZE;
+	/* Make sure boot data is updated */
+	smp_mb();
+	hsm_data = __pa(bdata);
+	return sbi_hsm_hart_start(hartid, boot_addr, hsm_data);
 }
 
 static int sbi_cpu_prepare(unsigned int cpuid)
@@ -97,7 +111,7 @@ static int sbi_cpu_is_stopped(unsigned int cpuid)
 
 	rc = sbi_hsm_hart_get_status(hartid);
 
-	if (rc == SBI_HSM_HART_STATUS_STOPPED)
+	if (rc == SBI_HSM_STATE_STOPPED)
 		return 0;
 	return rc;
 }

arch/riscv/kernel/entry.S

@@ -251,7 +251,7 @@ ret_from_syscall_rejected:
 	andi t0, t0, _TIF_SYSCALL_WORK
 	bnez t0, handle_syscall_trace_exit
 
-ret_from_exception:
+ENTRY(ret_from_exception)
 	REG_L s0, PT_STATUS(sp)
 	csrc CSR_STATUS, SR_IE
 #ifdef CONFIG_TRACE_IRQFLAGS

arch/riscv/kernel/head.S

@@ -10,6 +10,7 @@
 #include <asm/thread_info.h>
 #include <asm/page.h>
 #include <asm/csr.h>
+#include <asm/cpu_ops_sbi.h>
 #include <asm/hwcap.h>
 #include <asm/image.h>
 #include "efi-header.S"
@@ -67,7 +68,8 @@ pe_head_start:
 
 .align 2
 #ifdef CONFIG_MMU
-relocate:
+	.global relocate_enable_mmu
+relocate_enable_mmu:
 	/* Relocate return address */
 	li a1, PAGE_OFFSET
 	la a2, _start
@@ -142,13 +144,15 @@ secondary_start_sbi:
 	la a3, .Lsecondary_park
 	csrw CSR_TVEC, a3
 
-	slli a3, a0, LGREG
+	/* a0 contains the hartid & a1 contains boot data */
-	la a4, __cpu_up_stack_pointer
+	li a2, SBI_HART_BOOT_TASK_PTR_OFFSET
-	la a5, __cpu_up_task_pointer
+	XIP_FIXUP_OFFSET a2
-	add a4, a3, a4
+	add a2, a2, a1
-	add a5, a3, a5
+	REG_L tp, (a2)
-	REG_L sp, (a4)
+	li a3, SBI_HART_BOOT_STACK_PTR_OFFSET
-	REG_L tp, (a5)
+	XIP_FIXUP_OFFSET a3
+	add a3, a3, a1
+	REG_L sp, (a3)
 
 	.global secondary_start_common
 secondary_start_common:
@@ -156,7 +160,8 @@ secondary_start_common:
 #ifdef CONFIG_MMU
 	/* Enable virtual memory and relocate to virtual address */
 	la a0, swapper_pg_dir
-	call relocate
+	XIP_FIXUP_OFFSET a0
+	call relocate_enable_mmu
 #endif
 	call setup_trap_vector
 	tail smp_callin
@@ -266,7 +271,8 @@ clear_bss_done:
 	call setup_vm
 #ifdef CONFIG_MMU
 	la a0, early_pg_dir
-	call relocate
+	XIP_FIXUP_OFFSET a0
+	call relocate_enable_mmu
 #endif /* CONFIG_MMU */
 
 	call setup_trap_vector

arch/riscv/kernel/machine_kexec.c

@@ -179,9 +179,10 @@ machine_crash_shutdown(struct pt_regs *regs)
 {
 	local_irq_disable();
 
+#ifdef CONFIG_SMP
 	/* shutdown non-crashing cpus */
 	crash_smp_send_stop();
-
+#endif
 	crash_save_cpu(regs, smp_processor_id());
 	machine_kexec_mask_interrupts();
 
@@ -211,8 +212,10 @@ machine_kexec(struct kimage *image)
 	void *control_code_buffer = page_address(image->control_code_page);
 	riscv_kexec_method kexec_method = NULL;
 
+#ifdef CONFIG_SMP
 	WARN(smp_crash_stop_failed(),
 		"Some CPUs may be stale, kdump will be unreliable.\n");
+#endif
 
 	if (image->type != KEXEC_TYPE_CRASH)
 		kexec_method = control_code_buffer;

arch/riscv/kernel/perf_callchain.c

@@ -75,13 +75,13 @@ void perf_callchain_user(struct perf_callchain_entry_ctx *entry,
 		fp = user_backtrace(entry, fp, 0);
 }
 
-bool fill_callchain(unsigned long pc, void *entry)
+bool fill_callchain(unsigned long pc, unsigned long regs, void *entry)
 {
-	return perf_callchain_store(entry, pc) == 0;
+	return perf_callchain_store(entry, pc);
 }
 
 void notrace walk_stackframe(struct task_struct *task,
-	struct pt_regs *regs, bool (*fn)(unsigned long, void *), void *arg);
+	struct pt_regs *regs, bool (*fn)(unsigned long, unsigned long, void *), void *arg);
 void perf_callchain_kernel(struct perf_callchain_entry_ctx *entry,
 			   struct pt_regs *regs)
 {

arch/riscv/kernel/probes/decode-insn.c

@@ -38,11 +38,10 @@ riscv_probe_decode_insn(probe_opcode_t *addr, struct arch_probe_insn *api)
 	RISCV_INSN_REJECTED(c_ebreak,		insn);
 #endif
 
-	RISCV_INSN_REJECTED(auipc,		insn);
-	RISCV_INSN_REJECTED(branch,		insn);
-
 	RISCV_INSN_SET_SIMULATE(jal,		insn);
 	RISCV_INSN_SET_SIMULATE(jalr,		insn);
+	RISCV_INSN_SET_SIMULATE(auipc,		insn);
+	RISCV_INSN_SET_SIMULATE(branch,		insn);
 
 	return INSN_GOOD;
 }

arch/riscv/kernel/probes/kprobes.c

@@ -46,6 +46,21 @@ static void __kprobes arch_simulate_insn(struct kprobe *p, struct pt_regs *regs)
 	post_kprobe_handler(kcb, regs);
 }
 
+static bool __kprobes arch_check_kprobe(struct kprobe *p)
+{
+	unsigned long tmp  = (unsigned long)p->addr - p->offset;
+	unsigned long addr = (unsigned long)p->addr;
+
+	while (tmp <= addr) {
+		if (tmp == addr)
+			return true;
+
+		tmp += GET_INSN_LENGTH(*(u16 *)tmp);
+	}
+
+	return false;
+}
+
 int __kprobes arch_prepare_kprobe(struct kprobe *p)
 {
 	unsigned long probe_addr = (unsigned long)p->addr;
@@ -56,6 +71,9 @@ int __kprobes arch_prepare_kprobe(struct kprobe *p)
 		return -EINVAL;
 	}
 
+	if (!arch_check_kprobe(p))
+		return -EILSEQ;
+
 	/* copy instruction */
 	p->opcode = le32_to_cpu(*p->addr);
 

arch/riscv/kernel/probes/simulate-insn.c

@@ -83,3 +83,115 @@ bool __kprobes simulate_jalr(u32 opcode, unsigned long addr, struct pt_regs *reg
 
 	return ret;
 }
+
+#define auipc_rd_idx(opcode) \
+	((opcode >> 7) & 0x1f)
+
+#define auipc_imm(opcode) \
+	((((opcode) >> 12) & 0xfffff) << 12)
+
+#if __riscv_xlen == 64
+#define auipc_offset(opcode)	sign_extend64(auipc_imm(opcode), 31)
+#elif __riscv_xlen == 32
+#define auipc_offset(opcode)	auipc_imm(opcode)
+#else
+#error "Unexpected __riscv_xlen"
+#endif
+
+bool __kprobes simulate_auipc(u32 opcode, unsigned long addr, struct pt_regs *regs)
+{
+	/*
+	 * auipc instruction:
+	 *  31        12 11 7 6      0
+	 * | imm[31:12] | rd | opcode |
+	 *        20       5     7
+	 */
+
+	u32 rd_idx = auipc_rd_idx(opcode);
+	unsigned long rd_val = addr + auipc_offset(opcode);
+
+	if (!rv_insn_reg_set_val(regs, rd_idx, rd_val))
+		return false;
+
+	instruction_pointer_set(regs, addr + 4);
+
+	return true;
+}
+
+#define branch_rs1_idx(opcode) \
+	(((opcode) >> 15) & 0x1f)
+
+#define branch_rs2_idx(opcode) \
+	(((opcode) >> 20) & 0x1f)
+
+#define branch_funct3(opcode) \
+	(((opcode) >> 12) & 0x7)
+
+#define branch_imm(opcode) \
+	(((((opcode) >>  8) & 0xf ) <<  1) | \
+	 ((((opcode) >> 25) & 0x3f) <<  5) | \
+	 ((((opcode) >>  7) & 0x1 ) << 11) | \
+	 ((((opcode) >> 31) & 0x1 ) << 12))
+
+#define branch_offset(opcode) \
+	sign_extend32((branch_imm(opcode)), 12)
+
+#define BRANCH_BEQ	0x0
+#define BRANCH_BNE	0x1
+#define BRANCH_BLT	0x4
+#define BRANCH_BGE	0x5
+#define BRANCH_BLTU	0x6
+#define BRANCH_BGEU	0x7
+
+bool __kprobes simulate_branch(u32 opcode, unsigned long addr, struct pt_regs *regs)
+{
+	/*
+	 * branch instructions:
+	 *      31    30       25 24 20 19 15 14    12 11       8    7      6      0
+	 * | imm[12] | imm[10:5] | rs2 | rs1 | funct3 | imm[4:1] | imm[11] | opcode |
+	 *     1           6        5     5      3         4         1         7
+	 *     imm[12|10:5]        rs2   rs1    000       imm[4:1|11]       1100011  BEQ
+	 *     imm[12|10:5]        rs2   rs1    001       imm[4:1|11]       1100011  BNE
+	 *     imm[12|10:5]        rs2   rs1    100       imm[4:1|11]       1100011  BLT
+	 *     imm[12|10:5]        rs2   rs1    101       imm[4:1|11]       1100011  BGE
+	 *     imm[12|10:5]        rs2   rs1    110       imm[4:1|11]       1100011  BLTU
+	 *     imm[12|10:5]        rs2   rs1    111       imm[4:1|11]       1100011  BGEU
+	 */
+
+	s32 offset;
+	s32 offset_tmp;
+	unsigned long rs1_val;
+	unsigned long rs2_val;
+
+	if (!rv_insn_reg_get_val(regs, branch_rs1_idx(opcode), &rs1_val) ||
+	    !rv_insn_reg_get_val(regs, branch_rs2_idx(opcode), &rs2_val))
+		return false;
+
+	offset_tmp = branch_offset(opcode);
+	switch (branch_funct3(opcode)) {
+	case BRANCH_BEQ:
+		offset = (rs1_val == rs2_val) ? offset_tmp : 4;
+		break;
+	case BRANCH_BNE:
+		offset = (rs1_val != rs2_val) ? offset_tmp : 4;
+		break;
+	case BRANCH_BLT:
+		offset = ((long)rs1_val < (long)rs2_val) ? offset_tmp : 4;
+		break;
+	case BRANCH_BGE:
+		offset = ((long)rs1_val >= (long)rs2_val) ? offset_tmp : 4;
+		break;
+	case BRANCH_BLTU:
+		offset = (rs1_val < rs2_val) ? offset_tmp : 4;
+		break;
+	case BRANCH_BGEU:
+		offset = (rs1_val >= rs2_val) ? offset_tmp : 4;
+		break;
+	default:
+		return false;
+	}
+
+	instruction_pointer_set(regs, addr + offset);
+
+	return true;
+}

arch/riscv/kernel/process.c

@@ -23,6 +23,7 @@
 #include <asm/string.h>
 #include <asm/switch_to.h>
 #include <asm/thread_info.h>
+#include <asm/cpuidle.h>
 
 register unsigned long gp_in_global __asm__("gp");
 
@@ -37,7 +38,7 @@ extern asmlinkage void ret_from_kernel_thread(void);
 
 void arch_cpu_idle(void)
 {
-	wait_for_interrupt();
+	cpu_do_idle();
 	raw_local_irq_enable();
 }
 

arch/riscv/kernel/ptrace.c

@@ -97,6 +97,7 @@ static int riscv_vr_get(struct task_struct *target,
 	struct __riscv_v_state *vstate = &target->thread.vstate;
 
 	membuf_write(&to, vstate, offsetof(struct __riscv_v_state, vtype));
+	membuf_store(&to, vstate->vtype);
 	return membuf_zero(&to, 4);	// explicitly pad
 }
 

arch/riscv/kernel/stacktrace.c

@@ -21,8 +21,10 @@ struct stackframe {
 	unsigned long ra;
 };
 
+extern asmlinkage void ret_from_exception(void);
+
 void notrace walk_stackframe(struct task_struct *task, struct pt_regs *regs,
-			     bool (*fn)(unsigned long, void *), void *arg)
+			     bool (*fn)(unsigned long, unsigned long, void *), void *arg)
 {
 	unsigned long fp, sp, pc;
 
@@ -46,7 +48,7 @@ void notrace walk_stackframe(struct task_struct *task, struct pt_regs *regs,
 		unsigned long low, high;
 		struct stackframe *frame;
 
-		if (unlikely(!__kernel_text_address(pc) || fn(pc, arg)))
+		if (unlikely(!__kernel_text_address(pc) || fn(pc, 0, arg)))
 			break;
 
 		/* Validate frame pointer */
@@ -57,16 +59,29 @@ void notrace walk_stackframe(struct task_struct *task, struct pt_regs *regs,
 		/* Unwind stack frame */
 		frame = (struct stackframe *)fp - 1;
 		sp = fp;
+		if (regs && (regs->epc == pc) && (frame->fp & 0x7)) {
+			fp = frame->ra;
+			pc = regs->ra;
+		} else {
 			fp = frame->fp;
 			pc = ftrace_graph_ret_addr(current, NULL, frame->ra,
-					   (unsigned long *)(fp - 8));
+						   &frame->ra);
+			if (pc == (unsigned long)ret_from_exception) {
+				if (unlikely(!__kernel_text_address(pc) || fn(pc, sp, arg)))
+					break;
+
+				pc = ((struct pt_regs *)sp)->epc;
+				fp = ((struct pt_regs *)sp)->s0;
+			}
+		}
+
 	}
 }
 
 #else /* !CONFIG_FRAME_POINTER */
 
 void notrace walk_stackframe(struct task_struct *task,
-	struct pt_regs *regs, bool (*fn)(unsigned long, void *), void *arg)
+	struct pt_regs *regs, bool (*fn)(unsigned long, unsigned long, void *), void *arg)
 {
 	unsigned long sp, pc;
 	unsigned long *ksp;
@@ -88,7 +103,7 @@ void notrace walk_stackframe(struct task_struct *task,
 
 	ksp = (unsigned long *)sp;
 	while (!kstack_end(ksp)) {
-		if (__kernel_text_address(pc) && unlikely(fn(pc, arg)))
+		if (__kernel_text_address(pc) && unlikely(fn(pc, 0, arg)))
 			break;
 		pc = (*ksp++) - 0x4;
 	}
@@ -97,11 +112,15 @@ void notrace walk_stackframe(struct task_struct *task,
 #endif /* CONFIG_FRAME_POINTER */
 
 
-static bool print_trace_address(unsigned long pc, void *arg)
+static bool print_trace_address(unsigned long pc, unsigned long regs, void *arg)
 {
 	const char *loglvl = arg;
 
 	print_ip_sym(loglvl, pc);
+
+	if (regs)
+		show_regs((struct pt_regs *)regs);
+
 	return false;
 }
 
@@ -109,9 +128,10 @@ void show_stack(struct task_struct *task, unsigned long *sp, const char *loglvl)
 {
 	pr_cont("Call Trace:\n");
 	walk_stackframe(task, NULL, print_trace_address, (void *)loglvl);
+	pr_cont("End Trace.\n");
 }
 
-static bool save_wchan(unsigned long pc, void *arg)
+static bool save_wchan(unsigned long pc, unsigned long regs, void *arg)
 {
 	if (!in_sched_functions(pc)) {
 		unsigned long *p = arg;
@@ -148,7 +168,7 @@ static bool __save_trace(unsigned long pc, void *arg, bool nosched)
 	return (trace->nr_entries >= trace->max_entries);
 }
 
-static bool save_trace(unsigned long pc, void *arg)
+static bool save_trace(unsigned long pc, unsigned long regs, void *arg)
 {
 	return __save_trace(pc, arg, false);
 }

arch/riscv/kernel/suspend.c

@@ -0,0 +1,87 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2021 Western Digital Corporation or its affiliates.
+ * Copyright (c) 2022 Ventana Micro Systems Inc.
+ */
+
+#include <linux/ftrace.h>
+#include <asm/csr.h>
+#include <asm/suspend.h>
+
+static void suspend_save_csrs(struct suspend_context *context)
+{
+	context->scratch = csr_read(CSR_SCRATCH);
+	context->tvec = csr_read(CSR_TVEC);
+	context->ie = csr_read(CSR_IE);
+
+	/*
+	 * No need to save/restore IP CSR (i.e. MIP or SIP) because:
+	 *
+	 * 1. For no-MMU (M-mode) kernel, the bits in MIP are set by
+	 *    external devices (such as interrupt controller, timer, etc).
+	 * 2. For MMU (S-mode) kernel, the bits in SIP are set by
+	 *    M-mode firmware and external devices (such as interrupt
+	 *    controller, etc).
+	 */
+
+#ifdef CONFIG_MMU
+	context->satp = csr_read(CSR_SATP);
+#endif
+}
+
+static void suspend_restore_csrs(struct suspend_context *context)
+{
+	csr_write(CSR_SCRATCH, context->scratch);
+	csr_write(CSR_TVEC, context->tvec);
+	csr_write(CSR_IE, context->ie);
+
+#ifdef CONFIG_MMU
+	csr_write(CSR_SATP, context->satp);
+#endif
+}
+
+int cpu_suspend(unsigned long arg,
+		int (*finish)(unsigned long arg,
+			      unsigned long entry,
+			      unsigned long context))
+{
+	int rc = 0;
+	struct suspend_context context = { 0 };
+
+	/* Finisher should be non-NULL */
+	if (!finish)
+		return -EINVAL;
+
+	/* Save additional CSRs*/
+	suspend_save_csrs(&context);
+
+	/*
+	 * Function graph tracer state gets incosistent when the kernel
+	 * calls functions that never return (aka finishers) hence disable
+	 * graph tracing during their execution.
+	 */
+	pause_graph_tracing();
+
+	/* Save context on stack */
+	if (__cpu_suspend_enter(&context)) {
+		/* Call the finisher */
+		rc = finish(arg, __pa_symbol(__cpu_resume_enter),
+			    (ulong)&context);
+
+		/*
+		 * Should never reach here, unless the suspend finisher
+		 * fails. Successful cpu_suspend() should return from
+		 * __cpu_resume_entry()
+		 */
+		if (!rc)
+			rc = -EOPNOTSUPP;
+	}
+
+	/* Enable function graph tracer */
+	unpause_graph_tracing();
+
+	/* Restore additional CSRs */
+	suspend_restore_csrs(&context);
+
+	return rc;
+}

arch/riscv/kernel/suspend_entry.S

@@ -0,0 +1,124 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2021 Western Digital Corporation or its affiliates.
+ * Copyright (c) 2022 Ventana Micro Systems Inc.
+ */
+
+#include <linux/linkage.h>
+#include <asm/asm.h>
+#include <asm/asm-offsets.h>
+#include <asm/csr.h>
+
+	.text
+	.altmacro
+	.option norelax
+
+ENTRY(__cpu_suspend_enter)
+	/* Save registers (except A0 and T0-T6) */
+	REG_S	ra, (SUSPEND_CONTEXT_REGS + PT_RA)(a0)
+	REG_S	sp, (SUSPEND_CONTEXT_REGS + PT_SP)(a0)
+	REG_S	gp, (SUSPEND_CONTEXT_REGS + PT_GP)(a0)
+	REG_S	tp, (SUSPEND_CONTEXT_REGS + PT_TP)(a0)
+	REG_S	s0, (SUSPEND_CONTEXT_REGS + PT_S0)(a0)
+	REG_S	s1, (SUSPEND_CONTEXT_REGS + PT_S1)(a0)
+	REG_S	a1, (SUSPEND_CONTEXT_REGS + PT_A1)(a0)
+	REG_S	a2, (SUSPEND_CONTEXT_REGS + PT_A2)(a0)
+	REG_S	a3, (SUSPEND_CONTEXT_REGS + PT_A3)(a0)
+	REG_S	a4, (SUSPEND_CONTEXT_REGS + PT_A4)(a0)
+	REG_S	a5, (SUSPEND_CONTEXT_REGS + PT_A5)(a0)
+	REG_S	a6, (SUSPEND_CONTEXT_REGS + PT_A6)(a0)
+	REG_S	a7, (SUSPEND_CONTEXT_REGS + PT_A7)(a0)
+	REG_S	s2, (SUSPEND_CONTEXT_REGS + PT_S2)(a0)
+	REG_S	s3, (SUSPEND_CONTEXT_REGS + PT_S3)(a0)
+	REG_S	s4, (SUSPEND_CONTEXT_REGS + PT_S4)(a0)
+	REG_S	s5, (SUSPEND_CONTEXT_REGS + PT_S5)(a0)
+	REG_S	s6, (SUSPEND_CONTEXT_REGS + PT_S6)(a0)
+	REG_S	s7, (SUSPEND_CONTEXT_REGS + PT_S7)(a0)
+	REG_S	s8, (SUSPEND_CONTEXT_REGS + PT_S8)(a0)
+	REG_S	s9, (SUSPEND_CONTEXT_REGS + PT_S9)(a0)
+	REG_S	s10, (SUSPEND_CONTEXT_REGS + PT_S10)(a0)
+	REG_S	s11, (SUSPEND_CONTEXT_REGS + PT_S11)(a0)
+
+	/* Save CSRs */
+	csrr	t0, CSR_EPC
+	REG_S	t0, (SUSPEND_CONTEXT_REGS + PT_EPC)(a0)
+	csrr	t0, CSR_STATUS
+	REG_S	t0, (SUSPEND_CONTEXT_REGS + PT_STATUS)(a0)
+	csrr	t0, CSR_TVAL
+	REG_S	t0, (SUSPEND_CONTEXT_REGS + PT_BADADDR)(a0)
+	csrr	t0, CSR_CAUSE
+	REG_S	t0, (SUSPEND_CONTEXT_REGS + PT_CAUSE)(a0)
+
+	/* Return non-zero value */
+	li	a0, 1
+
+	/* Return to C code */
+	ret
+END(__cpu_suspend_enter)
+
+ENTRY(__cpu_resume_enter)
+	/* Load the global pointer */
+	.option push
+	.option norelax
+		la gp, __global_pointer$
+	.option pop
+
+#ifdef CONFIG_MMU
+	/* Save A0 and A1 */
+	add	t0, a0, zero
+	add	t1, a1, zero
+
+	/* Enable MMU */
+	la	a0, swapper_pg_dir
+	XIP_FIXUP_OFFSET a0
+	call	relocate_enable_mmu
+
+	/* Restore A0 and A1 */
+	add	a0, t0, zero
+	add	a1, t1, zero
+#endif
+
+	/* Make A0 point to suspend context */
+	add	a0, a1, zero
+
+	/* Restore CSRs */
+	REG_L	t0, (SUSPEND_CONTEXT_REGS + PT_EPC)(a0)
+	csrw	CSR_EPC, t0
+	REG_L	t0, (SUSPEND_CONTEXT_REGS + PT_STATUS)(a0)
+	csrw	CSR_STATUS, t0
+	REG_L	t0, (SUSPEND_CONTEXT_REGS + PT_BADADDR)(a0)
+	csrw	CSR_TVAL, t0
+	REG_L	t0, (SUSPEND_CONTEXT_REGS + PT_CAUSE)(a0)
+	csrw	CSR_CAUSE, t0
+
+	/* Restore registers (except A0 and T0-T6) */
+	REG_L	ra, (SUSPEND_CONTEXT_REGS + PT_RA)(a0)
+	REG_L	sp, (SUSPEND_CONTEXT_REGS + PT_SP)(a0)
+	REG_L	gp, (SUSPEND_CONTEXT_REGS + PT_GP)(a0)
+	REG_L	tp, (SUSPEND_CONTEXT_REGS + PT_TP)(a0)
+	REG_L	s0, (SUSPEND_CONTEXT_REGS + PT_S0)(a0)
+	REG_L	s1, (SUSPEND_CONTEXT_REGS + PT_S1)(a0)
+	REG_L	a1, (SUSPEND_CONTEXT_REGS + PT_A1)(a0)
+	REG_L	a2, (SUSPEND_CONTEXT_REGS + PT_A2)(a0)
+	REG_L	a3, (SUSPEND_CONTEXT_REGS + PT_A3)(a0)
+	REG_L	a4, (SUSPEND_CONTEXT_REGS + PT_A4)(a0)
+	REG_L	a5, (SUSPEND_CONTEXT_REGS + PT_A5)(a0)
+	REG_L	a6, (SUSPEND_CONTEXT_REGS + PT_A6)(a0)
+	REG_L	a7, (SUSPEND_CONTEXT_REGS + PT_A7)(a0)
+	REG_L	s2, (SUSPEND_CONTEXT_REGS + PT_S2)(a0)
+	REG_L	s3, (SUSPEND_CONTEXT_REGS + PT_S3)(a0)
+	REG_L	s4, (SUSPEND_CONTEXT_REGS + PT_S4)(a0)
+	REG_L	s5, (SUSPEND_CONTEXT_REGS + PT_S5)(a0)
+	REG_L	s6, (SUSPEND_CONTEXT_REGS + PT_S6)(a0)
+	REG_L	s7, (SUSPEND_CONTEXT_REGS + PT_S7)(a0)
+	REG_L	s8, (SUSPEND_CONTEXT_REGS + PT_S8)(a0)
+	REG_L	s9, (SUSPEND_CONTEXT_REGS + PT_S9)(a0)
+	REG_L	s10, (SUSPEND_CONTEXT_REGS + PT_S10)(a0)
+	REG_L	s11, (SUSPEND_CONTEXT_REGS + PT_S11)(a0)
+
+	/* Return zero value */
+	add	a0, zero, zero
+
+	/* Return to C code */
+	ret
+END(__cpu_resume_enter)

arch/riscv/kvm/vcpu_sbi_hsm.c

@@ -0,0 +1,105 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2021 Western Digital Corporation or its affiliates.
+ *
+ * Authors:
+ *     Atish Patra <atish.patra@wdc.com>
+ */
+
+#include <linux/errno.h>
+#include <linux/err.h>
+#include <linux/kvm_host.h>
+#include <asm/csr.h>
+#include <asm/sbi.h>
+#include <asm/kvm_vcpu_sbi.h>
+
+static int kvm_sbi_hsm_vcpu_start(struct kvm_vcpu *vcpu)
+{
+	struct kvm_cpu_context *reset_cntx;
+	struct kvm_cpu_context *cp = &vcpu->arch.guest_context;
+	struct kvm_vcpu *target_vcpu;
+	unsigned long target_vcpuid = cp->a0;
+
+	target_vcpu = kvm_get_vcpu_by_id(vcpu->kvm, target_vcpuid);
+	if (!target_vcpu)
+		return -EINVAL;
+	if (!target_vcpu->arch.power_off)
+		return -EALREADY;
+
+	reset_cntx = &target_vcpu->arch.guest_reset_context;
+	/* start address */
+	reset_cntx->sepc = cp->a1;
+	/* target vcpu id to start */
+	reset_cntx->a0 = target_vcpuid;
+	/* private data passed from kernel */
+	reset_cntx->a1 = cp->a2;
+	kvm_make_request(KVM_REQ_VCPU_RESET, target_vcpu);
+
+	kvm_riscv_vcpu_power_on(target_vcpu);
+
+	return 0;
+}
+
+static int kvm_sbi_hsm_vcpu_stop(struct kvm_vcpu *vcpu)
+{
+	if (vcpu->arch.power_off)
+		return -EINVAL;
+
+	kvm_riscv_vcpu_power_off(vcpu);
+
+	return 0;
+}
+
+static int kvm_sbi_hsm_vcpu_get_status(struct kvm_vcpu *vcpu)
+{
+	struct kvm_cpu_context *cp = &vcpu->arch.guest_context;
+	unsigned long target_vcpuid = cp->a0;
+	struct kvm_vcpu *target_vcpu;
+
+	target_vcpu = kvm_get_vcpu_by_id(vcpu->kvm, target_vcpuid);
+	if (!target_vcpu)
+		return -EINVAL;
+	if (!target_vcpu->arch.power_off)
+		return SBI_HSM_STATE_STARTED;
+	else
+		return SBI_HSM_STATE_STOPPED;
+}
+
+static int kvm_sbi_ext_hsm_handler(struct kvm_vcpu *vcpu, struct kvm_run *run,
+				   unsigned long *out_val,
+				   struct kvm_cpu_trap *utrap,
+				   bool *exit)
+{
+	int ret = 0;
+	struct kvm_cpu_context *cp = &vcpu->arch.guest_context;
+	struct kvm *kvm = vcpu->kvm;
+	unsigned long funcid = cp->a6;
+
+	switch (funcid) {
+	case SBI_EXT_HSM_HART_START:
+		mutex_lock(&kvm->lock);
+		ret = kvm_sbi_hsm_vcpu_start(vcpu);
+		mutex_unlock(&kvm->lock);
+		break;
+	case SBI_EXT_HSM_HART_STOP:
+		ret = kvm_sbi_hsm_vcpu_stop(vcpu);
+		break;
+	case SBI_EXT_HSM_HART_STATUS:
+		ret = kvm_sbi_hsm_vcpu_get_status(vcpu);
+		if (ret >= 0) {
+			*out_val = ret;
+			ret = 0;
+		}
+		break;
+	default:
+		ret = -EOPNOTSUPP;
+	}
+
+	return ret;
+}
+
+const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_hsm = {
+	.extid_start = SBI_EXT_HSM,
+	.extid_end = SBI_EXT_HSM,
+	.handler = kvm_sbi_ext_hsm_handler,
+};

arch/riscv/mm/cacheflush.c

@@ -84,8 +84,10 @@ void flush_icache_pte(pte_t pte)
 {
 	struct page *page = pte_page(pte);
 
-	if (!test_and_set_bit(PG_dcache_clean, &page->flags))
+	if (!test_bit(PG_dcache_clean, &page->flags)) {
 		flush_icache_all();
+		set_bit(PG_dcache_clean, &page->flags);
+	}
 }
 #endif /* CONFIG_MMU */
 

arch/riscv/mm/context.c

@@ -56,14 +56,48 @@ void switch_mm(struct mm_struct *prev, struct mm_struct *next,
 	 */
 	cpu = smp_processor_id();
 
-	cpumask_clear_cpu(cpu, mm_cpumask(prev));
 	cpumask_set_cpu(cpu, mm_cpumask(next));
 
 #ifdef CONFIG_MMU
+	__asm__ __volatile__(
+			"jal t0,1f\n\t"
+			"1: \n\t"
+			"jal t0,2f\n\t"
+			"2: \n\t"
+			"jal t0,3f\n\t"
+			"3: \n\t"
+			"jal t0,4f\n\t"
+			"4: \n\t"
+			"jal t0,5f\n\t"
+			"5: \n\t"
+			"jal t0,6f\n\t"
+			"6: \n\t"
+			"jal t0,7f\n\t"
+			"7: \n\t"
+			"jal t0,8f\n\t"
+			"8: \n\t"
+			"jal t0,9f\n\t"
+			"9: \n\t"
+			"jal t0,10f\n\t"
+			"10: \n\t"
+			"jal t0,11f\n\t"
+			"11: \n\t"
+			"jal t0,12f\n\t"
+			"12: \n\t"
+			::: "memory", "t0");
+
 	check_and_switch_context(next, cpu);
 	asid = (next->context.asid.counter & SATP_ASID_MASK)
 		<< SATP_ASID_SHIFT;
 
+	local_flush_tlb_page(0);
+
+	/* flush utlb before setting satp */
+	__asm__ __volatile__(
+			"li t0, 0\n\t"
+			"sfence.vma t0, t0\n\t"
+			::: "memory", "t0");
+
 	csr_write(sptbr, virt_to_pfn(next->pgd) | SATP_MODE | asid);
 #endif
 

arch/riscv/mm/tlbflush.c

@@ -3,73 +3,6 @@
 #include <linux/mm.h>
 #include <linux/smp.h>
 #include <linux/sched.h>
-
-#define XUANTIE
-#ifdef  XUANTIE
-#include <asm/mmu_context.h>
-
-void flush_tlb_all(void)
-{
-#ifdef CONFIG_NO_SFENCE_VMA
-	csr_write(CSR_SMCIR, 1 << 26);
-#else
-	__asm__ __volatile__ ("sfence.vma" : : : "memory");
-#endif
-}
-
-void flush_tlb_mm(struct mm_struct *mm)
-{
-	int newpid = cpu_asid(mm);
-
-#ifdef CONFIG_NO_SFENCE_VMA
-	csr_write(CSR_SMCIR, (1 << 27) | newpid);
-#else
-	__asm__ __volatile__ ("sfence.vma zero, %0"
-				:
-				: "r"(newpid)
-				: "memory");
-#endif
-}
-
-void flush_tlb_page(struct vm_area_struct *vma, unsigned long addr)
-{
-	int newpid = cpu_asid(vma->vm_mm);
-
-#ifdef CONFIG_NO_SFENCE_VMA
-	csr_write(CSR_SMCIR, (1 << 27) | newpid);
-#else
-	addr &= PAGE_MASK;
-
-	__asm__ __volatile__ ("sfence.vma %0, %1"
-				:
-				: "r"(addr), "r"(newpid)
-				: "memory");
-#endif
-}
-
-void flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
-			unsigned long end)
-{
-	unsigned long newpid = cpu_asid(vma->vm_mm);
-
-#ifdef CONFIG_NO_SFENCE_VMA
-	csr_write(CSR_SMCIR, (1 << 27) | newpid);
-#else
-	start &= PAGE_MASK;
-	end   += PAGE_SIZE - 1;
-	end   &= PAGE_MASK;
-
-	while (start < end) {
-		__asm__ __volatile__ ("sfence.vma %0, %1"
-					:
-					: "r"(start), "r"(newpid)
-					: "memory");
-		start += PAGE_SIZE;
-	}
-#endif
-}
-#else
-
 #include <asm/sbi.h>
 
 void flush_tlb_all(void)
@@ -121,4 +54,3 @@ void flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
 {
 	__sbi_tlb_flush_range(mm_cpumask(vma->vm_mm), start, end - start);
 }
-#endif

drivers/block/zram/zram_drv.c

@@ -1385,14 +1385,13 @@ compress_again:
 				__GFP_KSWAPD_RECLAIM |
 				__GFP_NOWARN |
 				__GFP_HIGHMEM |
-				__GFP_MOVABLE |
+				__GFP_MOVABLE);
-				__GFP_CMA);
 	if (!handle) {
 		zcomp_stream_put(zram->comp);
 		atomic64_inc(&zram->stats.writestall);
 		handle = zs_malloc(zram->mem_pool, comp_len,
 				GFP_NOIO | __GFP_HIGHMEM |
-				__GFP_MOVABLE | __GFP_CMA);
+				__GFP_MOVABLE);
 		if (handle)
 			goto compress_again;
 		return -ENOMEM;

drivers/clk/thead/clk-light-fm.c

@@ -50,6 +50,7 @@ static u32 share_cnt_spi_clk_en;
 static u32 share_cnt_uart0_clk_en;
 static u32 share_cnt_uart2_clk_en;
 static u32 share_cnt_i2c2_clk_en;
+static u32 share_cnt_i2c3_clk_en;
 static u32 share_cnt_peri_i2s_clk_en;
 static u32 share_cnt_qspi1_clk_en;
 static u32 share_cnt_uart1_clk_en;
@@ -378,31 +379,31 @@ static int light_clocks_probe(struct platform_device *pdev)
 	clks[AONSYS_BUS_CLK] = thead_clk_fixed("aonsys_hclk", 101606400);	//from sys_pll, maybe change ?
 
 	/* Light Fullmask AP MUX */
-	clks[CPU_PLL0_BYPASS] = thead_light_clk_mux_flags("cpu_pll0_bypass", ap_base + 0x4, 30, 1, cpu_pll0_bypass_sels, ARRAY_SIZE(cpu_pll0_bypass_sels), CLK_SET_RATE_PARENT);
+	clks[CPU_PLL0_BYPASS] = thead_light_clk_mux_flags("cpu_pll0_bypass", ap_base + 0x4, 30, 1, cpu_pll0_bypass_sels, ARRAY_SIZE(cpu_pll0_bypass_sels), CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT);
-	clks[CPU_PLL1_BYPASS] = thead_light_clk_mux_flags("cpu_pll1_bypass", ap_base + 0x14, 30, 1, cpu_pll1_bypass_sels, ARRAY_SIZE(cpu_pll1_bypass_sels), CLK_SET_RATE_PARENT);
+	clks[CPU_PLL1_BYPASS] = thead_light_clk_mux_flags("cpu_pll1_bypass", ap_base + 0x14, 30, 1, cpu_pll1_bypass_sels, ARRAY_SIZE(cpu_pll1_bypass_sels), CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT);
-	clks[GMAC_PLL_BYPASS] = thead_light_clk_mux_flags("gmac_pll_bypass", ap_base + 0x24, 30, 1, gmac_pll_bypass_sels, ARRAY_SIZE(gmac_pll_bypass_sels), CLK_SET_RATE_PARENT);
+	clks[GMAC_PLL_BYPASS] = thead_light_clk_mux_flags("gmac_pll_bypass", ap_base + 0x24, 30, 1, gmac_pll_bypass_sels, ARRAY_SIZE(gmac_pll_bypass_sels), CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT);
-	clks[VIDEO_PLL_BYPASS] = thead_light_clk_mux_flags("video_pll_bypass", ap_base + 0x34, 30, 1, video_pll_bypass_sels, ARRAY_SIZE(video_pll_bypass_sels), CLK_SET_RATE_PARENT);
+	clks[VIDEO_PLL_BYPASS] = thead_light_clk_mux_flags("video_pll_bypass", ap_base + 0x34, 30, 1, video_pll_bypass_sels, ARRAY_SIZE(video_pll_bypass_sels), CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT);
-	clks[TEE_PLL_BYPASS] = thead_light_clk_mux_flags("tee_pll_bypass", ap_base + 0x64, 30, 1, tee_pll_bypass_sels, ARRAY_SIZE(tee_pll_bypass_sels), CLK_SET_RATE_PARENT);
+	clks[TEE_PLL_BYPASS] = thead_light_clk_mux_flags("tee_pll_bypass", ap_base + 0x64, 30, 1, tee_pll_bypass_sels, ARRAY_SIZE(tee_pll_bypass_sels), CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT);
-	clks[DPU0_PLL_BYPASS] = thead_light_clk_mux_flags("dpu0_pll_bypass", ap_base + 0x44, 30, 1, dpu0_pll_bypass_sels, ARRAY_SIZE(dpu0_pll_bypass_sels), CLK_SET_RATE_PARENT);
+	clks[DPU0_PLL_BYPASS] = thead_light_clk_mux_flags("dpu0_pll_bypass", ap_base + 0x44, 30, 1, dpu0_pll_bypass_sels, ARRAY_SIZE(dpu0_pll_bypass_sels), CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT);
-	clks[DPU1_PLL_BYPASS] = thead_light_clk_mux_flags("dpu1_pll_bypass", ap_base + 0x54, 30, 1, dpu1_pll_bypass_sels, ARRAY_SIZE(dpu1_pll_bypass_sels), CLK_SET_RATE_PARENT);
+	clks[DPU1_PLL_BYPASS] = thead_light_clk_mux_flags("dpu1_pll_bypass", ap_base + 0x54, 30, 1, dpu1_pll_bypass_sels, ARRAY_SIZE(dpu1_pll_bypass_sels), CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT);
 
-	clks[AHB2_CPUSYS_HCLK] = thead_light_clk_mux_flags("ahb2_cpusys_hclk", ap_base + 0x120, 5, 1, ahb2_cpusys_hclk_sels, ARRAY_SIZE(ahb2_cpusys_hclk_sels), CLK_SET_RATE_PARENT);
+	clks[AHB2_CPUSYS_HCLK] = thead_light_clk_mux_flags("ahb2_cpusys_hclk", ap_base + 0x120, 5, 1, ahb2_cpusys_hclk_sels, ARRAY_SIZE(ahb2_cpusys_hclk_sels), CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT);
-	clks[C910_CCLK_I0] = thead_light_clk_mux_flags("c910_cclk_i0", ap_base + 0x100, 1, 1, c910_cclk_i0_sels, ARRAY_SIZE(c910_cclk_i0_sels), CLK_SET_RATE_PARENT);
+	clks[C910_CCLK_I0] = thead_light_clk_mux_flags("c910_cclk_i0", ap_base + 0x100, 1, 1, c910_cclk_i0_sels, ARRAY_SIZE(c910_cclk_i0_sels), CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT);
-	clks[C910_CCLK] = thead_light_clk_mux_flags("c910_cclk", ap_base + 0x100, 0, 1, c910_cclk_sels, ARRAY_SIZE(c910_cclk_sels), CLK_SET_RATE_PARENT);
+	clks[C910_CCLK] = thead_light_clk_mux_flags("c910_cclk", ap_base + 0x100, 0, 1, c910_cclk_sels, ARRAY_SIZE(c910_cclk_sels), CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT);
-	clks[CFG_AXI_ACLK] = thead_light_clk_mux_flags("cfg_axi_aclk", ap_base + 0x138, 5, 1, cfg_axi_aclk_sels, ARRAY_SIZE(cfg_axi_aclk_sels), CLK_SET_RATE_PARENT);
+	clks[CFG_AXI_ACLK] = thead_light_clk_mux_flags("cfg_axi_aclk", ap_base + 0x138, 5, 1, cfg_axi_aclk_sels, ARRAY_SIZE(cfg_axi_aclk_sels), CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT);
 
 	if (teesys)
-		clks[TEESYS_HCLK] = thead_light_clk_mux_flags("teesys_hclk", ap_base + 0x1cc, 13, 1, teesys_hclk_sels, ARRAY_SIZE(teesys_hclk_sels), CLK_SET_RATE_PARENT); //just for teesys!!!
+		clks[TEESYS_HCLK] = thead_light_clk_mux_flags("teesys_hclk", ap_base + 0x1cc, 13, 1, teesys_hclk_sels, ARRAY_SIZE(teesys_hclk_sels), CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT); //just for teesys!!!
 
-	clks[PERISYS_AHB_HCLK] = thead_light_clk_mux_flags("perisys_ahb_hclk", ap_base + 0x140, 5, 1, perisys_ahb_hclk_sels, ARRAY_SIZE(perisys_ahb_hclk_sels), CLK_SET_RATE_PARENT);
+	clks[PERISYS_AHB_HCLK] = thead_light_clk_mux_flags("perisys_ahb_hclk", ap_base + 0x140, 5, 1, perisys_ahb_hclk_sels, ARRAY_SIZE(perisys_ahb_hclk_sels), CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT);
-	clks[CLK_OUT_1] = thead_light_clk_mux_flags("clk_out_1", ap_base + 0x1b4, 4, 1, clk_out_1_sels, ARRAY_SIZE(clk_out_1_sels), CLK_SET_RATE_PARENT);
+	clks[CLK_OUT_1] = thead_light_clk_mux_flags("clk_out_1", ap_base + 0x1b4, 4, 1, clk_out_1_sels, ARRAY_SIZE(clk_out_1_sels), CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT);
-	clks[CLK_OUT_2] = thead_light_clk_mux_flags("clk_out_2", ap_base + 0x1b8, 4, 1, clk_out_2_sels, ARRAY_SIZE(clk_out_2_sels), CLK_SET_RATE_PARENT);
+	clks[CLK_OUT_2] = thead_light_clk_mux_flags("clk_out_2", ap_base + 0x1b8, 4, 1, clk_out_2_sels, ARRAY_SIZE(clk_out_2_sels), CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT);
-	clks[CLK_OUT_3] = thead_light_clk_mux_flags("clk_out_3", ap_base + 0x1bc, 4, 1, clk_out_3_sels, ARRAY_SIZE(clk_out_3_sels), CLK_SET_RATE_PARENT);
+	clks[CLK_OUT_3] = thead_light_clk_mux_flags("clk_out_3", ap_base + 0x1bc, 4, 1, clk_out_3_sels, ARRAY_SIZE(clk_out_3_sels), CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT);
-	clks[CLK_OUT_4] = thead_light_clk_mux_flags("clk_out_4", ap_base + 0x1c0, 4, 1, clk_out_4_sels, ARRAY_SIZE(clk_out_4_sels), CLK_SET_RATE_PARENT);
+	clks[CLK_OUT_4] = thead_light_clk_mux_flags("clk_out_4", ap_base + 0x1c0, 4, 1, clk_out_4_sels, ARRAY_SIZE(clk_out_4_sels), CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT);
-	clks[PERI_I2S_SRC_CLK] = thead_light_clk_mux_flags("peri_i2s_src_clk", ap_base + 0x1f0, 0, 1, peri_i2s_src_clk_sels, ARRAY_SIZE(peri_i2s_src_clk_sels), CLK_SET_RATE_PARENT);
+	clks[PERI_I2S_SRC_CLK] = thead_light_clk_mux_flags("peri_i2s_src_clk", ap_base + 0x1f0, 0, 1, peri_i2s_src_clk_sels, ARRAY_SIZE(peri_i2s_src_clk_sels), CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT);
 	clks[NPU_CCLK] = thead_light_clk_mux_flags("npu_cclk", ap_base + 0x1c8, 6, 1, npu_cclk_sels, ARRAY_SIZE(npu_cclk_sels), CLK_SET_RATE_PARENT);
-	clks[CFG_APB_PCLK] = thead_light_clk_mux_flags("cfg_apb_pclk", ap_base + 0x1c4, 7, 1, cfg_apb_pclk_sels, ARRAY_SIZE(cfg_apb_pclk_sels), CLK_SET_RATE_PARENT);
+	clks[CFG_APB_PCLK] = thead_light_clk_mux_flags("cfg_apb_pclk", ap_base + 0x1c4, 7, 1, cfg_apb_pclk_sels, ARRAY_SIZE(cfg_apb_pclk_sels), CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT);
-	clks[UART_SCLK] = thead_light_clk_mux_flags("uart_sclk", ap_base + 0x210, 0, 1, uart_sclk_sels, ARRAY_SIZE(uart_sclk_sels), CLK_SET_RATE_PARENT);
+	clks[UART_SCLK] = thead_light_clk_mux_flags("uart_sclk", ap_base + 0x210, 0, 1, uart_sclk_sels, ARRAY_SIZE(uart_sclk_sels), CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT);
 
 	/* Light Fullmask AP Divider */
 	clks[AHB2_CPUSYS_HCLK_OUT_DIV] = thead_clk_light_divider("ahb2_cpusys_hclk_out_div", "gmac_pll_fout1ph0", ap_base + 0x120, 0, 3, 4, MUX_TYPE_DIV, 2, 7);
@@ -436,7 +437,7 @@ static int light_clocks_probe(struct platform_device *pdev)
 	/* Light Fullmask PLL FOUT */
 	clks[GMAC_PLL_FOUT1PH0] = thead_light_clk_fixed_factor("gmac_pll_fout1ph0", "gmac_pll_bypass", 1, 2);
 	clks[GMAC_PLL_FOUT4] = thead_light_clk_fixed_factor("gmac_pll_fout4", "gmac_pll_bypass", 1, 8);
-	clks[VIDEO_PLL_FOUT1PH0] = thead_light_clk_fixed_factor("video_pll_fout1ph0", "video_pll_bybass", 1, 2);
+	clks[VIDEO_PLL_FOUT1PH0] = thead_light_clk_fixed_factor("video_pll_fout1ph0", "video_pll_bypass", 1, 2);
 	clks[VIDEO_PLL_FOUT4] = thead_light_clk_fixed_factor("video_pll_fout4", "video_pll_bypass", 1, 8);
 	clks[TEE_PLL_FOUT4] = thead_light_clk_fixed_factor("tee_pll_fout4", "tee_pll_bypass", 1, 8);
 	clks[CPU_PLL0_FOUT4] = thead_light_clk_fixed_factor("cpu_pll0_fout4", "cpu_pll0_bypass", 1, 8);
@@ -450,7 +451,7 @@ static int light_clocks_probe(struct platform_device *pdev)
 	clks[QSPI0_SSI_CLK] = thead_light_clk_fixed_factor("qspi0_ssi_clk", "qspi_ssi_clk", 1, 1);
 	clks[QSPI1_SSI_CLK] = thead_light_clk_fixed_factor("qspi1_ssi_clk", "video_pll_fout1ph0", 1, 1);
 	clks[SPI_SSI_CLK] = thead_light_clk_fixed_factor("spi_ssi_clk", "video_pll_fout1ph0", 1, 1);
-	clks[EMMC_SDIO_REF_CLK] = thead_light_clk_fixed_factor("emmc_sdio_ref_clk", "video_pll_foutpostdiv", 1, 1);	/* Note: no mux to select, use default value */
+	clks[EMMC_SDIO_REF_CLK] = thead_light_clk_fixed_factor("emmc_sdio_ref_clk", "video_pll_foutpostdiv", 1, 4);	/* Note: base clk is div 4 to 198M*/
 	clks[PWM_CCLK] = thead_light_clk_fixed_factor("pwm_cclk", "osc_24m", 1, 1);
 	clks[CHIP_DBG_CCLK] = thead_light_clk_fixed_factor("chip_dbg_cclk", "osc_24m", 1, 1);
 	clks[GMAC_CCLK] = thead_light_clk_fixed_factor("gmac_cclk", "gmac_pll_fout1ph0", 1, 1);
@@ -568,8 +569,8 @@ static int light_clocks_probe(struct platform_device *pdev)
 	clks[CLKGEN_UART2_SCLK] = thead_clk_light_gate_shared("clkgen_uart2_sclk", "uart_sclk", ap_base + 0x204, 12, &share_cnt_uart2_clk_en);
 	clks[CLKGEN_I2C2_PCLK] = thead_clk_light_gate_shared("clkgen_i2c2_pclk", "perisys_apb_pclk", ap_base + 0x204, 3, &share_cnt_i2c2_clk_en);
 	clks[CLKGEN_I2C2_IC_CLK] = thead_clk_light_gate_shared("clkgen_i2c2_ic_clk", "i2c_ic_clk", ap_base + 0x204, 3, &share_cnt_i2c2_clk_en);
-	clks[CLKGEN_I2C3_PCLK] = thead_clk_light_gate_shared("clkgen_i2c3_pclk", "perisys_apb_pclk", ap_base + 0x204, 2, &share_cnt_i2c2_clk_en);
+	clks[CLKGEN_I2C3_PCLK] = thead_clk_light_gate_shared("clkgen_i2c3_pclk", "perisys_apb_pclk", ap_base + 0x204, 2, &share_cnt_i2c3_clk_en);
-	clks[CLKGEN_I2C3_IC_CLK] = thead_clk_light_gate_shared("clkgen_i2c3_ic_clk", "i2c_ic_clk", ap_base + 0x204, 2, &share_cnt_i2c2_clk_en);
+	clks[CLKGEN_I2C3_IC_CLK] = thead_clk_light_gate_shared("clkgen_i2c3_ic_clk", "i2c_ic_clk", ap_base + 0x204, 2, &share_cnt_i2c3_clk_en);
 	clks[CLKGEN_I2S_PCLK] = thead_clk_light_gate_shared("clkgen_i2s_pclk", "perisys_apb_pclk", ap_base + 0x1f0, 1, &share_cnt_peri_i2s_clk_en);
 	clks[CLKGEN_I2S_SRC_CLK] = thead_clk_light_gate_shared("clkgen_i2s_src_clk", "peri_i2s_src_clk", ap_base + 0x1f0, 1, &share_cnt_peri_i2s_clk_en);
 	clks[CLKGEN_QSPI1_PCLK] = thead_clk_light_gate_shared("clkgen_qspi1_pclk", "peri2sys_apb_pclk", ap_base + 0x204, 16, &share_cnt_qspi1_clk_en);
@@ -608,8 +609,6 @@ static int light_clocks_probe(struct platform_device *pdev)
 
 #ifndef FPGA_EMU
 	/* HW defalut */
-	clk_prepare_enable(clks[CPU_PLL1_FOUTPOSTDIV]);
-	udelay(1);
 	clk_set_parent(clks[C910_CCLK], clks[CPU_PLL1_FOUTPOSTDIV]);
 #else
 	clk_set_parent(clks[C910_CCLK_I0], clks[OSC_24M]);