configs: fix load dtb name

Signed-off-by: Han Gao <gaohan@iscas.ac.cn>

.github/workflows/build.yml

@@ -12,10 +12,10 @@ on:
     - cron: "0 2 * * *"
 
 env:
-  xuantie_toolchain: https://occ-oss-prod.oss-cn-hangzhou.aliyuncs.com/resource//1698113812618
-  toolchain_file_name: Xuantie-900-gcc-linux-5.10.4-glibc-x86_64-V2.8.0-20231018.tar.gz
-  mainline_toolchain: https://github.com/riscv-collab/riscv-gnu-toolchain/releases/download/2023.10.18
-  mainline_toolchain_file_name: riscv64-glibc-ubuntu-22.04-gcc-nightly-2023.10.18-nightly.tar.gz
+  xuantie_toolchain: https://occ-oss-prod.oss-cn-hangzhou.aliyuncs.com/resource//1705395627867
+  toolchain_file_name: Xuantie-900-gcc-linux-5.10.4-glibc-x86_64-V2.8.1-20240115.tar.gz
+  mainline_toolchain: https://github.com/riscv-collab/riscv-gnu-toolchain/releases/download/2024.04.12
+  mainline_toolchain_file_name: riscv64-glibc-ubuntu-22.04-gcc-nightly-2024.04.12-nightly.tar.gz
   wget_alias: 'wget --retry-connrefused --waitretry=1 --read-timeout=20 --timeout=15 -t 0'
   ARCH: riscv
   CROSS_COMPILE: riscv64-unknown-linux-gnu-
@@ -46,7 +46,7 @@ jobs:
               if [[ ${{ matrix.name }} = "thead-gcc" ]]; then
                 ${wget_alias} ${xuantie_toolchain}/${toolchain_file_name}
                 tar -xvf ${toolchain_file_name} -C /opt
-                export PATH="/opt/Xuantie-900-gcc-linux-5.10.4-glibc-x86_64-V2.8.0/bin:$PATH"
+                export PATH="/opt/Xuantie-900-gcc-linux-5.10.4-glibc-x86_64-V2.8.1/bin:$PATH"
               else
                 ${wget_alias} ${mainline_toolchain}/${mainline_toolchain_file_name}
                 tar -xvf ${mainline_toolchain_file_name} -C /opt
@@ -94,6 +94,10 @@ jobs:
                 make light_milkv_meles_singlerank_defconfig
                 make -j$(nproc)
                 find . -name "u-boot-with-spl.bin" | xargs -I{} cp -av {} ${GITHUB_WORKSPACE}/output/u-boot-with-spl-meles-4g.bin
+                make clean
+                make light_huiwei_defconfig
+                make -j$(nproc)
+                find . -name "u-boot-with-spl.bin" | xargs -I{} cp -av {} ${GITHUB_WORKSPACE}/output/u-boot-with-spl-huiwei.bin
 
                 # mainline support
                 make clean

Makefile

@@ -757,6 +757,8 @@ libs-y += drivers/net/phy/
 libs-y += drivers/power/ \
 	drivers/power/domain/ \
 	drivers/power/fuel_gauge/ \
+	drivers/power/charge/ \
+	drivers/mcu/ \
 	drivers/power/mfd/ \
 	drivers/power/pmic/ \
 	drivers/power/battery/ \

arch/riscv/cpu/c9xx/dram.c

@@ -14,9 +14,9 @@ DECLARE_GLOBAL_DATA_PTR;
 int dram_init(void)
 {
 #ifdef CONFIG_DDR_BOARD_CONFIG
-extern unsigned long get_ddr_density(void);
-	// update ram_size from board config info
-	gd->ram_size = get_ddr_density();
+	// already setup during ddr initial flow
+	gd->bd->bi_memsize = gd->ram_size;
+	gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
 	return 0;
 #else
 	return fdtdec_setup_mem_size_base();

arch/riscv/cpu/cpu.c

@@ -27,6 +27,15 @@ u32 hart_lottery __attribute__((section(".data"))) = 0;
 u32 available_harts_lock = 1;
 #endif
 
+void arch_setup_gd(struct global_data *gd_ptr)
+{
+	// sync specific info from spl
+	gd_ptr->ram_size = gd->ram_size;
+
+	// setup gd ptr
+	gd = gd_ptr;
+}
+
 static inline bool supports_extension(char ext)
 {
 #ifdef CONFIG_CPU

arch/riscv/cpu/start.S

@@ -104,12 +104,6 @@ call_board_init_f_0:
 	mv	a0, sp
 	jal	board_init_f_alloc_reserve
 
-	/*
-	 * Set global data pointer here for all harts, uninitialized at this
-	 * point.
-	 */
-	mv	gp, a0
-
 	/* setup stack */
 #ifdef CONFIG_SMP
 	/* tp: hart id */
@@ -127,16 +121,34 @@ call_board_init_f_0:
 	la	t0, hart_lottery
 	li	s2, 1
 	amoswap.w s2, t1, 0(t0)
-	bnez	s2, wait_for_gd_init
+	beqz	s2, call_board_init_f_1
+
+	/*
+	 * Set global data pointer here for secondary harts, uninitialized at this
+	 * point.
+	 */
+	mv	gp, a0
+
+	jal wait_for_gd_init
 #else
-	bnez	tp, secondary_hart_loop
+	beqz	tp, call_board_init_f_1
+
+	/*
+	 * Set global data pointer here for secondary harts, uninitialized at this
+	 * point.
+	 */
+	mv	gp, a0
+
+	jal secondary_hart_loop
 #endif
 
+call_board_init_f_1:
 #ifdef CONFIG_OF_PRIOR_STAGE
 	la	t0, prior_stage_fdt_address
 	SREG	s1, 0(t0)
 #endif
 
+	 /* Set global data pointer here for main hart */
 	jal	board_init_f_init_reserve
 
 	/* save the boot hart id to global_data */

arch/riscv/dts/Makefile

@@ -7,6 +7,7 @@ dtb-$(CONFIG_TARGET_LIGHT_EVB_MPW_C910) += light-evb-mpw-c910.dtb
 dtb-$(CONFIG_TARGET_LIGHT_FPGA_FM_C910) += light-fpga-fm-c910.dtb
 dtb-$(CONFIG_TARGET_LIGHT_C910) += light-a-ref.dtb light-b-ref.dtb light-a-val.dtb light-b-product.dtb light-a-product.dtb light-ant-ref.dtb light-beagle.dtb light-b-power.dtb light-lpi4a.dtb light-milkv-meles.dtb
 dtb-$(CONFIG_TARGET_LIGHT_C910) += light-lpi4a-laptop.dtb
+dtb-$(CONFIG_TARGET_LIGHT_C910) += light-huiwei.dtb
 
 targets += $(dtb-y)
 

arch/riscv/dts/light-a-val.dts

@@ -1,4 +1,7 @@
 /dts-v1/;
+
+#include <dt-bindings/pmic/light_pmic.h>
+
 / {
 	model = "T-HEAD c910 light";
 	compatible = "thead,c910_light";
@@ -359,6 +362,20 @@
 			};
 		};
 
+		usb: usb@ffe7040000 {
+			compatible = "snps,dwc3";
+			reg = <0xff 0xe7040000 0x0 0x10000>;
+			interrupts = <68>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			maximum-speed = "super-speed";
+			dr_mode = "host";
+			dma-mask = <0xf 0xffffffff>;
+			snps,usb3_lpm_capable;
+			snps,usb_sofitpsync;
+			status = "okay";
+		};
+
 		pwm: pwm@ffec01c000 {
 			compatible = "thead,pwm-light";
 			reg = <0xff 0xec01c000 0x0 0x4000>;
@@ -479,6 +496,429 @@
 			lcd-en-gpios    = <&pcal6408ahk_a 2 0>; /* active high */
 			lcd-bias-en-gpios = <&pcal6408ahk_a 4 0>;/* active high */
 		};
+
+		aon {
+		compatible = "thead,light-aon";
+		status = "okay";
+
+		wakeup-by-gpio-on;
+		wakeup-by-rtc-on;
+
+		pd: light-aon-pd {
+			compatible = "thead,light-aon-pd";
+			#power-domain-cells = <1>;
+		};
+
+		light-regu-reg {
+			compatible = "thead,light-dialog-pmic";
+			status = "okay";
+
+			soc_dvdd18_aon_reg: soc_dvdd18_aon {
+				regulator-name = "soc_dvdd18_aon";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_avdd33_usb3_reg: soc_avdd33_usb3 {
+				regulator-name = "soc_avdd33_usb3";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_dvdd08_aon_reg: soc_dvdd08_aon {
+				regulator-name = "soc_dvdd08_aon";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_apcpu_dvdd_dvddm_reg: soc_apcpu_dvdd_dvddm {
+				regulator-name = "soc_apcpu_dvdd_dvddm";
+				regulator-min-microvolt = <300000>;
+				regulator-max-microvolt = <1570000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_dvdd08_ddr_reg: soc_dvdd08_ddr {
+				regulator-name = "soc_dvdd08_ddr";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_vdd_ddr_1v8_reg: soc_vdd_ddr_1v8 {
+				regulator-name = "soc_vdd_ddr_1v8";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_vdd_ddr_1v1_reg: soc_vdd_ddr_1v1 {
+				regulator-name = "soc_vdd_ddr_1v1";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_vdd_ddr_0v6_reg: soc_vdd_ddr_0v6 {
+				regulator-name = "soc_vdd_ddr_0v6";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_dvdd18_ap_reg: soc_dvdd18_ap {
+				regulator-name = "soc_dvdd18_ap";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_dvdd08_ap_reg: soc_dvdd08_ap {
+				regulator-name = "soc_dvdd08_ap";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_avdd08_mipi_hdmi_reg: soc_avdd08_mipi_hdmi {
+				regulator-name = "soc_avdd08_mipi_hdmi";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_avdd18_mipi_hdmi_reg: soc_avdd18_mipi_hdmi {
+				regulator-name = "soc_avdd18_mipi_hdmi";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_dvdd33_emmc_reg: soc_dvdd33_emmc {
+				regulator-name = "soc_dvdd33_emmc";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_dvdd18_emmc_reg: soc_dvdd18_emmc {
+				regulator-name = "soc_vdd18_emmc";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+			soc_dovdd18_scan_reg: soc_dovdd18_scan {
+				regulator-name = "soc_dovdd18_scan";
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <3600000>;
+			};
+			soc_vext_2v8_reg: soc_vext_2v8 {
+				regulator-name = "soc_vext_2v8";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+			soc_dvdd12_scan_reg: soc_dvdd12_scan {
+				regulator-name = "soc_dvdd12_scan";
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <3600000>;
+			};
+			soc_avdd28_scan_en_reg: soc_avdd28_scan_en {
+				regulator-name = "soc_avdd28_scan_en";
+				regulator-min-microvolt = <2800000>;
+				regulator-max-microvolt = <2800000>;
+			};
+			soc_avdd28_rgb_reg: soc_avdd28_rgb {
+				regulator-name = "soc_avdd28_rgb";
+				regulator-min-microvolt = <2200000>;
+				regulator-max-microvolt = <3475000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+			soc_dovdd18_rgb_reg: soc_dovdd18_rgb {
+				regulator-name = "soc_dovdd18_rgb";
+				regulator-min-microvolt = <1200000>;
+				regulator-max-microvolt = <3600000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+			soc_dvdd12_rgb_reg: soc_dvdd12_rgb {
+				regulator-name = "soc_dvdd12_rgb";
+				regulator-min-microvolt = <400000>;
+				regulator-max-microvolt = <1675000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+			soc_avdd25_ir_reg: soc_avdd25_ir {
+				regulator-name = "soc_avdd25_ir";
+				regulator-min-microvolt = <2200000>;
+				regulator-max-microvolt = <3475000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+			soc_dovdd18_ir_reg: soc_dovdd18_ir {
+				regulator-name = "soc_dovdd18_ir";
+				regulator-min-microvolt = <1200000>;
+				regulator-max-microvolt = <3600000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+			soc_dvdd12_ir_reg: soc_dvdd12_ir {
+				regulator-name = "soc_dvdd12_ir";
+				regulator-min-microvolt = <400000>;
+				regulator-max-microvolt = <1675000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+	   };
+
+	    aon_pmic_config {
+			compatible = "thead,light-pmic-conf";
+			status = "okay";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			iic-config = <0 0 2>;
+			pmic_dev_0: pmic-dev@0 {
+			  pmic-name = "dialog,da9063,v1";
+			  pmic-addr = <0x5a 0x5b>;
+			  pmic_wdt_on;
+			  errio_gpio = <0 14 3>;
+			  status = "okay";
+			};
+
+			pmic_dev_1: pmic-dev@1 {
+			  pmic-name = "dialog,da9121,v1";
+			  pmic-addr = <0x68>;
+			  status = "okay";
+			};
+
+			pmic_dev_2: pmic-dev@2 {
+			  pmic-name = "dialog,slg51000,v1";
+			  pmic-addr = <0x75>;
+			  status = "okay";
+			};
+
+			regu_config_0 {
+                reg_info = <&soc_dvdd18_aon_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_0 DA9063_ID_LDO3>;
+				};
+			};
+
+			regu_config_1 {
+                reg_info = <&soc_avdd33_usb3_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_0 DA9063_ID_LDO9>;
+				};
+			};
+
+			regu_config_2 {
+                reg_info = <&soc_dvdd08_aon_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_0 DA9063_ID_LDO2>;
+				};
+			};
+
+			regu_config_3 {
+                reg_info = <&soc_apcpu_dvdd_dvddm_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_0 DA9063_ID_BCORE1>;
+					auto_on_info = <0 0 800000>;
+				};
+
+				regu_id@1 {
+                    pmic_dev = <&pmic_dev_0 DA9063_ID_BCORE2>;
+					auto_on_info = <1 0 800000>;
+				};
+
+				coupling_info@0 {
+					negative-min;
+                    info = <0 1 5 30>;
+				};
+			};
+
+			regu_config_4 {
+                reg_info = <&soc_dvdd08_ddr_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_0 DA9063_ID_BUCKPERI>;
+				};
+			};
+
+			regu_config_5 {
+                reg_info = <&soc_vdd_ddr_1v8_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_0 DA9063_ID_LDO4>;
+				};
+			};
+
+		    regu_config_6 {
+                reg_info = <&soc_vdd_ddr_1v1_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_0 DA9063_ID_BUCKMEM>;
+				};
+				regu_id@1 {
+                    pmic_dev = <&pmic_dev_0 DA9063_ID_BUCKIO>;
+				};
+
+			};
+
+			regu_config_7 {
+                reg_info = <&soc_vdd_ddr_0v6_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_0 DA9063_ID_BUCKPRO>;
+				};
+			};
+
+			regu_config_8 {
+                reg_info = <&soc_dvdd18_ap_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_0 DA9063_ID_LDO11>;
+				};
+			};
+
+            regu_config_9 {
+                reg_info = <&soc_avdd08_mipi_hdmi_reg>;
+				status = "okay";
+				regu_id@0 {
+					pmic_dev = <&pmic_dev_0 DA9063_ID_LDO1>;
+				};
+			};
+
+			regu_config_10 {
+                reg_info = <&soc_avdd18_mipi_hdmi_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_0 DA9063_ID_LDO5>;
+				};
+			};
+
+			regu_config_11 {
+                reg_info = <&soc_dvdd33_emmc_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_0 DA9063_ID_LDO10>;
+				};
+			};
+
+			regu_config_12 {
+                reg_info = <&soc_dovdd18_scan_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_0 DA9063_ID_LDO6>;
+					auto_on_info = <2 1 1800000>;
+					auto_off_info = <7 1>;
+				};
+			};
+
+			regu_config_13 {
+                reg_info = <&soc_vext_2v8_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_0 DA9063_ID_LDO7>;
+					auto_on_info = <3 1 2800000>;
+					auto_off_info = <8 1>;
+				};
+			};
+
+			regu_config_14 {
+                reg_info = <&soc_dvdd12_scan_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_0 DA9063_ID_LDO8>;
+					auto_on_info = <4 1 1200000>;
+					auto_off_info = <9 1>;
+				};
+			};
+
+			regu_config_15 {
+                reg_info = <&soc_avdd28_scan_en_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_0 DA9063_ID_GPIO4>;
+					auto_on_info = <5 1 2800000>;
+					auto_off_info = <6 1>;
+				};
+			};
+
+			regu_config_16 {
+                reg_info = <&soc_dvdd08_ap_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_1 DA9121_ID_BUCK1>;
+                    parent_pmic_dev = <&pmic_dev_0 2 0>;
+				};
+			};
+
+			regu_config_17 {
+                reg_info = <&soc_avdd28_rgb_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_2 SLG51000_ID_LDO1>;
+                    auto_on_info = <6 0 2800000>;
+					auto_off_info = <0 1>;
+				};
+			};
+
+			regu_config_18 {
+                reg_info = <&soc_avdd25_ir_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_2 SLG51000_ID_LDO2>;
+                    auto_on_info = <7 0 2500000>;
+					auto_off_info = <1 1>;
+				};
+			};
+
+			regu_config_19 {
+                reg_info = <&soc_dvdd18_emmc_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_2 SLG51000_ID_LDO3>;
+					parent_pmic_dev = <&pmic_dev_0 7 0>;
+				};
+			};
+
+			regu_config_20 {
+                reg_info = <&soc_dovdd18_rgb_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_2 SLG51000_ID_LDO4>;
+				    auto_on_info = <8 0 1800000>;
+					auto_off_info = <2 1>;
+				};
+			};
+
+			regu_config_21 {
+                reg_info = <&soc_dvdd12_rgb_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_2 SLG51000_ID_LDO5>;
+				    auto_on_info = <9 0 1200000>;
+					auto_off_info = <3 1>;
+				};
+			};
+
+			regu_config_22 {
+                reg_info = <&soc_dvdd12_ir_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_2 SLG51000_ID_LDO6>;
+				    auto_on_info = <10 0 1200000>;
+					auto_off_info = <4 1>;
+				};
+			};
+
+			 regu_config_23 {
+                reg_info = <&soc_dovdd18_ir_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_2 SLG51000_ID_LDO7>;
+				    auto_on_info = <11 0 1800000>;
+					auto_off_info = <5 1>;
+				};
+			};
+		};
+	};
+
 	};
 
 	chosen {

arch/riscv/dts/light-b-product.dts

@@ -1,4 +1,7 @@
 /dts-v1/;
+
+#include <dt-bindings/pmic/light_pmic.h>
+
 / {
 	model = "T-HEAD c910 light";
 	compatible = "thead,c910_light";
@@ -469,6 +472,362 @@
 			lcd-en-gpios    = <&gpio1_porta 9 0>; /* active high */
 			lcd-bias-en-gpios = <&gpio1_porta 10 0>;/* active high */
 		};
+
+		aon {
+		compatible = "thead,light-aon";
+		status = "okay";
+
+		wakeup-by-gpio-on;
+		wakeup-by-rtc-on;
+
+		pd: light-aon-pd {
+			compatible = "thead,light-aon-pd";
+			#power-domain-cells = <1>;
+		};
+
+		light-regu-reg {
+			compatible = "thead,light-dialog-pmic";
+			status = "okay";
+
+
+
+			soc_dvdd18_aon_reg: soc_dvdd18_aon {
+				regulator-name = "soc_dvdd18_aon";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_avdd33_usb3_reg: soc_avdd33_usb3 {
+				regulator-name = "soc_avdd33_usb3";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_dvdd08_aon_reg: soc_dvdd08_aon {
+				regulator-name = "soc_dvdd08_aon";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_apcpu_dvdd_dvddm_reg: soc_apcpu_dvdd_dvddm {
+				regulator-name = "soc_apcpu_dvdd_dvddm";
+				regulator-min-microvolt = <300000>;
+				regulator-max-microvolt = <1570000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_dvdd08_ddr_reg: soc_dvdd08_ddr {
+				regulator-name = "soc_dvdd08_ddr";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_vdd_ddr_1v8_reg: soc_vdd_ddr_1v8 {
+				regulator-name = "soc_vdd_ddr_1v8";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_vdd_ddr_1v1_reg: soc_vdd_ddr_1v1 {
+				regulator-name = "soc_vdd_ddr_1v1";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_vdd_ddr_0v6_reg: soc_vdd_ddr_0v6 {
+				regulator-name = "soc_vdd_ddr_0v6";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_dvdd18_ap_reg: soc_dvdd18_ap {
+				regulator-name = "soc_dvdd18_ap";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_dvdd08_ap_reg: soc_dvdd08_ap {
+				regulator-name = "soc_dvdd08_ap";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_avdd08_mipi_hdmi_reg: soc_avdd08_mipi_hdmi {
+				regulator-name = "soc_avdd08_mipi_hdmi";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_avdd18_mipi_hdmi_reg: soc_avdd18_mipi_hdmi {
+				regulator-name = "soc_avdd18_mipi_hdmi";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_dvdd33_emmc_reg: soc_dvdd33_emmc {
+				regulator-name = "soc_dvdd33_emmc";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_dvdd18_emmc_reg: soc_dvdd18_emmc {
+				regulator-name = "soc_vdd18_emmc";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+			soc_dovdd18_scan_reg: soc_dovdd18_scan {
+				regulator-name = "soc_dovdd18_scan";
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <3600000>;
+				status = "disabled";
+			};
+			soc_vext_2v8_reg: soc_vext_2v8 {
+				regulator-name = "soc_vext_2v8";
+				regulator-boot-on;
+				regulator-always-on;
+				status = "disabled";
+			};
+			soc_dvdd12_scan_reg: soc_dvdd12_scan {
+				regulator-name = "soc_dvdd12_scan";
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <3600000>;
+				status = "disabled";
+			};
+			soc_avdd28_scan_en_reg: soc_avdd28_scan_en {
+				regulator-name = "soc_avdd28_scan_en";
+				regulator-min-microvolt = <2800000>;
+				regulator-max-microvolt = <2800000>;
+				status = "disabled";
+			};
+			soc_avdd28_rgb_reg: soc_avdd28_rgb {
+				regulator-name = "soc_avdd28_rgb";
+				regulator-min-microvolt = <2200000>;
+				regulator-max-microvolt = <3475000>;
+				regulator-boot-on;
+				regulator-always-on;
+				status = "disabled";
+			};
+			soc_dovdd18_rgb_reg: soc_dovdd18_rgb {
+				regulator-name = "soc_dovdd18_rgb";
+				regulator-min-microvolt = <1200000>;
+				regulator-max-microvolt = <3600000>;
+				regulator-boot-on;
+				regulator-always-on;
+				status = "disabled";
+			};
+			soc_dvdd12_rgb_reg: soc_dvdd12_rgb {
+				regulator-name = "soc_dvdd12_rgb";
+				regulator-min-microvolt = <400000>;
+				regulator-max-microvolt = <1675000>;
+				regulator-boot-on;
+				regulator-always-on;
+				status = "disabled";
+			};
+			soc_avdd25_ir_reg: soc_avdd25_ir {
+				regulator-name = "soc_avdd25_ir";
+				regulator-min-microvolt = <2200000>;
+				regulator-max-microvolt = <3475000>;
+				regulator-boot-on;
+				regulator-always-on;
+				status = "disabled";
+			};
+			soc_dovdd18_ir_reg: soc_dovdd18_ir {
+				regulator-name = "soc_dovdd18_ir";
+				regulator-min-microvolt = <1200000>;
+				regulator-max-microvolt = <3600000>;
+				regulator-boot-on;
+				regulator-always-on;
+				status = "disabled";
+			};
+			soc_dvdd12_ir_reg: soc_dvdd12_ir {
+				regulator-name = "soc_dvdd12_ir";
+				regulator-min-microvolt = <400000>;
+				regulator-max-microvolt = <1675000>;
+				regulator-boot-on;
+				regulator-always-on;
+				status = "disabled";
+			};
+			soc_adc_vref_reg: soc_adc_vref {
+				regulator-name = "soc_adc_vref";
+			};
+			soc_lcd0_en_reg: soc_lcd0_en {
+				regulator-name = "soc_lcd0_en";
+			};
+			soc_vext_1v8_reg: soc_vext_1v8 {
+				regulator-name = "soc_vext_1v8";
+			};
+	   };
+
+	    aon_pmic_config {
+			compatible = "thead,light-pmic-conf";
+			status = "okay";
+			#address-cells = <1>;
+		    #size-cells = <0>;
+			iic-config = <0 0 2>;
+			pmic_dev_0: pmic-dev@0 {
+			  pmic-name = "ricoh,rn5t567,v0";
+			  pmic-addr = <0x31>;
+			  pmic_wdt_on;
+			  status = "okay";
+			};
+
+			pmic_dev_1: pmic-dev@1 {
+			  pmic-name = "ricoh,rn5t567,v1";
+			  pmic-addr = <0x32>;
+			  status = "okay";
+			};
+
+			regu_config_0 {
+                reg_info = <&soc_dvdd18_aon_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_0 RICOH567_ID_LDO4>;
+				};
+			};
+
+			regu_config_1 {
+                reg_info = <&soc_avdd33_usb3_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_0 RICOH567_ID_LDO1>;
+				};
+			};
+
+			regu_config_2 {
+                reg_info = <&soc_dvdd08_aon_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_0 RICOH567_ID_LDO3>;
+				};
+			};
+
+			regu_config_3 {
+                reg_info = <&soc_apcpu_dvdd_dvddm_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_0 RICOH567_ID_DC3>;
+					auto_on_info = <2 0 800000>;
+				};
+
+				regu_id@1 {
+                    pmic_dev = <&pmic_dev_0 RICOH567_ID_DC4>;
+					auto_on_info = <3 0 800000>;
+				};
+
+				coupling_info@0 {
+					negative-min;
+                    info = <0 1 5 30>;
+				};
+			};
+
+			regu_config_4 {
+                reg_info = <&soc_dvdd08_ddr_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_0 RICOH567_ID_DC1>;
+				};
+			};
+
+			regu_config_5 {
+                reg_info = <&soc_vdd_ddr_1v8_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_0 RICOH567_ID_LDO2>;
+				};
+			};
+
+		    regu_config_6 {
+                reg_info = <&soc_vdd_ddr_1v1_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_1 RICOH567_ID_DC2>;
+				};
+			};
+
+			regu_config_7 {
+                reg_info = <&soc_vdd_ddr_0v6_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_1 RICOH567_ID_DC1>;
+				};
+			};
+
+			regu_config_8 {
+                reg_info = <&soc_dvdd18_ap_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_1 RICOH567_ID_LDO2>;
+				};
+			};
+
+            regu_config_9 {
+                reg_info = <&soc_avdd08_mipi_hdmi_reg>;
+				status = "okay";
+				regu_id@0 {
+					pmic_dev = <&pmic_dev_1 RICOH567_ID_LDO3>;
+				};
+			};
+
+			regu_config_10 {
+                reg_info = <&soc_avdd18_mipi_hdmi_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_1 RICOH567_ID_LDO4>;
+				};
+			};
+
+			regu_config_11 {
+                reg_info = <&soc_dvdd33_emmc_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_1 RICOH567_ID_LDO1>;
+				};
+			};
+
+			regu_config_12 {
+                reg_info = <&soc_dvdd08_ap_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_1 RICOH567_ID_GPIO3>;
+				};
+			};
+
+			regu_config_13 {
+                reg_info = <&soc_dvdd18_emmc_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_1 RICOH567_ID_DC3>;
+				};
+			};
+
+			regu_config_14 {
+                reg_info = <&soc_adc_vref_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_1 RICOH567_ID_LDO5>;
+				};
+			};
+
+			regu_config_15 {
+                reg_info = <&soc_lcd0_en_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_0 RICOH567_ID_LDO5>;
+					auto_on_info = <0 0 1800000>;
+				};
+			};
+
+			regu_config_16 {
+                reg_info = <&soc_vext_1v8_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_1 RICOH567_ID_DC4>;
+					auto_on_info = <1 0 1800000>;
+				};
+			};
+		};
+	};
 	};
 
 	chosen {

arch/riscv/dts/light-lpi4a-laptop.dts

@@ -35,6 +35,7 @@
 };
 
 &panel0 {
+	compatible = "ilitek,ili9881c";
 	status = "okay";
 	backlight = <&lcd_backlight>;
 	// 5v power cycle

arch/riscv/dts/light-lpi4a.dts

@@ -1,4 +1,7 @@
 /dts-v1/;
+
+#include <dt-bindings/pmic/light_pmic.h>
+
 / {
 	model = "T-HEAD c910 light";
 	compatible = "thead,c910_light";
@@ -147,6 +150,13 @@
 
 			#address-cells = <1>;
 			#size-cells = <0>;
+
+			pcal6408ahk_d: gpio@20 {
+				compatible = "nxp,pca9557";
+				reg = <0x18>;
+				gpio-controller;
+				#gpio-cells = <2>;
+			};
 		};
 
 		i2c4: i2c@ffe7f28000{
@@ -157,13 +167,6 @@
 
 			#address-cells = <1>;
 			#size-cells = <0>;
-
-			pcal6408ahk_a: gpio@20 {
-				compatible = "nxp,pca9554";
-				reg = <0x20>;
-				gpio-controller;
-				#gpio-cells = <2>;
-			};
 		};
 
 		i2c5: i2c@fff7f2c000{
@@ -382,6 +385,20 @@
 			reg = <0xff 0xef600000 0x0 0x100>;
 		};
 
+		usb: usb@ffe7040000 {
+			compatible = "snps,dwc3";
+			reg = <0xff 0xe7040000 0x0 0x10000>;
+			interrupts = <68>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			maximum-speed = "super-speed";
+			dr_mode = "host";
+			dma-mask = <0xf 0xffffffff>;
+			snps,usb3_lpm_capable;
+			snps,usb_sofitpsync;
+			status = "okay";
+		};
+
 		axiscr {
 			compatible = "thead,axiscr";
 			reg = <0xff 0xff004000 0x0 0x1000>;
@@ -473,12 +490,375 @@
 		};
 
 		panel0: dsi_panel0 {
-			compatible      = "ilitek,ili9881c";
+			compatible      = "jadard,jd9365da-h3";
 			backlight       = <&lcd_backlight>;
-			reset-gpios     = <&gpio1_porta 5 1>;   /* active low  */
-			lcd-en-gpios    = <&pcal6408ahk_a 2 0>; /* active high */
-			lcd-bias-en-gpios = <&pcal6408ahk_a 4 0>;/* active high */
+			reset-gpio     = <&pcal6408ahk_d 7 0>;
+			hsvcc-gpio   = <&pcal6408ahk_d 6 1>;
+			vspn3v3-gpio = <&pcal6408ahk_d 5 1>;
 		};
+
+		aon {
+		compatible = "thead,light-aon";
+		status = "okay";
+
+		wakeup-by-gpio-on;
+		wakeup-by-rtc-on;
+
+		pd: light-aon-pd {
+			compatible = "thead,light-aon-pd";
+			#power-domain-cells = <1>;
+		};
+
+		light-regu-reg {
+			compatible = "thead,light-dialog-pmic";
+			status = "okay";
+
+
+
+			soc_dvdd18_aon_reg: soc_dvdd18_aon {
+				regulator-name = "soc_dvdd18_aon";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_avdd33_usb3_reg: soc_avdd33_usb3 {
+				regulator-name = "soc_avdd33_usb3";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_dvdd08_aon_reg: soc_dvdd08_aon {
+				regulator-name = "soc_dvdd08_aon";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_apcpu_dvdd_dvddm_reg: soc_apcpu_dvdd_dvddm {
+				regulator-name = "soc_apcpu_dvdd_dvddm";
+				regulator-min-microvolt = <300000>;
+				regulator-max-microvolt = <1570000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_dvdd08_ddr_reg: soc_dvdd08_ddr {
+				regulator-name = "soc_dvdd08_ddr";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_vdd_ddr_1v8_reg: soc_vdd_ddr_1v8 {
+				regulator-name = "soc_vdd_ddr_1v8";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_vdd_ddr_1v1_reg: soc_vdd_ddr_1v1 {
+				regulator-name = "soc_vdd_ddr_1v1";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_vdd_ddr_0v6_reg: soc_vdd_ddr_0v6 {
+				regulator-name = "soc_vdd_ddr_0v6";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_dvdd18_ap_reg: soc_dvdd18_ap {
+				regulator-name = "soc_dvdd18_ap";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_dvdd08_ap_reg: soc_dvdd08_ap {
+				regulator-name = "soc_dvdd08_ap";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_avdd08_mipi_hdmi_reg: soc_avdd08_mipi_hdmi {
+				regulator-name = "soc_avdd08_mipi_hdmi";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_avdd18_mipi_hdmi_reg: soc_avdd18_mipi_hdmi {
+				regulator-name = "soc_avdd18_mipi_hdmi";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_dvdd33_emmc_reg: soc_dvdd33_emmc {
+				regulator-name = "soc_dvdd33_emmc";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_dvdd18_emmc_reg: soc_dvdd18_emmc {
+				regulator-name = "soc_vdd18_emmc";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+			soc_dovdd18_scan_reg: soc_dovdd18_scan {
+				regulator-name = "soc_dovdd18_scan";
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <3600000>;
+			};
+			soc_vext_2v8_reg: soc_vext_2v8 {
+				regulator-name = "soc_vext_2v8";
+				regulator-boot-on;
+				regulator-always-on;
+				status = "disabled";
+			};
+			soc_dvdd12_scan_reg: soc_dvdd12_scan {
+				regulator-name = "soc_dvdd12_scan";
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <3600000>;
+			};
+			soc_avdd28_scan_en_reg: soc_avdd28_scan_en {
+				regulator-name = "soc_avdd28_scan_en";
+				regulator-min-microvolt = <2800000>;
+				regulator-max-microvolt = <2800000>;
+			};
+			soc_avdd28_rgb_reg: soc_avdd28_rgb {
+				regulator-name = "soc_avdd28_rgb";
+				regulator-min-microvolt = <2200000>;
+				regulator-max-microvolt = <3475000>;
+				regulator-boot-on;
+				regulator-always-on;
+				status = "disabled";
+			};
+			soc_dovdd18_rgb_reg: soc_dovdd18_rgb {
+				regulator-name = "soc_dovdd18_rgb";
+				regulator-min-microvolt = <1200000>;
+				regulator-max-microvolt = <3600000>;
+				regulator-boot-on;
+				regulator-always-on;
+				status = "disabled";
+			};
+			soc_dvdd12_rgb_reg: soc_dvdd12_rgb {
+				regulator-name = "soc_dvdd12_rgb";
+				regulator-min-microvolt = <400000>;
+				regulator-max-microvolt = <1675000>;
+				regulator-boot-on;
+				regulator-always-on;
+				status = "disabled";
+			};
+			soc_avdd25_ir_reg: soc_avdd25_ir {
+				regulator-name = "soc_avdd25_ir";
+				regulator-min-microvolt = <2200000>;
+				regulator-max-microvolt = <3475000>;
+				regulator-boot-on;
+				regulator-always-on;
+				status = "disabled";
+			};
+			soc_dovdd18_ir_reg: soc_dovdd18_ir {
+				regulator-name = "soc_dovdd18_ir";
+				regulator-min-microvolt = <1200000>;
+				regulator-max-microvolt = <3600000>;
+				regulator-boot-on;
+				regulator-always-on;
+				status = "disabled";
+			};
+			soc_dvdd12_ir_reg: soc_dvdd12_ir {
+				regulator-name = "soc_dvdd12_ir";
+				regulator-min-microvolt = <400000>;
+				regulator-max-microvolt = <1675000>;
+				regulator-boot-on;
+				regulator-always-on;
+				status = "disabled";
+			};
+	   };
+
+	    aon_pmic_config {
+			compatible = "thead,light-pmic-conf";
+			status = "okay";
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+			iic-config = <0 0 2>;
+			pmic_dev_0: pmic-dev@0 {
+			  pmic-name = "dialog,da9063,v1";
+			  pmic-addr = <0x5a 0x5b>;
+			  pmic_wdt_on;
+			  status = "okay";
+			};
+
+			pmic_dev_1: pmic-dev@1 {
+			  pmic-name = "dialog,da9121,v1";
+			  pmic-addr = <0x68>;
+			  status = "okay";
+			};
+
+			regu_config_0 {
+                reg_info = <&soc_dvdd18_aon_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_0 DA9063_ID_LDO3>;
+				};
+			};
+
+			regu_config_1 {
+                reg_info = <&soc_avdd33_usb3_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_0 DA9063_ID_LDO9>;
+				};
+			};
+
+			regu_config_2 {
+                reg_info = <&soc_dvdd08_aon_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_0 DA9063_ID_LDO2>;
+				};
+			};
+
+			regu_config_3 {
+                reg_info = <&soc_apcpu_dvdd_dvddm_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_0 DA9063_ID_BCORE1>;
+					auto_on_info = <0 0 800000>;
+				};
+
+				regu_id@1 {
+                    pmic_dev = <&pmic_dev_0 DA9063_ID_BCORE2>;
+					auto_on_info = <1 0 800000>;
+				};
+
+				regu_id@2 {
+                    pmic_dev = <&pmic_dev_0 DA9063_ID_BUCKIO>;
+					auto_on_info = <2 0 800000>;
+				};
+
+				coupling_info@0 {
+					negative-min;
+                    info = <0 2 5 30>;
+				};
+
+				coupling_info@1 {
+					negative-min;
+                    info = <1 2 5 30>;
+				};
+			};
+
+			regu_config_4 {
+                reg_info = <&soc_dvdd08_ddr_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_0 DA9063_ID_BUCKPERI>;
+				};
+			};
+
+			regu_config_5 {
+                reg_info = <&soc_vdd_ddr_1v8_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_0 DA9063_ID_LDO4>;
+				};
+			};
+
+		    regu_config_6 {
+                reg_info = <&soc_vdd_ddr_1v1_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_0 DA9063_ID_BUCKMEM>;
+				};
+			};
+
+			regu_config_7 {
+                reg_info = <&soc_vdd_ddr_0v6_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_0 DA9063_ID_BUCKPRO>;
+				};
+			};
+
+			regu_config_8 {
+                reg_info = <&soc_dvdd18_ap_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_0 DA9063_ID_LDO11>;
+				};
+			};
+
+            regu_config_9 {
+                reg_info = <&soc_avdd08_mipi_hdmi_reg>;
+				status = "okay";
+				regu_id@0 {
+					pmic_dev = <&pmic_dev_0 DA9063_ID_LDO1>;
+				};
+			};
+
+			regu_config_10 {
+                reg_info = <&soc_avdd18_mipi_hdmi_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_0 DA9063_ID_LDO5>;
+				};
+			};
+
+			regu_config_11 {
+                reg_info = <&soc_dvdd33_emmc_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_0 DA9063_ID_LDO10>;
+				};
+			};
+
+			regu_config_12 {
+                reg_info = <&soc_dovdd18_scan_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_0 DA9063_ID_LDO6>;
+					auto_on_info = <3 1 1800000>;
+					auto_off_info = <1 1>;
+				};
+			};
+
+
+			regu_config_13 {
+                reg_info = <&soc_dvdd12_scan_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_0 DA9063_ID_LDO8>;
+					auto_on_info = <4 1 1200000>;
+					auto_off_info = <2 1>;
+				};
+			};
+
+			regu_config_14 {
+                reg_info = <&soc_avdd28_scan_en_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_0 DA9063_ID_LDO7>;
+					auto_on_info = <5 1 2800000>;
+					auto_off_info = <0 1>;
+				};
+			};
+
+			regu_config_15 {
+                reg_info = <&soc_dvdd08_ap_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_1 DA9121_ID_BUCK1>;
+                    parent_pmic_dev = <&pmic_dev_0 2 0>;
+				};
+			};
+
+			regu_config_16 {
+                reg_info = <&soc_dvdd18_emmc_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_0 DA9063_ID_GPIO7>;
+					parent_pmic_dev = <&pmic_dev_0 7 0>;
+				};
+			};
+		};
+	};
+
 	};
 
 	chosen {

arch/riscv/dts/light-milkv-meles.dts

@@ -1,4 +1,7 @@
 /dts-v1/;
+
+#include <dt-bindings/pmic/light_pmic.h>
+
 / {
 	model = "Milk-V Meles";
 	compatible = "milkv,meles", "thead,c910_light";
@@ -279,6 +282,369 @@
 				u-boot,dm-pre-reloc;
 			};
 		};
+
+		aon {
+		compatible = "thead,light-aon";
+		status = "okay";
+
+		wakeup-by-gpio-on;
+		wakeup-by-rtc-on;
+
+		pd: light-aon-pd {
+			compatible = "thead,light-aon-pd";
+			#power-domain-cells = <1>;
+		};
+
+		light-regu-reg {
+			compatible = "thead,light-dialog-pmic";
+			status = "okay";
+
+
+
+			soc_dvdd18_aon_reg: soc_dvdd18_aon {
+				regulator-name = "soc_dvdd18_aon";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_avdd33_usb3_reg: soc_avdd33_usb3 {
+				regulator-name = "soc_avdd33_usb3";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_dvdd08_aon_reg: soc_dvdd08_aon {
+				regulator-name = "soc_dvdd08_aon";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_apcpu_dvdd_dvddm_reg: soc_apcpu_dvdd_dvddm {
+				regulator-name = "soc_apcpu_dvdd_dvddm";
+				regulator-min-microvolt = <300000>;
+				regulator-max-microvolt = <1570000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_dvdd08_ddr_reg: soc_dvdd08_ddr {
+				regulator-name = "soc_dvdd08_ddr";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_vdd_ddr_1v8_reg: soc_vdd_ddr_1v8 {
+				regulator-name = "soc_vdd_ddr_1v8";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_vdd_ddr_1v1_reg: soc_vdd_ddr_1v1 {
+				regulator-name = "soc_vdd_ddr_1v1";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_vdd_ddr_0v6_reg: soc_vdd_ddr_0v6 {
+				regulator-name = "soc_vdd_ddr_0v6";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_dvdd18_ap_reg: soc_dvdd18_ap {
+				regulator-name = "soc_dvdd18_ap";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_dvdd08_ap_reg: soc_dvdd08_ap {
+				regulator-name = "soc_dvdd08_ap";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_avdd08_mipi_hdmi_reg: soc_avdd08_mipi_hdmi {
+				regulator-name = "soc_avdd08_mipi_hdmi";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_avdd18_mipi_hdmi_reg: soc_avdd18_mipi_hdmi {
+				regulator-name = "soc_avdd18_mipi_hdmi";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_dvdd33_emmc_reg: soc_dvdd33_emmc {
+				regulator-name = "soc_dvdd33_emmc";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_dvdd18_emmc_reg: soc_dvdd18_emmc {
+				regulator-name = "soc_vdd18_emmc";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+			soc_dovdd18_scan_reg: soc_dovdd18_scan {
+				regulator-name = "soc_dovdd18_scan";
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <3600000>;
+			};
+			soc_vext_2v8_reg: soc_vext_2v8 {
+				regulator-name = "soc_vext_2v8";
+				regulator-boot-on;
+				regulator-always-on;
+				status = "disabled";
+			};
+			soc_dvdd12_scan_reg: soc_dvdd12_scan {
+				regulator-name = "soc_dvdd12_scan";
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <3600000>;
+			};
+			soc_avdd28_scan_en_reg: soc_avdd28_scan_en {
+				regulator-name = "soc_avdd28_scan_en";
+				regulator-min-microvolt = <2800000>;
+				regulator-max-microvolt = <2800000>;
+			};
+			soc_avdd28_rgb_reg: soc_avdd28_rgb {
+				regulator-name = "soc_avdd28_rgb";
+				regulator-min-microvolt = <2200000>;
+				regulator-max-microvolt = <3475000>;
+				regulator-boot-on;
+				regulator-always-on;
+				status = "disabled";
+			};
+			soc_dovdd18_rgb_reg: soc_dovdd18_rgb {
+				regulator-name = "soc_dovdd18_rgb";
+				regulator-min-microvolt = <1200000>;
+				regulator-max-microvolt = <3600000>;
+				regulator-boot-on;
+				regulator-always-on;
+				status = "disabled";
+			};
+			soc_dvdd12_rgb_reg: soc_dvdd12_rgb {
+				regulator-name = "soc_dvdd12_rgb";
+				regulator-min-microvolt = <400000>;
+				regulator-max-microvolt = <1675000>;
+				regulator-boot-on;
+				regulator-always-on;
+				status = "disabled";
+			};
+			soc_avdd25_ir_reg: soc_avdd25_ir {
+				regulator-name = "soc_avdd25_ir";
+				regulator-min-microvolt = <2200000>;
+				regulator-max-microvolt = <3475000>;
+				regulator-boot-on;
+				regulator-always-on;
+				status = "disabled";
+			};
+			soc_dovdd18_ir_reg: soc_dovdd18_ir {
+				regulator-name = "soc_dovdd18_ir";
+				regulator-min-microvolt = <1200000>;
+				regulator-max-microvolt = <3600000>;
+				regulator-boot-on;
+				regulator-always-on;
+				status = "disabled";
+			};
+			soc_dvdd12_ir_reg: soc_dvdd12_ir {
+				regulator-name = "soc_dvdd12_ir";
+				regulator-min-microvolt = <400000>;
+				regulator-max-microvolt = <1675000>;
+				regulator-boot-on;
+				regulator-always-on;
+				status = "disabled";
+			};
+	   };
+
+	    aon_pmic_config {
+			compatible = "thead,light-pmic-conf";
+			status = "okay";
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+			iic-config = <0 0 2>;
+			pmic_dev_0: pmic-dev@0 {
+			  pmic-name = "dialog,da9063,v1";
+			  pmic-addr = <0x5a 0x5b>;
+			  pmic_wdt_on;
+			  status = "okay";
+			};
+
+			pmic_dev_1: pmic-dev@1 {
+			  pmic-name = "dialog,da9121,v1";
+			  pmic-addr = <0x68>;
+			  status = "okay";
+			};
+
+			regu_config_0 {
+                reg_info = <&soc_dvdd18_aon_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_0 DA9063_ID_LDO3>;
+				};
+			};
+
+			regu_config_1 {
+                reg_info = <&soc_avdd33_usb3_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_0 DA9063_ID_LDO9>;
+				};
+			};
+
+			regu_config_2 {
+                reg_info = <&soc_dvdd08_aon_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_0 DA9063_ID_LDO2>;
+				};
+			};
+
+			regu_config_3 {
+                reg_info = <&soc_apcpu_dvdd_dvddm_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_0 DA9063_ID_BCORE1>;
+					auto_on_info = <0 0 800000>;
+				};
+
+				regu_id@1 {
+                    pmic_dev = <&pmic_dev_0 DA9063_ID_BCORE2>;
+					auto_on_info = <1 0 800000>;
+				};
+
+				regu_id@2 {
+                    pmic_dev = <&pmic_dev_0 DA9063_ID_BUCKIO>;
+					auto_on_info = <2 0 800000>;
+				};
+
+				coupling_info@0 {
+					negative-min;
+                    info = <0 2 5 30>;
+				};
+
+				coupling_info@1 {
+					negative-min;
+                    info = <1 2 5 30>;
+				};
+			};
+
+			regu_config_4 {
+                reg_info = <&soc_dvdd08_ddr_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_0 DA9063_ID_BUCKPERI>;
+				};
+			};
+
+			regu_config_5 {
+                reg_info = <&soc_vdd_ddr_1v8_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_0 DA9063_ID_LDO4>;
+				};
+			};
+
+		    regu_config_6 {
+                reg_info = <&soc_vdd_ddr_1v1_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_0 DA9063_ID_BUCKMEM>;
+				};
+			};
+
+			regu_config_7 {
+                reg_info = <&soc_vdd_ddr_0v6_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_0 DA9063_ID_BUCKPRO>;
+				};
+			};
+
+			regu_config_8 {
+                reg_info = <&soc_dvdd18_ap_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_0 DA9063_ID_LDO11>;
+				};
+			};
+
+            regu_config_9 {
+                reg_info = <&soc_avdd08_mipi_hdmi_reg>;
+				status = "okay";
+				regu_id@0 {
+					pmic_dev = <&pmic_dev_0 DA9063_ID_LDO1>;
+				};
+			};
+
+			regu_config_10 {
+                reg_info = <&soc_avdd18_mipi_hdmi_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_0 DA9063_ID_LDO5>;
+				};
+			};
+
+			regu_config_11 {
+                reg_info = <&soc_dvdd33_emmc_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_0 DA9063_ID_LDO10>;
+				};
+			};
+
+			regu_config_12 {
+                reg_info = <&soc_dovdd18_scan_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_0 DA9063_ID_LDO6>;
+					auto_on_info = <3 1 1800000>;
+					auto_off_info = <1 1>;
+				};
+			};
+
+
+			regu_config_13 {
+                reg_info = <&soc_dvdd12_scan_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_0 DA9063_ID_LDO8>;
+					auto_on_info = <4 1 1200000>;
+					auto_off_info = <2 1>;
+				};
+			};
+
+			regu_config_14 {
+                reg_info = <&soc_avdd28_scan_en_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_0 DA9063_ID_LDO7>;
+					auto_on_info = <5 1 2800000>;
+					auto_off_info = <0 1>;
+				};
+			};
+
+			regu_config_15 {
+                reg_info = <&soc_dvdd08_ap_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_1 DA9121_ID_BUCK1>;
+                    parent_pmic_dev = <&pmic_dev_0 2 0>;
+				};
+			};
+
+			regu_config_16 {
+                reg_info = <&soc_dvdd18_emmc_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_0 DA9063_ID_GPIO7>;
+					parent_pmic_dev = <&pmic_dev_0 7 0>;
+				};
+			};
+		};
+	};
+	
 	};
 
 	chosen {

board/thead/light-c910/Kconfig

@@ -140,8 +140,7 @@ config SYS_TEXT_BASE
 
 config SPL_TEXT_BASE
     hex
-    default 0xffe0000800 if LIGHT_SEC_BOOT_WITH_VERIFY_VAL_A || LIGHT_SEC_BOOT_WITH_VERIFY_VAL_B || LIGHT_SEC_BOOT_WITH_VERIFY_ANT_REF || LIGHT_SEC_BOOT_WITH_VERIFY_LPI4A
-    default 0xffe0000000 if !(LIGHT_SEC_BOOT_WITH_VERIFY_VAL_A || LIGHT_SEC_BOOT_WITH_VERIFY_VAL_B || LIGHT_SEC_BOOT_WITH_VERIFY_ANT_REF || LIGHT_SEC_BOOT_WITH_VERIFY_LPI4A)
+    default 0xffe0000000
 
 config SPL_MAX_SIZE
     hex
@@ -258,6 +257,11 @@ config DDR_DDP
 	  Enabling this will support ddr Dual Die Package configuration.
 	  e.g. to support 8GB ddr device with 17-bit row address (16:0)
 
+config FIXUP_MEMORY_REGION
+	bool "self-adapt to query and fixup memory region"
+	help
+	  Enabling this will support self-adapt to query and fixup memory region
+
 config DDR_H32_MODE
         bool "LPDDR4/4X 32bit mode configuration"
         help

board/thead/light-c910/Makefile

@@ -23,6 +23,7 @@ obj-$(CONFIG_LPDDR) += $(DDR_SRC_PATH)/init_ddr.o
 obj-$(CONFIG_LPDDR) += $(DDR_SRC_PATH)/pinmux.o
 obj-$(CONFIG_LPDDR) += $(DDR_SRC_PATH)/waitfwdone.o
 obj-$(CONFIG_LPDDR) += $(DDR_SRC_PATH)/ddr_common_func.o
+obj-$(CONFIG_LPDDR) += $(DDR_SRC_PATH)/ddr_retention.o
 obj-$(CONFIG_LPDDR) += $(DDR_SRC_PATH)/common_lib.o
 obj-$(CONFIG_LPDDR) += $(DDR_SRC_PATH)/lpddr4_init.o
 ifdef CONFIG_DDR_DBI_OFF
@@ -63,6 +64,7 @@ obj-y += boot.o
 obj-y += sbmeta/sbmeta.o
 ifndef CONFIG_TARGET_LIGHT_FPGA_FM_C910
 obj-$(CONFIG_LPDDR) += $(DDR_SRC_PATH)/ddr_common_func.o
+obj-$(CONFIG_LPDDR) += $(DDR_SRC_PATH)/ddr_retention.o
 obj-$(CONFIG_LPDDR) += $(DDR_SRC_PATH)/common_lib.o
 endif
 

board/thead/light-c910/board.c

@@ -8,11 +8,18 @@
 #include <asm/io.h>
 #include <dwc3-uboot.h>
 #include <usb.h>
+#include <usb/xhci.h>
 #include <cpu_func.h>
 #include <asm/gpio.h>
 #include <abuf.h>
 #include "sec_library.h"
 
+#ifdef CONFIG_LIGHT_AON_CONF
+#include "../../../drivers/misc/light_regu.h"
+#include "dm/device.h"
+#include "dm/uclass.h"
+#endif
+
 #ifdef CONFIG_USB_DWC3
 static struct dwc3_device dwc3_device_data = {
 	.maximum_speed = USB_SPEED_SUPER,
@@ -29,6 +36,13 @@ int usb_gadget_handle_interrupts(int index)
 int board_usb_init(int index, enum usb_init_type init)
 {
 	dwc3_device_data.base = 0xFFE7040000UL;
+
+	if (init == USB_INIT_DEVICE) {
+		dwc3_device_data.dr_mode = USB_DR_MODE_PERIPHERAL;
+	} else {
+		dwc3_device_data.dr_mode = USB_DR_MODE_HOST;
+	}
+
 	return dwc3_uboot_init(&dwc3_device_data);
 }
 
@@ -38,6 +52,28 @@ int board_usb_cleanup(int index, enum usb_init_type init)
 	return 0;
 }
 
+int xhci_hcd_init(int index, struct xhci_hccr **hccr, struct xhci_hcor **hcor)
+{
+
+
+	int ret = board_usb_init(index, USB_INIT_HOST);
+	if (ret != 0) {
+		puts("Failed to initialize board for USB\n");
+		return ret;
+	}
+
+	*hccr = (struct xhci_hccr *)dwc3_device_data.base;
+	*hcor = (struct xhci_hcor *)(dwc3_device_data.base +
+			HC_LENGTH(xhci_readl(&(*hccr)->cr_capbase)));;
+
+	return ret;
+}
+
+void xhci_hcd_stop(int index)
+{
+	board_usb_cleanup(index, USB_INIT_HOST);
+}
+
 int g_dnl_board_usb_cable_connected(void)
 {
 	return 1;
@@ -45,9 +81,14 @@ int g_dnl_board_usb_cable_connected(void)
 #endif
 
 #ifdef CONFIG_CMD_BOOT_SLAVE
+#ifdef CONFIG_LIGHT_AON_CONF
+#define E902_AON_CONFIG_SIZE 0xC00
+#else
+#define E902_AON_CONFIG_SIZE 0x000
+#endif
 #define E902_SYSREG_START	0xfffff48044
 #define E902_SYSREG_RESET	0xfffff44024
-#define E902_START_ADDRESS	0xFFEF8000
+#define E902_START_ADDRESS	(0xFFEF8000 + E902_AON_CONFIG_SIZE)
 #define C910_E902_START_ADDRESS 0xFFFFEF8000
 #define E902_IOPMP_BASE		0xFFFFC21000
 
@@ -87,31 +128,119 @@ void set_c906_cpu_entry(phys_addr_t entry_h, phys_addr_t entry_l)
 
 void boot_audio(void)
 {
-        writel(0x37, (volatile void *)C906_RESET_REG);
+	writel(0x37, (volatile void *)C906_RESET_REG);
 
-        set_c906_cpu_entry(C906_START_ADDRESS_H, C906_START_ADDRESS_L);
-        flush_cache((uintptr_t)C910_C906_START_ADDRESS, 0x20000);
+	set_c906_cpu_entry(C906_START_ADDRESS_H, C906_START_ADDRESS_L);
+	flush_cache((uintptr_t)C910_C906_START_ADDRESS, 0x20000);
 
-        writel(0x7ffff1f, (volatile void *)C906_CPR_IPCG_ADDRESS);
-        writel((1<<23) | (1<<24), (volatile void *)C906_IOCTL_GPIO_SEL_ADDRESS);
-        writel(0, (volatile void *)C906_IOCTL_AF_SELH_ADDRESS);
+	writel(0x7ffff1f, (volatile void *)C906_CPR_IPCG_ADDRESS);
+	writel((1<<23) | (1<<24), (volatile void *)C906_IOCTL_GPIO_SEL_ADDRESS);
+	writel(0, (volatile void *)C906_IOCTL_AF_SELH_ADDRESS);
 
-        writel(0x3f, (volatile void *)C906_RESET_REG);
+	writel(0x3f, (volatile void *)C906_RESET_REG);
 }
 
-void boot_aon(void)
+#ifdef CONFIG_LIGHT_AON_CONF
+
+int get_and_set_aon_config_data(void)
 {
+	int ret =0;
+    struct udevice *dev;
+	struct mic_regu_platdata *config_data =NULL;
+
+	ret = uclass_first_device_err(UCLASS_MISC, &dev);
+	if(ret){
+        printf("get light aon config faild %d\n", ret);
+		return ret;
+	}
+
+	config_data = (struct mic_regu_platdata *)(dev->platdata);
+
+    volatile aon_config_t* read_config = (aon_config_t* )C910_E902_START_ADDRESS;
+	if(strncmp((const char*)read_config->magic , AON_CONFIG_MAGIC, strlen(AON_CONFIG_MAGIC))) {
+        printf("No aon config magic found in aon bin, please check the aon bin\n");
+		return -1;
+	}
+
+	if(strncmp((const char*)read_config->version, AON_CONFIG_VERSION, strlen(AON_CONFIG_VERSION))) {
+       printf("Err aon config version, aon bin is:%s, u-boot is:%s\n", read_config->version, AON_CONFIG_VERSION);
+	   return -1;
+	}
+
+	if(PMIC_MAX_HW_ID_NUM >  read_config->max_hw_id_num) {
+        printf("Invald max hw id num, aon bin support %d , u-boot is %d\n",read_config->max_hw_id_num, PMIC_MAX_HW_ID_NUM);
+		return -1;
+	}
+
+	/*set pmic dev info */
+	int pmic_dev_num =  config_data->pmic_list.pmic_num;
+    int pmic_dev_list_offset   = sizeof(aon_config_t);
+	uint64_t pmic_dev_start_addr  =  C910_E902_START_ADDRESS + pmic_dev_list_offset;
+
+	int  regu_num            = config_data->regu_id_list.regu_id_num;
+	int  regu_id_list_offset = pmic_dev_list_offset + pmic_dev_num * sizeof(pmic_dev_info_t);
+	uint64_t regu_start_addr  = C910_E902_START_ADDRESS + regu_id_list_offset;
+    int aon_bin_size  =  regu_id_list_offset + regu_num* sizeof(csi_regu_id_t);
+    if( aon_bin_size > read_config->aon_config_partition_size) {
+         printf("Invalid aon partition size, aon bin support:%lld, u-boot is %d\n", read_config->aon_config_partition_size, aon_bin_size);
+		 return -1;
+	}
+
+	printf("pmic_dev_num:%d offset:%d addr:%lld\n",pmic_dev_num, pmic_dev_list_offset, pmic_dev_start_addr);
+
+	memcpy((void*)pmic_dev_start_addr, config_data->pmic_list.pmic_list, pmic_dev_num * sizeof(pmic_dev_info_t));
+    printf("regu_num:%d offset:%d addr:%lld\n",regu_num,regu_id_list_offset, regu_start_addr);
+
+	memcpy((void*)regu_start_addr, config_data->regu_id_list.regu_id_list, regu_num * sizeof(csi_regu_id_t));
+    
+	read_config->wakeup_flag = config_data->wakeup_flag;
+	read_config->aon_pmic.iic_config.iic_id = config_data->iic_config.iic_id;
+	read_config->aon_pmic.iic_config.addr_mode = config_data->iic_config.addr_mode;
+	read_config->aon_pmic.iic_config.speed  = config_data->iic_config.speed;
+	read_config->aon_pmic.pmic_dev_num =  pmic_dev_num;
+    read_config->aon_pmic.pmic_dev_list_offset   = pmic_dev_list_offset;
+
+	/*set regu list info*/
+	read_config->aon_pmic.regu_num =  regu_num;
+	read_config->aon_pmic.regu_id_list_offset = regu_id_list_offset;
+
+	memcpy((void*)read_config->uboot_set_magic, UBOOT_CONFIG_MAGIC, strlen(UBOOT_CONFIG_MAGIC));
+
+    flush_cache((uintptr_t)C910_E902_START_ADDRESS, aon_bin_size);
+
+	printf("-->pmic_dev_num:%d offset:%d\n",read_config->aon_pmic.pmic_dev_num, read_config->aon_pmic.pmic_dev_list_offset);
+	printf("-->regu_num:%d offset:%d\n",read_config->aon_pmic.regu_num,read_config->aon_pmic.regu_id_list_offset);
+	return 0;
+}
+#endif
+
+int do_boot_aon(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
+{
+#ifdef CONFIG_LIGHT_AON_CONF
+    int ret = 0;
+	ret = get_and_set_aon_config_data();
+	if(ret) {
+        printf("aon config and set faild %d", ret);
+		hang();
+		return ret;
+	}
+#endif
 	writel(0xffffffff, (void *)(E902_IOPMP_BASE + 0xc0));
 	disable_slave_cpu();
 	set_slave_cpu_entry(E902_START_ADDRESS);
 	flush_cache((uintptr_t)C910_E902_START_ADDRESS, 0x10000);
 	enable_slave_cpu();
+	return 0;
 }
 
+U_BOOT_CMD(
+	bootaon, CONFIG_SYS_MAXARGS, 0, do_boot_aon,
+	"Boot aon from memory  ",
+	" "
+);
+
 int do_bootslave(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
 {
-	boot_aon();
-	mdelay(100);
 	boot_audio();
 	return 0;
 }

board/thead/light-c910/clock_config.c

@@ -1220,7 +1220,7 @@ int clk_config(void)
 		return -EINVAL;
 
 	printf("C910 CPU FREQ: %ldMHz\n", rate / 1000000);
-
+#ifdef PERI_BUS_PLL_FREQ_PRINT
 	rate = clk_light_get_rate("ahb2_cpusys_hclk", CLK_DEV_MUX);
 	if (!rate)
 		return -EINVAL;
@@ -1262,6 +1262,7 @@ int clk_config(void)
 		return -EINVAL;
 
 	printf("DPU1 PLL POSTDIV FREQ: %ldMHZ\n", rate / 1000000);
+#endif
 
 #ifdef AUDIO_PLL_FREQ_PRINT
 	rate = clk_light_get_rate("audio_pll_foutpostdiv", CLK_DEV_PLL);

board/thead/light-c910/ddr.c

@@ -12,3 +12,17 @@ void init_ddr(void)
 {
 	writel(0x1ff << 4, (void *)0xffff005000);
 }
+
+int fixup_ddr_addrmap(unsigned long size)
+{
+	return 0;
+}
+
+int query_ddr_boundary(unsigned long size)
+{
+	return 0;
+}
+unsigned long get_ddr_density(void)
+{
+	return 0x100000000;
+}

board/thead/light-c910/light.c

@@ -11,6 +11,10 @@
 #include <thead/clock_config.h>
 #include <linux/bitops.h>
 #include <asm/arch-thead/light-iopmp.h>
+#include <memalign.h>
+#include <fdt_support.h>
+#include <fs.h>
+#include <asm/global_data.h>
 
 #define SOC_PIN_AP_RIGHT_TOP          (0x0)
 #define SOC_PIN_AP_LEFT_TOP           (0x1)
@@ -1426,6 +1430,8 @@ static void light_iopin_init(void)
 	light_pin_cfg(CPU_JTG_TMS, PIN_SPEED_NORMAL, PIN_PN, 2);
 	light_pin_mux(CPU_JTG_TDI, 3);
 	light_pin_cfg(CPU_JTG_TDI, PIN_SPEED_NORMAL, PIN_PN, 2);
+	light_pin_mux(CPU_JTG_TRST, 3);
+	light_pin_cfg(CPU_JTG_TRST, PIN_SPEED_NORMAL, PIN_PN, 2);
 
 	light_pin_mux(AOGPIO_7, 1);
 	light_pin_mux(AOGPIO_8, 1);
@@ -1438,7 +1444,7 @@ static void light_iopin_init(void)
 	// light_pin_mux(AOGPIO_15,0);
 	light_pin_cfg(AOGPIO_7, PIN_SPEED_NORMAL, PIN_PN, 2);     ///NC
 	light_pin_cfg(AOGPIO_8, PIN_SPEED_NORMAL, PIN_PN, 2);     ///NC
-	// light_pin_cfg(AOGPIO_9,PIN_SPEED_NORMAL,PIN_PN,2);
+	light_pin_cfg(AOGPIO_9,PIN_SPEED_NORMAL,PIN_PN,2);
 	light_pin_cfg(AOGPIO_10, PIN_SPEED_NORMAL, PIN_PN, 2);
 	light_pin_cfg(AOGPIO_11, PIN_SPEED_NORMAL, PIN_PN, 2);
 	light_pin_cfg(AOGPIO_12, PIN_SPEED_NORMAL, PIN_PN, 2);
@@ -1472,6 +1478,7 @@ static void light_iopin_init(void)
 	light_pin_cfg(AUDIO_PA29, PIN_SPEED_NORMAL, PIN_PN, 2);
 	light_pin_mux(AUDIO_PA30, 0);
 	light_pin_cfg(AUDIO_PA30, PIN_SPEED_NORMAL, PIN_PN, 2);
+	light_pin_mux(AUDIO_PA30, 3);
 
 	// light_pin_mux(AUDIO_PA9,3);                         ///AUDIO-PA-RESET
 	// light_pin_cfg(AUDIO_PA9,PIN_SPEED_NORMAL,PIN_PN,2);
@@ -1611,7 +1618,7 @@ static void light_iopin_init(void)
 	light_pin_cfg(I2C3_SCL, PIN_SPEED_NORMAL, PIN_PN, 4);
 	light_pin_cfg(I2C3_SDA, PIN_SPEED_NORMAL, PIN_PN, 4);
 
-	// light_pin_mux(SPI_CSN,3);                                                /// W_DISABLE_CATE1
+	light_pin_mux(SPI_CSN,3);                                                /// W_DISABLE_CATE1
 	// light_pin_mux(SPI_MOSI,3);                                               /// NC
 	// light_pin_mux(SPI_MISO,3);                                               /// RERST1_N_CAT1
 	// light_pin_mux(SPI_SCLK,3);
@@ -2247,16 +2254,19 @@ static void light_iopin_init(void)
 }
 
 #else
+
 static void light_iopin_init(void)
 {
 	light_pin_cfg(I2C_AON_SCL,PIN_SPEED_NORMAL,PIN_PN,4);
 	light_pin_cfg(I2C_AON_SDA,PIN_SPEED_NORMAL,PIN_PN,4);
 	light_pin_cfg(AOGPIO_8,PIN_SPEED_NORMAL,PIN_PN,2);
 	light_pin_cfg(AOGPIO_9,PIN_SPEED_NORMAL,PIN_PN,2);
+	light_pin_cfg(AOGPIO_14, PIN_SPEED_NORMAL, PIN_PN, 2);
 	light_pin_mux(AOGPIO_10,1);
 	light_pin_mux(AOGPIO_11,1);
 	light_pin_mux(AOGPIO_12,1);
 	light_pin_mux(AOGPIO_13,1);
+	light_pin_mux(AOGPIO_14, 0);
 	light_pin_mux(AUDIO_PA30,3);
 
 	/*qspi1 cs0 gpio0-1 pad strength and pin-pull mode*/
@@ -2496,6 +2506,15 @@ int board_late_init(void)
 	light_usb_boot_check();
 	light_mac_vaild_check();
 	ap_peri_clk_disable();
+
+#ifdef CONFIG_MCU_HC32fX
+	mcu_poweron();
+#endif
+
+#ifdef CONFIG_DM_CHARGE_DISPLAY
+	charge_display();
+#endif
+
 	return 0;
 }
 
@@ -2525,3 +2544,208 @@ U_BOOT_CMD(
 	"check ethaddrs in environment variables is valid",
 	""
 );
+
+
+#define PAGE_SIZE 4096
+#define HIBERNATE_SIG	"S1SUSPEND"
+#define HIBERNATE_SIG2	"S1SUSPEN2" //sign for 2nd time load image
+
+static inline int fdt_disabled_node(void *blob,const char *path)
+{
+	int offset;
+	offset = fdt_path_offset(blob,path);
+	if (offset < 0) {
+		printf("ERROR:failed to find %s node in dtb (ret %d)\n",path,offset);
+		return offset;
+	}
+	return fdt_status_disabled(blob,offset);
+}
+
+static int do_board_check_hibernate(cmd_tbl_t *cmdtp, int flag, int argc,
+		       char * const argv[])
+{
+	int ret;
+	char runcmd[128];
+	ulong addr;
+	void *blob = NULL;
+	ulong mask = 0;
+	int mmc_parts;
+	int resume_part;
+	bool fastresume = 0;
+	#define ON_RET_ERROR(str) if(ret < 0) printf("set node %s status failed %d\n",str,ret)
+	ALLOC_CACHE_ALIGN_BUFFER(u8,swsusp_header_buf,PAGE_SIZE);
+	u8 *header = &swsusp_header_buf[0];
+
+	mmc_parts = env_get_hex("mmcpart",3);
+	resume_part = mmc_parts - 2;
+
+	if(argc >= 4) { // is user pass in ,use that
+		sprintf(runcmd, "read %s %s %s 0 8",
+			argv[1],argv[2],argv[3]);
+		header = (u8 *)simple_strtoul(argv[3],NULL,16);
+		if(argc >= 5)
+			mask = simple_strtoul(argv[4],NULL,16);
+		printf("read swsusp_header to %p,dtb disbale mask 0x%lx\n",header,mask);
+	} else {
+		sprintf(runcmd, "read mmc 0:%d 0x%lx 0 8",
+			resume_part,(unsigned long)&header[0]);
+	}
+
+	ret = run_command(runcmd, 0);
+	if(ret != CMD_RET_SUCCESS)
+		goto failed;
+	if(!memcmp(HIBERNATE_SIG, &header[PAGE_SIZE-10], 10) ||
+		!memcmp(HIBERNATE_SIG2, &header[PAGE_SIZE-10], 10) ) {
+		printf("found sign\n");
+	}
+	else {
+		sprintf(runcmd, "0:%s",env_get("mmcbootpart"));
+		if(file_exists("mmc",runcmd,"no_fastresume",FS_TYPE_EXT)) {
+			printf("do not fastresume\n");
+			goto default_set;
+		}
+
+		sprintf(runcmd, "read mmc 0:%d 0x%lx 0 8",
+			resume_part+1,(unsigned long)&header[0]);
+		ret = run_command(runcmd, 0);
+		if(ret != CMD_RET_SUCCESS)
+			goto failed;
+		if(!memcmp(HIBERNATE_SIG, &header[PAGE_SIZE-10], 10) ||
+			!memcmp(HIBERNATE_SIG2, &header[PAGE_SIZE-10], 10) ) {
+			printf("found fastresume sign\n");
+			resume_part = resume_part+1;
+			fastresume = true;
+		}
+		else {
+			printf(" not find hibernate sign\n");
+			goto default_set;
+		}
+	}
+
+	/*get dtb address*/
+	if(env_get("dtb_addr") == NULL)
+	{
+		printf("Cannot get dtb_addr,check flow !\n");
+		goto failed;
+	}
+	addr = env_get_hex("dtb_addr",0);
+	sprintf(runcmd, "fdt addr 0x%lx", env_get_hex("dtb_addr",0));
+	ret = run_command(runcmd, 0);
+	if(ret != CMD_RET_SUCCESS)
+		goto failed;
+	sprintf(runcmd, "fdt resize");
+	ret = run_command(runcmd, 0);
+	if(ret != CMD_RET_SUCCESS)
+		goto failed;
+
+	/*set unneed devices node disabled for hibernate resume in kernel dtb*/
+	blob = (void *)addr;
+	ret = fdt_status_disabled_by_alias(blob,"i2c0");
+	ON_RET_ERROR("i2c0");
+	ret = fdt_status_disabled_by_alias(blob,"i2c1");
+	ON_RET_ERROR("i2c1");
+	ret = fdt_status_disabled_by_alias(blob,"i2c2");
+	ON_RET_ERROR("i2c2");
+
+	ret = fdt_status_disabled_by_alias(blob,"audio_i2c0");
+	ON_RET_ERROR("audio_i2c0");
+	ret = fdt_status_disabled_by_alias(blob,"audio_i2c1");
+	ON_RET_ERROR("audio_i2c1");
+	ret = fdt_status_disabled_by_alias(blob,"ethernet0");
+	ON_RET_ERROR("ethernet0");
+	ret = fdt_status_disabled_by_alias(blob,"ethernet1");
+	ON_RET_ERROR("ethernet1");
+	ret = fdt_status_disabled_by_alias(blob,"spi0");
+	ON_RET_ERROR("spi0");
+	ret = fdt_status_disabled_by_alias(blob,"spi1");
+	ON_RET_ERROR("spi1");
+	ret = fdt_status_disabled_by_alias(blob,"spi2");
+	ON_RET_ERROR("spi2");
+
+	ret = fdt_disabled_node(blob,"/soc/adc");
+	ON_RET_ERROR("/soc/adc");
+
+	//default mask is 0, need set this node disbaled
+	if(0 == (mask & 0x01)) {
+		ret = fdt_disabled_node(blob,"/soc/light_i2s");
+		ON_RET_ERROR("/soc/light_i2s");
+		ret = fdt_disabled_node(blob,"/soc/audio_i2s0");
+		ON_RET_ERROR("/soc/audio_i2s0");
+		ret = fdt_disabled_node(blob,"/soc/audio_i2s1");
+		ON_RET_ERROR("/soc/audio_i2s1");
+		ret = fdt_disabled_node(blob,"/soc/audio_i2s2");
+		ON_RET_ERROR("/soc/audio_i2s2");
+	}
+	if(0 == (mask & 0x02)) {
+		ret = fdt_disabled_node(blob,"/soc/audio_i2s_8ch_sd0");
+		ON_RET_ERROR("/soc/audio_i2s_8ch_sd0");
+		ret = fdt_disabled_node(blob,"/soc/audio_i2s_8ch_sd1");
+		ON_RET_ERROR("/soc/audio_i2s_8ch_sd1");
+		ret = fdt_disabled_node(blob,"/soc/audio_i2s_8ch_sd2");
+		ON_RET_ERROR("/soc/audio_i2s_8ch_sd2");
+		ret = fdt_disabled_node(blob,"/soc/audio_i2s_8ch_sd3");
+		ON_RET_ERROR("/soc/audio_i2s_8ch_sd3");
+	}
+	/*set resume_bootargs for kernel do fast bootup */
+	sprintf(runcmd,"resume=/dev/mmcblk0p%d notrace noftrace nopty noclkdebug ",resume_part);
+	env_set("resume_bootargs",runcmd);
+
+	return CMD_RET_SUCCESS;
+
+default_set:
+	sprintf(runcmd,"resume=/dev/mmcblk0p%d",resume_part);
+	env_set("resume_bootargs",runcmd);
+	return CMD_RET_SUCCESS;
+
+failed:
+	printf("ERROR:runcmd %s failed!\n",runcmd);
+	sprintf(runcmd,"resume=/dev/mmcblk0p%d",resume_part);
+	env_set("resume_bootargs",runcmd);
+	return CMD_RET_FAILURE;
+}
+
+U_BOOT_CMD(
+	chk_hibernate, 6, 0,	do_board_check_hibernate,
+	"check hibernate image sign,if valid set dtb nodes and bootargs for fast boot resume",
+	" [<interface> <dev[:part]>] [mask]"
+);
+
+#ifdef CONFIG_FIXUP_MEMORY_REGION
+static int do_fixup_memory_region(cmd_tbl_t *cmdtp, int flag, int argc,
+		       char * const argv[])
+{
+	ulong addr;
+	void *blob = NULL;
+	DECLARE_GLOBAL_DATA_PTR;
+	u64 base, size;
+
+	base = gd->ram_base;
+	size = gd->ram_size;
+
+	/*get dtb address*/
+	if(env_get("dtb_addr") == NULL)
+	{
+		printf("Cannot get dtb_addr,check flow !\n");
+		return CMD_RET_FAILURE;
+	}
+	addr = env_get_hex("dtb_addr",0);
+
+	/*set unneed devices node disabled for hibernate resume in kernel dtb*/
+	blob = (void *)addr;
+	fdtdec_setup_mem_size_base_fdt(blob);
+	size -= gd->ram_base;
+
+	if (size != gd->ram_size) {
+		printf("fixup memory region from [0x%09lx ~ 0x%09lx] to [0x%09lx ~ 0x%09lx]\n",
+				gd->ram_base, gd->ram_base+gd->ram_size, gd->ram_base, gd->ram_base+size);
+		gd->ram_size = size;
+		fdt_fixup_memory(blob, gd->ram_base, gd->ram_size);
+	}
+	return CMD_RET_SUCCESS;
+}
+U_BOOT_CMD(
+	fixup_memory_region, 2, 0,	do_fixup_memory_region,
+	"modify linux memory region via gd->ram_size",
+	""
+);
+#endif

board/thead/light-c910/lpddr-regu/ddr_regu.c

@@ -794,7 +794,7 @@ static void light_iopmp_config(void)
 	}
 }
 
-int pmic_ddr_regu_init(void)
+int aon_local_init(void)
 {
 #define AON_PADMUX_BASE (0xfffff4a000)
 	int ret;

board/thead/light-c910/lpddr-regu/ddr_regu.h

@@ -9,5 +9,5 @@
 #define __DDR_REGU_H__
 
 int pmic_ddr_set_voltage(void);
-int pmic_ddr_regu_init(void);
+int aon_local_init(void);
 #endif

board/thead/light-c910/lpddr4/include/aonsys_reg_define.h

@@ -0,0 +1,218 @@
+//------------------------------------------------------------
+// DONOT MODIFY THIS FILE
+// generated by JISHENGJU automatically
+//------------------------------------------------------------
+
+#ifndef AONSYS_SYSREG_REG_OFFSET_DEFINE_H
+#define AONSYS_SYSREG_REG_OFFSET_DEFINE_H
+
+#define AONSYS_REG_BASE			0xFFFFF48000
+
+#define REG_AON_CPU_LP_MODE         (AONSYS_REG_BASE + 0x0  )
+#define REG_AON_CHIP_LP_MODE        (AONSYS_REG_BASE + 0x4  )
+#define REG_AON_AO_SERAM_TRN        (AONSYS_REG_BASE + 0x10 )
+#define REG_AON_AO_SERAM_INT        (AONSYS_REG_BASE + 0x14 )
+#define REG_AON_STR_SERAM_TRN       (AONSYS_REG_BASE + 0x18 )
+#define REG_AON_STR_SERAM_INT       (AONSYS_REG_BASE + 0x1c )
+#define REG_AON_STR_INDICATOR_0     (AONSYS_REG_BASE + 0x20 )
+#define REG_AON_STR_INDICATOR_1     (AONSYS_REG_BASE + 0x24 )
+#define REG_AON_STR_INDICATOR_2     (AONSYS_REG_BASE + 0x28 )
+#define REG_AON_STR_INDICATOR_3     (AONSYS_REG_BASE + 0x2c )
+#define REG_AON_PVTC_WR_LOCK        (AONSYS_REG_BASE + 0x30 )
+#define REG_AON_PVTC_TS_ALARM       (AONSYS_REG_BASE + 0x34 )
+#define REG_AON_PVTC_VM_ALARM       (AONSYS_REG_BASE + 0x38 )
+#define REG_AON_PVTC_PD_ALARM       (AONSYS_REG_BASE + 0x3c )
+#define REG_AON_E902_CNT_CLR        (AONSYS_REG_BASE + 0x40 )
+#define REG_AON_E902_RST_ADDR       (AONSYS_REG_BASE + 0x44 )
+#define REG_AON_C906_RST_ADDR_L     (AONSYS_REG_BASE + 0x48 )
+#define REG_AON_C906_RST_ADDR_H     (AONSYS_REG_BASE + 0x4c )
+#define REG_AON_RESERVED_REG_0      (AONSYS_REG_BASE + 0x50 )
+#define REG_AON_RESERVED_REG_1      (AONSYS_REG_BASE + 0x54 )
+#define REG_AON_RESERVED_REG_2      (AONSYS_REG_BASE + 0x58 )
+#define REG_AON_RESERVED_REG_3      (AONSYS_REG_BASE + 0x5c )
+#define REG_AON_AON_AHB_ADEXT       (AONSYS_REG_BASE + 0x60 )
+#define REG_AON_RC_EN               (AONSYS_REG_BASE + 0x70 )
+#define REG_AON_RC_FCAL             (AONSYS_REG_BASE + 0x74 )
+#define REG_AON_RC_MODE             (AONSYS_REG_BASE + 0x78 )
+#define REG_AON_RC_READY            (AONSYS_REG_BASE + 0x7c )
+#define REG_AON_ISO_CFG             (AONSYS_REG_BASE + 0x80 )
+#define REG_AON_OCRAM_ERR           (AONSYS_REG_BASE + 0x90 )
+#define REG_AON_TIMER_LINK          (AONSYS_REG_BASE + 0x100)
+#define REG_AON_PD_REQ              (AONSYS_REG_BASE + 0x110)
+#define REG_AON_PD_ISO_EN_SET       (AONSYS_REG_BASE + 0x114)
+#define REG_AON_PD_ISO_EN_CLR       (AONSYS_REG_BASE + 0x118)
+#define REG_AON_PD_SW_EN_SET        (AONSYS_REG_BASE + 0x11c)
+#define REG_AON_PD_SW_EN_CLR        (AONSYS_REG_BASE + 0x120)
+#define REG_AON_PD_SW_ACK           (AONSYS_REG_BASE + 0x124)
+#define REG_AON_PD_SW_CNT_EN        (AONSYS_REG_BASE + 0x128)
+#define REG_AON_PD_FSM_RST          (AONSYS_REG_BASE + 0x12c)
+#define REG_AON_PD_INT_MASK         (AONSYS_REG_BASE + 0x130)
+#define REG_AON_PD_FSM_STS_L        (AONSYS_REG_BASE + 0x134)
+#define REG_AON_PD_FSM_STS_H        (AONSYS_REG_BASE + 0x138)
+#define REG_AON_PD_INT_STS          (AONSYS_REG_BASE + 0x13c)
+#define REG_AON_PD_INT_CLR          (AONSYS_REG_BASE + 0x140)
+#define REG_AON_PD_BLK0_SW_CNT      (AONSYS_REG_BASE + 0x144)
+#define REG_AON_PD_BLK1_SW_CNT      (AONSYS_REG_BASE + 0x148)
+#define REG_AON_PD_BLK2_SW_CNT      (AONSYS_REG_BASE + 0x14c)
+#define REG_AON_PD_BLK3_SW_CNT      (AONSYS_REG_BASE + 0x150)
+#define REG_AON_PD_BLK4_SW_CNT      (AONSYS_REG_BASE + 0x154)
+#define REG_AON_PD_BLK5_SW_CNT      (AONSYS_REG_BASE + 0x158)
+#define REG_AON_PD_BLK6_SW_CNT      (AONSYS_REG_BASE + 0x15c)
+#define REG_AON_PD_BLK7_SW_CNT      (AONSYS_REG_BASE + 0x160)
+#define REG_AON_PD_BLK8_SW_CNT      (AONSYS_REG_BASE + 0x164)
+#define REG_AON_PD_BLK9_SW_CNT      (AONSYS_REG_BASE + 0x168)
+#define REG_AON_PD_BLK10_SW_CNT     (AONSYS_REG_BASE + 0x16c)
+#define REG_AON_PD_BLK0_INTV_CNT    (AONSYS_REG_BASE + 0x180)
+#define REG_AON_PD_BLK1_INTV_CNT    (AONSYS_REG_BASE + 0x184)
+#define REG_AON_PD_BLK2_INTV_CNT    (AONSYS_REG_BASE + 0x188)
+#define REG_AON_PD_BLK3_INTV_CNT    (AONSYS_REG_BASE + 0x18c)
+#define REG_AON_PD_BLK4_INTV_CNT    (AONSYS_REG_BASE + 0x190)
+#define REG_AON_PD_BLK5_INTV_CNT    (AONSYS_REG_BASE + 0x194)
+#define REG_AON_PD_BLK6_INTV_CNT    (AONSYS_REG_BASE + 0x198)
+#define REG_AON_PD_BLK7_INTV_CNT    (AONSYS_REG_BASE + 0x19c)
+#define REG_AON_PD_BLK8_INTV_CNT    (AONSYS_REG_BASE + 0x1a0)
+#define REG_AON_PD_BLK9_INTV_CNT    (AONSYS_REG_BASE + 0x1a4)
+#define REG_AON_PD_BLK10_INTV_CNT   (AONSYS_REG_BASE + 0x1a8)
+#define REG_AON_AUDIO_PMU_REQ       (AONSYS_REG_BASE + 0x1f8)
+#define REG_AON_AUDIO_PMU_STS       (AONSYS_REG_BASE + 0x1fc)
+#define REG_AON_AUDIO_PMU_INTR      (AONSYS_REG_BASE + 0x204)
+#define REG_AON_PMU_AUDIO_REQ       (AONSYS_REG_BASE + 0x208)
+#define REG_AON_PMU_AUDIO_STS       (AONSYS_REG_BASE + 0x20c)
+#define REG_AON_MEM_LP_MODE         (AONSYS_REG_BASE + 0x210)
+#define REG_AON_C910_DBG_MASK       (AONSYS_REG_BASE + 0x214)
+#define REG_AON_C910_L2CACHE        (AONSYS_REG_BASE + 0x218)
+#define REG_AON_BISR_CTRL           (AONSYS_REG_BASE + 0x220)
+#define REG_AON_EFUSE_PRELOAD_DONE  (AONSYS_REG_BASE + 0x224)
+#define REG_AON_GPIO_RTE            (AONSYS_REG_BASE + 0x228)
+#define REG_AON_PLL_DSKEW_LOCK      (AONSYS_REG_BASE + 0x22c)
+#define REG_AON_SRAM_AXI_CFG        (AONSYS_REG_BASE + 0x230)
+#define REG_AON_SRAM_AXI_ST         (AONSYS_REG_BASE + 0x234)
+#define REG_AON_SRAM_AXI_ERR_STS_0  (AONSYS_REG_BASE + 0x238)
+#define REG_AON_SRAM_AXI_ERR_STS_1  (AONSYS_REG_BASE + 0x23c)
+#define REG_AON_SRAM_AXI_ERR_STS_2  (AONSYS_REG_BASE + 0x240)
+#define REG_AON_SRAM_AXI_ERR_STS_3  (AONSYS_REG_BASE + 0x244)
+#define REG_AON_SRAM_AXI_ERR_STS_4  (AONSYS_REG_BASE + 0x248)
+#define REG_AON_SE_MUX_LOCK         (AONSYS_REG_BASE + 0x24c)
+#define REG_AON_CPU_DBG_DIS_LOCK    (AONSYS_REG_BASE + 0x270)
+#define REG_AON_RESERVED_REG_4      (AONSYS_REG_BASE + 0x300)
+#define REG_AON_RESERVED_REG_5      (AONSYS_REG_BASE + 0x304)
+#define REG_AON_RESERVED_REG_6      (AONSYS_REG_BASE + 0x308)
+#define REG_AON_RESERVED_REG_7      (AONSYS_REG_BASE + 0x30c)
+#define REG_AON_RESERVED_REG_8      (AONSYS_REG_BASE + 0x400)
+#define REG_AON_RESERVED_REG_9      (AONSYS_REG_BASE + 0x404)
+#define REG_AON_RESERVED_REG_10     (AONSYS_REG_BASE + 0x408)
+#define REG_AON_RESERVED_REG_11     (AONSYS_REG_BASE + 0x40c)
+#define REG_AON_RESERVED_REG_12     (AONSYS_REG_BASE + 0x500)
+#define REG_AON_RESERVED_REG_13     (AONSYS_REG_BASE + 0x504)
+#define REG_AON_RESERVED_REG_14     (AONSYS_REG_BASE + 0x508)
+#define REG_AON_RESERVED_REG_15     (AONSYS_REG_BASE + 0x50c)
+#define REG_AON_RESERVED_REG_16     (AONSYS_REG_BASE + 0x600)
+#define REG_AON_RESERVED_REG_17     (AONSYS_REG_BASE + 0x604)
+#define REG_AON_RESERVED_REG_18     (AONSYS_REG_BASE + 0x608)
+#define REG_AON_RESERVED_REG_19     (AONSYS_REG_BASE + 0x60c)
+
+#define CPU_LP_MODE_DFLT_VAL          0x3ff
+#define CHIP_LP_MODE_DFLT_VAL         0x0
+#define AO_SERAM_TRN_DFLT_VAL         0x0
+#define AO_SERAM_INT_DFLT_VAL         0x0
+#define STR_SERAM_TRN_DFLT_VAL        0x0
+#define STR_SERAM_INT_DFLT_VAL        0x0
+#define STR_INDICATOR_0_DFLT_VAL      0x0
+#define STR_INDICATOR_1_DFLT_VAL      0x0
+#define STR_INDICATOR_2_DFLT_VAL      0x0
+#define STR_INDICATOR_3_DFLT_VAL      0x0
+#define PVTC_WR_LOCK_DFLT_VAL         0x0
+#define PVTC_TS_ALARM_DFLT_VAL        0x0
+#define PVTC_VM_ALARM_DFLT_VAL        0x0
+#define PVTC_PD_ALARM_DFLT_VAL        0x0
+#define E902_CNT_CLR_DFLT_VAL         0x0
+#define E902_RST_ADDR_DFLT_VAL        0xffef8000
+#define C906_RST_ADDR_L_DFLT_VAL      0xc0000000
+#define C906_RST_ADDR_H_DFLT_VAL      0xff
+#define RESERVED_REG_0_DFLT_VAL       0x0
+#define RESERVED_REG_1_DFLT_VAL       0x0
+#define RESERVED_REG_2_DFLT_VAL       0x0
+#define RESERVED_REG_3_DFLT_VAL       0x0
+#define AON_AHB_ADEXT_DFLT_VAL        0x0
+#define RC_EN_DFLT_VAL                0x1
+#define RC_FCAL_DFLT_VAL              0x77f
+#define RC_MODE_DFLT_VAL              0x1
+#define RC_READY_DFLT_VAL             0x0
+#define ISO_CFG_DFLT_VAL              0x0
+#define OCRAM_ERR_DFLT_VAL            0x0
+#define TIMER_LINK_DFLT_VAL           0x0
+#define PD_REQ_DFLT_VAL               0x0
+#define PD_ISO_EN_SET_DFLT_VAL        0x0
+#define PD_ISO_EN_CLR_DFLT_VAL        0x0
+#define PD_SW_EN_SET_DFLT_VAL         0x0
+#define PD_SW_EN_CLR_DFLT_VAL         0x0
+#define PD_SW_ACK_DFLT_VAL            0x3fffff
+#define PD_SW_CNT_EN_DFLT_VAL         0x0
+#define PD_FSM_RST_DFLT_VAL           0x0
+#define PD_INT_MASK_DFLT_VAL          0x3fffff
+#define PD_FSM_STS_L_DFLT_VAL         0x0
+#define PD_FSM_STS_H_DFLT_VAL         0x0
+#define PD_INT_STS_DFLT_VAL           0x0
+#define PD_INT_CLR_DFLT_VAL           0x0
+#define PD_BLK0_SW_CNT_DFLT_VAL       0xff00ff
+#define PD_BLK1_SW_CNT_DFLT_VAL       0xff00ff
+#define PD_BLK2_SW_CNT_DFLT_VAL       0xff00ff
+#define PD_BLK3_SW_CNT_DFLT_VAL       0xff00ff
+#define PD_BLK4_SW_CNT_DFLT_VAL       0xff00ff
+#define PD_BLK5_SW_CNT_DFLT_VAL       0xff00ff
+#define PD_BLK6_SW_CNT_DFLT_VAL       0xff00ff
+#define PD_BLK7_SW_CNT_DFLT_VAL       0xff00ff
+#define PD_BLK8_SW_CNT_DFLT_VAL       0xff00ff
+#define PD_BLK9_SW_CNT_DFLT_VAL       0xff00ff
+#define PD_BLK10_SW_CNT_DFLT_VAL      0xff00ff
+#define PD_BLK0_INTV_CNT_DFLT_VAL     0xff0ffff
+#define PD_BLK1_INTV_CNT_DFLT_VAL     0xff0ffff
+#define PD_BLK2_INTV_CNT_DFLT_VAL     0xff0ffff
+#define PD_BLK3_INTV_CNT_DFLT_VAL     0xff0ffff
+#define PD_BLK4_INTV_CNT_DFLT_VAL     0xff0ffff
+#define PD_BLK5_INTV_CNT_DFLT_VAL     0xff0ffff
+#define PD_BLK6_INTV_CNT_DFLT_VAL     0xff0ffff
+#define PD_BLK7_INTV_CNT_DFLT_VAL     0xff0ffff
+#define PD_BLK8_INTV_CNT_DFLT_VAL     0xff0ffff
+#define PD_BLK9_INTV_CNT_DFLT_VAL     0xff0ffff
+#define PD_BLK10_INTV_CNT_DFLT_VAL    0xff0ffff
+#define AUDIO_PMU_REQ_DFLT_VAL        0x0
+#define AUDIO_PMU_STS_DFLT_VAL        0x0
+#define AUDIO_PMU_INTR_DFLT_VAL       0x0
+#define PMU_AUDIO_REQ_DFLT_VAL        0x0
+#define PMU_AUDIO_STS_DFLT_VAL        0x0
+#define MEM_LP_MODE_DFLT_VAL          0x0
+#define C910_DBG_MASK_DFLT_VAL        0x0
+#define C910_L2CACHE_DFLT_VAL         0x0
+#define BISR_CTRL_DFLT_VAL            0x0
+#define EFUSE_PRELOAD_DONE_DFLT_VAL   0x0
+#define GPIO_RTE_DFLT_VAL             0x0
+#define PLL_DSKEW_LOCK_DFLT_VAL       0x0
+#define SRAM_AXI_CFG_DFLT_VAL         0x0
+#define SRAM_AXI_ST_DFLT_VAL          0x0
+#define SRAM_AXI_ERR_STS_0_DFLT_VAL   0x0
+#define SRAM_AXI_ERR_STS_1_DFLT_VAL   0x0
+#define SRAM_AXI_ERR_STS_2_DFLT_VAL   0x0
+#define SRAM_AXI_ERR_STS_3_DFLT_VAL   0x0
+#define SRAM_AXI_ERR_STS_4_DFLT_VAL   0x0
+#define SE_MUX_LOCK_DFLT_VAL          0x0
+#define CPU_DBG_DIS_LOCK_DFLT_VAL     0x0
+#define RESERVED_REG_4_DFLT_VAL       0x0
+#define RESERVED_REG_5_DFLT_VAL       0x0
+#define RESERVED_REG_6_DFLT_VAL       0x0
+#define RESERVED_REG_7_DFLT_VAL       0x0
+#define RESERVED_REG_8_DFLT_VAL       0x0
+#define RESERVED_REG_9_DFLT_VAL       0x0
+#define RESERVED_REG_10_DFLT_VAL      0x0
+#define RESERVED_REG_11_DFLT_VAL      0x0
+#define RESERVED_REG_12_DFLT_VAL      0x0
+#define RESERVED_REG_13_DFLT_VAL      0x0
+#define RESERVED_REG_14_DFLT_VAL      0x0
+#define RESERVED_REG_15_DFLT_VAL      0x0
+#define RESERVED_REG_16_DFLT_VAL      0x0
+#define RESERVED_REG_17_DFLT_VAL      0x0
+#define RESERVED_REG_18_DFLT_VAL      0x0
+#define RESERVED_REG_19_DFLT_VAL      0x0
+
+
+#endif

board/thead/light-c910/lpddr4/include/aonsys_rstget_reg_define.h

@@ -0,0 +1,90 @@
+//------------------------------------------------------------
+// DONOT MODIFY THIS FILE
+// generated by JISHENGJU automatically
+//------------------------------------------------------------
+
+#ifndef AONSYS_RSTGEN_REG_OFFSET_DEFINE_H
+#define AONSYS_RSTGEN_REG_OFFSET_DEFINE_H
+
+#define AONSYS_RSTGEN_REG_BASE	0xFFFFF44000
+
+#define REG_AON_RST_CNT             (AONSYS_RSTGEN_REG_BASE + 0x0   )
+#define REG_AON_SYS_RST_CFG         (AONSYS_RSTGEN_REG_BASE + 0x10  )
+#define REG_AON_RTC_RST_CFG         (AONSYS_RSTGEN_REG_BASE + 0x14  )
+#define REG_AON_AOGPIO_RST_CFG      (AONSYS_RSTGEN_REG_BASE + 0x18  )
+#define REG_AON_AOI2C_RST_CFG       (AONSYS_RSTGEN_REG_BASE + 0x1c  )
+#define REG_AON_PVTC_RST_CFG        (AONSYS_RSTGEN_REG_BASE + 0x20  )
+#define REG_AON_E902_RST_CFG        (AONSYS_RSTGEN_REG_BASE + 0x24  )
+#define REG_AON_AOTIMER_RST_CFG     (AONSYS_RSTGEN_REG_BASE + 0x28  )
+#define REG_AON_AOWDT_RST_CFG       (AONSYS_RSTGEN_REG_BASE + 0x2c  )
+#define REG_AON_APSYS_RST_CFG       (AONSYS_RSTGEN_REG_BASE + 0x30  )
+#define REG_AON_NPUSYS_RST_CFG      (AONSYS_RSTGEN_REG_BASE + 0x34  )
+#define REG_AON_DDRSYS_RST_CFG      (AONSYS_RSTGEN_REG_BASE + 0x38  )
+#define REG_AON_AUDIO_RST_CFG       (AONSYS_RSTGEN_REG_BASE + 0x3c  )
+#define REG_AON_BISR_RST_CFG        (AONSYS_RSTGEN_REG_BASE + 0x50  )
+#define REG_AON_DSP0_RST_CFG        (AONSYS_RSTGEN_REG_BASE + 0x54  )
+#define REG_AON_DSP1_RST_CFG        (AONSYS_RSTGEN_REG_BASE + 0x58  )
+#define REG_AON_GPU_RST_CFG         (AONSYS_RSTGEN_REG_BASE + 0x5c  )
+#define REG_AON_VDEC_RST_CFG        (AONSYS_RSTGEN_REG_BASE + 0x60  )
+#define REG_AON_VENC_RST_CFG        (AONSYS_RSTGEN_REG_BASE + 0x64  )
+#define REG_AON_ADC_RST_CFG         (AONSYS_RSTGEN_REG_BASE + 0x70  )
+#define REG_AON_AUDGPIO_RST_CFG     (AONSYS_RSTGEN_REG_BASE + 0x74  )
+#define REG_AON_AOUART_RST_CFG      (AONSYS_RSTGEN_REG_BASE + 0x78  )
+#define REG_AON_RST_CLR_0           (AONSYS_RSTGEN_REG_BASE + 0x100 )
+#define REG_AON_RST_CLR_1           (AONSYS_RSTGEN_REG_BASE + 0x104 )
+#define REG_AON_RST_CLR_2           (AONSYS_RSTGEN_REG_BASE + 0x108 )
+#define REG_AON_RST_CLR_3           (AONSYS_RSTGEN_REG_BASE + 0x10c )
+#define REG_AON_RST_CLR_4           (AONSYS_RSTGEN_REG_BASE + 0x110 )
+#define REG_AON_RST_STS_0           (AONSYS_RSTGEN_REG_BASE + 0x120 )
+#define REG_AON_RST_STS_1           (AONSYS_RSTGEN_REG_BASE + 0x124 )
+#define REG_AON_RST_STS_2           (AONSYS_RSTGEN_REG_BASE + 0x128 )
+#define REG_AON_RST_STS_3           (AONSYS_RSTGEN_REG_BASE + 0x12c )
+#define REG_AON_RST_STS_4           (AONSYS_RSTGEN_REG_BASE + 0x130 )
+#define REG_AON_RST_REQ_EN_0        (AONSYS_RSTGEN_REG_BASE + 0x140 )
+#define REG_AON_RST_REQ_EN_1        (AONSYS_RSTGEN_REG_BASE + 0x144 )
+#define REG_AON_RST_REQ_EN_2        (AONSYS_RSTGEN_REG_BASE + 0x148 )
+#define REG_AON_RST_REQ_EN_3        (AONSYS_RSTGEN_REG_BASE + 0x14c )
+#define REG_AON_SRAM_AXI_RST_CFG    (AONSYS_RSTGEN_REG_BASE + 0x11f4)
+#define REG_AON_SE_RST_CFG          (AONSYS_RSTGEN_REG_BASE + 0x160 )
+
+#define RST_CNT_DFLT_VAL              0xf0f
+#define SYS_RST_CFG_DFLT_VAL          0x0
+#define RTC_RST_CFG_DFLT_VAL          0x3
+#define AOGPIO_RST_CFG_DFLT_VAL       0x3
+#define AOI2C_RST_CFG_DFLT_VAL        0x1
+#define PVTC_RST_CFG_DFLT_VAL         0x1
+#define E902_RST_CFG_DFLT_VAL         0x2
+#define AOTIMER_RST_CFG_DFLT_VAL      0x3
+#define AOWDT_RST_CFG_DFLT_VAL        0x1
+#define APSYS_RST_CFG_DFLT_VAL        0x1
+#define NPUSYS_RST_CFG_DFLT_VAL       0x1
+#define DDRSYS_RST_CFG_DFLT_VAL       0x1
+#define AUDIO_RST_CFG_DFLT_VAL        0x0
+#define BISR_RST_CFG_DFLT_VAL         0x3
+#define DSP0_RST_CFG_DFLT_VAL         0x1
+#define DSP1_RST_CFG_DFLT_VAL         0x1
+#define GPU_RST_CFG_DFLT_VAL          0x1
+#define VDEC_RST_GEN_RST_CFG_DFLT_VAL         0x1
+#define VENC_RST_CFG_DFLT_VAL         0x1
+#define ADC_RST_CFG_DFLT_VAL          0x1
+#define AUDGPIO_RST_CFG_DFLT_VAL      0x3
+#define AOUART_RST_CFG_DFLT_VAL       0x3
+#define RST_CLR_0_DFLT_VAL            0x0
+#define RST_CLR_1_DFLT_VAL            0x0
+#define RST_CLR_2_DFLT_VAL            0x0
+#define RST_CLR_3_DFLT_VAL            0x0
+#define RST_CLR_4_DFLT_VAL            0x0
+#define RST_STS_0_DFLT_VAL            0x0
+#define RST_STS_1_DFLT_VAL            0x0
+#define RST_STS_2_DFLT_VAL            0x0
+#define RST_STS_3_DFLT_VAL            0x0
+#define RST_STS_4_DFLT_VAL            0x0
+#define RST_REQ_EN_0_DFLT_VAL         0x11100
+#define RST_REQ_EN_1_DFLT_VAL         0xbb000000
+#define RST_REQ_EN_2_DFLT_VAL         0x0
+#define RST_REQ_EN_3_DFLT_VAL         0x0
+#define SRAM_AXI_RST_CFG_DFLT_VAL     0x5f
+#define SE_RST_CFG_DFLT_VAL           0x1
+
+
+#endif

board/thead/light-c910/lpddr4/include/common_lib.h

@@ -7,6 +7,8 @@
 #include "ddr_reg_define.h"
 #include "ddr_sysreg_registers_struct.h"
 #include "ddr_sysreg_registers.h"
+#include "aonsys_reg_define.h"
+#include "aonsys_rstget_reg_define.h"
 #include "define_ddr.h"
 #include "DWC_ddr_umctl2_c_struct.h"
 #include "DWC_ddr_umctl2_header.h"

board/thead/light-c910/lpddr4/include/ddr_common_func.h

@@ -15,6 +15,9 @@ enum DDR_BITWIDTH {
 
 unsigned long get_ddr_density(void);
 enum DDR_TYPE get_ddr_type(void);
+int get_ddr_rank_number(void);
+int get_ddr_freq(void);
+enum DDR_BITWIDTH get_ddr_bitwidth(void);
 void ddr_sysreg_wr(unsigned long int addr,unsigned int wr_data);
 unsigned int ddr_sysreg_rd(unsigned long int addr);
 
@@ -49,4 +52,8 @@ void addrmap(int rank_num, enum DDR_BITWIDTH bits);
 void ctrl_en(enum DDR_BITWIDTH bits);
 void enable_auto_refresh(void);
 void lpddr4_auto_selref(void);
+int lpddr4_query_boundary(enum DDR_TYPE type, int rank_num, int speed,
+                    enum DDR_BITWIDTH bits, unsigned long size);
+int lpddr4_reinit_ctrl(enum DDR_TYPE type, int rank_num, int speed,
+                    enum DDR_BITWIDTH bits, unsigned long size);
 #endif // DDR_COMMON_FUNCE_H

board/thead/light-c910/lpddr4/include/ddr_retention.h

@@ -0,0 +1,36 @@
+#ifndef DDR_RETENTION_H
+#define DDR_RETENTION_H
+
+///data structure to store ddr misc register address, value
+typedef struct Reg_Misc_Addr_Val {
+  uint32_t Address; ///< register address
+  uint32_t Value;   ///< register value
+} Reg_Misc_Addr_Val_t;
+
+///data structure to store register address, value pairs
+typedef struct Reg_Phy_Addr_Val {
+  uint32_t Address; ///< register address
+  uint16_t Value0;   ///< register value phy0
+  uint16_t Value1;   ///< register value phy1
+} Reg_Phy_Addr_Val_t;
+
+/// enumeration of instructions for PhyInit Register Interface
+typedef enum {
+  saveRegs,         ///< save(read) tracked register values
+  restoreRegs,      ///< restore (write) saved register values
+} regInstr;
+
+// typedef struct Reg_Addr_Value {
+//   uint32_t reg_num;
+//   Reg_Addr_Val_t reg[0];
+// } Reg_Addr_Value_t;
+
+typedef struct Ddr_Reg_Config {
+    uint32_t misc_reg_num;
+    uint32_t phy_reg_num;
+} Ddr_Reg_Config_t;
+
+int dwc_ddrphy_phyinit_regInterface(regInstr myRegInstr);
+void dwc_ddr_misc_regu_save(void);
+
+#endif

board/thead/light-c910/lpddr4/src/ddr_common_func.c

@@ -2,9 +2,14 @@
 #include <linux/sizes.h>
 #include "../include/common_lib.h"
 #include "../include/ddr_common_func.h"
+#include "../include/ddr_retention.h"
 
 DDR_SYSREG_REG_SW_REG_S ddr_sysreg;
 
+#ifdef CONFIG_DDR_MSG
+#define DDR_DEBUG(x) printf(x)
+#endif
+
 #ifndef CONFIG_DDR_RANK_SIZE
 #define CONFIG_DDR_RANK_SIZE SZ_4G
 #endif
@@ -34,6 +39,44 @@ enum DDR_TYPE get_ddr_type() {
 #endif // #ifdef CONFIG_LPDDR4X
 }
 
+int get_ddr_rank_number() {
+#ifdef CONFIG_DDR_SINGLE_RANK
+	return 1;
+#elif defined CONFIG_DDR_DUAL_RANK
+	return 2;
+#else
+#ifdef CONFIG_DDR_MSG
+	DDR_DEBUG("unsupported ddr rank type!!!\n");
+#endif
+    return NULL;
+#endif
+}
+
+int get_ddr_freq() {
+#ifdef CONFIG_DDR_4266
+    return 4266;
+#elif CONFIG_DDR_3733
+    return 3733;
+#elif CONFIG_DDR_3200
+    return 3200;
+#elif CONFIG_DDR_2133
+	return 2133;
+#else
+    printf("unsupport lpddr4 freq!!!\n");
+    return -1;
+#endif
+}
+
+enum DDR_BITWIDTH get_ddr_bitwidth() {
+#ifdef CONFIG_DDR_H32_MODE
+    return DDR_BITWIDTH_32;
+#elif CONFIG_DDR_H16_MODE
+    return DDR_BITWIDTH_16;
+#else
+    return DDR_BITWIDTH_64;
+#endif
+}
+
 void ddr_sysreg_wr(unsigned long int addr,unsigned int wr_data) {
   wr(addr+DDR_SYSREG_BADDR,wr_data);
 }
@@ -104,75 +147,114 @@ unsigned int ddr_phy_reg_rd(unsigned long int addr) {
 
   void lp4_mrw(int addr, int wdata,int dch,int rank) {
   DWC_DDR_UMCTL2_C_STRUCT_REG_S umctl2_reg;
+  uint32_t val_t0,val_t1;
   if(dch==0) {
-  umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32 = rd(MRCTRL0);
-  //umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_addr = addr; //do not care for lp4
-  umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_rank = rank;//rank0 only
-  umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_type = 0;//write
-  wr(MRCTRL0,umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32);
+        while ((rd(MRSTAT) & 0x1) == 0x1);
+        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32 = rd(MRCTRL0);
+        //umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_addr = addr; //do not care for lp4
+        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_rank = rank;//rank0 only
+        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_type = 0;//write
+        wr(MRCTRL0, umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32);
 
-  umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32 = rd(MRCTRL1);
-  umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.mr_data = (addr<<8) | (wdata&0xFF);
-  wr(MRCTRL1,umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32);
-  
-  umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32 = rd(MRCTRL0);
-  umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_wr = 1;//trigger wr/rd
-  wr(MRCTRL0,umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32);
+        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32 = rd(MRCTRL1);
+        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.mr_data = (addr << 8) | (wdata & 0xFF);
+        wr(MRCTRL1, umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32);
+
+        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32 = rd(MRCTRL1);
+        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.mr_data = (addr << 8) | (wdata & 0xFF);
+        wr(MRCTRL1, umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32);
+
+        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32 = rd(MRCTRL0);
+        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_wr = 1;//trigger wr/rd
+        wr(MRCTRL0, umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32);
+
+        //udelay(10);
+        //delay 5us
+        val_t0=rd(0xFFF4D004);
+        val_t1=rd(0xFFF4D004);
+        while((val_t0-val_t1)<200){val_t1=rd(0xFFF4D004);};
+
+        while ((rd(MRSTAT) & 0x1) == 0x1);
   }
   else {
-  umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32 = rd(MRCTRL0_DCH1);
-  //umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_addr = addr; //do not care for lp4
-  umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_rank = rank;//rank0 only
-  umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_type = 0;//write
-  wr(MRCTRL0_DCH1,umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32);
+        while ((rd(MRSTAT_DCH1) & 0x1) == 0x1);
+        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32 = rd(MRCTRL0_DCH1);
+        //umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_addr = addr; //do not care for lp4
+        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_rank = rank;//rank0 only
+        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_type = 0;//write
+        wr(MRCTRL0_DCH1, umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32);
 
-  umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32 = rd(MRCTRL1_DCH1);
-  umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.mr_data = (addr<<8) | (wdata&0xFF);
-  wr(MRCTRL1_DCH1,umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32);
-  
-  umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32 = rd(MRCTRL0_DCH1);
-  umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_wr = 1;//trigger wr/rd
-  wr(MRCTRL0_DCH1,umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32);
-  }
+        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32 = rd(MRCTRL1_DCH1);
+        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.mr_data = (addr << 8) | (wdata & 0xFF);
+        wr(MRCTRL1_DCH1, umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32);
+
+
+        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32 = rd(MRCTRL1_DCH1);
+        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.mr_data = (addr << 8) | (wdata & 0xFF);
+        wr(MRCTRL1_DCH1, umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32);
+
+        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32 = rd(MRCTRL0_DCH1);
+        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_wr = 1;//trigger wr/rd
+        wr(MRCTRL0_DCH1, umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32);
+
+        //udelay(10);
+        //delay 5us
+        val_t0=rd(0xFFF4D004);
+        val_t1=rd(0xFFF4D004);
+        while((val_t0-val_t1)<200){val_t1=rd(0xFFF4D004);};
+        while ((rd(MRSTAT_DCH1) & 0x1) == 0x1);
   }
+}
 
   int lp4_mrr(int addr,int dch,int rank) {
   DWC_DDR_UMCTL2_C_STRUCT_REG_S umctl2_reg;
   if(dch==0) {
-  umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32 = rd(MRCTRL0);
-  //umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_addr = addr; //do not care for lp4
-  umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_rank = rank;//rank0 only
-  umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_type = 1;//read
-  wr(MRCTRL0,umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32);
+        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32 = rd(MRCTRL0);
+        //umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_addr = addr; //do not care for lp4
+        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_rank = rank;//rank0 only
+        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_type = 1;//read
+        wr(MRCTRL0, umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32);
 
-  umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32 = rd(MRCTRL1);
-  umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.mr_data = addr<<8;
-  wr(MRCTRL1,umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32);
-  
-  umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32 = rd(MRCTRL0);
-  umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_wr = 1;//trigger wr/rd
-  wr(MRCTRL0,umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32);
+        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32 = rd(MRCTRL1);
+        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.mr_data = addr << 8;
+        wr(MRCTRL1, umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32);
 
-  umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32 = rd(MRCTRL1);
-  return (umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.mr_data & 0xFF);
+        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32 = rd(MRCTRL1);
+        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.mr_data = addr << 8;
+        wr(MRCTRL1, umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32);
+
+
+        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32 = rd(MRCTRL0);
+        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_wr = 1;//trigger wr/rd
+        wr(MRCTRL0, umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32);
+
+        udelay(20);
+        while ((rd(MRSTAT) & 0x1) == 0x1);
+        return ddr_sysreg_rd(MRR_STS_CH0);
   }
   else {
-  umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32 = rd(MRCTRL0_DCH1);
-  //umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_addr = addr; //do not care for lp4
-  umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_rank = rank;//rank0 only
-  umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_type = 1;//read
-  wr(MRCTRL0_DCH1,umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32);
+        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32 = rd(MRCTRL0_DCH1);
+        //umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_addr = addr; //do not care for lp4
+        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_rank = rank;//rank0 only
+        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_type = 1;//read
+        wr(MRCTRL0_DCH1, umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32);
 
-  umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32 = rd(MRCTRL1_DCH1);
-  umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.mr_data = addr<<8;
-  wr(MRCTRL1_DCH1,umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32);
-  
-  umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32 = rd(MRCTRL0_DCH1);
-  umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_wr = 1;//trigger wr/rd
-  wr(MRCTRL0_DCH1,umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32);
+        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32 = rd(MRCTRL1_DCH1);
+        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.mr_data = addr << 8;
+        wr(MRCTRL1_DCH1, umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32);
 
-  umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32 = rd(MRCTRL1_DCH1);
-  return (umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.mr_data & 0xFF);
+
+        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32 = rd(MRCTRL1_DCH1);
+        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.mr_data = addr << 8;
+        wr(MRCTRL1_DCH1, umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32);
+
+        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32 = rd(MRCTRL0_DCH1);
+        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_wr = 1;//trigger wr/rd
+        wr(MRCTRL0_DCH1, umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32);
+
+        udelay(20);
+        while ((rd(MRSTAT_DCH1) & 0x1) == 0x1);
+        return ddr_sysreg_rd(MRR_STS_CH1);
   }
   }
 
@@ -236,15 +318,15 @@ unsigned int ddr_phy_reg_rd(unsigned long int addr) {
     if(port & 0x4) wr(PCTRL_2,0);
     if(port & 0x8) wr(PCTRL_3,0);
     if(port & 0x10) wr(PCTRL_4,0);
-    if(port & 0x1F) { //at least one port is not disabled
-        wr(DBG1,0);
-        wr(DBG1_DCH1,0);
+    while (rd(PSTAT) != 0x0);
+    if ((port & 0x1F) == 0x1F) { //all ports are disabled
+        wr(DBG1, 2);
+        wr(DBG1_DCH1, 2);
     }
-    else { //all ports are disabled
-        wr(DBG1,3);
-        wr(DBG1_DCH1,3);
+    else { //at least one port is not disabled
+        wr(DBG1, 0);
+        wr(DBG1_DCH1, 0);
     }
-
   }
 
   void enable_axi_port(int port) {
@@ -457,7 +539,7 @@ if(bits==64) {
   wr(DFITMG0,0x05a3820e);//[28:24] dft_t_ctrl_delay [22:16] dfi_t_rddate_en=RL-5
 #endif
   wr(DFITMG1,0x000c0303);
-  wr(DFILPCFG0,0x0351a001);
+  wr(DFILPCFG0,0x0351a101); //[8]=1: enable dfi lp mode during selfref
   //wr(DFIUPD0,0x00400018); //[31:30]=0 use ctrlupd enable
   //wr(DFIUPD1,0x00b700c4);
   //wr(DFIUPD2,0x00000000);//[31]=0 disable phy ctrlupdate
@@ -557,7 +639,7 @@ if(bits==64) {
   wr(DFITMG0,0x059f820c);//[28:24] dfi_t_ctrl_delay
 #endif
   wr(DFITMG1,0x000c0303);//dfi_t_wrdata_delay=tctrl+6+BL/2+trainedTdqsdly=24, may need take care cmd pipe
-  wr(DFILPCFG0,0x0351a001);
+  wr(DFILPCFG0,0x0351a101); //[8]=1: enable dfi lp mode during selfref
   //wr(DFIUPD0,0xc0400018);
   //wr(DFIUPD1,0x00b700c4);
   //wr(DFIUPD2,0x80000000);
@@ -645,7 +727,7 @@ if(bits==64) {
   wr(DFITMG0,0x059b820a); //[22:16] dfi_t_rddate_en=RL-5
 #endif
   wr(DFITMG1,0x000b0303);
-  wr(DFILPCFG0,0x0351a001);
+  wr(DFILPCFG0,0x0351a101); //[8]=1: enable dfi lp mode during selfref
   //wr(DFIUPD0,0xc0400018);
   //wr(DFIUPD1,0x00b700c4);
   //wr(DFIUPD2,0x80000000);
@@ -730,7 +812,7 @@ if(bits==64) {
   wr(ZQCTL2,0x00000000);
   wr(DFITMG0,0x048f8206);
   wr(DFITMG1,0x000b0303);
-  wr(DFILPCFG0,0x0351a001);
+  wr(DFILPCFG0,0x0351a101); //[8]=1: enable dfi lp mode during selfref
   //wr(DFIUPD0,0xc0400018);
   //wr(DFIUPD1,0x00b700c4);
   //wr(DFIUPD2,0x80000000);
@@ -856,17 +938,28 @@ if(bits==64) {
 #ifdef CONFIG_DDR_MSG
  printf("DDR 32bit mode\n");
 #endif
-  wr(ADDRMAP0,0x001f001f);  //
   if(rank_num==2) {
-  wr(ADDRMAP0,0x001f0017);//4GB
+#ifdef CONFIG_DDR_DDP
+    wr(ADDRMAP0,0x001f0018);//max 8GB
+#else
+    wr(ADDRMAP0,0x001f0017); //4GB
+#endif
+  }
+  else {
+    wr(ADDRMAP0,0x001f001f); //cs_bit0: NULL
   }
   wr(ADDRMAP1,0x00080808); //bank +2
   wr(ADDRMAP2,0x00000000); //col b5+5 ~ col b2  +2
   wr(ADDRMAP3,0x00000000); //col b9 ~ col b6
   wr(ADDRMAP4,0x00001f1f); //col b11~ col b10
   wr(ADDRMAP5,0x070f0707); //row_b11 row b2_10 row b1 row b0  +6
-  wr(ADDRMAP6,0x07070707); //max row 15
-  wr(ADDRMAP7,0x00000f0f);
+  wr(ADDRMAP6,0x07070707); //row 15
+  wr(ADDRMAP7,0x00000f0f); //row16: NULL
+#ifdef CONFIG_DDR_DDP
+  if(rank_num==2) {
+    wr(ADDRMAP7,0x00000f07); //max row16
+  }
+#endif
   wr(ADDRMAP9,0x07070707);
   wr(ADDRMAP10,0x07070707);
   wr(ADDRMAP11,0x00000007);
@@ -874,12 +967,12 @@ if(bits==64) {
 #ifdef CONFIG_DDR_MSG
  printf("DDR 64bit mode, 256B interleaving\n");
 #endif
-  wr(ADDRMAP0,0x0004001f);  // +2
+  wr(ADDRMAP0,0x0004001f); //cs_bit0: NULL
   if(rank_num==2) {
 #ifdef CONFIG_DDR_DDP
-  wr(ADDRMAP0,0x00040019);//16GB
+    wr(ADDRMAP0,0x00040019);//max 16GB
 #else
-  wr(ADDRMAP0,0x00040018);//8GB
+    wr(ADDRMAP0,0x00040018);//8GB
 #endif
   }
   wr(ADDRMAP1,0x00090909); //bank +2
@@ -887,11 +980,11 @@ if(bits==64) {
   wr(ADDRMAP3,0x01010101); //col b9 ~ col b6
   wr(ADDRMAP4,0x00001f1f); //col b11~ col b10
   wr(ADDRMAP5,0x080f0808); //row_b11 row b2_10 row b1 row b0  +6
-  wr(ADDRMAP6,0x08080808);
+  wr(ADDRMAP6,0x08080808); //row15
 #ifdef CONFIG_DDR_DDP
-  wr(ADDRMAP7,0x00000f08);
+  wr(ADDRMAP7,0x00000f08); //row16
 #else
-  wr(ADDRMAP7,0x00000f0f);
+  wr(ADDRMAP7,0x00000f0f); //row16: NULL
 #endif
   wr(ADDRMAP9,0x08080808);
   wr(ADDRMAP10,0x08080808);
@@ -901,6 +994,130 @@ if(bits==64) {
  }
 }
 
+#define MEMSIZE_MIN_MB (2*1024)
+#define MEMSIZE_MAX_MB (16*1024)
+#define UNIT_MB (1024*1024)
+int lpddr4_query_boundary(enum DDR_TYPE type, int rank_num, int speed,
+					enum DDR_BITWIDTH bits, unsigned long size)
+{
+  if ((size < (unsigned long)MEMSIZE_MIN_MB*UNIT_MB) ||
+    (size > (unsigned long)MEMSIZE_MAX_MB*UNIT_MB))
+    goto err_ret;
+
+  if (bits == DDR_BITWIDTH_32) {// only phy0
+    if (rank_num == 2) {
+      if (size == 0x80000000) //2GB
+        goto err_ret;
+      else if (size == 0x100000000) //4GB
+        goto ret_ok;
+      else if (size == 0x200000000) //8GB
+        goto ret_ok;
+      else if (size == 0x400000000) //16GB
+        goto err_ret;
+      else
+        goto err_ret;
+    }
+    else { // single rank
+      if (size == 0x80000000) //2GB
+        goto ret_ok;
+      else if (size == 0x100000000) //4GB
+        goto err_ret;
+      else if (size == 0x200000000) //8GB
+        goto err_ret;
+      else if (size == 0x400000000) //16GB
+        goto err_ret;
+      else
+        goto err_ret;
+    }
+  }
+  else if (bits == DDR_BITWIDTH_64) { // phy0+phy1
+    if (rank_num == 2) {
+      if (size == 0x80000000) //2GB
+        goto err_ret;
+      else if (size == 0x100000000) //4GB
+        goto err_ret;
+      else if (size == 0x200000000) //8GB
+        goto ret_ok;
+      else if (size == 0x400000000) //16GB
+        goto ret_ok;
+      else
+        goto err_ret;
+    }
+    else { // single rank
+      if (size == 0x80000000) //2GB
+        goto err_ret;
+      else if (size == 0x100000000) //4GB
+        goto ret_ok;
+      else if (size == 0x200000000) //8GB
+        goto err_ret;
+      else if (size == 0x400000000) //16GB
+        goto err_ret;
+      else
+        goto err_ret;
+    }
+  }
+  else {
+    goto err_ret;
+  }
+
+ret_ok:
+  return 0;
+
+err_ret:
+  return -1;
+}
+
+int adjust_ddr_addrmap(enum DDR_TYPE type, int rank_num, int speed,
+					enum DDR_BITWIDTH bits, unsigned long size)
+{
+  if (lpddr4_query_boundary(type, rank_num, speed, bits, size) < 0)
+    goto err_ret;
+
+  if (bits == DDR_BITWIDTH_32) {// only phy0
+    if (rank_num == 2) {
+      if (size == 0x100000000) {//4GB
+        wr(ADDRMAP0,0x001f0017); // cs_bit0: HIF[29]
+        wr(ADDRMAP7,0x00000f0f); // row16: NULL
+      }
+      else if (size == 0x200000000) {//8GB
+        wr(ADDRMAP0,0x001f0018); // cs_bit0: HIF[30]
+        wr(ADDRMAP7,0x00000f07); // row16: HIF[29]
+      }
+    }
+	else { // single rank
+      if (size == 0x80000000) //2GB
+        wr(ADDRMAP0,0x001f001f); // cs_bit0: NULL
+    }
+  }
+  else if (bits == DDR_BITWIDTH_64) { // phy0+phy1
+    if (rank_num == 2) {
+      if (size == 0x200000000) {//8GB
+        wr(ADDRMAP0,0x00040018); // cs_bit0: HIF[30]
+        wr(ADDRMAP7,0x00000f0f); // row16: NULL
+      }
+      else if (size == 0x400000000) {//16GB
+        wr(ADDRMAP0,0x00040019); // cs_bit0: HIF[31]
+        wr(ADDRMAP7,0x00000f08); // row16: HIF[30]
+      }
+    }
+    else { // single rank
+      if (size == 0x100000000) {//4GB
+        wr(ADDRMAP0,0x0004001f); // cs_bit0: NULL
+        wr(ADDRMAP7,0x00000f0f); // row16: NULL
+      }
+    }
+  }
+  else {
+    // nothing
+  }
+
+  return 0;
+
+err_ret:
+  printf("unsupport memsize %ld\n", size);
+  return -1;
+}
+
   void quasi_reg_write(unsigned long int reg,int wdata) {
     DWC_DDR_UMCTL2_C_STRUCT_REG_S umctl2_reg;
 
@@ -1015,11 +1232,11 @@ void lpddr4_enter_selfrefresh(int pwdn_en,int dis_dram_clk,int mode) {
     umctl2_reg.dwc_ddr_umctl2_c_struct_stat.u32 = rd(STAT_DCH1);
     if(pwdn_en) {
     while( umctl2_reg.dwc_ddr_umctl2_c_struct_stat.selfref_state != 2) //wait sdram enter selfrefresh-powerdown state
-        umctl2_reg.dwc_ddr_umctl2_c_struct_stat.u32 = rd(STAT);
+        umctl2_reg.dwc_ddr_umctl2_c_struct_stat.u32 = rd(STAT_DCH1);
     }
     else {
     while( umctl2_reg.dwc_ddr_umctl2_c_struct_stat.selfref_state != 1) //wait sdram enter selfrefresh state
-        umctl2_reg.dwc_ddr_umctl2_c_struct_stat.u32 = rd(STAT);
+        umctl2_reg.dwc_ddr_umctl2_c_struct_stat.u32 = rd(STAT_DCH1);
     }
 #ifdef CONFIG_DDR_MSG
     printf("[lpddr4_enter_selfrefresh]: CH1 STAT is :%x after enter selfrefresh state\n",umctl2_reg.dwc_ddr_umctl2_c_struct_stat.u32);
@@ -1055,7 +1272,8 @@ void lpddr4_auto_ps_en(int pwdn_en,int selfref_en,int clock_auto_disable ) {
     //ddr_sysreg_wr(DDR_CFG0,0x1ff0);
     //ddr_sysreg_wr(DDR_CFG0,0x1ff0);
     ddr_sysreg.ddr_sysreg_registers_struct_ddr_cfg0.u32 = ddr_sysreg_rd(DDR_CFG0);
-    ddr_sysreg.ddr_sysreg_registers_struct_ddr_cfg0.rg_ctl_ddr_usw_rst_reg |= 0x1F2;
+    //ddr_sysreg.ddr_sysreg_registers_struct_ddr_cfg0.rg_ctl_ddr_usw_rst_reg |= 0x1F2;
+    ddr_sysreg.ddr_sysreg_registers_struct_ddr_cfg0.rg_ctl_ddr_usw_rst_reg |= 0x1FA;
     ddr_sysreg_wr(DDR_CFG0,ddr_sysreg.ddr_sysreg_registers_struct_ddr_cfg0.u32);
   }
 
@@ -1075,7 +1293,7 @@ void dfi_freq_change(int dfi_freq,int skip_dram_init) {
 #ifdef CONFIG_DDR_MSG
   printf("[dfi_freq_change]: start dfi_freq_change, target dfi_freq is %x \n",dfi_freq);
 #endif
-  wr(DBG1,3);
+  //wr(DBG1,3);
   umctl2_reg.dwc_ddr_umctl2_c_struct_swctl.u32 = rd(SWCTL);
   umctl2_reg.dwc_ddr_umctl2_c_struct_swctl.sw_done = 0;
   wr(SWCTL,umctl2_reg.dwc_ddr_umctl2_c_struct_swctl.u32);
@@ -1086,7 +1304,6 @@ void dfi_freq_change(int dfi_freq,int skip_dram_init) {
 
   umctl2_reg.dwc_ddr_umctl2_c_struct_dfimisc.u32 = rd(DFIMISC);
   umctl2_reg.dwc_ddr_umctl2_c_struct_dfimisc.dfi_frequency = dfi_freq;
-  umctl2_reg.dwc_ddr_umctl2_c_struct_dfimisc.dfi_init_start = 0x1;
   umctl2_reg.dwc_ddr_umctl2_c_struct_dfimisc.dfi_init_complete_en = 0;
   wr(DFIMISC,umctl2_reg.dwc_ddr_umctl2_c_struct_dfimisc.u32);
 
@@ -1097,15 +1314,28 @@ void dfi_freq_change(int dfi_freq,int skip_dram_init) {
   while( umctl2_reg.dwc_ddr_umctl2_c_struct_swstat.sw_done_ack == 0)
     umctl2_reg.dwc_ddr_umctl2_c_struct_swctl.u32 = rd(SWSTAT);
 
+  wr(SWCTL,0x0);
+  umctl2_reg.dwc_ddr_umctl2_c_struct_dfimisc.u32 = rd(DFIMISC);
+  umctl2_reg.dwc_ddr_umctl2_c_struct_dfimisc.dfi_init_start = 0x1;
+  wr(DFIMISC,umctl2_reg.dwc_ddr_umctl2_c_struct_dfimisc.u32);
+  wr(SWCTL,0x1);
+  while(rd(SWSTAT)!=0x00000001);
   rdata = rd(DFISTAT);
+  while ((rdata & 0x1) != 0) //wait dfi_init_complete = 0
+    rdata = rd(DFISTAT);
+
+#ifndef CONFIG_DDR_H32_MODE
+  rdata = rd(DCH1_DFISTAT);
   while((rdata & 0x1) != 0) //wait dfi_init_complete = 0
-  rdata = rd(DFISTAT);
+    rdata = rd(DCH1_DFISTAT);
+#endif
+
   //change dfi clk freq here
   //pull down dfi_init_start
   umctl2_reg.dwc_ddr_umctl2_c_struct_swctl.u32 = rd(SWCTL);
   umctl2_reg.dwc_ddr_umctl2_c_struct_swctl.sw_done = 0;
-  wr(SWCTL,umctl2_reg.dwc_ddr_umctl2_c_struct_swctl.u32);
-
+  wr(SWCTL, umctl2_reg.dwc_ddr_umctl2_c_struct_swctl.u32);
+ 
   umctl2_reg.dwc_ddr_umctl2_c_struct_dfimisc.u32 = rd(DFIMISC);
   umctl2_reg.dwc_ddr_umctl2_c_struct_dfimisc.dfi_init_start = 0;
   wr(DFIMISC,umctl2_reg.dwc_ddr_umctl2_c_struct_dfimisc.u32);
@@ -1119,9 +1349,17 @@ void dfi_freq_change(int dfi_freq,int skip_dram_init) {
   umctl2_reg.dwc_ddr_umctl2_c_struct_dfistat.u32 = rd(DFISTAT);
   while(umctl2_reg.dwc_ddr_umctl2_c_struct_dfistat.dfi_init_complete == 0)
     umctl2_reg.dwc_ddr_umctl2_c_struct_dfistat.u32 = rd(DFISTAT);
-  wr(DBG1,0);
+
+  //wait dfi_init_complete = 1
+#ifndef CONFIG_DDR_H32_MODE
+  umctl2_reg.dwc_ddr_umctl2_c_struct_dfistat.u32 = rd(DCH1_DFISTAT);
+  while(umctl2_reg.dwc_ddr_umctl2_c_struct_dfistat.dfi_init_complete == 0)
+    umctl2_reg.dwc_ddr_umctl2_c_struct_dfistat.u32 = rd(DCH1_DFISTAT);
+#endif
+
+  //wr(DBG1,0);
 #ifdef CONFIG_DDR_MSG
-  printf("[dfi_freq_change]: dfi_freq_change, end \n",dfi_freq);
+  printf("[dfi_freq_change]: dfi_freq_change, end \n");
 #endif
 }
 
@@ -1146,3 +1384,168 @@ void lpddr4_auto_selref(void)
   wr(PWRCTL,0x0000000b); //[3] dfi_dram_clk_disable [1] powerdown_en [0]serref_en
   wr(DCH1_PWRCTL,0x0000000b);
 }
+
+void ctrl_en_lp3_exit(enum DDR_BITWIDTH bits) {
+  //skip DRAM init, because this has done 
+  wr(SWCTL,0x00000000);
+  wr(INIT0,0xc0020002);
+  wr(SWCTL,0x00000001);
+  while(rd(SWSTAT)!=0x00000001);
+
+  //dfi frequency change proto ,to PS0
+  wr(SWCTL,0x00000000);
+  wr(DFIMISC,0x00000000);// [5]dfi_freq=0x0
+  wr(SWCTL,0x00000001);
+  while(rd(SWSTAT)!=0x00000001);
+
+  wr(SWCTL,0x00000000);
+  wr(DFIMISC,0x00000020);// [5]dfi_init_start=0x1
+  wr(SWCTL,0x00000001);
+  while(rd(SWSTAT)!=0x00000001);
+
+
+  while(rd(DFISTAT)!=0x00000001); //polling dfi_init_complete
+if(bits==64) {
+  while(rd(DCH1_DFISTAT)!=0x00000001);
+ }
+  wr(SWCTL,0x00000000);
+  wr(DFIMISC,0x00000000);
+  wr(SWCTL,0x00000001);
+  while(rd(SWSTAT)!=0x00000001);
+
+
+  wr(SWCTL,0x00000000);
+  wr(DFIMISC,0x00000001);
+  wr(SWCTL,0x00000001);
+  while(rd(SWSTAT)!=0x00000001);
+
+  //for low power,
+  wr(SWCTL,0x00000000);
+  wr(PWRCTL,0x0000000a); //[3] dfi_dram_clk_disable [1] powerdown_en
+  wr(DCH1_PWRCTL,0x0000000a);
+  wr(SWCTL,0x00000001);
+  while (rd(SWSTAT) != 0x00000001);
+  //detect until umctrl into normal state
+  while (rd(STAT) != 0x00000001);
+  if(bits==64) {
+    while(rd(DCH1_STAT) != 0x00000001);
+  }
+
+  //en phy master proto
+  wr(DFIPHYMSTR,0x14000001);
+
+#ifdef CONFIG_DDR_MSG
+    DDR_DEBUG("DFIPHYMSTR is %0x \n", rd(DFIPHYMSTR));
+    DDR_DEBUG("DFIUPD0    is %0x \n", rd(DFIUPD0));
+    DDR_DEBUG("DFIUPD1    is %0x \n", rd(DFIUPD1));
+    DDR_DEBUG("ZQCTL0     is %0x \n", rd(ZQCTL0));
+    DDR_DEBUG("ADDRMAP0     is %0x \n", rd(ADDRMAP0));
+    DDR_DEBUG("ADDRMAP1     is %0x \n", rd(ADDRMAP1));
+#endif
+}
+
+int lpddr4_reinit_ctrl(enum DDR_TYPE type, int rank_num, int speed,
+					enum DDR_BITWIDTH bits, unsigned long size)
+{
+    int ret;
+    unsigned int rdata;
+
+    //a.
+    ddr_sysreg_wr(DDR_CFG1, 0xa000011f);   //remove core clock after xx
+    wr(PWRCTL, 0x00000000); //[3] dfi_dram_clk_disable [1] powerdown_en [0]serref_en
+    wr(DCH1_PWRCTL, 0x00000000);
+
+    // use phy value stored in spl
+    //dwc_ddrphy_phyinit_regInterface(saveRegs);
+
+    //b.dis axi port
+    disable_axi_port(0x1f);
+    while (rd(PSTAT) != 0x0);
+
+#ifdef CONFIG_DDR_MSG
+    DDR_DEBUG("Axi prot idle\n");
+#endif
+    wr(DFIPHYMSTR, 0x14000000);
+    //check status.
+    while ((rd(STAT) & 0x3) == 0x03);
+
+#ifndef CONFIG_DDR_H32_MODE
+    while ((rd(STAT_DCH1) & 0x3) == 0x03);
+#endif
+    //c.poll cam empty flag
+    while ((rd(DBGCAM) & 0x36000000) != 0x36000000);
+    //d.save phy regs
+    //e.SRE
+    lpddr4_enter_selfrefresh(1, 0, 0);
+    //f.LP3 enter
+    dfi_freq_change(0x1f, 0x3);
+    //g.PwrOk disassert
+    rdata = ddr_sysreg_rd(DDR_CFG0);
+    rdata &= ~(0x1 << 6);
+    ddr_sysreg_wr(DDR_CFG0, rdata);   //Pwrokin dessert
+
+    //p.phy reset
+    rdata = ddr_sysreg_rd(DDR_CFG0);
+    rdata &= ~(0x1 << 7);
+    rdata &= 0x0;
+    ddr_sysreg_wr(DDR_CFG0, rdata);   //Phy reset .DDR_CFG0 ALL reset
+
+    //r.ddr core reset
+    rdata = ddr_sysreg_rd(DDR_CFG0);
+    rdata &= ~(0x1 << 5);
+    ddr_sysreg_wr(DDR_CFG0, rdata);   //ctrl sw reset
+
+    //s.pwr ok assert
+    rdata = ddr_sysreg_rd(DDR_CFG0);
+    rdata |= (0x1 << 6);
+    ddr_sysreg_wr(DDR_CFG0, rdata);   //Pwrokin dessert
+
+    //t.ctrl init
+    //dwc_umctl_init_skip_traing(type, rank_num, speed, bits);
+    ddr_sysreg_wr(DDR_CFG0, 0x50);  // release apb presetn
+    ddr_sysreg_wr(DDR_CFG0, 0x50);
+    ddr_sysreg_wr(DDR_CFG0, 0x50);
+    if (bits == 32) {
+        ddr_sysreg_wr(DDR_CFG0, 0x52);
+    }
+    ctrl_init(rank_num, speed);
+    addrmap(rank_num, bits);
+    ret = adjust_ddr_addrmap(type, rank_num, speed, bits, size);
+
+    // msic regu restore for str
+    dwc_ddr_misc_regu_save();
+
+    de_assert_other_reset_ddr(); //after this step, only PwrOk is staill low
+
+    dq_pinmux(bits);
+
+    //u.phy restor
+	  dwc_ddrphy_phyinit_regInterface(restoreRegs);
+
+    //v.ctrl en ,hs
+    ctrl_en_lp3_exit(bits);
+
+    //w.SRE
+    lpddr4_selfrefresh_exit(0);
+
+    //y.en auto refresh
+    enable_auto_refresh();
+ 
+    //x.en axi port
+    enable_axi_port(0x1f);
+    wr(DFIPHYMSTR, 0x14000001);
+    lpddr4_auto_selref();
+
+    if(rd(PSTAT))
+    {
+#ifdef CONFIG_DDR_MSG
+	    DDR_DEBUG("***** DDR busy in LP3 Mode *****\n");
+#endif
+    }else{
+#ifdef CONFIG_DDR_MSG
+	    DDR_DEBUG("***** AXI port idle *****\n");
+#endif
+    }
+    return ret;
+ }
+

board/thead/light-c910/spl.c

@@ -26,6 +26,11 @@
 DECLARE_GLOBAL_DATA_PTR;
 
 extern void init_ddr(void);
+#ifdef CONFIG_FIXUP_MEMORY_REGION
+extern int fixup_ddr_addrmap(unsigned long size);
+extern int query_ddr_boundary(unsigned long size);
+#endif
+extern unsigned long get_ddr_density(void);
 extern void cpu_clk_config(int cpu_freq);
 extern void sys_clk_config(void);
 extern void ddr_clk_config(int ddr_freq);
@@ -93,6 +98,25 @@ void setup_ddr_pmp(void)
 	sync_is();
 }
 
+void clear_ddr_pmp(void)
+{
+	/* restore pmp entry0,entry1 setting in bootrom */
+	writel(0x0400000000 >> 12, (void *)(PMP_BASE_ADDR + 0x104));
+	writel(0x0 >> 12, (void *)(PMP_BASE_ADDR + 0x100));
+	writel(0xffe1000000 >> 12, (void *)(PMP_BASE_ADDR + 0x10c));
+	writel(0xffe0180000 >> 12, (void *)(PMP_BASE_ADDR + 0x108));
+
+	writel(0x4040, (void *)(PMP_BASE_ADDR + 0x000));
+
+	sync_is();
+}
+
+static inline void _l2cache_ciall(void)
+{
+	asm volatile (".long 0x0170000b");
+}
+
+
 int get_rng(unsigned int *rng, int cnt)
 {
 	int i;
@@ -297,6 +321,100 @@ void setup_ddr_parity(void)
 	}
 }
 
+#ifdef CONFIG_FIXUP_MEMORY_REGION
+
+#define MAGIC_DATA (0xF4240)
+#define MAGIC_DATA2 (0x5AA5)
+#define MAGIC_DATA3 (0x3C3C)
+#define MAGIC_DATA4 (0xF0F0)
+
+/*
+return: 0: found boundary;
+*/
+int boundary_verify(unsigned long boundary) {
+	phys_addr_t verify_addr = (phys_addr_t)CONFIG_SYS_SDRAM_BASE;
+	phys_addr_t verify_addr2 = ((phys_addr_t)boundary + CONFIG_SYS_SDRAM_BASE)/4;
+	phys_addr_t verify_addr3 = ((phys_addr_t)boundary + CONFIG_SYS_SDRAM_BASE)/2;
+	phys_addr_t verify_addr4 = (phys_addr_t)boundary + CONFIG_SYS_SDRAM_BASE;
+
+	// verify data accessing result firstly
+	writel(MAGIC_DATA2, verify_addr);
+	invalidate_dcache_range(verify_addr, verify_addr + CONFIG_SYS_CACHELINE_SIZE);
+	if (readl(verify_addr) != MAGIC_DATA2) {
+		printf("ddr rw test failed\n");
+		return -1;
+	}
+	writel(MAGIC_DATA, verify_addr);  // writing at beginning
+	invalidate_dcache_range(verify_addr, verify_addr + CONFIG_SYS_CACHELINE_SIZE);
+	if (readl(verify_addr) != MAGIC_DATA) {
+		printf("ddr rw test failed\n");
+		return -1;
+	}
+	writel(MAGIC_DATA2, verify_addr2); // writing at one-quarter addr
+	writel(MAGIC_DATA3, verify_addr3); // writing at half addr
+	invalidate_dcache_range(verify_addr, verify_addr + CONFIG_SYS_CACHELINE_SIZE);
+	invalidate_dcache_range(verify_addr2, verify_addr2 + CONFIG_SYS_CACHELINE_SIZE);
+	invalidate_dcache_range(verify_addr3, verify_addr3 + CONFIG_SYS_CACHELINE_SIZE);
+
+	if (boundary == (unsigned long)MAXIMAL_DDR_DENSITY_MB * UNIT_MB) { // boundary by design
+		if ((readl(verify_addr) == MAGIC_DATA) &&
+			(readl(verify_addr2) == MAGIC_DATA2) &&
+			(readl(verify_addr3) == MAGIC_DATA3))
+			return 0;
+	}
+	else {
+		writel(MAGIC_DATA4, verify_addr4); // writing out of boundary
+		invalidate_dcache_range(verify_addr4, verify_addr4 + CONFIG_SYS_CACHELINE_SIZE);
+		if ((readl(verify_addr) == MAGIC_DATA4) && // overwrite by verify_addr4
+			(readl(verify_addr2) == MAGIC_DATA2) &&
+			(readl(verify_addr3) == MAGIC_DATA3) &&
+			(readl(verify_addr4) == MAGIC_DATA4))
+			return 0;
+	}
+
+	return -1;
+}
+
+int setup_ddr_addrmap(void)
+{
+	unsigned long boundary = (unsigned long)MAXIMAL_DDR_DENSITY_MB * UNIT_MB;
+
+	// verify data accessing result firstly
+	writel(MAGIC_DATA, (phys_addr_t)CONFIG_SYS_SDRAM_BASE);
+	invalidate_dcache_range(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_CACHELINE_SIZE);
+	if (readl((phys_addr_t)CONFIG_SYS_SDRAM_BASE) != MAGIC_DATA) {
+		printf("ddr rw test failed\n");
+		goto addrmap_err;
+	}
+	writel(MAGIC_DATA2, (phys_addr_t)CONFIG_SYS_SDRAM_BASE);
+	invalidate_dcache_range(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_CACHELINE_SIZE);
+	if (readl((phys_addr_t)CONFIG_SYS_SDRAM_BASE) != MAGIC_DATA2) {
+		printf("ddr rw test failed\n");
+		goto addrmap_err;
+	}
+
+	// try to find memory boundary
+	while (boundary >= (unsigned long)MINIMAL_DDR_DENSITY_MB * UNIT_MB) {
+		if (query_ddr_boundary(boundary) == 0) {
+			clear_ddr_pmp();
+			fixup_ddr_addrmap(boundary);
+			setup_ddr_pmp();
+			if (boundary_verify(boundary) == 0) {
+				gd->ram_size = boundary;
+				printf("found ddr boundary <0x%lx>\n", boundary);
+				return 0;
+			}
+		}
+		boundary = boundary >> 1;
+	}
+
+	gd->ram_size = get_ddr_density();
+addrmap_err:
+	printf("failed to setup ddr addrmap\n");
+	return -1;
+}
+#endif
+
 void cpu_performance_enable(void)
 {
 #define CSR_MHINT2_E	0x7cc
@@ -308,7 +426,6 @@ void cpu_performance_enable(void)
 	csr_write(CSR_MCCR2, 0xe2490009);
 	// FIXME: Clear bit[12] to disable L0BTB.
 	csr_write(CSR_MHCR, 0x17f); // clear bit7 to disable indirect brantch prediction
-	csr_write(CSR_MXSTATUS, 0x638000);
 	csr_write(CSR_MHINT, 0x6e30c | (1<<21) | (1<<22)); // set bit21 & bit 22 to close tlb & fence broadcast
 	mdelay(50); // workaround
 }
@@ -372,9 +489,9 @@ void board_init_f(ulong dummy)
 	preloader_console_init();
 
 #ifdef CONFIG_PMIC_VOL_INIT
-	ret = pmic_ddr_regu_init();
+	ret = aon_local_init();
 	if (ret) {
-		printf("%s pmic init failed %d \n",__func__,ret);
+		printf("%s aon local init failed %d \n",__func__,ret);
 		hang();
 	}
 
@@ -389,7 +506,6 @@ void board_init_f(ulong dummy)
 		printf("%s set apcpu voltage failed \n",__func__);
 		hang();
 	}
-
 #endif
 	ddr_clk_config(0);
 	cpu_clk_config(0);
@@ -398,6 +514,12 @@ void board_init_f(ulong dummy)
 	setup_ddr_scramble();
 	setup_ddr_parity();
 	setup_ddr_pmp();
+#ifdef CONFIG_FIXUP_MEMORY_REGION
+	setup_ddr_addrmap();
+#else
+	// update ram_size from board config
+	gd->ram_size = get_ddr_density();
+#endif
 
 	printf("ddr initialized, jump to uboot\n");
 	light_board_init_r(NULL, 0);

cmd/net.c

@@ -458,3 +458,22 @@ U_BOOT_CMD(
 );
 
 #endif  /* CONFIG_CMD_LINK_LOCAL */
+
+/* moved from board_init_r sequence here to save normal boot time */
+static int do_eth_init(cmd_tbl_t *cmdtp, int flag, int argc,
+			char * const argv[])
+{
+	puts("Net:   ");
+	eth_initialize();
+#if defined(CONFIG_RESET_PHY_R)
+	debug("Reset Ethernet PHY\n");
+	reset_phy();
+#endif
+	return 0;
+}
+
+U_BOOT_CMD(
+	eth,	6,	1,	do_eth_init,
+	"eth initialize",
+	""
+);

common/image-fdt.c

@@ -416,7 +416,7 @@ int boot_get_fdt(int flag, int argc, char * const argv[], uint8_t arch,
 				 * FDT blob
 				 */
 				debug("*  fdt: raw FDT blob\n");
-				printf("## Flattened Device Tree blob at %08lx\n",
+				debug("## Flattened Device Tree blob at %08lx\n",
 				       (long)fdt_addr);
 			}
 			break;
@@ -425,7 +425,7 @@ int boot_get_fdt(int flag, int argc, char * const argv[], uint8_t arch,
 			goto no_fdt;
 		}
 
-		printf("   Booting using the fdt blob at %#08lx\n", fdt_addr);
+		debug("   Booting using the fdt blob at %#08lx\n", fdt_addr);
 		fdt_blob = map_sysmem(fdt_addr, 0);
 	} else if (images->legacy_hdr_valid &&
 			image_check_type(&images->legacy_hdr_os_copy,

configs/light_a_val_android_defconfig

@@ -18,6 +18,7 @@ CONFIG_SYS_PROMPT="C910 Light# "
 CONFIG_DDR_LP4X_3733_SINGLERANK=y
 # CONFIG_DDR_LP4_3733_DUALRANK is not set
 CONFIG_DDR_BOARD_CONFIG=y
+CONFIG_FIXUP_MEMORY_REGION=n
 CONFIG_CMD_BOOT_SLAVE=y
 CONFIG_CMD_ERASEENV=y
 CONFIG_CMD_GPT=y

configs/light_a_val_defconfig

@@ -22,17 +22,18 @@ CONFIG_SYS_PROMPT="Light VAL-A# "
 CONFIG_DDR_LP4X_3733_SINGLERANK=y
 # CONFIG_DDR_LP4_3733_DUALRANK is not set
 CONFIG_DDR_BOARD_CONFIG=y
+CONFIG_FIXUP_MEMORY_REGION=y
 CONFIG_CMD_BOOT_SLAVE=y
 CONFIG_CMD_ERASEENV=y
 CONFIG_CMD_GPT=y
 CONFIG_CMD_MTD=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MEMTEST=y
 CONFIG_DDR_SCAN=y
 CONFIG_DDR_PRBS_TEST=n
-# CONFIG_DOS_PARTITION is not set
 # CONFIG_ISO_PARTITION is not set
 CONFIG_PARTITION_TYPE_GUID=y
 CONFIG_OF_EMBED=y
@@ -78,6 +79,9 @@ CONFIG_SPI=y
 CONFIG_DESIGNWARE_SPI=y
 CONFIG_DESIGNWARE_QSPI=y
 CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_DWC3=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_MANUFACTURER="U-Boot-THEAD"
@@ -108,3 +112,5 @@ CONFIG_DDR_REGU_0V6=600000
 CONFIG_DDR_REGU_0V8=800000
 CONFIG_DDR_REGU_1V1=1100000
 CONFIG_BOARD_RNG_SEED=y
+CONFIG_MISC=y
+CONFIG_LIGHT_AON_CONF=y

configs/light_a_val_sec_defconfig

@@ -18,6 +18,7 @@ CONFIG_SYS_PROMPT="C910 Light# "
 CONFIG_DDR_LP4X_3733_SINGLERANK=y
 # CONFIG_DDR_LP4_3733_DUALRANK is not set
 CONFIG_DDR_BOARD_CONFIG=y
+CONFIG_FIXUP_MEMORY_REGION=y
 # CONFIG_TPM is not set
 # CONFIG_TPM_Z32H330TC_SPI is not set
 # CONFIG_TPM_V2 is not set
@@ -34,7 +35,6 @@ CONFIG_CMD_I2C=y
 CONFIG_CMD_MEMTEST=y
 CONFIG_DDR_SCAN=y
 CONFIG_DDR_PRBS_TEST=n
-# CONFIG_DOS_PARTITION is not set
 # CONFIG_ISO_PARTITION is not set
 CONFIG_PARTITION_TYPE_GUID=y
 CONFIG_OF_EMBED=y
@@ -79,6 +79,9 @@ CONFIG_SPI=y
 CONFIG_DESIGNWARE_SPI=y
 CONFIG_DESIGNWARE_QSPI=y
 CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_DWC3=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_MANUFACTURER="U-Boot-THEAD"
@@ -96,6 +99,7 @@ CONFIG_PHY=y
 CONFIG_REGMAP=y
 CONFIG_SYSCON=y
 CONFIG_CMD_BMP=y
+CONFIG_CMD_USB=y
 CONFIG_VIDEO_BRIDGE=y
 CONFIG_DM_PCA953X=y
 CONFIG_VIDEO_VS_DPU=y
@@ -108,3 +112,5 @@ CONFIG_PMIC_VOL_INIT=y
 CONFIG_DDR_REGU_0V6=600000
 CONFIG_DDR_REGU_0V8=800000
 CONFIG_DDR_REGU_1V1=1100000
+CONFIG_MISC=y
+CONFIG_LIGHT_AON_CONF=y

configs/light_ant_ref_android_defconfig

@@ -20,6 +20,7 @@ CONFIG_DDR_LP4X_3200_SINGLERANK=y
 CONFIG_DDR_H32_MODE=y
 # CONFIG_DDR_LP4_3733_DUALRANK is not set
 CONFIG_DDR_BOARD_CONFIG=y
+CONFIG_FIXUP_MEMORY_REGION=n
 CONFIG_CMD_BOOT_SLAVE=y
 CONFIG_CMD_ERASEENV=y
 CONFIG_CMD_GPT=y

configs/light_ant_ref_defconfig

@@ -20,6 +20,7 @@ CONFIG_DDR_LP4X_3200_SINGLERANK=y
 CONFIG_DDR_H32_MODE=y
 # CONFIG_DDR_LP4_3733_DUALRANK is not set
 CONFIG_DDR_BOARD_CONFIG=y
+CONFIG_FIXUP_MEMORY_REGION=y
 CONFIG_CMD_BOOT_SLAVE=y
 CONFIG_CMD_ERASEENV=y
 CONFIG_CMD_GPT=y

configs/light_ant_ref_sec_defconfig

@@ -20,6 +20,7 @@ CONFIG_DDR_LP4X_3200_SINGLERANK=y
 CONFIG_DDR_H32_MODE=y
 # CONFIG_DDR_LP4_3733_DUALRANK is not set
 CONFIG_DDR_BOARD_CONFIG=y
+CONFIG_FIXUP_MEMORY_REGION=y
 CONFIG_CMD_BOOT_SLAVE=y
 CONFIG_CMD_ERASEENV=y
 CONFIG_CMD_GPT=y

configs/light_b_product_android_defconfig

@@ -20,6 +20,7 @@ CONFIG_DDR_LP4X_3200_SINGLERANK=y
 CONFIG_DDR_H32_MODE=y
 # CONFIG_DDR_LP4_3733_DUALRANK is not set
 CONFIG_DDR_BOARD_CONFIG=y
+CONFIG_FIXUP_MEMORY_REGION=n
 CONFIG_CMD_BOOT_SLAVE=y
 CONFIG_CMD_ERASEENV=y
 CONFIG_CMD_GPT=y

configs/light_b_product_defconfig

@@ -20,6 +20,7 @@ CONFIG_DDR_LP4X_3200_SINGLERANK=y
 CONFIG_DDR_H32_MODE=y
 # CONFIG_DDR_LP4_3733_DUALRANK is not set
 CONFIG_DDR_BOARD_CONFIG=y
+CONFIG_FIXUP_MEMORY_REGION=y
 CONFIG_CMD_BOOT_SLAVE=y
 CONFIG_CMD_ERASEENV=y
 CONFIG_CMD_GPT=y
@@ -104,3 +105,5 @@ CONFIG_PMIC_VOL_INIT=y
 CONFIG_DDR_REGU_0V6=600000
 CONFIG_DDR_REGU_0V8=800000
 CONFIG_DDR_REGU_1V1=1100000
+CONFIG_MISC=y
+CONFIG_LIGHT_AON_CONF=y

configs/light_b_product_sec_defconfig

@@ -20,6 +20,7 @@ CONFIG_DDR_LP4X_3200_SINGLERANK=y
 CONFIG_DDR_H32_MODE=y
 # CONFIG_DDR_LP4_3733_DUALRANK is not set
 CONFIG_DDR_BOARD_CONFIG=y
+CONFIG_FIXUP_MEMORY_REGION=y
 CONFIG_CMD_BOOT_SLAVE=y
 CONFIG_CMD_ERASEENV=y
 CONFIG_CMD_GPT=y
@@ -104,3 +105,5 @@ CONFIG_PMIC_VOL_INIT=y
 CONFIG_DDR_REGU_0V6=600000
 CONFIG_DDR_REGU_0V8=800000
 CONFIG_DDR_REGU_1V1=1100000
+CONFIG_MISC=y
+CONFIG_LIGHT_AON_CONF=y

configs/light_beagle_android_defconfig

@@ -19,6 +19,7 @@ CONFIG_SYS_PROMPT="C910 Light# "
 CONFIG_DDR_LP4X_3733_SINGLERANK=y
 # CONFIG_DDR_LP4_3733_DUALRANK is not set
 CONFIG_DDR_BOARD_CONFIG=y
+CONFIG_FIXUP_MEMORY_REGION=n
 CONFIG_CMD_BOOT_SLAVE=y
 CONFIG_CMD_ERASEENV=y
 CONFIG_CMD_GPT=y
@@ -114,4 +115,4 @@ CONFIG_ANDROID_AB=y
 CONFIG_CMD_AB_SELECT=y
 CONFIG_XBC=y
 CONFIG_BOARD_RNG_SEED=y
-CONFIG_SPL_TEXT_BASE=0xffe0000800
+CONFIG_SPL_TEXT_BASE=0xffe0000800

configs/light_beagle_defconfig

@@ -99,3 +99,6 @@ CONFIG_VIDEO_DW_DPHY=y
 CONFIG_OF_LIBFDT_OVERLAY=y
 # CONFIG_EFI_LOADER is not set
 CONFIG_BOARD_RNG_SEED=y
+CONFIG_FIXUP_MEMORY_REGION=y
+CONFIG_MISC=y
+CONFIG_LIGHT_AON_CONF=y

configs/light_huiwei_defconfig

@@ -0,0 +1,137 @@
+CONFIG_RISCV=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_ENV_SIZE=0x20000
+CONFIG_ENV_OFFSET=0xe0000
+CONFIG_NR_DRAM_BANKS=8
+CONFIG_SPL=y
+CONFIG_SMP=y
+CONFIG_TARGET_LIGHT_C910=y
+CONFIG_TARGET_LIGHT_FM_C910_LPI4A=y
+# CONFIG_THEAD_PLIC is not set
+# CONFIG_THEAD_LIGHT_TIMER is not set
+# CONFIG_THEAD_LIGHT_DIGITAL_SENSOR is not set
+CONFIG_ARCH_RV64I=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_BUILD_TARGET="u-boot-with-spl.bin"
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_DISPLAY_BOARDINFO=y
+# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
+CONFIG_SPL_RAM_SUPPORT=y
+CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SYS_PROMPT="Light huiwei# "
+CONFIG_DDR_LP4X_3733_DUALRANK=y
+# CONFIG_DDR_LP4_3733_DUALRANK is not set
+CONFIG_DDR_BOARD_CONFIG=y
+CONFIG_FIXUP_MEMORY_REGION=y
+CONFIG_CMD_BOOT_SLAVE=y
+CONFIG_CMD_ERASEENV=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_DDR_SCAN=y
+CONFIG_DDR_PRBS_TEST=n
+# CONFIG_ISO_PARTITION is not set
+CONFIG_PARTITION_TYPE_GUID=y
+CONFIG_OF_EMBED=y
+CONFIG_DEFAULT_DEVICE_TREE="light-huiwei"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SPL_CLK=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_UDP_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x10000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_DW=y
+CONFIG_DWAPB_GPIO=y
+# CONFIG_MMC_SPI is not set
+CONFIG_MMC_VERBOSE=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_SNPS=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SNPS=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MMC_RPMB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_SPI_NAND=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_PHY_REALTEK=y
+CONFIG_RTL8211E_PINE64_GIGABIT_FIX=y
+CONFIG_RTL8211X_PHY_FORCE_MASTER=y
+CONFIG_RTL8211F_PHY_FORCE_EEE_RXC_ON=y
+CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_DESIGNWARE_SPI=y
+CONFIG_DESIGNWARE_QSPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="U-Boot-THEAD"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1234
+CONFIG_USB_GADGET_PRODUCT_NUM=0x8888
+CONFIG_USB_FUNCTION_MASS_STORAGE=y
+# CONFIG_SPL_USE_TINY_PRINTF is not set
+# CONFIG_EFI_LOADER is not set
+# CONFIG_LIGHT_SEC_BOOT is not set
+CONFIG_DEFAULT_FDT_FILE="thead/th1520-huiwei-product.dtb"
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_DM_VIDEO=y
+CONFIG_PHY=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_USB=y
+CONFIG_VIDEO_BRIDGE=y
+CONFIG_DM_PCA953X=y
+CONFIG_VIDEO_VS_DPU=y
+CONFIG_VIDEO_LCD_ILITEK_ILI9881C=n
+CONFIG_VIDEO_LCD_JD9365DA=y
+#CONFIG_VIDEO_LCD_CUSTOM_LOGO=y
+CONFIG_VIDEO_DW_DSI_LIGHT=y
+CONFIG_VIDEO_DW_DPHY=y
+CONFIG_VIDEO_DW_DSI_HOST=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_PMIC_VOL_INIT=y
+CONFIG_DDR_REGU_0V6=600000
+CONFIG_DDR_REGU_0V8=800000
+CONFIG_DDR_REGU_1V1=1100000
+CONFIG_BOARD_RNG_SEED=y
+CONFIG_MISC=y
+CONFIG_LIGHT_AON_CONF=y
+CONFIG_TPM=y
+CONFIG_TPM_V2=y
+CONFIG_TPM_Z32H330TC_SPI=y
+CONFIG_CMD_TPM=y
+CONFIG_CMD_TPM_V2=y
+CONFIG_CMD_TPM_TEST=y
+CONFIG_DM_CHARGE_DISPLAY=y
+CONFIG_CHARGE_ANIMATION=y
+CONFIG_DM_FUEL_GAUGE=y
+CONFIG_POWER_FG_CW201X=y
+CONFIG_CHARGER_BQ25700=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_DM_MCU=y
+CONFIG_MCU_HC32fX=y
+CONFIG_DM_POWER_DELIVERY=y
+CONFIG_TYPEC_TCPM=y
+CONFIG_TYPEC_TCPCI=y
+CONFIG_TYPEC_HUSB311=y

configs/light_lpi4a_16g_defconfig

@@ -109,3 +109,6 @@ CONFIG_DDR_REGU_0V6=600000
 CONFIG_DDR_REGU_0V8=800000
 CONFIG_DDR_REGU_1V1=1100000
 CONFIG_BOARD_RNG_SEED=y
+CONFIG_FIXUP_MEMORY_REGION=y
+CONFIG_MISC=y
+CONFIG_LIGHT_AON_CONF=y

configs/light_lpi4a_android_defconfig

@@ -19,6 +19,7 @@ CONFIG_SYS_PROMPT="C910 Light# "
 CONFIG_DDR_LP4X_3733_DUALRANK=y
 # CONFIG_DDR_LP4_3733_DUALRANK is not set
 CONFIG_DDR_BOARD_CONFIG=y
+CONFIG_FIXUP_MEMORY_REGION=n
 CONFIG_CMD_BOOT_SLAVE=y
 CONFIG_CMD_ERASEENV=y
 CONFIG_CMD_GPT=y

configs/light_lpi4a_cluster_16g_defconfig

@@ -109,3 +109,6 @@ CONFIG_DDR_REGU_0V6=600000
 CONFIG_DDR_REGU_0V8=800000
 CONFIG_DDR_REGU_1V1=1100000
 CONFIG_BOARD_RNG_SEED=y
+CONFIG_FIXUP_MEMORY_REGION=y
+CONFIG_MISC=y
+CONFIG_LIGHT_AON_CONF=y

configs/light_lpi4a_cluster_defconfig

@@ -108,3 +108,6 @@ CONFIG_DDR_REGU_0V6=600000
 CONFIG_DDR_REGU_0V8=800000
 CONFIG_DDR_REGU_1V1=1100000
 CONFIG_BOARD_RNG_SEED=y
+CONFIG_FIXUP_MEMORY_REGION=y
+CONFIG_MISC=y
+CONFIG_LIGHT_AON_CONF=y

configs/light_lpi4a_console_16g_defconfig

@@ -109,3 +109,6 @@ CONFIG_DDR_REGU_0V6=600000
 CONFIG_DDR_REGU_0V8=800000
 CONFIG_DDR_REGU_1V1=1100000
 CONFIG_BOARD_RNG_SEED=y
+CONFIG_FIXUP_MEMORY_REGION=y
+CONFIG_MISC=y
+CONFIG_LIGHT_AON_CONF=y

configs/light_lpi4a_console_defconfig

@@ -108,3 +108,6 @@ CONFIG_DDR_REGU_0V6=600000
 CONFIG_DDR_REGU_0V8=800000
 CONFIG_DDR_REGU_1V1=1100000
 CONFIG_BOARD_RNG_SEED=y
+CONFIG_FIXUP_MEMORY_REGION=y
+CONFIG_MISC=y
+CONFIG_LIGHT_AON_CONF=y

configs/light_lpi4a_defconfig

@@ -22,6 +22,7 @@ CONFIG_SYS_PROMPT="Light LPI4A# "
 CONFIG_DDR_LP4X_3733_DUALRANK=y
 # CONFIG_DDR_LP4_3733_DUALRANK is not set
 CONFIG_DDR_BOARD_CONFIG=y
+CONFIG_FIXUP_MEMORY_REGION=y
 CONFIG_CMD_BOOT_SLAVE=y
 CONFIG_CMD_ERASEENV=y
 CONFIG_CMD_GPT=y
@@ -32,7 +33,6 @@ CONFIG_CMD_I2C=y
 CONFIG_CMD_MEMTEST=y
 CONFIG_DDR_SCAN=y
 CONFIG_DDR_PRBS_TEST=n
-# CONFIG_DOS_PARTITION is not set
 # CONFIG_ISO_PARTITION is not set
 CONFIG_PARTITION_TYPE_GUID=y
 CONFIG_OF_EMBED=y
@@ -78,6 +78,9 @@ CONFIG_SPI=y
 CONFIG_DESIGNWARE_SPI=y
 CONFIG_DESIGNWARE_QSPI=y
 CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_DWC3=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_MANUFACTURER="U-Boot-THEAD"
@@ -95,10 +98,13 @@ CONFIG_PHY=y
 CONFIG_REGMAP=y
 CONFIG_SYSCON=y
 CONFIG_CMD_BMP=y
+CONFIG_CMD_USB=y
 CONFIG_VIDEO_BRIDGE=y
 CONFIG_DM_PCA953X=y
 CONFIG_VIDEO_VS_DPU=y
-CONFIG_VIDEO_LCD_ILITEK_ILI9881C=y
+CONFIG_VIDEO_LCD_ILITEK_ILI9881C=n
+CONFIG_VIDEO_LCD_JD9365DA=y
+#CONFIG_VIDEO_LCD_CUSTOM_LOGO=y
 CONFIG_VIDEO_DW_DSI_LIGHT=y
 CONFIG_VIDEO_DW_DPHY=y
 CONFIG_VIDEO_DW_DSI_HOST=y
@@ -108,3 +114,5 @@ CONFIG_DDR_REGU_0V6=600000
 CONFIG_DDR_REGU_0V8=800000
 CONFIG_DDR_REGU_1V1=1100000
 CONFIG_BOARD_RNG_SEED=y
+CONFIG_MISC=y
+CONFIG_LIGHT_AON_CONF=y

configs/light_lpi4a_sec_defconfig

@@ -22,6 +22,7 @@ CONFIG_SYS_PROMPT="C910 Light# "
 CONFIG_DDR_LP4X_3733_DUALRANK=y
 # CONFIG_DDR_LP4_3733_DUALRANK is not set
 CONFIG_DDR_BOARD_CONFIG=y
+CONFIG_FIXUP_MEMORY_REGION=y
 CONFIG_CMD_BOOT_SLAVE=y
 CONFIG_CMD_ERASEENV=y
 CONFIG_CMD_GPT=y
@@ -32,7 +33,6 @@ CONFIG_CMD_I2C=y
 CONFIG_CMD_MEMTEST=y
 CONFIG_DDR_SCAN=y
 CONFIG_DDR_PRBS_TEST=n
-# CONFIG_DOS_PARTITION is not set
 # CONFIG_ISO_PARTITION is not set
 CONFIG_PARTITION_TYPE_GUID=y
 CONFIG_OF_EMBED=y
@@ -77,6 +77,9 @@ CONFIG_SPI=y
 CONFIG_DESIGNWARE_SPI=y
 CONFIG_DESIGNWARE_QSPI=y
 CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_DWC3=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_MANUFACTURER="U-Boot-THEAD"
@@ -93,10 +96,13 @@ CONFIG_PHY=y
 CONFIG_REGMAP=y
 CONFIG_SYSCON=y
 CONFIG_CMD_BMP=y
+CONFIG_CMD_USB=y
 CONFIG_VIDEO_BRIDGE=y
 CONFIG_DM_PCA953X=y
 CONFIG_VIDEO_VS_DPU=y
-CONFIG_VIDEO_LCD_ILITEK_ILI9881C=y
+CONFIG_VIDEO_LCD_ILITEK_ILI9881C=n
+CONFIG_VIDEO_LCD_JD9365DA=y
+#CONFIG_VIDEO_LCD_CUSTOM_LOGO=y
 CONFIG_VIDEO_DW_DSI_LIGHT=y
 CONFIG_VIDEO_DW_DPHY=y
 CONFIG_VIDEO_DW_DSI_HOST=y
@@ -105,3 +111,5 @@ CONFIG_PMIC_VOL_INIT=y
 CONFIG_DDR_REGU_0V6=600000
 CONFIG_DDR_REGU_0V8=800000
 CONFIG_DDR_REGU_1V1=1100000
+CONFIG_MISC=y
+CONFIG_LIGHT_AON_CONF=y

configs/light_milkv_meles_dualrank_defconfig

@@ -88,3 +88,6 @@ CONFIG_SYS_WHITE_ON_BLACK=y
 CONFIG_OF_LIBFDT_OVERLAY=y
 # CONFIG_EFI_LOADER is not set
 CONFIG_BOARD_RNG_SEED=y
+CONFIG_FIXUP_MEMORY_REGION=y
+CONFIG_MISC=y
+CONFIG_LIGHT_AON_CONF=y

configs/light_milkv_meles_singlerank_defconfig

@@ -88,3 +88,6 @@ CONFIG_SYS_WHITE_ON_BLACK=y
 CONFIG_OF_LIBFDT_OVERLAY=y
 # CONFIG_EFI_LOADER is not set
 CONFIG_BOARD_RNG_SEED=y
+CONFIG_FIXUP_MEMORY_REGION=y
+CONFIG_MISC=y
+CONFIG_LIGHT_AON_CONF=y

drivers/Kconfig

@@ -130,6 +130,8 @@ source "drivers/w1-eeprom/Kconfig"
 
 source "drivers/watchdog/Kconfig"
 
+source "drivers/mcu/Kconfig"
+
 config PHYS_TO_BUS
 	bool "Custom physical to bus address mapping"
 	help

drivers/Makefile

@@ -85,6 +85,7 @@ obj-y += misc/
 obj-$(CONFIG_MMC) += mmc/
 obj-$(CONFIG_NVME) += nvme/
 obj-$(CONFIG_PCI_ENDPOINT) += pci_endpoint/
+obj-$(CONFIG_DM_POWER_DELIVERY) += power/power_delivery/
 obj-y += dfu/
 obj-$(CONFIG_PCH) += pch/
 obj-y += phy/allwinner/

drivers/fastboot/fb_command.c

@@ -310,6 +310,7 @@ static void flash(char *cmd_parameter, char *response)
 	char cmdbuf[32];
 	u32 block_cnt;
 	struct blk_desc *dev_desc;
+	disk_partition_t info;
 	int ret = 0;
 
 	if (strcmp(cmd_parameter, "uboot") == 0) {
@@ -351,8 +352,25 @@ static void flash(char *cmd_parameter, char *response)
 		memcpy((void *)LIGHT_TF_FW_ADDR, fastboot_buf_addr, image_size);
 	} else if ((strcmp(cmd_parameter, TEE_PART_NAME) == 0)) {
 		memcpy((void *)LIGHT_TEE_FW_ADDR, fastboot_buf_addr, image_size);
+	} else if ((strcmp(cmd_parameter, "boot") == 0)) {
+		dev_desc = blk_get_dev("mmc", CONFIG_FASTBOOT_FLASH_MMC_DEV);
+		if (!dev_desc || dev_desc->type == DEV_TYPE_UNKNOWN) {
+			fastboot_fail("invalid mmc device", response);
+			return;
+        }
+		/* if fastresume partition exists, earse the old image header */
+		if(part_get_info_by_name(dev_desc, "fastresume", &info)) {
+			printf(" find fastresume partition , erase the header:\n");
+			char * buf = memalign(CONFIG_SYS_CACHELINE_SIZE,4096);
+			if(!buf) {
+				printf(" fastresume partition header mem alloc failed\n");
+				return;
+			}
+			memset(buf,0xff,4096);
+			blk_dwrite(dev_desc, info.start, 4096/info.blksz, buf);
+			free(buf);
+		}
 	}
-
 	if(strcmp(cmd_parameter, "uboot") == 0 || (strcmp(cmd_parameter, "fw") == 0) ||
 	   (strcmp(cmd_parameter, "uImage") == 0) || (strcmp(cmd_parameter, "dtb") == 0) ||
 	   (strcmp(cmd_parameter, "rootfs") == 0) || (strcmp(cmd_parameter, "aon") == 0)) {

drivers/mcu/Kconfig

@@ -0,0 +1,15 @@
+menu "MCU Support"
+
+config DM_MCU
+	bool "Enable driver model for mcu device support"
+	depends on DM
+	help
+	  This adds a simple uclass for mcu device.
+	  
+config MCU_HC32fX
+	bool "Enable HC32fX MCU support"
+	depends on DM_MCU
+	help
+	  This adds a driver for the HC32fX MCU support.
+
+endmenu

drivers/mcu/Makefile

@@ -0,0 +1,9 @@
+#
+# Copyright (c) 2015 Google, Inc
+# Written by Simon Glass <sjg@chromium.org>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-$(CONFIG_DM_MCU)	+= mcu-uclass.o
+obj-$(CONFIG_MCU_HC32fX) += mcu_hc32fx.o

drivers/mcu/mcu-uclass.c

@@ -0,0 +1,65 @@
+/*
+ * Copyright (c) 2015 Google, Inc
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <mcu/mcu-uclass.h>
+#include <dm/root.h>
+#include <dm/uclass-internal.h>
+
+int _mcu_shutdown(struct udevice *dev)
+{
+	struct mcu_ops *ops = dev_get_driver_ops(dev);
+
+	if (!ops->shutdown)
+		return -ENOSYS;
+
+	return ops->shutdown(dev);
+}
+
+int _mcu_poweron(struct udevice *dev)
+{
+	struct mcu_ops *ops = dev_get_driver_ops(dev);
+
+	if (!ops->poweron)
+		return -ENOSYS;
+
+	return ops->poweron(dev);
+}
+
+int mcu_poweron(void)
+{
+	struct udevice *mcu;
+	int ret;
+
+	ret = uclass_get_device(UCLASS_MCU, 0, &mcu);
+	if (ret) {
+		printf("Get UCLASS_MCU failed, ret=%d\n", ret);
+		return ret;
+	}
+
+	return _mcu_poweron(mcu);
+}
+
+int mcu_shutdown(void)
+{
+	struct udevice *mcu;
+	int ret;
+
+	ret = uclass_get_device(UCLASS_MCU, 0, &mcu);
+	if (ret) {
+		printf("Get charge display failed, ret=%d\n", ret);
+		return ret;
+	}
+
+	return _mcu_shutdown(mcu);
+}
+
+UCLASS_DRIVER(mcu) = {
+	.id		= UCLASS_MCU,
+	.name		= "mcu",
+};

drivers/mcu/mcu_hc32fx.c

@@ -0,0 +1,97 @@
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <mcu/mcu-uclass.h>
+#include <dm/lists.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define HC32FX_POWEROFF_20    0x20
+#define HC32FX_POWERON_30    0x30
+#define POWER_OFF   0x55
+#define POWER_ON   0x01
+
+struct hc32fx_info {
+	struct udevice *dev;
+};
+
+static u8 hc32fx_read(struct hc32fx_info *hc32fx, u8 reg)
+{
+	u8 val;
+	int ret;
+
+	ret = dm_i2c_read(hc32fx->dev, reg, &val, 1);
+	if (ret) {
+		printf("write error to device: %p register: %#x!",
+		      hc32fx->dev, reg);
+		return ret;
+	}
+
+	return val;
+}
+
+static int hc32fx_write(struct hc32fx_info *hc32fx, u8 reg, u8 val)
+{
+	int ret;
+
+	ret = dm_i2c_write(hc32fx->dev, reg, &val, 1);
+	if (ret) {
+		printf("write error to device: %p register: %#x!",
+		      hc32fx->dev, reg);
+		return ret;
+	}
+
+	return 0;
+}
+
+static int mcu_hc32fx_poweron(struct udevice *dev)
+{
+	struct hc32fx_info *hc32fx = dev_get_priv(dev);
+	int ret;
+
+	ret = hc32fx_write(hc32fx, HC32FX_POWERON_30, POWER_ON);
+	if(ret)
+		printf("set mcu POWERON fail\n");
+
+	return ret;
+}
+
+static int mcu_hc32fx_shutdown(struct udevice *dev)
+{
+	struct hc32fx_info *hc32fx = dev_get_priv(dev);
+	int ret;
+
+	ret = hc32fx_write(hc32fx, HC32FX_POWEROFF_20, POWER_OFF);
+	if(ret)
+		printf("set mcu POWEROFF fail\n");
+
+	return ret;
+}
+
+static int mcu_gpio_probe(struct udevice *dev)
+{
+	struct hc32fx_info *priv = dev_get_priv(dev);
+	priv->dev = dev;
+
+	return 0;
+}
+
+static const struct mcu_ops mcu_hc32fx_ops = {
+	.poweron	= mcu_hc32fx_poweron,
+	.shutdown	= mcu_hc32fx_shutdown,
+};
+
+static const struct udevice_id hc32fx_ops_ids[] = {
+	{ .compatible = "mcu_hc32fx" },
+	{ }
+};
+
+U_BOOT_DRIVER(mcu_gpio) = {
+	.name	= "hc32fx-mcu",
+	.id	= UCLASS_MCU,
+	.of_match = hc32fx_ops_ids,
+	.ops	= &mcu_hc32fx_ops,
+	.priv_auto_alloc_size = sizeof(struct hc32fx_info),
+	.probe	= mcu_gpio_probe,
+};

drivers/misc/Kconfig

@@ -439,4 +439,10 @@ config K3_AVS0
 	  optimized voltage from the efuse, so that it can be programmed
 	  to the PMIC on board.
 
+config LIGHT_AON_CONF
+	bool "Light aon config support"
+	depends on MISC
+	help
+	  Select this to enable aon config by dts.
+
 endmenu

drivers/misc/Makefile

@@ -68,3 +68,4 @@ obj-$(CONFIG_WINBOND_W83627) += winbond_w83627.o
 obj-$(CONFIG_JZ4780_EFUSE) += jz4780_efuse.o
 obj-$(CONFIG_MICROCHIP_FLEXCOM) += microchip_flexcom.o
 obj-$(CONFIG_K3_AVS0) += k3_avs.o
+obj-$(CONFIG_LIGHT_AON_CONF) += light_regu.o

drivers/misc/light_regu.h

@@ -0,0 +1,271 @@
+#ifndef __LIGHT_REGU_H__
+#define __LIGHT_REGU_H__
+
+typedef enum
+{
+	SOC_DVDD18_AON,		  /*da9063:  ldo-3 */
+	SOC_AVDD33_USB3,	  /*da9063:  ldo-9 */
+	SOC_DVDD08_AON,		  /*da9063:  ldo-2 */
+	SOC_APCPU_DVDD_DVDDM, /*da9063:  vbcore1 & vbcore2*/
+	SOC_DVDD08_DDR,		  /*da9063:  buckperi */
+	SOC_VDD_DDR_1V8,	  /*da9063:  ldo-4  */
+	SOC_VDD_DDR_1V1,	  /*da9063:  buckmem & buckio  */
+	SOC_VDD_DDR_0V6,	  /*da9063:  buckpro */
+	SOC_DVDD18_AP,		  /*da9063:  ldo-11 */
+	SOC_DVDD08_AP,		  /*da9121:  da9121_ex */
+	SOC_AVDD08_MIPI_HDMI, /*da9063:  ldo-1  */
+	SOC_AVDD18_MIPI_HDMI, /*da9063:  ldo-5  */
+	SOC_DVDD33_EMMC,	  /*da9063:  ldo-10 */
+	SOC_DVDD18_EMMC,	  /*slg51000:ldo-3 */
+	SOC_DOVDD18_SCAN,	  /*da9063:  ldo-6 */
+	SOC_VEXT_2V8,		  /*da9063:  ldo-7 */
+	SOC_DVDD12_SCAN,	  /*da9063:  ldo-8 */
+	SOC_AVDD28_SCAN_EN,	  /*da9063:  gpio-4,SGM2019-ADJ */
+	SOC_AVDD28_RGB,		  /*slg51000:ldo-1 */
+	SOC_DOVDD18_RGB,	  /*slg51000:ldo-4 */
+	SOC_DVDD12_RGB,		  /*slg51000:ldo-5 */
+	SOC_AVDD25_IR,		  /*slg51000:ldo-2 */
+	SOC_DOVDD18_IR,		  /*slg51000:ldo-7 */
+	SOC_DVDD12_IR,		  /*slg51000:ldo-6 */
+	SOC_ADC_VREF,
+	SOC_LCD0_EN,
+	SOC_VEXT_1V8,
+
+	SOC_REGU_INVALID = 0xFF
+} soc_virtual_id_en;
+
+#define REGU_DTS_NAME "light-regu-reg"
+#define AON_CONF_NAME "aon_pmic_config"
+#define PMIC_DEV_DTS_NAME "pmic-dev"
+#define PMIC_PARENT_CTRL_NAME "pmic_ctrl_info"
+#define REGU_ID_CONF_NAME "regu_config"
+#define REGU_ID_NAME "regu_id"
+#define COUPLING_ID_INFO_NAME "coupling_info"
+
+#define PMIC_DEV_ENABLE_WDT (1U << 0)
+#define PMIC_DEV_ENABLE_ERR_IO (1U << 1)
+#define PMIC_DEV_ENABLE_LPM_IO (1U << 2)
+
+#define HW_ID_NO_SOFT_AUTO_ON (0xff)
+#define HW_ID_NO_SOFT_AUTO_OFF (0xff)
+#define HW_ID_INVALID (0xff)
+#define PMIC_ID_INVALID (0xff)
+#define REGU_SUB_ID_INVALID (0xff)
+
+#define REGU_EXT_ID_NAME_LEN 30
+#define PMIC_DEV_NAME_LEN 20
+#define PMIC_DEV_VERSION_LEN 20
+
+#define PMIC_MAX_HW_ID_NUM 3
+#define PMIC_MAX_COUPLING_NUM 3
+
+#define AON_WAKEUP_BY_GPIO (1 << 0)
+#define AON_WAKEUP_BY_RTC (1 << 1)
+
+#define AON_CONFIG_MAGIC "AON_CONFIG"
+#define UBOOT_CONFIG_MAGIC "UBOOT_SET"
+#define AON_CONFIG_VERSION "1.0.0"
+
+typedef enum
+{
+	HW_ID_ACTIVATE_HIGH = 0U,
+	HW_ID_ACTIVATE_LOW = 1U,
+} hw_activate_status_en;
+
+typedef struct __packed
+{
+	uint8_t pmic_id;
+	uint8_t io_hw_id;
+	uint8_t activate_status;
+} pmic_parent_hw_io_ctrl_info_t;
+
+typedef struct __packed
+{
+	uint8_t on_order;
+	uint8_t on_delay_ms;
+	uint32_t init_target_uv;
+} regu_soft_power_ctrl_on_t;
+
+typedef struct __packed
+{
+	uint8_t off_order;
+	uint8_t off_delay_ms;
+} regu_soft_power_ctrl_off_t;
+
+typedef struct __packed
+{
+	regu_soft_power_ctrl_on_t on_info;
+	regu_soft_power_ctrl_off_t off_info;
+} regu_soft_power_ctrl_t;
+
+typedef struct __packed
+{
+	uint8_t id0;
+	uint8_t id1;
+	int8_t max_spread; // mv/10
+	int8_t min_spread; // mv/10
+} coupling_desc_t;
+
+typedef enum
+{
+	GPIO_IRQ_MODE_RISING_EDGE = 0, ///< Interrupt mode for rising edge
+	GPIO_IRQ_MODE_FALLING_EDGE,	   ///< Interrupt mode for falling edge
+	GPIO_IRQ_MODE_BOTH_EDGE,	   ///< Interrupt mode for both edge
+	GPIO_IRQ_MODE_LOW_LEVEL,	   ///< Interrupt mode for low level
+	GPIO_IRQ_MODE_HIGH_LEVEL,	   ///< Interrupt mode for high level
+} csi_gpio_irq_mode_t;
+
+typedef enum
+{
+	IIC_ADDRESS_7BIT = 0U, ///< 7-bit address mode
+	IIC_ADDRESS_10BIT	   ///< 10-bit address mode
+} csi_iic_addr_mode_t;
+
+typedef enum
+{
+	IIC_BUS_SPEED_STANDARD = 0U, ///< Standard Speed  (<=100kHz)
+	IIC_BUS_SPEED_FAST,			 ///< Fast Speed      (<=400kHz)
+	IIC_BUS_SPEED_FAST_PLUS,	 ///< Fast plus Speed (<=  1MHz)
+	IIC_BUS_SPEED_HIGH			 ///< High Speed      (<=3.4MHz)
+} csi_iic_speed_t;
+
+typedef struct __packed
+{
+	uint8_t pmic_id;
+	uint8_t hw_id;
+	uint8_t benable;
+	pmic_parent_hw_io_ctrl_info_t parent_hw_info;
+	regu_soft_power_ctrl_t soft_power_ctrl_info;
+} pmic_hw_info_t;
+
+typedef struct __packed
+{
+	coupling_desc_t coupling_list[PMIC_MAX_COUPLING_NUM];
+	pmic_hw_info_t id[PMIC_MAX_HW_ID_NUM]; ///<  sub id1 for single-rail or first src of dual-rail
+} pmic_hw_id_t;
+
+typedef struct __packed
+{
+	uint8_t regu_ext_id;						 ///< virtual global regulator id
+	char regu_ext_id_name[REGU_EXT_ID_NAME_LEN]; ///< vitual regu-id name
+	pmic_hw_id_t sub;							 ///<  sub id set for dual-rail/single-rail regulator
+} csi_regu_id_t;
+
+typedef enum
+{
+	PMIC_CTRL_BY_AON_GPIO = 0U,
+	PMIC_CTRL_BY_PMIC_GPIO = 1U,
+	PMIC_CTRL_BY_NOTHINTG = 0xFF,
+} pmic_ctrl_info_en;
+
+typedef struct __packed
+{
+	uint8_t gpio_port;
+	uint8_t pin;
+	uint8_t activate_status;
+} pmic_ctrl_by_aon_info_t;
+
+typedef struct __packed
+{
+	uint8_t pmic_id;
+	uint8_t io_hw_id;
+	uint8_t activate_status;
+} pmic_ctrl_by_pmic_info_t;
+
+typedef struct __packed
+{
+	uint8_t pmic_ctrl_type;
+	union
+	{
+		pmic_ctrl_by_aon_info_t aon_io;
+		pmic_ctrl_by_pmic_info_t pmic_io;
+	} info;
+} pmic_parent_ctrl_info_t;
+
+typedef struct __packed
+{
+	uint8_t gpio_port;
+	uint8_t pin;
+	uint8_t trigger_mode;
+} pmic_interrupt_io_info_t;
+
+typedef struct __packed
+{
+	char device_name[PMIC_DEV_NAME_LEN];
+	char version_name[PMIC_DEV_VERSION_LEN];
+	uint8_t pmic_id;
+	uint8_t addr1;
+	uint8_t addr2;
+	uint8_t flag; /*support wdt|errio| lpm io*/
+	uint8_t slew_rate;
+	uint32_t wdt_len;
+	pmic_interrupt_io_info_t err_io_info;
+	pmic_interrupt_io_info_t lpm_io_info;
+	pmic_parent_ctrl_info_t ctrl_info;
+} pmic_dev_info_t;
+
+typedef struct
+{
+	soc_virtual_id_en id;
+	char virtual_id_name[REGU_EXT_ID_NAME_LEN];
+	int min_uv;
+	int max_uv;
+} soc_virtual_id_t;
+
+typedef struct
+{
+	int regu_num;
+	soc_virtual_id_t *regu_list;
+} virtual_regu_list_t;
+
+typedef struct
+{
+	int pmic_num;
+	pmic_dev_info_t *pmic_list;
+} pmic_dev_list_t;
+
+typedef struct
+{
+	int regu_id_num;
+	csi_regu_id_t *regu_id_list;
+} regu_id_list_t;
+
+typedef struct __packed
+{
+	uint8_t iic_id;	   ///< iic id
+	uint8_t addr_mode; ///< iic addr_mode  ---> csi_iic_addr_mode_t
+	uint8_t speed;	   ///< iic speed type  ---> csi_iic_speed_t
+	uint8_t reserved[1];
+} csi_pmic_if_config_t;
+
+struct mic_regu_platdata
+{
+	const char *name;
+	uint32_t wakeup_flag;
+	csi_pmic_if_config_t iic_config;
+	virtual_regu_list_t regu_list;
+	pmic_dev_list_t pmic_list;
+	regu_id_list_t regu_id_list;
+};
+
+typedef struct __packed
+{
+	csi_pmic_if_config_t iic_config;
+	uint8_t pmic_dev_num;
+	uint8_t regu_num;
+	uint32_t pmic_dev_list_offset;
+	uint32_t regu_id_list_offset;
+} aon_pmic_config_t;
+
+typedef struct __packed
+{
+	const char magic[11];
+	const char version[11];
+	const char uboot_set_magic[11];
+	uint8_t max_hw_id_num;
+	uint64_t aon_config_partition_size;
+	uint32_t wakeup_flag;
+	aon_pmic_config_t aon_pmic;
+} aon_config_t;
+
+#endif

drivers/misc/misc-uclass.c

@@ -13,7 +13,6 @@
  * general classes. A set of generic read, write and ioctl methods may
  * be used to access the device.
  */
-
 int misc_read(struct udevice *dev, int offset, void *buf, int size)
 {
 	const struct misc_ops *ops = device_get_ops(dev);

drivers/mmc/sdhci.c

@@ -38,9 +38,7 @@ static void sdhci_reset(struct sdhci_host *host, u8 mask)
 		timeout--;
 		udelay(1000);
 	}
-#ifdef CONFIG_TARGET_LIGHT_C910
-	mdelay(50);
-#endif
+
 }
 
 static void sdhci_cmd_done(struct sdhci_host *host, struct mmc_cmd *cmd)

drivers/power/Kconfig

@@ -2,10 +2,22 @@ menu "Power"
 
 source "drivers/power/domain/Kconfig"
 
+source "drivers/power/fuel_gauge/Kconfig"
+
 source "drivers/power/pmic/Kconfig"
 
 source "drivers/power/regulator/Kconfig"
 
+source "drivers/power/charge/Kconfig"
+
+source "drivers/power/power_delivery/Kconfig"
+
+config DM_CHARGE_DISPLAY
+	bool "Enable driver model for charge display support"
+	depends on DM
+	help
+	  This adds a simple uclass for charge display.
+	  
 choice
 	prompt "Select Sunxi PMIC Variant"
 	depends on ARCH_SUNXI
@@ -72,6 +84,13 @@ config SY8106A_POWER
 
 endchoice
 
+config CHARGE_ANIMATION
+	bool "Enable charge animation"
+	depends on DM_CHARGE_DISPLAY && DM_FUEL_GAUGE
+	select ARM_CPU_SUSPEND
+	help
+	  This adds a simple function for charge animation display.
+
 config AXP_DCDC1_VOLT
 	int "axp pmic dcdc1 voltage"
 	depends on AXP221_POWER || AXP809_POWER || AXP818_POWER

drivers/power/Makefile

@@ -3,11 +3,14 @@
 # Copyright (c) 2009 Wind River Systems, Inc.
 # Tom Rix <Tom.Rix at windriver.com>
 
+obj-$(CONFIG_DM_CHARGE_DISPLAY)	+= charge-display-uclass.o
+
 obj-$(CONFIG_AXP152_POWER)	+= axp152.o
 obj-$(CONFIG_AXP209_POWER)	+= axp209.o
 obj-$(CONFIG_AXP221_POWER)	+= axp221.o
 obj-$(CONFIG_AXP809_POWER)	+= axp809.o
 obj-$(CONFIG_AXP818_POWER)	+= axp818.o
+obj-$(CONFIG_CHARGE_ANIMATION)	+= charge_animation.o
 obj-$(CONFIG_EXYNOS_TMU)	+= exynos-tmu.o
 obj-$(CONFIG_FTPMU010_POWER)	+= ftpmu010.o
 obj-$(CONFIG_SY8106A_POWER)	+= sy8106a.o
@@ -20,3 +23,4 @@ obj-$(CONFIG_DIALOG_POWER) += power_dialog.o
 obj-$(CONFIG_POWER_FSL) += power_fsl.o
 obj-$(CONFIG_POWER_I2C) += power_i2c.o
 obj-$(CONFIG_POWER_SPI) += power_spi.o
+

drivers/power/charge-display-uclass.c

@@ -0,0 +1,40 @@
+/*
+ * (C) Copyright 2017 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <command.h>
+#include <common.h>
+#include <dm.h>
+#include <power/charge_display.h>
+
+int charge_display_show(struct udevice *dev)
+{
+	const struct dm_charge_display_ops *ops = dev_get_driver_ops(dev);
+
+	if (!ops || !ops->show)
+		return -ENOSYS;
+
+	return ops->show(dev);
+}
+
+int charge_display(void)
+{
+	struct udevice *dev;
+	struct udevice *fg_dev;
+	int ret;
+
+	ret = uclass_get_device(UCLASS_CHARGE_DISPLAY, 0, &dev);
+	if (ret) {
+		debug("Get charge display failed, ret=%d\n", ret);
+		return ret;
+	}
+	
+	return charge_display_show(dev);
+}
+
+UCLASS_DRIVER(charge_display) = {
+	.id	= UCLASS_CHARGE_DISPLAY,
+	.name	= "charge_display",
+};

drivers/power/charge/Kconfig

@@ -0,0 +1,5 @@
+config CHARGER_BQ25700
+	bool "BQ25700 charger support"
+	depends on DM_FUEL_GAUGE
+	help
+	  This adds support for BQ25700 charger support.

drivers/power/charge/Makefile

@@ -0,0 +1,7 @@
+#
+# Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+obj-$(CONFIG_CHARGER_BQ25700) += bq25700_charger.o

drivers/power/charge/bq25700_charger.c

@@ -0,0 +1,334 @@
+/*
+ * (C) Copyright 2019 Fuzhou Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/gpio.h>
+#include <dm/device.h>
+#include <dm/uclass.h>
+#include <power/fuel_gauge.h>
+#include <power/pmic.h>
+#include <power/power_delivery/power_delivery.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define BQ25700_ID				0x25700
+#define BQ25703_ID				0x25703
+
+#define COMPAT_BQ25700				"ti,bq25700"
+#define COMPAT_BQ25703				"ti,bq25703"
+
+#define BQ25700_I2C_SPEED			100000
+#define BQ25700_CHARGE_CURRENT_1500MA		0x5C0
+#define BQ25700_SDP_INPUT_CURRENT_500MA		0xA00
+#define BQ25700_DCP_INPUT_CURRENT_1500MA	0x1E00
+#define BQ25700_DCP_INPUT_CURRENT_2000MA	0x2800
+#define BQ25700_DCP_INPUT_CURRENT_3000MA	0x3C00
+
+#define WATCHDOG_ENSABLE			(0x03 << 13)
+
+#define BQ25700_CHARGEOPTION0_REG		0x12
+#define BQ25700_CHARGECURREN_REG		0x14
+#define BQ25700_CHARGERSTAUS_REG		0x20
+#define BQ25700_INPUTVOLTAGE_REG		0x3D
+#define BQ25700_INPUTCURREN_REG			0x3F
+
+#define BQ25703_CHARGEOPTION0_REG		0x00
+#define BQ25703_CHARGECURREN_REG		0x02
+#define BQ25703_CHARGERSTAUS_REG		0x20
+#define BQ25703_INPUTVOLTAGE_REG		0x0A
+#define BQ25703_INPUTCURREN_REG			0x0E
+#define PD_MUN 2
+#define TYPEC0_I2C "i2c@ffe7f20000"
+#define TYPEC1_I2C "i2c@ffe7f24000"
+
+enum bq25700_table_ids {
+	/* range tables */
+	TBL_ICHG,
+	TBL_CHGMAX,
+	TBL_INPUTVOL,
+	TBL_INPUTCUR,
+	TBL_SYSVMIN,
+	TBL_OTGVOL,
+	TBL_OTGCUR,
+	TBL_EXTCON,
+};
+
+struct bq25700 {
+	struct udevice *dev;
+	u32 ichg;
+	u32 chip_id;
+	struct udevice *pd[PD_MUN];
+};
+
+struct bq25700_range {
+	u32 min;
+	u32 max;
+	u32 step;
+};
+
+static int bq25700_read(struct bq25700 *charger, uint reg)
+{
+	u16 val;
+	int ret;
+
+	ret = dm_i2c_read(charger->dev, reg, (u8 *)&val, 2);
+	if (ret) {
+		printf("write error to device: %p register: %#x!",
+			   charger->dev, reg);
+		return ret;
+	}
+
+	return val;
+}
+
+static int bq25700_write(struct bq25700 *charger, uint reg, u16 val)
+{
+	int ret;
+
+	ret = dm_i2c_write(charger->dev, reg, (u8 *)&val, 2);
+	if (ret) {
+		printf("write error to device: %p register: %#x!",
+			   charger->dev, reg);
+		return ret;
+	}
+
+	return 0;
+}
+
+static const union {
+	struct bq25700_range rt;
+} bq25700_tables[] = {
+	/* range tables */
+	[TBL_ICHG] = {.rt = {0, 8128000, 64000}},
+	/* uV */
+	[TBL_CHGMAX] = {.rt = {0, 19200000, 16000}},
+	/* uV  max charge voltage*/
+	[TBL_INPUTVOL] = {.rt = {3200000, 19520000, 64000}},
+	/* uV  input charge voltage*/
+	[TBL_INPUTCUR] = {.rt = {0, 6350000, 50000}},
+	/*uA input current*/
+	[TBL_SYSVMIN] = {.rt = {1024000, 16182000, 256000}},
+	/* uV min system voltage*/
+	[TBL_OTGVOL] = {.rt = {4480000, 20800000, 64000}},
+	/*uV OTG volage*/
+	[TBL_OTGCUR] = {.rt = {0, 6350000, 50000}},
+};
+
+static u32 bq25700_find_idx(u32 value, enum bq25700_table_ids id)
+{
+	const struct bq25700_range *rtbl = &bq25700_tables[id].rt;
+	u32 rtbl_size;
+	u32 idx;
+
+	rtbl_size = (rtbl->max - rtbl->min) / rtbl->step + 1;
+
+	for (idx = 1;
+		 idx < rtbl_size && (idx * rtbl->step + rtbl->min <= value);
+		 idx++)
+		;
+
+	return idx - 1;
+}
+
+static bool bq25700_charger_status(struct bq25700 *charger)
+{
+	int state_of_charger;
+	u16 value;
+
+	value = bq25700_read(charger, BQ25700_CHARGERSTAUS_REG);
+	state_of_charger = value >> 15;
+
+	return state_of_charger;
+}
+
+static bool bq25703_charger_status(struct bq25700 *charger)
+{
+	int state_of_charger;
+	u16 value;
+
+	value = bq25700_read(charger, BQ25703_CHARGERSTAUS_REG);
+	state_of_charger = value >> 15;
+
+	return state_of_charger;
+}
+
+static bool bq257xx_charger_status(struct udevice *dev)
+{
+	struct bq25700 *charger = dev_get_priv(dev);
+
+	if (charger->chip_id == BQ25700_ID)
+		return bq25700_charger_status(charger);
+	else
+		return bq25703_charger_status(charger);
+}
+
+static int bq25700_charger_capability(struct udevice *dev)
+{
+	return FG_CAP_CHARGER;
+}
+
+static int bq25700_get_usb_type(void)
+{
+#ifdef CONFIG_PHY_ROCKCHIP_INNO_USB2
+	return rockchip_chg_get_type();
+#else
+	return 0;
+#endif
+}
+
+static int bq25700_get_pd_output_val(struct bq25700 *charger,
+									 int *vol, int *cur)
+{
+	struct power_delivery_data pd_data;
+	int ret;
+
+	if (!charger->pd[0] && !charger->pd[1]) {
+		return -EINVAL;
+	}
+
+	memset(&pd_data, 0, sizeof(pd_data));
+	int i = 0;
+	for (i = 0; i < PD_MUN; i++) {
+		if (!charger->pd[i]) {
+			continue;
+		}
+		ret = power_delivery_get_data(charger->pd[i], &pd_data);
+		if (ret) {
+			continue;
+		}
+		if (!pd_data.online || !pd_data.voltage || !pd_data.current) {
+			continue;
+		}
+
+		*vol = pd_data.voltage;
+		*cur = pd_data.current;
+		printf("voltage is %d current is %d\n", *vol, *cur);
+		goto end;
+	}
+	return -EINVAL;
+
+end:
+	return 0;
+}
+
+static void bq25703_charger_current_init(struct bq25700 *charger)
+{
+	u16 charge_current = BQ25700_CHARGE_CURRENT_1500MA;
+	u16 sdp_inputcurrent = BQ25700_SDP_INPUT_CURRENT_500MA;
+	u16 dcp_inputcurrent = BQ25700_DCP_INPUT_CURRENT_1500MA;
+	int pd_inputvol, pd_inputcurrent;
+	u16 vol_idx = 0, cur_idx;
+	u16 temp;
+
+	temp = bq25700_read(charger, BQ25703_CHARGEOPTION0_REG);
+	temp &= (~WATCHDOG_ENSABLE);
+	bq25700_write(charger, BQ25703_CHARGEOPTION0_REG, temp);
+
+	if (!bq25700_get_pd_output_val(charger, &pd_inputvol,
+								   &pd_inputcurrent)) {
+		if (pd_inputvol > 5000000) {
+			vol_idx = bq25700_find_idx(pd_inputvol - 1280000 - 3200000,
+									   TBL_INPUTVOL);
+			vol_idx = vol_idx << 6;
+		}
+		cur_idx = bq25700_find_idx(pd_inputcurrent,
+								   TBL_INPUTCUR);
+		cur_idx = cur_idx << 8;
+		if (pd_inputcurrent != 0)
+		{
+			bq25700_write(charger, BQ25703_INPUTCURREN_REG,
+						  cur_idx);
+			if (vol_idx)
+				bq25700_write(charger, BQ25703_INPUTVOLTAGE_REG,
+							  vol_idx);
+			charge_current = bq25700_find_idx(pd_inputcurrent,
+											  TBL_ICHG);
+			charge_current = charge_current << 6;
+		}
+	} else {
+		bq25700_write(charger, BQ25703_INPUTCURREN_REG,
+					  dcp_inputcurrent);
+	}
+
+	if (bq25703_charger_status(charger)) {
+		bq25700_write(charger, BQ25703_CHARGECURREN_REG,
+					  charge_current);
+	}
+}
+
+static int bq25700_ofdata_to_platdata(struct udevice *dev)
+{
+	struct bq25700 *charger = dev_get_priv(dev);
+	const void *blob = gd->fdt_blob;
+	int node, node1;
+
+	charger->dev = dev;
+
+	node = fdt_node_offset_by_compatible(blob, 0, COMPAT_BQ25700);
+	node1 = fdt_node_offset_by_compatible(blob, 0, COMPAT_BQ25703);
+	if ((node < 0) && (node1 < 0)) {
+		printf("Can't find dts node for charger bq25700\n");
+		return -ENODEV;
+	}
+
+	if (node < 0) {
+		node = node1;
+		charger->chip_id = BQ25703_ID;
+	} else {
+		charger->chip_id = BQ25700_ID;
+	}
+
+	return 0;
+}
+
+static int bq25700_probe(struct udevice *dev)
+{
+	struct bq25700 *charger = dev_get_priv(dev);
+	int ret;
+
+	struct udevice *pd_tmp;
+	struct udevice *dev_tmp;
+
+	for (uclass_first_device(UCLASS_PD, &pd_tmp);
+		 pd_tmp;
+		 uclass_next_device(&pd_tmp))
+	{
+		dev_tmp = dev_get_parent(pd_tmp);
+		if (!strncmp(TYPEC0_I2C, dev_tmp->name, strlen(TYPEC0_I2C))) { // Ensure that typec0 has the highest priority
+			charger->pd[0] = pd_tmp;
+		} else if (!strncmp(TYPEC1_I2C, dev_tmp->name, strlen(TYPEC1_I2C))) {
+			charger->pd[1] = pd_tmp;
+		}
+	}
+
+	if (charger->chip_id == BQ25703_ID) {
+		bq25703_charger_current_init(charger);
+	}
+
+	return 0;
+}
+
+static const struct udevice_id charger_ids[] = {
+	{.compatible = "ti,bq25700"},
+	{.compatible = "ti,bq25703"},
+	{},
+	{ },
+};
+
+static struct dm_fuel_gauge_ops charger_ops = {
+	.get_chrg_online = bq257xx_charger_status,
+	.capability = bq25700_charger_capability,
+};
+
+U_BOOT_DRIVER(bq25700_charger) = {
+	.name = "bq25700_charger",
+	.id = UCLASS_FG,
+	.probe = bq25700_probe,
+	.of_match = charger_ids,
+	.ops = &charger_ops,
+	.ofdata_to_platdata = bq25700_ofdata_to_platdata,
+	.priv_auto_alloc_size = sizeof(struct bq25700),
+};

drivers/power/charge_animation.c

@@ -0,0 +1,366 @@
+/*
+ * (C) Copyright 2017 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include <common.h>
+#include <console.h>
+#include <dm.h>
+#include <errno.h>
+#include <led.h>
+#include <rtc.h>
+#include <pwm.h>
+#include <power/charge_display.h>
+#include <power/charge_animation.h>
+#include <power/fuel_gauge.h>
+#include <power/pmic.h>
+#include <mcu/mcu-uclass.h>
+#ifdef CONFIG_IRQ
+#include <irq-generic.h>
+#include <rk_timer_irq.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define IMAGE_RECALC_IDX				-1
+#define IMAGE_SOC_100_IDX(n)			((n) - 2)
+#define IMAGE_LOWPOWER_IDX(n)			((n) - 1)
+#define SYSTEM_SUSPEND_DELAY_MS			5000
+#define FUEL_GAUGE_POLL_MS			1000
+
+#define LED_CHARGING_NAME			"battery_charging"
+#define LED_CHARGING_FULL_NAME			"battery_full"
+#define LED_CHARGING_START_NAME			"battery_start"
+
+struct charge_image {
+	const char *name;
+	int soc;
+	int period;	/* ms */
+};
+
+struct charge_animation_priv {
+	struct udevice *fg;
+	struct udevice *charger;
+	struct udevice *mcu;
+#ifdef CONFIG_LED
+	struct udevice *led_charging;
+	struct udevice *led_full;
+	struct udevice *led_start;
+#endif
+	const struct charge_image *image;
+	int image_num;
+
+	int auto_wakeup_key_state;
+	ulong auto_screen_off_timeout;	/* ms */
+	ulong suspend_delay_timeout;	/* ms */
+};
+
+struct gpio_desc powerkey_gpio;
+static int leds_switch = 0;
+
+#ifdef CONFIG_LED
+static int leds_update(struct udevice *dev, int soc)
+{
+	struct charge_animation_priv *priv = dev_get_priv(dev);
+	static int old_soc = -1;
+	int ret, ledst;
+
+	if (old_soc == soc)
+		return 0;
+
+	old_soc = soc;
+	if (priv->led_charging) {
+		ledst = (soc < 100) ? LEDST_ON : LEDST_OFF;
+		ret = led_set_state(priv->led_charging, ledst);
+		if (ret) {
+			printf("set charging led %s failed, ret=%d\n",
+			       (ledst == LEDST_ON) ? "ON" : "OFF", ret);
+			return ret;
+		}
+	}
+
+	if (priv->led_full) {
+		ledst = (soc == 100) ? LEDST_ON : LEDST_OFF;
+		ret = led_set_state(priv->led_full, ledst);
+		if (ret) {
+			printf("set charging full led %s failed, ret=%d\n",
+			       ledst == LEDST_ON ? "ON" : "OFF", ret);
+			return ret;
+		}
+	}
+
+	return 0;
+}
+
+static int leds_charge_on(struct udevice *dev, int soc)
+{
+	struct charge_animation_priv *priv = dev_get_priv(dev);
+	int ret, ledst;
+
+	ledst = LEDST_ON;
+	ret = led_set_state(priv->led_full, ledst);
+		if (ret) {
+			printf("set charging full led %s failed, ret=%d\n",
+			       ledst == LEDST_ON ? "ON" : "OFF", ret);
+			return ret;
+		}
+	return 0;
+}
+
+static int leds_charge_off(struct udevice *dev, int soc)
+{
+	struct charge_animation_priv *priv = dev_get_priv(dev);
+	int ret, ledst;
+	ledst = LEDST_OFF;
+	ret = led_set_state(priv->led_charging, ledst);
+		if (ret) {
+			printf("set charging full led %s failed, ret=%d\n",
+			       ledst == LEDST_ON ? "ON" : "OFF", ret);
+			return ret;
+		}
+	ret = led_set_state(priv->led_full, ledst);
+		if (ret) {
+			printf("set charging full led %s failed, ret=%d\n",
+			       ledst == LEDST_ON ? "ON" : "OFF", ret);
+			return ret;
+		}
+	return 0;
+}
+
+static int leds_charge_update(struct udevice *dev, int soc)
+{
+	struct charge_animation_priv *priv = dev_get_priv(dev);
+	int ret, ledst;
+	if (leds_switch > 5){
+		leds_charge_on(dev, soc);
+	} else {
+		leds_charge_off(dev, soc);
+	}
+	leds_switch++;
+	if (leds_switch > 10)
+		leds_switch = 0;
+	return 0;
+}
+
+
+#else
+static int leds_update(struct udevice *dev, int soc) { return 0; }
+
+static int leds_charge_on(struct udevice *dev, int soc) { return 0; }
+
+static int leds_charge_off(struct udevice *dev, int soc) { return 0; }
+
+static int leds_charge_update(struct udevice *dev, int soc) { return 0; }
+#endif
+
+static int charge_animation_ofdata_to_platdata(struct udevice *dev)
+{
+	struct charge_animation_pdata *pdata = dev_get_platdata(dev);
+	pdata->low_power_voltage =
+		dev_read_u32_default(dev, "uboot-low-power-voltage", 0);
+
+	return 0;
+}
+
+static int fg_charger_get_chrg_online(struct udevice *dev)
+{
+	struct charge_animation_priv *priv = dev_get_priv(dev);
+	struct udevice *charger;
+
+	charger = priv->charger ? : priv->fg;
+
+	return fuel_gauge_get_chrg_online(charger);
+}
+
+static int get_reboot_state(void){
+	const char *var_name = "battery_charge";
+	char *value = env_get(var_name);
+	if (value)
+		if (strcmp(value, "0") == 0) {
+			env_set(var_name, "1");
+			env_save();
+			return 0;
+		}
+
+	env_set(var_name, "1");
+	env_save();
+
+	return 1;
+}
+
+static int charge_animation_show(struct udevice *dev)
+{
+	int soc, voltage, ret, charging = 0;
+	struct charge_animation_priv *priv = dev_get_priv(dev);
+	struct charge_animation_pdata *pdata = dev_get_platdata(dev);
+	struct udevice *fg = priv->fg;
+	struct udevice *mcu = priv->mcu;
+
+	voltage = fuel_gauge_get_voltage(fg);
+	if (voltage < 0)
+		return -EINVAL;
+
+	while (voltage < pdata->low_power_voltage + 50) {
+		soc = fuel_gauge_update_get_soc(fg);
+		if (soc < 0 || soc > 100) {
+			printf("get soc failed: %d\n", soc);
+			continue;
+		} else if (soc >= 1) {
+			printf("soc is: %d\n", soc);
+			break;
+		}
+
+		voltage = fuel_gauge_get_voltage(fg);
+		if (voltage < 0) {
+			printf("get voltage failed: %d\n", voltage);
+			continue;
+		}
+
+		ret = leds_update(dev, soc);
+		if (ret)
+			printf("update led failed: %d\n", ret);
+
+		printf("soc is: %d voltage is :%d\n", soc, voltage);
+
+		charging = fg_charger_get_chrg_online(dev);
+		if (charging <= 0) {
+			mcu_shutdown(); // shutdown system power
+		}
+		mdelay(100);
+	};
+	leds_charge_off(dev, soc);
+
+	ret = get_reboot_state();
+
+	charging = fg_charger_get_chrg_online(dev);
+
+	if (!(charging <= 0) && ret != 0)
+		while(1){
+			ret = dm_gpio_get_value(&powerkey_gpio);
+			if (ret == 0){
+				break;
+			}
+
+			charging = fg_charger_get_chrg_online(dev);
+			if (charging <= 0) {
+				mcu_shutdown(); // shutdown system power
+			}
+
+			soc = fuel_gauge_update_get_soc(fg);
+			if (soc == 100){
+				leds_charge_on(dev, soc);
+			}else if (soc < 100){
+				leds_charge_update(dev, soc);
+			}
+			mdelay(300);
+		}
+
+	leds_charge_off(dev, soc);
+
+	ret = led_set_state(priv->led_start, LEDST_ON);
+	if (!ret)
+		printf("Found Charging-Start LED\n");
+
+	return 0;
+}
+
+static int fg_charger_get_device(struct udevice **fuel_gauge,
+				 struct udevice **charger)
+{
+	struct udevice *dev;
+	struct uclass *uc;
+	int ret, cap;
+
+	*fuel_gauge = NULL,
+	*charger = NULL;
+
+	ret = uclass_get(UCLASS_FG, &uc);
+	if (ret)
+		return ret;
+
+	for (uclass_first_device(UCLASS_FG, &dev);
+	     dev;
+	     uclass_next_device(&dev)) {
+		cap = fuel_gauge_capability(dev);
+		if (cap == (FG_CAP_CHARGER | FG_CAP_FUEL_GAUGE)) {
+			*fuel_gauge = dev;
+			*charger = NULL;
+		} else if (cap == FG_CAP_FUEL_GAUGE) {
+			*fuel_gauge = dev;
+		} else if (cap == FG_CAP_CHARGER) {
+			*charger = dev;
+		}
+	}
+
+	return (*fuel_gauge) ? 0 : -ENODEV;
+}
+
+static const struct dm_charge_display_ops charge_animation_ops = {
+	.show = charge_animation_show,
+};
+
+static int charge_animation_probe(struct udevice *dev)
+{
+	struct charge_animation_priv *priv = dev_get_priv(dev);
+	int ret, soc;
+	/* Get PMIC: used for power off system  */
+	ret = uclass_get_device(UCLASS_MCU, 0, &priv->mcu);
+	if (ret) {
+		if (ret == -ENODEV)
+			printf("Can't find MCU\n");
+		else
+			printf("Get UCLASS MCU failed: %d\n", ret);
+	}
+
+	/* Get fuel gauge and charger(If need) */
+	ret = fg_charger_get_device(&priv->fg, &priv->charger);
+	if (ret) {
+		if (ret == -ENODEV)
+			debug("Can't find FG\n");
+		else
+			debug("Get UCLASS FG failed: %d\n", ret);
+		// return ret;
+	}
+
+
+#ifdef CONFIG_LED
+	ret = led_get_by_label(LED_CHARGING_NAME, &priv->led_charging);
+	if (!ret)
+		printf("Found Charging LED \n");
+		
+	ret = led_get_by_label(LED_CHARGING_FULL_NAME, &priv->led_full);
+	if (!ret)
+		printf("Found Charging-Full LED\n");
+	
+	ret = led_get_by_label(LED_CHARGING_START_NAME, &priv->led_start);
+	if (!ret)
+		printf("Found Charging-Start LED\n");
+#endif
+	ret = gpio_request_by_name(dev, "powerkey-gpio", 0, &powerkey_gpio, 0);
+	if (dm_gpio_is_valid(&powerkey_gpio)) {
+		dm_gpio_set_dir_flags(&powerkey_gpio, GPIOD_IS_IN);
+	}
+
+	printf("Enable charge animation display\n");
+
+	return 0;
+}
+
+static const struct udevice_id charge_animation_ids[] = {
+	{ .compatible = "rockchip,uboot-charge" },
+	{ },
+};
+
+U_BOOT_DRIVER(charge_animation) = {
+	.name = "charge-animation",
+	.id = UCLASS_CHARGE_DISPLAY,
+	.probe = charge_animation_probe,
+	.of_match = charge_animation_ids,
+	.ops = &charge_animation_ops,
+	.ofdata_to_platdata = charge_animation_ofdata_to_platdata,
+	.platdata_auto_alloc_size = sizeof(struct charge_animation_pdata),
+	.priv_auto_alloc_size = sizeof(struct charge_animation_priv),
+};

drivers/power/fuel_gauge/Kconfig

@@ -0,0 +1,11 @@
+config DM_FUEL_GAUGE
+	bool "Enable driver model fuel gauge support"
+	depends on DM
+	help
+	  This adds a simple uclass for fuel gauge.
+
+config POWER_FG_CW201X
+	bool "CW201X Fuel gauge support"
+	depends on DM_FUEL_GAUGE
+	help
+	  This adds support for CW201X fuel gauge support.

drivers/power/fuel_gauge/Makefile

@@ -3,4 +3,7 @@
 # Copyright (C) 2012 Samsung Electronics
 # Lukasz Majewski <l.majewski@samsung.com>
 
+obj-$(CONFIG_$(SPL_)DM_FUEL_GAUGE) += fuel_gauge_uclass.o
+
 obj-$(CONFIG_POWER_FG_MAX17042) += fg_max17042.o
+obj-$(CONFIG_POWER_FG_CW201X) += fg_cw201x.o

drivers/power/fuel_gauge/fg_cw201x.c

@@ -0,0 +1,415 @@
+/*
+ * (C) Copyright 2008-2015 Fuzhou Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#include <common.h>
+#include <asm/gpio.h>
+#include <dm.h>
+#include <dm/device.h>
+#include <errno.h>
+#include <fdtdec.h>
+#include <i2c.h>
+// #include <linux/usb/phy-rockchip-usb2.h>
+#include <malloc.h>
+#include <power/battery.h>
+#include <power/fuel_gauge.h>
+// #include <power/pmic.h>
+#include "fg_regs.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define COMPAT_ROCKCHIP_CW201X "cw201x"
+
+#define REG_VERSION		0x0
+#define REG_VCELL		0x2
+#define REG_SOC			0x4
+#define REG_RRT_ALERT		0x6
+#define REG_CONFIG		0x8
+#define REG_MODE		0xA
+#define REG_BATINFO		0x10
+
+#define MODE_SLEEP_MASK		(0x3 << 6)
+#define MODE_SLEEP		(0x3 << 6)
+#define MODE_NORMAL		(0x0 << 6)
+#define MODE_QUICK_START	(0x3 << 4)
+#define MODE_RESTART		(0xf << 0)
+
+#define CONFIG_UPDATE_FLG	(0x1 << 1)
+#define ATHD			(0x0 << 3)
+
+enum charger_type {
+	CHARGER_TYPE_NO = 0,
+	CHARGER_TYPE_USB,
+	CHARGER_TYPE_AC,
+	CHARGER_TYPE_DC,
+	CHARGER_TYPE_UNDEF,
+};
+
+struct cw201x_info {
+	struct udevice *dev;
+	int capacity;
+	u32 *cw_bat_config_info;
+	int divider_res1;
+	int divider_res2;
+	int hw_id_check;
+	struct gpio_desc hw_id0;
+	struct gpio_desc hw_id1;
+	int support_dc_adp;
+	struct gpio_desc dc_det_gpio;
+	int dc_det_flag;
+	bool dual_cell;
+};
+
+static u8 cw201x_read(struct cw201x_info *cw201x, u8 reg)
+{
+	u8 val;
+	int ret;
+
+	ret = dm_i2c_read(cw201x->dev, reg, &val, 1);
+	if (ret) {
+		printf("write error to device: %p register: %#x!",
+		      cw201x->dev, reg);
+		return ret;
+	}
+
+	return val;
+}
+
+static int cw201x_write(struct cw201x_info *cw201x, u8 reg, u8 val)
+{
+	int ret;
+
+	ret = dm_i2c_write(cw201x->dev, reg, &val, 1);
+	if (ret) {
+		printf("write error to device: %p register: %#x!",
+		      cw201x->dev, reg);
+		return ret;
+	}
+
+	return 0;
+}
+
+static u16 cw201x_read_half_word(struct cw201x_info *cw201x, int reg)
+{
+	u8 vall, valh;
+	u16 val;
+
+	valh = cw201x_read(cw201x, reg);
+	vall = cw201x_read(cw201x, reg + 1);
+	val = ((u16)valh << 8) | vall;
+
+	return val;
+}
+
+static int cw201x_parse_config_info(struct cw201x_info *cw201x)
+{
+	int ret;
+	int i, len, size;
+	const u8 *info;
+	struct udevice *dev = cw201x->dev;
+
+	if (dev_read_prop(dev, "bat_config_info", &len)) {
+		len /= sizeof(u32);
+		size = sizeof(*cw201x->cw_bat_config_info) * len;
+		cw201x->cw_bat_config_info = calloc(size, 1);
+		if (!cw201x->cw_bat_config_info) {
+			printf("calloc cw_bat_config_info fail\n");
+			return -EINVAL;
+		}
+		ret = dev_read_u32_array(dev, "bat_config_info",
+					 cw201x->cw_bat_config_info, len);
+		if (ret) {
+			printf("fdtdec_get cw_bat_config_info fail\n");
+			return -EINVAL;
+		}
+
+		return 0;
+	}
+
+	if (!dev_read_prop(dev, "cellwise,battery-profile", &len))
+		return -EINVAL;
+
+	size = sizeof(*cw201x->cw_bat_config_info) * len;
+	cw201x->cw_bat_config_info = calloc(size, 1);
+	if (!cw201x->cw_bat_config_info) {
+		printf("calloc cw_bat_config_info fail\n");
+		return -EINVAL;
+	}
+
+	info = dev_read_u8_array_ptr(dev, "cellwise,battery-profile", len);
+	if (!info) {
+		printf("fdtdec_get battery profile fail\n");
+		return -EINVAL;
+	}
+	for (i = 0; i < len; i++) {
+		cw201x->cw_bat_config_info[i] = info[i];
+		printf("%#x ", cw201x->cw_bat_config_info[i]);
+		if ((i+1) % 8 == 0)
+			printf("\n");
+	}
+
+	return 0;
+}
+
+static int cw201x_ofdata_to_platdata(struct udevice *dev)
+{
+	struct cw201x_info *cw201x = dev_get_priv(dev);
+	int ret;
+	int hw_id0_val, hw_id1_val;
+
+	cw201x->dev = dev;
+	ret = cw201x_parse_config_info(cw201x);
+	if (ret)
+		return ret;
+
+	cw201x->dual_cell = dev_read_bool(dev, "cellwise,dual-cell");
+	ret = gpio_request_by_name_nodev(dev_ofnode(dev), "dc_det_gpio",
+					 0, &cw201x->dc_det_gpio, GPIOD_IS_IN);
+	if (!ret) {
+		cw201x->support_dc_adp = 1;
+		printf("DC is valid\n");
+	} else {
+		printf("DC is invalid, ret=%d\n", ret);
+	}
+
+	cw201x->hw_id_check = dev_read_u32_default(dev, "hw_id_check", 0);
+	if (cw201x->hw_id_check) {
+		ret = gpio_request_by_name_nodev(dev_ofnode(dev),
+						 "hw_id0_gpio", 0,
+						 &cw201x->hw_id0, GPIOD_IS_IN);
+		if (ret)
+			return -EINVAL;
+		hw_id0_val = dm_gpio_get_value(&cw201x->hw_id0);
+
+		ret = gpio_request_by_name_nodev(dev_ofnode(dev),
+						 "hw_id1_gpio", 0,
+						 &cw201x->hw_id1, GPIOD_IS_IN);
+		if (ret)
+			return -EINVAL;
+		hw_id1_val = dm_gpio_get_value(&cw201x->hw_id1);
+
+		/* ID1 = 0, ID0 = 1 : Battery */
+		if (!hw_id0_val || hw_id1_val)
+			return -EINVAL;
+	}
+
+	cw201x->divider_res1 = dev_read_u32_default(dev, "divider_res1", 0);
+	cw201x->divider_res2 = dev_read_u32_default(dev, "divider_res2", 0);
+
+	return 0;
+}
+
+static int cw201x_get_vol(struct cw201x_info *cw201x)
+{
+	u16 value16, value16_1, value16_2, value16_3;
+	int voltage;
+	int res1, res2;
+	int retry = 0;
+
+__retry:
+	value16 = cw201x_read_half_word(cw201x, REG_VCELL);
+	if (value16 < 0)
+		return -1;
+
+	value16_1 = cw201x_read_half_word(cw201x, REG_VCELL);
+	if (value16_1 < 0)
+		return -1;
+
+	value16_2 = cw201x_read_half_word(cw201x, REG_VCELL);
+	if (value16_2 < 0)
+		return -1;
+
+	if (value16 > value16_1) {
+		value16_3 = value16;
+		value16 = value16_1;
+		value16_1 = value16_3;
+	}
+
+	if (value16_1 > value16_2) {
+		value16_3 = value16_1;
+		value16_1 = value16_2;
+		value16_2 = value16_3;
+	}
+
+	if (value16 > value16_1) {
+		value16_3 = value16;
+		value16 = value16_1;
+		value16_1 = value16_3;
+	}
+
+	voltage = value16_1 * 312 / 1024;
+	if (voltage <= 0 && retry < 10) {
+		retry++;
+		mdelay(20);
+		goto __retry;
+	}
+
+	if (cw201x->divider_res1 &&
+	    cw201x->divider_res2) {
+		res1 = cw201x->divider_res1;
+		res2 = cw201x->divider_res2;
+		voltage = voltage * (res1 + res2) / res2;
+	}
+
+	if (cw201x->dual_cell)
+		voltage *= 2;
+
+	// printf("the cw201x voltage=%d\n", voltage);
+	return voltage;
+}
+
+static int cw201x_dwc_otg_check_dpdm(void)
+{
+#if defined(CONFIG_PHY_ROCKCHIP_INNO_USB2) && !defined(CONFIG_SPL_BUILD)
+	return rockchip_chg_get_type();
+#else
+	printf("rockchip_chg_get_type() is not implement\n");
+	return CHARGER_TYPE_NO;
+#endif
+}
+
+static int cw201x_get_usb_state(struct cw201x_info *cw201x)
+{
+	int charger_type;
+
+	switch (cw201x_dwc_otg_check_dpdm()) {
+	case 0:
+		charger_type = CHARGER_TYPE_NO;
+		break;
+	case 1:
+	case 3:
+		charger_type = CHARGER_TYPE_USB;
+		break;
+	case 2:
+		charger_type = CHARGER_TYPE_AC;
+		break;
+	default:
+		charger_type = CHARGER_TYPE_NO;
+		break;
+	}
+
+	return charger_type;
+}
+
+static bool cw201x_get_dc_state(struct cw201x_info *cw201x)
+{
+	if (dm_gpio_get_value(&cw201x->dc_det_gpio))
+		return true;
+
+	return false;
+}
+
+static bool cw201x_check_charge(struct cw201x_info *cw201x)
+{
+	if (cw201x_get_usb_state(cw201x) != CHARGER_TYPE_NO)
+		return true;
+	if (cw201x_get_dc_state(cw201x))
+		return true;
+
+	return false;
+}
+
+static int cw201x_get_soc(struct cw201x_info *cw201x)
+{
+	int cap, i = 0;
+
+	while (i < 10) {
+		mdelay(30);
+		cap = cw201x_read(cw201x, REG_SOC);
+		if ((cap < 0) || (cap > 100))
+			cap = cw201x->capacity;
+		i++;
+		if (cap)
+			break;
+	}
+	cw201x->capacity = cap;
+
+	return cw201x->capacity;
+}
+
+static int cw201x_update_get_soc(struct udevice *dev)
+{
+	struct cw201x_info *cw201x = dev_get_priv(dev);
+
+	return cw201x_get_soc(cw201x);
+}
+
+static int cw201x_update_get_voltage(struct udevice *dev)
+{
+	struct cw201x_info *cw201x = dev_get_priv(dev);
+
+	return cw201x_get_vol(cw201x);
+}
+
+static int cw201x_update_get_current(struct udevice *dev)
+{
+	return 0;
+}
+
+static bool cw201x_update_get_chrg_online(struct udevice *dev)
+{
+	struct cw201x_info *cw201x = dev_get_priv(dev);
+
+	return cw201x_check_charge(cw201x);
+}
+
+static int cw201x_capability(struct udevice *dev)
+{
+	return FG_CAP_FUEL_GAUGE;
+}
+
+static struct dm_fuel_gauge_ops cw201x_fg_ops = {
+	.capability = cw201x_capability,
+	.get_soc = cw201x_update_get_soc,
+	.get_voltage = cw201x_update_get_voltage,
+	.get_current = cw201x_update_get_current,
+	.get_chrg_online = cw201x_update_get_chrg_online,
+};
+
+static int cw201x_fg_cfg(struct cw201x_info *cw201x)
+{
+	u8 val = MODE_SLEEP;
+	int i;
+
+	if ((val & MODE_SLEEP_MASK) == MODE_SLEEP) {
+		val = MODE_NORMAL;
+		cw201x_write(cw201x, REG_MODE, val);
+	}
+
+	for (i = 0; i < 64; i++) {
+		cw201x_write(cw201x, REG_BATINFO + i,
+			     (u8)cw201x->cw_bat_config_info[i]);
+	}
+
+	return 0;
+}
+
+static int cw201x_fg_probe(struct udevice *dev)
+{
+	struct cw201x_info *cw201x = dev_get_priv(dev);
+
+	cw201x->dev = dev;
+	cw201x_fg_cfg(cw201x);
+
+	printf("vol: %d, soc: %d\n",
+	      cw201x_get_vol(cw201x), cw201x_get_soc(cw201x));
+
+	return 0;
+}
+
+static const struct udevice_id cw201x_ids[] = {
+	{ .compatible = "cw201x" },
+	{ .compatible = "cellwise,cw2015" },
+	{ }
+};
+
+U_BOOT_DRIVER(cw201x_fg) = {
+	.name = "cw201x_fg",
+	.id = UCLASS_FG,
+	.of_match = cw201x_ids,
+	.probe = cw201x_fg_probe,
+	.ofdata_to_platdata = cw201x_ofdata_to_platdata,
+	.ops = &cw201x_fg_ops,
+	.priv_auto_alloc_size = sizeof(struct cw201x_info),
+};

drivers/power/fuel_gauge/fg_regs.h

@@ -0,0 +1,95 @@
+/*
+ * (C) Copyright 2017 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef _FG_RK8XX_H_
+#define _FG_RK8XX_H_
+
+/* register definition */
+#define SECONDS_REG		0X00
+#define VB_MON_REG		0x21
+#define THERMAL_REG		0x22
+#define SUP_STS_REG		0xA0
+#define USB_CTRL_REG		0xA1
+#define CHRG_CTRL_REG1		0xA3
+#define CHRG_CTRL_REG2		0xA4
+#define CHRG_CTRL_REG3		0xA5
+#define BAT_CTRL_REG		0xA6
+#define BAT_HTS_TS_REG		0xA8
+#define BAT_LTS_TS_REG		0xA9
+#define TS_CTRL_REG		0xAC
+#define ADC_CTRL_REG		0xAD
+#define GGCON_REG		0xB0
+#define GGSTS_REG		0xB1
+#define ZERO_CUR_ADC_REGH	0xB2
+#define ZERO_CUR_ADC_REGL	0xB3
+#define GASCNT_CAL_REG3		0xB4
+#define GASCNT_CAL_REG2		0xB5
+#define GASCNT_CAL_REG1		0xB6
+#define GASCNT_CAL_REG0		0xB7
+#define GASCNT_REG3		0xB8
+#define GASCNT_REG2		0xB9
+#define GASCNT_REG1		0xBA
+#define GASCNT_REG0		0xBB
+#define BAT_CUR_AVG_REGH	0xBC
+#define BAT_CUR_AVG_REGL	0xBD
+#define TS_ADC_REGH		0xBE
+#define TS_ADC_REGL		0xBF
+#define RK818_TS2_ADC_REGH	0xC0
+#define RK818_TS2_ADC_REGL	0xC1
+#define RK816_USB_ADC_REGH	0xC0
+#define RK816_USB_ADC_REGL	0xC1
+#define BAT_OCV_REGH		0xC2
+#define BAT_OCV_REGL		0xC3
+#define BAT_VOL_REGH		0xC4
+#define BAT_VOL_REGL		0xC5
+#define RELAX_ENTRY_THRES_REGH	0xC6
+#define RELAX_ENTRY_THRES_REGL	0xC7
+#define RELAX_EXIT_THRES_REGH	0xC8
+#define RELAX_EXIT_THRES_REGL	0xC9
+#define RELAX_VOL1_REGH		0xCA
+#define RELAX_VOL1_REGL		0xCB
+#define RELAX_VOL2_REGH		0xCC
+#define RELAX_VOL2_REGL		0xCD
+#define RELAX_CUR1_REGH		0xCE
+#define RELAX_CUR1_REGL		0xCF
+#define RELAX_CUR2_REGH		0xD0
+#define RELAX_CUR2_REGL		0xD1
+#define CAL_OFFSET_REGH		0xD2
+#define CAL_OFFSET_REGL		0xD3
+#define NON_ACT_TIMER_CNT_REG	0xD4
+#define VCALIB0_REGH		0xD5
+#define VCALIB0_REGL		0xD6
+#define VCALIB1_REGH		0xD7
+#define VCALIB1_REGL		0xD8
+#define FCC_GASCNT_REG3		0xD9
+#define FCC_GASCNT_REG2		0xDA
+#define FCC_GASCNT_REG1		0xDB
+#define FCC_GASCNT_REG0		0xDC
+#define IOFFSET_REGH		0xDD
+#define IOFFSET_REGL		0xDE
+#define SLEEP_CON_SAMP_CUR_REG	0xDF
+#define SOC_REG			0xE0
+#define	REMAIN_CAP_REG3		0xE1
+#define	REMAIN_CAP_REG2		0xE2
+#define	REMAIN_CAP_REG1		0xE3
+#define	REMAIN_CAP_REG0		0xE4
+#define	UPDAT_LEVE_REG		0xE5
+#define	NEW_FCC_REG3		0xE6
+#define	NEW_FCC_REG2		0xE7
+#define	NEW_FCC_REG1		0xE8
+#define	NEW_FCC_REG0		0xE9
+#define NON_ACT_TIMER_CNT_SAVE_REG 0xEA
+#define OCV_VOL_VALID_REG	0xEB
+#define REBOOT_CNT_REG		0xEC
+#define POFFSET_REG		0xED
+#define MISC_MARK_REG		0xEE
+#define HALT_CNT_REG          	0xEF
+#define DATA15_REG		0xEF
+#define DATA16_REG		0xF0
+#define DATA17_REG		0xF1
+#define DATA18_REG		0xF2
+
+#endif

drivers/power/fuel_gauge/fuel_gauge_uclass.c

@@ -0,0 +1,136 @@
+/*
+ * (C) Copyright 2017 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <errno.h>
+#include <dm.h>
+#include <power/fuel_gauge.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int fuel_gauge_capability(struct udevice *dev)
+{
+	const struct dm_fuel_gauge_ops *ops = dev_get_driver_ops(dev);
+
+	if (!ops || !ops->capability)
+		return (FG_CAP_CHARGER | FG_CAP_FUEL_GAUGE);
+
+	return ops->capability(dev);
+}
+
+int fuel_gauge_bat_is_exist(struct udevice *dev)
+{
+	const struct dm_fuel_gauge_ops *ops = dev_get_driver_ops(dev);
+
+	if (!ops || !ops->bat_is_exist)
+		return -ENOSYS;
+
+	return ops->bat_is_exist(dev);
+}
+
+int fuel_gauge_get_current(struct udevice *dev)
+{
+	const struct dm_fuel_gauge_ops *ops = dev_get_driver_ops(dev);
+
+	if (!ops || !ops->get_current)
+		return -ENOSYS;
+
+	return ops->get_current(dev);
+}
+
+int fuel_gauge_get_voltage(struct udevice *dev)
+{
+	const struct dm_fuel_gauge_ops *ops = dev_get_driver_ops(dev);
+
+	if (!ops || !ops->get_voltage)
+		return -ENOSYS;
+
+	return ops->get_voltage(dev);
+}
+
+int fuel_gauge_update_get_soc(struct udevice *dev)
+{
+	const struct dm_fuel_gauge_ops *ops = dev_get_driver_ops(dev);
+
+	if (!ops || !ops->get_soc)
+		return -ENOSYS;
+
+	return ops->get_soc(dev);
+}
+
+bool fuel_gauge_get_chrg_online(struct udevice *dev)
+{
+	const struct dm_fuel_gauge_ops *ops = dev_get_driver_ops(dev);
+
+	if (!ops || !ops->get_chrg_online)
+		return -ENOSYS;
+
+	return ops->get_chrg_online(dev);
+}
+
+int fuel_gauge_get_temperature(struct udevice *dev, int *temp)
+{
+	const struct dm_fuel_gauge_ops *ops = dev_get_driver_ops(dev);
+
+	if (!ops || !ops->get_temperature)
+		return -ENOSYS;
+
+	return ops->get_temperature(dev, temp);
+}
+
+int charger_set_charger_voltage(struct udevice *dev, int uV)
+{
+	const struct dm_fuel_gauge_ops *ops = dev_get_driver_ops(dev);
+
+	if (!ops || !ops->set_charger_voltage)
+		return -ENOSYS;
+
+	return ops->set_charger_voltage(dev, uV);
+}
+
+int charger_set_current(struct udevice *dev, int ichrg_uA)
+{
+	const struct dm_fuel_gauge_ops *ops = dev_get_driver_ops(dev);
+
+	if (!ops || !ops->set_charger_current)
+		return -ENOSYS;
+
+	return ops->set_charger_current(dev, ichrg_uA);
+}
+
+int charger_set_iprechg_current(struct udevice *dev, int iprechrg_uA)
+{
+	const struct dm_fuel_gauge_ops *ops = dev_get_driver_ops(dev);
+
+	if (!ops || !ops->set_iprechg_current)
+		return -ENOSYS;
+
+	return ops->set_iprechg_current(dev, iprechrg_uA);
+}
+
+int charger_set_enable(struct udevice *dev)
+{
+	const struct dm_fuel_gauge_ops *ops = dev_get_driver_ops(dev);
+
+	if (!ops || !ops->set_charger_enable)
+		return -ENOSYS;
+
+	return ops->set_charger_enable(dev);
+}
+
+int charger_set_disable(struct udevice *dev)
+{
+	const struct dm_fuel_gauge_ops *ops = dev_get_driver_ops(dev);
+
+	if (!ops || !ops->set_charger_disable)
+		return -ENOSYS;
+
+	return ops->set_charger_disable(dev);
+}
+
+UCLASS_DRIVER(fuel_guage) = {
+	.id		= UCLASS_FG,
+	.name		= "fuel_gauge",
+};

drivers/power/power_delivery/Kconfig

@@ -0,0 +1,40 @@
+# SPDX-License-Identifier: GPL-2.0
+
+config DM_POWER_DELIVERY
+	bool "Enable driver model power delivery support"
+	depends on DM
+	help
+	  This adds a simple uclass for power delivery.
+
+config TYPEC_TCPM
+	tristate "USB Type-C Port Controller Manager"
+	depends on DM && DM_POWER_DELIVERY
+	help
+	  The Type-C Port Controller Manager provides a USB PD and USB Type-C
+	  state machine for use with Type-C Port Controllers.
+
+config TYPEC_TCPCI
+	tristate "Type-C Port Controller Interface driver"
+	depends on DM && DM_POWER_DELIVERY && DM_I2C
+	help
+	  Type-C Port Controller driver for TCPCI-compliant controller.
+
+if TYPEC_TCPCI
+
+config TYPEC_HUSB311
+	tristate "Hynetek HUSB311 Type-C chip driver"
+	depends on DM && DM_POWER_DELIVERY && DM_I2C
+	help
+	  Hynetek HUSB311 Type-C chip driver that works with
+	  Type-C Port Controller Manager to provide USB PD and USB
+	  Type-C functionalities.
+
+endif # TYPEC_TCPCI
+
+config TYPEC_FUSB302
+	tristate "Fairchild FUSB302 Type-C chip driver"
+	depends on DM && DM_POWER_DELIVERY && DM_I2C
+	help
+	  The Fairchild FUSB302 Type-C chip driver that works with
+	  Type-C Port Controller Manager to provide USB PD and USB
+	  Type-C functionalities.

drivers/power/power_delivery/Makefile

@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0
+
+obj-$(CONFIG_$(SPL_)DM_POWER_DELIVERY) += power_delivery_uclass.o
+obj-$(CONFIG_TYPEC_TCPM) += tcpm.o
+obj-$(CONFIG_TYPEC_FUSB302) += fusb302.o
+obj-$(CONFIG_TYPEC_TCPCI) += tcpci.o
+obj-$(CONFIG_TYPEC_HUSB311) += tcpci_husb311.o

drivers/power/power_delivery/power_delivery_uclass.c

@@ -0,0 +1,31 @@
+/*
+ * (C) Copyright 2022 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <errno.h>
+#include <dm.h>
+#include <dm/device-internal.h>
+#include <power/power_delivery/power_delivery.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int power_delivery_get_data(struct udevice *dev, struct power_delivery_data *pd_data)
+{
+	const struct dm_power_delivery_ops *ops = dev_get_driver_ops(dev);
+
+	if (!ops || !ops->get_current || !ops->get_voltage || !ops->get_online)
+		return -ENOSYS;
+
+	pd_data->voltage = ops->get_voltage(dev);
+	pd_data->current = ops->get_current(dev);
+	pd_data->online = ops->get_online(dev);
+
+	return 0;
+}
+
+UCLASS_DRIVER(power_delivery) = {
+	.id		= UCLASS_PD,
+	.name		= "power_delivery",
+};

drivers/power/power_delivery/tcpci.c

@@ -0,0 +1,778 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2015-2017 Google, Inc
+ *
+ * USB Type-C Port Controller Interface.
+ */
+
+#include <dm.h>
+#include <i2c.h>
+#include <asm/gpio.h>
+#include <power/power_delivery/pd.h>
+#include <power/power_delivery/tcpm.h>
+#include <power/power_delivery/typec.h>
+#include <power/power_delivery/power_delivery.h>
+
+#include "tcpci.h"
+
+#define PD_RETRY_COUNT 3
+
+#define tcpc_presenting_cc1_rd(reg) \
+	(!(TCPC_ROLE_CTRL_DRP & (reg)) && \
+	 (((reg) & (TCPC_ROLE_CTRL_CC1_MASK << TCPC_ROLE_CTRL_CC1_SHIFT)) == \
+	  (TCPC_ROLE_CTRL_CC_RD << TCPC_ROLE_CTRL_CC1_SHIFT)))
+#define tcpc_presenting_cc2_rd(reg) \
+	(!(TCPC_ROLE_CTRL_DRP & (reg)) && \
+	 (((reg) & (TCPC_ROLE_CTRL_CC2_MASK << TCPC_ROLE_CTRL_CC2_SHIFT)) == \
+	  (TCPC_ROLE_CTRL_CC_RD << TCPC_ROLE_CTRL_CC2_SHIFT)))
+
+struct tcpci {
+	struct udevice *dev;
+
+	struct tcpm_port *port;
+
+	bool controls_vbus;
+	bool gpio_cc_int_present;
+
+	struct tcpc_dev tcpc;
+	struct tcpci_data *data;
+	struct gpio_desc gpio_cc_int;
+};
+
+struct tcpci_chip {
+	struct udevice *udev;
+	struct tcpci *tcpci;
+	struct tcpci_data data;
+};
+
+static inline struct tcpci *tcpc_to_tcpci(struct tcpc_dev *tcpc)
+{
+	return container_of(tcpc, struct tcpci, tcpc);
+}
+
+static int tcpci_read16(struct tcpci *tcpci, unsigned int reg, u16 *val)
+{
+	int ret = 0;
+	u8 buffer[2];
+
+	ret = dm_i2c_read(tcpci->dev, reg, buffer, 2);
+	if (ret) {
+		printf("%s: cannot read %02x, ret=%d\n",
+			__func__, reg, ret);
+		return ret;
+	}
+
+	*val = ((buffer[1] << 8) & 0xFF00) | (buffer[0] & 0xFF);
+
+	return ret;
+}
+
+static int tcpci_block_read(struct tcpci *tcpci, unsigned int reg,
+			    u8 *data, u8 length)
+{
+	int ret = 0;
+
+	ret = dm_i2c_read(tcpci->dev, reg, data, length);
+	if (ret)
+		printf("%s: cannot block read 0x%02x, len=%d, ret=%d\n",
+			__func__, reg, length, ret);
+
+	return ret;
+}
+
+static int tcpci_write16(struct tcpci *tcpci, unsigned int reg, u16 val)
+{
+	int ret = 0;
+	u8 buffer[2];
+
+	buffer[0] = val & 0xFF;
+	buffer[1] = (val >> 8) & 0xFF;
+	ret = dm_i2c_write(tcpci->dev, reg, buffer, 2);
+	if (ret)
+		printf("%s: cannot write 0x%02x, ret=%d\n",
+			__func__, reg, ret);
+
+	return ret;
+}
+
+static int tcpci_block_write(struct tcpci *tcpci, unsigned int reg,
+			     u8 *data, u8 length)
+{
+	int ret = 0;
+
+	ret = dm_i2c_write(tcpci->dev, reg, data, length);
+	if (ret)
+		printf("%s: cannot block write 0x%02x, len=%d, ret=%d\n",
+			__func__, reg, length, ret);
+
+	return ret;
+}
+
+static int tcpci_set_cc(struct tcpc_dev *tcpc, enum typec_cc_status cc)
+{
+	struct tcpci *tcpci = tcpc_to_tcpci(tcpc);
+	unsigned int reg;
+	int ret;
+
+	switch (cc) {
+	case TYPEC_CC_RA:
+		reg = (TCPC_ROLE_CTRL_CC_RA << TCPC_ROLE_CTRL_CC1_SHIFT) |
+			(TCPC_ROLE_CTRL_CC_RA << TCPC_ROLE_CTRL_CC2_SHIFT);
+		break;
+	case TYPEC_CC_RD:
+		reg = (TCPC_ROLE_CTRL_CC_RD << TCPC_ROLE_CTRL_CC1_SHIFT) |
+			(TCPC_ROLE_CTRL_CC_RD << TCPC_ROLE_CTRL_CC2_SHIFT);
+		break;
+	case TYPEC_CC_RP_DEF:
+		reg = (TCPC_ROLE_CTRL_CC_RP << TCPC_ROLE_CTRL_CC1_SHIFT) |
+			(TCPC_ROLE_CTRL_CC_RP << TCPC_ROLE_CTRL_CC2_SHIFT) |
+			(TCPC_ROLE_CTRL_RP_VAL_DEF <<
+			 TCPC_ROLE_CTRL_RP_VAL_SHIFT);
+		break;
+	case TYPEC_CC_RP_1_5:
+		reg = (TCPC_ROLE_CTRL_CC_RP << TCPC_ROLE_CTRL_CC1_SHIFT) |
+			(TCPC_ROLE_CTRL_CC_RP << TCPC_ROLE_CTRL_CC2_SHIFT) |
+			(TCPC_ROLE_CTRL_RP_VAL_1_5 <<
+			 TCPC_ROLE_CTRL_RP_VAL_SHIFT);
+		break;
+	case TYPEC_CC_RP_3_0:
+		reg = (TCPC_ROLE_CTRL_CC_RP << TCPC_ROLE_CTRL_CC1_SHIFT) |
+			(TCPC_ROLE_CTRL_CC_RP << TCPC_ROLE_CTRL_CC2_SHIFT) |
+			(TCPC_ROLE_CTRL_RP_VAL_3_0 <<
+			 TCPC_ROLE_CTRL_RP_VAL_SHIFT);
+		break;
+	case TYPEC_CC_OPEN:
+	default:
+		reg = (TCPC_ROLE_CTRL_CC_OPEN << TCPC_ROLE_CTRL_CC1_SHIFT) |
+			(TCPC_ROLE_CTRL_CC_OPEN << TCPC_ROLE_CTRL_CC2_SHIFT);
+		break;
+	}
+
+	ret = dm_i2c_reg_write(tcpci->dev, TCPC_ROLE_CTRL, reg);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
+static int tcpci_start_toggling(struct tcpc_dev *tcpc,
+				enum typec_port_type port_type,
+				enum typec_cc_status cc)
+{
+	int ret;
+	struct tcpci *tcpci = tcpc_to_tcpci(tcpc);
+	unsigned int reg = TCPC_ROLE_CTRL_DRP;
+
+	if (port_type != TYPEC_PORT_DRP)
+		return -EOPNOTSUPP;
+
+	/* Handle vendor drp toggling */
+	if (tcpci->data->start_drp_toggling) {
+		ret = tcpci->data->start_drp_toggling(tcpci, tcpci->data, cc);
+		if (ret < 0)
+			return ret;
+	}
+
+	switch (cc) {
+	default:
+	case TYPEC_CC_RP_DEF:
+		reg |= (TCPC_ROLE_CTRL_RP_VAL_DEF <<
+			TCPC_ROLE_CTRL_RP_VAL_SHIFT);
+		break;
+	case TYPEC_CC_RP_1_5:
+		reg |= (TCPC_ROLE_CTRL_RP_VAL_1_5 <<
+			TCPC_ROLE_CTRL_RP_VAL_SHIFT);
+		break;
+	case TYPEC_CC_RP_3_0:
+		reg |= (TCPC_ROLE_CTRL_RP_VAL_3_0 <<
+			TCPC_ROLE_CTRL_RP_VAL_SHIFT);
+		break;
+	}
+
+	if (cc == TYPEC_CC_RD)
+		reg |= (TCPC_ROLE_CTRL_CC_RD << TCPC_ROLE_CTRL_CC1_SHIFT) |
+			   (TCPC_ROLE_CTRL_CC_RD << TCPC_ROLE_CTRL_CC2_SHIFT);
+	else
+		reg |= (TCPC_ROLE_CTRL_CC_RP << TCPC_ROLE_CTRL_CC1_SHIFT) |
+			   (TCPC_ROLE_CTRL_CC_RP << TCPC_ROLE_CTRL_CC2_SHIFT);
+	ret = dm_i2c_reg_write(tcpci->dev, TCPC_ROLE_CTRL, reg);
+	if (ret < 0)
+		return ret;
+	return dm_i2c_reg_write(tcpci->dev, TCPC_COMMAND,
+				TCPC_CMD_LOOK4CONNECTION);
+}
+
+static enum typec_cc_status tcpci_to_typec_cc(unsigned int cc, bool sink)
+{
+	switch (cc) {
+	case 0x1:
+		return sink ? TYPEC_CC_RP_DEF : TYPEC_CC_RA;
+	case 0x2:
+		return sink ? TYPEC_CC_RP_1_5 : TYPEC_CC_RD;
+	case 0x3:
+		if (sink)
+			return TYPEC_CC_RP_3_0;
+		/* fall through */
+	case 0x0:
+	default:
+		return TYPEC_CC_OPEN;
+	}
+}
+
+static int tcpci_get_cc(struct tcpc_dev *tcpc,
+			enum typec_cc_status *cc1, enum typec_cc_status *cc2)
+{
+	struct tcpci *tcpci = tcpc_to_tcpci(tcpc);
+	unsigned int reg, role_control;
+
+	role_control = dm_i2c_reg_read(tcpci->dev, TCPC_ROLE_CTRL);
+	if (role_control < 0)
+		return role_control;
+
+	reg = dm_i2c_reg_read(tcpci->dev, TCPC_CC_STATUS);
+	if (reg < 0)
+		return reg;
+
+	*cc1 = tcpci_to_typec_cc((reg >> TCPC_CC_STATUS_CC1_SHIFT) &
+				 TCPC_CC_STATUS_CC1_MASK,
+				 reg & TCPC_CC_STATUS_TERM ||
+				 tcpc_presenting_cc1_rd(role_control));
+	*cc2 = tcpci_to_typec_cc((reg >> TCPC_CC_STATUS_CC2_SHIFT) &
+				 TCPC_CC_STATUS_CC2_MASK,
+				 reg & TCPC_CC_STATUS_TERM ||
+				 tcpc_presenting_cc2_rd(role_control));
+
+	return 0;
+}
+
+static int tcpci_set_polarity(struct tcpc_dev *tcpc,
+			      enum typec_cc_polarity polarity)
+{
+	struct tcpci *tcpci = tcpc_to_tcpci(tcpc);
+	unsigned int reg;
+	int ret;
+	enum typec_cc_status cc1, cc2;
+
+	/* Obtain Rp setting from role control */
+	reg = dm_i2c_reg_read(tcpci->dev, TCPC_ROLE_CTRL);
+	if (reg < 0)
+		return reg;
+
+	ret = tcpci_get_cc(tcpc, &cc1, &cc2);
+	if (ret < 0)
+		return ret;
+
+	/*
+	 * When port has drp toggling enabled, ROLE_CONTROL would only have the initial
+	 * terminations for the toggling and does not indicate the final cc
+	 * terminations when ConnectionResult is 0 i.e. drp toggling stops and
+	 * the connection is resolbed. Infer port role from TCPC_CC_STATUS based on the
+	 * terminations seen. The port role is then used to set the cc terminations.
+	 */
+	if (reg & TCPC_ROLE_CTRL_DRP) {
+		/* Disable DRP for the OPEN setting to take effect */
+		reg = reg & ~TCPC_ROLE_CTRL_DRP;
+
+		if (polarity == TYPEC_POLARITY_CC2) {
+			reg &= ~(TCPC_ROLE_CTRL_CC2_MASK << TCPC_ROLE_CTRL_CC2_SHIFT);
+			/* Local port is source */
+			if (cc2 == TYPEC_CC_RD)
+				/* Role control would have the Rp setting when DRP was enabled */
+				reg |= TCPC_ROLE_CTRL_CC_RP << TCPC_ROLE_CTRL_CC2_SHIFT;
+			else
+				reg |= TCPC_ROLE_CTRL_CC_RD << TCPC_ROLE_CTRL_CC2_SHIFT;
+		} else {
+			reg &= ~(TCPC_ROLE_CTRL_CC1_MASK << TCPC_ROLE_CTRL_CC1_SHIFT);
+			/* Local port is source */
+			if (cc1 == TYPEC_CC_RD)
+				/* Role control would have the Rp setting when DRP was enabled */
+				reg |= TCPC_ROLE_CTRL_CC_RP << TCPC_ROLE_CTRL_CC1_SHIFT;
+			else
+				reg |= TCPC_ROLE_CTRL_CC_RD << TCPC_ROLE_CTRL_CC1_SHIFT;
+		}
+	}
+
+	if (polarity == TYPEC_POLARITY_CC2)
+		reg |= TCPC_ROLE_CTRL_CC_OPEN << TCPC_ROLE_CTRL_CC1_SHIFT;
+	else
+		reg |= TCPC_ROLE_CTRL_CC_OPEN << TCPC_ROLE_CTRL_CC2_SHIFT;
+	ret = dm_i2c_reg_write(tcpci->dev, TCPC_ROLE_CTRL, reg);
+	if (ret < 0)
+		return ret;
+
+	return dm_i2c_reg_write(tcpci->dev, TCPC_TCPC_CTRL,
+			(polarity == TYPEC_POLARITY_CC2) ?
+			 TCPC_TCPC_CTRL_ORIENTATION : 0);
+}
+
+static int tcpci_set_vconn(struct tcpc_dev *tcpc, bool enable)
+{
+	struct tcpci *tcpci = tcpc_to_tcpci(tcpc);
+	int ret;
+	unsigned int reg;
+
+	/* Handle vendor set vconn */
+	if (tcpci->data->set_vconn) {
+		ret = tcpci->data->set_vconn(tcpci, tcpci->data, enable);
+		if (ret < 0)
+			return ret;
+	}
+
+	reg = dm_i2c_reg_read(tcpci->dev, TCPC_POWER_CTRL);
+	if (reg)
+		return reg;
+	reg &= ~TCPC_POWER_CTRL_VCONN_ENABLE;
+	reg |= enable ? TCPC_POWER_CTRL_VCONN_ENABLE : 0;
+	return dm_i2c_reg_write(tcpci->dev, TCPC_POWER_CTRL, reg);
+}
+
+static int tcpci_set_roles(struct tcpc_dev *tcpc, bool attached,
+			   enum typec_role role, enum typec_data_role data)
+{
+	struct tcpci *tcpci = tcpc_to_tcpci(tcpc);
+	unsigned int reg;
+	int ret;
+
+	reg = PD_REV20 << TCPC_MSG_HDR_INFO_REV_SHIFT;
+	if (role == TYPEC_SOURCE)
+		reg |= TCPC_MSG_HDR_INFO_PWR_ROLE;
+	if (data == TYPEC_HOST)
+		reg |= TCPC_MSG_HDR_INFO_DATA_ROLE;
+	ret = dm_i2c_reg_write(tcpci->dev, TCPC_MSG_HDR_INFO, reg);
+	if (ret < 0)
+		return ret;
+
+	return 0;
+}
+
+static int tcpci_set_pd_rx(struct tcpc_dev *tcpc, bool enable)
+{
+	struct tcpci *tcpci = tcpc_to_tcpci(tcpc);
+	unsigned int reg = 0;
+	int ret;
+
+	if (enable)
+		reg = TCPC_RX_DETECT_SOP | TCPC_RX_DETECT_HARD_RESET;
+	ret = dm_i2c_reg_write(tcpci->dev, TCPC_RX_DETECT, reg);
+	if (ret < 0)
+		return ret;
+
+	return 0;
+}
+
+static int tcpci_get_vbus(struct tcpc_dev *tcpc)
+{
+	struct tcpci *tcpci = tcpc_to_tcpci(tcpc);
+	unsigned int reg;
+
+	reg = dm_i2c_reg_read(tcpci->dev, TCPC_POWER_STATUS);
+	if (reg < 0)
+		return reg;
+
+	return !!(reg & TCPC_POWER_STATUS_VBUS_PRES);
+}
+
+static int tcpci_set_vbus(struct tcpc_dev *tcpc, bool source, bool sink)
+{
+	struct tcpci *tcpci = tcpc_to_tcpci(tcpc);
+	int ret;
+
+	/* Disable both source and sink first before enabling anything */
+
+	if (!source) {
+		ret = dm_i2c_reg_write(tcpci->dev, TCPC_COMMAND,
+				       TCPC_CMD_DISABLE_SRC_VBUS);
+		if (ret < 0)
+			return ret;
+	}
+
+	if (!sink) {
+		ret = dm_i2c_reg_write(tcpci->dev, TCPC_COMMAND,
+				       TCPC_CMD_DISABLE_SINK_VBUS);
+		if (ret < 0)
+			return ret;
+	}
+
+	if (source) {
+		ret = dm_i2c_reg_write(tcpci->dev, TCPC_COMMAND,
+				       TCPC_CMD_SRC_VBUS_DEFAULT);
+		if (ret < 0)
+			return ret;
+	}
+
+	if (sink) {
+		ret = dm_i2c_reg_write(tcpci->dev, TCPC_COMMAND,
+				       TCPC_CMD_SINK_VBUS);
+		if (ret < 0)
+			return ret;
+	}
+
+	return 0;
+}
+
+static int tcpci_pd_transmit(struct tcpc_dev *tcpc,
+			     enum tcpm_transmit_type type,
+			     const struct pd_message *msg,
+			     unsigned int negotiated_rev)
+{
+	struct tcpci *tcpci = tcpc_to_tcpci(tcpc);
+	u16 header = msg ? le16_to_cpu(msg->header) : 0;
+	unsigned int reg, cnt;
+	int ret;
+
+	cnt = msg ? pd_header_cnt(header) * 4 : 0;
+	ret = dm_i2c_reg_write(tcpci->dev, TCPC_TX_BYTE_CNT, cnt + 2);
+	if (ret < 0)
+		return ret;
+
+	ret = tcpci_write16(tcpci, TCPC_TX_HDR, header);
+	if (ret < 0)
+		return ret;
+
+	if (cnt > 0) {
+		ret = tcpci_block_write(tcpci, TCPC_TX_DATA,
+				       (u8 *)&msg->payload, cnt);
+		if (ret < 0)
+			return ret;
+	}
+
+	reg = (PD_RETRY_COUNT << TCPC_TRANSMIT_RETRY_SHIFT) |
+		(type << TCPC_TRANSMIT_TYPE_SHIFT);
+	ret = dm_i2c_reg_write(tcpci->dev, TCPC_TRANSMIT, reg);
+	if (ret < 0)
+		return ret;
+
+	return 0;
+}
+
+static int tcpci_init(struct tcpc_dev *tcpc)
+{
+	struct tcpci *tcpci = tcpc_to_tcpci(tcpc);
+	unsigned int timeout = 0; /* XXX */
+	unsigned int reg;
+	int ret;
+
+	while (timeout < 100) {
+		reg = dm_i2c_reg_read(tcpci->dev, TCPC_POWER_STATUS);
+		if (reg < 0)
+			return reg;
+		if (!(reg & TCPC_POWER_STATUS_UNINIT))
+			break;
+		timeout++;
+		udelay(200);
+	}
+	if (timeout >= 100)
+		return -ETIMEDOUT;
+
+	/* Handle vendor init */
+	if (tcpci->data->init) {
+		ret = tcpci->data->init(tcpci, tcpci->data);
+		if (ret < 0)
+			return ret;
+	}
+
+	/* Clear all events */
+	ret = tcpci_write16(tcpci, TCPC_ALERT, 0xffff);
+	if (ret < 0)
+		return ret;
+
+	if (tcpci->controls_vbus)
+		reg = TCPC_POWER_STATUS_VBUS_PRES;
+	else
+		reg = 0;
+	ret = dm_i2c_reg_write(tcpci->dev, TCPC_POWER_STATUS_MASK, reg);
+	if (ret < 0)
+		return ret;
+
+	/* Enable Vbus detection */
+	ret = dm_i2c_reg_write(tcpci->dev, TCPC_COMMAND,
+			       TCPC_CMD_ENABLE_VBUS_DETECT);
+	if (ret < 0)
+		return ret;
+
+	reg = TCPC_ALERT_TX_SUCCESS | TCPC_ALERT_TX_FAILED |
+		TCPC_ALERT_TX_DISCARDED | TCPC_ALERT_RX_STATUS |
+		TCPC_ALERT_RX_HARD_RST | TCPC_ALERT_CC_STATUS;
+	if (tcpci->controls_vbus)
+		reg |= TCPC_ALERT_POWER_STATUS;
+	return tcpci_write16(tcpci, TCPC_ALERT_MASK, reg);
+}
+
+static void tcpci_poll_event(struct tcpc_dev *tcpc)
+{
+	u16 status;
+	struct tcpci *tcpci = tcpc_to_tcpci(tcpc);
+
+	tcpci_read16(tcpci, TCPC_ALERT, &status);
+
+	/*
+	 * Clear alert status for everything except RX_STATUS, which shouldn't
+	 * be cleared until we have successfully retrieved message.
+	 */
+	if (status & ~TCPC_ALERT_RX_STATUS)
+		tcpci_write16(tcpci, TCPC_ALERT,
+			      status & ~TCPC_ALERT_RX_STATUS);
+
+	if (status & TCPC_ALERT_CC_STATUS)
+		tcpm_cc_change(tcpci->port);
+
+	if (status & TCPC_ALERT_POWER_STATUS) {
+		unsigned int reg;
+
+		reg = dm_i2c_reg_read(tcpci->dev, TCPC_POWER_STATUS_MASK);
+		if (reg < 0)
+			return;
+
+		/*
+		 * If power status mask has been reset, then the TCPC
+		 * has reset.
+		 */
+		if (reg == 0xff)
+			tcpm_tcpc_reset(tcpci->port);
+		else
+			tcpm_vbus_change(tcpci->port);
+	}
+
+	if (status & TCPC_ALERT_RX_STATUS) {
+		struct pd_message msg;
+		unsigned int cnt, payload_cnt;
+		u16 header;
+
+		cnt = dm_i2c_reg_read(tcpci->dev, TCPC_RX_BYTE_CNT);
+		if (cnt < 0)
+			return;
+		/*
+		 * 'cnt' corresponds to READABLE_BYTE_COUNT in section 4.4.14
+		 * of the TCPCI spec [Rev 2.0 Ver 1.0 October 2017] and is
+		 * defined in table 4-36 as one greater than the number of
+		 * bytes received. And that number includes the header. So:
+		 */
+		if (cnt > 3)
+			payload_cnt = cnt - (1 + sizeof(msg.header));
+		else
+			payload_cnt = 0;
+
+		tcpci_read16(tcpci, TCPC_RX_HDR, &header);
+		msg.header = cpu_to_le16(header);
+
+		if ((payload_cnt > sizeof(msg.payload)))
+			payload_cnt = sizeof(msg.payload);
+
+		if (payload_cnt > 0)
+			tcpci_block_read(tcpci, TCPC_RX_DATA,
+					(u8 *)&msg.payload, payload_cnt);
+
+		/* Read complete, clear RX status alert bit */
+		tcpci_write16(tcpci, TCPC_ALERT, TCPC_ALERT_RX_STATUS);
+
+		tcpm_pd_receive(tcpci->port, &msg);
+	}
+
+	if (status & TCPC_ALERT_RX_HARD_RST)
+		tcpm_pd_hard_reset(tcpci->port);
+
+	if (status & TCPC_ALERT_TX_SUCCESS)
+		tcpm_pd_transmit_complete(tcpci->port, TCPC_TX_SUCCESS);
+	else if (status & TCPC_ALERT_TX_DISCARDED)
+		tcpm_pd_transmit_complete(tcpci->port, TCPC_TX_DISCARDED);
+	else if (status & TCPC_ALERT_TX_FAILED)
+		tcpm_pd_transmit_complete(tcpci->port, TCPC_TX_FAILED);
+}
+
+static int tcpci_enter_low_power_mode(struct tcpc_dev *tcpc,
+				      bool attached, bool pd_capable)
+{
+	int ret;
+	struct tcpci *tcpci = tcpc_to_tcpci(tcpc);
+	unsigned int reg;
+
+	/* Disable chip interrupts before unregistering port */
+	ret = tcpci_write16(tcpci, TCPC_ALERT_MASK, 0);
+	if (ret < 0)
+		return ret;
+
+	reg = dm_i2c_reg_read(tcpci->dev, TCPC_BMCIO_CTRL);
+	if (reg < 0)
+		return reg;
+	/*
+	 * For Type-C devices with PD capability, Only disable VBUS detect,
+	 * do not diable 24M oscillator for BMC communication. Otherwise,
+	 * data packets cannot be received.
+	 */
+	if (attached && pd_capable)
+		reg &= ~TCPC_BMCIO_VBUS_DETECT_MASK;
+	else
+		reg &= ~(TCPC_BMCIO_VBUS_DETECT_MASK | TCPC_BMCIO_24M_OSC_MASK);
+	return dm_i2c_reg_write(tcpci->dev, TCPC_BMCIO_CTRL, reg);
+}
+
+static int tcpci_parse_config(struct tcpci *tcpci)
+{
+	tcpci->controls_vbus = true; /* XXX */
+
+	tcpci->tcpc.connector_node = dev_read_subnode(tcpci->dev, "connector");
+	if (!ofnode_valid(tcpci->tcpc.connector_node)) {
+		printf("%s: 'connector' node is not found\n", __func__);
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+struct tcpci *tcpci_register_port(struct udevice *dev, struct tcpci_data *data)
+{
+	struct tcpci *tcpci;
+	int err;
+
+	tcpci = devm_kzalloc(dev, sizeof(*tcpci), GFP_KERNEL);
+	if (!tcpci)
+		return ERR_PTR(-ENOMEM);
+
+	err = gpio_request_by_name(dev, "int-n-gpios", 0, &tcpci->gpio_cc_int, GPIOD_IS_IN);
+	if (err) {
+		printf("%s: fail to get int GPIO: err=%d\n", __func__, err);
+		tcpci->gpio_cc_int_present = false;
+	} else {
+		printf("%s: success to get int GPIO: err=%d\n", __func__, err);
+		tcpci->gpio_cc_int_present = true;
+	}
+
+	tcpci->dev = dev;
+	tcpci->data = data;
+
+	tcpci->tcpc.init = tcpci_init;
+	tcpci->tcpc.get_vbus = tcpci_get_vbus;
+	tcpci->tcpc.set_vbus = tcpci_set_vbus;
+	tcpci->tcpc.set_cc = tcpci_set_cc;
+	tcpci->tcpc.get_cc = tcpci_get_cc;
+	tcpci->tcpc.set_polarity = tcpci_set_polarity;
+	tcpci->tcpc.set_vconn = tcpci_set_vconn;
+	tcpci->tcpc.start_toggling = tcpci_start_toggling;
+
+	tcpci->tcpc.set_pd_rx = tcpci_set_pd_rx;
+	tcpci->tcpc.set_roles = tcpci_set_roles;
+	tcpci->tcpc.pd_transmit = tcpci_pd_transmit;
+	tcpci->tcpc.poll_event = tcpci_poll_event;
+	tcpci->tcpc.enter_low_power_mode = tcpci_enter_low_power_mode;
+
+	err = tcpci_parse_config(tcpci);
+	if (err < 0)
+		return ERR_PTR(err);
+
+	tcpci->port = tcpm_port_init(tcpci->dev, &tcpci->tcpc);
+	if (IS_ERR(tcpci->port)) {
+		printf("%s: failed to tcpm port init\n", __func__);
+		return ERR_CAST(tcpci->port);
+	}
+
+	// tcpm_tcpc_reset(tcpci->port);
+
+	tcpm_poll_event(tcpci->port);
+
+	return tcpci;
+}
+EXPORT_SYMBOL_GPL(tcpci_register_port);
+
+void tcpci_unregister_port(struct tcpci *tcpci)
+{
+	tcpm_uninit_port(tcpci->port);
+}
+EXPORT_SYMBOL_GPL(tcpci_unregister_port);
+
+int tcpci_get_voltage_fun(struct tcpci *tcpci)
+{
+	return tcpm_get_voltage(tcpci->port);
+}
+EXPORT_SYMBOL_GPL(tcpci_get_voltage_fun);
+
+int tcpci_get_current_fun(struct tcpci *tcpci)
+{
+	return tcpm_get_current(tcpci->port);
+}
+EXPORT_SYMBOL_GPL(tcpci_get_current_fun);
+
+int tcpci_get_online_fun(struct tcpci *tcpci)
+{
+	return tcpm_get_online(tcpci->port);
+}
+EXPORT_SYMBOL_GPL(tcpci_get_online_fun);
+
+static int tcpci_probe(struct udevice *dev)
+{
+	struct tcpci_chip *chip = dev_get_priv(dev);
+	int err;
+	u16 val = 0;
+
+	chip->udev = dev;
+
+	/* Disable chip interrupts before requesting irq */
+	err = tcpci_write16(chip->tcpci, TCPC_ALERT_MASK, val);
+	if (err < 0)
+		return err;
+
+	chip->tcpci = tcpci_register_port(chip->udev, &chip->data);
+	if (IS_ERR(chip->tcpci))
+		return PTR_ERR(chip->tcpci);
+
+	return 0;
+}
+
+static int tcpci_remove(struct udevice *dev)
+{
+	struct tcpci_chip *chip = dev_get_priv(dev);
+	int err;
+
+	/* Disable chip interrupts before unregistering port */
+	err = tcpci_write16(chip->tcpci, TCPC_ALERT_MASK, 0);
+	if (err < 0)
+		return err;
+
+	tcpci_unregister_port(chip->tcpci);
+
+	return 0;
+}
+
+static int tcpci_get_voltage(struct udevice *dev)
+{
+	struct tcpci_chip *chip = dev_get_priv(dev);
+
+	return tcpm_get_voltage(chip->tcpci->port);
+}
+
+static int tcpci_get_current(struct udevice *dev)
+{
+	struct tcpci_chip *chip = dev_get_priv(dev);
+
+	return tcpm_get_current(chip->tcpci->port);
+}
+
+static int tcpci_get_online(struct udevice *dev)
+{
+	struct tcpci_chip *chip = dev_get_priv(dev);
+
+	return tcpm_get_online(chip->tcpci->port);
+}
+
+static struct dm_power_delivery_ops tcpci_ops = {
+	.get_voltage = tcpci_get_voltage,
+	.get_current = tcpci_get_current,
+	.get_online = tcpci_get_online,
+};
+
+static const struct udevice_id tcpci_ids[] = {
+	{ .compatible = "nxp,ptn5110", },
+	{},
+};
+
+U_BOOT_DRIVER(tcpci) = {
+	.name = "tcpci",
+	.id = UCLASS_PD,
+	.of_match = tcpci_ids,
+	.ops = &tcpci_ops,
+	.probe = tcpci_probe,
+	.remove = tcpci_remove,
+	.priv_auto_alloc_size = sizeof(struct tcpci_chip),
+}
+
+MODULE_DESCRIPTION("USB Type-C Port Controller Interface driver");
+MODULE_LICENSE("GPL");

drivers/power/power_delivery/tcpci.h

@@ -0,0 +1,150 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2015-2017 Google, Inc
+ *
+ * USB Type-C Port Controller Interface.
+ */
+
+#ifndef __LINUX_USB_TCPCI_H
+#define __LINUX_USB_TCPCI_H
+
+#define TCPC_VENDOR_ID			0x0
+#define TCPC_PRODUCT_ID			0x2
+#define TCPC_BCD_DEV			0x4
+#define TCPC_TC_REV			0x6
+#define TCPC_PD_REV			0x8
+#define TCPC_PD_INT_REV			0xa
+
+#define TCPC_ALERT			0x10
+#define TCPC_ALERT_VBUS_DISCNCT		BIT(11)
+#define TCPC_ALERT_RX_BUF_OVF		BIT(10)
+#define TCPC_ALERT_FAULT		BIT(9)
+#define TCPC_ALERT_V_ALARM_LO		BIT(8)
+#define TCPC_ALERT_V_ALARM_HI		BIT(7)
+#define TCPC_ALERT_TX_SUCCESS		BIT(6)
+#define TCPC_ALERT_TX_DISCARDED		BIT(5)
+#define TCPC_ALERT_TX_FAILED		BIT(4)
+#define TCPC_ALERT_RX_HARD_RST		BIT(3)
+#define TCPC_ALERT_RX_STATUS		BIT(2)
+#define TCPC_ALERT_POWER_STATUS		BIT(1)
+#define TCPC_ALERT_CC_STATUS		BIT(0)
+
+#define TCPC_ALERT_MASK			0x12
+#define TCPC_POWER_STATUS_MASK		0x14
+#define TCPC_FAULT_STATUS_MASK		0x15
+#define TCPC_CONFIG_STD_OUTPUT		0x18
+
+#define TCPC_TCPC_CTRL			0x19
+#define TCPC_TCPC_CTRL_ORIENTATION	BIT(0)
+
+#define TCPC_ROLE_CTRL			0x1a
+#define TCPC_ROLE_CTRL_DRP		BIT(6)
+#define TCPC_ROLE_CTRL_RP_VAL_SHIFT	4
+#define TCPC_ROLE_CTRL_RP_VAL_MASK	0x3
+#define TCPC_ROLE_CTRL_RP_VAL_DEF	0x0
+#define TCPC_ROLE_CTRL_RP_VAL_1_5	0x1
+#define TCPC_ROLE_CTRL_RP_VAL_3_0	0x2
+#define TCPC_ROLE_CTRL_CC2_SHIFT	2
+#define TCPC_ROLE_CTRL_CC2_MASK		0x3
+#define TCPC_ROLE_CTRL_CC1_SHIFT	0
+#define TCPC_ROLE_CTRL_CC1_MASK		0x3
+#define TCPC_ROLE_CTRL_CC_RA		0x0
+#define TCPC_ROLE_CTRL_CC_RP		0x1
+#define TCPC_ROLE_CTRL_CC_RD		0x2
+#define TCPC_ROLE_CTRL_CC_OPEN		0x3
+
+#define TCPC_FAULT_CTRL			0x1b
+
+#define TCPC_POWER_CTRL			0x1c
+#define TCPC_POWER_CTRL_VCONN_ENABLE	BIT(0)
+
+#define TCPC_CC_STATUS			0x1d
+#define TCPC_CC_STATUS_TOGGLING		BIT(5)
+#define TCPC_CC_STATUS_TERM		BIT(4)
+#define TCPC_CC_STATUS_CC2_SHIFT	2
+#define TCPC_CC_STATUS_CC2_MASK		0x3
+#define TCPC_CC_STATUS_CC1_SHIFT	0
+#define TCPC_CC_STATUS_CC1_MASK		0x3
+
+#define TCPC_POWER_STATUS		0x1e
+#define TCPC_POWER_STATUS_UNINIT	BIT(6)
+#define TCPC_POWER_STATUS_VBUS_DET	BIT(3)
+#define TCPC_POWER_STATUS_VBUS_PRES	BIT(2)
+
+#define TCPC_FAULT_STATUS		0x1f
+
+#define TCPC_COMMAND			0x23
+#define TCPC_CMD_WAKE_I2C		0x11
+#define TCPC_CMD_DISABLE_VBUS_DETECT	0x22
+#define TCPC_CMD_ENABLE_VBUS_DETECT	0x33
+#define TCPC_CMD_DISABLE_SINK_VBUS	0x44
+#define TCPC_CMD_SINK_VBUS		0x55
+#define TCPC_CMD_DISABLE_SRC_VBUS	0x66
+#define TCPC_CMD_SRC_VBUS_DEFAULT	0x77
+#define TCPC_CMD_SRC_VBUS_HIGH		0x88
+#define TCPC_CMD_LOOK4CONNECTION	0x99
+#define TCPC_CMD_RXONEMORE		0xAA
+#define TCPC_CMD_I2C_IDLE		0xFF
+
+#define TCPC_DEV_CAP_1			0x24
+#define TCPC_DEV_CAP_2			0x26
+#define TCPC_STD_INPUT_CAP		0x28
+#define TCPC_STD_OUTPUT_CAP		0x29
+
+#define TCPC_MSG_HDR_INFO		0x2e
+#define TCPC_MSG_HDR_INFO_DATA_ROLE	BIT(3)
+#define TCPC_MSG_HDR_INFO_PWR_ROLE	BIT(0)
+#define TCPC_MSG_HDR_INFO_REV_SHIFT	1
+#define TCPC_MSG_HDR_INFO_REV_MASK	0x3
+
+#define TCPC_RX_DETECT			0x2f
+#define TCPC_RX_DETECT_HARD_RESET	BIT(5)
+#define TCPC_RX_DETECT_SOP		BIT(0)
+
+#define TCPC_RX_BYTE_CNT		0x30
+#define TCPC_RX_BUF_FRAME_TYPE		0x31
+#define TCPC_RX_HDR			0x32
+#define TCPC_RX_DATA			0x34 /* through 0x4f */
+
+#define TCPC_TRANSMIT			0x50
+#define TCPC_TRANSMIT_RETRY_SHIFT	4
+#define TCPC_TRANSMIT_RETRY_MASK	0x3
+#define TCPC_TRANSMIT_TYPE_SHIFT	0
+#define TCPC_TRANSMIT_TYPE_MASK		0x7
+
+#define TCPC_TX_BYTE_CNT		0x51
+#define TCPC_TX_HDR			0x52
+#define TCPC_TX_DATA			0x54 /* through 0x6f */
+
+#define TCPC_VBUS_VOLTAGE			0x70
+#define TCPC_VBUS_SINK_DISCONNECT_THRESH	0x72
+#define TCPC_VBUS_STOP_DISCHARGE_THRESH		0x74
+#define TCPC_VBUS_VOLTAGE_ALARM_HI_CFG		0x76
+#define TCPC_VBUS_VOLTAGE_ALARM_LO_CFG		0x78
+
+#define TCPC_BMCIO_CTRL				0x90
+#define TCPC_BMCIO_VBUS_DETECT_MASK		BIT(1)
+#define TCPC_BMCIO_VBUS_DETECT_ENABLE		BIT(1)
+#define TCPC_BMCIO_VBUS_DETECT_DISABLE		0
+#define TCPC_BMCIO_24M_OSC_MASK                 BIT(0)
+#define TCPC_BMCIO_ENABLE_24M_OSC		BIT(0)
+#define TCPC_BMCIO_DISABLE_24M_OSC		0
+
+struct tcpci;
+struct tcpci_data {
+	struct regmap *regmap;
+	int (*init)(struct tcpci *tcpci, struct tcpci_data *data);
+	int (*set_vconn)(struct tcpci *tcpci, struct tcpci_data *data,
+			 bool enable);
+	int (*start_drp_toggling)(struct tcpci *tcpci, struct tcpci_data *data,
+				  enum typec_cc_status cc);
+};
+
+struct tcpci *tcpci_register_port(struct udevice *dev, struct tcpci_data *data);
+void tcpci_unregister_port(struct tcpci *tcpci);
+int tcpci_get_voltage_fun(struct tcpci *tcpci);
+int tcpci_get_current_fun(struct tcpci *tcpci);
+int tcpci_get_online_fun(struct tcpci *tcpci);
+irqreturn_t tcpci_irq(struct tcpci *tcpci);
+
+#endif /* __LINUX_USB_TCPCI_H */

drivers/power/power_delivery/tcpci_husb311.c

@@ -0,0 +1,229 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2021 Rockchip Co.,Ltd.
+ * Author: Wang Jie <dave.wang@rock-chips.com>
+ *
+ * Hynetek Husb311 Type-C Chip Driver
+ */
+
+#include <dm.h>
+#include <i2c.h>
+#include <asm/gpio.h>
+#include <power/power_delivery/tcpm.h>
+#include <power/power_delivery/power_delivery.h>
+#include "tcpci.h"
+
+#define HUSB311_VID		0x2E99
+#define HUSB311_PID		0x0311
+#define HUSB311_TCPC_I2C_RESET	0x9E
+#define HUSB311_TCPC_SOFTRESET	0xA0
+#define HUSB311_TCPC_FILTER	0xA1
+#define HUSB311_TCPC_TDRP	0xA2
+#define HUSB311_TCPC_DCSRCDRP	0xA3
+#define HUSB311_I2C_RETRY_MAX_CNT 3
+
+struct husb311_chip {
+	struct udevice *udev;
+	struct tcpci_data data;
+	struct tcpci *tcpci;
+};
+
+static int husb311_read16(struct husb311_chip *chip, unsigned int reg)
+{
+	int ret = 0;
+	u8 buffer[2];
+
+	ret = dm_i2c_read(chip->udev, reg, buffer, 2);
+	if (ret < 0) {
+		printf("%s: cannot read %02x, ret=%d\n",
+			__func__, reg, ret);
+		return ret;
+	}
+	ret = ((buffer[1] << 8) & 0xFF00) + (buffer[0] & 0xFF);
+
+	return ret;
+}
+
+static int husb311_write8(struct husb311_chip *chip, unsigned int reg, u8 val)
+{
+	int ret = 0;
+	int i;
+
+	for (i = 0; i < HUSB311_I2C_RETRY_MAX_CNT; i++) {
+		ret = dm_i2c_write(chip->udev, reg, &val, 1);
+		if (!ret)
+			break;
+		else
+			udelay(200);
+	}
+
+	if (ret)
+		printf("%s: cannot write 0x%02x to 0x%02x, ret=%d\n",
+			__func__, val, reg, ret);
+
+	return ret;
+}
+
+static int husb311_write16(struct husb311_chip *chip, unsigned int reg, u16 val)
+{
+	int ret = 0;
+	u8 buffer[2];
+
+	buffer[0] = val & 0xFF;
+	buffer[1] = (val >> 8) & 0xFF;
+	ret = dm_i2c_write(chip->udev, reg, buffer, 2);
+	if (ret)
+		printf("%s: cannot write 0x%02x, len=%d, ret=%d\n",
+			__func__, reg, 2, ret);
+
+	return ret;
+}
+
+static struct husb311_chip *tdata_to_husb311(struct tcpci_data *tdata)
+{
+	return container_of(tdata, struct husb311_chip, data);
+}
+
+static int husb311_sw_reset(struct husb311_chip *chip)
+{
+	/* soft reset */
+	return husb311_write8(chip, HUSB311_TCPC_SOFTRESET, 0x01);
+}
+
+static int husb311_init(struct tcpci *tcpci, struct tcpci_data *tdata)
+{
+	int ret;
+	struct husb311_chip *chip = tdata_to_husb311(tdata);
+
+	/* I2C reset : (val + 1) * 12.5ms */
+	ret = husb311_write8(chip, HUSB311_TCPC_I2C_RESET, 0x8F);
+	/* tTCPCfilter : (26.7 * val) us */
+	ret |= husb311_write8(chip, HUSB311_TCPC_FILTER, 0x0F);
+	/* tDRP : (51.2 + 6.4 * val) ms */
+	ret |= husb311_write8(chip, HUSB311_TCPC_TDRP, 0x04);
+	/* dcSRC.DRP : 33% */
+	ret |= husb311_write16(chip, HUSB311_TCPC_DCSRCDRP, 330);
+
+	if (ret)
+		printf("%s: fail to init registers(%d)\n", __func__, ret);
+
+	return ret;
+}
+
+static int husb311_check_revision(struct husb311_chip *chip)
+{
+	int ret;
+
+	ret = husb311_read16(chip, TCPC_VENDOR_ID);
+	if (ret < 0) {
+		printf("%s: fail to read Vendor id(%d)\n", __func__, ret);
+		return ret;
+	}
+
+	if (ret != HUSB311_VID) {
+		printf("%s: vid is not correct, 0x%04x\n", __func__, ret);
+		return -ENODEV;
+	}
+
+	ret = husb311_read16(chip, TCPC_PRODUCT_ID);
+	if (ret < 0) {
+		printf("%s: fail to read Product id(%d)\n", __func__, ret);
+		return ret;
+	}
+
+	if (ret != HUSB311_PID) {
+		printf("%s: pid is not correct, 0x%04x\n", __func__, ret);
+		return -ENODEV;
+	}
+
+	return 0;
+}
+
+static int husb311_probe(struct udevice *dev)
+{
+	int ret;
+	struct husb311_chip *chip = dev_get_priv(dev);
+
+	chip->udev = dev;
+
+	ret = husb311_check_revision(chip);
+	if (ret < 0) {
+		printf("%s: check vid/pid fail(%d)\n", __func__, ret);
+		return ret;
+	}
+
+	ret = husb311_sw_reset(chip);
+	if (ret) {
+		printf("%s: fail to soft reset, ret = %d\n", __func__, ret);
+		return ret;
+	}
+
+	chip->data.init = husb311_init;
+	chip->tcpci = tcpci_register_port(chip->udev, &chip->data);
+	if (IS_ERR(chip->tcpci))
+		return PTR_ERR(chip->tcpci);
+
+	return 0;
+}
+
+static int husb311_remove(struct udevice *dev)
+{
+	struct husb311_chip *chip = dev_get_priv(dev);
+	int ret = 0;
+
+	printf("PD chip husb311 remove\n");
+	/* Disable chip interrupts before unregistering port */
+	ret = husb311_write16(chip, TCPC_ALERT_MASK, 0);
+	if (ret < 0)
+		return ret;
+
+	tcpci_unregister_port(chip->tcpci);
+
+	return 0;
+}
+
+static int husb311_get_voltage(struct udevice *dev)
+{
+	struct husb311_chip *chip = dev_get_priv(dev);
+
+	return tcpci_get_voltage_fun(chip->tcpci);
+}
+
+static int husb311_get_current(struct udevice *dev)
+{
+	struct husb311_chip *chip = dev_get_priv(dev);
+
+	return tcpci_get_current_fun(chip->tcpci);
+}
+
+static int husb311_get_online(struct udevice *dev)
+{
+	struct husb311_chip *chip = dev_get_priv(dev);
+
+	return tcpci_get_online_fun(chip->tcpci);
+}
+
+static struct dm_power_delivery_ops husb311_ops = {
+	.get_voltage = husb311_get_voltage,
+	.get_current = husb311_get_current,
+	.get_online = husb311_get_online,
+};
+
+static const struct udevice_id husb311_ids[] = {
+	{ .compatible = "hynetek,husb311" },
+	{},
+};
+
+U_BOOT_DRIVER(husb311) = {
+	.name = "husb311",
+	.id = UCLASS_PD,
+	.of_match = husb311_ids,
+	.ops = &husb311_ops,
+	.probe = husb311_probe,
+	.remove = husb311_remove,
+	.priv_auto_alloc_size = sizeof(struct husb311_chip),
+};
+
+MODULE_AUTHOR("Wang Jie <dave.wang@rock-chips.com>");
+MODULE_DESCRIPTION("Husb311 USB Type-C Port Controller Interface Driver");
+MODULE_LICENSE("GPL v2");

drivers/tpm/Kconfig

@@ -93,6 +93,16 @@ config TPM_ST33ZP24_SPI
 	  to the device using the standard TPM Interface Specification (TIS)
 	  protocol
 
+config TPM_Z32H330TC_SPI
+	bool "STMicroelectronics Z32H330TC SPI TPM"
+	depends on TPM_V1 && DM_SPI
+	---help---
+	  This driver supports STMicroelectronics TPM devices connected on the SP
+	  I bus.
+	  The usual tpm operations and the 'tpm' command can be used to talk
+	  to the device using the standard TPM Interface Specification (TIS)
+	  protocol
+
 config TPM_FLUSH_RESOURCES
 	bool "Enable TPM resource flushing support"
 	depends on TPM_V1

drivers/video/Kconfig

@@ -357,7 +357,14 @@ config VIDEO_LCD_MINGJUN_070BI30IA2
 	select VIDEO_MIPI_DSI
 	help
 	Say Y here if you want to enable support for Mingjun 070BI30IA2
-	800x1280 DSI video mode panel.
+        800x1280 DSI video mode panel.
+
+config VIDEO_LCD_JD9365DA
+	bool "JD9365DA DSI LCD panel support"
+	depends on DM_VIDEO
+	select VIDEO_MIPI_DSI
+	help
+	Say Y here if you want to enable support for JD9365DA
 
 config VIDEO_LCD_CUSTOM_LOGO
 	bool "LCD CUSTOM logo support"

drivers/video/Makefile

@@ -70,6 +70,7 @@ obj-$(CONFIG_VIDEO_SIMPLE) += simplefb.o
 obj-$(CONFIG_VIDEO_TEGRA20) += tegra.o
 obj-$(CONFIG_VIDEO_VCXK) += bus_vcxk.o
 obj-$(CONFIG_VIDEO_VESA) += vesa.o
+obj-$(CONFIG_VIDEO_LCD_JD9365DA) += jadard-jd9365da-h3.o
 
 obj-y += bridge/
 obj-y += sunxi/

drivers/video/ilitek-ili9881c.c

@@ -12,6 +12,7 @@ enum ili9881c_op {
 	ILI9881C_COMMAND,
 };
 
+
 struct ili9881c_instr {
 	enum ili9881c_op        op;
 
@@ -480,6 +481,7 @@ static int ili9881c_panel_ofdata_to_platdata(struct udevice *dev)
 		mdelay(100);
 	}
 
+
 	/* power gpios */
 	ret = gpio_request_by_name(dev, "lcd-en-gpios", 0,
 			&priv->lcd_en, GPIOD_IS_OUT);

drivers/video/jadard-jd9365da-h3.c

@@ -0,0 +1,238 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2019 Radxa Limited
+ * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd.
+ *
+ * Author:
+ * - Jagan Teki <jagan@amarulasolutions.com>
+ * - Stephen Chen <stephen@radxa.com>
+ */
+
+#include <common.h>
+#include <backlight.h>
+#include <dm.h>
+#include <mipi_dsi.h>
+#include <panel.h>
+#include <asm/gpio.h>
+
+struct jadard_panel_desc {
+	const struct display_timing *timing;
+	unsigned long mode_flags;
+	enum mipi_dsi_pixel_format format;
+	unsigned int lanes;
+};
+
+struct panel_info {
+	const struct jadard_panel_desc *desc;
+	struct gpio_desc	reset;
+	struct gpio_desc	hsvcc;
+	struct gpio_desc	vspn3v3;
+	bool   prepared;
+	bool   enabled;
+};
+
+static int jd9365_get_display_timing(struct udevice *dev,
+		struct display_timing *timings)
+{
+	struct mipi_dsi_panel_plat *plat = dev_get_platdata(dev);
+	struct mipi_dsi_device *device = plat->device;
+	struct panel_info *pinfo = dev_get_priv(dev);
+
+	memcpy(timings, pinfo->desc->timing, sizeof(*timings));
+
+	device->lanes	   = pinfo->desc->lanes;
+	device->format	   = pinfo->desc->format;
+	device->mode_flags = pinfo->desc->mode_flags;
+
+	return 0;
+}
+
+static int jadard_prepare(struct udevice *panel)
+{
+	struct panel_info *pinfo = dev_get_priv(panel);
+	int ret;
+
+	if (pinfo->prepared)
+		return 0;
+	dm_gpio_set_value(&pinfo->reset, false);
+
+	/* Power the panel */
+	ret = dm_gpio_set_value(&pinfo->hsvcc, true);
+	if (ret) {
+		return ret;
+	}
+
+	mdelay(1);
+	ret = dm_gpio_set_value(&pinfo->vspn3v3, true);
+	if (ret) {
+		return ret;
+	}
+	mdelay(1);
+
+	dm_gpio_set_value(&pinfo->reset, true);
+	mdelay(10);
+
+	pinfo->prepared = true;
+
+	return 0;
+}
+
+static int jadard_enable(struct udevice *panel)
+{
+	struct mipi_dsi_panel_plat *plat = dev_get_platdata(panel);
+	struct mipi_dsi_device *dsi = plat->device;
+	struct panel_info *pinfo = dev_get_priv(panel);
+	u8 power_mode;
+	int ret;
+
+	if (pinfo->enabled)
+		return 0;
+
+	dsi->mode_flags |= MIPI_DSI_MODE_LPM;
+
+	/* sanity test for connection */
+	ret = mipi_dsi_dcs_get_power_mode(dsi, &power_mode);
+	if (ret) {
+		dev_warn(dsi->dev, "%s: failed to get power mode: %d\n", __func__, ret);
+		return ret;
+	}
+
+	ret = mipi_dsi_dcs_set_tear_on(dsi, MIPI_DSI_DCS_TEAR_MODE_VBLANK);
+	if (ret)
+		return ret;
+
+	ret = mipi_dsi_dcs_exit_sleep_mode(dsi);
+	if (ret)
+	{
+		return ret;
+	}
+
+	mdelay(10);
+
+	ret = mipi_dsi_dcs_set_display_on(dsi);
+	if (ret){
+		return ret;
+	}
+
+	pinfo->enabled = true;
+
+	return 0;
+}
+
+static int jd9365_panel_enable(struct udevice *dev)
+{
+	struct mipi_dsi_panel_plat *plat   = dev_get_platdata(dev);
+	struct mipi_dsi_device     *device = plat->device;
+	int ret;
+
+	ret = mipi_dsi_attach(device);
+	if (ret < 0)
+		return ret;
+
+	ret = jadard_enable(dev);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
+static const struct display_timing txd_jd9365_timing = {
+	.pixelclock.typ		= 74250000,
+	.hactive.typ		= 800,
+	.hfront_porch.typ	= 60,
+	.hback_porch.typ	= 60,
+	.hsync_len.typ		= 40,
+	.vactive.typ		= 1280,
+	.vfront_porch.typ	= 16,
+	.vback_porch.typ	= 16,
+	.vsync_len.typ		= 8,
+	.flags			=  DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
+};
+
+static const struct jadard_panel_desc jd9365_panel_desc = {
+	.timing = &txd_jd9365_timing,
+	.mode_flags = MIPI_DSI_MODE_VIDEO |  MIPI_DSI_MODE_VIDEO_BURST,
+	.format = MIPI_DSI_FMT_RGB888,
+	.lanes = 4,
+};
+
+static int jd9365_panel_ofdata_to_platdata(struct udevice *dev)
+{
+	struct panel_info *pinfo = dev_get_priv(dev);
+	int ret;
+
+	ret = gpio_request_by_name(dev, "reset-gpio", 0,
+			&pinfo->reset, GPIOD_IS_OUT);
+	if (ret) {
+		dev_err(dev, "Warning: cannot get reset GPIO\n");
+		if (ret != -ENOENT)
+			return ret;
+	}
+
+	ret = gpio_request_by_name(dev, "hsvcc-gpio", 0,
+			&pinfo->hsvcc, GPIOD_IS_OUT);
+	if (ret) {
+		dev_err(dev, "Warning: cannot get hsvcc GPIO\n");
+		if (ret != -ENOENT)
+			return ret;
+	}
+
+	ret = gpio_request_by_name(dev, "vspn3v3-gpio", 0,
+			&pinfo->vspn3v3, GPIOD_IS_OUT);
+	if (ret) {
+		dev_err(dev, "Warning: cannot get vspn3v3 GPIO\n");
+		if (ret != -ENOENT)
+			return ret;
+	}
+
+	return 0;
+}
+
+static int jadard_dsi_probe(struct udevice *panel)
+{
+	int ret;
+	struct panel_info *pinfo = dev_get_priv(panel);
+
+	pinfo->desc = (const struct jadard_panel_desc*)dev_get_driver_data(panel);
+
+	ret = jadard_prepare(panel);
+	if (ret) {
+		dev_err(panel, "failed to prepare panel : %d\n", ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+static int jadard_dsi_remove(struct udevice *panel)
+{
+	return 0;
+}
+
+static const struct panel_ops jd9365_panel_ops = {
+	.enable_backlight	= jd9365_panel_enable,
+	.get_display_timing	= jd9365_get_display_timing,
+};
+
+static const struct udevice_id panel_of_match[] = {
+	{
+		.compatible = "jadard,jd9365da-h3",
+		.data = (ulong)&jd9365_panel_desc,
+	},
+	{
+		/* sentinel */
+	}
+};
+
+U_BOOT_DRIVER(jadard_jd9365da) = {
+	.name 			  = "jadard_jd9365da",
+	.id			      = UCLASS_PANEL,
+	.of_match		  = panel_of_match,
+	.ops			  = &jd9365_panel_ops,
+	.ofdata_to_platdata	  = jd9365_panel_ofdata_to_platdata,
+	.probe			  = jadard_dsi_probe,
+	.remove			  = jadard_dsi_remove,
+	.platdata_auto_alloc_size = sizeof(struct mipi_dsi_panel_plat),
+	.priv_auto_alloc_size	  = sizeof(struct panel_info),
+};
+

env/env.c

@@ -243,7 +243,7 @@ int env_save(void)
 		if (!env_has_inited(drv->location))
 			return -ENODEV;
 
-		printf("Saving Environment to %s... ", drv->name);
+		// printf("Saving Environment to %s... ", drv->name);
 		ret = drv->save();
 		if (ret)
 			printf("Failed (%d)\n", ret);

include/configs/light-c910.h

@@ -30,10 +30,15 @@
 #define CONFIG_SYS_BOOTM_LEN        SZ_64M
 #define CONFIG_SYS_CACHELINE_SIZE   64
 
+#define CONFIG_CMD_READ 1
+
 #define SRAM_BASE_ADDR	 0xffe0000000
 #define PLIC_BASE_ADDR   0xffd8000000
 #define PMP_BASE_ADDR    0xffdc020000
 
+#define MINIMAL_DDR_DENSITY_MB (1*1024)
+#define MAXIMAL_DDR_DENSITY_MB (16*1024)
+#define UNIT_MB (1024*1024)
 
 /* Network Configuration */
 #define CONFIG_DW_ALTDESCRIPTOR
@@ -127,6 +132,8 @@
 #define ENV_STR_SERIAL 		"serial#=\0"
 #define ENV_KERNEL_KDUMP	"kdump_buf=0M\0"
 #endif
+/*public bootargs in mostly boards, make env 'set_booargs' shorter and clean */
+#define ENV_PUBLIC_BOOTARGS "pub_bootargs=rootfstype=ext4 rdinit=/sbin/init rootwait rw earlycon clk_ignore_unused\0"
 
 #define CONFIG_MISC_INIT_R
 
@@ -137,6 +144,7 @@
 	"pxefile_addr_r=0x00600000\0" \
 	"dtb_addr=0x03800000\0" \
 	"fdt_addr_r=0x03800000\0" \
+	"fdtoverlay_addr_r=0x03700000\0" \
 	"kernel_addr_r=0x00200000\0" \
 	"ramdisk_addr_r=0x06000000\0" \
 	"boot_conf_addr_r=0xc0000000\0" \
@@ -153,18 +161,21 @@
 	"kdump_buf=180M\0" \
 	"mmcbootpart=2\0" \
 	"default_mmcdev=1\0" \
+	"emmc_dev=0\0" \
+	"sdcard_dev=1\0" \
 	"mmc_select=if test -e mmc ${default_mmcdev}:${mmcbootpart} ${boot_conf_file}; then mmcdev=1; else mmcdev=0; fi;\0" \
 	"boot_conf_file=/extlinux/extlinux.conf\0" \
 	"uuid_rootfsA=80a5a8e9-c744-491a-93c1-4f4194fd690a\0" \
 	"uuid_swap=5ebcaaf0-e098-43b9-beef-1f8deedd135e\0" \
 	"partitions=name=table,size=2031KB;name=boot,size=500MiB,type=boot;name=swap,size=4096MiB,type=swap,uuid=${uuid_swap};name=root,size=-,type=linux,uuid=${uuid_rootfsA}\0" \
-	"gpt_partition=gpt write mmc ${mmcdev} $partitions\0" \
-	"load_aon=load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_aon_fpga.bin;cp.b $fwaddr $aon_ram_addr $filesize\0" \
+	"gpt_partition=gpt write mmc ${emmc_dev} $partitions\0" \
+	"sdcard_gpt_partition=gpt write mmc ${sdcard_dev} $partitions\0" \
+	"load_aon=load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_aon_fpga.bin;cp.b $fwaddr $aon_ram_addr $filesize;bootaon\0" \
 	"load_c906_audio=load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_c906_audio.bin;cp.b $fwaddr $audio_ram_addr $filesize\0" \
 	"load_str=load mmc ${mmcdev}:${mmcbootpart} $fwaddr str.bin;cp.b $fwaddr $str_ram_addr $filesize\0" \
 	"load_opensbi=load mmc ${mmcdev}:${mmcbootpart} $opensbi_addr fw_dynamic.bin\0" \
 	"bootcmd_load=run mmc_select; run load_aon; run load_c906_audio; run load_str; run load_opensbi\0" \
-	"bootcmd=run bootcmd_load; bootslave; sysboot mmc ${mmcdev}:${mmcbootpart} any $boot_conf_addr_r $boot_conf_file;\0" \
+	"bootcmd=run bootcmd_load; chk_hibernate; fixup_memory_region; bootslave; sysboot mmc ${mmcdev}:${mmcbootpart} any $boot_conf_addr_r $boot_conf_file;\0" \
 	"fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
 	"\0"
 

include/dm/uclass-id.h

@@ -115,7 +115,10 @@ enum uclass_id {
 	UCLASS_W1,		/* Dallas 1-Wire bus */
 	UCLASS_W1_EEPROM,	/* one-wire EEPROMs */
 	UCLASS_WDT,		/* Watchdog Timer driver */
-
+	UCLASS_FG,		/* Fuel gauge */
+	UCLASS_CHARGE_DISPLAY,	/* Charge display */
+	UCLASS_MCU,		/* MCU device */
+	UCLASS_PD,		/* PD device */
 	UCLASS_COUNT,
 	UCLASS_INVALID = -1,
 };

include/dt-bindings/pmic/light_pmic.h

@@ -0,0 +1,55 @@
+#ifndef __LIGHT_PMIC_H_
+#define __LIGHT_PMIC_H_
+
+/*for da9063*/
+#define DA9063_ID_BCORE1   0
+#define DA9063_ID_BCORE2   1
+#define DA9063_ID_BUCKPRO  2
+#define DA9063_ID_BUCKMEM  3
+#define DA9063_ID_BUCKIO   4
+#define DA9063_ID_BUCKPERI 5
+#define DA9063_ID_LDO1     6
+#define DA9063_ID_LDO2     7
+#define DA9063_ID_LDO3     8
+#define DA9063_ID_LDO4     9
+#define DA9063_ID_LDO5     10
+#define DA9063_ID_LDO9     11
+#define DA9063_ID_LDO10    12
+#define DA9063_ID_LDO11    13
+#define DA9063_ID_LDO6     14
+#define DA9063_ID_LDO7     15
+#define DA9063_ID_LDO8     16
+#define DA9063_ID_GPIO4    17
+#define DA9063_ID_GPIO7    18
+
+/*for da9121*/
+#define DA9121_ID_BUCK1  0
+
+
+/* for slg51000*/
+
+#define SLG51000_ID_LDO1   0
+#define SLG51000_ID_LDO2   1
+#define SLG51000_ID_LDO3   2
+#define SLG51000_ID_LDO4   3
+#define SLG51000_ID_LDO5   4
+#define SLG51000_ID_LDO6   5
+#define SLG51000_ID_LDO7   6
+
+
+/* for ricoh567*/
+#define RICOH567_ID_DC1     0
+#define RICOH567_ID_DC2     1
+#define RICOH567_ID_DC3     2
+#define RICOH567_ID_DC4     3
+#define RICOH567_ID_LDO1    4
+#define RICOH567_ID_LDO2    5
+#define RICOH567_ID_LDO3    6
+#define RICOH567_ID_LDO4    7
+#define RICOH567_ID_LDO5    8
+#define RICOH567_ID_LDORTC1 9
+#define RICOH567_ID_LDORTC2 10
+#define RICOH567_ID_GPIO3   11
+
+
+#endif

include/mcu/mcu-uclass.h

@@ -0,0 +1,23 @@
+#ifndef __MCU_H
+#define __MCU_H
+
+struct mcu_ops {
+	int (*shutdown)(struct udevice *dev);
+	int (*poweron)(struct udevice *dev);
+};
+
+/**
+ * mcu_shutdown() - power off supplies
+ *
+ * @return 0 on success or negative value of errno.
+ */
+int mcu_shutdown(void);
+
+/**
+ * mcu_poweron() - power on supplies
+ *
+ * @return 0 on success or negative value of errno.
+ */
+int mcu_poweron(void);
+
+#endif

include/power/charge_animation.h

@@ -0,0 +1,33 @@
+/*
+ * (C) Copyright 2017 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef _CHARGE_ANIMATION_H_
+#define _CHARGE_ANIMATION_H_
+
+struct regulator_mem {
+	struct udevice *dev;
+	bool enable;
+};
+
+struct charge_animation_pdata {
+	int android_charge;	/* android charge, 1: enable, 0: disable */
+	int uboot_charge;	/* u-boot charge, 1: enable, 0: disable */
+
+	int auto_exit_charge;	/* energy enough auto exit uboot charging*/
+	int exit_charge_voltage;/* lowest voltage allowed to exit charging */
+	int exit_charge_level;  /* lowest soc level allowed to exit charging */
+	int low_power_voltage;	/* below this voltage, force system into charge mode anyway */
+	int screen_on_voltage;	/* lowest voltage allowed to turn on screen */
+
+	int system_suspend;	/* enter ATF system suspend, 1: enable, 0: disable */
+	int auto_wakeup_interval;/* timeout seconds to auto wakeup system */
+	int auto_wakeup_screen_invert;/* auto wakeup system, 1: enable, 0: disable */
+	int auto_off_screen_interval;/* timeout seconds to auto turn off screen */
+
+	struct regulator_mem *regulators_mem; /* assigned regulator suspend state */
+};
+
+#endif

include/power/charge_display.h

@@ -0,0 +1,17 @@
+/*
+ * (C) Copyright 2017 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef _CHARGE_DISPLAY_H_
+#define _CHARGE_DISPLAY_H_
+
+struct dm_charge_display_ops {
+	int (*show)(struct udevice *dev);
+};
+
+int charge_display(void);
+int charge_display_show(struct udevice *dev);
+
+#endif

include/power/fuel_gauge.h

@@ -0,0 +1,46 @@
+/*
+ * (C) Copyright 2017 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef _FUEL_GAUGE_H_
+#define _FUEL_GAUGE_H_
+
+#ifndef BIT
+#define BIT(nr)				(1 << (nr))
+#endif
+
+/* Capability */
+#define FG_CAP_FUEL_GAUGE	BIT(0)
+#define FG_CAP_CHARGER		BIT(1)
+
+struct dm_fuel_gauge_ops {
+	int (*capability)(struct udevice *dev);
+	int (*bat_is_exist)(struct udevice *dev);
+	int (*get_soc)(struct udevice *dev);
+	int (*get_voltage)(struct udevice *dev);
+	int (*get_current)(struct udevice *dev);
+	int (*get_temperature)(struct udevice *dev, int *temp);
+	bool (*get_chrg_online)(struct udevice *dev);
+	int (*set_charger_voltage)(struct udevice *dev, int uV);
+	int (*set_charger_enable)(struct udevice *dev);
+	int (*set_charger_disable)(struct udevice *dev);
+	int (*set_iprechg_current)(struct udevice *dev, int iprechrg_uA);
+	int (*set_charger_current)(struct udevice *dev, int ichrg_uA);
+};
+
+int fuel_gauge_capability(struct udevice *dev);
+int fuel_gauge_bat_is_exist(struct udevice *dev);
+int fuel_gauge_update_get_soc(struct udevice *dev);
+int fuel_gauge_get_voltage(struct udevice *dev);
+int fuel_gauge_get_current(struct udevice *dev);
+bool fuel_gauge_get_chrg_online(struct udevice *dev);
+int fuel_gauge_get_temperature(struct udevice *dev, int *temp);
+int charger_set_charger_voltage(struct udevice *dev, int uV);
+int charger_set_iprechg_current(struct udevice *dev, int iprechrg_uA);
+int charger_set_current(struct udevice *dev, int ichrg_uA);
+int charger_set_enable(struct udevice *dev);
+int charger_set_disable(struct udevice *dev);
+
+#endif

include/power/power_delivery/pd.h

@@ -0,0 +1,498 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright 2015-2017 Google, Inc
+ */
+
+#ifndef __LINUX_USB_PD_H
+#define __LINUX_USB_PD_H
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include "typec.h"
+
+/* USB PD Messages */
+enum pd_ctrl_msg_type {
+	/* 0 Reserved */
+	PD_CTRL_GOOD_CRC = 1,
+	PD_CTRL_GOTO_MIN = 2,
+	PD_CTRL_ACCEPT = 3,
+	PD_CTRL_REJECT = 4,
+	PD_CTRL_PING = 5,
+	PD_CTRL_PS_RDY = 6,
+	PD_CTRL_GET_SOURCE_CAP = 7,
+	PD_CTRL_GET_SINK_CAP = 8,
+	PD_CTRL_DR_SWAP = 9,
+	PD_CTRL_PR_SWAP = 10,
+	PD_CTRL_VCONN_SWAP = 11,
+	PD_CTRL_WAIT = 12,
+	PD_CTRL_SOFT_RESET = 13,
+	/* 14-15 Reserved */
+	PD_CTRL_NOT_SUPP = 16,
+	PD_CTRL_GET_SOURCE_CAP_EXT = 17,
+	PD_CTRL_GET_STATUS = 18,
+	PD_CTRL_FR_SWAP = 19,
+	PD_CTRL_GET_PPS_STATUS = 20,
+	PD_CTRL_GET_COUNTRY_CODES = 21,
+	/* 22-31 Reserved */
+};
+
+enum pd_data_msg_type {
+	/* 0 Reserved */
+	PD_DATA_SOURCE_CAP = 1,
+	PD_DATA_REQUEST = 2,
+	PD_DATA_BIST = 3,
+	PD_DATA_SINK_CAP = 4,
+	PD_DATA_BATT_STATUS = 5,
+	PD_DATA_ALERT = 6,
+	PD_DATA_GET_COUNTRY_INFO = 7,
+	PD_DATA_ENTER_USB = 8,
+	/* 9-14 Reserved */
+	PD_DATA_VENDOR_DEF = 15,
+	/* 16-31 Reserved */
+};
+
+enum pd_ext_msg_type {
+	/* 0 Reserved */
+	PD_EXT_SOURCE_CAP_EXT = 1,
+	PD_EXT_STATUS = 2,
+	PD_EXT_GET_BATT_CAP = 3,
+	PD_EXT_GET_BATT_STATUS = 4,
+	PD_EXT_BATT_CAP = 5,
+	PD_EXT_GET_MANUFACTURER_INFO = 6,
+	PD_EXT_MANUFACTURER_INFO = 7,
+	PD_EXT_SECURITY_REQUEST = 8,
+	PD_EXT_SECURITY_RESPONSE = 9,
+	PD_EXT_FW_UPDATE_REQUEST = 10,
+	PD_EXT_FW_UPDATE_RESPONSE = 11,
+	PD_EXT_PPS_STATUS = 12,
+	PD_EXT_COUNTRY_INFO = 13,
+	PD_EXT_COUNTRY_CODES = 14,
+	/* 15-31 Reserved */
+};
+
+#define PD_REV10	0x0
+#define PD_REV20	0x1
+#define PD_REV30	0x2
+#define PD_MAX_REV	PD_REV30
+
+#define PD_HEADER_EXT_HDR	BIT(15)
+#define PD_HEADER_CNT_SHIFT	12
+#define PD_HEADER_CNT_MASK	0x7
+#define PD_HEADER_ID_SHIFT	9
+#define PD_HEADER_ID_MASK	0x7
+#define PD_HEADER_PWR_ROLE	BIT(8)
+#define PD_HEADER_REV_SHIFT	6
+#define PD_HEADER_REV_MASK	0x3
+#define PD_HEADER_DATA_ROLE	BIT(5)
+#define PD_HEADER_TYPE_SHIFT	0
+#define PD_HEADER_TYPE_MASK	0x1f
+
+#define PD_HEADER(type, pwr, data, rev, id, cnt, ext_hdr)		\
+	((((type) & PD_HEADER_TYPE_MASK) << PD_HEADER_TYPE_SHIFT) |	\
+	 ((pwr) == TYPEC_SOURCE ? PD_HEADER_PWR_ROLE : 0) |		\
+	 ((data) == TYPEC_HOST ? PD_HEADER_DATA_ROLE : 0) |		\
+	 (rev << PD_HEADER_REV_SHIFT) |					\
+	 (((id) & PD_HEADER_ID_MASK) << PD_HEADER_ID_SHIFT) |		\
+	 (((cnt) & PD_HEADER_CNT_MASK) << PD_HEADER_CNT_SHIFT) |	\
+	 ((ext_hdr) ? PD_HEADER_EXT_HDR : 0))
+
+#define PD_HEADER_LE(type, pwr, data, rev, id, cnt) \
+	cpu_to_le16(PD_HEADER((type), (pwr), (data), (rev), (id), (cnt), (0)))
+
+static inline unsigned int pd_header_cnt(u16 header)
+{
+	return (header >> PD_HEADER_CNT_SHIFT) & PD_HEADER_CNT_MASK;
+}
+
+static inline unsigned int pd_header_cnt_le(__le16 header)
+{
+	return pd_header_cnt(le16_to_cpu(header));
+}
+
+static inline unsigned int pd_header_type(u16 header)
+{
+	return (header >> PD_HEADER_TYPE_SHIFT) & PD_HEADER_TYPE_MASK;
+}
+
+static inline unsigned int pd_header_type_le(__le16 header)
+{
+	return pd_header_type(le16_to_cpu(header));
+}
+
+static inline unsigned int pd_header_msgid(u16 header)
+{
+	return (header >> PD_HEADER_ID_SHIFT) & PD_HEADER_ID_MASK;
+}
+
+static inline unsigned int pd_header_msgid_le(__le16 header)
+{
+	return pd_header_msgid(le16_to_cpu(header));
+}
+
+static inline unsigned int pd_header_rev(u16 header)
+{
+	return (header >> PD_HEADER_REV_SHIFT) & PD_HEADER_REV_MASK;
+}
+
+static inline unsigned int pd_header_rev_le(__le16 header)
+{
+	return pd_header_rev(le16_to_cpu(header));
+}
+
+#define PD_EXT_HDR_CHUNKED		BIT(15)
+#define PD_EXT_HDR_CHUNK_NUM_SHIFT	11
+#define PD_EXT_HDR_CHUNK_NUM_MASK	0xf
+#define PD_EXT_HDR_REQ_CHUNK		BIT(10)
+#define PD_EXT_HDR_DATA_SIZE_SHIFT	0
+#define PD_EXT_HDR_DATA_SIZE_MASK	0x1ff
+
+#define PD_EXT_HDR(data_size, req_chunk, chunk_num, chunked)				\
+	((((data_size) & PD_EXT_HDR_DATA_SIZE_MASK) << PD_EXT_HDR_DATA_SIZE_SHIFT) |	\
+	 ((req_chunk) ? PD_EXT_HDR_REQ_CHUNK : 0) |					\
+	 (((chunk_num) & PD_EXT_HDR_CHUNK_NUM_MASK) << PD_EXT_HDR_CHUNK_NUM_SHIFT) |	\
+	 ((chunked) ? PD_EXT_HDR_CHUNKED : 0))
+
+#define PD_EXT_HDR_LE(data_size, req_chunk, chunk_num, chunked) \
+	cpu_to_le16(PD_EXT_HDR((data_size), (req_chunk), (chunk_num), (chunked)))
+
+static inline unsigned int pd_ext_header_chunk_num(u16 ext_header)
+{
+	return (ext_header >> PD_EXT_HDR_CHUNK_NUM_SHIFT) &
+		PD_EXT_HDR_CHUNK_NUM_MASK;
+}
+
+static inline unsigned int pd_ext_header_data_size(u16 ext_header)
+{
+	return (ext_header >> PD_EXT_HDR_DATA_SIZE_SHIFT) &
+		PD_EXT_HDR_DATA_SIZE_MASK;
+}
+
+static inline unsigned int pd_ext_header_data_size_le(__le16 ext_header)
+{
+	return pd_ext_header_data_size(le16_to_cpu(ext_header));
+}
+
+#define PD_MAX_PAYLOAD		7
+#define PD_EXT_MAX_CHUNK_DATA	26
+
+/**
+  * struct pd_chunked_ext_message_data - PD chunked extended message data as
+  *					 seen on wire
+  * @header:    PD extended message header
+  * @data:      PD extended message data
+  */
+struct pd_chunked_ext_message_data {
+	__le16 header;
+	u8 data[PD_EXT_MAX_CHUNK_DATA];
+} __packed;
+
+/**
+  * struct pd_message - PD message as seen on wire
+  * @header:    PD message header
+  * @payload:   PD message payload
+  * @ext_msg:   PD message chunked extended message data
+  */
+struct pd_message {
+	__le16 header;
+	union {
+		__le32 payload[PD_MAX_PAYLOAD];
+		struct pd_chunked_ext_message_data ext_msg;
+	};
+} __packed;
+
+/* PDO: Power Data Object */
+#define PDO_MAX_OBJECTS		7
+
+enum pd_pdo_type {
+	PDO_TYPE_FIXED = 0,
+	PDO_TYPE_BATT = 1,
+	PDO_TYPE_VAR = 2,
+	PDO_TYPE_APDO = 3,
+};
+
+#define PDO_TYPE_SHIFT		30
+#define PDO_TYPE_MASK		0x3
+
+#define PDO_TYPE(t)	((t) << PDO_TYPE_SHIFT)
+
+#define PDO_VOLT_MASK		0x3ff
+#define PDO_CURR_MASK		0x3ff
+#define PDO_PWR_MASK		0x3ff
+
+#define PDO_FIXED_DUAL_ROLE		BIT(29)	/* Power role swap supported */
+#define PDO_FIXED_SUSPEND		BIT(28) /* USB Suspend supported (Source) */
+#define PDO_FIXED_HIGHER_CAP		BIT(28) /* Requires more than vSafe5V (Sink) */
+#define PDO_FIXED_EXTPOWER		BIT(27) /* Externally powered */
+#define PDO_FIXED_USB_COMM		BIT(26) /* USB communications capable */
+#define PDO_FIXED_DATA_SWAP		BIT(25) /* Data role swap supported */
+#define PDO_FIXED_UNCHUNK_EXT		BIT(24) /* Unchunked Extended Message supported (Source) */
+#define PDO_FIXED_FRS_CURR_MASK		(BIT(24) | BIT(23)) /* FR_Swap Current (Sink) */
+#define PDO_FIXED_FRS_CURR_SHIFT	23
+#define PDO_FIXED_VOLT_SHIFT		10	/* 50mV units */
+#define PDO_FIXED_CURR_SHIFT		0	/* 10mA units */
+
+#define PDO_FIXED_VOLT(mv)	((((mv) / 50) & PDO_VOLT_MASK) << PDO_FIXED_VOLT_SHIFT)
+#define PDO_FIXED_CURR(ma)	((((ma) / 10) & PDO_CURR_MASK) << PDO_FIXED_CURR_SHIFT)
+
+#define PDO_FIXED(mv, ma, flags)			\
+	(PDO_TYPE(PDO_TYPE_FIXED) | (flags) |		\
+	 PDO_FIXED_VOLT(mv) | PDO_FIXED_CURR(ma))
+
+#define VSAFE5V 5000 /* mv units */
+
+#define PDO_BATT_MAX_VOLT_SHIFT	20	/* 50mV units */
+#define PDO_BATT_MIN_VOLT_SHIFT	10	/* 50mV units */
+#define PDO_BATT_MAX_PWR_SHIFT	0	/* 250mW units */
+
+#define PDO_BATT_MIN_VOLT(mv) ((((mv) / 50) & PDO_VOLT_MASK) << PDO_BATT_MIN_VOLT_SHIFT)
+#define PDO_BATT_MAX_VOLT(mv) ((((mv) / 50) & PDO_VOLT_MASK) << PDO_BATT_MAX_VOLT_SHIFT)
+#define PDO_BATT_MAX_POWER(mw) ((((mw) / 250) & PDO_PWR_MASK) << PDO_BATT_MAX_PWR_SHIFT)
+
+#define PDO_BATT(min_mv, max_mv, max_mw)			\
+	(PDO_TYPE(PDO_TYPE_BATT) | PDO_BATT_MIN_VOLT(min_mv) |	\
+	 PDO_BATT_MAX_VOLT(max_mv) | PDO_BATT_MAX_POWER(max_mw))
+
+#define PDO_VAR_MAX_VOLT_SHIFT	20	/* 50mV units */
+#define PDO_VAR_MIN_VOLT_SHIFT	10	/* 50mV units */
+#define PDO_VAR_MAX_CURR_SHIFT	0	/* 10mA units */
+
+#define PDO_VAR_MIN_VOLT(mv) ((((mv) / 50) & PDO_VOLT_MASK) << PDO_VAR_MIN_VOLT_SHIFT)
+#define PDO_VAR_MAX_VOLT(mv) ((((mv) / 50) & PDO_VOLT_MASK) << PDO_VAR_MAX_VOLT_SHIFT)
+#define PDO_VAR_MAX_CURR(ma) ((((ma) / 10) & PDO_CURR_MASK) << PDO_VAR_MAX_CURR_SHIFT)
+
+#define PDO_VAR(min_mv, max_mv, max_ma)				\
+	(PDO_TYPE(PDO_TYPE_VAR) | PDO_VAR_MIN_VOLT(min_mv) |	\
+	 PDO_VAR_MAX_VOLT(max_mv) | PDO_VAR_MAX_CURR(max_ma))
+
+enum pd_apdo_type {
+	APDO_TYPE_PPS = 0,
+};
+
+#define PDO_APDO_TYPE_SHIFT	28	/* Only valid value currently is 0x0 - PPS */
+#define PDO_APDO_TYPE_MASK	0x3
+
+#define PDO_APDO_TYPE(t)	((t) << PDO_APDO_TYPE_SHIFT)
+
+#define PDO_PPS_APDO_MAX_VOLT_SHIFT	17	/* 100mV units */
+#define PDO_PPS_APDO_MIN_VOLT_SHIFT	8	/* 100mV units */
+#define PDO_PPS_APDO_MAX_CURR_SHIFT	0	/* 50mA units */
+
+#define PDO_PPS_APDO_VOLT_MASK	0xff
+#define PDO_PPS_APDO_CURR_MASK	0x7f
+
+#define PDO_PPS_APDO_MIN_VOLT(mv)	\
+	((((mv) / 100) & PDO_PPS_APDO_VOLT_MASK) << PDO_PPS_APDO_MIN_VOLT_SHIFT)
+#define PDO_PPS_APDO_MAX_VOLT(mv)	\
+	((((mv) / 100) & PDO_PPS_APDO_VOLT_MASK) << PDO_PPS_APDO_MAX_VOLT_SHIFT)
+#define PDO_PPS_APDO_MAX_CURR(ma)	\
+	((((ma) / 50) & PDO_PPS_APDO_CURR_MASK) << PDO_PPS_APDO_MAX_CURR_SHIFT)
+
+#define PDO_PPS_APDO(min_mv, max_mv, max_ma)				\
+	(PDO_TYPE(PDO_TYPE_APDO) | PDO_APDO_TYPE(APDO_TYPE_PPS) |	\
+	PDO_PPS_APDO_MIN_VOLT(min_mv) | PDO_PPS_APDO_MAX_VOLT(max_mv) |	\
+	PDO_PPS_APDO_MAX_CURR(max_ma))
+
+static inline enum pd_pdo_type pdo_type(u32 pdo)
+{
+	return (pdo >> PDO_TYPE_SHIFT) & PDO_TYPE_MASK;
+}
+
+static inline unsigned int pdo_fixed_voltage(u32 pdo)
+{
+	return ((pdo >> PDO_FIXED_VOLT_SHIFT) & PDO_VOLT_MASK) * 50;
+}
+
+static inline unsigned int pdo_min_voltage(u32 pdo)
+{
+	return ((pdo >> PDO_VAR_MIN_VOLT_SHIFT) & PDO_VOLT_MASK) * 50;
+}
+
+static inline unsigned int pdo_max_voltage(u32 pdo)
+{
+	return ((pdo >> PDO_VAR_MAX_VOLT_SHIFT) & PDO_VOLT_MASK) * 50;
+}
+
+static inline unsigned int pdo_max_current(u32 pdo)
+{
+	return ((pdo >> PDO_VAR_MAX_CURR_SHIFT) & PDO_CURR_MASK) * 10;
+}
+
+static inline unsigned int pdo_max_power(u32 pdo)
+{
+	return ((pdo >> PDO_BATT_MAX_PWR_SHIFT) & PDO_PWR_MASK) * 250;
+}
+
+static inline enum pd_apdo_type pdo_apdo_type(u32 pdo)
+{
+	return (pdo >> PDO_APDO_TYPE_SHIFT) & PDO_APDO_TYPE_MASK;
+}
+
+static inline unsigned int pdo_pps_apdo_min_voltage(u32 pdo)
+{
+	return ((pdo >> PDO_PPS_APDO_MIN_VOLT_SHIFT) &
+		PDO_PPS_APDO_VOLT_MASK) * 100;
+}
+
+static inline unsigned int pdo_pps_apdo_max_voltage(u32 pdo)
+{
+	return ((pdo >> PDO_PPS_APDO_MAX_VOLT_SHIFT) &
+		PDO_PPS_APDO_VOLT_MASK) * 100;
+}
+
+static inline unsigned int pdo_pps_apdo_max_current(u32 pdo)
+{
+	return ((pdo >> PDO_PPS_APDO_MAX_CURR_SHIFT) &
+		PDO_PPS_APDO_CURR_MASK) * 50;
+}
+
+/* RDO: Request Data Object */
+#define RDO_OBJ_POS_SHIFT	28
+#define RDO_OBJ_POS_MASK	0x7
+#define RDO_GIVE_BACK		BIT(27)	/* Supports reduced operating current */
+#define RDO_CAP_MISMATCH	BIT(26) /* Not satisfied by source caps */
+#define RDO_USB_COMM		BIT(25) /* USB communications capable */
+#define RDO_NO_SUSPEND		BIT(24) /* USB Suspend not supported */
+
+#define RDO_PWR_MASK			0x3ff
+#define RDO_CURR_MASK			0x3ff
+
+#define RDO_FIXED_OP_CURR_SHIFT		10
+#define RDO_FIXED_MAX_CURR_SHIFT	0
+
+#define RDO_OBJ(idx) (((idx) & RDO_OBJ_POS_MASK) << RDO_OBJ_POS_SHIFT)
+
+#define PDO_FIXED_OP_CURR(ma) ((((ma) / 10) & RDO_CURR_MASK) << RDO_FIXED_OP_CURR_SHIFT)
+#define PDO_FIXED_MAX_CURR(ma) ((((ma) / 10) & RDO_CURR_MASK) << RDO_FIXED_MAX_CURR_SHIFT)
+
+#define RDO_FIXED(idx, op_ma, max_ma, flags)			\
+	(RDO_OBJ(idx) | (flags) |				\
+	 PDO_FIXED_OP_CURR(op_ma) | PDO_FIXED_MAX_CURR(max_ma))
+
+#define RDO_BATT_OP_PWR_SHIFT		10	/* 250mW units */
+#define RDO_BATT_MAX_PWR_SHIFT		0	/* 250mW units */
+
+#define RDO_BATT_OP_PWR(mw) ((((mw) / 250) & RDO_PWR_MASK) << RDO_BATT_OP_PWR_SHIFT)
+#define RDO_BATT_MAX_PWR(mw) ((((mw) / 250) & RDO_PWR_MASK) << RDO_BATT_MAX_PWR_SHIFT)
+
+#define RDO_BATT(idx, op_mw, max_mw, flags)			\
+	(RDO_OBJ(idx) | (flags) |				\
+	 RDO_BATT_OP_PWR(op_mw) | RDO_BATT_MAX_PWR(max_mw))
+
+#define RDO_PROG_VOLT_MASK	0x7ff
+#define RDO_PROG_CURR_MASK	0x7f
+
+#define RDO_PROG_VOLT_SHIFT	9
+#define RDO_PROG_CURR_SHIFT	0
+
+#define RDO_PROG_VOLT_MV_STEP	20
+#define RDO_PROG_CURR_MA_STEP	50
+
+#define PDO_PROG_OUT_VOLT(mv)	\
+	((((mv) / RDO_PROG_VOLT_MV_STEP) & RDO_PROG_VOLT_MASK) << RDO_PROG_VOLT_SHIFT)
+#define PDO_PROG_OP_CURR(ma)	\
+	((((ma) / RDO_PROG_CURR_MA_STEP) & RDO_PROG_CURR_MASK) << RDO_PROG_CURR_SHIFT)
+
+#define RDO_PROG(idx, out_mv, op_ma, flags)			\
+	(RDO_OBJ(idx) | (flags) |				\
+	 PDO_PROG_OUT_VOLT(out_mv) | PDO_PROG_OP_CURR(op_ma))
+
+static inline unsigned int rdo_index(u32 rdo)
+{
+	return (rdo >> RDO_OBJ_POS_SHIFT) & RDO_OBJ_POS_MASK;
+}
+
+static inline unsigned int rdo_op_current(u32 rdo)
+{
+	return ((rdo >> RDO_FIXED_OP_CURR_SHIFT) & RDO_CURR_MASK) * 10;
+}
+
+static inline unsigned int rdo_max_current(u32 rdo)
+{
+	return ((rdo >> RDO_FIXED_MAX_CURR_SHIFT) &
+		RDO_CURR_MASK) * 10;
+}
+
+static inline unsigned int rdo_op_power(u32 rdo)
+{
+	return ((rdo >> RDO_BATT_OP_PWR_SHIFT) & RDO_PWR_MASK) * 250;
+}
+
+static inline unsigned int rdo_max_power(u32 rdo)
+{
+	return ((rdo >> RDO_BATT_MAX_PWR_SHIFT) & RDO_PWR_MASK) * 250;
+}
+
+/* Enter_USB Data Object */
+#define EUDO_USB_MODE_MASK		GENMASK(30, 28)
+#define EUDO_USB_MODE_SHIFT		28
+#define   EUDO_USB_MODE_USB2		0
+#define   EUDO_USB_MODE_USB3		1
+#define   EUDO_USB_MODE_USB4		2
+#define EUDO_USB4_DRD			BIT(26)
+#define EUDO_USB3_DRD			BIT(25)
+#define EUDO_CABLE_SPEED_MASK		GENMASK(23, 21)
+#define EUDO_CABLE_SPEED_SHIFT		21
+#define   EUDO_CABLE_SPEED_USB2		0
+#define   EUDO_CABLE_SPEED_USB3_GEN1	1
+#define   EUDO_CABLE_SPEED_USB4_GEN2	2
+#define   EUDO_CABLE_SPEED_USB4_GEN3	3
+#define EUDO_CABLE_TYPE_MASK		GENMASK(20, 19)
+#define EUDO_CABLE_TYPE_SHIFT		19
+#define   EUDO_CABLE_TYPE_PASSIVE	0
+#define   EUDO_CABLE_TYPE_RE_TIMER	1
+#define   EUDO_CABLE_TYPE_RE_DRIVER	2
+#define   EUDO_CABLE_TYPE_OPTICAL	3
+#define EUDO_CABLE_CURRENT_MASK		GENMASK(18, 17)
+#define EUDO_CABLE_CURRENT_SHIFT	17
+#define   EUDO_CABLE_CURRENT_NOTSUPP	0
+#define   EUDO_CABLE_CURRENT_3A		2
+#define   EUDO_CABLE_CURRENT_5A		3
+#define EUDO_PCIE_SUPPORT		BIT(16)
+#define EUDO_DP_SUPPORT			BIT(15)
+#define EUDO_TBT_SUPPORT		BIT(14)
+#define EUDO_HOST_PRESENT		BIT(13)
+
+/* USB PD timers and counters */
+#define PD_T_NO_RESPONSE	5000	/* 4.5 - 5.5 seconds */
+#define PD_T_DB_DETECT		10000	/* 10 - 15 seconds */
+#define PD_T_SEND_SOURCE_CAP	150	/* 100 - 200 ms */
+#define PD_T_SENDER_RESPONSE	60	/* 24 - 30 ms, relaxed */
+#define PD_T_RECEIVER_RESPONSE	15	/* 15ms max */
+#define PD_T_SOURCE_ACTIVITY	45
+#define PD_T_SINK_ACTIVITY	135
+#define PD_T_SINK_WAIT_CAP	310	/* 310 - 620 ms */
+#define PD_T_PS_TRANSITION	500
+#define PD_T_SRC_TRANSITION	35
+#define PD_T_DRP_SNK		40
+#define PD_T_DRP_SRC		30
+#define PD_T_PS_SOURCE_OFF	920
+#define PD_T_PS_SOURCE_ON	480
+#define PD_T_PS_SOURCE_ON_PRS	450	/* 390 - 480ms */
+#define PD_T_PS_HARD_RESET	30
+#define PD_T_SRC_RECOVER	760
+#define PD_T_SRC_RECOVER_MAX	1000
+#define PD_T_SRC_TURN_ON	275
+#define PD_T_SAFE_0V		650
+#define PD_T_VCONN_SOURCE_ON	100
+#define PD_T_SINK_REQUEST	100	/* 100 ms minimum */
+#define PD_T_ERROR_RECOVERY	100	/* minimum 25 is insufficient */
+#define PD_T_SRCSWAPSTDBY	625	/* Maximum of 650ms */
+#define PD_T_NEWSRC		250	/* Maximum of 275ms */
+#define PD_T_SWAP_SRC_START	20	/* Minimum of 20ms */
+#define PD_T_BIST_CONT_MODE	50	/* 30 - 60 ms */
+#define PD_T_SINK_TX		16	/* 16 - 20 ms */
+#define PD_T_CHUNK_NOT_SUPP	42	/* 40 - 50 ms */
+
+#define PD_T_DRP_TRY		100	/* 75 - 150 ms */
+#define PD_T_DRP_TRYWAIT	600	/* 400 - 800 ms */
+
+#define PD_T_CC_DEBOUNCE	200	/* 100 - 200 ms */
+#define PD_T_PD_DEBOUNCE	20	/* 10 - 20 ms */
+#define PD_T_TRY_CC_DEBOUNCE	15	/* 10 - 20 ms */
+
+#define PD_N_CAPS_COUNT		(PD_T_NO_RESPONSE / PD_T_SEND_SOURCE_CAP)
+#define PD_N_HARD_RESET_COUNT	1
+
+#define PD_P_SNK_STDBY_MW	2500	/* 2500 mW */
+
+#endif /* __LINUX_USB_PD_H */

include/power/power_delivery/pd_vdo.h

@@ -0,0 +1,518 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright 2015-2017 Google, Inc
+ */
+
+#ifndef __LINUX_USB_PD_VDO_H
+#define __LINUX_USB_PD_VDO_H
+
+#include "pd.h"
+
+/*
+ * VDO : Vendor Defined Message Object
+ * VDM object is minimum of VDM header + 6 additional data objects.
+ */
+
+#define VDO_MAX_OBJECTS		6
+#define VDO_MAX_SIZE		(VDO_MAX_OBJECTS + 1)
+
+/*
+ * VDM header
+ * ----------
+ * <31:16>  :: SVID
+ * <15>     :: VDM type ( 1b == structured, 0b == unstructured )
+ * <14:13>  :: Structured VDM version
+ * <12:11>  :: reserved
+ * <10:8>   :: object position (1-7 valid ... used for enter/exit mode only)
+ * <7:6>    :: command type (SVDM only?)
+ * <5>      :: reserved (SVDM), command type (UVDM)
+ * <4:0>    :: command
+ */
+#define VDO(vid, type, ver, custom)			\
+	(((vid) << 16) |				\
+	 ((type) << 15) |				\
+	 ((ver) << 13) |				\
+	 ((custom) & 0x7FFF))
+
+#define VDO_SVDM_TYPE		(1 << 15)
+#define VDO_SVDM_VERS(x)	((x) << 13)
+#define VDO_OPOS(x)		((x) << 8)
+#define VDO_CMDT(x)		((x) << 6)
+#define VDO_SVDM_VERS_MASK	VDO_SVDM_VERS(0x3)
+#define VDO_OPOS_MASK		VDO_OPOS(0x7)
+#define VDO_CMDT_MASK		VDO_CMDT(0x3)
+
+#define CMDT_INIT		0
+#define CMDT_RSP_ACK		1
+#define CMDT_RSP_NAK		2
+#define CMDT_RSP_BUSY		3
+
+/* reserved for SVDM ... for Google UVDM */
+#define VDO_SRC_INITIATOR	(0 << 5)
+#define VDO_SRC_RESPONDER	(1 << 5)
+
+#define CMD_DISCOVER_IDENT	1
+#define CMD_DISCOVER_SVID	2
+#define CMD_DISCOVER_MODES	3
+#define CMD_ENTER_MODE		4
+#define CMD_EXIT_MODE		5
+#define CMD_ATTENTION		6
+
+#define VDO_CMD_VENDOR(x)    (((0x10 + (x)) & 0x1f))
+
+/* ChromeOS specific commands */
+#define VDO_CMD_VERSION		VDO_CMD_VENDOR(0)
+#define VDO_CMD_SEND_INFO	VDO_CMD_VENDOR(1)
+#define VDO_CMD_READ_INFO	VDO_CMD_VENDOR(2)
+#define VDO_CMD_REBOOT		VDO_CMD_VENDOR(5)
+#define VDO_CMD_FLASH_ERASE	VDO_CMD_VENDOR(6)
+#define VDO_CMD_FLASH_WRITE	VDO_CMD_VENDOR(7)
+#define VDO_CMD_ERASE_SIG	VDO_CMD_VENDOR(8)
+#define VDO_CMD_PING_ENABLE	VDO_CMD_VENDOR(10)
+#define VDO_CMD_CURRENT		VDO_CMD_VENDOR(11)
+#define VDO_CMD_FLIP		VDO_CMD_VENDOR(12)
+#define VDO_CMD_GET_LOG		VDO_CMD_VENDOR(13)
+#define VDO_CMD_CCD_EN		VDO_CMD_VENDOR(14)
+
+#define PD_VDO_VID(vdo)		((vdo) >> 16)
+#define PD_VDO_SVDM(vdo)	(((vdo) >> 15) & 1)
+#define PD_VDO_SVDM_VER(vdo)	(((vdo) >> 13) & 0x3)
+#define PD_VDO_OPOS(vdo)	(((vdo) >> 8) & 0x7)
+#define PD_VDO_CMD(vdo)		((vdo) & 0x1f)
+#define PD_VDO_CMDT(vdo)	(((vdo) >> 6) & 0x3)
+
+/*
+ * SVDM Identity request -> response
+ *
+ * Request is simply properly formatted SVDM header
+ *
+ * Response is 4 data objects:
+ * [0] :: SVDM header
+ * [1] :: Identitiy header
+ * [2] :: Cert Stat VDO
+ * [3] :: (Product | Cable) VDO
+ * [4] :: AMA VDO
+ *
+ */
+#define VDO_INDEX_HDR		0
+#define VDO_INDEX_IDH		1
+#define VDO_INDEX_CSTAT		2
+#define VDO_INDEX_CABLE		3
+#define VDO_INDEX_PRODUCT	3
+#define VDO_INDEX_AMA		4
+
+/*
+ * SVDM Identity Header
+ * --------------------
+ * <31>     :: data capable as a USB host
+ * <30>     :: data capable as a USB device
+ * <29:27>  :: product type (UFP / Cable / VPD)
+ * <26>     :: modal operation supported (1b == yes)
+ * <25:23>  :: product type (DFP) (SVDM version 2.0+ only; set to zero in version 1.0)
+ * <22:21>  :: connector type (SVDM version 2.0+ only; set to zero in version 1.0)
+ * <20:16>  :: Reserved, Shall be set to zero
+ * <15:0>   :: USB-IF assigned VID for this cable vendor
+ */
+
+/* PD Rev2.0 definition */
+#define IDH_PTYPE_UNDEF		0
+
+/* SOP Product Type (UFP) */
+#define IDH_PTYPE_NOT_UFP	0
+#define IDH_PTYPE_HUB		1
+#define IDH_PTYPE_PERIPH	2
+#define IDH_PTYPE_PSD		3
+#define IDH_PTYPE_AMA		5
+
+/* SOP' Product Type (Cable Plug / VPD) */
+#define IDH_PTYPE_NOT_CABLE	0
+#define IDH_PTYPE_PCABLE	3
+#define IDH_PTYPE_ACABLE	4
+#define IDH_PTYPE_VPD		6
+
+/* SOP Product Type (DFP) */
+#define IDH_PTYPE_NOT_DFP	0
+#define IDH_PTYPE_DFP_HUB	1
+#define IDH_PTYPE_DFP_HOST	2
+#define IDH_PTYPE_DFP_PB	3
+
+/* ID Header Mask */
+#define IDH_DFP_MASK		GENMASK(25, 23)
+#define IDH_CONN_MASK		GENMASK(22, 21)
+
+#define VDO_IDH(usbh, usbd, ufp_cable, is_modal, dfp, conn, vid)		\
+	((usbh) << 31 | (usbd) << 30 | ((ufp_cable) & 0x7) << 27		\
+	 | (is_modal) << 26 | ((dfp) & 0x7) << 23 | ((conn) & 0x3) << 21	\
+	 | ((vid) & 0xffff))
+
+#define PD_IDH_PTYPE(vdo)	(((vdo) >> 27) & 0x7)
+#define PD_IDH_VID(vdo)		((vdo) & 0xffff)
+#define PD_IDH_MODAL_SUPP(vdo)	((vdo) & (1 << 26))
+#define PD_IDH_DFP_PTYPE(vdo)	(((vdo) >> 23) & 0x7)
+#define PD_IDH_CONN_TYPE(vdo)	(((vdo) >> 21) & 0x3)
+
+/*
+ * Cert Stat VDO
+ * -------------
+ * <31:0>  : USB-IF assigned XID for this cable
+ */
+#define PD_CSTAT_XID(vdo)	(vdo)
+#define VDO_CERT(xid)		((xid) & 0xffffffff)
+
+/*
+ * Product VDO
+ * -----------
+ * <31:16> : USB Product ID
+ * <15:0>  : USB bcdDevice
+ */
+#define VDO_PRODUCT(pid, bcd)	(((pid) & 0xffff) << 16 | ((bcd) & 0xffff))
+#define PD_PRODUCT_PID(vdo)	(((vdo) >> 16) & 0xffff)
+
+/*
+ * UFP VDO (PD Revision 3.0+ only)
+ * --------
+ * <31:29> :: UFP VDO version
+ * <28>    :: Reserved
+ * <27:24> :: Device capability
+ * <23:22> :: Connector type (10b == receptacle, 11b == captive plug)
+ * <21:11> :: Reserved
+ * <10:8>  :: Vconn power (AMA only)
+ * <7>     :: Vconn required (AMA only, 0b == no, 1b == yes)
+ * <6>     :: Vbus required (AMA only, 0b == yes, 1b == no)
+ * <5:3>   :: Alternate modes
+ * <2:0>   :: USB highest speed
+ */
+#define PD_VDO_UFP_DEVCAP(vdo)	(((vdo) & GENMASK(27, 24)) >> 24)
+
+/* UFP VDO Version */
+#define UFP_VDO_VER1_2		2
+
+/* Device Capability */
+#define DEV_USB2_CAPABLE	BIT(0)
+#define DEV_USB2_BILLBOARD	BIT(1)
+#define DEV_USB3_CAPABLE	BIT(2)
+#define DEV_USB4_CAPABLE	BIT(3)
+
+/* Connector Type */
+#define UFP_RECEPTACLE		2
+#define UFP_CAPTIVE		3
+
+/* Vconn Power (AMA only, set to AMA_VCONN_NOT_REQ if Vconn is not required) */
+#define AMA_VCONN_PWR_1W	0
+#define AMA_VCONN_PWR_1W5	1
+#define AMA_VCONN_PWR_2W	2
+#define AMA_VCONN_PWR_3W	3
+#define AMA_VCONN_PWR_4W	4
+#define AMA_VCONN_PWR_5W	5
+#define AMA_VCONN_PWR_6W	6
+
+/* Vconn Required (AMA only) */
+#define AMA_VCONN_NOT_REQ	0
+#define AMA_VCONN_REQ		1
+
+/* Vbus Required (AMA only) */
+#define AMA_VBUS_REQ		0
+#define AMA_VBUS_NOT_REQ	1
+
+/* Alternate Modes */
+#define UFP_ALTMODE_NOT_SUPP	0
+#define UFP_ALTMODE_TBT3	BIT(0)
+#define UFP_ALTMODE_RECFG	BIT(1)
+#define UFP_ALTMODE_NO_RECFG	BIT(2)
+
+/* USB Highest Speed */
+#define UFP_USB2_ONLY		0
+#define UFP_USB32_GEN1		1
+#define UFP_USB32_4_GEN2	2
+#define UFP_USB4_GEN3		3
+
+#define VDO_UFP(ver, cap, conn, vcpwr, vcr, vbr, alt, spd)			\
+	(((ver) & 0x7) << 29 | ((cap) & 0xf) << 24 | ((conn) & 0x3) << 22	\
+	 | ((vcpwr) & 0x7) << 8 | (vcr) << 7 | (vbr) << 6 | ((alt) & 0x7) << 3	\
+	 | ((spd) & 0x7))
+
+/*
+ * DFP VDO (PD Revision 3.0+ only)
+ * --------
+ * <31:29> :: DFP VDO version
+ * <28:27> :: Reserved
+ * <26:24> :: Host capability
+ * <23:22> :: Connector type (10b == receptacle, 11b == captive plug)
+ * <21:5>  :: Reserved
+ * <4:0>   :: Port number
+ */
+#define PD_VDO_DFP_HOSTCAP(vdo)	(((vdo) & GENMASK(26, 24)) >> 24)
+
+#define DFP_VDO_VER1_1		1
+#define HOST_USB2_CAPABLE	BIT(0)
+#define HOST_USB3_CAPABLE	BIT(1)
+#define HOST_USB4_CAPABLE	BIT(2)
+#define DFP_RECEPTACLE		2
+#define DFP_CAPTIVE		3
+
+#define VDO_DFP(ver, cap, conn, pnum)						\
+	(((ver) & 0x7) << 29 | ((cap) & 0x7) << 24 | ((conn) & 0x3) << 22	\
+	 | ((pnum) & 0x1f))
+
+/*
+ * Cable VDO (for both Passive and Active Cable VDO in PD Rev2.0)
+ * ---------
+ * <31:28> :: Cable HW version
+ * <27:24> :: Cable FW version
+ * <23:20> :: Reserved, Shall be set to zero
+ * <19:18> :: type-C to Type-A/B/C/Captive (00b == A, 01 == B, 10 == C, 11 == Captive)
+ * <17>    :: Reserved, Shall be set to zero
+ * <16:13> :: cable latency (0001 == <10ns(~1m length))
+ * <12:11> :: cable termination type (11b == both ends active VCONN req)
+ * <10>    :: SSTX1 Directionality support (0b == fixed, 1b == cfgable)
+ * <9>     :: SSTX2 Directionality support
+ * <8>     :: SSRX1 Directionality support
+ * <7>     :: SSRX2 Directionality support
+ * <6:5>   :: Vbus current handling capability (01b == 3A, 10b == 5A)
+ * <4>     :: Vbus through cable (0b == no, 1b == yes)
+ * <3>     :: SOP" controller present? (0b == no, 1b == yes)
+ * <2:0>   :: USB SS Signaling support
+ *
+ * Passive Cable VDO (PD Rev3.0+)
+ * ---------
+ * <31:28> :: Cable HW version
+ * <27:24> :: Cable FW version
+ * <23:21> :: VDO version
+ * <20>    :: Reserved, Shall be set to zero
+ * <19:18> :: Type-C to Type-C/Captive (10b == C, 11b == Captive)
+ * <17>    :: Reserved, Shall be set to zero
+ * <16:13> :: cable latency (0001 == <10ns(~1m length))
+ * <12:11> :: cable termination type (10b == Vconn not req, 01b == Vconn req)
+ * <10:9>  :: Maximum Vbus voltage (00b == 20V, 01b == 30V, 10b == 40V, 11b == 50V)
+ * <8:7>   :: Reserved, Shall be set to zero
+ * <6:5>   :: Vbus current handling capability (01b == 3A, 10b == 5A)
+ * <4:3>   :: Reserved, Shall be set to zero
+ * <2:0>   :: USB highest speed
+ *
+ * Active Cable VDO 1 (PD Rev3.0+)
+ * ---------
+ * <31:28> :: Cable HW version
+ * <27:24> :: Cable FW version
+ * <23:21> :: VDO version
+ * <20>    :: Reserved, Shall be set to zero
+ * <19:18> :: Connector type (10b == C, 11b == Captive)
+ * <17>    :: Reserved, Shall be set to zero
+ * <16:13> :: cable latency (0001 == <10ns(~1m length))
+ * <12:11> :: cable termination type (10b == one end active, 11b == both ends active VCONN req)
+ * <10:9>  :: Maximum Vbus voltage (00b == 20V, 01b == 30V, 10b == 40V, 11b == 50V)
+ * <8>     :: SBU supported (0b == supported, 1b == not supported)
+ * <7>     :: SBU type (0b == passive, 1b == active)
+ * <6:5>   :: Vbus current handling capability (01b == 3A, 10b == 5A)
+ * <2:0>   :: USB highest speed
+ */
+/* Cable VDO Version */
+#define CABLE_VDO_VER1_0	0
+#define CABLE_VDO_VER1_3	3
+
+/* Connector Type (_ATYPE and _BTYPE are for PD Rev2.0 only) */
+#define CABLE_ATYPE		0
+#define CABLE_BTYPE		1
+#define CABLE_CTYPE		2
+#define CABLE_CAPTIVE		3
+
+/* Cable Latency */
+#define CABLE_LATENCY_1M	1
+#define CABLE_LATENCY_2M	2
+#define CABLE_LATENCY_3M	3
+#define CABLE_LATENCY_4M	4
+#define CABLE_LATENCY_5M	5
+#define CABLE_LATENCY_6M	6
+#define CABLE_LATENCY_7M	7
+#define CABLE_LATENCY_7M_PLUS	8
+
+/* Cable Termination Type */
+#define PCABLE_VCONN_NOT_REQ	0
+#define PCABLE_VCONN_REQ	1
+#define ACABLE_ONE_END		2
+#define ACABLE_BOTH_END		3
+
+/* Maximum Vbus Voltage */
+#define CABLE_MAX_VBUS_20V	0
+#define CABLE_MAX_VBUS_30V	1
+#define CABLE_MAX_VBUS_40V	2
+#define CABLE_MAX_VBUS_50V	3
+
+/* Active Cable SBU Supported/Type */
+#define ACABLE_SBU_SUPP		0
+#define ACABLE_SBU_NOT_SUPP	1
+#define ACABLE_SBU_PASSIVE	0
+#define ACABLE_SBU_ACTIVE	1
+
+/* Vbus Current Handling Capability */
+#define CABLE_CURR_DEF		0
+#define CABLE_CURR_3A		1
+#define CABLE_CURR_5A		2
+
+/* USB SuperSpeed Signaling Support (PD Rev2.0) */
+#define CABLE_USBSS_U2_ONLY	0
+#define CABLE_USBSS_U31_GEN1	1
+#define CABLE_USBSS_U31_GEN2	2
+
+/* USB Highest Speed */
+#define CABLE_USB2_ONLY		0
+#define CABLE_USB32_GEN1	1
+#define CABLE_USB32_4_GEN2	2
+#define CABLE_USB4_GEN3		3
+
+#define VDO_CABLE(hw, fw, cbl, lat, term, tx1d, tx2d, rx1d, rx2d, cur, vps, sopp, usbss) \
+	(((hw) & 0x7) << 28 | ((fw) & 0x7) << 24 | ((cbl) & 0x3) << 18		\
+	 | ((lat) & 0x7) << 13 | ((term) & 0x3) << 11 | (tx1d) << 10		\
+	 | (tx2d) << 9 | (rx1d) << 8 | (rx2d) << 7 | ((cur) & 0x3) << 5		\
+	 | (vps) << 4 | (sopp) << 3 | ((usbss) & 0x7))
+#define VDO_PCABLE(hw, fw, ver, conn, lat, term, vbm, cur, spd)			\
+	(((hw) & 0xf) << 28 | ((fw) & 0xf) << 24 | ((ver) & 0x7) << 21		\
+	 | ((conn) & 0x3) << 18 | ((lat) & 0xf) << 13 | ((term) & 0x3) << 11	\
+	 | ((vbm) & 0x3) << 9 | ((cur) & 0x3) << 5 | ((spd) & 0x7))
+#define VDO_ACABLE1(hw, fw, ver, conn, lat, term, vbm, sbu, sbut, cur, vbt, sopp, spd) \
+	(((hw) & 0xf) << 28 | ((fw) & 0xf) << 24 | ((ver) & 0x7) << 21		\
+	 | ((conn) & 0x3) << 18	| ((lat) & 0xf) << 13 | ((term) & 0x3) << 11	\
+	 | ((vbm) & 0x3) << 9 | (sbu) << 8 | (sbut) << 7 | ((cur) & 0x3) << 5	\
+	 | (vbt) << 4 | (sopp) << 3 | ((spd) & 0x7))
+
+#define VDO_TYPEC_CABLE_TYPE(vdo)	(((vdo) >> 18) & 0x3)
+
+/*
+ * Active Cable VDO 2
+ * ---------
+ * <31:24> :: Maximum operating temperature
+ * <23:16> :: Shutdown temperature
+ * <15>    :: Reserved, Shall be set to zero
+ * <14:12> :: U3/CLd power
+ * <11>    :: U3 to U0 transition mode (0b == direct, 1b == through U3S)
+ * <10>    :: Physical connection (0b == copper, 1b == optical)
+ * <9>     :: Active element (0b == redriver, 1b == retimer)
+ * <8>     :: USB4 supported (0b == yes, 1b == no)
+ * <7:6>   :: USB2 hub hops consumed
+ * <5>     :: USB2 supported (0b == yes, 1b == no)
+ * <4>     :: USB3.2 supported (0b == yes, 1b == no)
+ * <3>     :: USB lanes supported (0b == one lane, 1b == two lanes)
+ * <2>     :: Optically isolated active cable (0b == no, 1b == yes)
+ * <1>     :: Reserved, Shall be set to zero
+ * <0>     :: USB gen (0b == gen1, 1b == gen2+)
+ */
+
+/* U3/CLd Power*/
+#define ACAB2_U3_CLD_10MW_PLUS	0
+#define ACAB2_U3_CLD_10MW	1
+#define ACAB2_U3_CLD_5MW	2
+#define ACAB2_U3_CLD_1MW	3
+#define ACAB2_U3_CLD_500UW	4
+#define ACAB2_U3_CLD_200UW	5
+#define ACAB2_U3_CLD_50UW	6
+
+/* Other Active Cable VDO 2 Fields */
+#define ACAB2_U3U0_DIRECT	0
+#define ACAB2_U3U0_U3S		1
+#define ACAB2_PHY_COPPER	0
+#define ACAB2_PHY_OPTICAL	1
+#define ACAB2_REDRIVER		0
+#define ACAB2_RETIMER		1
+#define ACAB2_USB4_SUPP		0
+#define ACAB2_USB4_NOT_SUPP	1
+#define ACAB2_USB2_SUPP		0
+#define ACAB2_USB2_NOT_SUPP	1
+#define ACAB2_USB32_SUPP	0
+#define ACAB2_USB32_NOT_SUPP	1
+#define ACAB2_LANES_ONE		0
+#define ACAB2_LANES_TWO		1
+#define ACAB2_OPT_ISO_NO	0
+#define ACAB2_OPT_ISO_YES	1
+#define ACAB2_GEN_1		0
+#define ACAB2_GEN_2_PLUS	1
+
+#define VDO_ACABLE2(mtemp, stemp, u3p, trans, phy, ele, u4, hops, u2, u32, lane, iso, gen)	\
+	(((mtemp) & 0xff) << 24 | ((stemp) & 0xff) << 16 | ((u3p) & 0x7) << 12	\
+	 | (trans) << 11 | (phy) << 10 | (ele) << 9 | (u4) << 8			\
+	 | ((hops) & 0x3) << 6 | (u2) << 5 | (u32) << 4 | (lane) << 3		\
+	 | (iso) << 2 | (gen))
+
+/*
+ * AMA VDO (PD Rev2.0)
+ * ---------
+ * <31:28> :: Cable HW version
+ * <27:24> :: Cable FW version
+ * <23:12> :: Reserved, Shall be set to zero
+ * <11>    :: SSTX1 Directionality support (0b == fixed, 1b == cfgable)
+ * <10>    :: SSTX2 Directionality support
+ * <9>     :: SSRX1 Directionality support
+ * <8>     :: SSRX2 Directionality support
+ * <7:5>   :: Vconn power
+ * <4>     :: Vconn power required
+ * <3>     :: Vbus power required
+ * <2:0>   :: USB SS Signaling support
+ */
+#define VDO_AMA(hw, fw, tx1d, tx2d, rx1d, rx2d, vcpwr, vcr, vbr, usbss) \
+	(((hw) & 0x7) << 28 | ((fw) & 0x7) << 24			\
+	 | (tx1d) << 11 | (tx2d) << 10 | (rx1d) << 9 | (rx2d) << 8	\
+	 | ((vcpwr) & 0x7) << 5 | (vcr) << 4 | (vbr) << 3		\
+	 | ((usbss) & 0x7))
+
+#define PD_VDO_AMA_VCONN_REQ(vdo)	(((vdo) >> 4) & 1)
+#define PD_VDO_AMA_VBUS_REQ(vdo)	(((vdo) >> 3) & 1)
+
+#define AMA_USBSS_U2_ONLY	0
+#define AMA_USBSS_U31_GEN1	1
+#define AMA_USBSS_U31_GEN2	2
+#define AMA_USBSS_BBONLY	3
+
+/*
+ * VPD VDO
+ * ---------
+ * <31:28> :: HW version
+ * <27:24> :: FW version
+ * <23:21> :: VDO version
+ * <20:17> :: Reserved, Shall be set to zero
+ * <16:15> :: Maximum Vbus voltage (00b == 20V, 01b == 30V, 10b == 40V, 11b == 50V)
+ * <14>    :: Charge through current support (0b == 3A, 1b == 5A)
+ * <13>    :: Reserved, Shall be set to zero
+ * <12:7>  :: Vbus impedance
+ * <6:1>   :: Ground impedance
+ * <0>     :: Charge through support (0b == no, 1b == yes)
+ */
+#define VPD_VDO_VER1_0		0
+#define VPD_MAX_VBUS_20V	0
+#define VPD_MAX_VBUS_30V	1
+#define VPD_MAX_VBUS_40V	2
+#define VPD_MAX_VBUS_50V	3
+#define VPDCT_CURR_3A		0
+#define VPDCT_CURR_5A		1
+#define VPDCT_NOT_SUPP		0
+#define VPDCT_SUPP		1
+
+#define VDO_VPD(hw, fw, ver, vbm, curr, vbi, gi, ct)			\
+	(((hw) & 0xf) << 28 | ((fw) & 0xf) << 24 | ((ver) & 0x7) << 21	\
+	 | ((vbm) & 0x3) << 15 | (curr) << 14 | ((vbi) & 0x3f) << 7	\
+	 | ((gi) & 0x3f) << 1 | (ct))
+
+/*
+ * SVDM Discover SVIDs request -> response
+ *
+ * Request is properly formatted VDM Header with discover SVIDs command.
+ * Response is a set of SVIDs of all supported SVIDs with all zero's to
+ * mark the end of SVIDs.  If more than 12 SVIDs are supported command SHOULD be
+ * repeated.
+ */
+#define VDO_SVID(svid0, svid1)	(((svid0) & 0xffff) << 16 | ((svid1) & 0xffff))
+#define PD_VDO_SVID_SVID0(vdo)	((vdo) >> 16)
+#define PD_VDO_SVID_SVID1(vdo)	((vdo) & 0xffff)
+
+/* USB-IF SIDs */
+#define USB_SID_PD		0xff00 /* power delivery */
+#define USB_SID_DISPLAYPORT	0xff01
+#define USB_SID_MHL		0xff02	/* Mobile High-Definition Link */
+
+/* VDM command timeouts (in ms) */
+
+#define PD_T_VDM_UNSTRUCTURED	500
+#define PD_T_VDM_BUSY		100
+#define PD_T_VDM_WAIT_MODE_E	100
+#define PD_T_VDM_SNDR_RSP	30
+#define PD_T_VDM_E_MODE		25
+#define PD_T_VDM_RCVR_RSP	15
+
+#endif /* __LINUX_USB_PD_VDO_H */