configs/light_lpi4a_cluster_16g_defconfig: fix typo

16gb -> 16g

Signed-off-by: nekorouter <nekorouter@outlook.com>

.github/workflows/build.yml

@@ -12,10 +12,10 @@ on:
     - cron: "0 2 * * *"
 
 env:
-  xuantie_toolchain: https://occ-oss-prod.oss-cn-hangzhou.aliyuncs.com/resource//1698113812618
-  toolchain_file_name: Xuantie-900-gcc-linux-5.10.4-glibc-x86_64-V2.8.0-20231018.tar.gz
-  mainline_toolchain: https://github.com/riscv-collab/riscv-gnu-toolchain/releases/download/2023.10.18
-  mainline_toolchain_file_name: riscv64-glibc-ubuntu-22.04-gcc-nightly-2023.10.18-nightly.tar.gz
+  xuantie_toolchain: https://occ-oss-prod.oss-cn-hangzhou.aliyuncs.com/resource//1705395627867
+  toolchain_file_name: Xuantie-900-gcc-linux-5.10.4-glibc-x86_64-V2.8.1-20240115.tar.gz
+  mainline_toolchain: https://github.com/riscv-collab/riscv-gnu-toolchain/releases/download/2024.04.12
+  mainline_toolchain_file_name: riscv64-glibc-ubuntu-22.04-gcc-nightly-2024.04.12-nightly.tar.gz
   wget_alias: 'wget --retry-connrefused --waitretry=1 --read-timeout=20 --timeout=15 -t 0'
   ARCH: riscv
   CROSS_COMPILE: riscv64-unknown-linux-gnu-
@@ -46,7 +46,7 @@ jobs:
               if [[ ${{ matrix.name }} = "thead-gcc" ]]; then
                 ${wget_alias} ${xuantie_toolchain}/${toolchain_file_name}
                 tar -xvf ${toolchain_file_name} -C /opt
-                export PATH="/opt/Xuantie-900-gcc-linux-5.10.4-glibc-x86_64-V2.8.0/bin:$PATH"
+                export PATH="/opt/Xuantie-900-gcc-linux-5.10.4-glibc-x86_64-V2.8.1/bin:$PATH"
               else
                 ${wget_alias} ${mainline_toolchain}/${mainline_toolchain_file_name}
                 tar -xvf ${mainline_toolchain_file_name} -C /opt
@@ -71,6 +71,18 @@ jobs:
                 make -j$(nproc)
                 find . -name "u-boot-with-spl.bin" | xargs -I{} cp -av {} ${GITHUB_WORKSPACE}/output/u-boot-with-spl-lcon4a-16g.bin
                 make clean
+                make light_lpi4a_plastic_defconfig
+                make -j$(nproc)
+                find . -name "u-boot-with-spl.bin" | xargs -I{} cp -av {} ${GITHUB_WORKSPACE}/output/u-boot-with-spl-laptop4a.bin
+                make clean
+                make light_lpi4a_plastic_16g_defconfig
+                make -j$(nproc)
+                find . -name "u-boot-with-spl.bin" | xargs -I{} cp -av {} ${GITHUB_WORKSPACE}/output/u-boot-with-spl-laptop4a-16g.bin
+                make clean
+                make light_lpi4a_pocket_defconfig
+                make -j$(nproc)
+                find . -name "u-boot-with-spl.bin" | xargs -I{} cp -av {} ${GITHUB_WORKSPACE}/output/u-boot-with-spl-pocket4a.bin
+                make clean
                 make light_lpi4a_cluster_defconfig
                 make -j$(nproc)
                 find . -name "u-boot-with-spl.bin" | xargs -I{} cp -av {} ${GITHUB_WORKSPACE}/output/u-boot-with-spl-lc4a.bin
@@ -87,6 +99,10 @@ jobs:
                 make -j$(nproc)
                 find . -name "u-boot-with-spl.bin" | xargs -I{} cp -av {} ${GITHUB_WORKSPACE}/output/u-boot-with-spl-vala.bin
                 make clean
+                make light_milkv_meles_16g_defconfig
+                make -j$(nproc)
+                find . -name "u-boot-with-spl.bin" | xargs -I{} cp -av {} ${GITHUB_WORKSPACE}/output/u-boot-with-spl-meles-16g.bin
+                make clean
                 make light_milkv_meles_dualrank_defconfig
                 make -j$(nproc)
                 find . -name "u-boot-with-spl.bin" | xargs -I{} cp -av {} ${GITHUB_WORKSPACE}/output/u-boot-with-spl-meles.bin
@@ -95,35 +111,17 @@ jobs:
                 make -j$(nproc)
                 find . -name "u-boot-with-spl.bin" | xargs -I{} cp -av {} ${GITHUB_WORKSPACE}/output/u-boot-with-spl-meles-4g.bin
 
-                # mainline support
+                # 8g emmc support
+                sed -i 's/name=swap,size=4096MiB,type=swap/name=swap,size=2MiB,type=swap/' include/configs/light-c910.h
                 make clean
                 make light_lpi4a_defconfig
-                sed -i 's#thead/light-lpi4a.dtb#thead/th1520-lichee-pi-4a.dtb#' .config
                 make -j$(nproc)
-                find . -name "u-boot-with-spl.bin" | xargs -I{} cp -av {} ${GITHUB_WORKSPACE}/output/u-boot-with-spl-lpi4a-main.bin
-
-                make clean
-                make light_lpi4a_16g_defconfig
-                sed -i 's#thead/light-lpi4a-16gb.dtb#thead/th1520-lichee-pi-4a-16g.dtb#' .config
-                make -j$(nproc)
-                find . -name "u-boot-with-spl.bin" | xargs -I{} cp -av {} ${GITHUB_WORKSPACE}/output/u-boot-with-spl-lpi4a-16g-main.bin
-
-                make clean
-                make light_lpi4a_cluster_defconfig
-                sed -i 's#thead/light-lpi4a-cluster.dtb#thead/th1520-lichee-cluster-4a.dtb#' .config
-                make -j$(nproc)
-                find . -name "u-boot-with-spl.bin" | xargs -I{} cp -av {} ${GITHUB_WORKSPACE}/output/u-boot-with-spl-lc4a-main.bin
-
-                make clean
-                make light_lpi4a_cluster_16g_defconfig
-                sed -i 's#thead/light-lpi4a-cluster-16gb.dtb#thead/th1520-lichee-cluster-4a-16g.dtb#' .config
-                make -j$(nproc)
-                find . -name "u-boot-with-spl.bin" | xargs -I{} cp -av {} ${GITHUB_WORKSPACE}/output/u-boot-with-spl-lc4a-16g-main.bin
+                find . -name "u-boot-with-spl.bin" | xargs -I{} cp -av {} ${GITHUB_WORKSPACE}/output/u-boot-with-spl-lpi4a_8gemmc.bin
               popd
               tree ${GITHUB_WORKSPACE}/output
 
       - name: 'Upload Artifact'
-        uses: actions/upload-artifact@v3
+        uses: actions/upload-artifact@v4
         with:
           name: thead-u-uboot-${{ matrix.name }}
           path: output/*.bin

arch/riscv/cpu/c9xx/dram.c

@@ -14,9 +14,9 @@ DECLARE_GLOBAL_DATA_PTR;
 int dram_init(void)
 {
 #ifdef CONFIG_DDR_BOARD_CONFIG
-extern unsigned long get_ddr_density(void);
-	// update ram_size from board config info
-	gd->ram_size = get_ddr_density();
+	// already setup during ddr initial flow
+	gd->bd->bi_memsize = gd->ram_size;
+	gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
 	return 0;
 #else
 	return fdtdec_setup_mem_size_base();

arch/riscv/cpu/cpu.c

@@ -27,6 +27,15 @@ u32 hart_lottery __attribute__((section(".data"))) = 0;
 u32 available_harts_lock = 1;
 #endif
 
+void arch_setup_gd(struct global_data *gd_ptr)
+{
+	// sync specific info from spl
+	gd_ptr->ram_size = gd->ram_size;
+
+	// setup gd ptr
+	gd = gd_ptr;
+}
+
 static inline bool supports_extension(char ext)
 {
 #ifdef CONFIG_CPU

arch/riscv/cpu/start.S

@@ -104,12 +104,6 @@ call_board_init_f_0:
 	mv	a0, sp
 	jal	board_init_f_alloc_reserve
 
-	/*
-	 * Set global data pointer here for all harts, uninitialized at this
-	 * point.
-	 */
-	mv	gp, a0
-
 	/* setup stack */
 #ifdef CONFIG_SMP
 	/* tp: hart id */
@@ -127,16 +121,34 @@ call_board_init_f_0:
 	la	t0, hart_lottery
 	li	s2, 1
 	amoswap.w s2, t1, 0(t0)
-	bnez	s2, wait_for_gd_init
+	beqz	s2, call_board_init_f_1
+
+	/*
+	 * Set global data pointer here for secondary harts, uninitialized at this
+	 * point.
+	 */
+	mv	gp, a0
+
+	jal wait_for_gd_init
 #else
-	bnez	tp, secondary_hart_loop
+	beqz	tp, call_board_init_f_1
+
+	/*
+	 * Set global data pointer here for secondary harts, uninitialized at this
+	 * point.
+	 */
+	mv	gp, a0
+
+	jal secondary_hart_loop
 #endif
 
+call_board_init_f_1:
 #ifdef CONFIG_OF_PRIOR_STAGE
 	la	t0, prior_stage_fdt_address
 	SREG	s1, 0(t0)
 #endif
 
+	 /* Set global data pointer here for main hart */
 	jal	board_init_f_init_reserve
 
 	/* save the boot hart id to global_data */

arch/riscv/dts/light-a-val.dts

@@ -1,4 +1,7 @@
 /dts-v1/;
+
+#include <dt-bindings/pmic/light_pmic.h>
+
 / {
 	model = "T-HEAD c910 light";
 	compatible = "thead,c910_light";
@@ -359,6 +362,20 @@
 			};
 		};
 
+		usb: usb@ffe7040000 {
+			compatible = "snps,dwc3";
+			reg = <0xff 0xe7040000 0x0 0x10000>;
+			interrupts = <68>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			maximum-speed = "super-speed";
+			dr_mode = "host";
+			dma-mask = <0xf 0xffffffff>;
+			snps,usb3_lpm_capable;
+			snps,usb_sofitpsync;
+			status = "okay";
+		};
+
 		pwm: pwm@ffec01c000 {
 			compatible = "thead,pwm-light";
 			reg = <0xff 0xec01c000 0x0 0x4000>;
@@ -479,6 +496,429 @@
 			lcd-en-gpios    = <&pcal6408ahk_a 2 0>; /* active high */
 			lcd-bias-en-gpios = <&pcal6408ahk_a 4 0>;/* active high */
 		};
+
+		aon {
+		compatible = "thead,light-aon";
+		status = "okay";
+
+		wakeup-by-gpio-on;
+		wakeup-by-rtc-on;
+
+		pd: light-aon-pd {
+			compatible = "thead,light-aon-pd";
+			#power-domain-cells = <1>;
+		};
+
+		light-regu-reg {
+			compatible = "thead,light-dialog-pmic";
+			status = "okay";
+
+			soc_dvdd18_aon_reg: soc_dvdd18_aon {
+				regulator-name = "soc_dvdd18_aon";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_avdd33_usb3_reg: soc_avdd33_usb3 {
+				regulator-name = "soc_avdd33_usb3";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_dvdd08_aon_reg: soc_dvdd08_aon {
+				regulator-name = "soc_dvdd08_aon";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_apcpu_dvdd_dvddm_reg: soc_apcpu_dvdd_dvddm {
+				regulator-name = "soc_apcpu_dvdd_dvddm";
+				regulator-min-microvolt = <300000>;
+				regulator-max-microvolt = <1570000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_dvdd08_ddr_reg: soc_dvdd08_ddr {
+				regulator-name = "soc_dvdd08_ddr";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_vdd_ddr_1v8_reg: soc_vdd_ddr_1v8 {
+				regulator-name = "soc_vdd_ddr_1v8";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_vdd_ddr_1v1_reg: soc_vdd_ddr_1v1 {
+				regulator-name = "soc_vdd_ddr_1v1";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_vdd_ddr_0v6_reg: soc_vdd_ddr_0v6 {
+				regulator-name = "soc_vdd_ddr_0v6";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_dvdd18_ap_reg: soc_dvdd18_ap {
+				regulator-name = "soc_dvdd18_ap";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_dvdd08_ap_reg: soc_dvdd08_ap {
+				regulator-name = "soc_dvdd08_ap";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_avdd08_mipi_hdmi_reg: soc_avdd08_mipi_hdmi {
+				regulator-name = "soc_avdd08_mipi_hdmi";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_avdd18_mipi_hdmi_reg: soc_avdd18_mipi_hdmi {
+				regulator-name = "soc_avdd18_mipi_hdmi";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_dvdd33_emmc_reg: soc_dvdd33_emmc {
+				regulator-name = "soc_dvdd33_emmc";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_dvdd18_emmc_reg: soc_dvdd18_emmc {
+				regulator-name = "soc_vdd18_emmc";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+			soc_dovdd18_scan_reg: soc_dovdd18_scan {
+				regulator-name = "soc_dovdd18_scan";
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <3600000>;
+			};
+			soc_vext_2v8_reg: soc_vext_2v8 {
+				regulator-name = "soc_vext_2v8";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+			soc_dvdd12_scan_reg: soc_dvdd12_scan {
+				regulator-name = "soc_dvdd12_scan";
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <3600000>;
+			};
+			soc_avdd28_scan_en_reg: soc_avdd28_scan_en {
+				regulator-name = "soc_avdd28_scan_en";
+				regulator-min-microvolt = <2800000>;
+				regulator-max-microvolt = <2800000>;
+			};
+			soc_avdd28_rgb_reg: soc_avdd28_rgb {
+				regulator-name = "soc_avdd28_rgb";
+				regulator-min-microvolt = <2200000>;
+				regulator-max-microvolt = <3475000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+			soc_dovdd18_rgb_reg: soc_dovdd18_rgb {
+				regulator-name = "soc_dovdd18_rgb";
+				regulator-min-microvolt = <1200000>;
+				regulator-max-microvolt = <3600000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+			soc_dvdd12_rgb_reg: soc_dvdd12_rgb {
+				regulator-name = "soc_dvdd12_rgb";
+				regulator-min-microvolt = <400000>;
+				regulator-max-microvolt = <1675000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+			soc_avdd25_ir_reg: soc_avdd25_ir {
+				regulator-name = "soc_avdd25_ir";
+				regulator-min-microvolt = <2200000>;
+				regulator-max-microvolt = <3475000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+			soc_dovdd18_ir_reg: soc_dovdd18_ir {
+				regulator-name = "soc_dovdd18_ir";
+				regulator-min-microvolt = <1200000>;
+				regulator-max-microvolt = <3600000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+			soc_dvdd12_ir_reg: soc_dvdd12_ir {
+				regulator-name = "soc_dvdd12_ir";
+				regulator-min-microvolt = <400000>;
+				regulator-max-microvolt = <1675000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+	   };
+
+	    aon_pmic_config {
+			compatible = "thead,light-pmic-conf";
+			status = "okay";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			iic-config = <0 0 2>;
+			pmic_dev_0: pmic-dev@0 {
+			  pmic-name = "dialog,da9063,v1";
+			  pmic-addr = <0x5a 0x5b>;
+			  pmic_wdt_on;
+			  errio_gpio = <0 14 3>;
+			  status = "okay";
+			};
+
+			pmic_dev_1: pmic-dev@1 {
+			  pmic-name = "dialog,da9121,v1";
+			  pmic-addr = <0x68>;
+			  status = "okay";
+			};
+
+			pmic_dev_2: pmic-dev@2 {
+			  pmic-name = "dialog,slg51000,v1";
+			  pmic-addr = <0x75>;
+			  status = "okay";
+			};
+
+			regu_config_0 {
+                reg_info = <&soc_dvdd18_aon_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_0 DA9063_ID_LDO3>;
+				};
+			};
+
+			regu_config_1 {
+                reg_info = <&soc_avdd33_usb3_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_0 DA9063_ID_LDO9>;
+				};
+			};
+
+			regu_config_2 {
+                reg_info = <&soc_dvdd08_aon_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_0 DA9063_ID_LDO2>;
+				};
+			};
+
+			regu_config_3 {
+                reg_info = <&soc_apcpu_dvdd_dvddm_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_0 DA9063_ID_BCORE1>;
+					auto_on_info = <0 0 800000>;
+				};
+
+				regu_id@1 {
+                    pmic_dev = <&pmic_dev_0 DA9063_ID_BCORE2>;
+					auto_on_info = <1 0 800000>;
+				};
+
+				coupling_info@0 {
+					negative-min;
+                    info = <0 1 5 30>;
+				};
+			};
+
+			regu_config_4 {
+                reg_info = <&soc_dvdd08_ddr_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_0 DA9063_ID_BUCKPERI>;
+				};
+			};
+
+			regu_config_5 {
+                reg_info = <&soc_vdd_ddr_1v8_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_0 DA9063_ID_LDO4>;
+				};
+			};
+
+		    regu_config_6 {
+                reg_info = <&soc_vdd_ddr_1v1_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_0 DA9063_ID_BUCKMEM>;
+				};
+				regu_id@1 {
+                    pmic_dev = <&pmic_dev_0 DA9063_ID_BUCKIO>;
+				};
+
+			};
+
+			regu_config_7 {
+                reg_info = <&soc_vdd_ddr_0v6_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_0 DA9063_ID_BUCKPRO>;
+				};
+			};
+
+			regu_config_8 {
+                reg_info = <&soc_dvdd18_ap_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_0 DA9063_ID_LDO11>;
+				};
+			};
+
+            regu_config_9 {
+                reg_info = <&soc_avdd08_mipi_hdmi_reg>;
+				status = "okay";
+				regu_id@0 {
+					pmic_dev = <&pmic_dev_0 DA9063_ID_LDO1>;
+				};
+			};
+
+			regu_config_10 {
+                reg_info = <&soc_avdd18_mipi_hdmi_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_0 DA9063_ID_LDO5>;
+				};
+			};
+
+			regu_config_11 {
+                reg_info = <&soc_dvdd33_emmc_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_0 DA9063_ID_LDO10>;
+				};
+			};
+
+			regu_config_12 {
+                reg_info = <&soc_dovdd18_scan_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_0 DA9063_ID_LDO6>;
+					auto_on_info = <2 1 1800000>;
+					auto_off_info = <7 1>;
+				};
+			};
+
+			regu_config_13 {
+                reg_info = <&soc_vext_2v8_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_0 DA9063_ID_LDO7>;
+					auto_on_info = <3 1 2800000>;
+					auto_off_info = <8 1>;
+				};
+			};
+
+			regu_config_14 {
+                reg_info = <&soc_dvdd12_scan_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_0 DA9063_ID_LDO8>;
+					auto_on_info = <4 1 1200000>;
+					auto_off_info = <9 1>;
+				};
+			};
+
+			regu_config_15 {
+                reg_info = <&soc_avdd28_scan_en_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_0 DA9063_ID_GPIO4>;
+					auto_on_info = <5 1 2800000>;
+					auto_off_info = <6 1>;
+				};
+			};
+
+			regu_config_16 {
+                reg_info = <&soc_dvdd08_ap_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_1 DA9121_ID_BUCK1>;
+                    parent_pmic_dev = <&pmic_dev_0 2 0>;
+				};
+			};
+
+			regu_config_17 {
+                reg_info = <&soc_avdd28_rgb_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_2 SLG51000_ID_LDO1>;
+                    auto_on_info = <6 0 2800000>;
+					auto_off_info = <0 1>;
+				};
+			};
+
+			regu_config_18 {
+                reg_info = <&soc_avdd25_ir_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_2 SLG51000_ID_LDO2>;
+                    auto_on_info = <7 0 2500000>;
+					auto_off_info = <1 1>;
+				};
+			};
+
+			regu_config_19 {
+                reg_info = <&soc_dvdd18_emmc_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_2 SLG51000_ID_LDO3>;
+					parent_pmic_dev = <&pmic_dev_0 7 0>;
+				};
+			};
+
+			regu_config_20 {
+                reg_info = <&soc_dovdd18_rgb_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_2 SLG51000_ID_LDO4>;
+				    auto_on_info = <8 0 1800000>;
+					auto_off_info = <2 1>;
+				};
+			};
+
+			regu_config_21 {
+                reg_info = <&soc_dvdd12_rgb_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_2 SLG51000_ID_LDO5>;
+				    auto_on_info = <9 0 1200000>;
+					auto_off_info = <3 1>;
+				};
+			};
+
+			regu_config_22 {
+                reg_info = <&soc_dvdd12_ir_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_2 SLG51000_ID_LDO6>;
+				    auto_on_info = <10 0 1200000>;
+					auto_off_info = <4 1>;
+				};
+			};
+
+			 regu_config_23 {
+                reg_info = <&soc_dovdd18_ir_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_2 SLG51000_ID_LDO7>;
+				    auto_on_info = <11 0 1800000>;
+					auto_off_info = <5 1>;
+				};
+			};
+		};
+	};
+
 	};
 
 	chosen {

arch/riscv/dts/light-b-product.dts

@@ -1,4 +1,7 @@
 /dts-v1/;
+
+#include <dt-bindings/pmic/light_pmic.h>
+
 / {
 	model = "T-HEAD c910 light";
 	compatible = "thead,c910_light";
@@ -469,6 +472,362 @@
 			lcd-en-gpios    = <&gpio1_porta 9 0>; /* active high */
 			lcd-bias-en-gpios = <&gpio1_porta 10 0>;/* active high */
 		};
+
+		aon {
+		compatible = "thead,light-aon";
+		status = "okay";
+
+		wakeup-by-gpio-on;
+		wakeup-by-rtc-on;
+
+		pd: light-aon-pd {
+			compatible = "thead,light-aon-pd";
+			#power-domain-cells = <1>;
+		};
+
+		light-regu-reg {
+			compatible = "thead,light-dialog-pmic";
+			status = "okay";
+
+
+
+			soc_dvdd18_aon_reg: soc_dvdd18_aon {
+				regulator-name = "soc_dvdd18_aon";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_avdd33_usb3_reg: soc_avdd33_usb3 {
+				regulator-name = "soc_avdd33_usb3";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_dvdd08_aon_reg: soc_dvdd08_aon {
+				regulator-name = "soc_dvdd08_aon";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_apcpu_dvdd_dvddm_reg: soc_apcpu_dvdd_dvddm {
+				regulator-name = "soc_apcpu_dvdd_dvddm";
+				regulator-min-microvolt = <300000>;
+				regulator-max-microvolt = <1570000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_dvdd08_ddr_reg: soc_dvdd08_ddr {
+				regulator-name = "soc_dvdd08_ddr";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_vdd_ddr_1v8_reg: soc_vdd_ddr_1v8 {
+				regulator-name = "soc_vdd_ddr_1v8";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_vdd_ddr_1v1_reg: soc_vdd_ddr_1v1 {
+				regulator-name = "soc_vdd_ddr_1v1";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_vdd_ddr_0v6_reg: soc_vdd_ddr_0v6 {
+				regulator-name = "soc_vdd_ddr_0v6";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_dvdd18_ap_reg: soc_dvdd18_ap {
+				regulator-name = "soc_dvdd18_ap";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_dvdd08_ap_reg: soc_dvdd08_ap {
+				regulator-name = "soc_dvdd08_ap";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_avdd08_mipi_hdmi_reg: soc_avdd08_mipi_hdmi {
+				regulator-name = "soc_avdd08_mipi_hdmi";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_avdd18_mipi_hdmi_reg: soc_avdd18_mipi_hdmi {
+				regulator-name = "soc_avdd18_mipi_hdmi";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_dvdd33_emmc_reg: soc_dvdd33_emmc {
+				regulator-name = "soc_dvdd33_emmc";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_dvdd18_emmc_reg: soc_dvdd18_emmc {
+				regulator-name = "soc_vdd18_emmc";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+			soc_dovdd18_scan_reg: soc_dovdd18_scan {
+				regulator-name = "soc_dovdd18_scan";
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <3600000>;
+				status = "disabled";
+			};
+			soc_vext_2v8_reg: soc_vext_2v8 {
+				regulator-name = "soc_vext_2v8";
+				regulator-boot-on;
+				regulator-always-on;
+				status = "disabled";
+			};
+			soc_dvdd12_scan_reg: soc_dvdd12_scan {
+				regulator-name = "soc_dvdd12_scan";
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <3600000>;
+				status = "disabled";
+			};
+			soc_avdd28_scan_en_reg: soc_avdd28_scan_en {
+				regulator-name = "soc_avdd28_scan_en";
+				regulator-min-microvolt = <2800000>;
+				regulator-max-microvolt = <2800000>;
+				status = "disabled";
+			};
+			soc_avdd28_rgb_reg: soc_avdd28_rgb {
+				regulator-name = "soc_avdd28_rgb";
+				regulator-min-microvolt = <2200000>;
+				regulator-max-microvolt = <3475000>;
+				regulator-boot-on;
+				regulator-always-on;
+				status = "disabled";
+			};
+			soc_dovdd18_rgb_reg: soc_dovdd18_rgb {
+				regulator-name = "soc_dovdd18_rgb";
+				regulator-min-microvolt = <1200000>;
+				regulator-max-microvolt = <3600000>;
+				regulator-boot-on;
+				regulator-always-on;
+				status = "disabled";
+			};
+			soc_dvdd12_rgb_reg: soc_dvdd12_rgb {
+				regulator-name = "soc_dvdd12_rgb";
+				regulator-min-microvolt = <400000>;
+				regulator-max-microvolt = <1675000>;
+				regulator-boot-on;
+				regulator-always-on;
+				status = "disabled";
+			};
+			soc_avdd25_ir_reg: soc_avdd25_ir {
+				regulator-name = "soc_avdd25_ir";
+				regulator-min-microvolt = <2200000>;
+				regulator-max-microvolt = <3475000>;
+				regulator-boot-on;
+				regulator-always-on;
+				status = "disabled";
+			};
+			soc_dovdd18_ir_reg: soc_dovdd18_ir {
+				regulator-name = "soc_dovdd18_ir";
+				regulator-min-microvolt = <1200000>;
+				regulator-max-microvolt = <3600000>;
+				regulator-boot-on;
+				regulator-always-on;
+				status = "disabled";
+			};
+			soc_dvdd12_ir_reg: soc_dvdd12_ir {
+				regulator-name = "soc_dvdd12_ir";
+				regulator-min-microvolt = <400000>;
+				regulator-max-microvolt = <1675000>;
+				regulator-boot-on;
+				regulator-always-on;
+				status = "disabled";
+			};
+			soc_adc_vref_reg: soc_adc_vref {
+				regulator-name = "soc_adc_vref";
+			};
+			soc_lcd0_en_reg: soc_lcd0_en {
+				regulator-name = "soc_lcd0_en";
+			};
+			soc_vext_1v8_reg: soc_vext_1v8 {
+				regulator-name = "soc_vext_1v8";
+			};
+	   };
+
+	    aon_pmic_config {
+			compatible = "thead,light-pmic-conf";
+			status = "okay";
+			#address-cells = <1>;
+		    #size-cells = <0>;
+			iic-config = <0 0 2>;
+			pmic_dev_0: pmic-dev@0 {
+			  pmic-name = "ricoh,rn5t567,v0";
+			  pmic-addr = <0x31>;
+			  pmic_wdt_on;
+			  status = "okay";
+			};
+
+			pmic_dev_1: pmic-dev@1 {
+			  pmic-name = "ricoh,rn5t567,v1";
+			  pmic-addr = <0x32>;
+			  status = "okay";
+			};
+
+			regu_config_0 {
+                reg_info = <&soc_dvdd18_aon_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_0 RICOH567_ID_LDO4>;
+				};
+			};
+
+			regu_config_1 {
+                reg_info = <&soc_avdd33_usb3_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_0 RICOH567_ID_LDO1>;
+				};
+			};
+
+			regu_config_2 {
+                reg_info = <&soc_dvdd08_aon_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_0 RICOH567_ID_LDO3>;
+				};
+			};
+
+			regu_config_3 {
+                reg_info = <&soc_apcpu_dvdd_dvddm_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_0 RICOH567_ID_DC3>;
+					auto_on_info = <2 0 800000>;
+				};
+
+				regu_id@1 {
+                    pmic_dev = <&pmic_dev_0 RICOH567_ID_DC4>;
+					auto_on_info = <3 0 800000>;
+				};
+
+				coupling_info@0 {
+					negative-min;
+                    info = <0 1 5 30>;
+				};
+			};
+
+			regu_config_4 {
+                reg_info = <&soc_dvdd08_ddr_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_0 RICOH567_ID_DC1>;
+				};
+			};
+
+			regu_config_5 {
+                reg_info = <&soc_vdd_ddr_1v8_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_0 RICOH567_ID_LDO2>;
+				};
+			};
+
+		    regu_config_6 {
+                reg_info = <&soc_vdd_ddr_1v1_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_1 RICOH567_ID_DC2>;
+				};
+			};
+
+			regu_config_7 {
+                reg_info = <&soc_vdd_ddr_0v6_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_1 RICOH567_ID_DC1>;
+				};
+			};
+
+			regu_config_8 {
+                reg_info = <&soc_dvdd18_ap_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_1 RICOH567_ID_LDO2>;
+				};
+			};
+
+            regu_config_9 {
+                reg_info = <&soc_avdd08_mipi_hdmi_reg>;
+				status = "okay";
+				regu_id@0 {
+					pmic_dev = <&pmic_dev_1 RICOH567_ID_LDO3>;
+				};
+			};
+
+			regu_config_10 {
+                reg_info = <&soc_avdd18_mipi_hdmi_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_1 RICOH567_ID_LDO4>;
+				};
+			};
+
+			regu_config_11 {
+                reg_info = <&soc_dvdd33_emmc_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_1 RICOH567_ID_LDO1>;
+				};
+			};
+
+			regu_config_12 {
+                reg_info = <&soc_dvdd08_ap_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_1 RICOH567_ID_GPIO3>;
+				};
+			};
+
+			regu_config_13 {
+                reg_info = <&soc_dvdd18_emmc_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_1 RICOH567_ID_DC3>;
+				};
+			};
+
+			regu_config_14 {
+                reg_info = <&soc_adc_vref_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_1 RICOH567_ID_LDO5>;
+				};
+			};
+
+			regu_config_15 {
+                reg_info = <&soc_lcd0_en_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_0 RICOH567_ID_LDO5>;
+					auto_on_info = <0 0 1800000>;
+				};
+			};
+
+			regu_config_16 {
+                reg_info = <&soc_vext_1v8_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_1 RICOH567_ID_DC4>;
+					auto_on_info = <1 0 1800000>;
+				};
+			};
+		};
+	};
 	};
 
 	chosen {

arch/riscv/dts/light-lpi4a-laptop.dts

@@ -35,6 +35,7 @@
 };
 
 &panel0 {
+	compatible = "ilitek,ili9881c";
 	status = "okay";
 	backlight = <&lcd_backlight>;
 	// 5v power cycle
@@ -43,8 +44,3 @@
 	/delete-property/ lcd-en-gpios;
 	/delete-property/ lcd-bias-en-gpios;
 };
-
-&sdhci0 {
-	max-frequency = <35000000>;
-	status = "okay";
-};

arch/riscv/dts/light-lpi4a.dts

@@ -1,10 +1,17 @@
 /dts-v1/;
+
+#include <dt-bindings/pmic/light_pmic.h>
+
 / {
 	model = "T-HEAD c910 light";
 	compatible = "thead,c910_light";
 	#address-cells = <2>;
 	#size-cells = <2>;
 
+	config {
+		huben-gpio = <&gpio1_porta 16 0>;
+        };
+
 	memory@0 {
 		device_type = "memory";
 		reg = <0x0 0xc0000000 0x0 0x40000000>;
@@ -147,6 +154,13 @@
 
 			#address-cells = <1>;
 			#size-cells = <0>;
+
+			pcal6408ahk_d: gpio@20 {
+				compatible = "nxp,pca9557";
+				reg = <0x18>;
+				gpio-controller;
+				#gpio-cells = <2>;
+			};
 		};
 
 		i2c4: i2c@ffe7f28000{
@@ -157,13 +171,6 @@
 
 			#address-cells = <1>;
 			#size-cells = <0>;
-
-			pcal6408ahk_a: gpio@20 {
-				compatible = "nxp,pca9554";
-				reg = <0x20>;
-				gpio-controller;
-				#gpio-cells = <2>;
-			};
 		};
 
 		i2c5: i2c@fff7f2c000{
@@ -382,6 +389,20 @@
 			reg = <0xff 0xef600000 0x0 0x100>;
 		};
 
+		usb: usb@ffe7040000 {
+			compatible = "snps,dwc3";
+			reg = <0xff 0xe7040000 0x0 0x10000>;
+			interrupts = <68>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			maximum-speed = "super-speed";
+			dr_mode = "host";
+			dma-mask = <0xf 0xffffffff>;
+			snps,usb3_lpm_capable;
+			snps,usb_sofitpsync;
+			status = "okay";
+		};
+
 		axiscr {
 			compatible = "thead,axiscr";
 			reg = <0xff 0xff004000 0x0 0x1000>;
@@ -473,12 +494,375 @@
 		};
 
 		panel0: dsi_panel0 {
-			compatible      = "ilitek,ili9881c";
+			compatible      = "jadard,jd9365da-h3";
 			backlight       = <&lcd_backlight>;
-			reset-gpios     = <&gpio1_porta 5 1>;   /* active low  */
-			lcd-en-gpios    = <&pcal6408ahk_a 2 0>; /* active high */
-			lcd-bias-en-gpios = <&pcal6408ahk_a 4 0>;/* active high */
+			reset-gpio     = <&pcal6408ahk_d 7 0>;
+			hsvcc-gpio   = <&pcal6408ahk_d 6 1>;
+			vspn3v3-gpio = <&pcal6408ahk_d 5 1>;
 		};
+
+		aon {
+		compatible = "thead,light-aon";
+		status = "okay";
+
+		wakeup-by-gpio-on;
+		wakeup-by-rtc-on;
+
+		pd: light-aon-pd {
+			compatible = "thead,light-aon-pd";
+			#power-domain-cells = <1>;
+		};
+
+		light-regu-reg {
+			compatible = "thead,light-dialog-pmic";
+			status = "okay";
+
+
+
+			soc_dvdd18_aon_reg: soc_dvdd18_aon {
+				regulator-name = "soc_dvdd18_aon";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_avdd33_usb3_reg: soc_avdd33_usb3 {
+				regulator-name = "soc_avdd33_usb3";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_dvdd08_aon_reg: soc_dvdd08_aon {
+				regulator-name = "soc_dvdd08_aon";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_apcpu_dvdd_dvddm_reg: soc_apcpu_dvdd_dvddm {
+				regulator-name = "soc_apcpu_dvdd_dvddm";
+				regulator-min-microvolt = <300000>;
+				regulator-max-microvolt = <1570000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_dvdd08_ddr_reg: soc_dvdd08_ddr {
+				regulator-name = "soc_dvdd08_ddr";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_vdd_ddr_1v8_reg: soc_vdd_ddr_1v8 {
+				regulator-name = "soc_vdd_ddr_1v8";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_vdd_ddr_1v1_reg: soc_vdd_ddr_1v1 {
+				regulator-name = "soc_vdd_ddr_1v1";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_vdd_ddr_0v6_reg: soc_vdd_ddr_0v6 {
+				regulator-name = "soc_vdd_ddr_0v6";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_dvdd18_ap_reg: soc_dvdd18_ap {
+				regulator-name = "soc_dvdd18_ap";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_dvdd08_ap_reg: soc_dvdd08_ap {
+				regulator-name = "soc_dvdd08_ap";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_avdd08_mipi_hdmi_reg: soc_avdd08_mipi_hdmi {
+				regulator-name = "soc_avdd08_mipi_hdmi";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_avdd18_mipi_hdmi_reg: soc_avdd18_mipi_hdmi {
+				regulator-name = "soc_avdd18_mipi_hdmi";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_dvdd33_emmc_reg: soc_dvdd33_emmc {
+				regulator-name = "soc_dvdd33_emmc";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_dvdd18_emmc_reg: soc_dvdd18_emmc {
+				regulator-name = "soc_vdd18_emmc";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+			soc_dovdd18_scan_reg: soc_dovdd18_scan {
+				regulator-name = "soc_dovdd18_scan";
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <3600000>;
+			};
+			soc_vext_2v8_reg: soc_vext_2v8 {
+				regulator-name = "soc_vext_2v8";
+				regulator-boot-on;
+				regulator-always-on;
+				status = "disabled";
+			};
+			soc_dvdd12_scan_reg: soc_dvdd12_scan {
+				regulator-name = "soc_dvdd12_scan";
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <3600000>;
+			};
+			soc_avdd28_scan_en_reg: soc_avdd28_scan_en {
+				regulator-name = "soc_avdd28_scan_en";
+				regulator-min-microvolt = <2800000>;
+				regulator-max-microvolt = <2800000>;
+			};
+			soc_avdd28_rgb_reg: soc_avdd28_rgb {
+				regulator-name = "soc_avdd28_rgb";
+				regulator-min-microvolt = <2200000>;
+				regulator-max-microvolt = <3475000>;
+				regulator-boot-on;
+				regulator-always-on;
+				status = "disabled";
+			};
+			soc_dovdd18_rgb_reg: soc_dovdd18_rgb {
+				regulator-name = "soc_dovdd18_rgb";
+				regulator-min-microvolt = <1200000>;
+				regulator-max-microvolt = <3600000>;
+				regulator-boot-on;
+				regulator-always-on;
+				status = "disabled";
+			};
+			soc_dvdd12_rgb_reg: soc_dvdd12_rgb {
+				regulator-name = "soc_dvdd12_rgb";
+				regulator-min-microvolt = <400000>;
+				regulator-max-microvolt = <1675000>;
+				regulator-boot-on;
+				regulator-always-on;
+				status = "disabled";
+			};
+			soc_avdd25_ir_reg: soc_avdd25_ir {
+				regulator-name = "soc_avdd25_ir";
+				regulator-min-microvolt = <2200000>;
+				regulator-max-microvolt = <3475000>;
+				regulator-boot-on;
+				regulator-always-on;
+				status = "disabled";
+			};
+			soc_dovdd18_ir_reg: soc_dovdd18_ir {
+				regulator-name = "soc_dovdd18_ir";
+				regulator-min-microvolt = <1200000>;
+				regulator-max-microvolt = <3600000>;
+				regulator-boot-on;
+				regulator-always-on;
+				status = "disabled";
+			};
+			soc_dvdd12_ir_reg: soc_dvdd12_ir {
+				regulator-name = "soc_dvdd12_ir";
+				regulator-min-microvolt = <400000>;
+				regulator-max-microvolt = <1675000>;
+				regulator-boot-on;
+				regulator-always-on;
+				status = "disabled";
+			};
+	   };
+
+	    aon_pmic_config {
+			compatible = "thead,light-pmic-conf";
+			status = "okay";
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+			iic-config = <0 0 2>;
+			pmic_dev_0: pmic-dev@0 {
+			  pmic-name = "dialog,da9063,v1";
+			  pmic-addr = <0x5a 0x5b>;
+			  pmic_wdt_on;
+			  status = "okay";
+			};
+
+			pmic_dev_1: pmic-dev@1 {
+			  pmic-name = "dialog,da9121,v1";
+			  pmic-addr = <0x68>;
+			  status = "okay";
+			};
+
+			regu_config_0 {
+                reg_info = <&soc_dvdd18_aon_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_0 DA9063_ID_LDO3>;
+				};
+			};
+
+			regu_config_1 {
+                reg_info = <&soc_avdd33_usb3_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_0 DA9063_ID_LDO9>;
+				};
+			};
+
+			regu_config_2 {
+                reg_info = <&soc_dvdd08_aon_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_0 DA9063_ID_LDO2>;
+				};
+			};
+
+			regu_config_3 {
+                reg_info = <&soc_apcpu_dvdd_dvddm_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_0 DA9063_ID_BCORE1>;
+					auto_on_info = <0 0 800000>;
+				};
+
+				regu_id@1 {
+                    pmic_dev = <&pmic_dev_0 DA9063_ID_BCORE2>;
+					auto_on_info = <1 0 800000>;
+				};
+
+				regu_id@2 {
+                    pmic_dev = <&pmic_dev_0 DA9063_ID_BUCKIO>;
+					auto_on_info = <2 0 800000>;
+				};
+
+				coupling_info@0 {
+					negative-min;
+                    info = <0 2 5 30>;
+				};
+
+				coupling_info@1 {
+					negative-min;
+                    info = <1 2 5 30>;
+				};
+			};
+
+			regu_config_4 {
+                reg_info = <&soc_dvdd08_ddr_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_0 DA9063_ID_BUCKPERI>;
+				};
+			};
+
+			regu_config_5 {
+                reg_info = <&soc_vdd_ddr_1v8_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_0 DA9063_ID_LDO4>;
+				};
+			};
+
+		    regu_config_6 {
+                reg_info = <&soc_vdd_ddr_1v1_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_0 DA9063_ID_BUCKMEM>;
+				};
+			};
+
+			regu_config_7 {
+                reg_info = <&soc_vdd_ddr_0v6_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_0 DA9063_ID_BUCKPRO>;
+				};
+			};
+
+			regu_config_8 {
+                reg_info = <&soc_dvdd18_ap_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_0 DA9063_ID_LDO11>;
+				};
+			};
+
+            regu_config_9 {
+                reg_info = <&soc_avdd08_mipi_hdmi_reg>;
+				status = "okay";
+				regu_id@0 {
+					pmic_dev = <&pmic_dev_0 DA9063_ID_LDO1>;
+				};
+			};
+
+			regu_config_10 {
+                reg_info = <&soc_avdd18_mipi_hdmi_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_0 DA9063_ID_LDO5>;
+				};
+			};
+
+			regu_config_11 {
+                reg_info = <&soc_dvdd33_emmc_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_0 DA9063_ID_LDO10>;
+				};
+			};
+
+			regu_config_12 {
+                reg_info = <&soc_dovdd18_scan_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_0 DA9063_ID_LDO6>;
+					auto_on_info = <3 1 1800000>;
+					auto_off_info = <1 1>;
+				};
+			};
+
+
+			regu_config_13 {
+                reg_info = <&soc_dvdd12_scan_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_0 DA9063_ID_LDO8>;
+					auto_on_info = <4 1 1200000>;
+					auto_off_info = <2 1>;
+				};
+			};
+
+			regu_config_14 {
+                reg_info = <&soc_avdd28_scan_en_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_0 DA9063_ID_LDO7>;
+					auto_on_info = <5 1 2800000>;
+					auto_off_info = <0 1>;
+				};
+			};
+
+			regu_config_15 {
+                reg_info = <&soc_dvdd08_ap_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_1 DA9121_ID_BUCK1>;
+                    parent_pmic_dev = <&pmic_dev_0 2 0>;
+				};
+			};
+
+			regu_config_16 {
+                reg_info = <&soc_dvdd18_emmc_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_0 DA9063_ID_GPIO7>;
+					parent_pmic_dev = <&pmic_dev_0 7 0>;
+				};
+			};
+		};
+	};
+
 	};
 
 	chosen {

arch/riscv/dts/light-milkv-meles.dts

@@ -1,4 +1,7 @@
 /dts-v1/;
+
+#include <dt-bindings/pmic/light_pmic.h>
+
 / {
 	model = "Milk-V Meles";
 	compatible = "milkv,meles", "thead,c910_light";
@@ -6,7 +9,8 @@
 	#size-cells = <2>;
 
 	config {
-		select-gpio = <&gpio1_porta 16 0>;
+		select-gpio = <&gpio1_porta 16 0>; // Enable the blue LED on Milk-V Meles
+		fan-gpio = <&gpio2_porta 4 0>; // Enable the fan on Milk-V Meles, see schematic for details
 	};
 
 	memory@0 {
@@ -279,6 +283,369 @@
 				u-boot,dm-pre-reloc;
 			};
 		};
+
+		aon {
+		compatible = "thead,light-aon";
+		status = "okay";
+
+		wakeup-by-gpio-on;
+		wakeup-by-rtc-on;
+
+		pd: light-aon-pd {
+			compatible = "thead,light-aon-pd";
+			#power-domain-cells = <1>;
+		};
+
+		light-regu-reg {
+			compatible = "thead,light-dialog-pmic";
+			status = "okay";
+
+
+
+			soc_dvdd18_aon_reg: soc_dvdd18_aon {
+				regulator-name = "soc_dvdd18_aon";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_avdd33_usb3_reg: soc_avdd33_usb3 {
+				regulator-name = "soc_avdd33_usb3";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_dvdd08_aon_reg: soc_dvdd08_aon {
+				regulator-name = "soc_dvdd08_aon";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_apcpu_dvdd_dvddm_reg: soc_apcpu_dvdd_dvddm {
+				regulator-name = "soc_apcpu_dvdd_dvddm";
+				regulator-min-microvolt = <300000>;
+				regulator-max-microvolt = <1570000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_dvdd08_ddr_reg: soc_dvdd08_ddr {
+				regulator-name = "soc_dvdd08_ddr";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_vdd_ddr_1v8_reg: soc_vdd_ddr_1v8 {
+				regulator-name = "soc_vdd_ddr_1v8";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_vdd_ddr_1v1_reg: soc_vdd_ddr_1v1 {
+				regulator-name = "soc_vdd_ddr_1v1";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_vdd_ddr_0v6_reg: soc_vdd_ddr_0v6 {
+				regulator-name = "soc_vdd_ddr_0v6";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_dvdd18_ap_reg: soc_dvdd18_ap {
+				regulator-name = "soc_dvdd18_ap";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_dvdd08_ap_reg: soc_dvdd08_ap {
+				regulator-name = "soc_dvdd08_ap";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_avdd08_mipi_hdmi_reg: soc_avdd08_mipi_hdmi {
+				regulator-name = "soc_avdd08_mipi_hdmi";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_avdd18_mipi_hdmi_reg: soc_avdd18_mipi_hdmi {
+				regulator-name = "soc_avdd18_mipi_hdmi";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_dvdd33_emmc_reg: soc_dvdd33_emmc {
+				regulator-name = "soc_dvdd33_emmc";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_dvdd18_emmc_reg: soc_dvdd18_emmc {
+				regulator-name = "soc_vdd18_emmc";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+			soc_dovdd18_scan_reg: soc_dovdd18_scan {
+				regulator-name = "soc_dovdd18_scan";
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <3600000>;
+			};
+			soc_vext_2v8_reg: soc_vext_2v8 {
+				regulator-name = "soc_vext_2v8";
+				regulator-boot-on;
+				regulator-always-on;
+				status = "disabled";
+			};
+			soc_dvdd12_scan_reg: soc_dvdd12_scan {
+				regulator-name = "soc_dvdd12_scan";
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <3600000>;
+			};
+			soc_avdd28_scan_en_reg: soc_avdd28_scan_en {
+				regulator-name = "soc_avdd28_scan_en";
+				regulator-min-microvolt = <2800000>;
+				regulator-max-microvolt = <2800000>;
+			};
+			soc_avdd28_rgb_reg: soc_avdd28_rgb {
+				regulator-name = "soc_avdd28_rgb";
+				regulator-min-microvolt = <2200000>;
+				regulator-max-microvolt = <3475000>;
+				regulator-boot-on;
+				regulator-always-on;
+				status = "disabled";
+			};
+			soc_dovdd18_rgb_reg: soc_dovdd18_rgb {
+				regulator-name = "soc_dovdd18_rgb";
+				regulator-min-microvolt = <1200000>;
+				regulator-max-microvolt = <3600000>;
+				regulator-boot-on;
+				regulator-always-on;
+				status = "disabled";
+			};
+			soc_dvdd12_rgb_reg: soc_dvdd12_rgb {
+				regulator-name = "soc_dvdd12_rgb";
+				regulator-min-microvolt = <400000>;
+				regulator-max-microvolt = <1675000>;
+				regulator-boot-on;
+				regulator-always-on;
+				status = "disabled";
+			};
+			soc_avdd25_ir_reg: soc_avdd25_ir {
+				regulator-name = "soc_avdd25_ir";
+				regulator-min-microvolt = <2200000>;
+				regulator-max-microvolt = <3475000>;
+				regulator-boot-on;
+				regulator-always-on;
+				status = "disabled";
+			};
+			soc_dovdd18_ir_reg: soc_dovdd18_ir {
+				regulator-name = "soc_dovdd18_ir";
+				regulator-min-microvolt = <1200000>;
+				regulator-max-microvolt = <3600000>;
+				regulator-boot-on;
+				regulator-always-on;
+				status = "disabled";
+			};
+			soc_dvdd12_ir_reg: soc_dvdd12_ir {
+				regulator-name = "soc_dvdd12_ir";
+				regulator-min-microvolt = <400000>;
+				regulator-max-microvolt = <1675000>;
+				regulator-boot-on;
+				regulator-always-on;
+				status = "disabled";
+			};
+	   };
+
+	    aon_pmic_config {
+			compatible = "thead,light-pmic-conf";
+			status = "okay";
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+			iic-config = <0 0 2>;
+			pmic_dev_0: pmic-dev@0 {
+			  pmic-name = "dialog,da9063,v1";
+			  pmic-addr = <0x5a 0x5b>;
+			  pmic_wdt_on;
+			  status = "okay";
+			};
+
+			pmic_dev_1: pmic-dev@1 {
+			  pmic-name = "dialog,da9121,v1";
+			  pmic-addr = <0x68>;
+			  status = "okay";
+			};
+
+			regu_config_0 {
+                reg_info = <&soc_dvdd18_aon_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_0 DA9063_ID_LDO3>;
+				};
+			};
+
+			regu_config_1 {
+                reg_info = <&soc_avdd33_usb3_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_0 DA9063_ID_LDO9>;
+				};
+			};
+
+			regu_config_2 {
+                reg_info = <&soc_dvdd08_aon_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_0 DA9063_ID_LDO2>;
+				};
+			};
+
+			regu_config_3 {
+                reg_info = <&soc_apcpu_dvdd_dvddm_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_0 DA9063_ID_BCORE1>;
+					auto_on_info = <0 0 800000>;
+				};
+
+				regu_id@1 {
+                    pmic_dev = <&pmic_dev_0 DA9063_ID_BCORE2>;
+					auto_on_info = <1 0 800000>;
+				};
+
+				regu_id@2 {
+                    pmic_dev = <&pmic_dev_0 DA9063_ID_BUCKIO>;
+					auto_on_info = <2 0 800000>;
+				};
+
+				coupling_info@0 {
+					negative-min;
+                    info = <0 2 5 30>;
+				};
+
+				coupling_info@1 {
+					negative-min;
+                    info = <1 2 5 30>;
+				};
+			};
+
+			regu_config_4 {
+                reg_info = <&soc_dvdd08_ddr_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_0 DA9063_ID_BUCKPERI>;
+				};
+			};
+
+			regu_config_5 {
+                reg_info = <&soc_vdd_ddr_1v8_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_0 DA9063_ID_LDO4>;
+				};
+			};
+
+		    regu_config_6 {
+                reg_info = <&soc_vdd_ddr_1v1_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_0 DA9063_ID_BUCKMEM>;
+				};
+			};
+
+			regu_config_7 {
+                reg_info = <&soc_vdd_ddr_0v6_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_0 DA9063_ID_BUCKPRO>;
+				};
+			};
+
+			regu_config_8 {
+                reg_info = <&soc_dvdd18_ap_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_0 DA9063_ID_LDO11>;
+				};
+			};
+
+            regu_config_9 {
+                reg_info = <&soc_avdd08_mipi_hdmi_reg>;
+				status = "okay";
+				regu_id@0 {
+					pmic_dev = <&pmic_dev_0 DA9063_ID_LDO1>;
+				};
+			};
+
+			regu_config_10 {
+                reg_info = <&soc_avdd18_mipi_hdmi_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_0 DA9063_ID_LDO5>;
+				};
+			};
+
+			regu_config_11 {
+                reg_info = <&soc_dvdd33_emmc_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_0 DA9063_ID_LDO10>;
+				};
+			};
+
+			regu_config_12 {
+                reg_info = <&soc_dovdd18_scan_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_0 DA9063_ID_LDO6>;
+					auto_on_info = <3 1 1800000>;
+					auto_off_info = <1 1>;
+				};
+			};
+
+
+			regu_config_13 {
+                reg_info = <&soc_dvdd12_scan_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_0 DA9063_ID_LDO8>;
+					auto_on_info = <4 1 1200000>;
+					auto_off_info = <2 1>;
+				};
+			};
+
+			regu_config_14 {
+                reg_info = <&soc_avdd28_scan_en_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_0 DA9063_ID_LDO7>;
+					auto_on_info = <5 1 2800000>;
+					auto_off_info = <0 1>;
+				};
+			};
+
+			regu_config_15 {
+                reg_info = <&soc_dvdd08_ap_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_1 DA9121_ID_BUCK1>;
+                    parent_pmic_dev = <&pmic_dev_0 2 0>;
+				};
+			};
+
+			regu_config_16 {
+                reg_info = <&soc_dvdd18_emmc_reg>;
+				status = "okay";
+				regu_id@0 {
+                    pmic_dev = <&pmic_dev_0 DA9063_ID_GPIO7>;
+					parent_pmic_dev = <&pmic_dev_0 7 0>;
+				};
+			};
+		};
+	};
+	
 	};
 
 	chosen {

arch/riscv/lib/bootm.c

@@ -110,7 +110,7 @@ void next_stage(void)
 bool has_reset_sample(ulong dtb_addr)
 {
 	int node_offset;
-	node_offset = fdt_path_offset(dtb_addr, "/soc/reset-sample");
+	node_offset = fdt_path_offset((void *)dtb_addr, "/soc/reset-sample");
 	if (node_offset < 0) {
 		printf("## fdt has no reset_sample\n");
 		return false;
@@ -160,8 +160,8 @@ static void boot_jump_linux(bootm_headers_t *images, int flag)
 
 	announce_and_cleanup(fake);
 
-	_load_start = kernel;
-	_dtb_addr = images->ft_addr;
+	_load_start = (ulong)kernel;
+	_dtb_addr = (ulong)(images->ft_addr);
 	_dyn_info_addr = (ulong)&opensbi_info;
 	if (!has_reset_sample(_dtb_addr)) {
 		opensbi_info.magic = FW_DYNAMIC_INFO_MAGIC_VALUE;

board/thead/light-c910/Kconfig

@@ -140,8 +140,7 @@ config SYS_TEXT_BASE
 
 config SPL_TEXT_BASE
     hex
-    default 0xffe0000800 if LIGHT_SEC_BOOT_WITH_VERIFY_VAL_A || LIGHT_SEC_BOOT_WITH_VERIFY_VAL_B || LIGHT_SEC_BOOT_WITH_VERIFY_ANT_REF || LIGHT_SEC_BOOT_WITH_VERIFY_LPI4A
-    default 0xffe0000000 if !(LIGHT_SEC_BOOT_WITH_VERIFY_VAL_A || LIGHT_SEC_BOOT_WITH_VERIFY_VAL_B || LIGHT_SEC_BOOT_WITH_VERIFY_ANT_REF || LIGHT_SEC_BOOT_WITH_VERIFY_LPI4A)
+    default 0xffe0000000
 
 config SPL_MAX_SIZE
     hex
@@ -258,6 +257,11 @@ config DDR_DDP
 	  Enabling this will support ddr Dual Die Package configuration.
 	  e.g. to support 8GB ddr device with 17-bit row address (16:0)
 
+config FIXUP_MEMORY_REGION
+	bool "self-adapt to query and fixup memory region"
+	help
+	  Enabling this will support self-adapt to query and fixup memory region
+
 config DDR_H32_MODE
         bool "LPDDR4/4X 32bit mode configuration"
         help

board/thead/light-c910/Makefile

@@ -23,6 +23,7 @@ obj-$(CONFIG_LPDDR) += $(DDR_SRC_PATH)/init_ddr.o
 obj-$(CONFIG_LPDDR) += $(DDR_SRC_PATH)/pinmux.o
 obj-$(CONFIG_LPDDR) += $(DDR_SRC_PATH)/waitfwdone.o
 obj-$(CONFIG_LPDDR) += $(DDR_SRC_PATH)/ddr_common_func.o
+obj-$(CONFIG_LPDDR) += $(DDR_SRC_PATH)/ddr_retention.o
 obj-$(CONFIG_LPDDR) += $(DDR_SRC_PATH)/common_lib.o
 obj-$(CONFIG_LPDDR) += $(DDR_SRC_PATH)/lpddr4_init.o
 ifdef CONFIG_DDR_DBI_OFF
@@ -63,6 +64,7 @@ obj-y += boot.o
 obj-y += sbmeta/sbmeta.o
 ifndef CONFIG_TARGET_LIGHT_FPGA_FM_C910
 obj-$(CONFIG_LPDDR) += $(DDR_SRC_PATH)/ddr_common_func.o
+obj-$(CONFIG_LPDDR) += $(DDR_SRC_PATH)/ddr_retention.o
 obj-$(CONFIG_LPDDR) += $(DDR_SRC_PATH)/common_lib.o
 endif
 

board/thead/light-c910/board.c

@@ -8,11 +8,18 @@
 #include <asm/io.h>
 #include <dwc3-uboot.h>
 #include <usb.h>
+#include <usb/xhci.h>
 #include <cpu_func.h>
 #include <asm/gpio.h>
 #include <abuf.h>
 #include "sec_library.h"
 
+#ifdef CONFIG_LIGHT_AON_CONF
+#include "../../../drivers/misc/light_regu.h"
+#include "dm/device.h"
+#include "dm/uclass.h"
+#endif
+
 #ifdef CONFIG_USB_DWC3
 static struct dwc3_device dwc3_device_data = {
 	.maximum_speed = USB_SPEED_SUPER,
@@ -29,6 +36,13 @@ int usb_gadget_handle_interrupts(int index)
 int board_usb_init(int index, enum usb_init_type init)
 {
 	dwc3_device_data.base = 0xFFE7040000UL;
+
+	if (init == USB_INIT_DEVICE) {
+		dwc3_device_data.dr_mode = USB_DR_MODE_PERIPHERAL;
+	} else {
+		dwc3_device_data.dr_mode = USB_DR_MODE_HOST;
+	}
+
 	return dwc3_uboot_init(&dwc3_device_data);
 }
 
@@ -38,6 +52,26 @@ int board_usb_cleanup(int index, enum usb_init_type init)
 	return 0;
 }
 
+int xhci_hcd_init(int index, struct xhci_hccr **hccr, struct xhci_hcor **hcor)
+{
+	int ret = board_usb_init(index, USB_INIT_HOST);
+	if (ret != 0) {
+		puts("Failed to initialize board for USB\n");
+		return ret;
+	}
+
+	*hccr = (struct xhci_hccr *)dwc3_device_data.base;
+	*hcor = (struct xhci_hcor *)(dwc3_device_data.base +
+			HC_LENGTH(xhci_readl(&(*hccr)->cr_capbase)));;
+
+	return ret;
+}
+
+void xhci_hcd_stop(int index)
+{
+	board_usb_cleanup(index, USB_INIT_HOST);
+}
+
 int g_dnl_board_usb_cable_connected(void)
 {
 	return 1;
@@ -45,9 +79,14 @@ int g_dnl_board_usb_cable_connected(void)
 #endif
 
 #ifdef CONFIG_CMD_BOOT_SLAVE
+#ifdef CONFIG_LIGHT_AON_CONF
+#define E902_AON_CONFIG_SIZE 0xC00
+#else
+#define E902_AON_CONFIG_SIZE 0x000
+#endif
 #define E902_SYSREG_START	0xfffff48044
 #define E902_SYSREG_RESET	0xfffff44024
-#define E902_START_ADDRESS	0xFFEF8000
+#define E902_START_ADDRESS	(0xFFEF8000 + E902_AON_CONFIG_SIZE)
 #define C910_E902_START_ADDRESS 0xFFFFEF8000
 #define E902_IOPMP_BASE		0xFFFFC21000
 
@@ -87,37 +126,125 @@ void set_c906_cpu_entry(phys_addr_t entry_h, phys_addr_t entry_l)
 
 void boot_audio(void)
 {
-        writel(0x37, (volatile void *)C906_RESET_REG);
+	writel(0x37, (volatile void *)C906_RESET_REG);
 
-        set_c906_cpu_entry(C906_START_ADDRESS_H, C906_START_ADDRESS_L);
-        flush_cache((uintptr_t)C910_C906_START_ADDRESS, 0x20000);
+	set_c906_cpu_entry(C906_START_ADDRESS_H, C906_START_ADDRESS_L);
+	flush_cache((uintptr_t)C910_C906_START_ADDRESS, 0x20000);
 
-        writel(0x7ffff1f, (volatile void *)C906_CPR_IPCG_ADDRESS);
-        writel((1<<23) | (1<<24), (volatile void *)C906_IOCTL_GPIO_SEL_ADDRESS);
-        writel(0, (volatile void *)C906_IOCTL_AF_SELH_ADDRESS);
+	writel(0x7ffff1f, (volatile void *)C906_CPR_IPCG_ADDRESS);
+	writel((1<<23) | (1<<24), (volatile void *)C906_IOCTL_GPIO_SEL_ADDRESS);
+	writel(0, (volatile void *)C906_IOCTL_AF_SELH_ADDRESS);
 
-        writel(0x3f, (volatile void *)C906_RESET_REG);
+	writel(0x3f, (volatile void *)C906_RESET_REG);
 }
 
-void boot_aon(void)
+#ifdef CONFIG_LIGHT_AON_CONF
+
+int get_and_set_aon_config_data(void)
 {
+	int ret =0;
+    struct udevice *dev;
+	struct mic_regu_platdata *config_data =NULL;
+
+	ret = uclass_first_device_err(UCLASS_MISC, &dev);
+	if(ret){
+        printf("get light aon config faild %d\n", ret);
+		return ret;
+	}
+
+	config_data = (struct mic_regu_platdata *)(dev->platdata);
+
+    volatile aon_config_t* read_config = (aon_config_t* )C910_E902_START_ADDRESS;
+	if(strncmp((const char*)read_config->magic , AON_CONFIG_MAGIC, strlen(AON_CONFIG_MAGIC))) {
+        printf("No aon config magic found in aon bin, please check the aon bin\n");
+		return -1;
+	}
+
+	if(strncmp((const char*)read_config->version, AON_CONFIG_VERSION, strlen(AON_CONFIG_VERSION))) {
+       printf("Err aon config version, aon bin is:%s, u-boot is:%s\n", read_config->version, AON_CONFIG_VERSION);
+	   return -1;
+	}
+
+	if(PMIC_MAX_HW_ID_NUM >  read_config->max_hw_id_num) {
+        printf("Invald max hw id num, aon bin support %d , u-boot is %d\n",read_config->max_hw_id_num, PMIC_MAX_HW_ID_NUM);
+		return -1;
+	}
+
+	/*set pmic dev info */
+	int pmic_dev_num =  config_data->pmic_list.pmic_num;
+    int pmic_dev_list_offset   = sizeof(aon_config_t);
+	uint64_t pmic_dev_start_addr  =  C910_E902_START_ADDRESS + pmic_dev_list_offset;
+
+	int  regu_num            = config_data->regu_id_list.regu_id_num;
+	int  regu_id_list_offset = pmic_dev_list_offset + pmic_dev_num * sizeof(pmic_dev_info_t);
+	uint64_t regu_start_addr  = C910_E902_START_ADDRESS + regu_id_list_offset;
+    int aon_bin_size  =  regu_id_list_offset + regu_num* sizeof(csi_regu_id_t);
+    if( aon_bin_size > read_config->aon_config_partition_size) {
+         printf("Invalid aon partition size, aon bin support:%lld, u-boot is %d\n", read_config->aon_config_partition_size, aon_bin_size);
+		 return -1;
+	}
+
+	printf("pmic_dev_num:%d offset:%d addr:%lld\n",pmic_dev_num, pmic_dev_list_offset, pmic_dev_start_addr);
+
+	memcpy((void*)pmic_dev_start_addr, config_data->pmic_list.pmic_list, pmic_dev_num * sizeof(pmic_dev_info_t));
+    printf("regu_num:%d offset:%d addr:%lld\n",regu_num,regu_id_list_offset, regu_start_addr);
+
+	memcpy((void*)regu_start_addr, config_data->regu_id_list.regu_id_list, regu_num * sizeof(csi_regu_id_t));
+    
+	read_config->wakeup_flag = config_data->wakeup_flag;
+	read_config->aon_pmic.iic_config.iic_id = config_data->iic_config.iic_id;
+	read_config->aon_pmic.iic_config.addr_mode = config_data->iic_config.addr_mode;
+	read_config->aon_pmic.iic_config.speed  = config_data->iic_config.speed;
+	read_config->aon_pmic.pmic_dev_num =  pmic_dev_num;
+    read_config->aon_pmic.pmic_dev_list_offset   = pmic_dev_list_offset;
+
+	/*set regu list info*/
+	read_config->aon_pmic.regu_num =  regu_num;
+	read_config->aon_pmic.regu_id_list_offset = regu_id_list_offset;
+
+	memcpy((void*)read_config->uboot_set_magic, UBOOT_CONFIG_MAGIC, strlen(UBOOT_CONFIG_MAGIC));
+
+    flush_cache((uintptr_t)C910_E902_START_ADDRESS, aon_bin_size);
+
+	printf("-->pmic_dev_num:%d offset:%d\n",read_config->aon_pmic.pmic_dev_num, read_config->aon_pmic.pmic_dev_list_offset);
+	printf("-->regu_num:%d offset:%d\n",read_config->aon_pmic.regu_num,read_config->aon_pmic.regu_id_list_offset);
+	return 0;
+}
+#endif
+
+int do_boot_aon(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
+{
+#ifdef CONFIG_LIGHT_AON_CONF
+    int ret = 0;
+	ret = get_and_set_aon_config_data();
+	if(ret) {
+        printf("aon config and set faild %d", ret);
+		hang();
+		return ret;
+	}
+#endif
 	writel(0xffffffff, (void *)(E902_IOPMP_BASE + 0xc0));
 	disable_slave_cpu();
 	set_slave_cpu_entry(E902_START_ADDRESS);
 	flush_cache((uintptr_t)C910_E902_START_ADDRESS, 0x10000);
 	enable_slave_cpu();
+	return 0;
 }
 
+U_BOOT_CMD(
+	bootaon, CONFIG_SYS_MAXARGS, 0, do_boot_aon,
+	"Boot aon from memory  ",
+	" "
+);
+
 int do_bootslave(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
 {
-	boot_aon();
-	mdelay(100);
 	boot_audio();
 	return 0;
 }
 #endif
 
-static void light_c910_set_gpio_output_high(void)
+static void light_c910_set_gpio_output_high(const char* gpio_name)
 {
 	ofnode node;
 	struct gpio_desc select_gpio;
@@ -130,9 +257,9 @@ static void light_c910_set_gpio_output_high(void)
 		return;
 	}
 
-	if (gpio_request_by_name_nodev(node, "select-gpio", 0,
+	if (gpio_request_by_name_nodev(node, gpio_name, 0,
 				       &select_gpio, GPIOD_IS_OUT)) {
-		printf("%s: could not find a /config/select-gpio\n", __func__);
+		printf("%s: could not find a /config/%s\n", __func__, gpio_name);
 		return;
 	}
 
@@ -141,7 +268,12 @@ static void light_c910_set_gpio_output_high(void)
 
 int misc_init_r(void)
 {
-	light_c910_set_gpio_output_high();
+	// Enable blue LED
+	light_c910_set_gpio_output_high("select-gpio");
+
+	// Enable fan on some boards(currently only on Meles)
+	// For LPi4A, the fan is controlled by PWM, see lpi4a_fan_pwm_config() in light.c
+	light_c910_set_gpio_output_high("fan-gpio");
 
 	return 0;
 }

board/thead/light-c910/clock_config.c

@@ -1220,7 +1220,7 @@ int clk_config(void)
 		return -EINVAL;
 
 	printf("C910 CPU FREQ: %ldMHz\n", rate / 1000000);
-
+#ifdef PERI_BUS_PLL_FREQ_PRINT
 	rate = clk_light_get_rate("ahb2_cpusys_hclk", CLK_DEV_MUX);
 	if (!rate)
 		return -EINVAL;
@@ -1262,6 +1262,7 @@ int clk_config(void)
 		return -EINVAL;
 
 	printf("DPU1 PLL POSTDIV FREQ: %ldMHZ\n", rate / 1000000);
+#endif
 
 #ifdef AUDIO_PLL_FREQ_PRINT
 	rate = clk_light_get_rate("audio_pll_foutpostdiv", CLK_DEV_PLL);

board/thead/light-c910/ddr.c

@@ -12,3 +12,17 @@ void init_ddr(void)
 {
 	writel(0x1ff << 4, (void *)0xffff005000);
 }
+
+int fixup_ddr_addrmap(unsigned long size)
+{
+	return 0;
+}
+
+int query_ddr_boundary(unsigned long size)
+{
+	return 0;
+}
+unsigned long get_ddr_density(void)
+{
+	return 0x100000000;
+}

board/thead/light-c910/light.c

@@ -11,6 +11,10 @@
 #include <thead/clock_config.h>
 #include <linux/bitops.h>
 #include <asm/arch-thead/light-iopmp.h>
+#include <memalign.h>
+#include <fdt_support.h>
+#include <fs.h>
+#include <asm/global_data.h>
 
 #define SOC_PIN_AP_RIGHT_TOP          (0x0)
 #define SOC_PIN_AP_LEFT_TOP           (0x1)
@@ -1438,7 +1442,7 @@ static void light_iopin_init(void)
 	// light_pin_mux(AOGPIO_15,0);
 	light_pin_cfg(AOGPIO_7, PIN_SPEED_NORMAL, PIN_PN, 2);     ///NC
 	light_pin_cfg(AOGPIO_8, PIN_SPEED_NORMAL, PIN_PN, 2);     ///NC
-	// light_pin_cfg(AOGPIO_9,PIN_SPEED_NORMAL,PIN_PN,2);
+	light_pin_cfg(AOGPIO_9,PIN_SPEED_NORMAL,PIN_PN,2);
 	light_pin_cfg(AOGPIO_10, PIN_SPEED_NORMAL, PIN_PN, 2);
 	light_pin_cfg(AOGPIO_11, PIN_SPEED_NORMAL, PIN_PN, 2);
 	light_pin_cfg(AOGPIO_12, PIN_SPEED_NORMAL, PIN_PN, 2);
@@ -1472,6 +1476,7 @@ static void light_iopin_init(void)
 	light_pin_cfg(AUDIO_PA29, PIN_SPEED_NORMAL, PIN_PN, 2);
 	light_pin_mux(AUDIO_PA30, 0);
 	light_pin_cfg(AUDIO_PA30, PIN_SPEED_NORMAL, PIN_PN, 2);
+	light_pin_mux(AUDIO_PA30, 3);
 
 	// light_pin_mux(AUDIO_PA9,3);                         ///AUDIO-PA-RESET
 	// light_pin_cfg(AUDIO_PA9,PIN_SPEED_NORMAL,PIN_PN,2);
@@ -2247,16 +2252,19 @@ static void light_iopin_init(void)
 }
 
 #else
+
 static void light_iopin_init(void)
 {
 	light_pin_cfg(I2C_AON_SCL,PIN_SPEED_NORMAL,PIN_PN,4);
 	light_pin_cfg(I2C_AON_SDA,PIN_SPEED_NORMAL,PIN_PN,4);
 	light_pin_cfg(AOGPIO_8,PIN_SPEED_NORMAL,PIN_PN,2);
 	light_pin_cfg(AOGPIO_9,PIN_SPEED_NORMAL,PIN_PN,2);
+	light_pin_cfg(AOGPIO_14, PIN_SPEED_NORMAL, PIN_PN, 2);
 	light_pin_mux(AOGPIO_10,1);
 	light_pin_mux(AOGPIO_11,1);
 	light_pin_mux(AOGPIO_12,1);
 	light_pin_mux(AOGPIO_13,1);
+	light_pin_mux(AOGPIO_14, 0);
 	light_pin_mux(AUDIO_PA30,3);
 
 	/*qspi1 cs0 gpio0-1 pad strength and pin-pull mode*/
@@ -2394,13 +2402,59 @@ static void light_iopin_init(void)
 }
 #endif
 
+#define PWM_BASE				((void *)0xffec01c000)
+#define PWM_CHAN_REG(chan, off)	(PWM_BASE + (chan) * 0x20 + (off))
+#define PWM_PER_OFFSET			0x08  // Offset for Periodic Control Register
+#define PWM_FP_OFFSET			0x0C  // Offset for First Phase Control Register
+#define PWM_CTRL_OFFSET			0x00  // Offset for Control Register
+// See T-HEAD TH1520 Peripheral Interface User Manual
+// https://dl.sipeed.com/shareURL/LICHEE/licheepi4a/09_Doc
 
 static void light_pwm_config(void)
 {
-	/* pwm0 */
-	writel(0x4b0, (void *)0xFFEC01C008);
-	writel(0x258, (void *)0xFFEC01C00c);
-	writel(0x328, (void *)0xFFEC01C000);
+	/*
+	 * Enable MIPI Display backlight on PWM0.
+	 * Period=1200 clock cycles, Duty Cycle=50%
+	*/
+	// Set PWM Period to 1200 clock cycles
+	writel(0x4b0, PWM_CHAN_REG(0, PWM_PER_OFFSET));
+	// Set PWM First Phase to 600 clock cycles
+	writel(0x258, PWM_CHAN_REG(0, PWM_FP_OFFSET));
+	// Configure PWM Control Register:
+	// [9]  INACTOUT  = 1 (inactive output set to high)
+	// [8]  FPOUT     = 1 (first phase output set to high)
+	// [7:6] EVTRIG   = 00 (event-triggered mode disabled)
+	// [5:4] MODE     = 10 (continuous mode)
+	// [3]   INTEN    = 1 (interrupt enabled)
+	// [2]   CFG_UPDATE = 0 (do not wait for configuration update)
+	// [1]   SOFT_RST = 0 (software reset disabled)
+	// [0]   START    = 0 (PWM start coding enable, rising edge effective)
+	// Final address: 0xffec01c000 + 0x00 (channel 0) + 0x00 (control register offset) = 0xffec01c000
+	writel(0b1100101000, PWM_CHAN_REG(0, PWM_CTRL_OFFSET));
+}
+
+static void lpi4a_fan_pwm_config(void)
+{
+	/*
+	 * Enable fan on PWM1(GPIO10) for Lichee Pi 4A.
+	 * See LPi4A Schematic:
+	 * https://dl.sipeed.com/shareURL/LICHEE/licheepi4a/02_Schematic
+	*/
+	// Set PWM Period to 1200 clock cycles
+	writel(0x4b0, PWM_CHAN_REG(1, PWM_PER_OFFSET));
+	// Set PWM First Phase to 600 clock cycles
+	writel(0x258, PWM_CHAN_REG(1, PWM_FP_OFFSET));
+	// Configure PWM Control Register:
+	// [9]  INACTOUT  = 1 (inactive output set to high)
+	// [8]  FPOUT     = 1 (first phase output set to high)
+	// [7:6] EVTRIG   = 00 (event-triggered mode disabled)
+	// [5:4] MODE     = 10 (continuous mode)
+	// [3]   INTEN    = 0 (interrupt disabled)
+	// [2]   CFG_UPDATE = 0 (do not wait for configuration update)
+	// [1]   SOFT_RST = 0 (software reset disabled)
+	// [0]   START    = 0 (PWM start coding enable, rising edge effective)
+	// Final address: 0xffec01c000 + 0x20 (channel 1) + 0x00 (control register offset) = 0xffec01c020
+	writel(0b1100100000, PWM_CHAN_REG(1, PWM_CTRL_OFFSET));
 }
 
 int board_init(void)
@@ -2417,6 +2471,9 @@ int board_init(void)
 
 	light_pwm_config();
 
+#ifdef CONFIG_TARGET_LIGHT_FM_C910_LPI4A
+	lpi4a_fan_pwm_config();
+#endif
 	return 0;
 }
 
@@ -2525,3 +2582,208 @@ U_BOOT_CMD(
 	"check ethaddrs in environment variables is valid",
 	""
 );
+
+
+#define PAGE_SIZE 4096
+#define HIBERNATE_SIG	"S1SUSPEND"
+#define HIBERNATE_SIG2	"S1SUSPEN2" //sign for 2nd time load image
+
+static inline int fdt_disabled_node(void *blob,const char *path)
+{
+	int offset;
+	offset = fdt_path_offset(blob,path);
+	if (offset < 0) {
+		printf("ERROR:failed to find %s node in dtb (ret %d)\n",path,offset);
+		return offset;
+	}
+	return fdt_status_disabled(blob,offset);
+}
+
+static int do_board_check_hibernate(cmd_tbl_t *cmdtp, int flag, int argc,
+		       char * const argv[])
+{
+	int ret;
+	char runcmd[128];
+	ulong addr;
+	void *blob = NULL;
+	ulong mask = 0;
+	int mmc_parts;
+	int resume_part;
+	bool fastresume = 0;
+	#define ON_RET_ERROR(str) if(ret < 0) printf("set node %s status failed %d\n",str,ret)
+	ALLOC_CACHE_ALIGN_BUFFER(u8,swsusp_header_buf,PAGE_SIZE);
+	u8 *header = &swsusp_header_buf[0];
+
+	mmc_parts = env_get_hex("mmcpart",3);
+	resume_part = mmc_parts - 2;
+
+	if(argc >= 4) { // is user pass in ,use that
+		sprintf(runcmd, "read %s %s %s 0 8",
+			argv[1],argv[2],argv[3]);
+		header = (u8 *)simple_strtoul(argv[3],NULL,16);
+		if(argc >= 5)
+			mask = simple_strtoul(argv[4],NULL,16);
+		printf("read swsusp_header to %p,dtb disbale mask 0x%lx\n",header,mask);
+	} else {
+		sprintf(runcmd, "read mmc 0:%d 0x%lx 0 8",
+			resume_part,(unsigned long)&header[0]);
+	}
+
+	ret = run_command(runcmd, 0);
+	if(ret != CMD_RET_SUCCESS)
+		goto failed;
+	if(!memcmp(HIBERNATE_SIG, &header[PAGE_SIZE-10], 10) ||
+		!memcmp(HIBERNATE_SIG2, &header[PAGE_SIZE-10], 10) ) {
+		printf("found sign\n");
+	}
+	else {
+		sprintf(runcmd, "0:%s",env_get("mmcbootpart"));
+		if(file_exists("mmc",runcmd,"no_fastresume",FS_TYPE_EXT)) {
+			printf("do not fastresume\n");
+			goto default_set;
+		}
+
+		sprintf(runcmd, "read mmc 0:%d 0x%lx 0 8",
+			resume_part+1,(unsigned long)&header[0]);
+		ret = run_command(runcmd, 0);
+		if(ret != CMD_RET_SUCCESS)
+			goto failed;
+		if(!memcmp(HIBERNATE_SIG, &header[PAGE_SIZE-10], 10) ||
+			!memcmp(HIBERNATE_SIG2, &header[PAGE_SIZE-10], 10) ) {
+			printf("found fastresume sign\n");
+			resume_part = resume_part+1;
+			fastresume = true;
+		}
+		else {
+			printf(" not find hibernate sign\n");
+			goto default_set;
+		}
+	}
+
+	/*get dtb address*/
+	if(env_get("dtb_addr") == NULL)
+	{
+		printf("Cannot get dtb_addr,check flow !\n");
+		goto failed;
+	}
+	addr = env_get_hex("dtb_addr",0);
+	sprintf(runcmd, "fdt addr 0x%lx", env_get_hex("dtb_addr",0));
+	ret = run_command(runcmd, 0);
+	if(ret != CMD_RET_SUCCESS)
+		goto failed;
+	sprintf(runcmd, "fdt resize");
+	ret = run_command(runcmd, 0);
+	if(ret != CMD_RET_SUCCESS)
+		goto failed;
+
+	/*set unneed devices node disabled for hibernate resume in kernel dtb*/
+	blob = (void *)addr;
+	ret = fdt_status_disabled_by_alias(blob,"i2c0");
+	ON_RET_ERROR("i2c0");
+	ret = fdt_status_disabled_by_alias(blob,"i2c1");
+	ON_RET_ERROR("i2c1");
+	ret = fdt_status_disabled_by_alias(blob,"i2c2");
+	ON_RET_ERROR("i2c2");
+
+	ret = fdt_status_disabled_by_alias(blob,"audio_i2c0");
+	ON_RET_ERROR("audio_i2c0");
+	ret = fdt_status_disabled_by_alias(blob,"audio_i2c1");
+	ON_RET_ERROR("audio_i2c1");
+	ret = fdt_status_disabled_by_alias(blob,"ethernet0");
+	ON_RET_ERROR("ethernet0");
+	ret = fdt_status_disabled_by_alias(blob,"ethernet1");
+	ON_RET_ERROR("ethernet1");
+	ret = fdt_status_disabled_by_alias(blob,"spi0");
+	ON_RET_ERROR("spi0");
+	ret = fdt_status_disabled_by_alias(blob,"spi1");
+	ON_RET_ERROR("spi1");
+	ret = fdt_status_disabled_by_alias(blob,"spi2");
+	ON_RET_ERROR("spi2");
+
+	ret = fdt_disabled_node(blob,"/soc/adc");
+	ON_RET_ERROR("/soc/adc");
+
+	//default mask is 0, need set this node disbaled
+	if(0 == (mask & 0x01)) {
+		ret = fdt_disabled_node(blob,"/soc/light_i2s");
+		ON_RET_ERROR("/soc/light_i2s");
+		ret = fdt_disabled_node(blob,"/soc/audio_i2s0");
+		ON_RET_ERROR("/soc/audio_i2s0");
+		ret = fdt_disabled_node(blob,"/soc/audio_i2s1");
+		ON_RET_ERROR("/soc/audio_i2s1");
+		ret = fdt_disabled_node(blob,"/soc/audio_i2s2");
+		ON_RET_ERROR("/soc/audio_i2s2");
+	}
+	if(0 == (mask & 0x02)) {
+		ret = fdt_disabled_node(blob,"/soc/audio_i2s_8ch_sd0");
+		ON_RET_ERROR("/soc/audio_i2s_8ch_sd0");
+		ret = fdt_disabled_node(blob,"/soc/audio_i2s_8ch_sd1");
+		ON_RET_ERROR("/soc/audio_i2s_8ch_sd1");
+		ret = fdt_disabled_node(blob,"/soc/audio_i2s_8ch_sd2");
+		ON_RET_ERROR("/soc/audio_i2s_8ch_sd2");
+		ret = fdt_disabled_node(blob,"/soc/audio_i2s_8ch_sd3");
+		ON_RET_ERROR("/soc/audio_i2s_8ch_sd3");
+	}
+	/*set resume_bootargs for kernel do fast bootup */
+	sprintf(runcmd,"resume=/dev/mmcblk0p%d notrace noftrace nopty noclkdebug ",resume_part);
+	env_set("resume_bootargs",runcmd);
+
+	return CMD_RET_SUCCESS;
+
+default_set:
+	sprintf(runcmd,"resume=/dev/mmcblk0p%d",resume_part);
+	env_set("resume_bootargs",runcmd);
+	return CMD_RET_SUCCESS;
+
+failed:
+	printf("ERROR:runcmd %s failed!\n",runcmd);
+	sprintf(runcmd,"resume=/dev/mmcblk0p%d",resume_part);
+	env_set("resume_bootargs",runcmd);
+	return CMD_RET_FAILURE;
+}
+
+U_BOOT_CMD(
+	chk_hibernate, 6, 0,	do_board_check_hibernate,
+	"check hibernate image sign,if valid set dtb nodes and bootargs for fast boot resume",
+	" [<interface> <dev[:part]>] [mask]"
+);
+
+#ifdef CONFIG_FIXUP_MEMORY_REGION
+static int do_fixup_memory_region(cmd_tbl_t *cmdtp, int flag, int argc,
+		       char * const argv[])
+{
+	ulong addr;
+	void *blob = NULL;
+	DECLARE_GLOBAL_DATA_PTR;
+	u64 base, size;
+
+	base = gd->ram_base;
+	size = gd->ram_size;
+
+	/*get dtb address*/
+	if(env_get("dtb_addr") == NULL)
+	{
+		printf("Cannot get dtb_addr,check flow !\n");
+		return CMD_RET_FAILURE;
+	}
+	addr = env_get_hex("dtb_addr",0);
+
+	/*set unneed devices node disabled for hibernate resume in kernel dtb*/
+	blob = (void *)addr;
+	fdtdec_setup_mem_size_base_fdt(blob);
+	size -= gd->ram_base;
+
+	if (size != gd->ram_size) {
+		printf("fixup memory region from [0x%09lx ~ 0x%09lx] to [0x%09lx ~ 0x%09lx]\n",
+				gd->ram_base, gd->ram_base+gd->ram_size, gd->ram_base, gd->ram_base+size);
+		gd->ram_size = size;
+		fdt_fixup_memory(blob, gd->ram_base, gd->ram_size);
+	}
+	return CMD_RET_SUCCESS;
+}
+U_BOOT_CMD(
+	fixup_memory_region, 2, 0,	do_fixup_memory_region,
+	"modify linux memory region via gd->ram_size",
+	""
+);
+#endif

board/thead/light-c910/lpddr-regu/ddr_regu.c

@@ -794,7 +794,7 @@ static void light_iopmp_config(void)
 	}
 }
 
-int pmic_ddr_regu_init(void)
+int aon_local_init(void)
 {
 #define AON_PADMUX_BASE (0xfffff4a000)
 	int ret;

board/thead/light-c910/lpddr-regu/ddr_regu.h

@@ -9,5 +9,5 @@
 #define __DDR_REGU_H__
 
 int pmic_ddr_set_voltage(void);
-int pmic_ddr_regu_init(void);
+int aon_local_init(void);
 #endif

board/thead/light-c910/lpddr4/include/aonsys_reg_define.h

@@ -0,0 +1,218 @@
+//------------------------------------------------------------
+// DONOT MODIFY THIS FILE
+// generated by JISHENGJU automatically
+//------------------------------------------------------------
+
+#ifndef AONSYS_SYSREG_REG_OFFSET_DEFINE_H
+#define AONSYS_SYSREG_REG_OFFSET_DEFINE_H
+
+#define AONSYS_REG_BASE			0xFFFFF48000
+
+#define REG_AON_CPU_LP_MODE         (AONSYS_REG_BASE + 0x0  )
+#define REG_AON_CHIP_LP_MODE        (AONSYS_REG_BASE + 0x4  )
+#define REG_AON_AO_SERAM_TRN        (AONSYS_REG_BASE + 0x10 )
+#define REG_AON_AO_SERAM_INT        (AONSYS_REG_BASE + 0x14 )
+#define REG_AON_STR_SERAM_TRN       (AONSYS_REG_BASE + 0x18 )
+#define REG_AON_STR_SERAM_INT       (AONSYS_REG_BASE + 0x1c )
+#define REG_AON_STR_INDICATOR_0     (AONSYS_REG_BASE + 0x20 )
+#define REG_AON_STR_INDICATOR_1     (AONSYS_REG_BASE + 0x24 )
+#define REG_AON_STR_INDICATOR_2     (AONSYS_REG_BASE + 0x28 )
+#define REG_AON_STR_INDICATOR_3     (AONSYS_REG_BASE + 0x2c )
+#define REG_AON_PVTC_WR_LOCK        (AONSYS_REG_BASE + 0x30 )
+#define REG_AON_PVTC_TS_ALARM       (AONSYS_REG_BASE + 0x34 )
+#define REG_AON_PVTC_VM_ALARM       (AONSYS_REG_BASE + 0x38 )
+#define REG_AON_PVTC_PD_ALARM       (AONSYS_REG_BASE + 0x3c )
+#define REG_AON_E902_CNT_CLR        (AONSYS_REG_BASE + 0x40 )
+#define REG_AON_E902_RST_ADDR       (AONSYS_REG_BASE + 0x44 )
+#define REG_AON_C906_RST_ADDR_L     (AONSYS_REG_BASE + 0x48 )
+#define REG_AON_C906_RST_ADDR_H     (AONSYS_REG_BASE + 0x4c )
+#define REG_AON_RESERVED_REG_0      (AONSYS_REG_BASE + 0x50 )
+#define REG_AON_RESERVED_REG_1      (AONSYS_REG_BASE + 0x54 )
+#define REG_AON_RESERVED_REG_2      (AONSYS_REG_BASE + 0x58 )
+#define REG_AON_RESERVED_REG_3      (AONSYS_REG_BASE + 0x5c )
+#define REG_AON_AON_AHB_ADEXT       (AONSYS_REG_BASE + 0x60 )
+#define REG_AON_RC_EN               (AONSYS_REG_BASE + 0x70 )
+#define REG_AON_RC_FCAL             (AONSYS_REG_BASE + 0x74 )
+#define REG_AON_RC_MODE             (AONSYS_REG_BASE + 0x78 )
+#define REG_AON_RC_READY            (AONSYS_REG_BASE + 0x7c )
+#define REG_AON_ISO_CFG             (AONSYS_REG_BASE + 0x80 )
+#define REG_AON_OCRAM_ERR           (AONSYS_REG_BASE + 0x90 )
+#define REG_AON_TIMER_LINK          (AONSYS_REG_BASE + 0x100)
+#define REG_AON_PD_REQ              (AONSYS_REG_BASE + 0x110)
+#define REG_AON_PD_ISO_EN_SET       (AONSYS_REG_BASE + 0x114)
+#define REG_AON_PD_ISO_EN_CLR       (AONSYS_REG_BASE + 0x118)
+#define REG_AON_PD_SW_EN_SET        (AONSYS_REG_BASE + 0x11c)
+#define REG_AON_PD_SW_EN_CLR        (AONSYS_REG_BASE + 0x120)
+#define REG_AON_PD_SW_ACK           (AONSYS_REG_BASE + 0x124)
+#define REG_AON_PD_SW_CNT_EN        (AONSYS_REG_BASE + 0x128)
+#define REG_AON_PD_FSM_RST          (AONSYS_REG_BASE + 0x12c)
+#define REG_AON_PD_INT_MASK         (AONSYS_REG_BASE + 0x130)
+#define REG_AON_PD_FSM_STS_L        (AONSYS_REG_BASE + 0x134)
+#define REG_AON_PD_FSM_STS_H        (AONSYS_REG_BASE + 0x138)
+#define REG_AON_PD_INT_STS          (AONSYS_REG_BASE + 0x13c)
+#define REG_AON_PD_INT_CLR          (AONSYS_REG_BASE + 0x140)
+#define REG_AON_PD_BLK0_SW_CNT      (AONSYS_REG_BASE + 0x144)
+#define REG_AON_PD_BLK1_SW_CNT      (AONSYS_REG_BASE + 0x148)
+#define REG_AON_PD_BLK2_SW_CNT      (AONSYS_REG_BASE + 0x14c)
+#define REG_AON_PD_BLK3_SW_CNT      (AONSYS_REG_BASE + 0x150)
+#define REG_AON_PD_BLK4_SW_CNT      (AONSYS_REG_BASE + 0x154)
+#define REG_AON_PD_BLK5_SW_CNT      (AONSYS_REG_BASE + 0x158)
+#define REG_AON_PD_BLK6_SW_CNT      (AONSYS_REG_BASE + 0x15c)
+#define REG_AON_PD_BLK7_SW_CNT      (AONSYS_REG_BASE + 0x160)
+#define REG_AON_PD_BLK8_SW_CNT      (AONSYS_REG_BASE + 0x164)
+#define REG_AON_PD_BLK9_SW_CNT      (AONSYS_REG_BASE + 0x168)
+#define REG_AON_PD_BLK10_SW_CNT     (AONSYS_REG_BASE + 0x16c)
+#define REG_AON_PD_BLK0_INTV_CNT    (AONSYS_REG_BASE + 0x180)
+#define REG_AON_PD_BLK1_INTV_CNT    (AONSYS_REG_BASE + 0x184)
+#define REG_AON_PD_BLK2_INTV_CNT    (AONSYS_REG_BASE + 0x188)
+#define REG_AON_PD_BLK3_INTV_CNT    (AONSYS_REG_BASE + 0x18c)
+#define REG_AON_PD_BLK4_INTV_CNT    (AONSYS_REG_BASE + 0x190)
+#define REG_AON_PD_BLK5_INTV_CNT    (AONSYS_REG_BASE + 0x194)
+#define REG_AON_PD_BLK6_INTV_CNT    (AONSYS_REG_BASE + 0x198)
+#define REG_AON_PD_BLK7_INTV_CNT    (AONSYS_REG_BASE + 0x19c)
+#define REG_AON_PD_BLK8_INTV_CNT    (AONSYS_REG_BASE + 0x1a0)
+#define REG_AON_PD_BLK9_INTV_CNT    (AONSYS_REG_BASE + 0x1a4)
+#define REG_AON_PD_BLK10_INTV_CNT   (AONSYS_REG_BASE + 0x1a8)
+#define REG_AON_AUDIO_PMU_REQ       (AONSYS_REG_BASE + 0x1f8)
+#define REG_AON_AUDIO_PMU_STS       (AONSYS_REG_BASE + 0x1fc)
+#define REG_AON_AUDIO_PMU_INTR      (AONSYS_REG_BASE + 0x204)
+#define REG_AON_PMU_AUDIO_REQ       (AONSYS_REG_BASE + 0x208)
+#define REG_AON_PMU_AUDIO_STS       (AONSYS_REG_BASE + 0x20c)
+#define REG_AON_MEM_LP_MODE         (AONSYS_REG_BASE + 0x210)
+#define REG_AON_C910_DBG_MASK       (AONSYS_REG_BASE + 0x214)
+#define REG_AON_C910_L2CACHE        (AONSYS_REG_BASE + 0x218)
+#define REG_AON_BISR_CTRL           (AONSYS_REG_BASE + 0x220)
+#define REG_AON_EFUSE_PRELOAD_DONE  (AONSYS_REG_BASE + 0x224)
+#define REG_AON_GPIO_RTE            (AONSYS_REG_BASE + 0x228)
+#define REG_AON_PLL_DSKEW_LOCK      (AONSYS_REG_BASE + 0x22c)
+#define REG_AON_SRAM_AXI_CFG        (AONSYS_REG_BASE + 0x230)
+#define REG_AON_SRAM_AXI_ST         (AONSYS_REG_BASE + 0x234)
+#define REG_AON_SRAM_AXI_ERR_STS_0  (AONSYS_REG_BASE + 0x238)
+#define REG_AON_SRAM_AXI_ERR_STS_1  (AONSYS_REG_BASE + 0x23c)
+#define REG_AON_SRAM_AXI_ERR_STS_2  (AONSYS_REG_BASE + 0x240)
+#define REG_AON_SRAM_AXI_ERR_STS_3  (AONSYS_REG_BASE + 0x244)
+#define REG_AON_SRAM_AXI_ERR_STS_4  (AONSYS_REG_BASE + 0x248)
+#define REG_AON_SE_MUX_LOCK         (AONSYS_REG_BASE + 0x24c)
+#define REG_AON_CPU_DBG_DIS_LOCK    (AONSYS_REG_BASE + 0x270)
+#define REG_AON_RESERVED_REG_4      (AONSYS_REG_BASE + 0x300)
+#define REG_AON_RESERVED_REG_5      (AONSYS_REG_BASE + 0x304)
+#define REG_AON_RESERVED_REG_6      (AONSYS_REG_BASE + 0x308)
+#define REG_AON_RESERVED_REG_7      (AONSYS_REG_BASE + 0x30c)
+#define REG_AON_RESERVED_REG_8      (AONSYS_REG_BASE + 0x400)
+#define REG_AON_RESERVED_REG_9      (AONSYS_REG_BASE + 0x404)
+#define REG_AON_RESERVED_REG_10     (AONSYS_REG_BASE + 0x408)
+#define REG_AON_RESERVED_REG_11     (AONSYS_REG_BASE + 0x40c)
+#define REG_AON_RESERVED_REG_12     (AONSYS_REG_BASE + 0x500)
+#define REG_AON_RESERVED_REG_13     (AONSYS_REG_BASE + 0x504)
+#define REG_AON_RESERVED_REG_14     (AONSYS_REG_BASE + 0x508)
+#define REG_AON_RESERVED_REG_15     (AONSYS_REG_BASE + 0x50c)
+#define REG_AON_RESERVED_REG_16     (AONSYS_REG_BASE + 0x600)
+#define REG_AON_RESERVED_REG_17     (AONSYS_REG_BASE + 0x604)
+#define REG_AON_RESERVED_REG_18     (AONSYS_REG_BASE + 0x608)
+#define REG_AON_RESERVED_REG_19     (AONSYS_REG_BASE + 0x60c)
+
+#define CPU_LP_MODE_DFLT_VAL          0x3ff
+#define CHIP_LP_MODE_DFLT_VAL         0x0
+#define AO_SERAM_TRN_DFLT_VAL         0x0
+#define AO_SERAM_INT_DFLT_VAL         0x0
+#define STR_SERAM_TRN_DFLT_VAL        0x0
+#define STR_SERAM_INT_DFLT_VAL        0x0
+#define STR_INDICATOR_0_DFLT_VAL      0x0
+#define STR_INDICATOR_1_DFLT_VAL      0x0
+#define STR_INDICATOR_2_DFLT_VAL      0x0
+#define STR_INDICATOR_3_DFLT_VAL      0x0
+#define PVTC_WR_LOCK_DFLT_VAL         0x0
+#define PVTC_TS_ALARM_DFLT_VAL        0x0
+#define PVTC_VM_ALARM_DFLT_VAL        0x0
+#define PVTC_PD_ALARM_DFLT_VAL        0x0
+#define E902_CNT_CLR_DFLT_VAL         0x0
+#define E902_RST_ADDR_DFLT_VAL        0xffef8000
+#define C906_RST_ADDR_L_DFLT_VAL      0xc0000000
+#define C906_RST_ADDR_H_DFLT_VAL      0xff
+#define RESERVED_REG_0_DFLT_VAL       0x0
+#define RESERVED_REG_1_DFLT_VAL       0x0
+#define RESERVED_REG_2_DFLT_VAL       0x0
+#define RESERVED_REG_3_DFLT_VAL       0x0
+#define AON_AHB_ADEXT_DFLT_VAL        0x0
+#define RC_EN_DFLT_VAL                0x1
+#define RC_FCAL_DFLT_VAL              0x77f
+#define RC_MODE_DFLT_VAL              0x1
+#define RC_READY_DFLT_VAL             0x0
+#define ISO_CFG_DFLT_VAL              0x0
+#define OCRAM_ERR_DFLT_VAL            0x0
+#define TIMER_LINK_DFLT_VAL           0x0
+#define PD_REQ_DFLT_VAL               0x0
+#define PD_ISO_EN_SET_DFLT_VAL        0x0
+#define PD_ISO_EN_CLR_DFLT_VAL        0x0
+#define PD_SW_EN_SET_DFLT_VAL         0x0
+#define PD_SW_EN_CLR_DFLT_VAL         0x0
+#define PD_SW_ACK_DFLT_VAL            0x3fffff
+#define PD_SW_CNT_EN_DFLT_VAL         0x0
+#define PD_FSM_RST_DFLT_VAL           0x0
+#define PD_INT_MASK_DFLT_VAL          0x3fffff
+#define PD_FSM_STS_L_DFLT_VAL         0x0
+#define PD_FSM_STS_H_DFLT_VAL         0x0
+#define PD_INT_STS_DFLT_VAL           0x0
+#define PD_INT_CLR_DFLT_VAL           0x0
+#define PD_BLK0_SW_CNT_DFLT_VAL       0xff00ff
+#define PD_BLK1_SW_CNT_DFLT_VAL       0xff00ff
+#define PD_BLK2_SW_CNT_DFLT_VAL       0xff00ff
+#define PD_BLK3_SW_CNT_DFLT_VAL       0xff00ff
+#define PD_BLK4_SW_CNT_DFLT_VAL       0xff00ff
+#define PD_BLK5_SW_CNT_DFLT_VAL       0xff00ff
+#define PD_BLK6_SW_CNT_DFLT_VAL       0xff00ff
+#define PD_BLK7_SW_CNT_DFLT_VAL       0xff00ff
+#define PD_BLK8_SW_CNT_DFLT_VAL       0xff00ff
+#define PD_BLK9_SW_CNT_DFLT_VAL       0xff00ff
+#define PD_BLK10_SW_CNT_DFLT_VAL      0xff00ff
+#define PD_BLK0_INTV_CNT_DFLT_VAL     0xff0ffff
+#define PD_BLK1_INTV_CNT_DFLT_VAL     0xff0ffff
+#define PD_BLK2_INTV_CNT_DFLT_VAL     0xff0ffff
+#define PD_BLK3_INTV_CNT_DFLT_VAL     0xff0ffff
+#define PD_BLK4_INTV_CNT_DFLT_VAL     0xff0ffff
+#define PD_BLK5_INTV_CNT_DFLT_VAL     0xff0ffff
+#define PD_BLK6_INTV_CNT_DFLT_VAL     0xff0ffff
+#define PD_BLK7_INTV_CNT_DFLT_VAL     0xff0ffff
+#define PD_BLK8_INTV_CNT_DFLT_VAL     0xff0ffff
+#define PD_BLK9_INTV_CNT_DFLT_VAL     0xff0ffff
+#define PD_BLK10_INTV_CNT_DFLT_VAL    0xff0ffff
+#define AUDIO_PMU_REQ_DFLT_VAL        0x0
+#define AUDIO_PMU_STS_DFLT_VAL        0x0
+#define AUDIO_PMU_INTR_DFLT_VAL       0x0
+#define PMU_AUDIO_REQ_DFLT_VAL        0x0
+#define PMU_AUDIO_STS_DFLT_VAL        0x0
+#define MEM_LP_MODE_DFLT_VAL          0x0
+#define C910_DBG_MASK_DFLT_VAL        0x0
+#define C910_L2CACHE_DFLT_VAL         0x0
+#define BISR_CTRL_DFLT_VAL            0x0
+#define EFUSE_PRELOAD_DONE_DFLT_VAL   0x0
+#define GPIO_RTE_DFLT_VAL             0x0
+#define PLL_DSKEW_LOCK_DFLT_VAL       0x0
+#define SRAM_AXI_CFG_DFLT_VAL         0x0
+#define SRAM_AXI_ST_DFLT_VAL          0x0
+#define SRAM_AXI_ERR_STS_0_DFLT_VAL   0x0
+#define SRAM_AXI_ERR_STS_1_DFLT_VAL   0x0
+#define SRAM_AXI_ERR_STS_2_DFLT_VAL   0x0
+#define SRAM_AXI_ERR_STS_3_DFLT_VAL   0x0
+#define SRAM_AXI_ERR_STS_4_DFLT_VAL   0x0
+#define SE_MUX_LOCK_DFLT_VAL          0x0
+#define CPU_DBG_DIS_LOCK_DFLT_VAL     0x0
+#define RESERVED_REG_4_DFLT_VAL       0x0
+#define RESERVED_REG_5_DFLT_VAL       0x0
+#define RESERVED_REG_6_DFLT_VAL       0x0
+#define RESERVED_REG_7_DFLT_VAL       0x0
+#define RESERVED_REG_8_DFLT_VAL       0x0
+#define RESERVED_REG_9_DFLT_VAL       0x0
+#define RESERVED_REG_10_DFLT_VAL      0x0
+#define RESERVED_REG_11_DFLT_VAL      0x0
+#define RESERVED_REG_12_DFLT_VAL      0x0
+#define RESERVED_REG_13_DFLT_VAL      0x0
+#define RESERVED_REG_14_DFLT_VAL      0x0
+#define RESERVED_REG_15_DFLT_VAL      0x0
+#define RESERVED_REG_16_DFLT_VAL      0x0
+#define RESERVED_REG_17_DFLT_VAL      0x0
+#define RESERVED_REG_18_DFLT_VAL      0x0
+#define RESERVED_REG_19_DFLT_VAL      0x0
+
+
+#endif

board/thead/light-c910/lpddr4/include/aonsys_rstget_reg_define.h

@@ -0,0 +1,90 @@
+//------------------------------------------------------------
+// DONOT MODIFY THIS FILE
+// generated by JISHENGJU automatically
+//------------------------------------------------------------
+
+#ifndef AONSYS_RSTGEN_REG_OFFSET_DEFINE_H
+#define AONSYS_RSTGEN_REG_OFFSET_DEFINE_H
+
+#define AONSYS_RSTGEN_REG_BASE	0xFFFFF44000
+
+#define REG_AON_RST_CNT             (AONSYS_RSTGEN_REG_BASE + 0x0   )
+#define REG_AON_SYS_RST_CFG         (AONSYS_RSTGEN_REG_BASE + 0x10  )
+#define REG_AON_RTC_RST_CFG         (AONSYS_RSTGEN_REG_BASE + 0x14  )
+#define REG_AON_AOGPIO_RST_CFG      (AONSYS_RSTGEN_REG_BASE + 0x18  )
+#define REG_AON_AOI2C_RST_CFG       (AONSYS_RSTGEN_REG_BASE + 0x1c  )
+#define REG_AON_PVTC_RST_CFG        (AONSYS_RSTGEN_REG_BASE + 0x20  )
+#define REG_AON_E902_RST_CFG        (AONSYS_RSTGEN_REG_BASE + 0x24  )
+#define REG_AON_AOTIMER_RST_CFG     (AONSYS_RSTGEN_REG_BASE + 0x28  )
+#define REG_AON_AOWDT_RST_CFG       (AONSYS_RSTGEN_REG_BASE + 0x2c  )
+#define REG_AON_APSYS_RST_CFG       (AONSYS_RSTGEN_REG_BASE + 0x30  )
+#define REG_AON_NPUSYS_RST_CFG      (AONSYS_RSTGEN_REG_BASE + 0x34  )
+#define REG_AON_DDRSYS_RST_CFG      (AONSYS_RSTGEN_REG_BASE + 0x38  )
+#define REG_AON_AUDIO_RST_CFG       (AONSYS_RSTGEN_REG_BASE + 0x3c  )
+#define REG_AON_BISR_RST_CFG        (AONSYS_RSTGEN_REG_BASE + 0x50  )
+#define REG_AON_DSP0_RST_CFG        (AONSYS_RSTGEN_REG_BASE + 0x54  )
+#define REG_AON_DSP1_RST_CFG        (AONSYS_RSTGEN_REG_BASE + 0x58  )
+#define REG_AON_GPU_RST_CFG         (AONSYS_RSTGEN_REG_BASE + 0x5c  )
+#define REG_AON_VDEC_RST_CFG        (AONSYS_RSTGEN_REG_BASE + 0x60  )
+#define REG_AON_VENC_RST_CFG        (AONSYS_RSTGEN_REG_BASE + 0x64  )
+#define REG_AON_ADC_RST_CFG         (AONSYS_RSTGEN_REG_BASE + 0x70  )
+#define REG_AON_AUDGPIO_RST_CFG     (AONSYS_RSTGEN_REG_BASE + 0x74  )
+#define REG_AON_AOUART_RST_CFG      (AONSYS_RSTGEN_REG_BASE + 0x78  )
+#define REG_AON_RST_CLR_0           (AONSYS_RSTGEN_REG_BASE + 0x100 )
+#define REG_AON_RST_CLR_1           (AONSYS_RSTGEN_REG_BASE + 0x104 )
+#define REG_AON_RST_CLR_2           (AONSYS_RSTGEN_REG_BASE + 0x108 )
+#define REG_AON_RST_CLR_3           (AONSYS_RSTGEN_REG_BASE + 0x10c )
+#define REG_AON_RST_CLR_4           (AONSYS_RSTGEN_REG_BASE + 0x110 )
+#define REG_AON_RST_STS_0           (AONSYS_RSTGEN_REG_BASE + 0x120 )
+#define REG_AON_RST_STS_1           (AONSYS_RSTGEN_REG_BASE + 0x124 )
+#define REG_AON_RST_STS_2           (AONSYS_RSTGEN_REG_BASE + 0x128 )
+#define REG_AON_RST_STS_3           (AONSYS_RSTGEN_REG_BASE + 0x12c )
+#define REG_AON_RST_STS_4           (AONSYS_RSTGEN_REG_BASE + 0x130 )
+#define REG_AON_RST_REQ_EN_0        (AONSYS_RSTGEN_REG_BASE + 0x140 )
+#define REG_AON_RST_REQ_EN_1        (AONSYS_RSTGEN_REG_BASE + 0x144 )
+#define REG_AON_RST_REQ_EN_2        (AONSYS_RSTGEN_REG_BASE + 0x148 )
+#define REG_AON_RST_REQ_EN_3        (AONSYS_RSTGEN_REG_BASE + 0x14c )
+#define REG_AON_SRAM_AXI_RST_CFG    (AONSYS_RSTGEN_REG_BASE + 0x11f4)
+#define REG_AON_SE_RST_CFG          (AONSYS_RSTGEN_REG_BASE + 0x160 )
+
+#define RST_CNT_DFLT_VAL              0xf0f
+#define SYS_RST_CFG_DFLT_VAL          0x0
+#define RTC_RST_CFG_DFLT_VAL          0x3
+#define AOGPIO_RST_CFG_DFLT_VAL       0x3
+#define AOI2C_RST_CFG_DFLT_VAL        0x1
+#define PVTC_RST_CFG_DFLT_VAL         0x1
+#define E902_RST_CFG_DFLT_VAL         0x2
+#define AOTIMER_RST_CFG_DFLT_VAL      0x3
+#define AOWDT_RST_CFG_DFLT_VAL        0x1
+#define APSYS_RST_CFG_DFLT_VAL        0x1
+#define NPUSYS_RST_CFG_DFLT_VAL       0x1
+#define DDRSYS_RST_CFG_DFLT_VAL       0x1
+#define AUDIO_RST_CFG_DFLT_VAL        0x0
+#define BISR_RST_CFG_DFLT_VAL         0x3
+#define DSP0_RST_CFG_DFLT_VAL         0x1
+#define DSP1_RST_CFG_DFLT_VAL         0x1
+#define GPU_RST_CFG_DFLT_VAL          0x1
+#define VDEC_RST_GEN_RST_CFG_DFLT_VAL         0x1
+#define VENC_RST_CFG_DFLT_VAL         0x1
+#define ADC_RST_CFG_DFLT_VAL          0x1
+#define AUDGPIO_RST_CFG_DFLT_VAL      0x3
+#define AOUART_RST_CFG_DFLT_VAL       0x3
+#define RST_CLR_0_DFLT_VAL            0x0
+#define RST_CLR_1_DFLT_VAL            0x0
+#define RST_CLR_2_DFLT_VAL            0x0
+#define RST_CLR_3_DFLT_VAL            0x0
+#define RST_CLR_4_DFLT_VAL            0x0
+#define RST_STS_0_DFLT_VAL            0x0
+#define RST_STS_1_DFLT_VAL            0x0
+#define RST_STS_2_DFLT_VAL            0x0
+#define RST_STS_3_DFLT_VAL            0x0
+#define RST_STS_4_DFLT_VAL            0x0
+#define RST_REQ_EN_0_DFLT_VAL         0x11100
+#define RST_REQ_EN_1_DFLT_VAL         0xbb000000
+#define RST_REQ_EN_2_DFLT_VAL         0x0
+#define RST_REQ_EN_3_DFLT_VAL         0x0
+#define SRAM_AXI_RST_CFG_DFLT_VAL     0x5f
+#define SE_RST_CFG_DFLT_VAL           0x1
+
+
+#endif

board/thead/light-c910/lpddr4/include/common_lib.h

@@ -7,6 +7,8 @@
 #include "ddr_reg_define.h"
 #include "ddr_sysreg_registers_struct.h"
 #include "ddr_sysreg_registers.h"
+#include "aonsys_reg_define.h"
+#include "aonsys_rstget_reg_define.h"
 #include "define_ddr.h"
 #include "DWC_ddr_umctl2_c_struct.h"
 #include "DWC_ddr_umctl2_header.h"

board/thead/light-c910/lpddr4/include/ddr_common_func.h

@@ -15,6 +15,9 @@ enum DDR_BITWIDTH {
 
 unsigned long get_ddr_density(void);
 enum DDR_TYPE get_ddr_type(void);
+int get_ddr_rank_number(void);
+int get_ddr_freq(void);
+enum DDR_BITWIDTH get_ddr_bitwidth(void);
 void ddr_sysreg_wr(unsigned long int addr,unsigned int wr_data);
 unsigned int ddr_sysreg_rd(unsigned long int addr);
 
@@ -49,4 +52,8 @@ void addrmap(int rank_num, enum DDR_BITWIDTH bits);
 void ctrl_en(enum DDR_BITWIDTH bits);
 void enable_auto_refresh(void);
 void lpddr4_auto_selref(void);
+int lpddr4_query_boundary(enum DDR_TYPE type, int rank_num, int speed,
+                    enum DDR_BITWIDTH bits, unsigned long size);
+int lpddr4_reinit_ctrl(enum DDR_TYPE type, int rank_num, int speed,
+                    enum DDR_BITWIDTH bits, unsigned long size);
 #endif // DDR_COMMON_FUNCE_H

board/thead/light-c910/lpddr4/include/ddr_retention.h

@@ -0,0 +1,38 @@
+#ifndef DDR_RETENTION_H
+#define DDR_RETENTION_H
+
+///data structure to store ddr misc register address, value
+typedef struct Reg_Misc_Addr_Val {
+  uint32_t Address; ///< register address
+  uint32_t Value;   ///< register value
+} Reg_Misc_Addr_Val_t;
+
+///data structure to store register address, value pairs
+typedef struct Reg_Phy_Addr_Val {
+  uint32_t Address; ///< register address
+  uint16_t Value0;   ///< register value phy0
+  uint16_t Value1;   ///< register value phy1
+} Reg_Phy_Addr_Val_t;
+
+/// enumeration of instructions for PhyInit Register Interface
+typedef enum {
+  saveRegs,         ///< save(read) tracked register values
+  restoreRegs,      ///< restore (write) saved register values
+} regInstr;
+
+// typedef struct Reg_Addr_Value {
+//   uint32_t reg_num;
+//   Reg_Addr_Val_t reg[0];
+// } Reg_Addr_Value_t;
+
+typedef struct Ddr_Reg_Config {
+    uint32_t misc_reg_num;
+    uint32_t phy_reg_num;
+    uint8_t  ddr_rank;
+    uint8_t  reserve[55];
+} Ddr_Reg_Config_t;
+
+int dwc_ddrphy_phyinit_regInterface(regInstr myRegInstr);
+void dwc_ddr_misc_regu_save(void);
+
+#endif

board/thead/light-c910/lpddr4/src/ddr_common_func.c

@@ -2,9 +2,15 @@
 #include <linux/sizes.h>
 #include "../include/common_lib.h"
 #include "../include/ddr_common_func.h"
+#include "../include/ddr_retention.h"
+#include "../include/pinmux.h"
 
 DDR_SYSREG_REG_SW_REG_S ddr_sysreg;
 
+#ifdef CONFIG_DDR_MSG
+#define DDR_DEBUG(x) printf(x)
+#endif
+
 #ifndef CONFIG_DDR_RANK_SIZE
 #define CONFIG_DDR_RANK_SIZE SZ_4G
 #endif
@@ -34,6 +40,44 @@ enum DDR_TYPE get_ddr_type() {
 #endif // #ifdef CONFIG_LPDDR4X
 }
 
+int get_ddr_rank_number() {
+#ifdef CONFIG_DDR_SINGLE_RANK
+	return 1;
+#elif defined CONFIG_DDR_DUAL_RANK
+	return 2;
+#else
+#ifdef CONFIG_DDR_MSG
+	DDR_DEBUG("unsupported ddr rank type!!!\n");
+#endif
+    return 0;
+#endif
+}
+
+int get_ddr_freq() {
+#ifdef CONFIG_DDR_4266
+    return 4266;
+#elif CONFIG_DDR_3733
+    return 3733;
+#elif CONFIG_DDR_3200
+    return 3200;
+#elif CONFIG_DDR_2133
+	return 2133;
+#else
+    printf("unsupport lpddr4 freq!!!\n");
+    return -1;
+#endif
+}
+
+enum DDR_BITWIDTH get_ddr_bitwidth() {
+#ifdef CONFIG_DDR_H32_MODE
+    return DDR_BITWIDTH_32;
+#elif CONFIG_DDR_H16_MODE
+    return DDR_BITWIDTH_16;
+#else
+    return DDR_BITWIDTH_64;
+#endif
+}
+
 void ddr_sysreg_wr(unsigned long int addr,unsigned int wr_data) {
   wr(addr+DDR_SYSREG_BADDR,wr_data);
 }
@@ -104,75 +148,114 @@ unsigned int ddr_phy_reg_rd(unsigned long int addr) {
 
   void lp4_mrw(int addr, int wdata,int dch,int rank) {
   DWC_DDR_UMCTL2_C_STRUCT_REG_S umctl2_reg;
+  uint32_t val_t0,val_t1;
   if(dch==0) {
-  umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32 = rd(MRCTRL0);
-  //umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_addr = addr; //do not care for lp4
-  umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_rank = rank;//rank0 only
-  umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_type = 0;//write
-  wr(MRCTRL0,umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32);
+        while ((rd(MRSTAT) & 0x1) == 0x1);
+        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32 = rd(MRCTRL0);
+        //umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_addr = addr; //do not care for lp4
+        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_rank = rank;//rank0 only
+        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_type = 0;//write
+        wr(MRCTRL0, umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32);
 
-  umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32 = rd(MRCTRL1);
-  umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.mr_data = (addr<<8) | (wdata&0xFF);
-  wr(MRCTRL1,umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32);
-  
-  umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32 = rd(MRCTRL0);
-  umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_wr = 1;//trigger wr/rd
-  wr(MRCTRL0,umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32);
+        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32 = rd(MRCTRL1);
+        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.mr_data = (addr << 8) | (wdata & 0xFF);
+        wr(MRCTRL1, umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32);
+
+        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32 = rd(MRCTRL1);
+        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.mr_data = (addr << 8) | (wdata & 0xFF);
+        wr(MRCTRL1, umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32);
+
+        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32 = rd(MRCTRL0);
+        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_wr = 1;//trigger wr/rd
+        wr(MRCTRL0, umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32);
+
+        //udelay(10);
+        //delay 5us
+        val_t0=rd(0xFFF4D004);
+        val_t1=rd(0xFFF4D004);
+        while((val_t0-val_t1)<200){val_t1=rd(0xFFF4D004);};
+
+        while ((rd(MRSTAT) & 0x1) == 0x1);
   }
   else {
-  umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32 = rd(MRCTRL0_DCH1);
-  //umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_addr = addr; //do not care for lp4
-  umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_rank = rank;//rank0 only
-  umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_type = 0;//write
-  wr(MRCTRL0_DCH1,umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32);
+        while ((rd(MRSTAT_DCH1) & 0x1) == 0x1);
+        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32 = rd(MRCTRL0_DCH1);
+        //umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_addr = addr; //do not care for lp4
+        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_rank = rank;//rank0 only
+        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_type = 0;//write
+        wr(MRCTRL0_DCH1, umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32);
 
-  umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32 = rd(MRCTRL1_DCH1);
-  umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.mr_data = (addr<<8) | (wdata&0xFF);
-  wr(MRCTRL1_DCH1,umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32);
-  
-  umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32 = rd(MRCTRL0_DCH1);
-  umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_wr = 1;//trigger wr/rd
-  wr(MRCTRL0_DCH1,umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32);
-  }
+        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32 = rd(MRCTRL1_DCH1);
+        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.mr_data = (addr << 8) | (wdata & 0xFF);
+        wr(MRCTRL1_DCH1, umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32);
+
+
+        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32 = rd(MRCTRL1_DCH1);
+        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.mr_data = (addr << 8) | (wdata & 0xFF);
+        wr(MRCTRL1_DCH1, umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32);
+
+        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32 = rd(MRCTRL0_DCH1);
+        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_wr = 1;//trigger wr/rd
+        wr(MRCTRL0_DCH1, umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32);
+
+        //udelay(10);
+        //delay 5us
+        val_t0=rd(0xFFF4D004);
+        val_t1=rd(0xFFF4D004);
+        while((val_t0-val_t1)<200){val_t1=rd(0xFFF4D004);};
+        while ((rd(MRSTAT_DCH1) & 0x1) == 0x1);
   }
+}
 
   int lp4_mrr(int addr,int dch,int rank) {
   DWC_DDR_UMCTL2_C_STRUCT_REG_S umctl2_reg;
   if(dch==0) {
-  umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32 = rd(MRCTRL0);
-  //umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_addr = addr; //do not care for lp4
-  umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_rank = rank;//rank0 only
-  umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_type = 1;//read
-  wr(MRCTRL0,umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32);
+        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32 = rd(MRCTRL0);
+        //umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_addr = addr; //do not care for lp4
+        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_rank = rank;//rank0 only
+        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_type = 1;//read
+        wr(MRCTRL0, umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32);
 
-  umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32 = rd(MRCTRL1);
-  umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.mr_data = addr<<8;
-  wr(MRCTRL1,umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32);
-  
-  umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32 = rd(MRCTRL0);
-  umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_wr = 1;//trigger wr/rd
-  wr(MRCTRL0,umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32);
+        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32 = rd(MRCTRL1);
+        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.mr_data = addr << 8;
+        wr(MRCTRL1, umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32);
 
-  umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32 = rd(MRCTRL1);
-  return (umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.mr_data & 0xFF);
+        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32 = rd(MRCTRL1);
+        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.mr_data = addr << 8;
+        wr(MRCTRL1, umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32);
+
+
+        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32 = rd(MRCTRL0);
+        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_wr = 1;//trigger wr/rd
+        wr(MRCTRL0, umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32);
+
+        udelay(20);
+        while ((rd(MRSTAT) & 0x1) == 0x1);
+        return ddr_sysreg_rd(MRR_STS_CH0);
   }
   else {
-  umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32 = rd(MRCTRL0_DCH1);
-  //umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_addr = addr; //do not care for lp4
-  umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_rank = rank;//rank0 only
-  umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_type = 1;//read
-  wr(MRCTRL0_DCH1,umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32);
+        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32 = rd(MRCTRL0_DCH1);
+        //umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_addr = addr; //do not care for lp4
+        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_rank = rank;//rank0 only
+        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_type = 1;//read
+        wr(MRCTRL0_DCH1, umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32);
 
-  umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32 = rd(MRCTRL1_DCH1);
-  umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.mr_data = addr<<8;
-  wr(MRCTRL1_DCH1,umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32);
-  
-  umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32 = rd(MRCTRL0_DCH1);
-  umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_wr = 1;//trigger wr/rd
-  wr(MRCTRL0_DCH1,umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32);
+        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32 = rd(MRCTRL1_DCH1);
+        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.mr_data = addr << 8;
+        wr(MRCTRL1_DCH1, umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32);
 
-  umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32 = rd(MRCTRL1_DCH1);
-  return (umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.mr_data & 0xFF);
+
+        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32 = rd(MRCTRL1_DCH1);
+        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.mr_data = addr << 8;
+        wr(MRCTRL1_DCH1, umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32);
+
+        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32 = rd(MRCTRL0_DCH1);
+        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_wr = 1;//trigger wr/rd
+        wr(MRCTRL0_DCH1, umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32);
+
+        udelay(20);
+        while ((rd(MRSTAT_DCH1) & 0x1) == 0x1);
+        return ddr_sysreg_rd(MRR_STS_CH1);
   }
   }
 
@@ -236,15 +319,15 @@ unsigned int ddr_phy_reg_rd(unsigned long int addr) {
     if(port & 0x4) wr(PCTRL_2,0);
     if(port & 0x8) wr(PCTRL_3,0);
     if(port & 0x10) wr(PCTRL_4,0);
-    if(port & 0x1F) { //at least one port is not disabled
-        wr(DBG1,0);
-        wr(DBG1_DCH1,0);
+    while (rd(PSTAT) != 0x0);
+    if ((port & 0x1F) == 0x1F) { //all ports are disabled
+        wr(DBG1, 2);
+        wr(DBG1_DCH1, 2);
     }
-    else { //all ports are disabled
-        wr(DBG1,3);
-        wr(DBG1_DCH1,3);
+    else { //at least one port is not disabled
+        wr(DBG1, 0);
+        wr(DBG1_DCH1, 0);
     }
-
   }
 
   void enable_axi_port(int port) {
@@ -457,7 +540,7 @@ if(bits==64) {
   wr(DFITMG0,0x05a3820e);//[28:24] dft_t_ctrl_delay [22:16] dfi_t_rddate_en=RL-5
 #endif
   wr(DFITMG1,0x000c0303);
-  wr(DFILPCFG0,0x0351a001);
+  wr(DFILPCFG0,0x0351a101); //[8]=1: enable dfi lp mode during selfref
   //wr(DFIUPD0,0x00400018); //[31:30]=0 use ctrlupd enable
   //wr(DFIUPD1,0x00b700c4);
   //wr(DFIUPD2,0x00000000);//[31]=0 disable phy ctrlupdate
@@ -557,7 +640,7 @@ if(bits==64) {
   wr(DFITMG0,0x059f820c);//[28:24] dfi_t_ctrl_delay
 #endif
   wr(DFITMG1,0x000c0303);//dfi_t_wrdata_delay=tctrl+6+BL/2+trainedTdqsdly=24, may need take care cmd pipe
-  wr(DFILPCFG0,0x0351a001);
+  wr(DFILPCFG0,0x0351a101); //[8]=1: enable dfi lp mode during selfref
   //wr(DFIUPD0,0xc0400018);
   //wr(DFIUPD1,0x00b700c4);
   //wr(DFIUPD2,0x80000000);
@@ -645,7 +728,7 @@ if(bits==64) {
   wr(DFITMG0,0x059b820a); //[22:16] dfi_t_rddate_en=RL-5
 #endif
   wr(DFITMG1,0x000b0303);
-  wr(DFILPCFG0,0x0351a001);
+  wr(DFILPCFG0,0x0351a101); //[8]=1: enable dfi lp mode during selfref
   //wr(DFIUPD0,0xc0400018);
   //wr(DFIUPD1,0x00b700c4);
   //wr(DFIUPD2,0x80000000);
@@ -730,7 +813,7 @@ if(bits==64) {
   wr(ZQCTL2,0x00000000);
   wr(DFITMG0,0x048f8206);
   wr(DFITMG1,0x000b0303);
-  wr(DFILPCFG0,0x0351a001);
+  wr(DFILPCFG0,0x0351a101); //[8]=1: enable dfi lp mode during selfref
   //wr(DFIUPD0,0xc0400018);
   //wr(DFIUPD1,0x00b700c4);
   //wr(DFIUPD2,0x80000000);
@@ -856,17 +939,28 @@ if(bits==64) {
 #ifdef CONFIG_DDR_MSG
  printf("DDR 32bit mode\n");
 #endif
-  wr(ADDRMAP0,0x001f001f);  //
   if(rank_num==2) {
-  wr(ADDRMAP0,0x001f0017);//4GB
+#ifdef CONFIG_DDR_DDP
+    wr(ADDRMAP0,0x001f0018);//max 8GB
+#else
+    wr(ADDRMAP0,0x001f0017); //4GB
+#endif
+  }
+  else {
+    wr(ADDRMAP0,0x001f001f); //cs_bit0: NULL
   }
   wr(ADDRMAP1,0x00080808); //bank +2
   wr(ADDRMAP2,0x00000000); //col b5+5 ~ col b2  +2
   wr(ADDRMAP3,0x00000000); //col b9 ~ col b6
   wr(ADDRMAP4,0x00001f1f); //col b11~ col b10
   wr(ADDRMAP5,0x070f0707); //row_b11 row b2_10 row b1 row b0  +6
-  wr(ADDRMAP6,0x07070707); //max row 15
-  wr(ADDRMAP7,0x00000f0f);
+  wr(ADDRMAP6,0x07070707); //row 15
+  wr(ADDRMAP7,0x00000f0f); //row16: NULL
+#ifdef CONFIG_DDR_DDP
+  if(rank_num==2) {
+    wr(ADDRMAP7,0x00000f07); //max row16
+  }
+#endif
   wr(ADDRMAP9,0x07070707);
   wr(ADDRMAP10,0x07070707);
   wr(ADDRMAP11,0x00000007);
@@ -874,12 +968,12 @@ if(bits==64) {
 #ifdef CONFIG_DDR_MSG
  printf("DDR 64bit mode, 256B interleaving\n");
 #endif
-  wr(ADDRMAP0,0x0004001f);  // +2
+  wr(ADDRMAP0,0x0004001f); //cs_bit0: NULL
   if(rank_num==2) {
 #ifdef CONFIG_DDR_DDP
-  wr(ADDRMAP0,0x00040019);//16GB
+    wr(ADDRMAP0,0x00040019);//max 16GB
 #else
-  wr(ADDRMAP0,0x00040018);//8GB
+    wr(ADDRMAP0,0x00040018);//8GB
 #endif
   }
   wr(ADDRMAP1,0x00090909); //bank +2
@@ -887,11 +981,11 @@ if(bits==64) {
   wr(ADDRMAP3,0x01010101); //col b9 ~ col b6
   wr(ADDRMAP4,0x00001f1f); //col b11~ col b10
   wr(ADDRMAP5,0x080f0808); //row_b11 row b2_10 row b1 row b0  +6
-  wr(ADDRMAP6,0x08080808);
+  wr(ADDRMAP6,0x08080808); //row15
 #ifdef CONFIG_DDR_DDP
-  wr(ADDRMAP7,0x00000f08);
+  wr(ADDRMAP7,0x00000f08); //row16
 #else
-  wr(ADDRMAP7,0x00000f0f);
+  wr(ADDRMAP7,0x00000f0f); //row16: NULL
 #endif
   wr(ADDRMAP9,0x08080808);
   wr(ADDRMAP10,0x08080808);
@@ -901,6 +995,130 @@ if(bits==64) {
  }
 }
 
+#define MEMSIZE_MIN_MB (2*1024)
+#define MEMSIZE_MAX_MB (16*1024)
+#define UNIT_MB (1024*1024)
+int lpddr4_query_boundary(enum DDR_TYPE type, int rank_num, int speed,
+					enum DDR_BITWIDTH bits, unsigned long size)
+{
+  if ((size < (unsigned long)MEMSIZE_MIN_MB*UNIT_MB) ||
+    (size > (unsigned long)MEMSIZE_MAX_MB*UNIT_MB))
+    goto err_ret;
+
+  if (bits == DDR_BITWIDTH_32) {// only phy0
+    if (rank_num == 2) {
+      if (size == 0x80000000) //2GB
+        goto err_ret;
+      else if (size == 0x100000000) //4GB
+        goto ret_ok;
+      else if (size == 0x200000000) //8GB
+        goto ret_ok;
+      else if (size == 0x400000000) //16GB
+        goto err_ret;
+      else
+        goto err_ret;
+    }
+    else { // single rank
+      if (size == 0x80000000) //2GB
+        goto ret_ok;
+      else if (size == 0x100000000) //4GB
+        goto err_ret;
+      else if (size == 0x200000000) //8GB
+        goto err_ret;
+      else if (size == 0x400000000) //16GB
+        goto err_ret;
+      else
+        goto err_ret;
+    }
+  }
+  else if (bits == DDR_BITWIDTH_64) { // phy0+phy1
+    if (rank_num == 2) {
+      if (size == 0x80000000) //2GB
+        goto err_ret;
+      else if (size == 0x100000000) //4GB
+        goto err_ret;
+      else if (size == 0x200000000) //8GB
+        goto ret_ok;
+      else if (size == 0x400000000) //16GB
+        goto ret_ok;
+      else
+        goto err_ret;
+    }
+    else { // single rank
+      if (size == 0x80000000) //2GB
+        goto err_ret;
+      else if (size == 0x100000000) //4GB
+        goto ret_ok;
+      else if (size == 0x200000000) //8GB
+        goto err_ret;
+      else if (size == 0x400000000) //16GB
+        goto err_ret;
+      else
+        goto err_ret;
+    }
+  }
+  else {
+    goto err_ret;
+  }
+
+ret_ok:
+  return 0;
+
+err_ret:
+  return -1;
+}
+
+int adjust_ddr_addrmap(enum DDR_TYPE type, int rank_num, int speed,
+					enum DDR_BITWIDTH bits, unsigned long size)
+{
+  if (lpddr4_query_boundary(type, rank_num, speed, bits, size) < 0)
+    goto err_ret;
+
+  if (bits == DDR_BITWIDTH_32) {// only phy0
+    if (rank_num == 2) {
+      if (size == 0x100000000) {//4GB
+        wr(ADDRMAP0,0x001f0017); // cs_bit0: HIF[29]
+        wr(ADDRMAP7,0x00000f0f); // row16: NULL
+      }
+      else if (size == 0x200000000) {//8GB
+        wr(ADDRMAP0,0x001f0018); // cs_bit0: HIF[30]
+        wr(ADDRMAP7,0x00000f07); // row16: HIF[29]
+      }
+    }
+	else { // single rank
+      if (size == 0x80000000) //2GB
+        wr(ADDRMAP0,0x001f001f); // cs_bit0: NULL
+    }
+  }
+  else if (bits == DDR_BITWIDTH_64) { // phy0+phy1
+    if (rank_num == 2) {
+      if (size == 0x200000000) {//8GB
+        wr(ADDRMAP0,0x00040018); // cs_bit0: HIF[30]
+        wr(ADDRMAP7,0x00000f0f); // row16: NULL
+      }
+      else if (size == 0x400000000) {//16GB
+        wr(ADDRMAP0,0x00040019); // cs_bit0: HIF[31]
+        wr(ADDRMAP7,0x00000f08); // row16: HIF[30]
+      }
+    }
+    else { // single rank
+      if (size == 0x100000000) {//4GB
+        wr(ADDRMAP0,0x0004001f); // cs_bit0: NULL
+        wr(ADDRMAP7,0x00000f0f); // row16: NULL
+      }
+    }
+  }
+  else {
+    // nothing
+  }
+
+  return 0;
+
+err_ret:
+  printf("unsupport memsize %ld\n", size);
+  return -1;
+}
+
   void quasi_reg_write(unsigned long int reg,int wdata) {
     DWC_DDR_UMCTL2_C_STRUCT_REG_S umctl2_reg;
 
@@ -1015,11 +1233,11 @@ void lpddr4_enter_selfrefresh(int pwdn_en,int dis_dram_clk,int mode) {
     umctl2_reg.dwc_ddr_umctl2_c_struct_stat.u32 = rd(STAT_DCH1);
     if(pwdn_en) {
     while( umctl2_reg.dwc_ddr_umctl2_c_struct_stat.selfref_state != 2) //wait sdram enter selfrefresh-powerdown state
-        umctl2_reg.dwc_ddr_umctl2_c_struct_stat.u32 = rd(STAT);
+        umctl2_reg.dwc_ddr_umctl2_c_struct_stat.u32 = rd(STAT_DCH1);
     }
     else {
     while( umctl2_reg.dwc_ddr_umctl2_c_struct_stat.selfref_state != 1) //wait sdram enter selfrefresh state
-        umctl2_reg.dwc_ddr_umctl2_c_struct_stat.u32 = rd(STAT);
+        umctl2_reg.dwc_ddr_umctl2_c_struct_stat.u32 = rd(STAT_DCH1);
     }
 #ifdef CONFIG_DDR_MSG
     printf("[lpddr4_enter_selfrefresh]: CH1 STAT is :%x after enter selfrefresh state\n",umctl2_reg.dwc_ddr_umctl2_c_struct_stat.u32);
@@ -1055,7 +1273,8 @@ void lpddr4_auto_ps_en(int pwdn_en,int selfref_en,int clock_auto_disable ) {
     //ddr_sysreg_wr(DDR_CFG0,0x1ff0);
     //ddr_sysreg_wr(DDR_CFG0,0x1ff0);
     ddr_sysreg.ddr_sysreg_registers_struct_ddr_cfg0.u32 = ddr_sysreg_rd(DDR_CFG0);
-    ddr_sysreg.ddr_sysreg_registers_struct_ddr_cfg0.rg_ctl_ddr_usw_rst_reg |= 0x1F2;
+    //ddr_sysreg.ddr_sysreg_registers_struct_ddr_cfg0.rg_ctl_ddr_usw_rst_reg |= 0x1F2;
+    ddr_sysreg.ddr_sysreg_registers_struct_ddr_cfg0.rg_ctl_ddr_usw_rst_reg |= 0x1FA;
     ddr_sysreg_wr(DDR_CFG0,ddr_sysreg.ddr_sysreg_registers_struct_ddr_cfg0.u32);
   }
 
@@ -1075,7 +1294,7 @@ void dfi_freq_change(int dfi_freq,int skip_dram_init) {
 #ifdef CONFIG_DDR_MSG
   printf("[dfi_freq_change]: start dfi_freq_change, target dfi_freq is %x \n",dfi_freq);
 #endif
-  wr(DBG1,3);
+  //wr(DBG1,3);
   umctl2_reg.dwc_ddr_umctl2_c_struct_swctl.u32 = rd(SWCTL);
   umctl2_reg.dwc_ddr_umctl2_c_struct_swctl.sw_done = 0;
   wr(SWCTL,umctl2_reg.dwc_ddr_umctl2_c_struct_swctl.u32);
@@ -1086,7 +1305,6 @@ void dfi_freq_change(int dfi_freq,int skip_dram_init) {
 
   umctl2_reg.dwc_ddr_umctl2_c_struct_dfimisc.u32 = rd(DFIMISC);
   umctl2_reg.dwc_ddr_umctl2_c_struct_dfimisc.dfi_frequency = dfi_freq;
-  umctl2_reg.dwc_ddr_umctl2_c_struct_dfimisc.dfi_init_start = 0x1;
   umctl2_reg.dwc_ddr_umctl2_c_struct_dfimisc.dfi_init_complete_en = 0;
   wr(DFIMISC,umctl2_reg.dwc_ddr_umctl2_c_struct_dfimisc.u32);
 
@@ -1097,15 +1315,28 @@ void dfi_freq_change(int dfi_freq,int skip_dram_init) {
   while( umctl2_reg.dwc_ddr_umctl2_c_struct_swstat.sw_done_ack == 0)
     umctl2_reg.dwc_ddr_umctl2_c_struct_swctl.u32 = rd(SWSTAT);
 
+  wr(SWCTL,0x0);
+  umctl2_reg.dwc_ddr_umctl2_c_struct_dfimisc.u32 = rd(DFIMISC);
+  umctl2_reg.dwc_ddr_umctl2_c_struct_dfimisc.dfi_init_start = 0x1;
+  wr(DFIMISC,umctl2_reg.dwc_ddr_umctl2_c_struct_dfimisc.u32);
+  wr(SWCTL,0x1);
+  while(rd(SWSTAT)!=0x00000001);
   rdata = rd(DFISTAT);
+  while ((rdata & 0x1) != 0) //wait dfi_init_complete = 0
+    rdata = rd(DFISTAT);
+
+#ifndef CONFIG_DDR_H32_MODE
+  rdata = rd(DCH1_DFISTAT);
   while((rdata & 0x1) != 0) //wait dfi_init_complete = 0
-  rdata = rd(DFISTAT);
+    rdata = rd(DCH1_DFISTAT);
+#endif
+
   //change dfi clk freq here
   //pull down dfi_init_start
   umctl2_reg.dwc_ddr_umctl2_c_struct_swctl.u32 = rd(SWCTL);
   umctl2_reg.dwc_ddr_umctl2_c_struct_swctl.sw_done = 0;
-  wr(SWCTL,umctl2_reg.dwc_ddr_umctl2_c_struct_swctl.u32);
-
+  wr(SWCTL, umctl2_reg.dwc_ddr_umctl2_c_struct_swctl.u32);
+ 
   umctl2_reg.dwc_ddr_umctl2_c_struct_dfimisc.u32 = rd(DFIMISC);
   umctl2_reg.dwc_ddr_umctl2_c_struct_dfimisc.dfi_init_start = 0;
   wr(DFIMISC,umctl2_reg.dwc_ddr_umctl2_c_struct_dfimisc.u32);
@@ -1119,9 +1350,17 @@ void dfi_freq_change(int dfi_freq,int skip_dram_init) {
   umctl2_reg.dwc_ddr_umctl2_c_struct_dfistat.u32 = rd(DFISTAT);
   while(umctl2_reg.dwc_ddr_umctl2_c_struct_dfistat.dfi_init_complete == 0)
     umctl2_reg.dwc_ddr_umctl2_c_struct_dfistat.u32 = rd(DFISTAT);
-  wr(DBG1,0);
+
+  //wait dfi_init_complete = 1
+#ifndef CONFIG_DDR_H32_MODE
+  umctl2_reg.dwc_ddr_umctl2_c_struct_dfistat.u32 = rd(DCH1_DFISTAT);
+  while(umctl2_reg.dwc_ddr_umctl2_c_struct_dfistat.dfi_init_complete == 0)
+    umctl2_reg.dwc_ddr_umctl2_c_struct_dfistat.u32 = rd(DCH1_DFISTAT);
+#endif
+
+  //wr(DBG1,0);
 #ifdef CONFIG_DDR_MSG
-  printf("[dfi_freq_change]: dfi_freq_change, end \n",dfi_freq);
+  printf("[dfi_freq_change]: dfi_freq_change, end \n");
 #endif
 }
 
@@ -1146,3 +1385,168 @@ void lpddr4_auto_selref(void)
   wr(PWRCTL,0x0000000b); //[3] dfi_dram_clk_disable [1] powerdown_en [0]serref_en
   wr(DCH1_PWRCTL,0x0000000b);
 }
+
+void ctrl_en_lp3_exit(enum DDR_BITWIDTH bits) {
+  //skip DRAM init, because this has done 
+  wr(SWCTL,0x00000000);
+  wr(INIT0,0xc0020002);
+  wr(SWCTL,0x00000001);
+  while(rd(SWSTAT)!=0x00000001);
+
+  //dfi frequency change proto ,to PS0
+  wr(SWCTL,0x00000000);
+  wr(DFIMISC,0x00000000);// [5]dfi_freq=0x0
+  wr(SWCTL,0x00000001);
+  while(rd(SWSTAT)!=0x00000001);
+
+  wr(SWCTL,0x00000000);
+  wr(DFIMISC,0x00000020);// [5]dfi_init_start=0x1
+  wr(SWCTL,0x00000001);
+  while(rd(SWSTAT)!=0x00000001);
+
+
+  while(rd(DFISTAT)!=0x00000001); //polling dfi_init_complete
+if(bits==64) {
+  while(rd(DCH1_DFISTAT)!=0x00000001);
+ }
+  wr(SWCTL,0x00000000);
+  wr(DFIMISC,0x00000000);
+  wr(SWCTL,0x00000001);
+  while(rd(SWSTAT)!=0x00000001);
+
+
+  wr(SWCTL,0x00000000);
+  wr(DFIMISC,0x00000001);
+  wr(SWCTL,0x00000001);
+  while(rd(SWSTAT)!=0x00000001);
+
+  //for low power,
+  wr(SWCTL,0x00000000);
+  wr(PWRCTL,0x0000000a); //[3] dfi_dram_clk_disable [1] powerdown_en
+  wr(DCH1_PWRCTL,0x0000000a);
+  wr(SWCTL,0x00000001);
+  while (rd(SWSTAT) != 0x00000001);
+  //detect until umctrl into normal state
+  while (rd(STAT) != 0x00000001);
+  if(bits==64) {
+    while(rd(DCH1_STAT) != 0x00000001);
+  }
+
+  //en phy master proto
+  wr(DFIPHYMSTR,0x14000001);
+
+#ifdef CONFIG_DDR_MSG
+    DDR_DEBUG("DFIPHYMSTR is %0x \n", rd(DFIPHYMSTR));
+    DDR_DEBUG("DFIUPD0    is %0x \n", rd(DFIUPD0));
+    DDR_DEBUG("DFIUPD1    is %0x \n", rd(DFIUPD1));
+    DDR_DEBUG("ZQCTL0     is %0x \n", rd(ZQCTL0));
+    DDR_DEBUG("ADDRMAP0     is %0x \n", rd(ADDRMAP0));
+    DDR_DEBUG("ADDRMAP1     is %0x \n", rd(ADDRMAP1));
+#endif
+}
+
+int lpddr4_reinit_ctrl(enum DDR_TYPE type, int rank_num, int speed,
+					enum DDR_BITWIDTH bits, unsigned long size)
+{
+    int ret;
+    unsigned int rdata;
+
+    //a.
+    ddr_sysreg_wr(DDR_CFG1, 0xa000011f);   //remove core clock after xx
+    wr(PWRCTL, 0x00000000); //[3] dfi_dram_clk_disable [1] powerdown_en [0]serref_en
+    wr(DCH1_PWRCTL, 0x00000000);
+
+    // use phy value stored in spl
+    //dwc_ddrphy_phyinit_regInterface(saveRegs);
+
+    //b.dis axi port
+    disable_axi_port(0x1f);
+    while (rd(PSTAT) != 0x0);
+
+#ifdef CONFIG_DDR_MSG
+    DDR_DEBUG("Axi prot idle\n");
+#endif
+    wr(DFIPHYMSTR, 0x14000000);
+    //check status.
+    while ((rd(STAT) & 0x3) == 0x03);
+
+#ifndef CONFIG_DDR_H32_MODE
+    while ((rd(STAT_DCH1) & 0x3) == 0x03);
+#endif
+    //c.poll cam empty flag
+    while ((rd(DBGCAM) & 0x36000000) != 0x36000000);
+    //d.save phy regs
+    //e.SRE
+    lpddr4_enter_selfrefresh(1, 0, 0);
+    //f.LP3 enter
+    dfi_freq_change(0x1f, 0x3);
+    //g.PwrOk disassert
+    rdata = ddr_sysreg_rd(DDR_CFG0);
+    rdata &= ~(0x1 << 6);
+    ddr_sysreg_wr(DDR_CFG0, rdata);   //Pwrokin dessert
+
+    //p.phy reset
+    rdata = ddr_sysreg_rd(DDR_CFG0);
+    rdata &= ~(0x1 << 7);
+    rdata &= 0x0;
+    ddr_sysreg_wr(DDR_CFG0, rdata);   //Phy reset .DDR_CFG0 ALL reset
+
+    //r.ddr core reset
+    rdata = ddr_sysreg_rd(DDR_CFG0);
+    rdata &= ~(0x1 << 5);
+    ddr_sysreg_wr(DDR_CFG0, rdata);   //ctrl sw reset
+
+    //s.pwr ok assert
+    rdata = ddr_sysreg_rd(DDR_CFG0);
+    rdata |= (0x1 << 6);
+    ddr_sysreg_wr(DDR_CFG0, rdata);   //Pwrokin dessert
+
+    //t.ctrl init
+    //dwc_umctl_init_skip_traing(type, rank_num, speed, bits);
+    ddr_sysreg_wr(DDR_CFG0, 0x50);  // release apb presetn
+    ddr_sysreg_wr(DDR_CFG0, 0x50);
+    ddr_sysreg_wr(DDR_CFG0, 0x50);
+    if (bits == 32) {
+        ddr_sysreg_wr(DDR_CFG0, 0x52);
+    }
+    ctrl_init(rank_num, speed);
+    addrmap(rank_num, bits);
+    ret = adjust_ddr_addrmap(type, rank_num, speed, bits, size);
+
+    // msic regu restore for str
+    dwc_ddr_misc_regu_save();
+
+    de_assert_other_reset_ddr(); //after this step, only PwrOk is staill low
+
+    dq_pinmux(bits);
+
+    //u.phy restor
+	  dwc_ddrphy_phyinit_regInterface(restoreRegs);
+
+    //v.ctrl en ,hs
+    ctrl_en_lp3_exit(bits);
+
+    //w.SRE
+    lpddr4_selfrefresh_exit(0);
+
+    //y.en auto refresh
+    enable_auto_refresh();
+ 
+    //x.en axi port
+    enable_axi_port(0x1f);
+    wr(DFIPHYMSTR, 0x14000001);
+    lpddr4_auto_selref();
+
+    if(rd(PSTAT))
+    {
+#ifdef CONFIG_DDR_MSG
+	    DDR_DEBUG("***** DDR busy in LP3 Mode *****\n");
+#endif
+    }else{
+#ifdef CONFIG_DDR_MSG
+	    DDR_DEBUG("***** AXI port idle *****\n");
+#endif
+    }
+    return ret;
+ }
+

board/thead/light-c910/spl.c

@@ -26,6 +26,11 @@
 DECLARE_GLOBAL_DATA_PTR;
 
 extern void init_ddr(void);
+#ifdef CONFIG_FIXUP_MEMORY_REGION
+extern int fixup_ddr_addrmap(unsigned long size);
+extern int query_ddr_boundary(unsigned long size);
+#endif
+extern unsigned long get_ddr_density(void);
 extern void cpu_clk_config(int cpu_freq);
 extern void sys_clk_config(void);
 extern void ddr_clk_config(int ddr_freq);
@@ -93,6 +98,25 @@ void setup_ddr_pmp(void)
 	sync_is();
 }
 
+void clear_ddr_pmp(void)
+{
+	/* restore pmp entry0,entry1 setting in bootrom */
+	writel(0x0400000000 >> 12, (void *)(PMP_BASE_ADDR + 0x104));
+	writel(0x0 >> 12, (void *)(PMP_BASE_ADDR + 0x100));
+	writel(0xffe1000000 >> 12, (void *)(PMP_BASE_ADDR + 0x10c));
+	writel(0xffe0180000 >> 12, (void *)(PMP_BASE_ADDR + 0x108));
+
+	writel(0x4040, (void *)(PMP_BASE_ADDR + 0x000));
+
+	sync_is();
+}
+
+static inline void _l2cache_ciall(void)
+{
+	asm volatile (".long 0x0170000b");
+}
+
+
 int get_rng(unsigned int *rng, int cnt)
 {
 	int i;
@@ -297,6 +321,100 @@ void setup_ddr_parity(void)
 	}
 }
 
+#ifdef CONFIG_FIXUP_MEMORY_REGION
+
+#define MAGIC_DATA (0xF4240)
+#define MAGIC_DATA2 (0x5AA5)
+#define MAGIC_DATA3 (0x3C3C)
+#define MAGIC_DATA4 (0xF0F0)
+
+/*
+return: 0: found boundary;
+*/
+int boundary_verify(unsigned long boundary) {
+	phys_addr_t verify_addr = (phys_addr_t)CONFIG_SYS_SDRAM_BASE;
+	phys_addr_t verify_addr2 = ((phys_addr_t)boundary + CONFIG_SYS_SDRAM_BASE)/4;
+	phys_addr_t verify_addr3 = ((phys_addr_t)boundary + CONFIG_SYS_SDRAM_BASE)/2;
+	phys_addr_t verify_addr4 = (phys_addr_t)boundary + CONFIG_SYS_SDRAM_BASE;
+
+	// verify data accessing result firstly
+	writel(MAGIC_DATA2, (void *)verify_addr);
+	invalidate_dcache_range(verify_addr, verify_addr + CONFIG_SYS_CACHELINE_SIZE);
+	if (readl((void *)verify_addr) != MAGIC_DATA2) {
+		printf("ddr rw test failed\n");
+		return -1;
+	}
+	writel(MAGIC_DATA, (void *)verify_addr);  // writing at beginning
+	invalidate_dcache_range(verify_addr, verify_addr + CONFIG_SYS_CACHELINE_SIZE);
+	if (readl((void *)verify_addr) != MAGIC_DATA) {
+		printf("ddr rw test failed\n");
+		return -1;
+	}
+	writel(MAGIC_DATA2, (void *)verify_addr2); // writing at one-quarter addr
+	writel(MAGIC_DATA3, (void *)verify_addr3); // writing at half addr
+	invalidate_dcache_range(verify_addr, verify_addr + CONFIG_SYS_CACHELINE_SIZE);
+	invalidate_dcache_range(verify_addr2, verify_addr2 + CONFIG_SYS_CACHELINE_SIZE);
+	invalidate_dcache_range(verify_addr3, verify_addr3 + CONFIG_SYS_CACHELINE_SIZE);
+
+	if (boundary == (unsigned long)MAXIMAL_DDR_DENSITY_MB * UNIT_MB) { // boundary by design
+		if ((readl((void *)verify_addr) == MAGIC_DATA) &&
+			(readl((void *)verify_addr2) == MAGIC_DATA2) &&
+			(readl((void *)verify_addr3) == MAGIC_DATA3))
+			return 0;
+	}
+	else {
+		writel(MAGIC_DATA4, (void *)verify_addr4); // writing out of boundary
+		invalidate_dcache_range(verify_addr4, verify_addr4 + CONFIG_SYS_CACHELINE_SIZE);
+		if ((readl((void *)verify_addr) == MAGIC_DATA4) && // overwrite by verify_addr4
+			(readl((void *)verify_addr2) == MAGIC_DATA2) &&
+			(readl((void *)verify_addr3) == MAGIC_DATA3) &&
+			(readl((void *)verify_addr4) == MAGIC_DATA4))
+			return 0;
+	}
+
+	return -1;
+}
+
+int setup_ddr_addrmap(void)
+{
+	unsigned long boundary = (unsigned long)MAXIMAL_DDR_DENSITY_MB * UNIT_MB;
+
+	// verify data accessing result firstly
+	writel(MAGIC_DATA, (phys_addr_t)CONFIG_SYS_SDRAM_BASE);
+	invalidate_dcache_range(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_CACHELINE_SIZE);
+	if (readl((phys_addr_t)CONFIG_SYS_SDRAM_BASE) != MAGIC_DATA) {
+		printf("ddr rw test failed\n");
+		goto addrmap_err;
+	}
+	writel(MAGIC_DATA2, (phys_addr_t)CONFIG_SYS_SDRAM_BASE);
+	invalidate_dcache_range(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_CACHELINE_SIZE);
+	if (readl((phys_addr_t)CONFIG_SYS_SDRAM_BASE) != MAGIC_DATA2) {
+		printf("ddr rw test failed\n");
+		goto addrmap_err;
+	}
+
+	// try to find memory boundary
+	while (boundary >= (unsigned long)MINIMAL_DDR_DENSITY_MB * UNIT_MB) {
+		if (query_ddr_boundary(boundary) == 0) {
+			clear_ddr_pmp();
+			fixup_ddr_addrmap(boundary);
+			setup_ddr_pmp();
+			if (boundary_verify(boundary) == 0) {
+				gd->ram_size = boundary;
+				printf("found ddr boundary <0x%lx>\n", boundary);
+				return 0;
+			}
+		}
+		boundary = boundary >> 1;
+	}
+
+	gd->ram_size = get_ddr_density();
+addrmap_err:
+	printf("failed to setup ddr addrmap\n");
+	return -1;
+}
+#endif
+
 void cpu_performance_enable(void)
 {
 #define CSR_MHINT2_E	0x7cc
@@ -308,7 +426,6 @@ void cpu_performance_enable(void)
 	csr_write(CSR_MCCR2, 0xe2490009);
 	// FIXME: Clear bit[12] to disable L0BTB.
 	csr_write(CSR_MHCR, 0x17f); // clear bit7 to disable indirect brantch prediction
-	csr_write(CSR_MXSTATUS, 0x638000);
 	csr_write(CSR_MHINT, 0x6e30c | (1<<21) | (1<<22)); // set bit21 & bit 22 to close tlb & fence broadcast
 	mdelay(50); // workaround
 }
@@ -372,9 +489,9 @@ void board_init_f(ulong dummy)
 	preloader_console_init();
 
 #ifdef CONFIG_PMIC_VOL_INIT
-	ret = pmic_ddr_regu_init();
+	ret = aon_local_init();
 	if (ret) {
-		printf("%s pmic init failed %d \n",__func__,ret);
+		printf("%s aon local init failed %d \n",__func__,ret);
 		hang();
 	}
 
@@ -389,7 +506,6 @@ void board_init_f(ulong dummy)
 		printf("%s set apcpu voltage failed \n",__func__);
 		hang();
 	}
-
 #endif
 	ddr_clk_config(0);
 	cpu_clk_config(0);
@@ -398,6 +514,12 @@ void board_init_f(ulong dummy)
 	setup_ddr_scramble();
 	setup_ddr_parity();
 	setup_ddr_pmp();
+#ifdef CONFIG_FIXUP_MEMORY_REGION
+	setup_ddr_addrmap();
+#else
+	// update ram_size from board config
+	gd->ram_size = get_ddr_density();
+#endif
 
 	printf("ddr initialized, jump to uboot\n");
 	light_board_init_r(NULL, 0);

cmd/net.c

@@ -458,3 +458,22 @@ U_BOOT_CMD(
 );
 
 #endif  /* CONFIG_CMD_LINK_LOCAL */
+
+/* moved from board_init_r sequence here to save normal boot time */
+static int do_eth_init(cmd_tbl_t *cmdtp, int flag, int argc,
+			char * const argv[])
+{
+	puts("Net:   ");
+	eth_initialize();
+#if defined(CONFIG_RESET_PHY_R)
+	debug("Reset Ethernet PHY\n");
+	reset_phy();
+#endif
+	return 0;
+}
+
+U_BOOT_CMD(
+	eth,	6,	1,	do_eth_init,
+	"eth initialize",
+	""
+);

cmd/pxe_utils.c

@@ -335,7 +335,7 @@ static int label_localboot(struct pxe_label *label)
  * Loads fdt overlays specified in 'fdtoverlays'.
  */
 #ifdef CONFIG_OF_LIBFDT_OVERLAY
-static void label_boot_fdtoverlay(struct cmd_tbl *cmdtp, struct pxe_label *label)
+static void label_boot_fdtoverlay(cmd_tbl_t *cmdtp, struct pxe_label *label)
 {
 	char *fdtoverlay = label->fdtoverlays;
 	struct fdt_header *working_fdt;

common/image-fdt.c

@@ -416,7 +416,7 @@ int boot_get_fdt(int flag, int argc, char * const argv[], uint8_t arch,
 				 * FDT blob
 				 */
 				debug("*  fdt: raw FDT blob\n");
-				printf("## Flattened Device Tree blob at %08lx\n",
+				debug("## Flattened Device Tree blob at %08lx\n",
 				       (long)fdt_addr);
 			}
 			break;
@@ -425,7 +425,7 @@ int boot_get_fdt(int flag, int argc, char * const argv[], uint8_t arch,
 			goto no_fdt;
 		}
 
-		printf("   Booting using the fdt blob at %#08lx\n", fdt_addr);
+		debug("   Booting using the fdt blob at %#08lx\n", fdt_addr);
 		fdt_blob = map_sysmem(fdt_addr, 0);
 	} else if (images->legacy_hdr_valid &&
 			image_check_type(&images->legacy_hdr_os_copy,

configs/light_a_val_android_defconfig

@@ -18,6 +18,7 @@ CONFIG_SYS_PROMPT="C910 Light# "
 CONFIG_DDR_LP4X_3733_SINGLERANK=y
 # CONFIG_DDR_LP4_3733_DUALRANK is not set
 CONFIG_DDR_BOARD_CONFIG=y
+CONFIG_FIXUP_MEMORY_REGION=n
 CONFIG_CMD_BOOT_SLAVE=y
 CONFIG_CMD_ERASEENV=y
 CONFIG_CMD_GPT=y

configs/light_a_val_defconfig

@@ -22,17 +22,18 @@ CONFIG_SYS_PROMPT="Light VAL-A# "
 CONFIG_DDR_LP4X_3733_SINGLERANK=y
 # CONFIG_DDR_LP4_3733_DUALRANK is not set
 CONFIG_DDR_BOARD_CONFIG=y
+CONFIG_FIXUP_MEMORY_REGION=y
 CONFIG_CMD_BOOT_SLAVE=y
 CONFIG_CMD_ERASEENV=y
 CONFIG_CMD_GPT=y
 CONFIG_CMD_MTD=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MEMTEST=y
 CONFIG_DDR_SCAN=y
 CONFIG_DDR_PRBS_TEST=n
-# CONFIG_DOS_PARTITION is not set
 # CONFIG_ISO_PARTITION is not set
 CONFIG_PARTITION_TYPE_GUID=y
 CONFIG_OF_EMBED=y
@@ -78,6 +79,9 @@ CONFIG_SPI=y
 CONFIG_DESIGNWARE_SPI=y
 CONFIG_DESIGNWARE_QSPI=y
 CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_DWC3=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_MANUFACTURER="U-Boot-THEAD"
@@ -108,3 +112,5 @@ CONFIG_DDR_REGU_0V6=600000
 CONFIG_DDR_REGU_0V8=800000
 CONFIG_DDR_REGU_1V1=1100000
 CONFIG_BOARD_RNG_SEED=y
+CONFIG_MISC=y
+CONFIG_LIGHT_AON_CONF=y

configs/light_a_val_sec_defconfig

@@ -18,6 +18,7 @@ CONFIG_SYS_PROMPT="C910 Light# "
 CONFIG_DDR_LP4X_3733_SINGLERANK=y
 # CONFIG_DDR_LP4_3733_DUALRANK is not set
 CONFIG_DDR_BOARD_CONFIG=y
+CONFIG_FIXUP_MEMORY_REGION=y
 # CONFIG_TPM is not set
 # CONFIG_TPM_Z32H330TC_SPI is not set
 # CONFIG_TPM_V2 is not set
@@ -34,7 +35,6 @@ CONFIG_CMD_I2C=y
 CONFIG_CMD_MEMTEST=y
 CONFIG_DDR_SCAN=y
 CONFIG_DDR_PRBS_TEST=n
-# CONFIG_DOS_PARTITION is not set
 # CONFIG_ISO_PARTITION is not set
 CONFIG_PARTITION_TYPE_GUID=y
 CONFIG_OF_EMBED=y
@@ -79,6 +79,9 @@ CONFIG_SPI=y
 CONFIG_DESIGNWARE_SPI=y
 CONFIG_DESIGNWARE_QSPI=y
 CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_DWC3=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_MANUFACTURER="U-Boot-THEAD"
@@ -96,6 +99,7 @@ CONFIG_PHY=y
 CONFIG_REGMAP=y
 CONFIG_SYSCON=y
 CONFIG_CMD_BMP=y
+CONFIG_CMD_USB=y
 CONFIG_VIDEO_BRIDGE=y
 CONFIG_DM_PCA953X=y
 CONFIG_VIDEO_VS_DPU=y
@@ -108,3 +112,5 @@ CONFIG_PMIC_VOL_INIT=y
 CONFIG_DDR_REGU_0V6=600000
 CONFIG_DDR_REGU_0V8=800000
 CONFIG_DDR_REGU_1V1=1100000
+CONFIG_MISC=y
+CONFIG_LIGHT_AON_CONF=y

configs/light_ant_ref_android_defconfig

@@ -20,6 +20,7 @@ CONFIG_DDR_LP4X_3200_SINGLERANK=y
 CONFIG_DDR_H32_MODE=y
 # CONFIG_DDR_LP4_3733_DUALRANK is not set
 CONFIG_DDR_BOARD_CONFIG=y
+CONFIG_FIXUP_MEMORY_REGION=n
 CONFIG_CMD_BOOT_SLAVE=y
 CONFIG_CMD_ERASEENV=y
 CONFIG_CMD_GPT=y

configs/light_ant_ref_defconfig

@@ -20,6 +20,7 @@ CONFIG_DDR_LP4X_3200_SINGLERANK=y
 CONFIG_DDR_H32_MODE=y
 # CONFIG_DDR_LP4_3733_DUALRANK is not set
 CONFIG_DDR_BOARD_CONFIG=y
+CONFIG_FIXUP_MEMORY_REGION=y
 CONFIG_CMD_BOOT_SLAVE=y
 CONFIG_CMD_ERASEENV=y
 CONFIG_CMD_GPT=y

configs/light_ant_ref_sec_defconfig

@@ -20,6 +20,7 @@ CONFIG_DDR_LP4X_3200_SINGLERANK=y
 CONFIG_DDR_H32_MODE=y
 # CONFIG_DDR_LP4_3733_DUALRANK is not set
 CONFIG_DDR_BOARD_CONFIG=y
+CONFIG_FIXUP_MEMORY_REGION=y
 CONFIG_CMD_BOOT_SLAVE=y
 CONFIG_CMD_ERASEENV=y
 CONFIG_CMD_GPT=y

configs/light_b_product_android_defconfig

@@ -20,6 +20,7 @@ CONFIG_DDR_LP4X_3200_SINGLERANK=y
 CONFIG_DDR_H32_MODE=y
 # CONFIG_DDR_LP4_3733_DUALRANK is not set
 CONFIG_DDR_BOARD_CONFIG=y
+CONFIG_FIXUP_MEMORY_REGION=n
 CONFIG_CMD_BOOT_SLAVE=y
 CONFIG_CMD_ERASEENV=y
 CONFIG_CMD_GPT=y

configs/light_b_product_defconfig

@@ -20,6 +20,7 @@ CONFIG_DDR_LP4X_3200_SINGLERANK=y
 CONFIG_DDR_H32_MODE=y
 # CONFIG_DDR_LP4_3733_DUALRANK is not set
 CONFIG_DDR_BOARD_CONFIG=y
+CONFIG_FIXUP_MEMORY_REGION=y
 CONFIG_CMD_BOOT_SLAVE=y
 CONFIG_CMD_ERASEENV=y
 CONFIG_CMD_GPT=y
@@ -104,3 +105,5 @@ CONFIG_PMIC_VOL_INIT=y
 CONFIG_DDR_REGU_0V6=600000
 CONFIG_DDR_REGU_0V8=800000
 CONFIG_DDR_REGU_1V1=1100000
+CONFIG_MISC=y
+CONFIG_LIGHT_AON_CONF=y

configs/light_b_product_sec_defconfig

@@ -20,6 +20,7 @@ CONFIG_DDR_LP4X_3200_SINGLERANK=y
 CONFIG_DDR_H32_MODE=y
 # CONFIG_DDR_LP4_3733_DUALRANK is not set
 CONFIG_DDR_BOARD_CONFIG=y
+CONFIG_FIXUP_MEMORY_REGION=y
 CONFIG_CMD_BOOT_SLAVE=y
 CONFIG_CMD_ERASEENV=y
 CONFIG_CMD_GPT=y
@@ -104,3 +105,5 @@ CONFIG_PMIC_VOL_INIT=y
 CONFIG_DDR_REGU_0V6=600000
 CONFIG_DDR_REGU_0V8=800000
 CONFIG_DDR_REGU_1V1=1100000
+CONFIG_MISC=y
+CONFIG_LIGHT_AON_CONF=y

configs/light_beagle_android_defconfig

@@ -19,6 +19,7 @@ CONFIG_SYS_PROMPT="C910 Light# "
 CONFIG_DDR_LP4X_3733_SINGLERANK=y
 # CONFIG_DDR_LP4_3733_DUALRANK is not set
 CONFIG_DDR_BOARD_CONFIG=y
+CONFIG_FIXUP_MEMORY_REGION=n
 CONFIG_CMD_BOOT_SLAVE=y
 CONFIG_CMD_ERASEENV=y
 CONFIG_CMD_GPT=y
@@ -114,4 +115,4 @@ CONFIG_ANDROID_AB=y
 CONFIG_CMD_AB_SELECT=y
 CONFIG_XBC=y
 CONFIG_BOARD_RNG_SEED=y
-CONFIG_SPL_TEXT_BASE=0xffe0000800
+CONFIG_SPL_TEXT_BASE=0xffe0000800

configs/light_beagle_defconfig

@@ -13,7 +13,7 @@ CONFIG_DDR_BOARD_CONFIG=y
 CONFIG_ARCH_RV64I=y
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_BUILD_TARGET="u-boot-with-spl.bin"
-CONFIG_DEFAULT_FDT_FILE="thead/light-beagle.dtb"
+CONFIG_DEFAULT_FDT_FILE="thead/th1520-beaglev-ahead.dtb"
 CONFIG_BOARD_LATE_INIT=y
 CONFIG_DISPLAY_CPUINFO=y
 CONFIG_DISPLAY_BOARDINFO=y
@@ -99,3 +99,6 @@ CONFIG_VIDEO_DW_DPHY=y
 CONFIG_OF_LIBFDT_OVERLAY=y
 # CONFIG_EFI_LOADER is not set
 CONFIG_BOARD_RNG_SEED=y
+CONFIG_FIXUP_MEMORY_REGION=y
+CONFIG_MISC=y
+CONFIG_LIGHT_AON_CONF=y

configs/light_lpi4a_16g_defconfig

@@ -88,7 +88,7 @@ CONFIG_USB_FUNCTION_MASS_STORAGE=y
 # CONFIG_SPL_USE_TINY_PRINTF is not set
 # CONFIG_EFI_LOADER is not set
 # CONFIG_LIGHT_SEC_BOOT is not set
-CONFIG_DEFAULT_FDT_FILE="thead/light-lpi4a-16gb.dtb"
+CONFIG_DEFAULT_FDT_FILE="thead/th1520-lichee-pi-4a-16g.dtb"
 CONFIG_BOARD_LATE_INIT=y
 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
 CONFIG_DM_VIDEO=y
@@ -109,3 +109,6 @@ CONFIG_DDR_REGU_0V6=600000
 CONFIG_DDR_REGU_0V8=800000
 CONFIG_DDR_REGU_1V1=1100000
 CONFIG_BOARD_RNG_SEED=y
+CONFIG_FIXUP_MEMORY_REGION=y
+CONFIG_MISC=y
+CONFIG_LIGHT_AON_CONF=y

configs/light_lpi4a_android_defconfig

@@ -19,6 +19,7 @@ CONFIG_SYS_PROMPT="C910 Light# "
 CONFIG_DDR_LP4X_3733_DUALRANK=y
 # CONFIG_DDR_LP4_3733_DUALRANK is not set
 CONFIG_DDR_BOARD_CONFIG=y
+CONFIG_FIXUP_MEMORY_REGION=n
 CONFIG_CMD_BOOT_SLAVE=y
 CONFIG_CMD_ERASEENV=y
 CONFIG_CMD_GPT=y

configs/light_lpi4a_cluster_16g_defconfig

@@ -88,7 +88,7 @@ CONFIG_USB_FUNCTION_MASS_STORAGE=y
 # CONFIG_SPL_USE_TINY_PRINTF is not set
 # CONFIG_EFI_LOADER is not set
 # CONFIG_LIGHT_SEC_BOOT is not set
-CONFIG_DEFAULT_FDT_FILE="thead/light-lpi4a-cluster-16gb.dtb"
+CONFIG_DEFAULT_FDT_FILE="thead/th1520-lpi4a-cluster-16g.dtb"
 CONFIG_BOARD_LATE_INIT=y
 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
 CONFIG_DM_VIDEO=y
@@ -109,3 +109,6 @@ CONFIG_DDR_REGU_0V6=600000
 CONFIG_DDR_REGU_0V8=800000
 CONFIG_DDR_REGU_1V1=1100000
 CONFIG_BOARD_RNG_SEED=y
+CONFIG_FIXUP_MEMORY_REGION=y
+CONFIG_MISC=y
+CONFIG_LIGHT_AON_CONF=y

configs/light_lpi4a_cluster_defconfig

@@ -87,7 +87,7 @@ CONFIG_USB_FUNCTION_MASS_STORAGE=y
 # CONFIG_SPL_USE_TINY_PRINTF is not set
 # CONFIG_EFI_LOADER is not set
 # CONFIG_LIGHT_SEC_BOOT is not set
-CONFIG_DEFAULT_FDT_FILE="thead/light-lpi4a-cluster.dtb"
+CONFIG_DEFAULT_FDT_FILE="thead/th1520-lpi4a-cluster.dtb"
 CONFIG_BOARD_LATE_INIT=y
 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
 CONFIG_DM_VIDEO=y
@@ -108,3 +108,6 @@ CONFIG_DDR_REGU_0V6=600000
 CONFIG_DDR_REGU_0V8=800000
 CONFIG_DDR_REGU_1V1=1100000
 CONFIG_BOARD_RNG_SEED=y
+CONFIG_FIXUP_MEMORY_REGION=y
+CONFIG_MISC=y
+CONFIG_LIGHT_AON_CONF=y

configs/light_lpi4a_console_16g_defconfig

@@ -88,7 +88,7 @@ CONFIG_USB_FUNCTION_MASS_STORAGE=y
 # CONFIG_SPL_USE_TINY_PRINTF is not set
 # CONFIG_EFI_LOADER is not set
 # CONFIG_LIGHT_SEC_BOOT is not set
-CONFIG_DEFAULT_FDT_FILE="thead/light-lpi4a-console-16g.dtb"
+CONFIG_DEFAULT_FDT_FILE="thead/th1520-lpi4a-console-16g.dtb"
 CONFIG_BOARD_LATE_INIT=y
 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
 CONFIG_DM_VIDEO=y
@@ -109,3 +109,11 @@ CONFIG_DDR_REGU_0V6=600000
 CONFIG_DDR_REGU_0V8=800000
 CONFIG_DDR_REGU_1V1=1100000
 CONFIG_BOARD_RNG_SEED=y
+CONFIG_FIXUP_MEMORY_REGION=y
+CONFIG_MISC=y
+CONFIG_LIGHT_AON_CONF=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+# CONFIG_DOS_PARTITION is not set
+CONFIG_CMD_USB=y

configs/light_lpi4a_console_defconfig

@@ -87,7 +87,7 @@ CONFIG_USB_FUNCTION_MASS_STORAGE=y
 # CONFIG_SPL_USE_TINY_PRINTF is not set
 # CONFIG_EFI_LOADER is not set
 # CONFIG_LIGHT_SEC_BOOT is not set
-CONFIG_DEFAULT_FDT_FILE="thead/light-lpi4a-console.dtb"
+CONFIG_DEFAULT_FDT_FILE="thead/th1520-lpi4a-console.dtb"
 CONFIG_BOARD_LATE_INIT=y
 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
 CONFIG_DM_VIDEO=y
@@ -108,3 +108,11 @@ CONFIG_DDR_REGU_0V6=600000
 CONFIG_DDR_REGU_0V8=800000
 CONFIG_DDR_REGU_1V1=1100000
 CONFIG_BOARD_RNG_SEED=y
+CONFIG_FIXUP_MEMORY_REGION=y
+CONFIG_MISC=y
+CONFIG_LIGHT_AON_CONF=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+# CONFIG_DOS_PARTITION is not set
+CONFIG_CMD_USB=y

configs/light_lpi4a_defconfig

@@ -22,6 +22,7 @@ CONFIG_SYS_PROMPT="Light LPI4A# "
 CONFIG_DDR_LP4X_3733_DUALRANK=y
 # CONFIG_DDR_LP4_3733_DUALRANK is not set
 CONFIG_DDR_BOARD_CONFIG=y
+CONFIG_FIXUP_MEMORY_REGION=y
 CONFIG_CMD_BOOT_SLAVE=y
 CONFIG_CMD_ERASEENV=y
 CONFIG_CMD_GPT=y
@@ -32,7 +33,6 @@ CONFIG_CMD_I2C=y
 CONFIG_CMD_MEMTEST=y
 CONFIG_DDR_SCAN=y
 CONFIG_DDR_PRBS_TEST=n
-# CONFIG_DOS_PARTITION is not set
 # CONFIG_ISO_PARTITION is not set
 CONFIG_PARTITION_TYPE_GUID=y
 CONFIG_OF_EMBED=y
@@ -78,6 +78,9 @@ CONFIG_SPI=y
 CONFIG_DESIGNWARE_SPI=y
 CONFIG_DESIGNWARE_QSPI=y
 CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_DWC3=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_MANUFACTURER="U-Boot-THEAD"
@@ -87,7 +90,7 @@ CONFIG_USB_FUNCTION_MASS_STORAGE=y
 # CONFIG_SPL_USE_TINY_PRINTF is not set
 # CONFIG_EFI_LOADER is not set
 # CONFIG_LIGHT_SEC_BOOT is not set
-CONFIG_DEFAULT_FDT_FILE="thead/light-lpi4a.dtb"
+CONFIG_DEFAULT_FDT_FILE="thead/th1520-lichee-pi-4a.dtb"
 CONFIG_BOARD_LATE_INIT=y
 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
 CONFIG_DM_VIDEO=y
@@ -95,10 +98,13 @@ CONFIG_PHY=y
 CONFIG_REGMAP=y
 CONFIG_SYSCON=y
 CONFIG_CMD_BMP=y
+CONFIG_CMD_USB=y
 CONFIG_VIDEO_BRIDGE=y
 CONFIG_DM_PCA953X=y
 CONFIG_VIDEO_VS_DPU=y
-CONFIG_VIDEO_LCD_ILITEK_ILI9881C=y
+CONFIG_VIDEO_LCD_ILITEK_ILI9881C=n
+CONFIG_VIDEO_LCD_JD9365DA=y
+#CONFIG_VIDEO_LCD_CUSTOM_LOGO=y
 CONFIG_VIDEO_DW_DSI_LIGHT=y
 CONFIG_VIDEO_DW_DPHY=y
 CONFIG_VIDEO_DW_DSI_HOST=y
@@ -108,3 +114,5 @@ CONFIG_DDR_REGU_0V6=600000
 CONFIG_DDR_REGU_0V8=800000
 CONFIG_DDR_REGU_1V1=1100000
 CONFIG_BOARD_RNG_SEED=y
+CONFIG_MISC=y
+CONFIG_LIGHT_AON_CONF=y

configs/light_lpi4a_plastic_16g_defconfig

@@ -0,0 +1,119 @@
+CONFIG_RISCV=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_ENV_SIZE=0x20000
+CONFIG_ENV_OFFSET=0xe0000
+CONFIG_NR_DRAM_BANKS=8
+CONFIG_SPL=y
+CONFIG_SMP=y
+CONFIG_TARGET_LIGHT_C910=y
+CONFIG_TARGET_LIGHT_FM_C910_LPI4A=y
+# CONFIG_THEAD_PLIC is not set
+# CONFIG_THEAD_LIGHT_TIMER is not set
+# CONFIG_THEAD_LIGHT_DIGITAL_SENSOR is not set
+CONFIG_ARCH_RV64I=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_BUILD_TARGET="u-boot-with-spl.bin"
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_DISPLAY_BOARDINFO=y
+# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
+CONFIG_SPL_RAM_SUPPORT=y
+CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SYS_PROMPT="LicheeLaptop4A 16G # "
+CONFIG_DDR_LP4X_3733_DUALRANK=y
+# CONFIG_DDR_LP4_3733_DUALRANK is not set
+CONFIG_DDR_BOARD_CONFIG=y
+CONFIG_CMD_BOOT_SLAVE=y
+CONFIG_CMD_ERASEENV=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_DDR_SCAN=y
+CONFIG_DDR_PRBS_TEST=n
+# CONFIG_DOS_PARTITION is not set
+# CONFIG_ISO_PARTITION is not set
+CONFIG_PARTITION_TYPE_GUID=y
+CONFIG_OF_EMBED=y
+CONFIG_DEFAULT_DEVICE_TREE="light-lpi4a-laptop"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SPL_CLK=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_UDP_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x10000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_DW=y
+CONFIG_DWAPB_GPIO=y
+# CONFIG_MMC_SPI is not set
+CONFIG_MMC_VERBOSE=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_SNPS=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SNPS=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MMC_RPMB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_SPI_NAND=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_PHY_REALTEK=y
+CONFIG_RTL8211E_PINE64_GIGABIT_FIX=y
+CONFIG_RTL8211X_PHY_FORCE_MASTER=y
+CONFIG_RTL8211F_PHY_FORCE_EEE_RXC_ON=y
+CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_DESIGNWARE_SPI=y
+CONFIG_DESIGNWARE_QSPI=y
+CONFIG_USB=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="U-Boot-THEAD"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1234
+CONFIG_USB_GADGET_PRODUCT_NUM=0x8888
+CONFIG_USB_FUNCTION_MASS_STORAGE=y
+# CONFIG_SPL_USE_TINY_PRINTF is not set
+# CONFIG_EFI_LOADER is not set
+# CONFIG_LIGHT_SEC_BOOT is not set
+CONFIG_DEFAULT_FDT_FILE="thead/th1520-lpi4a-plastic-16g.dtb"
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_DM_VIDEO=y
+CONFIG_PHY=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_CMD_BMP=y
+CONFIG_VIDEO_BRIDGE=y
+CONFIG_DM_PCA953X=y
+CONFIG_VIDEO_VS_DPU=y
+CONFIG_VIDEO_LCD_ILITEK_ILI9881C=y
+CONFIG_VIDEO_DW_DSI_LIGHT=y
+CONFIG_VIDEO_DW_DPHY=y
+CONFIG_VIDEO_DW_DSI_HOST=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_PMIC_VOL_INIT=y
+CONFIG_DDR_REGU_0V6=600000
+CONFIG_DDR_REGU_0V8=800000
+CONFIG_DDR_REGU_1V1=1100000
+CONFIG_BOARD_RNG_SEED=y
+CONFIG_FIXUP_MEMORY_REGION=y
+CONFIG_MISC=y
+CONFIG_LIGHT_AON_CONF=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+# CONFIG_DOS_PARTITION is not set
+CONFIG_CMD_USB=y
+

configs/light_lpi4a_plastic_defconfig

@@ -0,0 +1,119 @@
+CONFIG_RISCV=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_ENV_SIZE=0x20000
+CONFIG_ENV_OFFSET=0xe0000
+CONFIG_NR_DRAM_BANKS=8
+CONFIG_SPL=y
+CONFIG_SMP=y
+CONFIG_TARGET_LIGHT_C910=y
+CONFIG_TARGET_LIGHT_FM_C910_LPI4A=y
+# CONFIG_THEAD_PLIC is not set
+# CONFIG_THEAD_LIGHT_TIMER is not set
+# CONFIG_THEAD_LIGHT_DIGITAL_SENSOR is not set
+CONFIG_ARCH_RV64I=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_BUILD_TARGET="u-boot-with-spl.bin"
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_DISPLAY_BOARDINFO=y
+# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
+CONFIG_SPL_RAM_SUPPORT=y
+CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SYS_PROMPT="LicheeLaptop4A # "
+CONFIG_DDR_LP4X_3733_DUALRANK=y
+# CONFIG_DDR_LP4_3733_DUALRANK is not set
+CONFIG_DDR_BOARD_CONFIG=y
+CONFIG_CMD_BOOT_SLAVE=y
+CONFIG_CMD_ERASEENV=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_DDR_SCAN=y
+CONFIG_DDR_PRBS_TEST=n
+# CONFIG_DOS_PARTITION is not set
+# CONFIG_ISO_PARTITION is not set
+CONFIG_PARTITION_TYPE_GUID=y
+CONFIG_OF_EMBED=y
+CONFIG_DEFAULT_DEVICE_TREE="light-lpi4a-laptop"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SPL_CLK=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_UDP_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x10000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_DW=y
+CONFIG_DWAPB_GPIO=y
+# CONFIG_MMC_SPI is not set
+CONFIG_MMC_VERBOSE=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_SNPS=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SNPS=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MMC_RPMB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_SPI_NAND=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_PHY_REALTEK=y
+CONFIG_RTL8211E_PINE64_GIGABIT_FIX=y
+CONFIG_RTL8211X_PHY_FORCE_MASTER=y
+CONFIG_RTL8211F_PHY_FORCE_EEE_RXC_ON=y
+CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_DESIGNWARE_SPI=y
+CONFIG_DESIGNWARE_QSPI=y
+CONFIG_USB=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="U-Boot-THEAD"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1234
+CONFIG_USB_GADGET_PRODUCT_NUM=0x8888
+CONFIG_USB_FUNCTION_MASS_STORAGE=y
+# CONFIG_SPL_USE_TINY_PRINTF is not set
+# CONFIG_EFI_LOADER is not set
+# CONFIG_LIGHT_SEC_BOOT is not set
+CONFIG_DEFAULT_FDT_FILE="thead/th1520-lpi4a-plastic.dtb"
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_DM_VIDEO=y
+CONFIG_PHY=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_CMD_BMP=y
+CONFIG_VIDEO_BRIDGE=y
+CONFIG_DM_PCA953X=y
+CONFIG_VIDEO_VS_DPU=y
+CONFIG_VIDEO_LCD_ILITEK_ILI9881C=y
+CONFIG_VIDEO_DW_DSI_LIGHT=y
+CONFIG_VIDEO_DW_DPHY=y
+CONFIG_VIDEO_DW_DSI_HOST=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_PMIC_VOL_INIT=y
+CONFIG_DDR_REGU_0V6=600000
+CONFIG_DDR_REGU_0V8=800000
+CONFIG_DDR_REGU_1V1=1100000
+CONFIG_BOARD_RNG_SEED=y
+CONFIG_FIXUP_MEMORY_REGION=y
+CONFIG_MISC=y
+CONFIG_LIGHT_AON_CONF=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+# CONFIG_DOS_PARTITION is not set
+CONFIG_CMD_USB=y
+

configs/light_lpi4a_pocket_defconfig

@@ -0,0 +1,119 @@
+CONFIG_RISCV=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_ENV_SIZE=0x20000
+CONFIG_ENV_OFFSET=0xe0000
+CONFIG_NR_DRAM_BANKS=8
+CONFIG_SPL=y
+CONFIG_SMP=y
+CONFIG_TARGET_LIGHT_C910=y
+CONFIG_TARGET_LIGHT_FM_C910_LPI4A=y
+# CONFIG_THEAD_PLIC is not set
+# CONFIG_THEAD_LIGHT_TIMER is not set
+# CONFIG_THEAD_LIGHT_DIGITAL_SENSOR is not set
+CONFIG_ARCH_RV64I=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_BUILD_TARGET="u-boot-with-spl.bin"
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_DISPLAY_BOARDINFO=y
+# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
+CONFIG_SPL_RAM_SUPPORT=y
+CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SYS_PROMPT="LicheePocket4A # "
+CONFIG_DDR_LP4X_3733_DUALRANK=y
+# CONFIG_DDR_LP4_3733_DUALRANK is not set
+CONFIG_DDR_BOARD_CONFIG=y
+CONFIG_CMD_BOOT_SLAVE=y
+CONFIG_CMD_ERASEENV=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_DDR_SCAN=y
+CONFIG_DDR_PRBS_TEST=n
+# CONFIG_DOS_PARTITION is not set
+# CONFIG_ISO_PARTITION is not set
+CONFIG_PARTITION_TYPE_GUID=y
+CONFIG_OF_EMBED=y
+CONFIG_DEFAULT_DEVICE_TREE="light-lpi4a"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SPL_CLK=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_UDP_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x10000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_DW=y
+CONFIG_DWAPB_GPIO=y
+# CONFIG_MMC_SPI is not set
+CONFIG_MMC_VERBOSE=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_SNPS=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SNPS=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MMC_RPMB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_SPI_NAND=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_PHY_REALTEK=y
+CONFIG_RTL8211E_PINE64_GIGABIT_FIX=y
+CONFIG_RTL8211X_PHY_FORCE_MASTER=y
+CONFIG_RTL8211F_PHY_FORCE_EEE_RXC_ON=y
+CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_DESIGNWARE_SPI=y
+CONFIG_DESIGNWARE_QSPI=y
+CONFIG_USB=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="U-Boot-THEAD"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1234
+CONFIG_USB_GADGET_PRODUCT_NUM=0x8888
+CONFIG_USB_FUNCTION_MASS_STORAGE=y
+# CONFIG_SPL_USE_TINY_PRINTF is not set
+# CONFIG_EFI_LOADER is not set
+# CONFIG_LIGHT_SEC_BOOT is not set
+CONFIG_DEFAULT_FDT_FILE="thead/th1520-lpi4a-pocket.dtb"
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_DM_VIDEO=y
+CONFIG_PHY=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_CMD_BMP=y
+CONFIG_VIDEO_BRIDGE=y
+CONFIG_DM_PCA953X=y
+CONFIG_VIDEO_VS_DPU=y
+CONFIG_VIDEO_LCD_ILITEK_ILI9881C=y
+CONFIG_VIDEO_DW_DSI_LIGHT=y
+CONFIG_VIDEO_DW_DPHY=y
+CONFIG_VIDEO_DW_DSI_HOST=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_PMIC_VOL_INIT=y
+CONFIG_DDR_REGU_0V6=600000
+CONFIG_DDR_REGU_0V8=800000
+CONFIG_DDR_REGU_1V1=1100000
+CONFIG_BOARD_RNG_SEED=y
+CONFIG_FIXUP_MEMORY_REGION=y
+CONFIG_MISC=y
+CONFIG_LIGHT_AON_CONF=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+# CONFIG_DOS_PARTITION is not set
+CONFIG_CMD_USB=y
+

configs/light_lpi4a_sec_defconfig

@@ -22,6 +22,7 @@ CONFIG_SYS_PROMPT="C910 Light# "
 CONFIG_DDR_LP4X_3733_DUALRANK=y
 # CONFIG_DDR_LP4_3733_DUALRANK is not set
 CONFIG_DDR_BOARD_CONFIG=y
+CONFIG_FIXUP_MEMORY_REGION=y
 CONFIG_CMD_BOOT_SLAVE=y
 CONFIG_CMD_ERASEENV=y
 CONFIG_CMD_GPT=y
@@ -32,7 +33,6 @@ CONFIG_CMD_I2C=y
 CONFIG_CMD_MEMTEST=y
 CONFIG_DDR_SCAN=y
 CONFIG_DDR_PRBS_TEST=n
-# CONFIG_DOS_PARTITION is not set
 # CONFIG_ISO_PARTITION is not set
 CONFIG_PARTITION_TYPE_GUID=y
 CONFIG_OF_EMBED=y
@@ -77,6 +77,9 @@ CONFIG_SPI=y
 CONFIG_DESIGNWARE_SPI=y
 CONFIG_DESIGNWARE_QSPI=y
 CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_DWC3=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_MANUFACTURER="U-Boot-THEAD"
@@ -93,10 +96,13 @@ CONFIG_PHY=y
 CONFIG_REGMAP=y
 CONFIG_SYSCON=y
 CONFIG_CMD_BMP=y
+CONFIG_CMD_USB=y
 CONFIG_VIDEO_BRIDGE=y
 CONFIG_DM_PCA953X=y
 CONFIG_VIDEO_VS_DPU=y
-CONFIG_VIDEO_LCD_ILITEK_ILI9881C=y
+CONFIG_VIDEO_LCD_ILITEK_ILI9881C=n
+CONFIG_VIDEO_LCD_JD9365DA=y
+#CONFIG_VIDEO_LCD_CUSTOM_LOGO=y
 CONFIG_VIDEO_DW_DSI_LIGHT=y
 CONFIG_VIDEO_DW_DPHY=y
 CONFIG_VIDEO_DW_DSI_HOST=y
@@ -105,3 +111,5 @@ CONFIG_PMIC_VOL_INIT=y
 CONFIG_DDR_REGU_0V6=600000
 CONFIG_DDR_REGU_0V8=800000
 CONFIG_DDR_REGU_1V1=1100000
+CONFIG_MISC=y
+CONFIG_LIGHT_AON_CONF=y

configs/light_milkv_meles_16g_defconfig

@@ -0,0 +1,94 @@
+CONFIG_RISCV=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_ENV_SIZE=0x20000
+CONFIG_ENV_OFFSET=0xe0000
+CONFIG_NR_DRAM_BANKS=8
+CONFIG_SPL=y
+CONFIG_SMP=y
+CONFIG_TARGET_LIGHT_C910=y
+CONFIG_PMIC_VOL_INIT=y
+CONFIG_TARGET_LIGHT_FM_C910_MILKV_MELES=y
+CONFIG_DDR_LP4X_3733_DUALRANK=y
+CONFIG_DDR_DDP=y
+CONFIG_DDR_BOARD_CONFIG=y
+CONFIG_ARCH_RV64I=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_BUILD_TARGET="u-boot-with-spl.bin"
+CONFIG_DEFAULT_FDT_FILE="thead/th1520-milkv-meles-16g.dtb"
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_DISPLAY_BOARDINFO=y
+# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
+CONFIG_SPL_RAM_SUPPORT=y
+CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SYS_PROMPT="Milk-V Meles 16G# "
+CONFIG_CMD_BOOT_SLAVE=y
+CONFIG_CMD_ERASEENV=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_DDR_SCAN=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_EXT4_WRITE=y
+# CONFIG_DOS_PARTITION is not set
+# CONFIG_ISO_PARTITION is not set
+CONFIG_PARTITION_TYPE_GUID=y
+CONFIG_OF_EMBED=y
+CONFIG_DEFAULT_DEVICE_TREE="light-milkv-meles"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_SPL_CLK=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_UDP_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x10000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_DM_GPIO=y
+CONFIG_DWAPB_GPIO=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_DW=y
+# CONFIG_MMC_SPI is not set
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_SNPS=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_MMC_SDHCI_SNPS=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_SPI_NAND=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_PHY_REALTEK=y
+CONFIG_RTL8211E_PINE64_GIGABIT_FIX=y
+CONFIG_RTL8211X_PHY_FORCE_MASTER=y
+CONFIG_RTL8211F_PHY_FORCE_EEE_RXC_ON=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_PHY=y
+CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_DESIGNWARE_SPI=y
+CONFIG_DESIGNWARE_QSPI=y
+CONFIG_USB=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="U-Boot-THEAD"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1234
+CONFIG_USB_GADGET_PRODUCT_NUM=0x8888
+CONFIG_SYS_WHITE_ON_BLACK=y
+# CONFIG_SPL_USE_TINY_PRINTF is not set
+CONFIG_OF_LIBFDT_OVERLAY=y
+# CONFIG_EFI_LOADER is not set
+CONFIG_BOARD_RNG_SEED=y
+CONFIG_FIXUP_MEMORY_REGION=y
+CONFIG_MISC=y
+CONFIG_LIGHT_AON_CONF=y

configs/light_milkv_meles_dualrank_defconfig

@@ -88,3 +88,6 @@ CONFIG_SYS_WHITE_ON_BLACK=y
 CONFIG_OF_LIBFDT_OVERLAY=y
 # CONFIG_EFI_LOADER is not set
 CONFIG_BOARD_RNG_SEED=y
+CONFIG_FIXUP_MEMORY_REGION=y
+CONFIG_MISC=y
+CONFIG_LIGHT_AON_CONF=y

configs/light_milkv_meles_singlerank_defconfig

@@ -88,3 +88,6 @@ CONFIG_SYS_WHITE_ON_BLACK=y
 CONFIG_OF_LIBFDT_OVERLAY=y
 # CONFIG_EFI_LOADER is not set
 CONFIG_BOARD_RNG_SEED=y
+CONFIG_FIXUP_MEMORY_REGION=y
+CONFIG_MISC=y
+CONFIG_LIGHT_AON_CONF=y

drivers/fastboot/fb_command.c

@@ -310,6 +310,7 @@ static void flash(char *cmd_parameter, char *response)
 	char cmdbuf[32];
 	u32 block_cnt;
 	struct blk_desc *dev_desc;
+	disk_partition_t info;
 	int ret = 0;
 
 	if (strcmp(cmd_parameter, "uboot") == 0) {
@@ -351,8 +352,25 @@ static void flash(char *cmd_parameter, char *response)
 		memcpy((void *)LIGHT_TF_FW_ADDR, fastboot_buf_addr, image_size);
 	} else if ((strcmp(cmd_parameter, TEE_PART_NAME) == 0)) {
 		memcpy((void *)LIGHT_TEE_FW_ADDR, fastboot_buf_addr, image_size);
+	} else if ((strcmp(cmd_parameter, "boot") == 0)) {
+		dev_desc = blk_get_dev("mmc", CONFIG_FASTBOOT_FLASH_MMC_DEV);
+		if (!dev_desc || dev_desc->type == DEV_TYPE_UNKNOWN) {
+			fastboot_fail("invalid mmc device", response);
+			return;
+        }
+		/* if fastresume partition exists, earse the old image header */
+		if(part_get_info_by_name(dev_desc, "fastresume", &info)) {
+			printf(" find fastresume partition , erase the header:\n");
+			char * buf = memalign(CONFIG_SYS_CACHELINE_SIZE,4096);
+			if(!buf) {
+				printf(" fastresume partition header mem alloc failed\n");
+				return;
+			}
+			memset(buf,0xff,4096);
+			blk_dwrite(dev_desc, info.start, 4096/info.blksz, buf);
+			free(buf);
+		}
 	}
-
 	if(strcmp(cmd_parameter, "uboot") == 0 || (strcmp(cmd_parameter, "fw") == 0) ||
 	   (strcmp(cmd_parameter, "uImage") == 0) || (strcmp(cmd_parameter, "dtb") == 0) ||
 	   (strcmp(cmd_parameter, "rootfs") == 0) || (strcmp(cmd_parameter, "aon") == 0)) {

drivers/misc/Kconfig

@@ -439,4 +439,10 @@ config K3_AVS0
 	  optimized voltage from the efuse, so that it can be programmed
 	  to the PMIC on board.
 
+config LIGHT_AON_CONF
+	bool "Light aon config support"
+	depends on MISC
+	help
+	  Select this to enable aon config by dts.
+
 endmenu

drivers/misc/Makefile

@@ -68,3 +68,4 @@ obj-$(CONFIG_WINBOND_W83627) += winbond_w83627.o
 obj-$(CONFIG_JZ4780_EFUSE) += jz4780_efuse.o
 obj-$(CONFIG_MICROCHIP_FLEXCOM) += microchip_flexcom.o
 obj-$(CONFIG_K3_AVS0) += k3_avs.o
+obj-$(CONFIG_LIGHT_AON_CONF) += light_regu.o

drivers/misc/light_regu.h

@@ -0,0 +1,271 @@
+#ifndef __LIGHT_REGU_H__
+#define __LIGHT_REGU_H__
+
+typedef enum
+{
+	SOC_DVDD18_AON,		  /*da9063:  ldo-3 */
+	SOC_AVDD33_USB3,	  /*da9063:  ldo-9 */
+	SOC_DVDD08_AON,		  /*da9063:  ldo-2 */
+	SOC_APCPU_DVDD_DVDDM, /*da9063:  vbcore1 & vbcore2*/
+	SOC_DVDD08_DDR,		  /*da9063:  buckperi */
+	SOC_VDD_DDR_1V8,	  /*da9063:  ldo-4  */
+	SOC_VDD_DDR_1V1,	  /*da9063:  buckmem & buckio  */
+	SOC_VDD_DDR_0V6,	  /*da9063:  buckpro */
+	SOC_DVDD18_AP,		  /*da9063:  ldo-11 */
+	SOC_DVDD08_AP,		  /*da9121:  da9121_ex */
+	SOC_AVDD08_MIPI_HDMI, /*da9063:  ldo-1  */
+	SOC_AVDD18_MIPI_HDMI, /*da9063:  ldo-5  */
+	SOC_DVDD33_EMMC,	  /*da9063:  ldo-10 */
+	SOC_DVDD18_EMMC,	  /*slg51000:ldo-3 */
+	SOC_DOVDD18_SCAN,	  /*da9063:  ldo-6 */
+	SOC_VEXT_2V8,		  /*da9063:  ldo-7 */
+	SOC_DVDD12_SCAN,	  /*da9063:  ldo-8 */
+	SOC_AVDD28_SCAN_EN,	  /*da9063:  gpio-4,SGM2019-ADJ */
+	SOC_AVDD28_RGB,		  /*slg51000:ldo-1 */
+	SOC_DOVDD18_RGB,	  /*slg51000:ldo-4 */
+	SOC_DVDD12_RGB,		  /*slg51000:ldo-5 */
+	SOC_AVDD25_IR,		  /*slg51000:ldo-2 */
+	SOC_DOVDD18_IR,		  /*slg51000:ldo-7 */
+	SOC_DVDD12_IR,		  /*slg51000:ldo-6 */
+	SOC_ADC_VREF,
+	SOC_LCD0_EN,
+	SOC_VEXT_1V8,
+
+	SOC_REGU_INVALID = 0xFF
+} soc_virtual_id_en;
+
+#define REGU_DTS_NAME "light-regu-reg"
+#define AON_CONF_NAME "aon_pmic_config"
+#define PMIC_DEV_DTS_NAME "pmic-dev"
+#define PMIC_PARENT_CTRL_NAME "pmic_ctrl_info"
+#define REGU_ID_CONF_NAME "regu_config"
+#define REGU_ID_NAME "regu_id"
+#define COUPLING_ID_INFO_NAME "coupling_info"
+
+#define PMIC_DEV_ENABLE_WDT (1U << 0)
+#define PMIC_DEV_ENABLE_ERR_IO (1U << 1)
+#define PMIC_DEV_ENABLE_LPM_IO (1U << 2)
+
+#define HW_ID_NO_SOFT_AUTO_ON (0xff)
+#define HW_ID_NO_SOFT_AUTO_OFF (0xff)
+#define HW_ID_INVALID (0xff)
+#define PMIC_ID_INVALID (0xff)
+#define REGU_SUB_ID_INVALID (0xff)
+
+#define REGU_EXT_ID_NAME_LEN 30
+#define PMIC_DEV_NAME_LEN 20
+#define PMIC_DEV_VERSION_LEN 20
+
+#define PMIC_MAX_HW_ID_NUM 3
+#define PMIC_MAX_COUPLING_NUM 3
+
+#define AON_WAKEUP_BY_GPIO (1 << 0)
+#define AON_WAKEUP_BY_RTC (1 << 1)
+
+#define AON_CONFIG_MAGIC "AON_CONFIG"
+#define UBOOT_CONFIG_MAGIC "UBOOT_SET"
+#define AON_CONFIG_VERSION "1.0.0"
+
+typedef enum
+{
+	HW_ID_ACTIVATE_HIGH = 0U,
+	HW_ID_ACTIVATE_LOW = 1U,
+} hw_activate_status_en;
+
+typedef struct __packed
+{
+	uint8_t pmic_id;
+	uint8_t io_hw_id;
+	uint8_t activate_status;
+} pmic_parent_hw_io_ctrl_info_t;
+
+typedef struct __packed
+{
+	uint8_t on_order;
+	uint8_t on_delay_ms;
+	uint32_t init_target_uv;
+} regu_soft_power_ctrl_on_t;
+
+typedef struct __packed
+{
+	uint8_t off_order;
+	uint8_t off_delay_ms;
+} regu_soft_power_ctrl_off_t;
+
+typedef struct __packed
+{
+	regu_soft_power_ctrl_on_t on_info;
+	regu_soft_power_ctrl_off_t off_info;
+} regu_soft_power_ctrl_t;
+
+typedef struct __packed
+{
+	uint8_t id0;
+	uint8_t id1;
+	int8_t max_spread; // mv/10
+	int8_t min_spread; // mv/10
+} coupling_desc_t;
+
+typedef enum
+{
+	GPIO_IRQ_MODE_RISING_EDGE = 0, ///< Interrupt mode for rising edge
+	GPIO_IRQ_MODE_FALLING_EDGE,	   ///< Interrupt mode for falling edge
+	GPIO_IRQ_MODE_BOTH_EDGE,	   ///< Interrupt mode for both edge
+	GPIO_IRQ_MODE_LOW_LEVEL,	   ///< Interrupt mode for low level
+	GPIO_IRQ_MODE_HIGH_LEVEL,	   ///< Interrupt mode for high level
+} csi_gpio_irq_mode_t;
+
+typedef enum
+{
+	IIC_ADDRESS_7BIT = 0U, ///< 7-bit address mode
+	IIC_ADDRESS_10BIT	   ///< 10-bit address mode
+} csi_iic_addr_mode_t;
+
+typedef enum
+{
+	IIC_BUS_SPEED_STANDARD = 0U, ///< Standard Speed  (<=100kHz)
+	IIC_BUS_SPEED_FAST,			 ///< Fast Speed      (<=400kHz)
+	IIC_BUS_SPEED_FAST_PLUS,	 ///< Fast plus Speed (<=  1MHz)
+	IIC_BUS_SPEED_HIGH			 ///< High Speed      (<=3.4MHz)
+} csi_iic_speed_t;
+
+typedef struct __packed
+{
+	uint8_t pmic_id;
+	uint8_t hw_id;
+	uint8_t benable;
+	pmic_parent_hw_io_ctrl_info_t parent_hw_info;
+	regu_soft_power_ctrl_t soft_power_ctrl_info;
+} pmic_hw_info_t;
+
+typedef struct __packed
+{
+	coupling_desc_t coupling_list[PMIC_MAX_COUPLING_NUM];
+	pmic_hw_info_t id[PMIC_MAX_HW_ID_NUM]; ///<  sub id1 for single-rail or first src of dual-rail
+} pmic_hw_id_t;
+
+typedef struct __packed
+{
+	uint8_t regu_ext_id;						 ///< virtual global regulator id
+	char regu_ext_id_name[REGU_EXT_ID_NAME_LEN]; ///< vitual regu-id name
+	pmic_hw_id_t sub;							 ///<  sub id set for dual-rail/single-rail regulator
+} csi_regu_id_t;
+
+typedef enum
+{
+	PMIC_CTRL_BY_AON_GPIO = 0U,
+	PMIC_CTRL_BY_PMIC_GPIO = 1U,
+	PMIC_CTRL_BY_NOTHINTG = 0xFF,
+} pmic_ctrl_info_en;
+
+typedef struct __packed
+{
+	uint8_t gpio_port;
+	uint8_t pin;
+	uint8_t activate_status;
+} pmic_ctrl_by_aon_info_t;
+
+typedef struct __packed
+{
+	uint8_t pmic_id;
+	uint8_t io_hw_id;
+	uint8_t activate_status;
+} pmic_ctrl_by_pmic_info_t;
+
+typedef struct __packed
+{
+	uint8_t pmic_ctrl_type;
+	union
+	{
+		pmic_ctrl_by_aon_info_t aon_io;
+		pmic_ctrl_by_pmic_info_t pmic_io;
+	} info;
+} pmic_parent_ctrl_info_t;
+
+typedef struct __packed
+{
+	uint8_t gpio_port;
+	uint8_t pin;
+	uint8_t trigger_mode;
+} pmic_interrupt_io_info_t;
+
+typedef struct __packed
+{
+	char device_name[PMIC_DEV_NAME_LEN];
+	char version_name[PMIC_DEV_VERSION_LEN];
+	uint8_t pmic_id;
+	uint8_t addr1;
+	uint8_t addr2;
+	uint8_t flag; /*support wdt|errio| lpm io*/
+	uint8_t slew_rate;
+	uint32_t wdt_len;
+	pmic_interrupt_io_info_t err_io_info;
+	pmic_interrupt_io_info_t lpm_io_info;
+	pmic_parent_ctrl_info_t ctrl_info;
+} pmic_dev_info_t;
+
+typedef struct
+{
+	soc_virtual_id_en id;
+	char virtual_id_name[REGU_EXT_ID_NAME_LEN];
+	int min_uv;
+	int max_uv;
+} soc_virtual_id_t;
+
+typedef struct
+{
+	int regu_num;
+	soc_virtual_id_t *regu_list;
+} virtual_regu_list_t;
+
+typedef struct
+{
+	int pmic_num;
+	pmic_dev_info_t *pmic_list;
+} pmic_dev_list_t;
+
+typedef struct
+{
+	int regu_id_num;
+	csi_regu_id_t *regu_id_list;
+} regu_id_list_t;
+
+typedef struct __packed
+{
+	uint8_t iic_id;	   ///< iic id
+	uint8_t addr_mode; ///< iic addr_mode  ---> csi_iic_addr_mode_t
+	uint8_t speed;	   ///< iic speed type  ---> csi_iic_speed_t
+	uint8_t reserved[1];
+} csi_pmic_if_config_t;
+
+struct mic_regu_platdata
+{
+	const char *name;
+	uint32_t wakeup_flag;
+	csi_pmic_if_config_t iic_config;
+	virtual_regu_list_t regu_list;
+	pmic_dev_list_t pmic_list;
+	regu_id_list_t regu_id_list;
+};
+
+typedef struct __packed
+{
+	csi_pmic_if_config_t iic_config;
+	uint8_t pmic_dev_num;
+	uint8_t regu_num;
+	uint32_t pmic_dev_list_offset;
+	uint32_t regu_id_list_offset;
+} aon_pmic_config_t;
+
+typedef struct __packed
+{
+	const char magic[11];
+	const char version[11];
+	const char uboot_set_magic[11];
+	uint8_t max_hw_id_num;
+	uint64_t aon_config_partition_size;
+	uint32_t wakeup_flag;
+	aon_pmic_config_t aon_pmic;
+} aon_config_t;
+
+#endif

drivers/misc/misc-uclass.c

@@ -13,7 +13,6 @@
  * general classes. A set of generic read, write and ioctl methods may
  * be used to access the device.
  */
-
 int misc_read(struct udevice *dev, int offset, void *buf, int size)
 {
 	const struct misc_ops *ops = device_get_ops(dev);

drivers/mmc/sdhci.c

@@ -38,9 +38,7 @@ static void sdhci_reset(struct sdhci_host *host, u8 mask)
 		timeout--;
 		udelay(1000);
 	}
-#ifdef CONFIG_TARGET_LIGHT_C910
-	mdelay(50);
-#endif
+
 }
 
 static void sdhci_cmd_done(struct sdhci_host *host, struct mmc_cmd *cmd)

drivers/usb/host/xhci-mem.c

@@ -34,7 +34,10 @@
  */
 void xhci_flush_cache(uintptr_t addr, u32 len)
 {
-	BUG_ON((void *)addr == NULL || len == 0);
+	// th1520 will load fw_dymaic.bin into 0x0
+	// so disable it
+	// load usb 0:2 0x0 fw_dynamic.bin
+	//BUG_ON((void *)addr == NULL || len == 0);
 
 	flush_dcache_range(addr & ~(CACHELINE_SIZE - 1),
 				ALIGN(addr + len, CACHELINE_SIZE));
@@ -49,7 +52,10 @@ void xhci_flush_cache(uintptr_t addr, u32 len)
  */
 void xhci_inval_cache(uintptr_t addr, u32 len)
 {
-	BUG_ON((void *)addr == NULL || len == 0);
+	// th1520 will load fw_dymaic.bin into 0x0
+	// so disable it
+	// load usb 0:2 0x0 fw_dynamic.bin
+	//BUG_ON((void *)addr == NULL || len == 0);
 
 	invalidate_dcache_range(addr & ~(CACHELINE_SIZE - 1),
 				ALIGN(addr + len, CACHELINE_SIZE));

drivers/video/Kconfig

@@ -357,7 +357,14 @@ config VIDEO_LCD_MINGJUN_070BI30IA2
 	select VIDEO_MIPI_DSI
 	help
 	Say Y here if you want to enable support for Mingjun 070BI30IA2
-	800x1280 DSI video mode panel.
+        800x1280 DSI video mode panel.
+
+config VIDEO_LCD_JD9365DA
+	bool "JD9365DA DSI LCD panel support"
+	depends on DM_VIDEO
+	select VIDEO_MIPI_DSI
+	help
+	Say Y here if you want to enable support for JD9365DA
 
 config VIDEO_LCD_CUSTOM_LOGO
 	bool "LCD CUSTOM logo support"

drivers/video/Makefile

@@ -70,6 +70,7 @@ obj-$(CONFIG_VIDEO_SIMPLE) += simplefb.o
 obj-$(CONFIG_VIDEO_TEGRA20) += tegra.o
 obj-$(CONFIG_VIDEO_VCXK) += bus_vcxk.o
 obj-$(CONFIG_VIDEO_VESA) += vesa.o
+obj-$(CONFIG_VIDEO_LCD_JD9365DA) += jadard-jd9365da-h3.o
 
 obj-y += bridge/
 obj-y += sunxi/

drivers/video/jadard-jd9365da-h3.c

@@ -0,0 +1,238 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2019 Radxa Limited
+ * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd.
+ *
+ * Author:
+ * - Jagan Teki <jagan@amarulasolutions.com>
+ * - Stephen Chen <stephen@radxa.com>
+ */
+
+#include <common.h>
+#include <backlight.h>
+#include <dm.h>
+#include <mipi_dsi.h>
+#include <panel.h>
+#include <asm/gpio.h>
+
+struct jadard_panel_desc {
+	const struct display_timing *timing;
+	unsigned long mode_flags;
+	enum mipi_dsi_pixel_format format;
+	unsigned int lanes;
+};
+
+struct panel_info {
+	const struct jadard_panel_desc *desc;
+	struct gpio_desc	reset;
+	struct gpio_desc	hsvcc;
+	struct gpio_desc	vspn3v3;
+	bool   prepared;
+	bool   enabled;
+};
+
+static int jd9365_get_display_timing(struct udevice *dev,
+		struct display_timing *timings)
+{
+	struct mipi_dsi_panel_plat *plat = dev_get_platdata(dev);
+	struct mipi_dsi_device *device = plat->device;
+	struct panel_info *pinfo = dev_get_priv(dev);
+
+	memcpy(timings, pinfo->desc->timing, sizeof(*timings));
+
+	device->lanes	   = pinfo->desc->lanes;
+	device->format	   = pinfo->desc->format;
+	device->mode_flags = pinfo->desc->mode_flags;
+
+	return 0;
+}
+
+static int jadard_prepare(struct udevice *panel)
+{
+	struct panel_info *pinfo = dev_get_priv(panel);
+	int ret;
+
+	if (pinfo->prepared)
+		return 0;
+	dm_gpio_set_value(&pinfo->reset, false);
+
+	/* Power the panel */
+	ret = dm_gpio_set_value(&pinfo->hsvcc, true);
+	if (ret) {
+		return ret;
+	}
+
+	mdelay(1);
+	ret = dm_gpio_set_value(&pinfo->vspn3v3, true);
+	if (ret) {
+		return ret;
+	}
+	mdelay(1);
+
+	dm_gpio_set_value(&pinfo->reset, true);
+	mdelay(10);
+
+	pinfo->prepared = true;
+
+	return 0;
+}
+
+static int jadard_enable(struct udevice *panel)
+{
+	struct mipi_dsi_panel_plat *plat = dev_get_platdata(panel);
+	struct mipi_dsi_device *dsi = plat->device;
+	struct panel_info *pinfo = dev_get_priv(panel);
+	u8 power_mode;
+	int ret;
+
+	if (pinfo->enabled)
+		return 0;
+
+	dsi->mode_flags |= MIPI_DSI_MODE_LPM;
+
+	/* sanity test for connection */
+	ret = mipi_dsi_dcs_get_power_mode(dsi, &power_mode);
+	if (ret) {
+		dev_warn(dsi->dev, "%s: failed to get power mode: %d\n", __func__, ret);
+		return ret;
+	}
+
+	ret = mipi_dsi_dcs_set_tear_on(dsi, MIPI_DSI_DCS_TEAR_MODE_VBLANK);
+	if (ret)
+		return ret;
+
+	ret = mipi_dsi_dcs_exit_sleep_mode(dsi);
+	if (ret)
+	{
+		return ret;
+	}
+
+	mdelay(10);
+
+	ret = mipi_dsi_dcs_set_display_on(dsi);
+	if (ret){
+		return ret;
+	}
+
+	pinfo->enabled = true;
+
+	return 0;
+}
+
+static int jd9365_panel_enable(struct udevice *dev)
+{
+	struct mipi_dsi_panel_plat *plat   = dev_get_platdata(dev);
+	struct mipi_dsi_device     *device = plat->device;
+	int ret;
+
+	ret = mipi_dsi_attach(device);
+	if (ret < 0)
+		return ret;
+
+	ret = jadard_enable(dev);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
+static const struct display_timing txd_jd9365_timing = {
+	.pixelclock.typ		= 74250000,
+	.hactive.typ		= 800,
+	.hfront_porch.typ	= 60,
+	.hback_porch.typ	= 60,
+	.hsync_len.typ		= 40,
+	.vactive.typ		= 1280,
+	.vfront_porch.typ	= 16,
+	.vback_porch.typ	= 16,
+	.vsync_len.typ		= 8,
+	.flags			=  DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
+};
+
+static const struct jadard_panel_desc jd9365_panel_desc = {
+	.timing = &txd_jd9365_timing,
+	.mode_flags = MIPI_DSI_MODE_VIDEO |  MIPI_DSI_MODE_VIDEO_BURST,
+	.format = MIPI_DSI_FMT_RGB888,
+	.lanes = 4,
+};
+
+static int jd9365_panel_ofdata_to_platdata(struct udevice *dev)
+{
+	struct panel_info *pinfo = dev_get_priv(dev);
+	int ret;
+
+	ret = gpio_request_by_name(dev, "reset-gpio", 0,
+			&pinfo->reset, GPIOD_IS_OUT);
+	if (ret) {
+		dev_err(dev, "Warning: cannot get reset GPIO\n");
+		if (ret != -ENOENT)
+			return ret;
+	}
+
+	ret = gpio_request_by_name(dev, "hsvcc-gpio", 0,
+			&pinfo->hsvcc, GPIOD_IS_OUT);
+	if (ret) {
+		dev_err(dev, "Warning: cannot get hsvcc GPIO\n");
+		if (ret != -ENOENT)
+			return ret;
+	}
+
+	ret = gpio_request_by_name(dev, "vspn3v3-gpio", 0,
+			&pinfo->vspn3v3, GPIOD_IS_OUT);
+	if (ret) {
+		dev_err(dev, "Warning: cannot get vspn3v3 GPIO\n");
+		if (ret != -ENOENT)
+			return ret;
+	}
+
+	return 0;
+}
+
+static int jadard_dsi_probe(struct udevice *panel)
+{
+	int ret;
+	struct panel_info *pinfo = dev_get_priv(panel);
+
+	pinfo->desc = (const struct jadard_panel_desc*)dev_get_driver_data(panel);
+
+	ret = jadard_prepare(panel);
+	if (ret) {
+		dev_err(panel, "failed to prepare panel : %d\n", ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+static int jadard_dsi_remove(struct udevice *panel)
+{
+	return 0;
+}
+
+static const struct panel_ops jd9365_panel_ops = {
+	.enable_backlight	= jd9365_panel_enable,
+	.get_display_timing	= jd9365_get_display_timing,
+};
+
+static const struct udevice_id panel_of_match[] = {
+	{
+		.compatible = "jadard,jd9365da-h3",
+		.data = (ulong)&jd9365_panel_desc,
+	},
+	{
+		/* sentinel */
+	}
+};
+
+U_BOOT_DRIVER(jadard_jd9365da) = {
+	.name 			  = "jadard_jd9365da",
+	.id			      = UCLASS_PANEL,
+	.of_match		  = panel_of_match,
+	.ops			  = &jd9365_panel_ops,
+	.ofdata_to_platdata	  = jd9365_panel_ofdata_to_platdata,
+	.probe			  = jadard_dsi_probe,
+	.remove			  = jadard_dsi_remove,
+	.platdata_auto_alloc_size = sizeof(struct mipi_dsi_panel_plat),
+	.priv_auto_alloc_size	  = sizeof(struct panel_info),
+};
+

include/configs/light-c910.h

@@ -30,10 +30,15 @@
 #define CONFIG_SYS_BOOTM_LEN        SZ_64M
 #define CONFIG_SYS_CACHELINE_SIZE   64
 
+#define CONFIG_CMD_READ 1
+
 #define SRAM_BASE_ADDR	 0xffe0000000
 #define PLIC_BASE_ADDR   0xffd8000000
 #define PMP_BASE_ADDR    0xffdc020000
 
+#define MINIMAL_DDR_DENSITY_MB (1*1024)
+#define MAXIMAL_DDR_DENSITY_MB (16*1024)
+#define UNIT_MB (1024*1024)
 
 /* Network Configuration */
 #define CONFIG_DW_ALTDESCRIPTOR
@@ -127,6 +132,8 @@
 #define ENV_STR_SERIAL 		"serial#=\0"
 #define ENV_KERNEL_KDUMP	"kdump_buf=0M\0"
 #endif
+/*public bootargs in mostly boards, make env 'set_booargs' shorter and clean */
+#define ENV_PUBLIC_BOOTARGS "pub_bootargs=rootfstype=ext4 rdinit=/sbin/init rootwait rw earlycon clk_ignore_unused\0"
 
 #define CONFIG_MISC_INIT_R
 
@@ -137,6 +144,8 @@
 	"pxefile_addr_r=0x00600000\0" \
 	"dtb_addr=0x03800000\0" \
 	"fdt_addr_r=0x03800000\0" \
+	"fdtoverlay_addr_r=0x03700000\0" \
+	"initrd_high=0x1a000000\0" \
 	"kernel_addr_r=0x00200000\0" \
 	"ramdisk_addr_r=0x06000000\0" \
 	"boot_conf_addr_r=0xc0000000\0" \
@@ -151,20 +160,25 @@
 	ENV_STR_BOARD \
 	"kernel_addr_r=0x00200000\0" \
 	"kdump_buf=180M\0" \
+	"boottype=mmc\0" \
 	"mmcbootpart=2\0" \
 	"default_mmcdev=1\0" \
-	"mmc_select=if test -e mmc ${default_mmcdev}:${mmcbootpart} ${boot_conf_file}; then mmcdev=1; else mmcdev=0; fi;\0" \
+	"emmc_dev=0\0" \
+	"sdcard_dev=1\0" \
+	"mmc_select=if test -e ${boottype} ${default_mmcdev}:${mmcbootpart} ${boot_conf_file}; then mmcdev=1; else mmcdev=0; fi;\0" \
 	"boot_conf_file=/extlinux/extlinux.conf\0" \
 	"uuid_rootfsA=80a5a8e9-c744-491a-93c1-4f4194fd690a\0" \
 	"uuid_swap=5ebcaaf0-e098-43b9-beef-1f8deedd135e\0" \
 	"partitions=name=table,size=2031KB;name=boot,size=500MiB,type=boot;name=swap,size=4096MiB,type=swap,uuid=${uuid_swap};name=root,size=-,type=linux,uuid=${uuid_rootfsA}\0" \
-	"gpt_partition=gpt write mmc ${mmcdev} $partitions\0" \
-	"load_aon=load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_aon_fpga.bin;cp.b $fwaddr $aon_ram_addr $filesize\0" \
-	"load_c906_audio=load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_c906_audio.bin;cp.b $fwaddr $audio_ram_addr $filesize\0" \
-	"load_str=load mmc ${mmcdev}:${mmcbootpart} $fwaddr str.bin;cp.b $fwaddr $str_ram_addr $filesize\0" \
-	"load_opensbi=load mmc ${mmcdev}:${mmcbootpart} $opensbi_addr fw_dynamic.bin\0" \
-	"bootcmd_load=run mmc_select; run load_aon; run load_c906_audio; run load_str; run load_opensbi\0" \
-	"bootcmd=run bootcmd_load; bootslave; sysboot mmc ${mmcdev}:${mmcbootpart} any $boot_conf_addr_r $boot_conf_file;\0" \
+	"gpt_partition=gpt write mmc ${emmc_dev} $partitions\0" \
+	"sdcard_gpt_partition=gpt write mmc ${sdcard_dev} $partitions\0" \
+	"load_aon=load ${boottype} ${mmcdev}:${mmcbootpart} $fwaddr light_aon_fpga.bin;cp.b $fwaddr $aon_ram_addr $filesize;bootaon\0" \
+	"load_c906_audio=load ${boottype} ${mmcdev}:${mmcbootpart} $fwaddr light_c906_audio.bin;cp.b $fwaddr $audio_ram_addr $filesize\0" \
+	"load_str=load ${boottype} ${mmcdev}:${mmcbootpart} $fwaddr str.bin;cp.b $fwaddr $str_ram_addr $filesize\0" \
+	"load_opensbi=load ${boottype} ${mmcdev}:${mmcbootpart} $opensbi_addr fw_dynamic.bin\0" \
+	"load_usb=usb start; load usb ${mmcdev}:${mmcbootpart} ${boot_conf_addr_r} ${boot_conf_file}; if test -e usb ${mmcdev}:${mmcbootpart} ${boot_conf_file}; then setenv boottype usb; fi;\0" \
+	"bootcmd_load=run load_usb; run mmc_select; run load_aon; run load_c906_audio; run load_str; run load_opensbi\0" \
+	"bootcmd=run bootcmd_load; chk_hibernate; fixup_memory_region; bootslave; sysboot ${boottype} ${mmcdev}:${mmcbootpart} any $boot_conf_addr_r $boot_conf_file;\0" \
 	"fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
 	"\0"
 

include/dt-bindings/pmic/light_pmic.h

@@ -0,0 +1,55 @@
+#ifndef __LIGHT_PMIC_H_
+#define __LIGHT_PMIC_H_
+
+/*for da9063*/
+#define DA9063_ID_BCORE1   0
+#define DA9063_ID_BCORE2   1
+#define DA9063_ID_BUCKPRO  2
+#define DA9063_ID_BUCKMEM  3
+#define DA9063_ID_BUCKIO   4
+#define DA9063_ID_BUCKPERI 5
+#define DA9063_ID_LDO1     6
+#define DA9063_ID_LDO2     7
+#define DA9063_ID_LDO3     8
+#define DA9063_ID_LDO4     9
+#define DA9063_ID_LDO5     10
+#define DA9063_ID_LDO9     11
+#define DA9063_ID_LDO10    12
+#define DA9063_ID_LDO11    13
+#define DA9063_ID_LDO6     14
+#define DA9063_ID_LDO7     15
+#define DA9063_ID_LDO8     16
+#define DA9063_ID_GPIO4    17
+#define DA9063_ID_GPIO7    18
+
+/*for da9121*/
+#define DA9121_ID_BUCK1  0
+
+
+/* for slg51000*/
+
+#define SLG51000_ID_LDO1   0
+#define SLG51000_ID_LDO2   1
+#define SLG51000_ID_LDO3   2
+#define SLG51000_ID_LDO4   3
+#define SLG51000_ID_LDO5   4
+#define SLG51000_ID_LDO6   5
+#define SLG51000_ID_LDO7   6
+
+
+/* for ricoh567*/
+#define RICOH567_ID_DC1     0
+#define RICOH567_ID_DC2     1
+#define RICOH567_ID_DC3     2
+#define RICOH567_ID_DC4     3
+#define RICOH567_ID_LDO1    4
+#define RICOH567_ID_LDO2    5
+#define RICOH567_ID_LDO3    6
+#define RICOH567_ID_LDO4    7
+#define RICOH567_ID_LDO5    8
+#define RICOH567_ID_LDORTC1 9
+#define RICOH567_ID_LDORTC2 10
+#define RICOH567_ID_GPIO3   11
+
+
+#endif