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base: t-head:huiwei
Branches Tags
t-head:th1520 t-head:thead-sdk t-head:huiwei t-head:downclock-sd t-head:develop t-head:master
t-head:20260504 t-head:20251124 t-head:20250930 t-head:20250813 t-head:20250110 t-head:20241223 t-head:Linux_SDK_V2.0.2 t-head:20240720 t-head:20240529 t-head:Linux_SDK_V1.5.4 t-head:20240328 t-head:20240324 t-head:20240131 t-head:20240127 t-head:Linux_SDK_V1.4.2 t-head:Linux_SDK_V1.3.3 t-head:Linux_SDK_V1.2.1 t-head:Linux_SDK_V1.2.0 t-head:Linux_SDK_V1.1.2 t-head:Linux_SDK_V1.0.3 t-head:Linux_SDK_V1.0.2 t-head:Linux_SDK_V0.9.5
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compare: t-head:Linux_SDK_V1.4.2
Branches Tags
t-head:th1520 t-head:thead-sdk t-head:huiwei t-head:downclock-sd t-head:develop t-head:master
t-head:20260504 t-head:20251124 t-head:20250930 t-head:20250813 t-head:20250110 t-head:20241223 t-head:Linux_SDK_V2.0.2 t-head:20240720 t-head:20240529 t-head:Linux_SDK_V1.5.4 t-head:20240328 t-head:20240324 t-head:20240131 t-head:20240127 t-head:Linux_SDK_V1.4.2 t-head:Linux_SDK_V1.3.3 t-head:Linux_SDK_V1.2.1 t-head:Linux_SDK_V1.2.0 t-head:Linux_SDK_V1.1.2 t-head:Linux_SDK_V1.0.3 t-head:Linux_SDK_V1.0.2 t-head:Linux_SDK_V0.9.5

5 Commits
huiwei ... Linux_SDK_

Author SHA1 Message Date
thead_admin
ba628b63b3 Linux_SDK_V1.4.2 
Signed-off-by: thead_admin <occ_thead@service.alibaba.com>
 2023-12-24 19:20:14 +08:00
thead_admin
60c2e85ba7 Linux_SDK_V1.3.3 
Signed-off-by: thead_admin <occ_thead@service.alibaba.com>
 2023-12-24 19:19:50 +08:00
thead_admin
e14a461444 Linux_SDK_V1.2.1 
Signed-off-by: thead_admin <occ_thead@service.alibaba.com>
 2023-08-19 00:09:12 +08:00
thead_admin
6c027f3c8e fix ftbfs 2023-07-30 03:40:57 +08:00
Han Gao
644f3eb8ff Linux_SDK_V1.2.0 2023-07-30 03:39:06 +08:00
127 changed files with 1760 additions and 18287 deletions
Expand all files Collapse all files

141
.github/workflows/build.yml vendored
View File

@@ -1,141 +0,0 @@
name: thead-u-boot-build
on:
push:
tags:
- '*'
branches:
- '*'
pull_request:
workflow_dispatch:
schedule:
- cron: "0 2 * * *"
env:
xuantie_toolchain: https://occ-oss-prod.oss-cn-hangzhou.aliyuncs.com/resource//1705395627867
toolchain_file_name: Xuantie-900-gcc-linux-5.10.4-glibc-x86_64-V2.8.1-20240115.tar.gz
mainline_toolchain: https://github.com/riscv-collab/riscv-gnu-toolchain/releases/download/2024.04.12
mainline_toolchain_file_name: riscv64-glibc-ubuntu-22.04-gcc-nightly-2024.04.12-nightly.tar.gz
wget_alias: 'wget --retry-connrefused --waitretry=1 --read-timeout=20 --timeout=15 -t 0'
ARCH: riscv
CROSS_COMPILE: riscv64-unknown-linux-gnu-
jobs:
build:
strategy:
fail-fast: false
matrix:
name: [thead-gcc, gcc-13]
runs-on: ubuntu-22.04
steps:
- name: Install software
run: |
sudo apt update && \
sudo apt install -y gdisk dosfstools g++-12-riscv64-linux-gnu build-essential \
libncurses-dev gawk flex bison openssl libssl-dev tree \
dkms libelf-dev libudev-dev libpci-dev libiberty-dev autoconf device-tree-compiler
- name: Checkout uboot
uses: actions/checkout@v4
- name: uboot compile
run: |
mkdir output
if [[ ${{ matrix.name }} = "thead-gcc" ]]; then
${wget_alias} ${xuantie_toolchain}/${toolchain_file_name}
tar -xvf ${toolchain_file_name} -C /opt
export PATH="/opt/Xuantie-900-gcc-linux-5.10.4-glibc-x86_64-V2.8.1/bin:$PATH"
else
${wget_alias} ${mainline_toolchain}/${mainline_toolchain_file_name}
tar -xvf ${mainline_toolchain_file_name} -C /opt
export PATH="/opt/riscv/bin:$PATH"
fi
${CROSS_COMPILE}gcc -v
pushd $PWD
make light_lpi4a_16g_defconfig
make -j$(nproc)
find . -name "u-boot-with-spl.bin" | xargs -I{} cp -av {} ${GITHUB_WORKSPACE}/output/u-boot-with-spl-lpi4a-16g.bin
make clean
make light_lpi4a_defconfig
make -j$(nproc)
find . -name "u-boot-with-spl.bin" | xargs -I{} cp -av {} ${GITHUB_WORKSPACE}/output/u-boot-with-spl-lpi4a.bin
make clean
make light_lpi4a_console_defconfig
make -j$(nproc)
find . -name "u-boot-with-spl.bin" | xargs -I{} cp -av {} ${GITHUB_WORKSPACE}/output/u-boot-with-spl-lcon4a.bin
make clean
make light_lpi4a_console_16g_defconfig
make -j$(nproc)
find . -name "u-boot-with-spl.bin" | xargs -I{} cp -av {} ${GITHUB_WORKSPACE}/output/u-boot-with-spl-lcon4a-16g.bin
make clean
make light_lpi4a_cluster_defconfig
make -j$(nproc)
find . -name "u-boot-with-spl.bin" | xargs -I{} cp -av {} ${GITHUB_WORKSPACE}/output/u-boot-with-spl-lc4a.bin
make clean
make light_lpi4a_cluster_16g_defconfig
make -j$(nproc)
find . -name "u-boot-with-spl.bin" | xargs -I{} cp -av {} ${GITHUB_WORKSPACE}/output/u-boot-with-spl-lc4a-16g.bin
make clean
make light_beagle_defconfig
make -j$(nproc)
find . -name "u-boot-with-spl.bin" | xargs -I{} cp -av {} ${GITHUB_WORKSPACE}/output/u-boot-with-spl-beagle.bin
make clean
make light_a_val_defconfig
make -j$(nproc)
find . -name "u-boot-with-spl.bin" | xargs -I{} cp -av {} ${GITHUB_WORKSPACE}/output/u-boot-with-spl-vala.bin
make clean
make light_milkv_meles_dualrank_defconfig
make -j$(nproc)
find . -name "u-boot-with-spl.bin" | xargs -I{} cp -av {} ${GITHUB_WORKSPACE}/output/u-boot-with-spl-meles.bin
make clean
make light_milkv_meles_singlerank_defconfig
make -j$(nproc)
find . -name "u-boot-with-spl.bin" | xargs -I{} cp -av {} ${GITHUB_WORKSPACE}/output/u-boot-with-spl-meles-4g.bin
make clean
make light_huiwei_defconfig
make -j$(nproc)
find . -name "u-boot-with-spl.bin" | xargs -I{} cp -av {} ${GITHUB_WORKSPACE}/output/u-boot-with-spl-huiwei.bin
# mainline support
make clean
make light_lpi4a_defconfig
sed -i 's#thead/light-lpi4a.dtb#thead/th1520-lichee-pi-4a.dtb#' .config
make -j$(nproc)
find . -name "u-boot-with-spl.bin" | xargs -I{} cp -av {} ${GITHUB_WORKSPACE}/output/u-boot-with-spl-lpi4a-main.bin
make clean
make light_lpi4a_16g_defconfig
sed -i 's#thead/light-lpi4a-16gb.dtb#thead/th1520-lichee-pi-4a-16g.dtb#' .config
make -j$(nproc)
find . -name "u-boot-with-spl.bin" | xargs -I{} cp -av {} ${GITHUB_WORKSPACE}/output/u-boot-with-spl-lpi4a-16g-main.bin
make clean
make light_lpi4a_cluster_defconfig
sed -i 's#thead/light-lpi4a-cluster.dtb#thead/th1520-lichee-cluster-4a.dtb#' .config
make -j$(nproc)
find . -name "u-boot-with-spl.bin" | xargs -I{} cp -av {} ${GITHUB_WORKSPACE}/output/u-boot-with-spl-lc4a-main.bin
make clean
make light_lpi4a_cluster_16g_defconfig
sed -i 's#thead/light-lpi4a-cluster-16gb.dtb#thead/th1520-lichee-cluster-4a-16g.dtb#' .config
make -j$(nproc)
find . -name "u-boot-with-spl.bin" | xargs -I{} cp -av {} ${GITHUB_WORKSPACE}/output/u-boot-with-spl-lc4a-16g-main.bin
popd
tree ${GITHUB_WORKSPACE}/output
- name: 'Upload Artifact'
uses: actions/upload-artifact@v3
with:
name: thead-u-uboot-${{ matrix.name }}
path: output/*.bin
retention-days: 30
- name: 'Create release by tag'
uses: softprops/action-gh-release@v1
if: ${{ startsWith(github.ref, 'refs/tags/') && matrix.name == 'thead-gcc' }}
with:
files: output/*.bin
token: ${{ secrets.GITHUB_TOKEN }}

2
Makefile
View File

@@ -757,8 +757,6 @@ libs-y += drivers/net/phy/
libs-y += drivers/power/ \
drivers/power/domain/ \
drivers/power/fuel_gauge/ \
drivers/power/charge/ \
drivers/mcu/ \
drivers/power/mfd/ \
drivers/power/pmic/ \
drivers/power/battery/ \

2
arch/Kconfig
View File

@@ -119,7 +119,6 @@ config SANDBOX
select SPI
select SUPPORT_OF_CONTROL
select SYSRESET_CMD_POWEROFF if CMD_POWEROFF
select SUPPORT_EXTENSION_SCAN
imply BITREVERSE
select BLOBLIST
imply CMD_DM
@@ -153,7 +152,6 @@ config SANDBOX
imply PHYLIB
imply DM_MDIO
imply DM_MDIO_MUX
imply CMD_EXTENSION
config SH
bool "SuperH architecture"

11
arch/riscv/Makefile
View File

@@ -24,16 +24,7 @@ ifeq ($(CONFIG_CMODEL_MEDANY),y)
CMODEL = medany
endif
RISCV_MARCH = $(ARCH_BASE)$(ARCH_A)$(ARCH_C)
# Newer binutils versions default to ISA spec version 20191213 which moves some
# instructions from the I extension to the Zicsr and Zifencei extensions.
toolchain-need-zicsr-zifencei := $(call cc-option-yn, -mabi=$(ABI) -march=$(RISCV_MARCH)_zicsr_zifencei)
ifeq ($(toolchain-need-zicsr-zifencei),y)
RISCV_MARCH := $(RISCV_MARCH)_zicsr_zifencei
endif
ARCH_FLAGS = -march=$(RISCV_MARCH) -mabi=$(ABI) \
ARCH_FLAGS = -march=$(ARCH_BASE)$(ARCH_A)$(ARCH_C) -mabi=$(ABI) \
-mcmodel=$(CMODEL)
PLATFORM_CPPFLAGS += $(ARCH_FLAGS)

11
arch/riscv/cpu/c9xx/cpu.c
View File

@@ -125,11 +125,10 @@ void icache_enable(void)
#ifdef CONFIG_SPL_BUILD
#ifdef CONFIG_SPL_RISCV_MMODE
#ifdef CONFIG_TARGET_LIGHT_C910
// mhcr is 0x7c1
asm volatile (
"csrr x29, 0x7c1\n\t"
"csrr x29, mhcr\n\t"
"ori x28, x29, 0x1\n\t"
"csrw 0x7c1, x28\n\t"
"csrw mhcr, x28\n\t"
);
#endif
#endif
@@ -142,9 +141,9 @@ void dcache_enable(void)
#ifdef CONFIG_SPL_RISCV_MMODE
#ifdef CONFIG_TARGET_LIGHT_C910
asm volatile (
"csrr x29, 0x7c1\n\t"
"ori x28, x29, 0x2\n\t"
"csrw 0x7c1, x28\n\t"
"csrr x29, mhcr\n\t"
"ori x28, x29, 0x2\n\t"
"csrw mhcr, x28\n\t"
);
#endif
#endif

6
arch/riscv/cpu/c9xx/dram.c
View File

@@ -14,9 +14,9 @@ DECLARE_GLOBAL_DATA_PTR;
int dram_init(void)
{
#ifdef CONFIG_DDR_BOARD_CONFIG
// already setup during ddr initial flow
gd->bd->bi_memsize = gd->ram_size;
gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
extern unsigned long get_ddr_density(void);
// update ram_size from board config info
gd->ram_size = get_ddr_density();
return 0;
#else
return fdtdec_setup_mem_size_base();

9
arch/riscv/cpu/cpu.c
View File

@@ -27,15 +27,6 @@ u32 hart_lottery __attribute__((section(".data"))) = 0;
u32 available_harts_lock = 1;
#endif
void arch_setup_gd(struct global_data *gd_ptr)
{
// sync specific info from spl
gd_ptr->ram_size = gd->ram_size;
// setup gd ptr
gd = gd_ptr;
}
static inline bool supports_extension(char ext)
{
#ifdef CONFIG_CPU

28
arch/riscv/cpu/start.S
View File

@@ -104,6 +104,12 @@ call_board_init_f_0:
mv a0, sp
jal board_init_f_alloc_reserve
/*
* Set global data pointer here for all harts, uninitialized at this
* point.
*/
mv gp, a0
/* setup stack */
#ifdef CONFIG_SMP
/* tp: hart id */
@@ -121,34 +127,16 @@ call_board_init_f_0:
la t0, hart_lottery
li s2, 1
amoswap.w s2, t1, 0(t0)
beqz s2, call_board_init_f_1
/*
* Set global data pointer here for secondary harts, uninitialized at this
* point.
*/
mv gp, a0
jal wait_for_gd_init
bnez s2, wait_for_gd_init
#else
beqz tp, call_board_init_f_1
/*
* Set global data pointer here for secondary harts, uninitialized at this
* point.
*/
mv gp, a0
jal secondary_hart_loop
bnez tp, secondary_hart_loop
#endif
call_board_init_f_1:
#ifdef CONFIG_OF_PRIOR_STAGE
la t0, prior_stage_fdt_address
SREG s1, 0(t0)
#endif
/* Set global data pointer here for main hart */
jal board_init_f_init_reserve
/* save the boot hart id to global_data */

4
arch/riscv/dts/Makefile
View File

@@ -5,9 +5,7 @@ dtb-$(CONFIG_TARGET_SIFIVE_FU540) += hifive-unleashed-a00.dtb
dtb-$(CONFIG_TARGET_ICE_C910) += ice-c910.dtb
dtb-$(CONFIG_TARGET_LIGHT_EVB_MPW_C910) += light-evb-mpw-c910.dtb
dtb-$(CONFIG_TARGET_LIGHT_FPGA_FM_C910) += light-fpga-fm-c910.dtb
dtb-$(CONFIG_TARGET_LIGHT_C910) += light-a-ref.dtb light-b-ref.dtb light-a-val.dtb light-b-product.dtb light-a-product.dtb light-ant-ref.dtb light-beagle.dtb light-b-power.dtb light-lpi4a.dtb light-milkv-meles.dtb
dtb-$(CONFIG_TARGET_LIGHT_C910) += light-lpi4a-laptop.dtb
dtb-$(CONFIG_TARGET_LIGHT_C910) += light-huiwei.dtb
dtb-$(CONFIG_TARGET_LIGHT_C910) += light-a-ref.dtb light-b-ref.dtb light-a-val.dtb light-b-product.dtb light-a-product.dtb light-ant-ref.dtb light-beagle.dtb light-b-power.dtb light-lpi4a.dtb
targets += $(dtb-y)

440
arch/riscv/dts/light-a-val.dts
View File

@@ -1,7 +1,4 @@
/dts-v1/;
#include <dt-bindings/pmic/light_pmic.h>
/ {
model = "T-HEAD c910 light";
compatible = "thead,c910_light";
@@ -362,20 +359,6 @@
};
};
usb: usb@ffe7040000 {
compatible = "snps,dwc3";
reg = <0xff 0xe7040000 0x0 0x10000>;
interrupts = <68>;
reg-shift = <2>;
reg-io-width = <4>;
maximum-speed = "super-speed";
dr_mode = "host";
dma-mask = <0xf 0xffffffff>;
snps,usb3_lpm_capable;
snps,usb_sofitpsync;
status = "okay";
};
pwm: pwm@ffec01c000 {
compatible = "thead,pwm-light";
reg = <0xff 0xec01c000 0x0 0x4000>;
@@ -496,429 +479,6 @@
lcd-en-gpios = <&pcal6408ahk_a 2 0>; /* active high */
lcd-bias-en-gpios = <&pcal6408ahk_a 4 0>;/* active high */
};
aon {
compatible = "thead,light-aon";
status = "okay";
wakeup-by-gpio-on;
wakeup-by-rtc-on;
pd: light-aon-pd {
compatible = "thead,light-aon-pd";
#power-domain-cells = <1>;
};
light-regu-reg {
compatible = "thead,light-dialog-pmic";
status = "okay";
soc_dvdd18_aon_reg: soc_dvdd18_aon {
regulator-name = "soc_dvdd18_aon";
regulator-boot-on;
regulator-always-on;
};
soc_avdd33_usb3_reg: soc_avdd33_usb3 {
regulator-name = "soc_avdd33_usb3";
regulator-boot-on;
regulator-always-on;
};
soc_dvdd08_aon_reg: soc_dvdd08_aon {
regulator-name = "soc_dvdd08_aon";
regulator-boot-on;
regulator-always-on;
};
soc_apcpu_dvdd_dvddm_reg: soc_apcpu_dvdd_dvddm {
regulator-name = "soc_apcpu_dvdd_dvddm";
regulator-min-microvolt = <300000>;
regulator-max-microvolt = <1570000>;
regulator-boot-on;
regulator-always-on;
};
soc_dvdd08_ddr_reg: soc_dvdd08_ddr {
regulator-name = "soc_dvdd08_ddr";
regulator-boot-on;
regulator-always-on;
};
soc_vdd_ddr_1v8_reg: soc_vdd_ddr_1v8 {
regulator-name = "soc_vdd_ddr_1v8";
regulator-boot-on;
regulator-always-on;
};
soc_vdd_ddr_1v1_reg: soc_vdd_ddr_1v1 {
regulator-name = "soc_vdd_ddr_1v1";
regulator-boot-on;
regulator-always-on;
};
soc_vdd_ddr_0v6_reg: soc_vdd_ddr_0v6 {
regulator-name = "soc_vdd_ddr_0v6";
regulator-boot-on;
regulator-always-on;
};
soc_dvdd18_ap_reg: soc_dvdd18_ap {
regulator-name = "soc_dvdd18_ap";
regulator-boot-on;
regulator-always-on;
};
soc_dvdd08_ap_reg: soc_dvdd08_ap {
regulator-name = "soc_dvdd08_ap";
regulator-boot-on;
regulator-always-on;
};
soc_avdd08_mipi_hdmi_reg: soc_avdd08_mipi_hdmi {
regulator-name = "soc_avdd08_mipi_hdmi";
regulator-boot-on;
regulator-always-on;
};
soc_avdd18_mipi_hdmi_reg: soc_avdd18_mipi_hdmi {
regulator-name = "soc_avdd18_mipi_hdmi";
regulator-boot-on;
regulator-always-on;
};
soc_dvdd33_emmc_reg: soc_dvdd33_emmc {
regulator-name = "soc_dvdd33_emmc";
regulator-boot-on;
regulator-always-on;
};
soc_dvdd18_emmc_reg: soc_dvdd18_emmc {
regulator-name = "soc_vdd18_emmc";
regulator-boot-on;
regulator-always-on;
};
soc_dovdd18_scan_reg: soc_dovdd18_scan {
regulator-name = "soc_dovdd18_scan";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <3600000>;
};
soc_vext_2v8_reg: soc_vext_2v8 {
regulator-name = "soc_vext_2v8";
regulator-boot-on;
regulator-always-on;
};
soc_dvdd12_scan_reg: soc_dvdd12_scan {
regulator-name = "soc_dvdd12_scan";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <3600000>;
};
soc_avdd28_scan_en_reg: soc_avdd28_scan_en {
regulator-name = "soc_avdd28_scan_en";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
};
soc_avdd28_rgb_reg: soc_avdd28_rgb {
regulator-name = "soc_avdd28_rgb";
regulator-min-microvolt = <2200000>;
regulator-max-microvolt = <3475000>;
regulator-boot-on;
regulator-always-on;
};
soc_dovdd18_rgb_reg: soc_dovdd18_rgb {
regulator-name = "soc_dovdd18_rgb";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3600000>;
regulator-boot-on;
regulator-always-on;
};
soc_dvdd12_rgb_reg: soc_dvdd12_rgb {
regulator-name = "soc_dvdd12_rgb";
regulator-min-microvolt = <400000>;
regulator-max-microvolt = <1675000>;
regulator-boot-on;
regulator-always-on;
};
soc_avdd25_ir_reg: soc_avdd25_ir {
regulator-name = "soc_avdd25_ir";
regulator-min-microvolt = <2200000>;
regulator-max-microvolt = <3475000>;
regulator-boot-on;
regulator-always-on;
};
soc_dovdd18_ir_reg: soc_dovdd18_ir {
regulator-name = "soc_dovdd18_ir";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3600000>;
regulator-boot-on;
regulator-always-on;
};
soc_dvdd12_ir_reg: soc_dvdd12_ir {
regulator-name = "soc_dvdd12_ir";
regulator-min-microvolt = <400000>;
regulator-max-microvolt = <1675000>;
regulator-boot-on;
regulator-always-on;
};
};
aon_pmic_config {
compatible = "thead,light-pmic-conf";
status = "okay";
#address-cells = <1>;
#size-cells = <0>;
iic-config = <0 0 2>;
pmic_dev_0: pmic-dev@0 {
pmic-name = "dialog,da9063,v1";
pmic-addr = <0x5a 0x5b>;
pmic_wdt_on;
errio_gpio = <0 14 3>;
status = "okay";
};
pmic_dev_1: pmic-dev@1 {
pmic-name = "dialog,da9121,v1";
pmic-addr = <0x68>;
status = "okay";
};
pmic_dev_2: pmic-dev@2 {
pmic-name = "dialog,slg51000,v1";
pmic-addr = <0x75>;
status = "okay";
};
regu_config_0 {
reg_info = <&soc_dvdd18_aon_reg>;
status = "okay";
regu_id@0 {
pmic_dev = <&pmic_dev_0 DA9063_ID_LDO3>;
};
};
regu_config_1 {
reg_info = <&soc_avdd33_usb3_reg>;
status = "okay";
regu_id@0 {
pmic_dev = <&pmic_dev_0 DA9063_ID_LDO9>;
};
};
regu_config_2 {
reg_info = <&soc_dvdd08_aon_reg>;
status = "okay";
regu_id@0 {
pmic_dev = <&pmic_dev_0 DA9063_ID_LDO2>;
};
};
regu_config_3 {
reg_info = <&soc_apcpu_dvdd_dvddm_reg>;
status = "okay";
regu_id@0 {
pmic_dev = <&pmic_dev_0 DA9063_ID_BCORE1>;
auto_on_info = <0 0 800000>;
};
regu_id@1 {
pmic_dev = <&pmic_dev_0 DA9063_ID_BCORE2>;
auto_on_info = <1 0 800000>;
};
coupling_info@0 {
negative-min;
info = <0 1 5 30>;
};
};
regu_config_4 {
reg_info = <&soc_dvdd08_ddr_reg>;
status = "okay";
regu_id@0 {
pmic_dev = <&pmic_dev_0 DA9063_ID_BUCKPERI>;
};
};
regu_config_5 {
reg_info = <&soc_vdd_ddr_1v8_reg>;
status = "okay";
regu_id@0 {
pmic_dev = <&pmic_dev_0 DA9063_ID_LDO4>;
};
};
regu_config_6 {
reg_info = <&soc_vdd_ddr_1v1_reg>;
status = "okay";
regu_id@0 {
pmic_dev = <&pmic_dev_0 DA9063_ID_BUCKMEM>;
};
regu_id@1 {
pmic_dev = <&pmic_dev_0 DA9063_ID_BUCKIO>;
};
};
regu_config_7 {
reg_info = <&soc_vdd_ddr_0v6_reg>;
status = "okay";
regu_id@0 {
pmic_dev = <&pmic_dev_0 DA9063_ID_BUCKPRO>;
};
};
regu_config_8 {
reg_info = <&soc_dvdd18_ap_reg>;
status = "okay";
regu_id@0 {
pmic_dev = <&pmic_dev_0 DA9063_ID_LDO11>;
};
};
regu_config_9 {
reg_info = <&soc_avdd08_mipi_hdmi_reg>;
status = "okay";
regu_id@0 {
pmic_dev = <&pmic_dev_0 DA9063_ID_LDO1>;
};
};
regu_config_10 {
reg_info = <&soc_avdd18_mipi_hdmi_reg>;
status = "okay";
regu_id@0 {
pmic_dev = <&pmic_dev_0 DA9063_ID_LDO5>;
};
};
regu_config_11 {
reg_info = <&soc_dvdd33_emmc_reg>;
status = "okay";
regu_id@0 {
pmic_dev = <&pmic_dev_0 DA9063_ID_LDO10>;
};
};
regu_config_12 {
reg_info = <&soc_dovdd18_scan_reg>;
status = "okay";
regu_id@0 {
pmic_dev = <&pmic_dev_0 DA9063_ID_LDO6>;
auto_on_info = <2 1 1800000>;
auto_off_info = <7 1>;
};
};
regu_config_13 {
reg_info = <&soc_vext_2v8_reg>;
status = "okay";
regu_id@0 {
pmic_dev = <&pmic_dev_0 DA9063_ID_LDO7>;
auto_on_info = <3 1 2800000>;
auto_off_info = <8 1>;
};
};
regu_config_14 {
reg_info = <&soc_dvdd12_scan_reg>;
status = "okay";
regu_id@0 {
pmic_dev = <&pmic_dev_0 DA9063_ID_LDO8>;
auto_on_info = <4 1 1200000>;
auto_off_info = <9 1>;
};
};
regu_config_15 {
reg_info = <&soc_avdd28_scan_en_reg>;
status = "okay";
regu_id@0 {
pmic_dev = <&pmic_dev_0 DA9063_ID_GPIO4>;
auto_on_info = <5 1 2800000>;
auto_off_info = <6 1>;
};
};
regu_config_16 {
reg_info = <&soc_dvdd08_ap_reg>;
status = "okay";
regu_id@0 {
pmic_dev = <&pmic_dev_1 DA9121_ID_BUCK1>;
parent_pmic_dev = <&pmic_dev_0 2 0>;
};
};
regu_config_17 {
reg_info = <&soc_avdd28_rgb_reg>;
status = "okay";
regu_id@0 {
pmic_dev = <&pmic_dev_2 SLG51000_ID_LDO1>;
auto_on_info = <6 0 2800000>;
auto_off_info = <0 1>;
};
};
regu_config_18 {
reg_info = <&soc_avdd25_ir_reg>;
status = "okay";
regu_id@0 {
pmic_dev = <&pmic_dev_2 SLG51000_ID_LDO2>;
auto_on_info = <7 0 2500000>;
auto_off_info = <1 1>;
};
};
regu_config_19 {
reg_info = <&soc_dvdd18_emmc_reg>;
status = "okay";
regu_id@0 {
pmic_dev = <&pmic_dev_2 SLG51000_ID_LDO3>;
parent_pmic_dev = <&pmic_dev_0 7 0>;
};
};
regu_config_20 {
reg_info = <&soc_dovdd18_rgb_reg>;
status = "okay";
regu_id@0 {
pmic_dev = <&pmic_dev_2 SLG51000_ID_LDO4>;
auto_on_info = <8 0 1800000>;
auto_off_info = <2 1>;
};
};
regu_config_21 {
reg_info = <&soc_dvdd12_rgb_reg>;
status = "okay";
regu_id@0 {
pmic_dev = <&pmic_dev_2 SLG51000_ID_LDO5>;
auto_on_info = <9 0 1200000>;
auto_off_info = <3 1>;
};
};
regu_config_22 {
reg_info = <&soc_dvdd12_ir_reg>;
status = "okay";
regu_id@0 {
pmic_dev = <&pmic_dev_2 SLG51000_ID_LDO6>;
auto_on_info = <10 0 1200000>;
auto_off_info = <4 1>;
};
};
regu_config_23 {
reg_info = <&soc_dovdd18_ir_reg>;
status = "okay";
regu_id@0 {
pmic_dev = <&pmic_dev_2 SLG51000_ID_LDO7>;
auto_on_info = <11 0 1800000>;
auto_off_info = <5 1>;
};
};
};
};
};
chosen {

359
arch/riscv/dts/light-b-product.dts
View File

@@ -1,7 +1,4 @@
/dts-v1/;
#include <dt-bindings/pmic/light_pmic.h>
/ {
model = "T-HEAD c910 light";
compatible = "thead,c910_light";
@@ -472,362 +469,6 @@
lcd-en-gpios = <&gpio1_porta 9 0>; /* active high */
lcd-bias-en-gpios = <&gpio1_porta 10 0>;/* active high */
};
aon {
compatible = "thead,light-aon";
status = "okay";
wakeup-by-gpio-on;
wakeup-by-rtc-on;
pd: light-aon-pd {
compatible = "thead,light-aon-pd";
#power-domain-cells = <1>;
};
light-regu-reg {
compatible = "thead,light-dialog-pmic";
status = "okay";
soc_dvdd18_aon_reg: soc_dvdd18_aon {
regulator-name = "soc_dvdd18_aon";
regulator-boot-on;
regulator-always-on;
};
soc_avdd33_usb3_reg: soc_avdd33_usb3 {
regulator-name = "soc_avdd33_usb3";
regulator-boot-on;
regulator-always-on;
};
soc_dvdd08_aon_reg: soc_dvdd08_aon {
regulator-name = "soc_dvdd08_aon";
regulator-boot-on;
regulator-always-on;
};
soc_apcpu_dvdd_dvddm_reg: soc_apcpu_dvdd_dvddm {
regulator-name = "soc_apcpu_dvdd_dvddm";
regulator-min-microvolt = <300000>;
regulator-max-microvolt = <1570000>;
regulator-boot-on;
regulator-always-on;
};
soc_dvdd08_ddr_reg: soc_dvdd08_ddr {
regulator-name = "soc_dvdd08_ddr";
regulator-boot-on;
regulator-always-on;
};
soc_vdd_ddr_1v8_reg: soc_vdd_ddr_1v8 {
regulator-name = "soc_vdd_ddr_1v8";
regulator-boot-on;
regulator-always-on;
};
soc_vdd_ddr_1v1_reg: soc_vdd_ddr_1v1 {
regulator-name = "soc_vdd_ddr_1v1";
regulator-boot-on;
regulator-always-on;
};
soc_vdd_ddr_0v6_reg: soc_vdd_ddr_0v6 {
regulator-name = "soc_vdd_ddr_0v6";
regulator-boot-on;
regulator-always-on;
};
soc_dvdd18_ap_reg: soc_dvdd18_ap {
regulator-name = "soc_dvdd18_ap";
regulator-boot-on;
regulator-always-on;
};
soc_dvdd08_ap_reg: soc_dvdd08_ap {
regulator-name = "soc_dvdd08_ap";
regulator-boot-on;
regulator-always-on;
};
soc_avdd08_mipi_hdmi_reg: soc_avdd08_mipi_hdmi {
regulator-name = "soc_avdd08_mipi_hdmi";
regulator-boot-on;
regulator-always-on;
};
soc_avdd18_mipi_hdmi_reg: soc_avdd18_mipi_hdmi {
regulator-name = "soc_avdd18_mipi_hdmi";
regulator-boot-on;
regulator-always-on;
};
soc_dvdd33_emmc_reg: soc_dvdd33_emmc {
regulator-name = "soc_dvdd33_emmc";
regulator-boot-on;
regulator-always-on;
};
soc_dvdd18_emmc_reg: soc_dvdd18_emmc {
regulator-name = "soc_vdd18_emmc";
regulator-boot-on;
regulator-always-on;
};
soc_dovdd18_scan_reg: soc_dovdd18_scan {
regulator-name = "soc_dovdd18_scan";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <3600000>;
status = "disabled";
};
soc_vext_2v8_reg: soc_vext_2v8 {
regulator-name = "soc_vext_2v8";
regulator-boot-on;
regulator-always-on;
status = "disabled";
};
soc_dvdd12_scan_reg: soc_dvdd12_scan {
regulator-name = "soc_dvdd12_scan";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <3600000>;
status = "disabled";
};
soc_avdd28_scan_en_reg: soc_avdd28_scan_en {
regulator-name = "soc_avdd28_scan_en";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
status = "disabled";
};
soc_avdd28_rgb_reg: soc_avdd28_rgb {
regulator-name = "soc_avdd28_rgb";
regulator-min-microvolt = <2200000>;
regulator-max-microvolt = <3475000>;
regulator-boot-on;
regulator-always-on;
status = "disabled";
};
soc_dovdd18_rgb_reg: soc_dovdd18_rgb {
regulator-name = "soc_dovdd18_rgb";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3600000>;
regulator-boot-on;
regulator-always-on;
status = "disabled";
};
soc_dvdd12_rgb_reg: soc_dvdd12_rgb {
regulator-name = "soc_dvdd12_rgb";
regulator-min-microvolt = <400000>;
regulator-max-microvolt = <1675000>;
regulator-boot-on;
regulator-always-on;
status = "disabled";
};
soc_avdd25_ir_reg: soc_avdd25_ir {
regulator-name = "soc_avdd25_ir";
regulator-min-microvolt = <2200000>;
regulator-max-microvolt = <3475000>;
regulator-boot-on;
regulator-always-on;
status = "disabled";
};
soc_dovdd18_ir_reg: soc_dovdd18_ir {
regulator-name = "soc_dovdd18_ir";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3600000>;
regulator-boot-on;
regulator-always-on;
status = "disabled";
};
soc_dvdd12_ir_reg: soc_dvdd12_ir {
regulator-name = "soc_dvdd12_ir";
regulator-min-microvolt = <400000>;
regulator-max-microvolt = <1675000>;
regulator-boot-on;
regulator-always-on;
status = "disabled";
};
soc_adc_vref_reg: soc_adc_vref {
regulator-name = "soc_adc_vref";
};
soc_lcd0_en_reg: soc_lcd0_en {
regulator-name = "soc_lcd0_en";
};
soc_vext_1v8_reg: soc_vext_1v8 {
regulator-name = "soc_vext_1v8";
};
};
aon_pmic_config {
compatible = "thead,light-pmic-conf";
status = "okay";
#address-cells = <1>;
#size-cells = <0>;
iic-config = <0 0 2>;
pmic_dev_0: pmic-dev@0 {
pmic-name = "ricoh,rn5t567,v0";
pmic-addr = <0x31>;
pmic_wdt_on;
status = "okay";
};
pmic_dev_1: pmic-dev@1 {
pmic-name = "ricoh,rn5t567,v1";
pmic-addr = <0x32>;
status = "okay";
};
regu_config_0 {
reg_info = <&soc_dvdd18_aon_reg>;
status = "okay";
regu_id@0 {
pmic_dev = <&pmic_dev_0 RICOH567_ID_LDO4>;
};
};
regu_config_1 {
reg_info = <&soc_avdd33_usb3_reg>;
status = "okay";
regu_id@0 {
pmic_dev = <&pmic_dev_0 RICOH567_ID_LDO1>;
};
};
regu_config_2 {
reg_info = <&soc_dvdd08_aon_reg>;
status = "okay";
regu_id@0 {
pmic_dev = <&pmic_dev_0 RICOH567_ID_LDO3>;
};
};
regu_config_3 {
reg_info = <&soc_apcpu_dvdd_dvddm_reg>;
status = "okay";
regu_id@0 {
pmic_dev = <&pmic_dev_0 RICOH567_ID_DC3>;
auto_on_info = <2 0 800000>;
};
regu_id@1 {
pmic_dev = <&pmic_dev_0 RICOH567_ID_DC4>;
auto_on_info = <3 0 800000>;
};
coupling_info@0 {
negative-min;
info = <0 1 5 30>;
};
};
regu_config_4 {
reg_info = <&soc_dvdd08_ddr_reg>;
status = "okay";
regu_id@0 {
pmic_dev = <&pmic_dev_0 RICOH567_ID_DC1>;
};
};
regu_config_5 {
reg_info = <&soc_vdd_ddr_1v8_reg>;
status = "okay";
regu_id@0 {
pmic_dev = <&pmic_dev_0 RICOH567_ID_LDO2>;
};
};
regu_config_6 {
reg_info = <&soc_vdd_ddr_1v1_reg>;
status = "okay";
regu_id@0 {
pmic_dev = <&pmic_dev_1 RICOH567_ID_DC2>;
};
};
regu_config_7 {
reg_info = <&soc_vdd_ddr_0v6_reg>;
status = "okay";
regu_id@0 {
pmic_dev = <&pmic_dev_1 RICOH567_ID_DC1>;
};
};
regu_config_8 {
reg_info = <&soc_dvdd18_ap_reg>;
status = "okay";
regu_id@0 {
pmic_dev = <&pmic_dev_1 RICOH567_ID_LDO2>;
};
};
regu_config_9 {
reg_info = <&soc_avdd08_mipi_hdmi_reg>;
status = "okay";
regu_id@0 {
pmic_dev = <&pmic_dev_1 RICOH567_ID_LDO3>;
};
};
regu_config_10 {
reg_info = <&soc_avdd18_mipi_hdmi_reg>;
status = "okay";
regu_id@0 {
pmic_dev = <&pmic_dev_1 RICOH567_ID_LDO4>;
};
};
regu_config_11 {
reg_info = <&soc_dvdd33_emmc_reg>;
status = "okay";
regu_id@0 {
pmic_dev = <&pmic_dev_1 RICOH567_ID_LDO1>;
};
};
regu_config_12 {
reg_info = <&soc_dvdd08_ap_reg>;
status = "okay";
regu_id@0 {
pmic_dev = <&pmic_dev_1 RICOH567_ID_GPIO3>;
};
};
regu_config_13 {
reg_info = <&soc_dvdd18_emmc_reg>;
status = "okay";
regu_id@0 {
pmic_dev = <&pmic_dev_1 RICOH567_ID_DC3>;
};
};
regu_config_14 {
reg_info = <&soc_adc_vref_reg>;
status = "okay";
regu_id@0 {
pmic_dev = <&pmic_dev_1 RICOH567_ID_LDO5>;
};
};
regu_config_15 {
reg_info = <&soc_lcd0_en_reg>;
status = "okay";
regu_id@0 {
pmic_dev = <&pmic_dev_0 RICOH567_ID_LDO5>;
auto_on_info = <0 0 1800000>;
};
};
regu_config_16 {
reg_info = <&soc_vext_1v8_reg>;
status = "okay";
regu_id@0 {
pmic_dev = <&pmic_dev_1 RICOH567_ID_DC4>;
auto_on_info = <1 0 1800000>;
};
};
};
};
};
chosen {

1000
arch/riscv/dts/light-huiwei.dts
View File

File diff suppressed because it is too large Load Diff

46
arch/riscv/dts/light-lpi4a-laptop.dts
View File

@@ -1,46 +0,0 @@
#include "light-lpi4a.dts"
/ {
};
&i2c1 {
clock-frequency = <400000>;
status = "okay";
pcal6408ahk_c: gpio@20 {
compatible = "nxp,pca9557";
reg = <0x18>;
gpio-controller;
#gpio-cells = <2>;
};
};
&i2c3 {
clock-frequency = <400000>;
status = "okay";
pcal6408ahk_d: gpio@20 {
compatible = "nxp,pca9557";
reg = <0x18>;
gpio-controller;
#gpio-cells = <2>;
};
};
&lcd_backlight {
pwms = <&pwm 0 50000>;
brightness-levels = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35
36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100>;
default-brightness-level = <2>;
};
&panel0 {
compatible = "ilitek,ili9881c";
status = "okay";
backlight = <&lcd_backlight>;
// 5v power cycle
// TODO: move into regulator
reset-gpios = <&pcal6408ahk_c 0 0>; /* active low */
/delete-property/ lcd-en-gpios;
/delete-property/ lcd-bias-en-gpios;
};

404
arch/riscv/dts/light-lpi4a.dts
View File

@@ -1,7 +1,4 @@
/dts-v1/;
#include <dt-bindings/pmic/light_pmic.h>
/ {
model = "T-HEAD c910 light";
compatible = "thead,c910_light";
@@ -150,13 +147,6 @@
#address-cells = <1>;
#size-cells = <0>;
pcal6408ahk_d: gpio@20 {
compatible = "nxp,pca9557";
reg = <0x18>;
gpio-controller;
#gpio-cells = <2>;
};
};
i2c4: i2c@ffe7f28000{
@@ -167,6 +157,13 @@
#address-cells = <1>;
#size-cells = <0>;
pcal6408ahk_a: gpio@20 {
compatible = "nxp,pca9554";
reg = <0x20>;
gpio-controller;
#gpio-cells = <2>;
};
};
i2c5: i2c@fff7f2c000{
@@ -385,20 +382,6 @@
reg = <0xff 0xef600000 0x0 0x100>;
};
usb: usb@ffe7040000 {
compatible = "snps,dwc3";
reg = <0xff 0xe7040000 0x0 0x10000>;
interrupts = <68>;
reg-shift = <2>;
reg-io-width = <4>;
maximum-speed = "super-speed";
dr_mode = "host";
dma-mask = <0xf 0xffffffff>;
snps,usb3_lpm_capable;
snps,usb_sofitpsync;
status = "okay";
};
axiscr {
compatible = "thead,axiscr";
reg = <0xff 0xff004000 0x0 0x1000>;
@@ -489,376 +472,13 @@
default-brightness-level = <7>;
};
panel0: dsi_panel0 {
compatible = "jadard,jd9365da-h3";
ili9881c_panel {
compatible = "ilitek,ili9881c";
backlight = <&lcd_backlight>;
reset-gpio = <&pcal6408ahk_d 7 0>;
hsvcc-gpio = <&pcal6408ahk_d 6 1>;
vspn3v3-gpio = <&pcal6408ahk_d 5 1>;
reset-gpios = <&gpio1_porta 5 1>; /* active low */
lcd-en-gpios = <&pcal6408ahk_a 2 0>; /* active high */
lcd-bias-en-gpios = <&pcal6408ahk_a 4 0>;/* active high */
};
aon {
compatible = "thead,light-aon";
status = "okay";
wakeup-by-gpio-on;
wakeup-by-rtc-on;
pd: light-aon-pd {
compatible = "thead,light-aon-pd";
#power-domain-cells = <1>;
};
light-regu-reg {
compatible = "thead,light-dialog-pmic";
status = "okay";
soc_dvdd18_aon_reg: soc_dvdd18_aon {
regulator-name = "soc_dvdd18_aon";
regulator-boot-on;
regulator-always-on;
};
soc_avdd33_usb3_reg: soc_avdd33_usb3 {
regulator-name = "soc_avdd33_usb3";
regulator-boot-on;
regulator-always-on;
};
soc_dvdd08_aon_reg: soc_dvdd08_aon {
regulator-name = "soc_dvdd08_aon";
regulator-boot-on;
regulator-always-on;
};
soc_apcpu_dvdd_dvddm_reg: soc_apcpu_dvdd_dvddm {
regulator-name = "soc_apcpu_dvdd_dvddm";
regulator-min-microvolt = <300000>;
regulator-max-microvolt = <1570000>;
regulator-boot-on;
regulator-always-on;
};
soc_dvdd08_ddr_reg: soc_dvdd08_ddr {
regulator-name = "soc_dvdd08_ddr";
regulator-boot-on;
regulator-always-on;
};
soc_vdd_ddr_1v8_reg: soc_vdd_ddr_1v8 {
regulator-name = "soc_vdd_ddr_1v8";
regulator-boot-on;
regulator-always-on;
};
soc_vdd_ddr_1v1_reg: soc_vdd_ddr_1v1 {
regulator-name = "soc_vdd_ddr_1v1";
regulator-boot-on;
regulator-always-on;
};
soc_vdd_ddr_0v6_reg: soc_vdd_ddr_0v6 {
regulator-name = "soc_vdd_ddr_0v6";
regulator-boot-on;
regulator-always-on;
};
soc_dvdd18_ap_reg: soc_dvdd18_ap {
regulator-name = "soc_dvdd18_ap";
regulator-boot-on;
regulator-always-on;
};
soc_dvdd08_ap_reg: soc_dvdd08_ap {
regulator-name = "soc_dvdd08_ap";
regulator-boot-on;
regulator-always-on;
};
soc_avdd08_mipi_hdmi_reg: soc_avdd08_mipi_hdmi {
regulator-name = "soc_avdd08_mipi_hdmi";
regulator-boot-on;
regulator-always-on;
};
soc_avdd18_mipi_hdmi_reg: soc_avdd18_mipi_hdmi {
regulator-name = "soc_avdd18_mipi_hdmi";
regulator-boot-on;
regulator-always-on;
};
soc_dvdd33_emmc_reg: soc_dvdd33_emmc {
regulator-name = "soc_dvdd33_emmc";
regulator-boot-on;
regulator-always-on;
};
soc_dvdd18_emmc_reg: soc_dvdd18_emmc {
regulator-name = "soc_vdd18_emmc";
regulator-boot-on;
regulator-always-on;
};
soc_dovdd18_scan_reg: soc_dovdd18_scan {
regulator-name = "soc_dovdd18_scan";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <3600000>;
};
soc_vext_2v8_reg: soc_vext_2v8 {
regulator-name = "soc_vext_2v8";
regulator-boot-on;
regulator-always-on;
status = "disabled";
};
soc_dvdd12_scan_reg: soc_dvdd12_scan {
regulator-name = "soc_dvdd12_scan";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <3600000>;
};
soc_avdd28_scan_en_reg: soc_avdd28_scan_en {
regulator-name = "soc_avdd28_scan_en";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
};
soc_avdd28_rgb_reg: soc_avdd28_rgb {
regulator-name = "soc_avdd28_rgb";
regulator-min-microvolt = <2200000>;
regulator-max-microvolt = <3475000>;
regulator-boot-on;
regulator-always-on;
status = "disabled";
};
soc_dovdd18_rgb_reg: soc_dovdd18_rgb {
regulator-name = "soc_dovdd18_rgb";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3600000>;
regulator-boot-on;
regulator-always-on;
status = "disabled";
};
soc_dvdd12_rgb_reg: soc_dvdd12_rgb {
regulator-name = "soc_dvdd12_rgb";
regulator-min-microvolt = <400000>;
regulator-max-microvolt = <1675000>;
regulator-boot-on;
regulator-always-on;
status = "disabled";
};
soc_avdd25_ir_reg: soc_avdd25_ir {
regulator-name = "soc_avdd25_ir";
regulator-min-microvolt = <2200000>;
regulator-max-microvolt = <3475000>;
regulator-boot-on;
regulator-always-on;
status = "disabled";
};
soc_dovdd18_ir_reg: soc_dovdd18_ir {
regulator-name = "soc_dovdd18_ir";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3600000>;
regulator-boot-on;
regulator-always-on;
status = "disabled";
};
soc_dvdd12_ir_reg: soc_dvdd12_ir {
regulator-name = "soc_dvdd12_ir";
regulator-min-microvolt = <400000>;
regulator-max-microvolt = <1675000>;
regulator-boot-on;
regulator-always-on;
status = "disabled";
};
};
aon_pmic_config {
compatible = "thead,light-pmic-conf";
status = "okay";
#address-cells = <1>;
#size-cells = <0>;
iic-config = <0 0 2>;
pmic_dev_0: pmic-dev@0 {
pmic-name = "dialog,da9063,v1";
pmic-addr = <0x5a 0x5b>;
pmic_wdt_on;
status = "okay";
};
pmic_dev_1: pmic-dev@1 {
pmic-name = "dialog,da9121,v1";
pmic-addr = <0x68>;
status = "okay";
};
regu_config_0 {
reg_info = <&soc_dvdd18_aon_reg>;
status = "okay";
regu_id@0 {
pmic_dev = <&pmic_dev_0 DA9063_ID_LDO3>;
};
};
regu_config_1 {
reg_info = <&soc_avdd33_usb3_reg>;
status = "okay";
regu_id@0 {
pmic_dev = <&pmic_dev_0 DA9063_ID_LDO9>;
};
};
regu_config_2 {
reg_info = <&soc_dvdd08_aon_reg>;
status = "okay";
regu_id@0 {
pmic_dev = <&pmic_dev_0 DA9063_ID_LDO2>;
};
};
regu_config_3 {
reg_info = <&soc_apcpu_dvdd_dvddm_reg>;
status = "okay";
regu_id@0 {
pmic_dev = <&pmic_dev_0 DA9063_ID_BCORE1>;
auto_on_info = <0 0 800000>;
};
regu_id@1 {
pmic_dev = <&pmic_dev_0 DA9063_ID_BCORE2>;
auto_on_info = <1 0 800000>;
};
regu_id@2 {
pmic_dev = <&pmic_dev_0 DA9063_ID_BUCKIO>;
auto_on_info = <2 0 800000>;
};
coupling_info@0 {
negative-min;
info = <0 2 5 30>;
};
coupling_info@1 {
negative-min;
info = <1 2 5 30>;
};
};
regu_config_4 {
reg_info = <&soc_dvdd08_ddr_reg>;
status = "okay";
regu_id@0 {
pmic_dev = <&pmic_dev_0 DA9063_ID_BUCKPERI>;
};
};
regu_config_5 {
reg_info = <&soc_vdd_ddr_1v8_reg>;
status = "okay";
regu_id@0 {
pmic_dev = <&pmic_dev_0 DA9063_ID_LDO4>;
};
};
regu_config_6 {
reg_info = <&soc_vdd_ddr_1v1_reg>;
status = "okay";
regu_id@0 {
pmic_dev = <&pmic_dev_0 DA9063_ID_BUCKMEM>;
};
};
regu_config_7 {
reg_info = <&soc_vdd_ddr_0v6_reg>;
status = "okay";
regu_id@0 {
pmic_dev = <&pmic_dev_0 DA9063_ID_BUCKPRO>;
};
};
regu_config_8 {
reg_info = <&soc_dvdd18_ap_reg>;
status = "okay";
regu_id@0 {
pmic_dev = <&pmic_dev_0 DA9063_ID_LDO11>;
};
};
regu_config_9 {
reg_info = <&soc_avdd08_mipi_hdmi_reg>;
status = "okay";
regu_id@0 {
pmic_dev = <&pmic_dev_0 DA9063_ID_LDO1>;
};
};
regu_config_10 {
reg_info = <&soc_avdd18_mipi_hdmi_reg>;
status = "okay";
regu_id@0 {
pmic_dev = <&pmic_dev_0 DA9063_ID_LDO5>;
};
};
regu_config_11 {
reg_info = <&soc_dvdd33_emmc_reg>;
status = "okay";
regu_id@0 {
pmic_dev = <&pmic_dev_0 DA9063_ID_LDO10>;
};
};
regu_config_12 {
reg_info = <&soc_dovdd18_scan_reg>;
status = "okay";
regu_id@0 {
pmic_dev = <&pmic_dev_0 DA9063_ID_LDO6>;
auto_on_info = <3 1 1800000>;
auto_off_info = <1 1>;
};
};
regu_config_13 {
reg_info = <&soc_dvdd12_scan_reg>;
status = "okay";
regu_id@0 {
pmic_dev = <&pmic_dev_0 DA9063_ID_LDO8>;
auto_on_info = <4 1 1200000>;
auto_off_info = <2 1>;
};
};
regu_config_14 {
reg_info = <&soc_avdd28_scan_en_reg>;
status = "okay";
regu_id@0 {
pmic_dev = <&pmic_dev_0 DA9063_ID_LDO7>;
auto_on_info = <5 1 2800000>;
auto_off_info = <0 1>;
};
};
regu_config_15 {
reg_info = <&soc_dvdd08_ap_reg>;
status = "okay";
regu_id@0 {
pmic_dev = <&pmic_dev_1 DA9121_ID_BUCK1>;
parent_pmic_dev = <&pmic_dev_0 2 0>;
};
};
regu_config_16 {
reg_info = <&soc_dvdd18_emmc_reg>;
status = "okay";
regu_id@0 {
pmic_dev = <&pmic_dev_0 DA9063_ID_GPIO7>;
parent_pmic_dev = <&pmic_dev_0 7 0>;
};
};
};
};
};
chosen {

654
arch/riscv/dts/light-milkv-meles.dts
View File

@@ -1,654 +0,0 @@
/dts-v1/;
#include <dt-bindings/pmic/light_pmic.h>
/ {
model = "Milk-V Meles";
compatible = "milkv,meles", "thead,c910_light";
#address-cells = <2>;
#size-cells = <2>;
config {
select-gpio = <&gpio1_porta 16 0>;
};
memory@0 {
device_type = "memory";
reg = <0x0 0xc0000000 0x0 0x40000000>;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
timebase-frequency = <3000000>;
u-boot,dm-pre-reloc;
cpu@0 {
device_type = "cpu";
reg = <0>;
status = "okay";
compatible = "riscv";
riscv,isa = "rv64imafdcvsu";
mmu-type = "riscv,sv39";
u-boot,dm-pre-reloc;
};
};
soc {
#address-cells = <2>;
#size-cells = <2>;
compatible = "simple-bus";
ranges;
u-boot,dm-pre-reloc;
intc: interrupt-controller@ffd8000000 {
compatible = "riscv,plic0";
reg = <0xff 0xd8000000 0x0 0x04000000>;
status = "disabled";
};
dummy_apb: apb-clock {
compatible = "fixed-clock";
clock-frequency = <62500000>;
clock-output-names = "dummy_apb";
#clock-cells = <0>;
u-boot,dm-pre-reloc;
};
dummy_ahb: ahb-clock {
compatible = "fixed-clock";
clock-frequency = <250000000>;
clock-output-names = "core";
#clock-cells = <0>;
u-boot,dm-pre-reloc;
};
dummy_spi: spi-clock {
compatible = "fixed-clock";
clock-frequency = <396000000>;
clock-output-names = "dummy_spi";
#clock-cells = <0>;
u-boot,dm-pre-reloc;
};
dummy_qspi0: qspi0-clock {
compatible = "fixed-clock";
clock-frequency = <792000000>;
clock-output-names = "dummy_qspi0";
#clock-cells = <0>;
u-boot,dm-pre-reloc;
};
dummy_uart_sclk: uart-sclk-clock {
compatible = "fixed-clock";
clock-frequency = <100000000>;
clock-output-names = "dummy_uart_sclk";
#clock-cells = <0>;
u-boot,dm-pre-reloc;
};
dummy_i2c_icclk: i2c-icclk-clock {
compatible = "fixed-clock";
clock-frequency = <50000000>;
clock-output-names = "dummy_i2c_icclk";
#clock-cells = <0>;
u-boot,dm-pre-reloc;
};
dummy_dpu_pixclk: dpu-pix-clock {
compatible = "fixed-clock";
clock-frequency = <74250000>;
clock-output-names = "dummy_dpu_pixclk";
#clock-cells = <0>;
u-boot,dm-pre-reloc;
};
dummy_dphy_refclk: dphy-ref-clock {
compatible = "fixed-clock";
clock-frequency = <24000000>;
clock-output-names = "dummy_dpu_refclk";
#clock-cells = <0>;
u-boot,dm-pre-reloc;
};
serial@ffe7014000 {
compatible = "snps,dw-apb-uart";
reg = <0xff 0xe7014000 0x0 0x400>;
clocks = <&dummy_uart_sclk>;
clock-frequency = <100000000>;
clock-names = "baudclk";
reg-shift = <2>;
reg-io-width = <4>;
u-boot,dm-pre-reloc;
};
gmac0: ethernet@ffe7070000 {
compatible = "snps,dwmac";
reg = <0xff 0xe7070000 0x0 0x2000>;
clocks = <&dummy_apb>;
clock-names = "stmmaceth";
snps,pbl = <32>;
snps,fixed-burst;
phy-mode = "rgmii-id";
phy-handle = <&phy_88E1111_a>;
status = "okay";
mdio0 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,dwmac-mdio";
phy_88E1111_a: ethernet-phy@1 {
reg = <0x1>;
};
};
};
emmc: sdhci@ffe7080000 {
compatible = "snps,dwcmshc-sdhci";
reg = <0xff 0xe7080000 0x0 0x10000>;
index = <0x0>;
clocks = <&dummy_ahb>;
clock-frequency = <198000000>;
clock-names = "core";
max-frequency = <198000000>;
sdhci-caps-mask = <0x0 0x1000000>;
mmc-hs400-1_8v;
non-removable;
no-sdio;
no-sd;
bus-width = <8>;
voltage= "1.8v";
pull_up;
io_fixed_1v8;
fifo-mode;
u-boot,dm-pre-reloc;
};
sdhci0: sd@ffe7090000 {
compatible = "snps,dwcmshc-sdhci";
reg = <0xff 0xe7090000 0x0 0x10000>;
index = <0x1>;
clocks = <&dummy_ahb>;
clock-frequency = <198000000>;
max-frequency = <198000000>;
sd-uhs-sdr104;
pull_up;
clock-names = "core";
bus-width = <4>;
voltage= "3.3v";
};
gpio2: gpio@ffe7f34000 {
compatible = "snps,dw-apb-gpio";
reg = <0xff 0xe7f34000 0x0 0x1000>;
clocks = <&dummy_apb>;
#address-cells = <1>;
#size-cells = <0>;
gpio2_porta: gpio-controller@0 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
snps,nr-gpios = <32>;
reg = <0>;
};
};
gpio0: gpio@ffec005000 {
compatible = "snps,dw-apb-gpio";
reg = <0xff 0xec005000 0x0 0x1000>;
clocks = <&dummy_apb>;
#address-cells = <1>;
#size-cells = <0>;
gpio0_porta: gpio-controller@0 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
snps,nr-gpios = <32>;
reg = <0>;
};
};
gpio1: gpio@ffec006000 {
compatible = "snps,dw-apb-gpio";
reg = <0xff 0xec006000 0x0 0x1000>;
clocks = <&dummy_apb>;
#address-cells = <1>;
#size-cells = <0>;
gpio1_porta: gpio-controller@0 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
snps,nr-gpios = <32>;
reg = <0>;
};
};
axiscr {
compatible = "thead,axiscr";
reg = <0xff 0xff004000 0x0 0x1000>;
lock-read = "okay";
lock-write = "okay";
#address-cells = <2>;
#size-cells = <2>;
u-boot,dm-pre-reloc;
axiscr0: axisrc@0 {
device_type = "axiscr";
region = <0x00 0x00000000 0x00 0x80000000>; // 4KB align
status = "disabled";
#address-cells = <2>;
#size-cells = <2>;
u-boot,dm-pre-reloc;
};
axiscr1: axisrc@1 {
device_type = "axiscr";
region = <0x00 0x80000000 0x00 0x80000000>; // 4KB align
status = "disabled";
#address-cells = <2>;
#size-cells = <2>;
u-boot,dm-pre-reloc;
};
axiscr2: axisrc@2 {
device_type = "axiscr";
region = <0x01 0x00000000 0x00 0x80000000>; // 4KB align
status = "disabled";
#address-cells = <2>;
#size-cells = <2>;
u-boot,dm-pre-reloc;
};
};
axiparity {
compatible = "thead,axiparity";
reg = <0xff 0xff00c000 0x0 0x1000>;
lock = "okay";
#address-cells = <2>;
#size-cells = <2>;
u-boot,dm-pre-reloc;
axiparity0: axiparity@0 {
device_type = "axiparity";
region = <0x00 0x00000000 0x01 0x0000000>; // 4KB align
status = "disabled";
#address-cells = <2>;
#size-cells = <2>;
u-boot,dm-pre-reloc;
};
axiparity1: axiparity@1 {
device_type = "axiparity";
region = <0x01 0x00000000 0x01 0x00000000>; // 4KB align
status = "disabled";
#address-cells = <2>;
#size-cells = <2>;
u-boot,dm-pre-reloc;
};
};
aon {
compatible = "thead,light-aon";
status = "okay";
wakeup-by-gpio-on;
wakeup-by-rtc-on;
pd: light-aon-pd {
compatible = "thead,light-aon-pd";
#power-domain-cells = <1>;
};
light-regu-reg {
compatible = "thead,light-dialog-pmic";
status = "okay";
soc_dvdd18_aon_reg: soc_dvdd18_aon {
regulator-name = "soc_dvdd18_aon";
regulator-boot-on;
regulator-always-on;
};
soc_avdd33_usb3_reg: soc_avdd33_usb3 {
regulator-name = "soc_avdd33_usb3";
regulator-boot-on;
regulator-always-on;
};
soc_dvdd08_aon_reg: soc_dvdd08_aon {
regulator-name = "soc_dvdd08_aon";
regulator-boot-on;
regulator-always-on;
};
soc_apcpu_dvdd_dvddm_reg: soc_apcpu_dvdd_dvddm {
regulator-name = "soc_apcpu_dvdd_dvddm";
regulator-min-microvolt = <300000>;
regulator-max-microvolt = <1570000>;
regulator-boot-on;
regulator-always-on;
};
soc_dvdd08_ddr_reg: soc_dvdd08_ddr {
regulator-name = "soc_dvdd08_ddr";
regulator-boot-on;
regulator-always-on;
};
soc_vdd_ddr_1v8_reg: soc_vdd_ddr_1v8 {
regulator-name = "soc_vdd_ddr_1v8";
regulator-boot-on;
regulator-always-on;
};
soc_vdd_ddr_1v1_reg: soc_vdd_ddr_1v1 {
regulator-name = "soc_vdd_ddr_1v1";
regulator-boot-on;
regulator-always-on;
};
soc_vdd_ddr_0v6_reg: soc_vdd_ddr_0v6 {
regulator-name = "soc_vdd_ddr_0v6";
regulator-boot-on;
regulator-always-on;
};
soc_dvdd18_ap_reg: soc_dvdd18_ap {
regulator-name = "soc_dvdd18_ap";
regulator-boot-on;
regulator-always-on;
};
soc_dvdd08_ap_reg: soc_dvdd08_ap {
regulator-name = "soc_dvdd08_ap";
regulator-boot-on;
regulator-always-on;
};
soc_avdd08_mipi_hdmi_reg: soc_avdd08_mipi_hdmi {
regulator-name = "soc_avdd08_mipi_hdmi";
regulator-boot-on;
regulator-always-on;
};
soc_avdd18_mipi_hdmi_reg: soc_avdd18_mipi_hdmi {
regulator-name = "soc_avdd18_mipi_hdmi";
regulator-boot-on;
regulator-always-on;
};
soc_dvdd33_emmc_reg: soc_dvdd33_emmc {
regulator-name = "soc_dvdd33_emmc";
regulator-boot-on;
regulator-always-on;
};
soc_dvdd18_emmc_reg: soc_dvdd18_emmc {
regulator-name = "soc_vdd18_emmc";
regulator-boot-on;
regulator-always-on;
};
soc_dovdd18_scan_reg: soc_dovdd18_scan {
regulator-name = "soc_dovdd18_scan";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <3600000>;
};
soc_vext_2v8_reg: soc_vext_2v8 {
regulator-name = "soc_vext_2v8";
regulator-boot-on;
regulator-always-on;
status = "disabled";
};
soc_dvdd12_scan_reg: soc_dvdd12_scan {
regulator-name = "soc_dvdd12_scan";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <3600000>;
};
soc_avdd28_scan_en_reg: soc_avdd28_scan_en {
regulator-name = "soc_avdd28_scan_en";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
};
soc_avdd28_rgb_reg: soc_avdd28_rgb {
regulator-name = "soc_avdd28_rgb";
regulator-min-microvolt = <2200000>;
regulator-max-microvolt = <3475000>;
regulator-boot-on;
regulator-always-on;
status = "disabled";
};
soc_dovdd18_rgb_reg: soc_dovdd18_rgb {
regulator-name = "soc_dovdd18_rgb";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3600000>;
regulator-boot-on;
regulator-always-on;
status = "disabled";
};
soc_dvdd12_rgb_reg: soc_dvdd12_rgb {
regulator-name = "soc_dvdd12_rgb";
regulator-min-microvolt = <400000>;
regulator-max-microvolt = <1675000>;
regulator-boot-on;
regulator-always-on;
status = "disabled";
};
soc_avdd25_ir_reg: soc_avdd25_ir {
regulator-name = "soc_avdd25_ir";
regulator-min-microvolt = <2200000>;
regulator-max-microvolt = <3475000>;
regulator-boot-on;
regulator-always-on;
status = "disabled";
};
soc_dovdd18_ir_reg: soc_dovdd18_ir {
regulator-name = "soc_dovdd18_ir";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3600000>;
regulator-boot-on;
regulator-always-on;
status = "disabled";
};
soc_dvdd12_ir_reg: soc_dvdd12_ir {
regulator-name = "soc_dvdd12_ir";
regulator-min-microvolt = <400000>;
regulator-max-microvolt = <1675000>;
regulator-boot-on;
regulator-always-on;
status = "disabled";
};
};
aon_pmic_config {
compatible = "thead,light-pmic-conf";
status = "okay";
#address-cells = <1>;
#size-cells = <0>;
iic-config = <0 0 2>;
pmic_dev_0: pmic-dev@0 {
pmic-name = "dialog,da9063,v1";
pmic-addr = <0x5a 0x5b>;
pmic_wdt_on;
status = "okay";
};
pmic_dev_1: pmic-dev@1 {
pmic-name = "dialog,da9121,v1";
pmic-addr = <0x68>;
status = "okay";
};
regu_config_0 {
reg_info = <&soc_dvdd18_aon_reg>;
status = "okay";
regu_id@0 {
pmic_dev = <&pmic_dev_0 DA9063_ID_LDO3>;
};
};
regu_config_1 {
reg_info = <&soc_avdd33_usb3_reg>;
status = "okay";
regu_id@0 {
pmic_dev = <&pmic_dev_0 DA9063_ID_LDO9>;
};
};
regu_config_2 {
reg_info = <&soc_dvdd08_aon_reg>;
status = "okay";
regu_id@0 {
pmic_dev = <&pmic_dev_0 DA9063_ID_LDO2>;
};
};
regu_config_3 {
reg_info = <&soc_apcpu_dvdd_dvddm_reg>;
status = "okay";
regu_id@0 {
pmic_dev = <&pmic_dev_0 DA9063_ID_BCORE1>;
auto_on_info = <0 0 800000>;
};
regu_id@1 {
pmic_dev = <&pmic_dev_0 DA9063_ID_BCORE2>;
auto_on_info = <1 0 800000>;
};
regu_id@2 {
pmic_dev = <&pmic_dev_0 DA9063_ID_BUCKIO>;
auto_on_info = <2 0 800000>;
};
coupling_info@0 {
negative-min;
info = <0 2 5 30>;
};
coupling_info@1 {
negative-min;
info = <1 2 5 30>;
};
};
regu_config_4 {
reg_info = <&soc_dvdd08_ddr_reg>;
status = "okay";
regu_id@0 {
pmic_dev = <&pmic_dev_0 DA9063_ID_BUCKPERI>;
};
};
regu_config_5 {
reg_info = <&soc_vdd_ddr_1v8_reg>;
status = "okay";
regu_id@0 {
pmic_dev = <&pmic_dev_0 DA9063_ID_LDO4>;
};
};
regu_config_6 {
reg_info = <&soc_vdd_ddr_1v1_reg>;
status = "okay";
regu_id@0 {
pmic_dev = <&pmic_dev_0 DA9063_ID_BUCKMEM>;
};
};
regu_config_7 {
reg_info = <&soc_vdd_ddr_0v6_reg>;
status = "okay";
regu_id@0 {
pmic_dev = <&pmic_dev_0 DA9063_ID_BUCKPRO>;
};
};
regu_config_8 {
reg_info = <&soc_dvdd18_ap_reg>;
status = "okay";
regu_id@0 {
pmic_dev = <&pmic_dev_0 DA9063_ID_LDO11>;
};
};
regu_config_9 {
reg_info = <&soc_avdd08_mipi_hdmi_reg>;
status = "okay";
regu_id@0 {
pmic_dev = <&pmic_dev_0 DA9063_ID_LDO1>;
};
};
regu_config_10 {
reg_info = <&soc_avdd18_mipi_hdmi_reg>;
status = "okay";
regu_id@0 {
pmic_dev = <&pmic_dev_0 DA9063_ID_LDO5>;
};
};
regu_config_11 {
reg_info = <&soc_dvdd33_emmc_reg>;
status = "okay";
regu_id@0 {
pmic_dev = <&pmic_dev_0 DA9063_ID_LDO10>;
};
};
regu_config_12 {
reg_info = <&soc_dovdd18_scan_reg>;
status = "okay";
regu_id@0 {
pmic_dev = <&pmic_dev_0 DA9063_ID_LDO6>;
auto_on_info = <3 1 1800000>;
auto_off_info = <1 1>;
};
};
regu_config_13 {
reg_info = <&soc_dvdd12_scan_reg>;
status = "okay";
regu_id@0 {
pmic_dev = <&pmic_dev_0 DA9063_ID_LDO8>;
auto_on_info = <4 1 1200000>;
auto_off_info = <2 1>;
};
};
regu_config_14 {
reg_info = <&soc_avdd28_scan_en_reg>;
status = "okay";
regu_id@0 {
pmic_dev = <&pmic_dev_0 DA9063_ID_LDO7>;
auto_on_info = <5 1 2800000>;
auto_off_info = <0 1>;
};
};
regu_config_15 {
reg_info = <&soc_dvdd08_ap_reg>;
status = "okay";
regu_id@0 {
pmic_dev = <&pmic_dev_1 DA9121_ID_BUCK1>;
parent_pmic_dev = <&pmic_dev_0 2 0>;
};
};
regu_config_16 {
reg_info = <&soc_dvdd18_emmc_reg>;
status = "okay";
regu_id@0 {
pmic_dev = <&pmic_dev_0 DA9063_ID_GPIO7>;
parent_pmic_dev = <&pmic_dev_0 7 0>;
};
};
};
};
};
chosen {
bootargs = "console=ttyS0,115200";
stdout-path = "/soc/serial@ffe7014000:115200";
};
};

10
arch/riscv/include/asm/bitops.h
View File

@@ -90,16 +90,6 @@ static inline int __test_and_clear_bit(int nr, void *addr)
return retval;
}
static inline int test_and_clear_bit(int nr, volatile void * addr)
{
unsigned long flags = 0;
int out;
out = __test_and_clear_bit(nr, addr);
return out;
}
static inline int __test_and_change_bit(int nr, void *addr)
{
int mask, retval;

1
arch/sandbox/dts/Makefile
View File

@@ -6,7 +6,6 @@ else
dtb-$(CONFIG_SANDBOX) += sandbox.dtb
endif
dtb-$(CONFIG_UT_DM) += test.dtb
dtb-$(CONFIG_CMD_EXTENSION) += overlay0.dtbo overlay1.dtbo
targets += $(dtb-y)

9
arch/sandbox/dts/overlay0.dts
View File

@@ -1,9 +0,0 @@
/dts-v1/;
/plugin/;
&{/buttons} {
btn3 {
gpios = <&gpio_a 5 0>;
label = "button3";
};
};

9
arch/sandbox/dts/overlay1.dts
View File

@@ -1,9 +0,0 @@
/dts-v1/;
/plugin/;
&{/buttons} {
btn4 {
gpios = <&gpio_a 5 0>;
label = "button4";
};
};

23
board/sandbox/sandbox.c
View File

@@ -12,9 +12,6 @@
#include <os.h>
#include <asm/test.h>
#include <asm/u-boot-sandbox.h>
#include <malloc.h>
#include <extension_board.h>
/*
* Pointer to initial global data area
@@ -61,26 +58,6 @@ int board_init(void)
return 0;
}
#ifdef CONFIG_CMD_EXTENSION
int extension_board_scan(struct list_head *extension_list)
{
struct extension *extension;
int i;
for (i = 0; i < 2; i++) {
extension = calloc(1, sizeof(struct extension));
snprintf(extension->overlay, sizeof(extension->overlay), "overlay%d.dtbo", i);
snprintf(extension->name, sizeof(extension->name), "extension board %d", i);
snprintf(extension->owner, sizeof(extension->owner), "sandbox");
snprintf(extension->version, sizeof(extension->version), "1.1");
snprintf(extension->other, sizeof(extension->other), "Fictionnal extension board");
list_add_tail(&extension->list, extension_list);
}
return i;
}
#endif
#ifdef CONFIG_BOARD_LATE_INIT
int board_late_init(void)
{

12
board/thead/light-c910/Kconfig
View File

@@ -130,17 +130,14 @@ config TARGET_LIGHT_FM_C910_B_POWER
bool "light fullmask for light-b-power board "
default n
config TARGET_LIGHT_FM_C910_MILKV_MELES
bool "light fullmask for Milk-V Meles board "
default n
config SYS_TEXT_BASE
default 0xc0000000 if RISCV_MMODE
default 0x00200000 if RISCV_SMODE
config SPL_TEXT_BASE
hex
default 0xffe0000000
default 0xffe0000800 if LIGHT_SEC_BOOT_WITH_VERIFY_VAL_A || LIGHT_SEC_BOOT_WITH_VERIFY_VAL_B || LIGHT_SEC_BOOT_WITH_VERIFY_ANT_REF || LIGHT_SEC_BOOT_WITH_VERIFY_LPI4A
default 0xffe0000000 if !(LIGHT_SEC_BOOT_WITH_VERIFY_VAL_A || LIGHT_SEC_BOOT_WITH_VERIFY_VAL_B || LIGHT_SEC_BOOT_WITH_VERIFY_ANT_REF || LIGHT_SEC_BOOT_WITH_VERIFY_LPI4A)
config SPL_MAX_SIZE
hex
@@ -257,11 +254,6 @@ config DDR_DDP
Enabling this will support ddr Dual Die Package configuration.
e.g. to support 8GB ddr device with 17-bit row address (16:0)
config FIXUP_MEMORY_REGION
bool "self-adapt to query and fixup memory region"
help
Enabling this will support self-adapt to query and fixup memory region
config DDR_H32_MODE
bool "LPDDR4/4X 32bit mode configuration"
help

2
board/thead/light-c910/Makefile
View File

@@ -23,7 +23,6 @@ obj-$(CONFIG_LPDDR) += $(DDR_SRC_PATH)/init_ddr.o
obj-$(CONFIG_LPDDR) += $(DDR_SRC_PATH)/pinmux.o
obj-$(CONFIG_LPDDR) += $(DDR_SRC_PATH)/waitfwdone.o
obj-$(CONFIG_LPDDR) += $(DDR_SRC_PATH)/ddr_common_func.o
obj-$(CONFIG_LPDDR) += $(DDR_SRC_PATH)/ddr_retention.o
obj-$(CONFIG_LPDDR) += $(DDR_SRC_PATH)/common_lib.o
obj-$(CONFIG_LPDDR) += $(DDR_SRC_PATH)/lpddr4_init.o
ifdef CONFIG_DDR_DBI_OFF
@@ -64,7 +63,6 @@ obj-y += boot.o
obj-y += sbmeta/sbmeta.o
ifndef CONFIG_TARGET_LIGHT_FPGA_FM_C910
obj-$(CONFIG_LPDDR) += $(DDR_SRC_PATH)/ddr_common_func.o
obj-$(CONFIG_LPDDR) += $(DDR_SRC_PATH)/ddr_retention.o
obj-$(CONFIG_LPDDR) += $(DDR_SRC_PATH)/common_lib.o
endif

181
board/thead/light-c910/board.c
View File

@@ -8,18 +8,10 @@
#include <asm/io.h>
#include <dwc3-uboot.h>
#include <usb.h>
#include <usb/xhci.h>
#include <cpu_func.h>
#include <asm/gpio.h>
#include <abuf.h>
#include "sec_library.h"
#ifdef CONFIG_LIGHT_AON_CONF
#include "../../../drivers/misc/light_regu.h"
#include "dm/device.h"
#include "dm/uclass.h"
#endif
#ifdef CONFIG_USB_DWC3
static struct dwc3_device dwc3_device_data = {
.maximum_speed = USB_SPEED_SUPER,
@@ -36,13 +28,6 @@ int usb_gadget_handle_interrupts(int index)
int board_usb_init(int index, enum usb_init_type init)
{
dwc3_device_data.base = 0xFFE7040000UL;
if (init == USB_INIT_DEVICE) {
dwc3_device_data.dr_mode = USB_DR_MODE_PERIPHERAL;
} else {
dwc3_device_data.dr_mode = USB_DR_MODE_HOST;
}
return dwc3_uboot_init(&dwc3_device_data);
}
@@ -52,28 +37,6 @@ int board_usb_cleanup(int index, enum usb_init_type init)
return 0;
}
int xhci_hcd_init(int index, struct xhci_hccr **hccr, struct xhci_hcor **hcor)
{
int ret = board_usb_init(index, USB_INIT_HOST);
if (ret != 0) {
puts("Failed to initialize board for USB\n");
return ret;
}
*hccr = (struct xhci_hccr *)dwc3_device_data.base;
*hcor = (struct xhci_hcor *)(dwc3_device_data.base +
HC_LENGTH(xhci_readl(&(*hccr)->cr_capbase)));;
return ret;
}
void xhci_hcd_stop(int index)
{
board_usb_cleanup(index, USB_INIT_HOST);
}
int g_dnl_board_usb_cable_connected(void)
{
return 1;
@@ -81,14 +44,9 @@ int g_dnl_board_usb_cable_connected(void)
#endif
#ifdef CONFIG_CMD_BOOT_SLAVE
#ifdef CONFIG_LIGHT_AON_CONF
#define E902_AON_CONFIG_SIZE 0xC00
#else
#define E902_AON_CONFIG_SIZE 0x000
#endif
#define E902_SYSREG_START 0xfffff48044
#define E902_SYSREG_RESET 0xfffff44024
#define E902_START_ADDRESS (0xFFEF8000 + E902_AON_CONFIG_SIZE)
#define E902_START_ADDRESS 0xFFEF8000
#define C910_E902_START_ADDRESS 0xFFFFEF8000
#define E902_IOPMP_BASE 0xFFFFC21000
@@ -128,153 +86,36 @@ void set_c906_cpu_entry(phys_addr_t entry_h, phys_addr_t entry_l)
void boot_audio(void)
{
writel(0x37, (volatile void *)C906_RESET_REG);
writel(0x37, (volatile void *)C906_RESET_REG);
set_c906_cpu_entry(C906_START_ADDRESS_H, C906_START_ADDRESS_L);
flush_cache((uintptr_t)C910_C906_START_ADDRESS, 0x20000);
set_c906_cpu_entry(C906_START_ADDRESS_H, C906_START_ADDRESS_L);
flush_cache((uintptr_t)C910_C906_START_ADDRESS, 0x20000);
writel(0x7ffff1f, (volatile void *)C906_CPR_IPCG_ADDRESS);
writel((1<<23) | (1<<24), (volatile void *)C906_IOCTL_GPIO_SEL_ADDRESS);
writel(0, (volatile void *)C906_IOCTL_AF_SELH_ADDRESS);
writel(0x7ffff1f, (volatile void *)C906_CPR_IPCG_ADDRESS);
writel((1<<23) | (1<<24), (volatile void *)C906_IOCTL_GPIO_SEL_ADDRESS);
writel(0, (volatile void *)C906_IOCTL_AF_SELH_ADDRESS);
writel(0x3f, (volatile void *)C906_RESET_REG);
writel(0x3f, (volatile void *)C906_RESET_REG);
}
#ifdef CONFIG_LIGHT_AON_CONF
int get_and_set_aon_config_data(void)
void boot_aon(void)
{
int ret =0;
struct udevice *dev;
struct mic_regu_platdata *config_data =NULL;
ret = uclass_first_device_err(UCLASS_MISC, &dev);
if(ret){
printf("get light aon config faild %d\n", ret);
return ret;
}
config_data = (struct mic_regu_platdata *)(dev->platdata);
volatile aon_config_t* read_config = (aon_config_t* )C910_E902_START_ADDRESS;
if(strncmp((const char*)read_config->magic , AON_CONFIG_MAGIC, strlen(AON_CONFIG_MAGIC))) {
printf("No aon config magic found in aon bin, please check the aon bin\n");
return -1;
}
if(strncmp((const char*)read_config->version, AON_CONFIG_VERSION, strlen(AON_CONFIG_VERSION))) {
printf("Err aon config version, aon bin is:%s, u-boot is:%s\n", read_config->version, AON_CONFIG_VERSION);
return -1;
}
if(PMIC_MAX_HW_ID_NUM > read_config->max_hw_id_num) {
printf("Invald max hw id num, aon bin support %d , u-boot is %d\n",read_config->max_hw_id_num, PMIC_MAX_HW_ID_NUM);
return -1;
}
/*set pmic dev info */
int pmic_dev_num = config_data->pmic_list.pmic_num;
int pmic_dev_list_offset = sizeof(aon_config_t);
uint64_t pmic_dev_start_addr = C910_E902_START_ADDRESS + pmic_dev_list_offset;
int regu_num = config_data->regu_id_list.regu_id_num;
int regu_id_list_offset = pmic_dev_list_offset + pmic_dev_num * sizeof(pmic_dev_info_t);
uint64_t regu_start_addr = C910_E902_START_ADDRESS + regu_id_list_offset;
int aon_bin_size = regu_id_list_offset + regu_num* sizeof(csi_regu_id_t);
if( aon_bin_size > read_config->aon_config_partition_size) {
printf("Invalid aon partition size, aon bin support:%lld, u-boot is %d\n", read_config->aon_config_partition_size, aon_bin_size);
return -1;
}
printf("pmic_dev_num:%d offset:%d addr:%lld\n",pmic_dev_num, pmic_dev_list_offset, pmic_dev_start_addr);
memcpy((void*)pmic_dev_start_addr, config_data->pmic_list.pmic_list, pmic_dev_num * sizeof(pmic_dev_info_t));
printf("regu_num:%d offset:%d addr:%lld\n",regu_num,regu_id_list_offset, regu_start_addr);
memcpy((void*)regu_start_addr, config_data->regu_id_list.regu_id_list, regu_num * sizeof(csi_regu_id_t));
read_config->wakeup_flag = config_data->wakeup_flag;
read_config->aon_pmic.iic_config.iic_id = config_data->iic_config.iic_id;
read_config->aon_pmic.iic_config.addr_mode = config_data->iic_config.addr_mode;
read_config->aon_pmic.iic_config.speed = config_data->iic_config.speed;
read_config->aon_pmic.pmic_dev_num = pmic_dev_num;
read_config->aon_pmic.pmic_dev_list_offset = pmic_dev_list_offset;
/*set regu list info*/
read_config->aon_pmic.regu_num = regu_num;
read_config->aon_pmic.regu_id_list_offset = regu_id_list_offset;
memcpy((void*)read_config->uboot_set_magic, UBOOT_CONFIG_MAGIC, strlen(UBOOT_CONFIG_MAGIC));
flush_cache((uintptr_t)C910_E902_START_ADDRESS, aon_bin_size);
printf("-->pmic_dev_num:%d offset:%d\n",read_config->aon_pmic.pmic_dev_num, read_config->aon_pmic.pmic_dev_list_offset);
printf("-->regu_num:%d offset:%d\n",read_config->aon_pmic.regu_num,read_config->aon_pmic.regu_id_list_offset);
return 0;
}
#endif
int do_boot_aon(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
{
#ifdef CONFIG_LIGHT_AON_CONF
int ret = 0;
ret = get_and_set_aon_config_data();
if(ret) {
printf("aon config and set faild %d", ret);
hang();
return ret;
}
#endif
writel(0xffffffff, (void *)(E902_IOPMP_BASE + 0xc0));
disable_slave_cpu();
set_slave_cpu_entry(E902_START_ADDRESS);
flush_cache((uintptr_t)C910_E902_START_ADDRESS, 0x10000);
enable_slave_cpu();
return 0;
}
U_BOOT_CMD(
bootaon, CONFIG_SYS_MAXARGS, 0, do_boot_aon,
"Boot aon from memory ",
" "
);
int do_bootslave(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
{
boot_aon();
mdelay(100);
boot_audio();
return 0;
}
#endif
static void light_c910_set_gpio_output_high(void)
{
ofnode node;
struct gpio_desc select_gpio;
printf("%s: trying to set gpio output high\n", __func__);
node = ofnode_path("/config");
if (!ofnode_valid(node)) {
printf("%s: no /config node?\n", __func__);
return;
}
if (gpio_request_by_name_nodev(node, "select-gpio", 0,
&select_gpio, GPIOD_IS_OUT)) {
printf("%s: could not find a /config/select-gpio\n", __func__);
return;
}
dm_gpio_set_value(&select_gpio, 1);
}
int misc_init_r(void)
{
light_c910_set_gpio_output_high();
return 0;
}
#ifdef CONFIG_BOARD_RNG_SEED
const char pre_gen_seed[128] = {211, 134, 226, 116, 1, 13, 224, 196, 88, 213, 188, 219, 128, 41, 231, 228, 129, 123, 173, 234, 219, 79, 152, 154, 169, 27, 183, 166, 52, 21, 118, 7, 155, 89, 124, 156, 102, 92, 96, 190, 49, 28, 154, 177, 69, 129, 149, 199, 253, 66, 177, 216, 146, 73, 114, 59, 100, 41, 225, 152, 62, 88, 160, 217, 177, 28, 117, 23, 120, 213, 213, 169, 242, 111, 90, 55, 241, 239, 254, 238, 50, 175, 198, 196, 248, 56, 255, 92, 97, 224, 245, 160, 56, 149, 121, 233, 177, 239, 0, 41, 196, 214, 210, 182, 69, 44, 238, 54, 27, 236, 36, 77, 156, 234, 17, 148, 34, 16, 241, 132, 241, 230, 36, 41, 123, 157, 19, 44};
/* Use hardware rng to seed Linux random. */

7
board/thead/light-c910/clock_config.c
View File

@@ -1146,7 +1146,7 @@ void ap_mipi_dsi1_clk_endisable(bool en)
writel(cfg1, (void __iomem *)AP_DPU1_PLL_CFG1);
}
#if defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_DISCRETE) || defined (CONFIG_TARGET_LIGHT_FM_C910_BEAGLE) || defined (CONFIG_TARGET_LIGHT_FM_C910_B_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_B_POWER) || defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_B) || defined (CONFIG_TARGET_LIGHT_FM_C910_LPI4A) || defined (CONFIG_TARGET_LIGHT_FM_C910_MILKV_MELES)
#if defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_DISCRETE) || defined (CONFIG_TARGET_LIGHT_FM_C910_BEAGLE) || defined (CONFIG_TARGET_LIGHT_FM_C910_B_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_B_POWER) || defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_B) || defined (CONFIG_TARGET_LIGHT_FM_C910_LPI4A)
static void ap_multimedia_div_num_set(enum multimedia_div_type type, unsigned int div_num)
{
unsigned long div_reg;
@@ -1220,7 +1220,7 @@ int clk_config(void)
return -EINVAL;
printf("C910 CPU FREQ: %ldMHz\n", rate / 1000000);
#ifdef PERI_BUS_PLL_FREQ_PRINT
rate = clk_light_get_rate("ahb2_cpusys_hclk", CLK_DEV_MUX);
if (!rate)
return -EINVAL;
@@ -1262,7 +1262,6 @@ int clk_config(void)
return -EINVAL;
printf("DPU1 PLL POSTDIV FREQ: %ldMHZ\n", rate / 1000000);
#endif
#ifdef AUDIO_PLL_FREQ_PRINT
rate = clk_light_get_rate("audio_pll_foutpostdiv", CLK_DEV_PLL);
@@ -1305,7 +1304,7 @@ int clk_config(void)
/* The boards other than the LightA board perform the bus down-speed operation */
#if defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_DISCRETE) || defined (CONFIG_TARGET_LIGHT_FM_C910_BEAGLE) || defined (CONFIG_TARGET_LIGHT_FM_C910_B_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_B_POWER) || defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_B) || defined (CONFIG_TARGET_LIGHT_FM_C910_LPI4A) || defined (CONFIG_TARGET_LIGHT_FM_C910_MILKV_MELES)
#if defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_DISCRETE) || defined (CONFIG_TARGET_LIGHT_FM_C910_BEAGLE) || defined (CONFIG_TARGET_LIGHT_FM_C910_B_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_B_POWER) || defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_B) || defined (CONFIG_TARGET_LIGHT_FM_C910_LPI4A)
ap_multimedia_div_num_set(VI_MIPI_CSI0_DIV, 12); /* Input frquency: 2376MHZ */
ap_multimedia_div_num_set(VI_ISP0_CORE_DIV, 12); /* Input frquency: 2376MHZ */
ap_multimedia_div_num_set(VI_ISP1_CORE_DIV, 12); /* Input frquency: 2376MHZ */

14
board/thead/light-c910/ddr.c
View File

@@ -12,17 +12,3 @@ void init_ddr(void)
{
writel(0x1ff << 4, (void *)0xffff005000);
}
int fixup_ddr_addrmap(unsigned long size)
{
return 0;
}
int query_ddr_boundary(unsigned long size)
{
return 0;
}
unsigned long get_ddr_density(void)
{
return 0x100000000;
}

854
board/thead/light-c910/light.c
View File

@@ -11,10 +11,6 @@
#include <thead/clock_config.h>
#include <linux/bitops.h>
#include <asm/arch-thead/light-iopmp.h>
#include <memalign.h>
#include <fdt_support.h>
#include <fs.h>
#include <asm/global_data.h>
#define SOC_PIN_AP_RIGHT_TOP (0x0)
#define SOC_PIN_AP_LEFT_TOP (0x1)
@@ -34,7 +30,6 @@
#define GMAC0_APB3S_BADDR 0xffec003000
#define GMAC1_APB3S_BADDR 0xffec004000
static uint64_t apb3s_baddr;
extern int check_image_board_id(uint8_t *image_data);
@@ -635,7 +630,6 @@ static void light_iopin_init(void)
{
return;
}
#elif defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_A)
static void light_iopin_init(void)
{
@@ -815,7 +809,6 @@ static void light_iopin_init(void)
light_pin_cfg(GMAC0_RXD3, PIN_SPEED_NORMAL, PIN_PN, 0xF);
}
#elif defined ( CONFIG_TARGET_LIGHT_FM_C910_VAL_B) || defined ( CONFIG_TARGET_LIGHT_FM_C910_B_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_B_POWER)
static void light_iopin_init(void)
{
@@ -1221,8 +1214,7 @@ static void light_iopin_init(void)
light_pin_cfg(GMAC0_RXD2, PIN_SPEED_NORMAL, PIN_PN, 0xF);
light_pin_cfg(GMAC0_RXD3, PIN_SPEED_NORMAL, PIN_PN, 0xF);
}
#elif defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_REF)
#elif defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_BEAGLE)
static void light_iopin_init(void)
{
/* aon-padmux config */
@@ -1375,7 +1367,7 @@ static void light_iopin_init(void)
light_pin_cfg(GPIO2_22,PIN_SPEED_NORMAL,PIN_PN,2); ///<WIFI_BT_GPIO2
light_pin_cfg(GPIO2_23,PIN_SPEED_NORMAL,PIN_PN,2); ///<WIFI_BT_GPIO3
light_pin_cfg(GPIO2_24,PIN_SPEED_NORMAL,PIN_PN,2); ///<WIFI_BT_RST_N
light_pin_cfg(GPIO2_25,PIN_SPEED_NORMAL,PIN_PN,2); ///KEY1
light_pin_cfg(GPIO2_25,PIN_SPEED_NORMAL,PIN_PU,2); ///KEY1
light_pin_mux(SDIO0_WPRTN,3);
@@ -1392,7 +1384,7 @@ static void light_iopin_init(void)
light_pin_mux(GPIO3_2,1);
light_pin_mux(GPIO3_3,0);
light_pin_cfg(GPIO2_30, PIN_SPEED_NORMAL, PIN_PN, 0x2); ///NC
light_pin_cfg(GPIO2_31, PIN_SPEED_NORMAL, PIN_PU, 0x2); ///NC
light_pin_cfg(GPIO2_31, PIN_SPEED_NORMAL, PIN_PN, 0x2); ///NC
light_pin_cfg(GPIO3_0, PIN_SPEED_NORMAL, PIN_PN, 0x2); ///NC
light_pin_cfg(GPIO3_1, PIN_SPEED_NORMAL, PIN_PN, 0x2);
light_pin_cfg(GPIO3_2, PIN_SPEED_NORMAL, PIN_PN, 0xF);
@@ -1430,8 +1422,6 @@ static void light_iopin_init(void)
light_pin_cfg(CPU_JTG_TMS, PIN_SPEED_NORMAL, PIN_PN, 2);
light_pin_mux(CPU_JTG_TDI, 3);
light_pin_cfg(CPU_JTG_TDI, PIN_SPEED_NORMAL, PIN_PN, 2);
light_pin_mux(CPU_JTG_TRST, 3);
light_pin_cfg(CPU_JTG_TRST, PIN_SPEED_NORMAL, PIN_PN, 2);
light_pin_mux(AOGPIO_7, 1);
light_pin_mux(AOGPIO_8, 1);
@@ -1444,7 +1434,7 @@ static void light_iopin_init(void)
// light_pin_mux(AOGPIO_15,0);
light_pin_cfg(AOGPIO_7, PIN_SPEED_NORMAL, PIN_PN, 2); ///NC
light_pin_cfg(AOGPIO_8, PIN_SPEED_NORMAL, PIN_PN, 2); ///NC
light_pin_cfg(AOGPIO_9,PIN_SPEED_NORMAL,PIN_PN,2);
// light_pin_cfg(AOGPIO_9,PIN_SPEED_NORMAL,PIN_PN,2);
light_pin_cfg(AOGPIO_10, PIN_SPEED_NORMAL, PIN_PN, 2);
light_pin_cfg(AOGPIO_11, PIN_SPEED_NORMAL, PIN_PN, 2);
light_pin_cfg(AOGPIO_12, PIN_SPEED_NORMAL, PIN_PN, 2);
@@ -1478,7 +1468,6 @@ static void light_iopin_init(void)
light_pin_cfg(AUDIO_PA29, PIN_SPEED_NORMAL, PIN_PN, 2);
light_pin_mux(AUDIO_PA30, 0);
light_pin_cfg(AUDIO_PA30, PIN_SPEED_NORMAL, PIN_PN, 2);
light_pin_mux(AUDIO_PA30, 3);
// light_pin_mux(AUDIO_PA9,3); ///AUDIO-PA-RESET
// light_pin_cfg(AUDIO_PA9,PIN_SPEED_NORMAL,PIN_PN,2);
@@ -1618,7 +1607,7 @@ static void light_iopin_init(void)
light_pin_cfg(I2C3_SCL, PIN_SPEED_NORMAL, PIN_PN, 4);
light_pin_cfg(I2C3_SDA, PIN_SPEED_NORMAL, PIN_PN, 4);
light_pin_mux(SPI_CSN,3); /// W_DISABLE_CATE1
// light_pin_mux(SPI_CSN,3); /// W_DISABLE_CATE1
// light_pin_mux(SPI_MOSI,3); /// NC
// light_pin_mux(SPI_MISO,3); /// RERST1_N_CAT1
// light_pin_mux(SPI_SCLK,3);
@@ -1694,579 +1683,17 @@ static void light_iopin_init(void)
light_pin_cfg(GMAC0_COL, PIN_SPEED_NORMAL, PIN_PU, 2);
light_pin_cfg(GMAC0_CRS, PIN_SPEED_NORMAL, PIN_PU, 2);
}
#elif defined (CONFIG_TARGET_LIGHT_FM_C910_BEAGLE)
static void light_iopin_init(void)
{
/* P8_03 (Ball:J34) GPIO1_21_MUX*/
light_pin_mux(GPIO1_21,3);
light_pin_cfg(GPIO1_21, PIN_SPEED_NORMAL, PIN_PN, 2);
/* P8_04 (Ball:J35) GPIO1_22_MUX*/
light_pin_mux(GPIO1_22,3);
light_pin_cfg(GPIO1_22, PIN_SPEED_NORMAL, PIN_PN, 2);
/* P8_05 (Ball:K32) GPIO1_23_MUX*/
light_pin_mux(GPIO1_23,3);
light_pin_cfg(GPIO1_23, PIN_SPEED_NORMAL, PIN_PN, 2);
/* P8_06 (Ball:K33) GPIO1_24_MUX*/
light_pin_mux(GPIO1_24,3);
light_pin_cfg(GPIO1_24, PIN_SPEED_NORMAL, PIN_PN, 2);
/* P8_07 (Ball:K34) GPIO1_25_MUX*/
light_pin_mux(GPIO1_25,3);
light_pin_cfg(GPIO1_25, PIN_SPEED_NORMAL, PIN_PN, 2);
/* P8_08 (Ball:K35) GPIO1_26_MUX*/
light_pin_mux(GPIO1_26,0);
light_pin_cfg(GPIO1_26, PIN_SPEED_NORMAL, PIN_PN, 2);
/* P8_09 (Ball:K36) GPIO1_27_MUX*/
light_pin_mux(GPIO1_27,0);
light_pin_cfg(GPIO1_27, PIN_SPEED_NORMAL, PIN_PN, 2);
/* P8_10 (Ball:K37) GPIO1_28_MUX*/
light_pin_mux(GPIO1_28,0);
light_pin_cfg(GPIO1_28, PIN_SPEED_NORMAL, PIN_PN, 2);
/* P8_11 (Ball:L32) GPIO1_29_MUX*/
light_pin_mux(GPIO1_29,0);
light_pin_cfg(GPIO1_29, PIN_SPEED_NORMAL, PIN_PN, 2);
/* P8_12 (Ball:L33) GPIO1_30_MUX*/
light_pin_mux(GPIO1_30,0);
light_pin_cfg(GPIO1_30, PIN_SPEED_NORMAL, PIN_PN, 2);
/* P8_13 (Ball:C6) GPIO3_2_MUX*/
light_pin_mux(GPIO3_2,0);
light_pin_cfg(GPIO3_2, PIN_SPEED_NORMAL, PIN_PN, 2);
/* P8_14 (Ball:E29) CLK_OUT_3_MUX*/
light_pin_mux(CLK_OUT_3,3);
light_pin_cfg(CLK_OUT_3, PIN_SPEED_NORMAL, PIN_PN, 2);
/* P8_15 (Ball:A6) GPIO3_0_MUX*/
light_pin_mux(GPIO3_0,0);
light_pin_cfg(GPIO3_0, PIN_SPEED_NORMAL, PIN_PN, 2);
/* P8_16 (Ball:F34) GPIO0_20_MUX*/
light_pin_mux(GPIO0_20,0);
light_pin_cfg(GPIO0_20, PIN_SPEED_NORMAL, PIN_PN, 2);
/* P8_17 (Ball:B6) GPIO3_1_MUX*/
light_pin_mux(GPIO3_1,0);
light_pin_cfg(GPIO3_1, PIN_SPEED_NORMAL, PIN_PN, 2);
/* P8_18 (Ball:B34) GPIO1_5_MUX*/
light_pin_mux(GPIO1_5,0);
light_pin_cfg(GPIO1_5, PIN_SPEED_NORMAL, PIN_PN, 2);
/* P8_19 (Ball:D6) GPIO3_3_MUX*/
light_pin_mux(GPIO3_3,0);
light_pin_cfg(GPIO3_3, PIN_SPEED_NORMAL, PIN_PN, 2);
/* P8_20 (Ball:C34) GPIO1_6_MUX*/
light_pin_mux(GPIO1_6,0);
light_pin_cfg(GPIO1_6, PIN_SPEED_NORMAL, PIN_PN, 2);
/* P8_21 (Ball:D34) GPIO1_7_MUX*/
light_pin_mux(GPIO1_7,0);
light_pin_cfg(GPIO1_7, PIN_SPEED_NORMAL, PIN_PN, 2);
/* P8_22 (Ball:B35) GPIO1_8_MUX*/
light_pin_mux(GPIO1_8,0);
light_pin_cfg(GPIO1_8, PIN_SPEED_NORMAL, PIN_PN, 2);
/* P8_23 (Ball:A36) GPIO1_9_MUX*/
light_pin_mux(GPIO1_9,0);
light_pin_cfg(GPIO1_9, PIN_SPEED_NORMAL, PIN_PN, 2);
/* P8_24 (Ball:B36) GPIO1_10_MUX*/
light_pin_mux(GPIO1_10,0);
light_pin_cfg(GPIO1_10, PIN_SPEED_NORMAL, PIN_PN, 2);
/* P8_25 (Ball:B37) GPIO1_11_MUX*/
light_pin_mux(GPIO1_11,0);
light_pin_cfg(GPIO1_11, PIN_SPEED_NORMAL, PIN_PN, 2);
/* P8_26 (Ball:C36) GPIO1_12_MUX*/
light_pin_mux(GPIO1_12,0);
light_pin_cfg(GPIO1_12, PIN_SPEED_NORMAL, PIN_PN, 2);
/* P8_27 (Ball:D37) GPIO1_15_MUX*/
light_pin_mux(GPIO1_15,0);
light_pin_cfg(GPIO1_15, PIN_SPEED_NORMAL, PIN_PN, 2);
/* P8_28 (Ball:E34) GPIO1_16_MUX*/
light_pin_mux(GPIO1_16,0);
light_pin_cfg(GPIO1_16, PIN_SPEED_NORMAL, PIN_PN, 2);
/* P8_29 (Ball:D36) GPIO1_14_MUX*/
light_pin_mux(GPIO1_14,0);
light_pin_cfg(GPIO1_14, PIN_SPEED_NORMAL, PIN_PN, 2);
/* P8_30 (Ball:D35) GPIO1_13_MUX*/
light_pin_mux(GPIO1_13,0);
light_pin_cfg(GPIO1_13, PIN_SPEED_NORMAL, PIN_PN, 2);
/* P8_31 (Ball:D33) GPIO1_3_MUX*/
light_pin_mux(GPIO1_3,0);
light_pin_cfg(GPIO1_3, PIN_SPEED_NORMAL, PIN_PN, 2);
/* P8_32 (Ball:A34) GPIO1_4_MUX*/
light_pin_mux(GPIO1_4,0);
light_pin_cfg(GPIO1_4, PIN_SPEED_NORMAL, PIN_PN, 2);
/* P8_33 (Ball:C33) GPIO1_2_MUX*/
light_pin_mux(GPIO1_2,0);
light_pin_cfg(GPIO1_2, PIN_SPEED_NORMAL, PIN_PN, 2);
/* P8_34 (Ball:E32) GPIO1_0_MUX*/
light_pin_mux(GPIO1_0,0);
light_pin_cfg(GPIO1_0, PIN_SPEED_NORMAL, PIN_PN, 2);
/* P8_35 (Ball:A32) GPIO1_1_MUX*/
light_pin_mux(GPIO1_1,0);
light_pin_cfg(GPIO1_1, PIN_SPEED_NORMAL, PIN_PN, 2);
/* P8_36 (Ball:D32) GPIO0_31_MUX*/
light_pin_mux(GPIO0_31,0);
light_pin_cfg(GPIO0_31, PIN_SPEED_NORMAL, PIN_PN, 2);
/* P8_37 (Ball:B32) GPIO0_29_MUX*/
light_pin_mux(GPIO0_29,0);
light_pin_cfg(GPIO0_29, PIN_SPEED_NORMAL, PIN_PN, 2);
/* P8_38 (Ball:C32) GPIO0_30_MUX*/
light_pin_mux(GPIO0_30,0);
light_pin_cfg(GPIO0_30, PIN_SPEED_NORMAL, PIN_PN, 2);
/* P8_39 (Ball:D31) GPIO0_27_MUX*/
light_pin_mux(GPIO0_27,0);
light_pin_cfg(GPIO0_27, PIN_SPEED_NORMAL, PIN_PN, 2);
/* P8_40 (Ball:E31) GPIO0_28_MUX*/
light_pin_mux(GPIO0_28,0);
light_pin_cfg(GPIO0_28, PIN_SPEED_NORMAL, PIN_PN, 2);
/* P8_41 (Ball:F30) GPIO0_25_MUX*/
light_pin_mux(GPIO0_25,0);
light_pin_cfg(GPIO0_25, PIN_SPEED_NORMAL, PIN_PN, 2);
/* P8_42 (Ball:C31) GPIO0_26_MUX*/
light_pin_mux(GPIO0_26,0);
light_pin_cfg(GPIO0_26, PIN_SPEED_NORMAL, PIN_PN, 2);
/* P8_43 (Ball:C30) GPIO0_23_MUX*/
light_pin_mux(GPIO0_23,0);
light_pin_cfg(GPIO0_23, PIN_SPEED_NORMAL, PIN_PN, 2);
/* P8_44 (Ball:D30) GPIO0_24_MUX*/
light_pin_mux(GPIO0_24,0);
light_pin_cfg(GPIO0_24, PIN_SPEED_NORMAL, PIN_PN, 2);
/* P8_45 (Ball:F36) GPIO0_21_MUX*/
light_pin_mux(GPIO0_21,0);
light_pin_cfg(GPIO0_21, PIN_SPEED_NORMAL, PIN_PN, 2);
/* P8_46 (Ball:D29) GPIO0_22_MUX*/
light_pin_mux(GPIO0_22,0);
light_pin_cfg(GPIO0_22, PIN_SPEED_NORMAL, PIN_PN, 2);
/* P9_01 - GND */
/* P9_02 - GND */
/* P9_03 - VOUT_3V3 */
/* P9_04 - VOUT_3V3 */
/* P9_05 - VIN */
/* P9_06 - VIN */
/* P9_07 - VOUT_SYS */
/* P9_08 - VOUT_SYS */
/* P9_09 - ONKEY# */
/* P9_10 - RESET# */
/* P9_11 (Ball:M32) UART1_TXD_MUX*/
light_pin_mux(UART1_TXD,3);
light_pin_cfg(UART1_TXD, PIN_SPEED_NORMAL, PIN_PN, 2);
/* P9_12 (Ball:H1) QSPI0_CSN0_MUX*/
light_pin_mux(QSPI0_CSN0,3);
light_pin_cfg(QSPI0_CSN0, PIN_SPEED_NORMAL, PIN_PN, 2);
/* P9_13 (Ball:M33) UART1_RXD_MUX*/
light_pin_mux(UART1_RXD,3);
light_pin_cfg(UART1_RXD, PIN_SPEED_NORMAL, PIN_PN, 2);
/* P9_14 (Ball:K3) QSPI0_D1_MISO_MUX*/
light_pin_mux(QSPI0_D1_MISO,3);
light_pin_cfg(QSPI0_D1_MISO, PIN_SPEED_NORMAL, PIN_PN, 2);
/* P9_15 (Ball:K2) QSPI0_D2_WP_MUX*/
light_pin_mux(QSPI0_D2_WP,3);
light_pin_cfg(QSPI0_D2_WP, PIN_SPEED_NORMAL, PIN_PN, 2);
/* P9_16 (Ball:J3) QSPI0_D0_MOSI_MUX*/
light_pin_mux(QSPI0_D0_MOSI,3);
light_pin_cfg(QSPI0_D0_MOSI, PIN_SPEED_NORMAL, PIN_PN, 2);
/* P9_17 (Ball:H32) QSPI1_CSN0_MUX*/
light_pin_mux(QSPI1_CSN0,3);
light_pin_cfg(QSPI1_CSN0, PIN_SPEED_NORMAL, PIN_PN, 2);
/* P9_18 (Ball:G35) QSPI1_D0_MOSI_MUX*/
light_pin_mux(QSPI1_D0_MOSI,3);
light_pin_cfg(QSPI1_D0_MOSI, PIN_SPEED_NORMAL, PIN_PN, 2);
/* P9_19 (Ball:G4) I2C2_SCL_MUX*/
light_pin_mux(I2C2_SCL,3);
light_pin_cfg(I2C2_SCL, PIN_SPEED_NORMAL, PIN_PN, 2);
/* P9_20 (Ball:G3) I2C2_SDA_MUX*/
light_pin_mux(I2C2_SDA,3);
light_pin_cfg(I2C2_SDA, PIN_SPEED_NORMAL, PIN_PN, 2);
/* P9_21 (Ball:G34) QSPI1_D1_MISO_MUX*/
light_pin_mux(QSPI1_D1_MISO,3);
light_pin_cfg(QSPI1_D1_MISO, PIN_SPEED_NORMAL, PIN_PN, 2);
/* P9_22 (Ball:H34) QSPI1_SCLK_MUX*/
light_pin_mux(QSPI1_SCLK,3);
light_pin_cfg(QSPI1_SCLK, PIN_SPEED_NORMAL, PIN_PN, 2);
/* P9_23 (Ball:K1) QSPI0_D3_HOLD_MUX*/
light_pin_mux(QSPI0_D3_HOLD,3);
light_pin_cfg(QSPI0_D3_HOLD, PIN_SPEED_NORMAL, PIN_PN, 2);
/* P9_24 (Ball:G33) QSPI1_D2_WP_MUX*/
light_pin_mux(QSPI1_D2_WP,3);
light_pin_cfg(QSPI1_D2_WP, PIN_SPEED_NORMAL, PIN_PN, 2);
/* P9_25 (Ball:F5) GPIO2_18_MUX*/
light_pin_mux(GPIO2_18,0);
light_pin_cfg(GPIO2_18, PIN_SPEED_NORMAL, PIN_PN, 2);
/* P9_26 (Ball:F37) QSPI1_D3_HOLD_MUX*/
light_pin_mux(QSPI1_D3_HOLD,3);
light_pin_cfg(QSPI1_D3_HOLD, PIN_SPEED_NORMAL, PIN_PN, 2);
/* P9_27 (Ball:E4) GPIO2_19_MUX*/
light_pin_mux(GPIO2_19,0);
light_pin_cfg(GPIO2_19, PIN_SPEED_NORMAL, PIN_PN, 2);
/* P9_28 (Ball:E3) SPI_CSN_MUX*/
light_pin_mux(SPI_CSN,3);
light_pin_cfg(SPI_CSN, PIN_SPEED_NORMAL, PIN_PN, 2);
/* P9_29 (Ball:F1) SPI_MISO_MUX*/
light_pin_mux(SPI_MISO,3);
light_pin_cfg(SPI_MISO, PIN_SPEED_NORMAL, PIN_PN, 2);
/* P9_30 (Ball:F2) SPI_MOSI_MUX*/
light_pin_mux(SPI_MOSI,3);
light_pin_cfg(SPI_MOSI, PIN_SPEED_NORMAL, PIN_PN, 2);
/* P9_31 (Ball:D3) SPI_SCLK_MUX*/
light_pin_mux(SPI_SCLK,3);
light_pin_cfg(SPI_SCLK, PIN_SPEED_NORMAL, PIN_PN, 2);
/* P9_32 - GND */
/* P9_33 - ADC_VIN_CH4 */
/* P9_34 - GND */
/* P9_35 - ADC_VIN_CH6 */
/* P9_36 - ADC_VIN_CH5 */
/* P9_37 - ADC_VIN_CH2 */
/* P9_38 - ADC_VIN_CH3 */
/* P9_39 - ADC_VIN_CH0 */
/* P9_39 - ADC_VIN_CH1 */
/* P9_41 (Ball:D2) GPIO2_13_MUX*/
light_pin_mux(GPIO2_13,0);
light_pin_cfg(GPIO2_13, PIN_SPEED_NORMAL, PIN_PN, 2);
/* P9_42 (Ball:H3) QSPI0_SCLK_MUX*/
light_pin_mux(QSPI0_SCLK,3);
light_pin_cfg(QSPI0_SCLK, PIN_SPEED_NORMAL, PIN_PN, 2);
/* P9_43 - GND */
/* P9_44 - GND */
/* P9_45 - GND */
/* P9_46 - GND */
/* RTL8211F-VD-CG */
light_pin_mux(GMAC0_COL,3);
light_pin_mux(GMAC0_CRS,3);
light_pin_cfg(GMAC0_COL,PIN_SPEED_NORMAL,PIN_PU,2);
light_pin_cfg(GMAC0_CRS,PIN_SPEED_NORMAL,PIN_PU,2);
light_pin_cfg(GMAC0_TX_CLK, PIN_SPEED_NORMAL, PIN_PN, 0xF);
light_pin_cfg(GMAC0_RX_CLK, PIN_SPEED_NORMAL, PIN_PN, 0xF);
light_pin_cfg(GMAC0_TXEN, PIN_SPEED_NORMAL, PIN_PN, 0xF);
light_pin_cfg(GMAC0_TXD0, PIN_SPEED_NORMAL, PIN_PN, 0xF);
light_pin_cfg(GMAC0_TXD1, PIN_SPEED_NORMAL, PIN_PN, 0xF);
light_pin_cfg(GMAC0_TXD2, PIN_SPEED_NORMAL, PIN_PN, 0xF);
light_pin_cfg(GMAC0_TXD3, PIN_SPEED_NORMAL, PIN_PN, 0xF);
light_pin_cfg(GMAC0_RXDV, PIN_SPEED_NORMAL, PIN_PN, 0xF);
light_pin_cfg(GMAC0_RXD0, PIN_SPEED_NORMAL, PIN_PN, 0xF);
light_pin_cfg(GMAC0_RXD1, PIN_SPEED_NORMAL, PIN_PN, 0xF);
light_pin_cfg(GMAC0_RXD2, PIN_SPEED_NORMAL, PIN_PN, 0xF);
light_pin_cfg(GMAC0_RXD3, PIN_SPEED_NORMAL, PIN_PN, 0xF);
/* PMIC */
light_pin_cfg(I2C_AON_SCL,PIN_SPEED_NORMAL,PIN_PN,8);
light_pin_cfg(I2C_AON_SDA,PIN_SPEED_NORMAL,PIN_PN,8);
light_pin_cfg(AOGPIO_14,PIN_SPEED_NORMAL,PIN_PN,2);
light_pin_cfg(AOGPIO_15,PIN_SPEED_NORMAL,PIN_PN,2);
light_pin_mux(AOGPIO_14,0);
light_pin_mux(AOGPIO_15,0);
/* Debug port */
light_pin_mux(AOGPIO_12,0xF); // TXD
light_pin_mux(AOGPIO_13,0xF); // RXD
/* LEDs */
light_pin_mux(AUDIO_PA8,3);
light_pin_cfg(AUDIO_PA8,PIN_SPEED_NORMAL,PIN_PN,2);
light_pin_mux(AUDIO_PA9,3);
light_pin_cfg(AUDIO_PA9,PIN_SPEED_NORMAL,PIN_PN,2);
light_pin_mux(AUDIO_PA10,3);
light_pin_cfg(AUDIO_PA10,PIN_SPEED_NORMAL,PIN_PU,2);
light_pin_mux(AUDIO_PA11,3);
light_pin_cfg(AUDIO_PA11,PIN_SPEED_NORMAL,PIN_PU,2);
light_pin_mux(AUDIO_PA12,3);
light_pin_cfg(AUDIO_PA12,PIN_SPEED_NORMAL,PIN_PU,2);
/* Boot select*/
/* SD boot button*/
light_pin_mux(CLK_OUT_0,3);
light_pin_cfg(CLK_OUT_0,PIN_SPEED_NORMAL,PIN_PD,2);
/* NC */
light_pin_mux(CLK_OUT_1,3);
light_pin_cfg(CLK_OUT_1,PIN_SPEED_NORMAL,PIN_PD,2);
/* USB boot button*/
light_pin_mux(CLK_OUT_2,3);
light_pin_cfg(CLK_OUT_2,PIN_SPEED_NORMAL,PIN_PU,2);
/*mikroBUS pinmuxing*/
/*mikroBUS PWM*/
light_pin_mux(QSPI0_CSN1,3); // MB_PWM
light_pin_cfg(QSPI0_CSN1,PIN_SPEED_NORMAL,PIN_PN,2);
/*mikroBUS GPIO*/
light_pin_mux(AUDIO_PA3,3); // MB_RST
light_pin_mux(GPIO2_21,0); // MB_INT
light_pin_cfg(AUDIO_PA3,PIN_SPEED_NORMAL,PIN_PN,2);
light_pin_cfg(GPIO2_21,PIN_SPEED_NORMAL,PIN_PN,2);
/*mikroBUS UART*/
light_pin_mux(UART3_RXD,3); // MB_RXD
light_pin_mux(UART3_TXD,3); // MB_TXD
light_pin_cfg(UART3_RXD,PIN_SPEED_NORMAL,PIN_PN,2);
light_pin_cfg(UART3_TXD,PIN_SPEED_NORMAL,PIN_PN,2);
/*mikroBUS SPI*/
light_pin_mux(GPIO2_20,3); // MB_CS
light_pin_mux(SPI_SCLK,3); // MB_SCK
light_pin_mux(SPI_MISO,3); // MB_MOSI
light_pin_mux(SPI_MOSI,3); // MB_MISO
light_pin_cfg(GPIO2_20,PIN_SPEED_NORMAL,PIN_PN,2);
light_pin_cfg(SPI_SCLK,PIN_SPEED_NORMAL,PIN_PN,2);
light_pin_cfg(SPI_MISO,PIN_SPEED_NORMAL,PIN_PN,2);
light_pin_cfg(SPI_MOSI,PIN_SPEED_NORMAL,PIN_PN,2);
/*mikroBUS I2C*/
light_pin_mux(GPIO0_18,0); // MB_SCL
light_pin_mux(GPIO0_19,0); // MB_SDA
light_pin_cfg(GPIO0_18,PIN_SPEED_NORMAL,PIN_PN,4);
light_pin_cfg(GPIO0_19,PIN_SPEED_NORMAL,PIN_PN,4);
/* CSI0 */
light_pin_mux(GPIO2_23,0); // CSI0
light_pin_cfg(GPIO2_23,PIN_SPEED_NORMAL,PIN_PN,2);
light_pin_cfg(I2C1_SCL,PIN_SPEED_NORMAL,PIN_PN,4);
light_pin_cfg(I2C1_SDA,PIN_SPEED_NORMAL,PIN_PN,4);
/* CSI1 */
light_pin_mux(GPIO2_24,0); // CSI1
light_pin_cfg(GPIO2_24,PIN_SPEED_NORMAL,PIN_PN,2);
light_pin_cfg(I2C3_SCL,PIN_SPEED_NORMAL,PIN_PN,4);
light_pin_cfg(I2C3_SDA,PIN_SPEED_NORMAL,PIN_PN,4);
/* EEPROM */
light_pin_mux(GPIO2_22,0); // EEPROM
light_pin_cfg(GPIO2_22,PIN_SPEED_NORMAL,PIN_PN,2);
light_pin_cfg(I2C0_SCL,PIN_SPEED_NORMAL,PIN_PN,4);
light_pin_cfg(I2C0_SDA,PIN_SPEED_NORMAL,PIN_PN,4);
/* AM6203BM */
light_pin_mux(SDIO1_WPRTN,3);
light_pin_mux(SDIO1_DETN,3);
light_pin_mux(GPIO2_25,0);
light_pin_mux(GPIO2_30,0);
light_pin_mux(GPIO2_31,0);
light_pin_cfg(SDIO1_WPRTN,PIN_SPEED_NORMAL,PIN_PU,2);
light_pin_cfg(SDIO1_DETN,PIN_SPEED_NORMAL,PIN_PN,2);
light_pin_cfg(GPIO2_25,PIN_SPEED_NORMAL,PIN_PN,2);
light_pin_cfg(GPIO2_30,PIN_SPEED_NORMAL,PIN_PN,2);
light_pin_cfg(GPIO2_31,PIN_SPEED_NORMAL,PIN_PU,2);
//BT hardware flow control uart
light_pin_cfg(UART4_TXD, PIN_SPEED_NORMAL, PIN_PN, 2);
light_pin_cfg(UART4_RXD, PIN_SPEED_NORMAL, PIN_PN, 2);
light_pin_cfg(UART4_CTSN, PIN_SPEED_NORMAL, PIN_PN, 2);
light_pin_cfg(UART4_RTSN, PIN_SPEED_NORMAL, PIN_PN, 2);
}
#elif defined (CONFIG_TARGET_LIGHT_FM_C910_MILKV_MELES)
static void light_iopin_init(void)
{
/* aon-padmux config */
light_pin_cfg(I2C_AON_SCL,PIN_SPEED_NORMAL,PIN_PN,8);
light_pin_cfg(I2C_AON_SDA,PIN_SPEED_NORMAL,PIN_PN,8);
light_pin_mux(AOGPIO_7,3);
light_pin_mux(AOGPIO_8,3);
light_pin_mux(AOGPIO_9,3);
light_pin_mux(AOGPIO_10,3);
light_pin_mux(AOGPIO_11,0);
light_pin_mux(AOGPIO_12,1);
light_pin_mux(AOGPIO_13,1);
light_pin_mux(AOGPIO_14,0);
light_pin_mux(AOGPIO_15,0);
light_pin_cfg(AOGPIO_7,PIN_SPEED_NORMAL,PIN_PN,2);
light_pin_cfg(AOGPIO_8,PIN_SPEED_NORMAL,PIN_PN,2);
light_pin_cfg(AOGPIO_9,PIN_SPEED_NORMAL,PIN_PN,2);
light_pin_cfg(AOGPIO_10,PIN_SPEED_NORMAL,PIN_PN,2);
light_pin_cfg(AOGPIO_11,PIN_SPEED_NORMAL,PIN_PN,2);
light_pin_cfg(AOGPIO_14,PIN_SPEED_NORMAL,PIN_PN,2);
light_pin_cfg(AOGPIO_15,PIN_SPEED_NORMAL,PIN_PN,2);
light_pin_mux(AUDIO_PA9,3);
light_pin_cfg(AUDIO_PA9,PIN_SPEED_NORMAL,PIN_PN,2);
light_pin_mux(AUDIO_PA10,3);
light_pin_cfg(AUDIO_PA10,PIN_SPEED_NORMAL,PIN_PU,2);
light_pin_mux(AUDIO_PA12,3);
light_pin_cfg(AUDIO_PA12,PIN_SPEED_NORMAL,PIN_PU,2);
light_pin_mux(AUDIO_PA13,0);
/*ap-padmux on left/top */
light_pin_mux(QSPI1_CSN0,3);
light_pin_mux(QSPI1_D2_WP,1);
light_pin_cfg(QSPI1_CSN0,PIN_SPEED_NORMAL,PIN_PN,8);
light_pin_cfg(QSPI1_SCLK,PIN_SPEED_NORMAL,PIN_PN,8);
light_pin_cfg(QSPI1_D0_MOSI,PIN_SPEED_NORMAL,PIN_PU,8);
light_pin_cfg(QSPI1_D1_MISO,PIN_SPEED_NORMAL,PIN_PU,8);
light_pin_cfg(QSPI1_D2_WP,PIN_SPEED_NORMAL,PIN_PN,0xF);
light_pin_cfg(QSPI1_D3_HOLD,PIN_SPEED_NORMAL,PIN_PN,8);
light_pin_mux(I2C0_SCL,0);
light_pin_mux(I2C0_SDA,0);
light_pin_cfg(I2C0_SCL,PIN_SPEED_NORMAL,PIN_PN,4);
light_pin_cfg(I2C0_SDA,PIN_SPEED_NORMAL,PIN_PN,4);
light_pin_mux(UART3_TXD,1);
light_pin_mux(UART3_RXD,1);
light_pin_cfg(UART3_TXD,PIN_SPEED_NORMAL,PIN_PN,2);
light_pin_cfg(UART3_RXD,PIN_SPEED_NORMAL,PIN_PN,2);
light_pin_mux(GPIO0_18,1);
light_pin_mux(GPIO0_19,1);
light_pin_cfg(GPIO0_18,PIN_SPEED_NORMAL,PIN_PN,4);
light_pin_cfg(GPIO0_19,PIN_SPEED_NORMAL,PIN_PN,4);
light_pin_mux(GPIO0_20,0);
light_pin_mux(GPIO0_21,0);
light_pin_mux(GPIO0_22,1);
light_pin_mux(GPIO0_23,1);
light_pin_mux(GPIO0_24,1);
light_pin_mux(GPIO0_25,1);
light_pin_mux(GPIO0_26,1);
light_pin_mux(GPIO0_27,0);
light_pin_mux(GPIO0_28,0);
light_pin_mux(GPIO0_29,0);
light_pin_mux(GPIO0_30,0);
light_pin_cfg(GPIO0_20,PIN_SPEED_NORMAL,PIN_PN,2);
light_pin_cfg(GPIO0_21,PIN_SPEED_NORMAL,PIN_PN,2);
light_pin_cfg(GPIO0_27,PIN_SPEED_NORMAL,PIN_PN,2);
light_pin_cfg(GPIO0_28,PIN_SPEED_NORMAL,PIN_PN,2);
light_pin_cfg(GPIO0_29,PIN_SPEED_NORMAL,PIN_PN,2);
light_pin_cfg(GPIO0_30,PIN_SPEED_NORMAL,PIN_PU,2);
light_pin_mux(GPIO1_0,1);
light_pin_mux(GPIO1_1,1);
light_pin_mux(GPIO1_2,1);
light_pin_mux(GPIO1_3,1);
light_pin_mux(GPIO1_4,1);
light_pin_mux(GPIO1_9,0);
light_pin_mux(GPIO1_10,0);
light_pin_mux(GPIO1_11,0);
light_pin_mux(GPIO1_12,0);
light_pin_mux(GPIO1_13,0);
light_pin_mux(GPIO1_14,0);
light_pin_mux(GPIO1_15,0);
light_pin_mux(GPIO1_16,0);
light_pin_mux(GPIO1_21,3);
light_pin_mux(GPIO1_22,3);
light_pin_mux(GPIO1_23,3);
light_pin_mux(GPIO1_24,3);
light_pin_mux(GPIO1_25,3);
light_pin_cfg(GPIO1_0,PIN_SPEED_NORMAL,PIN_PN,2);
light_pin_cfg(GPIO1_1,PIN_SPEED_NORMAL,PIN_PN,2);
light_pin_cfg(GPIO1_2,PIN_SPEED_NORMAL,PIN_PN,2);
light_pin_cfg(GPIO1_3,PIN_SPEED_NORMAL,PIN_PN,2);
light_pin_cfg(GPIO1_4,PIN_SPEED_NORMAL,PIN_PN,2);
light_pin_cfg(GPIO1_9,PIN_SPEED_NORMAL,PIN_PN,2);
light_pin_cfg(GPIO1_10,PIN_SPEED_NORMAL,PIN_PN,2);
light_pin_cfg(GPIO1_11,PIN_SPEED_NORMAL,PIN_PN,2);
light_pin_cfg(GPIO1_12,PIN_SPEED_NORMAL,PIN_PN,2);
light_pin_cfg(GPIO1_13,PIN_SPEED_NORMAL,PIN_PN,2);
light_pin_cfg(GPIO1_14,PIN_SPEED_NORMAL,PIN_PN,2);
light_pin_cfg(GPIO1_15,PIN_SPEED_NORMAL,PIN_PN,2);
light_pin_cfg(GPIO1_16,PIN_SPEED_NORMAL,PIN_PN,2);
light_pin_cfg(GPIO1_21,PIN_SPEED_NORMAL,PIN_PN,2);
light_pin_cfg(GPIO1_22,PIN_SPEED_NORMAL,PIN_PN,2);
light_pin_cfg(GPIO1_23,PIN_SPEED_NORMAL,PIN_PN,2);
light_pin_cfg(GPIO1_24,PIN_SPEED_NORMAL,PIN_PN,2);
light_pin_cfg(GPIO1_25,PIN_SPEED_NORMAL,PIN_PN,2);
light_pin_cfg(GPIO1_26,PIN_SPEED_NORMAL,PIN_PN,2);
light_pin_mux(CLK_OUT_0,1);
light_pin_mux(CLK_OUT_1,1);
light_pin_mux(CLK_OUT_3,1);
light_pin_mux(CLK_OUT_2,3);
light_pin_cfg(CLK_OUT_2,PIN_SPEED_NORMAL,PIN_PU,2);
/*ap-pdmux on righ/top*/
light_pin_mux(QSPI0_SCLK,3);
light_pin_mux(QSPI0_CSN0,3);
light_pin_mux(QSPI0_CSN1,3);
light_pin_mux(QSPI0_D0_MOSI,3);
light_pin_mux(QSPI0_D1_MISO,3);
light_pin_mux(QSPI0_D2_WP,3);
light_pin_mux(QSPI0_D3_HOLD,3);
light_pin_cfg(I2C2_SCL,PIN_SPEED_NORMAL,PIN_PN,4);
light_pin_cfg(I2C2_SDA,PIN_SPEED_NORMAL,PIN_PN,4);
light_pin_mux(I2C3_SCL,0);
light_pin_mux(I2C3_SDA,0);
light_pin_cfg(I2C3_SCL,PIN_SPEED_NORMAL,PIN_PU,4);
light_pin_cfg(I2C3_SDA,PIN_SPEED_NORMAL,PIN_PU,4);
light_pin_mux(SPI_CSN,1);
light_pin_cfg(SPI_CSN,PIN_SPEED_NORMAL,PIN_PU,2);
light_pin_mux(GPIO2_18,0);
light_pin_mux(GPIO2_19,0);
light_pin_mux(GPIO2_20,0);
light_pin_mux(GPIO2_21,0);
light_pin_mux(GPIO2_22,0);
light_pin_mux(GPIO2_23,0);
light_pin_mux(GPIO2_24,0);
light_pin_mux(GPIO2_25,0);
light_pin_cfg(GPIO2_18,PIN_SPEED_NORMAL,PIN_PN,2);
light_pin_cfg(GPIO2_19,PIN_SPEED_NORMAL,PIN_PN,2);
light_pin_cfg(GPIO2_20,PIN_SPEED_NORMAL,PIN_PN,2);
light_pin_cfg(GPIO2_21,PIN_SPEED_NORMAL,PIN_PN,2);
light_pin_cfg(GPIO2_22,PIN_SPEED_NORMAL,PIN_PN,2);
light_pin_cfg(GPIO2_23,PIN_SPEED_NORMAL,PIN_PN,2);
light_pin_cfg(GPIO2_24,PIN_SPEED_NORMAL,PIN_PN,2);
light_pin_cfg(GPIO2_25,PIN_SPEED_NORMAL,PIN_PU,2);
light_pin_mux(SDIO0_WPRTN,3);
light_pin_cfg(SDIO0_WPRTN,PIN_SPEED_NORMAL,PIN_PN,2);
light_pin_mux(SDIO1_WPRTN,3);
light_pin_cfg(SDIO1_WPRTN,PIN_SPEED_NORMAL,PIN_PU,2);
light_pin_mux(SDIO1_DETN,3);
light_pin_cfg(SDIO1_DETN,PIN_SPEED_NORMAL,PIN_PN,2);
light_pin_mux(GPIO2_30,0);
light_pin_mux(GPIO2_31,0);
light_pin_mux(GPIO3_0,0);
light_pin_mux(GPIO3_1,0);
light_pin_mux(GPIO3_2,1);
light_pin_mux(GPIO3_3,1);
light_pin_cfg(GPIO2_30, PIN_SPEED_NORMAL, PIN_PN, 0x2);
light_pin_cfg(GPIO2_31, PIN_SPEED_NORMAL, PIN_PN, 0x2);
light_pin_cfg(GPIO3_0, PIN_SPEED_NORMAL, PIN_PN, 0x2);
light_pin_cfg(GPIO3_1, PIN_SPEED_NORMAL, PIN_PN, 0x2);
light_pin_cfg(GPIO3_2, PIN_SPEED_NORMAL, PIN_PN, 0xF);
light_pin_cfg(GPIO3_3, PIN_SPEED_NORMAL, PIN_PN, 0xF);
light_pin_mux(GMAC0_COL,3);
light_pin_mux(GMAC0_CRS,3);
light_pin_cfg(GMAC0_COL,PIN_SPEED_NORMAL,PIN_PU,2);
light_pin_cfg(GMAC0_CRS,PIN_SPEED_NORMAL,PIN_PU,2);
/* GMAC0 pad drive strength configurate to 0xF */
light_pin_cfg(GMAC0_TX_CLK, PIN_SPEED_NORMAL, PIN_PN, 0xF);
light_pin_cfg(GMAC0_RX_CLK, PIN_SPEED_NORMAL, PIN_PN, 0xF);
light_pin_cfg(GMAC0_TXEN, PIN_SPEED_NORMAL, PIN_PN, 0xF);
light_pin_cfg(GMAC0_TXD0, PIN_SPEED_NORMAL, PIN_PN, 0xF);
light_pin_cfg(GMAC0_TXD1, PIN_SPEED_NORMAL, PIN_PN, 0xF);
light_pin_cfg(GMAC0_TXD2, PIN_SPEED_NORMAL, PIN_PN, 0xF);
light_pin_cfg(GMAC0_TXD3, PIN_SPEED_NORMAL, PIN_PN, 0xF);
light_pin_cfg(GMAC0_RXDV, PIN_SPEED_NORMAL, PIN_PN, 0xF);
light_pin_cfg(GMAC0_RXD0, PIN_SPEED_NORMAL, PIN_PN, 0xF);
light_pin_cfg(GMAC0_RXD1, PIN_SPEED_NORMAL, PIN_PN, 0xF);
light_pin_cfg(GMAC0_RXD2, PIN_SPEED_NORMAL, PIN_PN, 0xF);
light_pin_cfg(GMAC0_RXD3, PIN_SPEED_NORMAL, PIN_PN, 0xF);
}
#else
static void light_iopin_init(void)
{
light_pin_cfg(I2C_AON_SCL,PIN_SPEED_NORMAL,PIN_PN,4);
light_pin_cfg(I2C_AON_SDA,PIN_SPEED_NORMAL,PIN_PN,4);
light_pin_cfg(AOGPIO_8,PIN_SPEED_NORMAL,PIN_PN,2);
light_pin_cfg(AOGPIO_9,PIN_SPEED_NORMAL,PIN_PN,2);
light_pin_cfg(AOGPIO_14, PIN_SPEED_NORMAL, PIN_PN, 2);
light_pin_mux(AOGPIO_10,1);
light_pin_mux(AOGPIO_11,1);
light_pin_mux(AOGPIO_12,1);
light_pin_mux(AOGPIO_13,1);
light_pin_mux(AOGPIO_14, 0);
light_pin_mux(AUDIO_PA30,3);
/*qspi1 cs0 gpio0-1 pad strength and pin-pull mode*/
@@ -2432,10 +1859,10 @@ int board_init(void)
static void light_usb_boot_check(void)
{
uchar env_enetaddr[6];
uchar env_enet1addr[6];
int env_ethaddr_flag,env_eth1addr_flag;
int boot_mode;
uchar env_enetaddr[6]={0};
uchar env_enet1addr[6]={0};
int env_ethaddr_flag,env_eth1addr_flag;
int ret = 0;
boot_mode = readl((void *)SOC_OM_ADDRBASE) & 0x7;
@@ -2451,49 +1878,32 @@ static void light_usb_boot_check(void)
#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
env_set("usb_fastboot", "yes");
#endif
/* ensure flashing img not to lose mac address on ramfs mode */
env_ethaddr_flag = eth_env_get_enetaddr_by_index("eth", 0, env_enetaddr);
env_eth1addr_flag = eth_env_get_enetaddr_by_index("eth", 1, env_enet1addr);
run_command("env default -a -f", 0);
if (env_ethaddr_flag)
eth_env_set_enetaddr_by_index("eth", 0, env_enetaddr);
if (env_eth1addr_flag)
eth_env_set_enetaddr_by_index("eth", 1, env_enet1addr);
env_save();
run_command("run gpt_partition", 0);
run_command("fastboot usb 0", 0);
}
static void light_mac_vaild_check(void)
{
uchar env_enetaddr[6];
uchar env_enet1addr[6];
int env_ethaddr_flag,env_eth1addr_flag;
/*Get this version ethaddr(mac addr) env,which follows one board, trans to next version env*/
env_ethaddr_flag = eth_env_get_enetaddr_by_index("eth", 0, env_enetaddr);
env_eth1addr_flag = eth_env_get_enetaddr_by_index("eth", 1, env_enet1addr);
if (!env_ethaddr_flag || !env_eth1addr_flag) {
net_random_ethaddr(env_enetaddr);
if (env_enetaddr[5] == (uchar)(0xff)) {
env_enetaddr[5] = 0xfe;
}
run_command("env default -a -f", 0);
/*If mac addr in last version env is valid, before save,inherit env mac addr */
if(env_ethaddr_flag){
eth_env_set_enetaddr_by_index("eth", 0, env_enetaddr);
env_enetaddr[5] += 0x01;
eth_env_set_enetaddr_by_index("eth", 1, env_enetaddr);
printf("Use random addr as fixed mac addr\n");
env_save();
run_command("printenv ethaddr",0);
}else{
printf("env ethaddr not exist or invalid\n");
}
printf("ethaddr: %s\n", env_get("ethaddr"));
printf("eth1addr: %s\n", env_get("eth1addr"));
if(env_eth1addr_flag){
eth_env_set_enetaddr_by_index("eth", 1, env_enet1addr);
run_command("printenv eth1addr",0);
}else{
printf("env eth1addr not exist or invalid\n");
}
return;
run_command("env save", 0);
run_command("run gpt_partition", 0);
run_command("fastboot usb 0", 0);
}
int board_late_init(void)
{
@@ -2503,18 +1913,9 @@ int board_late_init(void)
sec_upgrade_thread();
sec_firmware_version_dump();
#endif
light_usb_boot_check();
light_mac_vaild_check();
ap_peri_clk_disable();
#ifdef CONFIG_MCU_HC32fX
mcu_poweron();
#endif
#ifdef CONFIG_DM_CHARGE_DISPLAY
charge_display();
#endif
return 0;
}
@@ -2544,208 +1945,3 @@ U_BOOT_CMD(
"check ethaddrs in environment variables is valid",
""
);
#define PAGE_SIZE 4096
#define HIBERNATE_SIG "S1SUSPEND"
#define HIBERNATE_SIG2 "S1SUSPEN2" //sign for 2nd time load image
static inline int fdt_disabled_node(void *blob,const char *path)
{
int offset;
offset = fdt_path_offset(blob,path);
if (offset < 0) {
printf("ERROR:failed to find %s node in dtb (ret %d)\n",path,offset);
return offset;
}
return fdt_status_disabled(blob,offset);
}
static int do_board_check_hibernate(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[])
{
int ret;
char runcmd[128];
ulong addr;
void *blob = NULL;
ulong mask = 0;
int mmc_parts;
int resume_part;
bool fastresume = 0;
#define ON_RET_ERROR(str) if(ret < 0) printf("set node %s status failed %d\n",str,ret)
ALLOC_CACHE_ALIGN_BUFFER(u8,swsusp_header_buf,PAGE_SIZE);
u8 *header = &swsusp_header_buf[0];
mmc_parts = env_get_hex("mmcpart",3);
resume_part = mmc_parts - 2;
if(argc >= 4) { // is user pass in ,use that
sprintf(runcmd, "read %s %s %s 0 8",
argv[1],argv[2],argv[3]);
header = (u8 *)simple_strtoul(argv[3],NULL,16);
if(argc >= 5)
mask = simple_strtoul(argv[4],NULL,16);
printf("read swsusp_header to %p,dtb disbale mask 0x%lx\n",header,mask);
} else {
sprintf(runcmd, "read mmc 0:%d 0x%lx 0 8",
resume_part,(unsigned long)&header[0]);
}
ret = run_command(runcmd, 0);
if(ret != CMD_RET_SUCCESS)
goto failed;
if(!memcmp(HIBERNATE_SIG, &header[PAGE_SIZE-10], 10) ||
!memcmp(HIBERNATE_SIG2, &header[PAGE_SIZE-10], 10) ) {
printf("found sign\n");
}
else {
sprintf(runcmd, "0:%s",env_get("mmcbootpart"));
if(file_exists("mmc",runcmd,"no_fastresume",FS_TYPE_EXT)) {
printf("do not fastresume\n");
goto default_set;
}
sprintf(runcmd, "read mmc 0:%d 0x%lx 0 8",
resume_part+1,(unsigned long)&header[0]);
ret = run_command(runcmd, 0);
if(ret != CMD_RET_SUCCESS)
goto failed;
if(!memcmp(HIBERNATE_SIG, &header[PAGE_SIZE-10], 10) ||
!memcmp(HIBERNATE_SIG2, &header[PAGE_SIZE-10], 10) ) {
printf("found fastresume sign\n");
resume_part = resume_part+1;
fastresume = true;
}
else {
printf(" not find hibernate sign\n");
goto default_set;
}
}
/*get dtb address*/
if(env_get("dtb_addr") == NULL)
{
printf("Cannot get dtb_addr,check flow !\n");
goto failed;
}
addr = env_get_hex("dtb_addr",0);
sprintf(runcmd, "fdt addr 0x%lx", env_get_hex("dtb_addr",0));
ret = run_command(runcmd, 0);
if(ret != CMD_RET_SUCCESS)
goto failed;
sprintf(runcmd, "fdt resize");
ret = run_command(runcmd, 0);
if(ret != CMD_RET_SUCCESS)
goto failed;
/*set unneed devices node disabled for hibernate resume in kernel dtb*/
blob = (void *)addr;
ret = fdt_status_disabled_by_alias(blob,"i2c0");
ON_RET_ERROR("i2c0");
ret = fdt_status_disabled_by_alias(blob,"i2c1");
ON_RET_ERROR("i2c1");
ret = fdt_status_disabled_by_alias(blob,"i2c2");
ON_RET_ERROR("i2c2");
ret = fdt_status_disabled_by_alias(blob,"audio_i2c0");
ON_RET_ERROR("audio_i2c0");
ret = fdt_status_disabled_by_alias(blob,"audio_i2c1");
ON_RET_ERROR("audio_i2c1");
ret = fdt_status_disabled_by_alias(blob,"ethernet0");
ON_RET_ERROR("ethernet0");
ret = fdt_status_disabled_by_alias(blob,"ethernet1");
ON_RET_ERROR("ethernet1");
ret = fdt_status_disabled_by_alias(blob,"spi0");
ON_RET_ERROR("spi0");
ret = fdt_status_disabled_by_alias(blob,"spi1");
ON_RET_ERROR("spi1");
ret = fdt_status_disabled_by_alias(blob,"spi2");
ON_RET_ERROR("spi2");
ret = fdt_disabled_node(blob,"/soc/adc");
ON_RET_ERROR("/soc/adc");
//default mask is 0, need set this node disbaled
if(0 == (mask & 0x01)) {
ret = fdt_disabled_node(blob,"/soc/light_i2s");
ON_RET_ERROR("/soc/light_i2s");
ret = fdt_disabled_node(blob,"/soc/audio_i2s0");
ON_RET_ERROR("/soc/audio_i2s0");
ret = fdt_disabled_node(blob,"/soc/audio_i2s1");
ON_RET_ERROR("/soc/audio_i2s1");
ret = fdt_disabled_node(blob,"/soc/audio_i2s2");
ON_RET_ERROR("/soc/audio_i2s2");
}
if(0 == (mask & 0x02)) {
ret = fdt_disabled_node(blob,"/soc/audio_i2s_8ch_sd0");
ON_RET_ERROR("/soc/audio_i2s_8ch_sd0");
ret = fdt_disabled_node(blob,"/soc/audio_i2s_8ch_sd1");
ON_RET_ERROR("/soc/audio_i2s_8ch_sd1");
ret = fdt_disabled_node(blob,"/soc/audio_i2s_8ch_sd2");
ON_RET_ERROR("/soc/audio_i2s_8ch_sd2");
ret = fdt_disabled_node(blob,"/soc/audio_i2s_8ch_sd3");
ON_RET_ERROR("/soc/audio_i2s_8ch_sd3");
}
/*set resume_bootargs for kernel do fast bootup */
sprintf(runcmd,"resume=/dev/mmcblk0p%d notrace noftrace nopty noclkdebug ",resume_part);
env_set("resume_bootargs",runcmd);
return CMD_RET_SUCCESS;
default_set:
sprintf(runcmd,"resume=/dev/mmcblk0p%d",resume_part);
env_set("resume_bootargs",runcmd);
return CMD_RET_SUCCESS;
failed:
printf("ERROR:runcmd %s failed!\n",runcmd);
sprintf(runcmd,"resume=/dev/mmcblk0p%d",resume_part);
env_set("resume_bootargs",runcmd);
return CMD_RET_FAILURE;
}
U_BOOT_CMD(
chk_hibernate, 6, 0, do_board_check_hibernate,
"check hibernate image sign,if valid set dtb nodes and bootargs for fast boot resume",
" [<interface> <dev[:part]>] [mask]"
);
#ifdef CONFIG_FIXUP_MEMORY_REGION
static int do_fixup_memory_region(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[])
{
ulong addr;
void *blob = NULL;
DECLARE_GLOBAL_DATA_PTR;
u64 base, size;
base = gd->ram_base;
size = gd->ram_size;
/*get dtb address*/
if(env_get("dtb_addr") == NULL)
{
printf("Cannot get dtb_addr,check flow !\n");
return CMD_RET_FAILURE;
}
addr = env_get_hex("dtb_addr",0);
/*set unneed devices node disabled for hibernate resume in kernel dtb*/
blob = (void *)addr;
fdtdec_setup_mem_size_base_fdt(blob);
size -= gd->ram_base;
if (size != gd->ram_size) {
printf("fixup memory region from [0x%09lx ~ 0x%09lx] to [0x%09lx ~ 0x%09lx]\n",
gd->ram_base, gd->ram_base+gd->ram_size, gd->ram_base, gd->ram_base+size);
gd->ram_size = size;
fdt_fixup_memory(blob, gd->ram_base, gd->ram_size);
}
return CMD_RET_SUCCESS;
}
U_BOOT_CMD(
fixup_memory_region, 2, 0, do_fixup_memory_region,
"modify linux memory region via gd->ram_size",
""
);
#endif

6
board/thead/light-c910/lpddr-regu/ddr_regu.c
View File

@@ -136,7 +136,7 @@ static const struct regulator_t g_apcpu_regu_id_list[] = {
REGU_ID_DEF(IIC_IDX_AONIIC,APCPU_REGU_VDDM,0x31,0x39,0,1,800000,600000,3500000,12500,1),
},
};
#elif defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_A_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_B_REF) || (CONFIG_TARGET_LIGHT_FM_C910_BEAGLE) || defined (CONFIG_TARGET_LIGHT_FM_C910_LPI4A) || defined (CONFIG_TARGET_LIGHT_FM_C910_MILKV_MELES)
#elif defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_A_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_B_REF) || (CONFIG_TARGET_LIGHT_FM_C910_BEAGLE) || defined (CONFIG_TARGET_LIGHT_FM_C910_LPI4A)
/**
* board for ant-ref
*
@@ -794,7 +794,7 @@ static void light_iopmp_config(void)
}
}
int aon_local_init(void)
int pmic_ddr_regu_init(void)
{
#define AON_PADMUX_BASE (0xfffff4a000)
int ret;
@@ -955,7 +955,7 @@ int pmic_reset_apcpu_voltage(void)
return ret;
return 0;
}
#elif defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_A_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_B_REF)|| (CONFIG_TARGET_LIGHT_FM_C910_BEAGLE) || defined (CONFIG_TARGET_LIGHT_FM_C910_LPI4A) || defined (CONFIG_TARGET_LIGHT_FM_C910_MILKV_MELES)
#elif defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_A_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_B_REF)|| (CONFIG_TARGET_LIGHT_FM_C910_BEAGLE) || defined (CONFIG_TARGET_LIGHT_FM_C910_LPI4A)
int pmic_reset_apcpu_voltage(void)
{
int ret = -1;

2
board/thead/light-c910/lpddr-regu/ddr_regu.h
View File

@@ -9,5 +9,5 @@
#define __DDR_REGU_H__
int pmic_ddr_set_voltage(void);
int aon_local_init(void);
int pmic_ddr_regu_init(void);
#endif

218
board/thead/light-c910/lpddr4/include/aonsys_reg_define.h
View File

@@ -1,218 +0,0 @@
//------------------------------------------------------------
// DONOT MODIFY THIS FILE
// generated by JISHENGJU automatically
//------------------------------------------------------------
#ifndef AONSYS_SYSREG_REG_OFFSET_DEFINE_H
#define AONSYS_SYSREG_REG_OFFSET_DEFINE_H
#define AONSYS_REG_BASE 0xFFFFF48000
#define REG_AON_CPU_LP_MODE (AONSYS_REG_BASE + 0x0 )
#define REG_AON_CHIP_LP_MODE (AONSYS_REG_BASE + 0x4 )
#define REG_AON_AO_SERAM_TRN (AONSYS_REG_BASE + 0x10 )
#define REG_AON_AO_SERAM_INT (AONSYS_REG_BASE + 0x14 )
#define REG_AON_STR_SERAM_TRN (AONSYS_REG_BASE + 0x18 )
#define REG_AON_STR_SERAM_INT (AONSYS_REG_BASE + 0x1c )
#define REG_AON_STR_INDICATOR_0 (AONSYS_REG_BASE + 0x20 )
#define REG_AON_STR_INDICATOR_1 (AONSYS_REG_BASE + 0x24 )
#define REG_AON_STR_INDICATOR_2 (AONSYS_REG_BASE + 0x28 )
#define REG_AON_STR_INDICATOR_3 (AONSYS_REG_BASE + 0x2c )
#define REG_AON_PVTC_WR_LOCK (AONSYS_REG_BASE + 0x30 )
#define REG_AON_PVTC_TS_ALARM (AONSYS_REG_BASE + 0x34 )
#define REG_AON_PVTC_VM_ALARM (AONSYS_REG_BASE + 0x38 )
#define REG_AON_PVTC_PD_ALARM (AONSYS_REG_BASE + 0x3c )
#define REG_AON_E902_CNT_CLR (AONSYS_REG_BASE + 0x40 )
#define REG_AON_E902_RST_ADDR (AONSYS_REG_BASE + 0x44 )
#define REG_AON_C906_RST_ADDR_L (AONSYS_REG_BASE + 0x48 )
#define REG_AON_C906_RST_ADDR_H (AONSYS_REG_BASE + 0x4c )
#define REG_AON_RESERVED_REG_0 (AONSYS_REG_BASE + 0x50 )
#define REG_AON_RESERVED_REG_1 (AONSYS_REG_BASE + 0x54 )
#define REG_AON_RESERVED_REG_2 (AONSYS_REG_BASE + 0x58 )
#define REG_AON_RESERVED_REG_3 (AONSYS_REG_BASE + 0x5c )
#define REG_AON_AON_AHB_ADEXT (AONSYS_REG_BASE + 0x60 )
#define REG_AON_RC_EN (AONSYS_REG_BASE + 0x70 )
#define REG_AON_RC_FCAL (AONSYS_REG_BASE + 0x74 )
#define REG_AON_RC_MODE (AONSYS_REG_BASE + 0x78 )
#define REG_AON_RC_READY (AONSYS_REG_BASE + 0x7c )
#define REG_AON_ISO_CFG (AONSYS_REG_BASE + 0x80 )
#define REG_AON_OCRAM_ERR (AONSYS_REG_BASE + 0x90 )
#define REG_AON_TIMER_LINK (AONSYS_REG_BASE + 0x100)
#define REG_AON_PD_REQ (AONSYS_REG_BASE + 0x110)
#define REG_AON_PD_ISO_EN_SET (AONSYS_REG_BASE + 0x114)
#define REG_AON_PD_ISO_EN_CLR (AONSYS_REG_BASE + 0x118)
#define REG_AON_PD_SW_EN_SET (AONSYS_REG_BASE + 0x11c)
#define REG_AON_PD_SW_EN_CLR (AONSYS_REG_BASE + 0x120)
#define REG_AON_PD_SW_ACK (AONSYS_REG_BASE + 0x124)
#define REG_AON_PD_SW_CNT_EN (AONSYS_REG_BASE + 0x128)
#define REG_AON_PD_FSM_RST (AONSYS_REG_BASE + 0x12c)
#define REG_AON_PD_INT_MASK (AONSYS_REG_BASE + 0x130)
#define REG_AON_PD_FSM_STS_L (AONSYS_REG_BASE + 0x134)
#define REG_AON_PD_FSM_STS_H (AONSYS_REG_BASE + 0x138)
#define REG_AON_PD_INT_STS (AONSYS_REG_BASE + 0x13c)
#define REG_AON_PD_INT_CLR (AONSYS_REG_BASE + 0x140)
#define REG_AON_PD_BLK0_SW_CNT (AONSYS_REG_BASE + 0x144)
#define REG_AON_PD_BLK1_SW_CNT (AONSYS_REG_BASE + 0x148)
#define REG_AON_PD_BLK2_SW_CNT (AONSYS_REG_BASE + 0x14c)
#define REG_AON_PD_BLK3_SW_CNT (AONSYS_REG_BASE + 0x150)
#define REG_AON_PD_BLK4_SW_CNT (AONSYS_REG_BASE + 0x154)
#define REG_AON_PD_BLK5_SW_CNT (AONSYS_REG_BASE + 0x158)
#define REG_AON_PD_BLK6_SW_CNT (AONSYS_REG_BASE + 0x15c)
#define REG_AON_PD_BLK7_SW_CNT (AONSYS_REG_BASE + 0x160)
#define REG_AON_PD_BLK8_SW_CNT (AONSYS_REG_BASE + 0x164)
#define REG_AON_PD_BLK9_SW_CNT (AONSYS_REG_BASE + 0x168)
#define REG_AON_PD_BLK10_SW_CNT (AONSYS_REG_BASE + 0x16c)
#define REG_AON_PD_BLK0_INTV_CNT (AONSYS_REG_BASE + 0x180)
#define REG_AON_PD_BLK1_INTV_CNT (AONSYS_REG_BASE + 0x184)
#define REG_AON_PD_BLK2_INTV_CNT (AONSYS_REG_BASE + 0x188)
#define REG_AON_PD_BLK3_INTV_CNT (AONSYS_REG_BASE + 0x18c)
#define REG_AON_PD_BLK4_INTV_CNT (AONSYS_REG_BASE + 0x190)
#define REG_AON_PD_BLK5_INTV_CNT (AONSYS_REG_BASE + 0x194)
#define REG_AON_PD_BLK6_INTV_CNT (AONSYS_REG_BASE + 0x198)
#define REG_AON_PD_BLK7_INTV_CNT (AONSYS_REG_BASE + 0x19c)
#define REG_AON_PD_BLK8_INTV_CNT (AONSYS_REG_BASE + 0x1a0)
#define REG_AON_PD_BLK9_INTV_CNT (AONSYS_REG_BASE + 0x1a4)
#define REG_AON_PD_BLK10_INTV_CNT (AONSYS_REG_BASE + 0x1a8)
#define REG_AON_AUDIO_PMU_REQ (AONSYS_REG_BASE + 0x1f8)
#define REG_AON_AUDIO_PMU_STS (AONSYS_REG_BASE + 0x1fc)
#define REG_AON_AUDIO_PMU_INTR (AONSYS_REG_BASE + 0x204)
#define REG_AON_PMU_AUDIO_REQ (AONSYS_REG_BASE + 0x208)
#define REG_AON_PMU_AUDIO_STS (AONSYS_REG_BASE + 0x20c)
#define REG_AON_MEM_LP_MODE (AONSYS_REG_BASE + 0x210)
#define REG_AON_C910_DBG_MASK (AONSYS_REG_BASE + 0x214)
#define REG_AON_C910_L2CACHE (AONSYS_REG_BASE + 0x218)
#define REG_AON_BISR_CTRL (AONSYS_REG_BASE + 0x220)
#define REG_AON_EFUSE_PRELOAD_DONE (AONSYS_REG_BASE + 0x224)
#define REG_AON_GPIO_RTE (AONSYS_REG_BASE + 0x228)
#define REG_AON_PLL_DSKEW_LOCK (AONSYS_REG_BASE + 0x22c)
#define REG_AON_SRAM_AXI_CFG (AONSYS_REG_BASE + 0x230)
#define REG_AON_SRAM_AXI_ST (AONSYS_REG_BASE + 0x234)
#define REG_AON_SRAM_AXI_ERR_STS_0 (AONSYS_REG_BASE + 0x238)
#define REG_AON_SRAM_AXI_ERR_STS_1 (AONSYS_REG_BASE + 0x23c)
#define REG_AON_SRAM_AXI_ERR_STS_2 (AONSYS_REG_BASE + 0x240)
#define REG_AON_SRAM_AXI_ERR_STS_3 (AONSYS_REG_BASE + 0x244)
#define REG_AON_SRAM_AXI_ERR_STS_4 (AONSYS_REG_BASE + 0x248)
#define REG_AON_SE_MUX_LOCK (AONSYS_REG_BASE + 0x24c)
#define REG_AON_CPU_DBG_DIS_LOCK (AONSYS_REG_BASE + 0x270)
#define REG_AON_RESERVED_REG_4 (AONSYS_REG_BASE + 0x300)
#define REG_AON_RESERVED_REG_5 (AONSYS_REG_BASE + 0x304)
#define REG_AON_RESERVED_REG_6 (AONSYS_REG_BASE + 0x308)
#define REG_AON_RESERVED_REG_7 (AONSYS_REG_BASE + 0x30c)
#define REG_AON_RESERVED_REG_8 (AONSYS_REG_BASE + 0x400)
#define REG_AON_RESERVED_REG_9 (AONSYS_REG_BASE + 0x404)
#define REG_AON_RESERVED_REG_10 (AONSYS_REG_BASE + 0x408)
#define REG_AON_RESERVED_REG_11 (AONSYS_REG_BASE + 0x40c)
#define REG_AON_RESERVED_REG_12 (AONSYS_REG_BASE + 0x500)
#define REG_AON_RESERVED_REG_13 (AONSYS_REG_BASE + 0x504)
#define REG_AON_RESERVED_REG_14 (AONSYS_REG_BASE + 0x508)
#define REG_AON_RESERVED_REG_15 (AONSYS_REG_BASE + 0x50c)
#define REG_AON_RESERVED_REG_16 (AONSYS_REG_BASE + 0x600)
#define REG_AON_RESERVED_REG_17 (AONSYS_REG_BASE + 0x604)
#define REG_AON_RESERVED_REG_18 (AONSYS_REG_BASE + 0x608)
#define REG_AON_RESERVED_REG_19 (AONSYS_REG_BASE + 0x60c)
#define CPU_LP_MODE_DFLT_VAL 0x3ff
#define CHIP_LP_MODE_DFLT_VAL 0x0
#define AO_SERAM_TRN_DFLT_VAL 0x0
#define AO_SERAM_INT_DFLT_VAL 0x0
#define STR_SERAM_TRN_DFLT_VAL 0x0
#define STR_SERAM_INT_DFLT_VAL 0x0
#define STR_INDICATOR_0_DFLT_VAL 0x0
#define STR_INDICATOR_1_DFLT_VAL 0x0
#define STR_INDICATOR_2_DFLT_VAL 0x0
#define STR_INDICATOR_3_DFLT_VAL 0x0
#define PVTC_WR_LOCK_DFLT_VAL 0x0
#define PVTC_TS_ALARM_DFLT_VAL 0x0
#define PVTC_VM_ALARM_DFLT_VAL 0x0
#define PVTC_PD_ALARM_DFLT_VAL 0x0
#define E902_CNT_CLR_DFLT_VAL 0x0
#define E902_RST_ADDR_DFLT_VAL 0xffef8000
#define C906_RST_ADDR_L_DFLT_VAL 0xc0000000
#define C906_RST_ADDR_H_DFLT_VAL 0xff
#define RESERVED_REG_0_DFLT_VAL 0x0
#define RESERVED_REG_1_DFLT_VAL 0x0
#define RESERVED_REG_2_DFLT_VAL 0x0
#define RESERVED_REG_3_DFLT_VAL 0x0
#define AON_AHB_ADEXT_DFLT_VAL 0x0
#define RC_EN_DFLT_VAL 0x1
#define RC_FCAL_DFLT_VAL 0x77f
#define RC_MODE_DFLT_VAL 0x1
#define RC_READY_DFLT_VAL 0x0
#define ISO_CFG_DFLT_VAL 0x0
#define OCRAM_ERR_DFLT_VAL 0x0
#define TIMER_LINK_DFLT_VAL 0x0
#define PD_REQ_DFLT_VAL 0x0
#define PD_ISO_EN_SET_DFLT_VAL 0x0
#define PD_ISO_EN_CLR_DFLT_VAL 0x0
#define PD_SW_EN_SET_DFLT_VAL 0x0
#define PD_SW_EN_CLR_DFLT_VAL 0x0
#define PD_SW_ACK_DFLT_VAL 0x3fffff
#define PD_SW_CNT_EN_DFLT_VAL 0x0
#define PD_FSM_RST_DFLT_VAL 0x0
#define PD_INT_MASK_DFLT_VAL 0x3fffff
#define PD_FSM_STS_L_DFLT_VAL 0x0
#define PD_FSM_STS_H_DFLT_VAL 0x0
#define PD_INT_STS_DFLT_VAL 0x0
#define PD_INT_CLR_DFLT_VAL 0x0
#define PD_BLK0_SW_CNT_DFLT_VAL 0xff00ff
#define PD_BLK1_SW_CNT_DFLT_VAL 0xff00ff
#define PD_BLK2_SW_CNT_DFLT_VAL 0xff00ff
#define PD_BLK3_SW_CNT_DFLT_VAL 0xff00ff
#define PD_BLK4_SW_CNT_DFLT_VAL 0xff00ff
#define PD_BLK5_SW_CNT_DFLT_VAL 0xff00ff
#define PD_BLK6_SW_CNT_DFLT_VAL 0xff00ff
#define PD_BLK7_SW_CNT_DFLT_VAL 0xff00ff
#define PD_BLK8_SW_CNT_DFLT_VAL 0xff00ff
#define PD_BLK9_SW_CNT_DFLT_VAL 0xff00ff
#define PD_BLK10_SW_CNT_DFLT_VAL 0xff00ff
#define PD_BLK0_INTV_CNT_DFLT_VAL 0xff0ffff
#define PD_BLK1_INTV_CNT_DFLT_VAL 0xff0ffff
#define PD_BLK2_INTV_CNT_DFLT_VAL 0xff0ffff
#define PD_BLK3_INTV_CNT_DFLT_VAL 0xff0ffff
#define PD_BLK4_INTV_CNT_DFLT_VAL 0xff0ffff
#define PD_BLK5_INTV_CNT_DFLT_VAL 0xff0ffff
#define PD_BLK6_INTV_CNT_DFLT_VAL 0xff0ffff
#define PD_BLK7_INTV_CNT_DFLT_VAL 0xff0ffff
#define PD_BLK8_INTV_CNT_DFLT_VAL 0xff0ffff
#define PD_BLK9_INTV_CNT_DFLT_VAL 0xff0ffff
#define PD_BLK10_INTV_CNT_DFLT_VAL 0xff0ffff
#define AUDIO_PMU_REQ_DFLT_VAL 0x0
#define AUDIO_PMU_STS_DFLT_VAL 0x0
#define AUDIO_PMU_INTR_DFLT_VAL 0x0
#define PMU_AUDIO_REQ_DFLT_VAL 0x0
#define PMU_AUDIO_STS_DFLT_VAL 0x0
#define MEM_LP_MODE_DFLT_VAL 0x0
#define C910_DBG_MASK_DFLT_VAL 0x0
#define C910_L2CACHE_DFLT_VAL 0x0
#define BISR_CTRL_DFLT_VAL 0x0
#define EFUSE_PRELOAD_DONE_DFLT_VAL 0x0
#define GPIO_RTE_DFLT_VAL 0x0
#define PLL_DSKEW_LOCK_DFLT_VAL 0x0
#define SRAM_AXI_CFG_DFLT_VAL 0x0
#define SRAM_AXI_ST_DFLT_VAL 0x0
#define SRAM_AXI_ERR_STS_0_DFLT_VAL 0x0
#define SRAM_AXI_ERR_STS_1_DFLT_VAL 0x0
#define SRAM_AXI_ERR_STS_2_DFLT_VAL 0x0
#define SRAM_AXI_ERR_STS_3_DFLT_VAL 0x0
#define SRAM_AXI_ERR_STS_4_DFLT_VAL 0x0
#define SE_MUX_LOCK_DFLT_VAL 0x0
#define CPU_DBG_DIS_LOCK_DFLT_VAL 0x0
#define RESERVED_REG_4_DFLT_VAL 0x0
#define RESERVED_REG_5_DFLT_VAL 0x0
#define RESERVED_REG_6_DFLT_VAL 0x0
#define RESERVED_REG_7_DFLT_VAL 0x0
#define RESERVED_REG_8_DFLT_VAL 0x0
#define RESERVED_REG_9_DFLT_VAL 0x0
#define RESERVED_REG_10_DFLT_VAL 0x0
#define RESERVED_REG_11_DFLT_VAL 0x0
#define RESERVED_REG_12_DFLT_VAL 0x0
#define RESERVED_REG_13_DFLT_VAL 0x0
#define RESERVED_REG_14_DFLT_VAL 0x0
#define RESERVED_REG_15_DFLT_VAL 0x0
#define RESERVED_REG_16_DFLT_VAL 0x0
#define RESERVED_REG_17_DFLT_VAL 0x0
#define RESERVED_REG_18_DFLT_VAL 0x0
#define RESERVED_REG_19_DFLT_VAL 0x0
#endif

90
board/thead/light-c910/lpddr4/include/aonsys_rstget_reg_define.h
View File

@@ -1,90 +0,0 @@
//------------------------------------------------------------
// DONOT MODIFY THIS FILE
// generated by JISHENGJU automatically
//------------------------------------------------------------
#ifndef AONSYS_RSTGEN_REG_OFFSET_DEFINE_H
#define AONSYS_RSTGEN_REG_OFFSET_DEFINE_H
#define AONSYS_RSTGEN_REG_BASE 0xFFFFF44000
#define REG_AON_RST_CNT (AONSYS_RSTGEN_REG_BASE + 0x0 )
#define REG_AON_SYS_RST_CFG (AONSYS_RSTGEN_REG_BASE + 0x10 )
#define REG_AON_RTC_RST_CFG (AONSYS_RSTGEN_REG_BASE + 0x14 )
#define REG_AON_AOGPIO_RST_CFG (AONSYS_RSTGEN_REG_BASE + 0x18 )
#define REG_AON_AOI2C_RST_CFG (AONSYS_RSTGEN_REG_BASE + 0x1c )
#define REG_AON_PVTC_RST_CFG (AONSYS_RSTGEN_REG_BASE + 0x20 )
#define REG_AON_E902_RST_CFG (AONSYS_RSTGEN_REG_BASE + 0x24 )
#define REG_AON_AOTIMER_RST_CFG (AONSYS_RSTGEN_REG_BASE + 0x28 )
#define REG_AON_AOWDT_RST_CFG (AONSYS_RSTGEN_REG_BASE + 0x2c )
#define REG_AON_APSYS_RST_CFG (AONSYS_RSTGEN_REG_BASE + 0x30 )
#define REG_AON_NPUSYS_RST_CFG (AONSYS_RSTGEN_REG_BASE + 0x34 )
#define REG_AON_DDRSYS_RST_CFG (AONSYS_RSTGEN_REG_BASE + 0x38 )
#define REG_AON_AUDIO_RST_CFG (AONSYS_RSTGEN_REG_BASE + 0x3c )
#define REG_AON_BISR_RST_CFG (AONSYS_RSTGEN_REG_BASE + 0x50 )
#define REG_AON_DSP0_RST_CFG (AONSYS_RSTGEN_REG_BASE + 0x54 )
#define REG_AON_DSP1_RST_CFG (AONSYS_RSTGEN_REG_BASE + 0x58 )
#define REG_AON_GPU_RST_CFG (AONSYS_RSTGEN_REG_BASE + 0x5c )
#define REG_AON_VDEC_RST_CFG (AONSYS_RSTGEN_REG_BASE + 0x60 )
#define REG_AON_VENC_RST_CFG (AONSYS_RSTGEN_REG_BASE + 0x64 )
#define REG_AON_ADC_RST_CFG (AONSYS_RSTGEN_REG_BASE + 0x70 )
#define REG_AON_AUDGPIO_RST_CFG (AONSYS_RSTGEN_REG_BASE + 0x74 )
#define REG_AON_AOUART_RST_CFG (AONSYS_RSTGEN_REG_BASE + 0x78 )
#define REG_AON_RST_CLR_0 (AONSYS_RSTGEN_REG_BASE + 0x100 )
#define REG_AON_RST_CLR_1 (AONSYS_RSTGEN_REG_BASE + 0x104 )
#define REG_AON_RST_CLR_2 (AONSYS_RSTGEN_REG_BASE + 0x108 )
#define REG_AON_RST_CLR_3 (AONSYS_RSTGEN_REG_BASE + 0x10c )
#define REG_AON_RST_CLR_4 (AONSYS_RSTGEN_REG_BASE + 0x110 )
#define REG_AON_RST_STS_0 (AONSYS_RSTGEN_REG_BASE + 0x120 )
#define REG_AON_RST_STS_1 (AONSYS_RSTGEN_REG_BASE + 0x124 )
#define REG_AON_RST_STS_2 (AONSYS_RSTGEN_REG_BASE + 0x128 )
#define REG_AON_RST_STS_3 (AONSYS_RSTGEN_REG_BASE + 0x12c )
#define REG_AON_RST_STS_4 (AONSYS_RSTGEN_REG_BASE + 0x130 )
#define REG_AON_RST_REQ_EN_0 (AONSYS_RSTGEN_REG_BASE + 0x140 )
#define REG_AON_RST_REQ_EN_1 (AONSYS_RSTGEN_REG_BASE + 0x144 )
#define REG_AON_RST_REQ_EN_2 (AONSYS_RSTGEN_REG_BASE + 0x148 )
#define REG_AON_RST_REQ_EN_3 (AONSYS_RSTGEN_REG_BASE + 0x14c )
#define REG_AON_SRAM_AXI_RST_CFG (AONSYS_RSTGEN_REG_BASE + 0x11f4)
#define REG_AON_SE_RST_CFG (AONSYS_RSTGEN_REG_BASE + 0x160 )
#define RST_CNT_DFLT_VAL 0xf0f
#define SYS_RST_CFG_DFLT_VAL 0x0
#define RTC_RST_CFG_DFLT_VAL 0x3
#define AOGPIO_RST_CFG_DFLT_VAL 0x3
#define AOI2C_RST_CFG_DFLT_VAL 0x1
#define PVTC_RST_CFG_DFLT_VAL 0x1
#define E902_RST_CFG_DFLT_VAL 0x2
#define AOTIMER_RST_CFG_DFLT_VAL 0x3
#define AOWDT_RST_CFG_DFLT_VAL 0x1
#define APSYS_RST_CFG_DFLT_VAL 0x1
#define NPUSYS_RST_CFG_DFLT_VAL 0x1
#define DDRSYS_RST_CFG_DFLT_VAL 0x1
#define AUDIO_RST_CFG_DFLT_VAL 0x0
#define BISR_RST_CFG_DFLT_VAL 0x3
#define DSP0_RST_CFG_DFLT_VAL 0x1
#define DSP1_RST_CFG_DFLT_VAL 0x1
#define GPU_RST_CFG_DFLT_VAL 0x1
#define VDEC_RST_GEN_RST_CFG_DFLT_VAL 0x1
#define VENC_RST_CFG_DFLT_VAL 0x1
#define ADC_RST_CFG_DFLT_VAL 0x1
#define AUDGPIO_RST_CFG_DFLT_VAL 0x3
#define AOUART_RST_CFG_DFLT_VAL 0x3
#define RST_CLR_0_DFLT_VAL 0x0
#define RST_CLR_1_DFLT_VAL 0x0
#define RST_CLR_2_DFLT_VAL 0x0
#define RST_CLR_3_DFLT_VAL 0x0
#define RST_CLR_4_DFLT_VAL 0x0
#define RST_STS_0_DFLT_VAL 0x0
#define RST_STS_1_DFLT_VAL 0x0
#define RST_STS_2_DFLT_VAL 0x0
#define RST_STS_3_DFLT_VAL 0x0
#define RST_STS_4_DFLT_VAL 0x0
#define RST_REQ_EN_0_DFLT_VAL 0x11100
#define RST_REQ_EN_1_DFLT_VAL 0xbb000000
#define RST_REQ_EN_2_DFLT_VAL 0x0
#define RST_REQ_EN_3_DFLT_VAL 0x0
#define SRAM_AXI_RST_CFG_DFLT_VAL 0x5f
#define SE_RST_CFG_DFLT_VAL 0x1
#endif

2
board/thead/light-c910/lpddr4/include/common_lib.h
View File

@@ -7,8 +7,6 @@
#include "ddr_reg_define.h"
#include "ddr_sysreg_registers_struct.h"
#include "ddr_sysreg_registers.h"
#include "aonsys_reg_define.h"
#include "aonsys_rstget_reg_define.h"
#include "define_ddr.h"
#include "DWC_ddr_umctl2_c_struct.h"
#include "DWC_ddr_umctl2_header.h"

7
board/thead/light-c910/lpddr4/include/ddr_common_func.h
View File

@@ -15,9 +15,6 @@ enum DDR_BITWIDTH {
unsigned long get_ddr_density(void);
enum DDR_TYPE get_ddr_type(void);
int get_ddr_rank_number(void);
int get_ddr_freq(void);
enum DDR_BITWIDTH get_ddr_bitwidth(void);
void ddr_sysreg_wr(unsigned long int addr,unsigned int wr_data);
unsigned int ddr_sysreg_rd(unsigned long int addr);
@@ -52,8 +49,4 @@ void addrmap(int rank_num, enum DDR_BITWIDTH bits);
void ctrl_en(enum DDR_BITWIDTH bits);
void enable_auto_refresh(void);
void lpddr4_auto_selref(void);
int lpddr4_query_boundary(enum DDR_TYPE type, int rank_num, int speed,
enum DDR_BITWIDTH bits, unsigned long size);
int lpddr4_reinit_ctrl(enum DDR_TYPE type, int rank_num, int speed,
enum DDR_BITWIDTH bits, unsigned long size);
#endif // DDR_COMMON_FUNCE_H

36
board/thead/light-c910/lpddr4/include/ddr_retention.h
View File

@@ -1,36 +0,0 @@
#ifndef DDR_RETENTION_H
#define DDR_RETENTION_H
///data structure to store ddr misc register address, value
typedef struct Reg_Misc_Addr_Val {
uint32_t Address; ///< register address
uint32_t Value; ///< register value
} Reg_Misc_Addr_Val_t;
///data structure to store register address, value pairs
typedef struct Reg_Phy_Addr_Val {
uint32_t Address; ///< register address
uint16_t Value0; ///< register value phy0
uint16_t Value1; ///< register value phy1
} Reg_Phy_Addr_Val_t;
/// enumeration of instructions for PhyInit Register Interface
typedef enum {
saveRegs, ///< save(read) tracked register values
restoreRegs, ///< restore (write) saved register values
} regInstr;
// typedef struct Reg_Addr_Value {
// uint32_t reg_num;
// Reg_Addr_Val_t reg[0];
// } Reg_Addr_Value_t;
typedef struct Ddr_Reg_Config {
uint32_t misc_reg_num;
uint32_t phy_reg_num;
} Ddr_Reg_Config_t;
int dwc_ddrphy_phyinit_regInterface(regInstr myRegInstr);
void dwc_ddr_misc_regu_save(void);
#endif

571
board/thead/light-c910/lpddr4/src/ddr_common_func.c
View File

@@ -2,14 +2,9 @@
#include <linux/sizes.h>
#include "../include/common_lib.h"
#include "../include/ddr_common_func.h"
#include "../include/ddr_retention.h"
DDR_SYSREG_REG_SW_REG_S ddr_sysreg;
#ifdef CONFIG_DDR_MSG
#define DDR_DEBUG(x) printf(x)
#endif
#ifndef CONFIG_DDR_RANK_SIZE
#define CONFIG_DDR_RANK_SIZE SZ_4G
#endif
@@ -39,44 +34,6 @@ enum DDR_TYPE get_ddr_type() {
#endif // #ifdef CONFIG_LPDDR4X
}
int get_ddr_rank_number() {
#ifdef CONFIG_DDR_SINGLE_RANK
return 1;
#elif defined CONFIG_DDR_DUAL_RANK
return 2;
#else
#ifdef CONFIG_DDR_MSG
DDR_DEBUG("unsupported ddr rank type!!!\n");
#endif
return NULL;
#endif
}
int get_ddr_freq() {
#ifdef CONFIG_DDR_4266
return 4266;
#elif CONFIG_DDR_3733
return 3733;
#elif CONFIG_DDR_3200
return 3200;
#elif CONFIG_DDR_2133
return 2133;
#else
printf("unsupport lpddr4 freq!!!\n");
return -1;
#endif
}
enum DDR_BITWIDTH get_ddr_bitwidth() {
#ifdef CONFIG_DDR_H32_MODE
return DDR_BITWIDTH_32;
#elif CONFIG_DDR_H16_MODE
return DDR_BITWIDTH_16;
#else
return DDR_BITWIDTH_64;
#endif
}
void ddr_sysreg_wr(unsigned long int addr,unsigned int wr_data) {
wr(addr+DDR_SYSREG_BADDR,wr_data);
}
@@ -147,114 +104,75 @@ unsigned int ddr_phy_reg_rd(unsigned long int addr) {
void lp4_mrw(int addr, int wdata,int dch,int rank) {
DWC_DDR_UMCTL2_C_STRUCT_REG_S umctl2_reg;
uint32_t val_t0,val_t1;
if(dch==0) {
while ((rd(MRSTAT) & 0x1) == 0x1);
umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32 = rd(MRCTRL0);
//umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_addr = addr; //do not care for lp4
umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_rank = rank;//rank0 only
umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_type = 0;//write
wr(MRCTRL0, umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32);
umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32 = rd(MRCTRL0);
//umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_addr = addr; //do not care for lp4
umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_rank = rank;//rank0 only
umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_type = 0;//write
wr(MRCTRL0,umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32);
umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32 = rd(MRCTRL1);
umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.mr_data = (addr << 8) | (wdata & 0xFF);
wr(MRCTRL1, umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32);
umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32 = rd(MRCTRL1);
umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.mr_data = (addr << 8) | (wdata & 0xFF);
wr(MRCTRL1, umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32);
umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32 = rd(MRCTRL0);
umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_wr = 1;//trigger wr/rd
wr(MRCTRL0, umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32);
//udelay(10);
//delay 5us
val_t0=rd(0xFFF4D004);
val_t1=rd(0xFFF4D004);
while((val_t0-val_t1)<200){val_t1=rd(0xFFF4D004);};
while ((rd(MRSTAT) & 0x1) == 0x1);
umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32 = rd(MRCTRL1);
umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.mr_data = (addr<<8) | (wdata&0xFF);
wr(MRCTRL1,umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32);
umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32 = rd(MRCTRL0);
umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_wr = 1;//trigger wr/rd
wr(MRCTRL0,umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32);
}
else {
while ((rd(MRSTAT_DCH1) & 0x1) == 0x1);
umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32 = rd(MRCTRL0_DCH1);
//umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_addr = addr; //do not care for lp4
umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_rank = rank;//rank0 only
umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_type = 0;//write
wr(MRCTRL0_DCH1, umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32);
umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32 = rd(MRCTRL0_DCH1);
//umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_addr = addr; //do not care for lp4
umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_rank = rank;//rank0 only
umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_type = 0;//write
wr(MRCTRL0_DCH1,umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32);
umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32 = rd(MRCTRL1_DCH1);
umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.mr_data = (addr << 8) | (wdata & 0xFF);
wr(MRCTRL1_DCH1, umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32);
umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32 = rd(MRCTRL1_DCH1);
umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.mr_data = (addr << 8) | (wdata & 0xFF);
wr(MRCTRL1_DCH1, umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32);
umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32 = rd(MRCTRL0_DCH1);
umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_wr = 1;//trigger wr/rd
wr(MRCTRL0_DCH1, umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32);
//udelay(10);
//delay 5us
val_t0=rd(0xFFF4D004);
val_t1=rd(0xFFF4D004);
while((val_t0-val_t1)<200){val_t1=rd(0xFFF4D004);};
while ((rd(MRSTAT_DCH1) & 0x1) == 0x1);
umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32 = rd(MRCTRL1_DCH1);
umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.mr_data = (addr<<8) | (wdata&0xFF);
wr(MRCTRL1_DCH1,umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32);
umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32 = rd(MRCTRL0_DCH1);
umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_wr = 1;//trigger wr/rd
wr(MRCTRL0_DCH1,umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32);
}
}
}
int lp4_mrr(int addr,int dch,int rank) {
DWC_DDR_UMCTL2_C_STRUCT_REG_S umctl2_reg;
if(dch==0) {
umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32 = rd(MRCTRL0);
//umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_addr = addr; //do not care for lp4
umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_rank = rank;//rank0 only
umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_type = 1;//read
wr(MRCTRL0, umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32);
umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32 = rd(MRCTRL0);
//umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_addr = addr; //do not care for lp4
umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_rank = rank;//rank0 only
umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_type = 1;//read
wr(MRCTRL0,umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32);
umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32 = rd(MRCTRL1);
umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.mr_data = addr << 8;
wr(MRCTRL1, umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32);
umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32 = rd(MRCTRL1);
umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.mr_data = addr<<8;
wr(MRCTRL1,umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32);
umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32 = rd(MRCTRL0);
umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_wr = 1;//trigger wr/rd
wr(MRCTRL0,umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32);
umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32 = rd(MRCTRL1);
umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.mr_data = addr << 8;
wr(MRCTRL1, umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32);
umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32 = rd(MRCTRL0);
umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_wr = 1;//trigger wr/rd
wr(MRCTRL0, umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32);
udelay(20);
while ((rd(MRSTAT) & 0x1) == 0x1);
return ddr_sysreg_rd(MRR_STS_CH0);
umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32 = rd(MRCTRL1);
return (umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.mr_data & 0xFF);
}
else {
umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32 = rd(MRCTRL0_DCH1);
//umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_addr = addr; //do not care for lp4
umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_rank = rank;//rank0 only
umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_type = 1;//read
wr(MRCTRL0_DCH1, umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32);
umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32 = rd(MRCTRL0_DCH1);
//umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_addr = addr; //do not care for lp4
umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_rank = rank;//rank0 only
umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_type = 1;//read
wr(MRCTRL0_DCH1,umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32);
umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32 = rd(MRCTRL1_DCH1);
umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.mr_data = addr << 8;
wr(MRCTRL1_DCH1, umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32);
umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32 = rd(MRCTRL1_DCH1);
umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.mr_data = addr<<8;
wr(MRCTRL1_DCH1,umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32);
umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32 = rd(MRCTRL0_DCH1);
umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_wr = 1;//trigger wr/rd
wr(MRCTRL0_DCH1,umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32);
umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32 = rd(MRCTRL1_DCH1);
umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.mr_data = addr << 8;
wr(MRCTRL1_DCH1, umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32);
umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32 = rd(MRCTRL0_DCH1);
umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_wr = 1;//trigger wr/rd
wr(MRCTRL0_DCH1, umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32);
udelay(20);
while ((rd(MRSTAT_DCH1) & 0x1) == 0x1);
return ddr_sysreg_rd(MRR_STS_CH1);
umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32 = rd(MRCTRL1_DCH1);
return (umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.mr_data & 0xFF);
}
}
@@ -318,15 +236,15 @@ unsigned int ddr_phy_reg_rd(unsigned long int addr) {
if(port & 0x4) wr(PCTRL_2,0);
if(port & 0x8) wr(PCTRL_3,0);
if(port & 0x10) wr(PCTRL_4,0);
while (rd(PSTAT) != 0x0);
if ((port & 0x1F) == 0x1F) { //all ports are disabled
wr(DBG1, 2);
wr(DBG1_DCH1, 2);
if(port & 0x1F) { //at least one port is not disabled
wr(DBG1,0);
wr(DBG1_DCH1,0);
}
else { //at least one port is not disabled
wr(DBG1, 0);
wr(DBG1_DCH1, 0);
else { //all ports are disabled
wr(DBG1,3);
wr(DBG1_DCH1,3);
}
}
void enable_axi_port(int port) {
@@ -539,7 +457,7 @@ if(bits==64) {
wr(DFITMG0,0x05a3820e);//[28:24] dft_t_ctrl_delay [22:16] dfi_t_rddate_en=RL-5
#endif
wr(DFITMG1,0x000c0303);
wr(DFILPCFG0,0x0351a101); //[8]=1: enable dfi lp mode during selfref
wr(DFILPCFG0,0x0351a001);
//wr(DFIUPD0,0x00400018); //[31:30]=0 use ctrlupd enable
//wr(DFIUPD1,0x00b700c4);
//wr(DFIUPD2,0x00000000);//[31]=0 disable phy ctrlupdate
@@ -639,7 +557,7 @@ if(bits==64) {
wr(DFITMG0,0x059f820c);//[28:24] dfi_t_ctrl_delay
#endif
wr(DFITMG1,0x000c0303);//dfi_t_wrdata_delay=tctrl+6+BL/2+trainedTdqsdly=24, may need take care cmd pipe
wr(DFILPCFG0,0x0351a101); //[8]=1: enable dfi lp mode during selfref
wr(DFILPCFG0,0x0351a001);
//wr(DFIUPD0,0xc0400018);
//wr(DFIUPD1,0x00b700c4);
//wr(DFIUPD2,0x80000000);
@@ -727,7 +645,7 @@ if(bits==64) {
wr(DFITMG0,0x059b820a); //[22:16] dfi_t_rddate_en=RL-5
#endif
wr(DFITMG1,0x000b0303);
wr(DFILPCFG0,0x0351a101); //[8]=1: enable dfi lp mode during selfref
wr(DFILPCFG0,0x0351a001);
//wr(DFIUPD0,0xc0400018);
//wr(DFIUPD1,0x00b700c4);
//wr(DFIUPD2,0x80000000);
@@ -812,7 +730,7 @@ if(bits==64) {
wr(ZQCTL2,0x00000000);
wr(DFITMG0,0x048f8206);
wr(DFITMG1,0x000b0303);
wr(DFILPCFG0,0x0351a101); //[8]=1: enable dfi lp mode during selfref
wr(DFILPCFG0,0x0351a001);
//wr(DFIUPD0,0xc0400018);
//wr(DFIUPD1,0x00b700c4);
//wr(DFIUPD2,0x80000000);
@@ -938,28 +856,17 @@ if(bits==64) {
#ifdef CONFIG_DDR_MSG
printf("DDR 32bit mode\n");
#endif
wr(ADDRMAP0,0x001f001f); //
if(rank_num==2) {
#ifdef CONFIG_DDR_DDP
wr(ADDRMAP0,0x001f0018);//max 8GB
#else
wr(ADDRMAP0,0x001f0017); //4GB
#endif
}
else {
wr(ADDRMAP0,0x001f001f); //cs_bit0: NULL
wr(ADDRMAP0,0x001f0017);//4GB
}
wr(ADDRMAP1,0x00080808); //bank +2
wr(ADDRMAP2,0x00000000); //col b5+5 ~ col b2 +2
wr(ADDRMAP3,0x00000000); //col b9 ~ col b6
wr(ADDRMAP4,0x00001f1f); //col b11~ col b10
wr(ADDRMAP5,0x070f0707); //row_b11 row b2_10 row b1 row b0 +6
wr(ADDRMAP6,0x07070707); //row 15
wr(ADDRMAP7,0x00000f0f); //row16: NULL
#ifdef CONFIG_DDR_DDP
if(rank_num==2) {
wr(ADDRMAP7,0x00000f07); //max row16
}
#endif
wr(ADDRMAP6,0x07070707); //max row 15
wr(ADDRMAP7,0x00000f0f);
wr(ADDRMAP9,0x07070707);
wr(ADDRMAP10,0x07070707);
wr(ADDRMAP11,0x00000007);
@@ -967,12 +874,12 @@ if(bits==64) {
#ifdef CONFIG_DDR_MSG
printf("DDR 64bit mode, 256B interleaving\n");
#endif
wr(ADDRMAP0,0x0004001f); //cs_bit0: NULL
wr(ADDRMAP0,0x0004001f); // +2
if(rank_num==2) {
#ifdef CONFIG_DDR_DDP
wr(ADDRMAP0,0x00040019);//max 16GB
wr(ADDRMAP0,0x00040019);//16GB
#else
wr(ADDRMAP0,0x00040018);//8GB
wr(ADDRMAP0,0x00040018);//8GB
#endif
}
wr(ADDRMAP1,0x00090909); //bank +2
@@ -980,11 +887,11 @@ if(bits==64) {
wr(ADDRMAP3,0x01010101); //col b9 ~ col b6
wr(ADDRMAP4,0x00001f1f); //col b11~ col b10
wr(ADDRMAP5,0x080f0808); //row_b11 row b2_10 row b1 row b0 +6
wr(ADDRMAP6,0x08080808); //row15
wr(ADDRMAP6,0x08080808);
#ifdef CONFIG_DDR_DDP
wr(ADDRMAP7,0x00000f08); //row16
wr(ADDRMAP7,0x00000f08);
#else
wr(ADDRMAP7,0x00000f0f); //row16: NULL
wr(ADDRMAP7,0x00000f0f);
#endif
wr(ADDRMAP9,0x08080808);
wr(ADDRMAP10,0x08080808);
@@ -994,130 +901,6 @@ if(bits==64) {
}
}
#define MEMSIZE_MIN_MB (2*1024)
#define MEMSIZE_MAX_MB (16*1024)
#define UNIT_MB (1024*1024)
int lpddr4_query_boundary(enum DDR_TYPE type, int rank_num, int speed,
enum DDR_BITWIDTH bits, unsigned long size)
{
if ((size < (unsigned long)MEMSIZE_MIN_MB*UNIT_MB) ||
(size > (unsigned long)MEMSIZE_MAX_MB*UNIT_MB))
goto err_ret;
if (bits == DDR_BITWIDTH_32) {// only phy0
if (rank_num == 2) {
if (size == 0x80000000) //2GB
goto err_ret;
else if (size == 0x100000000) //4GB
goto ret_ok;
else if (size == 0x200000000) //8GB
goto ret_ok;
else if (size == 0x400000000) //16GB
goto err_ret;
else
goto err_ret;
}
else { // single rank
if (size == 0x80000000) //2GB
goto ret_ok;
else if (size == 0x100000000) //4GB
goto err_ret;
else if (size == 0x200000000) //8GB
goto err_ret;
else if (size == 0x400000000) //16GB
goto err_ret;
else
goto err_ret;
}
}
else if (bits == DDR_BITWIDTH_64) { // phy0+phy1
if (rank_num == 2) {
if (size == 0x80000000) //2GB
goto err_ret;
else if (size == 0x100000000) //4GB
goto err_ret;
else if (size == 0x200000000) //8GB
goto ret_ok;
else if (size == 0x400000000) //16GB
goto ret_ok;
else
goto err_ret;
}
else { // single rank
if (size == 0x80000000) //2GB
goto err_ret;
else if (size == 0x100000000) //4GB
goto ret_ok;
else if (size == 0x200000000) //8GB
goto err_ret;
else if (size == 0x400000000) //16GB
goto err_ret;
else
goto err_ret;
}
}
else {
goto err_ret;
}
ret_ok:
return 0;
err_ret:
return -1;
}
int adjust_ddr_addrmap(enum DDR_TYPE type, int rank_num, int speed,
enum DDR_BITWIDTH bits, unsigned long size)
{
if (lpddr4_query_boundary(type, rank_num, speed, bits, size) < 0)
goto err_ret;
if (bits == DDR_BITWIDTH_32) {// only phy0
if (rank_num == 2) {
if (size == 0x100000000) {//4GB
wr(ADDRMAP0,0x001f0017); // cs_bit0: HIF[29]
wr(ADDRMAP7,0x00000f0f); // row16: NULL
}
else if (size == 0x200000000) {//8GB
wr(ADDRMAP0,0x001f0018); // cs_bit0: HIF[30]
wr(ADDRMAP7,0x00000f07); // row16: HIF[29]
}
}
else { // single rank
if (size == 0x80000000) //2GB
wr(ADDRMAP0,0x001f001f); // cs_bit0: NULL
}
}
else if (bits == DDR_BITWIDTH_64) { // phy0+phy1
if (rank_num == 2) {
if (size == 0x200000000) {//8GB
wr(ADDRMAP0,0x00040018); // cs_bit0: HIF[30]
wr(ADDRMAP7,0x00000f0f); // row16: NULL
}
else if (size == 0x400000000) {//16GB
wr(ADDRMAP0,0x00040019); // cs_bit0: HIF[31]
wr(ADDRMAP7,0x00000f08); // row16: HIF[30]
}
}
else { // single rank
if (size == 0x100000000) {//4GB
wr(ADDRMAP0,0x0004001f); // cs_bit0: NULL
wr(ADDRMAP7,0x00000f0f); // row16: NULL
}
}
}
else {
// nothing
}
return 0;
err_ret:
printf("unsupport memsize %ld\n", size);
return -1;
}
void quasi_reg_write(unsigned long int reg,int wdata) {
DWC_DDR_UMCTL2_C_STRUCT_REG_S umctl2_reg;
@@ -1232,11 +1015,11 @@ void lpddr4_enter_selfrefresh(int pwdn_en,int dis_dram_clk,int mode) {
umctl2_reg.dwc_ddr_umctl2_c_struct_stat.u32 = rd(STAT_DCH1);
if(pwdn_en) {
while( umctl2_reg.dwc_ddr_umctl2_c_struct_stat.selfref_state != 2) //wait sdram enter selfrefresh-powerdown state
umctl2_reg.dwc_ddr_umctl2_c_struct_stat.u32 = rd(STAT_DCH1);
umctl2_reg.dwc_ddr_umctl2_c_struct_stat.u32 = rd(STAT);
}
else {
while( umctl2_reg.dwc_ddr_umctl2_c_struct_stat.selfref_state != 1) //wait sdram enter selfrefresh state
umctl2_reg.dwc_ddr_umctl2_c_struct_stat.u32 = rd(STAT_DCH1);
umctl2_reg.dwc_ddr_umctl2_c_struct_stat.u32 = rd(STAT);
}
#ifdef CONFIG_DDR_MSG
printf("[lpddr4_enter_selfrefresh]: CH1 STAT is :%x after enter selfrefresh state\n",umctl2_reg.dwc_ddr_umctl2_c_struct_stat.u32);
@@ -1272,8 +1055,7 @@ void lpddr4_auto_ps_en(int pwdn_en,int selfref_en,int clock_auto_disable ) {
//ddr_sysreg_wr(DDR_CFG0,0x1ff0);
//ddr_sysreg_wr(DDR_CFG0,0x1ff0);
ddr_sysreg.ddr_sysreg_registers_struct_ddr_cfg0.u32 = ddr_sysreg_rd(DDR_CFG0);
//ddr_sysreg.ddr_sysreg_registers_struct_ddr_cfg0.rg_ctl_ddr_usw_rst_reg |= 0x1F2;
ddr_sysreg.ddr_sysreg_registers_struct_ddr_cfg0.rg_ctl_ddr_usw_rst_reg |= 0x1FA;
ddr_sysreg.ddr_sysreg_registers_struct_ddr_cfg0.rg_ctl_ddr_usw_rst_reg |= 0x1F2;
ddr_sysreg_wr(DDR_CFG0,ddr_sysreg.ddr_sysreg_registers_struct_ddr_cfg0.u32);
}
@@ -1293,7 +1075,7 @@ void dfi_freq_change(int dfi_freq,int skip_dram_init) {
#ifdef CONFIG_DDR_MSG
printf("[dfi_freq_change]: start dfi_freq_change, target dfi_freq is %x \n",dfi_freq);
#endif
//wr(DBG1,3);
wr(DBG1,3);
umctl2_reg.dwc_ddr_umctl2_c_struct_swctl.u32 = rd(SWCTL);
umctl2_reg.dwc_ddr_umctl2_c_struct_swctl.sw_done = 0;
wr(SWCTL,umctl2_reg.dwc_ddr_umctl2_c_struct_swctl.u32);
@@ -1304,6 +1086,7 @@ void dfi_freq_change(int dfi_freq,int skip_dram_init) {
umctl2_reg.dwc_ddr_umctl2_c_struct_dfimisc.u32 = rd(DFIMISC);
umctl2_reg.dwc_ddr_umctl2_c_struct_dfimisc.dfi_frequency = dfi_freq;
umctl2_reg.dwc_ddr_umctl2_c_struct_dfimisc.dfi_init_start = 0x1;
umctl2_reg.dwc_ddr_umctl2_c_struct_dfimisc.dfi_init_complete_en = 0;
wr(DFIMISC,umctl2_reg.dwc_ddr_umctl2_c_struct_dfimisc.u32);
@@ -1314,28 +1097,15 @@ void dfi_freq_change(int dfi_freq,int skip_dram_init) {
while( umctl2_reg.dwc_ddr_umctl2_c_struct_swstat.sw_done_ack == 0)
umctl2_reg.dwc_ddr_umctl2_c_struct_swctl.u32 = rd(SWSTAT);
wr(SWCTL,0x0);
umctl2_reg.dwc_ddr_umctl2_c_struct_dfimisc.u32 = rd(DFIMISC);
umctl2_reg.dwc_ddr_umctl2_c_struct_dfimisc.dfi_init_start = 0x1;
wr(DFIMISC,umctl2_reg.dwc_ddr_umctl2_c_struct_dfimisc.u32);
wr(SWCTL,0x1);
while(rd(SWSTAT)!=0x00000001);
rdata = rd(DFISTAT);
while ((rdata & 0x1) != 0) //wait dfi_init_complete = 0
rdata = rd(DFISTAT);
#ifndef CONFIG_DDR_H32_MODE
rdata = rd(DCH1_DFISTAT);
while((rdata & 0x1) != 0) //wait dfi_init_complete = 0
rdata = rd(DCH1_DFISTAT);
#endif
rdata = rd(DFISTAT);
//change dfi clk freq here
//pull down dfi_init_start
umctl2_reg.dwc_ddr_umctl2_c_struct_swctl.u32 = rd(SWCTL);
umctl2_reg.dwc_ddr_umctl2_c_struct_swctl.sw_done = 0;
wr(SWCTL, umctl2_reg.dwc_ddr_umctl2_c_struct_swctl.u32);
wr(SWCTL,umctl2_reg.dwc_ddr_umctl2_c_struct_swctl.u32);
umctl2_reg.dwc_ddr_umctl2_c_struct_dfimisc.u32 = rd(DFIMISC);
umctl2_reg.dwc_ddr_umctl2_c_struct_dfimisc.dfi_init_start = 0;
wr(DFIMISC,umctl2_reg.dwc_ddr_umctl2_c_struct_dfimisc.u32);
@@ -1349,17 +1119,9 @@ void dfi_freq_change(int dfi_freq,int skip_dram_init) {
umctl2_reg.dwc_ddr_umctl2_c_struct_dfistat.u32 = rd(DFISTAT);
while(umctl2_reg.dwc_ddr_umctl2_c_struct_dfistat.dfi_init_complete == 0)
umctl2_reg.dwc_ddr_umctl2_c_struct_dfistat.u32 = rd(DFISTAT);
//wait dfi_init_complete = 1
#ifndef CONFIG_DDR_H32_MODE
umctl2_reg.dwc_ddr_umctl2_c_struct_dfistat.u32 = rd(DCH1_DFISTAT);
while(umctl2_reg.dwc_ddr_umctl2_c_struct_dfistat.dfi_init_complete == 0)
umctl2_reg.dwc_ddr_umctl2_c_struct_dfistat.u32 = rd(DCH1_DFISTAT);
#endif
//wr(DBG1,0);
wr(DBG1,0);
#ifdef CONFIG_DDR_MSG
printf("[dfi_freq_change]: dfi_freq_change, end \n");
printf("[dfi_freq_change]: dfi_freq_change, end \n",dfi_freq);
#endif
}
@@ -1384,168 +1146,3 @@ void lpddr4_auto_selref(void)
wr(PWRCTL,0x0000000b); //[3] dfi_dram_clk_disable [1] powerdown_en [0]serref_en
wr(DCH1_PWRCTL,0x0000000b);
}
void ctrl_en_lp3_exit(enum DDR_BITWIDTH bits) {
//skip DRAM init, because this has done
wr(SWCTL,0x00000000);
wr(INIT0,0xc0020002);
wr(SWCTL,0x00000001);
while(rd(SWSTAT)!=0x00000001);
//dfi frequency change proto ,to PS0
wr(SWCTL,0x00000000);
wr(DFIMISC,0x00000000);// [5]dfi_freq=0x0
wr(SWCTL,0x00000001);
while(rd(SWSTAT)!=0x00000001);
wr(SWCTL,0x00000000);
wr(DFIMISC,0x00000020);// [5]dfi_init_start=0x1
wr(SWCTL,0x00000001);
while(rd(SWSTAT)!=0x00000001);
while(rd(DFISTAT)!=0x00000001); //polling dfi_init_complete
if(bits==64) {
while(rd(DCH1_DFISTAT)!=0x00000001);
}
wr(SWCTL,0x00000000);
wr(DFIMISC,0x00000000);
wr(SWCTL,0x00000001);
while(rd(SWSTAT)!=0x00000001);
wr(SWCTL,0x00000000);
wr(DFIMISC,0x00000001);
wr(SWCTL,0x00000001);
while(rd(SWSTAT)!=0x00000001);
//for low power,
wr(SWCTL,0x00000000);
wr(PWRCTL,0x0000000a); //[3] dfi_dram_clk_disable [1] powerdown_en
wr(DCH1_PWRCTL,0x0000000a);
wr(SWCTL,0x00000001);
while (rd(SWSTAT) != 0x00000001);
//detect until umctrl into normal state
while (rd(STAT) != 0x00000001);
if(bits==64) {
while(rd(DCH1_STAT) != 0x00000001);
}
//en phy master proto
wr(DFIPHYMSTR,0x14000001);
#ifdef CONFIG_DDR_MSG
DDR_DEBUG("DFIPHYMSTR is %0x \n", rd(DFIPHYMSTR));
DDR_DEBUG("DFIUPD0 is %0x \n", rd(DFIUPD0));
DDR_DEBUG("DFIUPD1 is %0x \n", rd(DFIUPD1));
DDR_DEBUG("ZQCTL0 is %0x \n", rd(ZQCTL0));
DDR_DEBUG("ADDRMAP0 is %0x \n", rd(ADDRMAP0));
DDR_DEBUG("ADDRMAP1 is %0x \n", rd(ADDRMAP1));
#endif
}
int lpddr4_reinit_ctrl(enum DDR_TYPE type, int rank_num, int speed,
enum DDR_BITWIDTH bits, unsigned long size)
{
int ret;
unsigned int rdata;
//a.
ddr_sysreg_wr(DDR_CFG1, 0xa000011f); //remove core clock after xx
wr(PWRCTL, 0x00000000); //[3] dfi_dram_clk_disable [1] powerdown_en [0]serref_en
wr(DCH1_PWRCTL, 0x00000000);
// use phy value stored in spl
//dwc_ddrphy_phyinit_regInterface(saveRegs);
//b.dis axi port
disable_axi_port(0x1f);
while (rd(PSTAT) != 0x0);
#ifdef CONFIG_DDR_MSG
DDR_DEBUG("Axi prot idle\n");
#endif
wr(DFIPHYMSTR, 0x14000000);
//check status.
while ((rd(STAT) & 0x3) == 0x03);
#ifndef CONFIG_DDR_H32_MODE
while ((rd(STAT_DCH1) & 0x3) == 0x03);
#endif
//c.poll cam empty flag
while ((rd(DBGCAM) & 0x36000000) != 0x36000000);
//d.save phy regs
//e.SRE
lpddr4_enter_selfrefresh(1, 0, 0);
//f.LP3 enter
dfi_freq_change(0x1f, 0x3);
//g.PwrOk disassert
rdata = ddr_sysreg_rd(DDR_CFG0);
rdata &= ~(0x1 << 6);
ddr_sysreg_wr(DDR_CFG0, rdata); //Pwrokin dessert
//p.phy reset
rdata = ddr_sysreg_rd(DDR_CFG0);
rdata &= ~(0x1 << 7);
rdata &= 0x0;
ddr_sysreg_wr(DDR_CFG0, rdata); //Phy reset .DDR_CFG0 ALL reset
//r.ddr core reset
rdata = ddr_sysreg_rd(DDR_CFG0);
rdata &= ~(0x1 << 5);
ddr_sysreg_wr(DDR_CFG0, rdata); //ctrl sw reset
//s.pwr ok assert
rdata = ddr_sysreg_rd(DDR_CFG0);
rdata |= (0x1 << 6);
ddr_sysreg_wr(DDR_CFG0, rdata); //Pwrokin dessert
//t.ctrl init
//dwc_umctl_init_skip_traing(type, rank_num, speed, bits);
ddr_sysreg_wr(DDR_CFG0, 0x50); // release apb presetn
ddr_sysreg_wr(DDR_CFG0, 0x50);
ddr_sysreg_wr(DDR_CFG0, 0x50);
if (bits == 32) {
ddr_sysreg_wr(DDR_CFG0, 0x52);
}
ctrl_init(rank_num, speed);
addrmap(rank_num, bits);
ret = adjust_ddr_addrmap(type, rank_num, speed, bits, size);
// msic regu restore for str
dwc_ddr_misc_regu_save();
de_assert_other_reset_ddr(); //after this step, only PwrOk is staill low
dq_pinmux(bits);
//u.phy restor
dwc_ddrphy_phyinit_regInterface(restoreRegs);
//v.ctrl en ,hs
ctrl_en_lp3_exit(bits);
//w.SRE
lpddr4_selfrefresh_exit(0);
//y.en auto refresh
enable_auto_refresh();
//x.en axi port
enable_axi_port(0x1f);
wr(DFIPHYMSTR, 0x14000001);
lpddr4_auto_selref();
if(rd(PSTAT))
{
#ifdef CONFIG_DDR_MSG
DDR_DEBUG("***** DDR busy in LP3 Mode *****\n");
#endif
}else{
#ifdef CONFIG_DDR_MSG
DDR_DEBUG("***** AXI port idle *****\n");
#endif
}
return ret;
}

1075
board/thead/light-c910/lpddr4/src/ddr_retention.c
View File

File diff suppressed because it is too large Load Diff

996
board/thead/light-c910/lpddr4/src/lpddr4_init.c
View File

File diff suppressed because it is too large Load Diff

131
board/thead/light-c910/spl.c
View File

@@ -26,11 +26,6 @@
DECLARE_GLOBAL_DATA_PTR;
extern void init_ddr(void);
#ifdef CONFIG_FIXUP_MEMORY_REGION
extern int fixup_ddr_addrmap(unsigned long size);
extern int query_ddr_boundary(unsigned long size);
#endif
extern unsigned long get_ddr_density(void);
extern void cpu_clk_config(int cpu_freq);
extern void sys_clk_config(void);
extern void ddr_clk_config(int ddr_freq);
@@ -98,25 +93,6 @@ void setup_ddr_pmp(void)
sync_is();
}
void clear_ddr_pmp(void)
{
/* restore pmp entry0,entry1 setting in bootrom */
writel(0x0400000000 >> 12, (void *)(PMP_BASE_ADDR + 0x104));
writel(0x0 >> 12, (void *)(PMP_BASE_ADDR + 0x100));
writel(0xffe1000000 >> 12, (void *)(PMP_BASE_ADDR + 0x10c));
writel(0xffe0180000 >> 12, (void *)(PMP_BASE_ADDR + 0x108));
writel(0x4040, (void *)(PMP_BASE_ADDR + 0x000));
sync_is();
}
static inline void _l2cache_ciall(void)
{
asm volatile (".long 0x0170000b");
}
int get_rng(unsigned int *rng, int cnt)
{
int i;
@@ -321,100 +297,6 @@ void setup_ddr_parity(void)
}
}
#ifdef CONFIG_FIXUP_MEMORY_REGION
#define MAGIC_DATA (0xF4240)
#define MAGIC_DATA2 (0x5AA5)
#define MAGIC_DATA3 (0x3C3C)
#define MAGIC_DATA4 (0xF0F0)
/*
return: 0: found boundary;
*/
int boundary_verify(unsigned long boundary) {
phys_addr_t verify_addr = (phys_addr_t)CONFIG_SYS_SDRAM_BASE;
phys_addr_t verify_addr2 = ((phys_addr_t)boundary + CONFIG_SYS_SDRAM_BASE)/4;
phys_addr_t verify_addr3 = ((phys_addr_t)boundary + CONFIG_SYS_SDRAM_BASE)/2;
phys_addr_t verify_addr4 = (phys_addr_t)boundary + CONFIG_SYS_SDRAM_BASE;
// verify data accessing result firstly
writel(MAGIC_DATA2, verify_addr);
invalidate_dcache_range(verify_addr, verify_addr + CONFIG_SYS_CACHELINE_SIZE);
if (readl(verify_addr) != MAGIC_DATA2) {
printf("ddr rw test failed\n");
return -1;
}
writel(MAGIC_DATA, verify_addr); // writing at beginning
invalidate_dcache_range(verify_addr, verify_addr + CONFIG_SYS_CACHELINE_SIZE);
if (readl(verify_addr) != MAGIC_DATA) {
printf("ddr rw test failed\n");
return -1;
}
writel(MAGIC_DATA2, verify_addr2); // writing at one-quarter addr
writel(MAGIC_DATA3, verify_addr3); // writing at half addr
invalidate_dcache_range(verify_addr, verify_addr + CONFIG_SYS_CACHELINE_SIZE);
invalidate_dcache_range(verify_addr2, verify_addr2 + CONFIG_SYS_CACHELINE_SIZE);
invalidate_dcache_range(verify_addr3, verify_addr3 + CONFIG_SYS_CACHELINE_SIZE);
if (boundary == (unsigned long)MAXIMAL_DDR_DENSITY_MB * UNIT_MB) { // boundary by design
if ((readl(verify_addr) == MAGIC_DATA) &&
(readl(verify_addr2) == MAGIC_DATA2) &&
(readl(verify_addr3) == MAGIC_DATA3))
return 0;
}
else {
writel(MAGIC_DATA4, verify_addr4); // writing out of boundary
invalidate_dcache_range(verify_addr4, verify_addr4 + CONFIG_SYS_CACHELINE_SIZE);
if ((readl(verify_addr) == MAGIC_DATA4) && // overwrite by verify_addr4
(readl(verify_addr2) == MAGIC_DATA2) &&
(readl(verify_addr3) == MAGIC_DATA3) &&
(readl(verify_addr4) == MAGIC_DATA4))
return 0;
}
return -1;
}
int setup_ddr_addrmap(void)
{
unsigned long boundary = (unsigned long)MAXIMAL_DDR_DENSITY_MB * UNIT_MB;
// verify data accessing result firstly
writel(MAGIC_DATA, (phys_addr_t)CONFIG_SYS_SDRAM_BASE);
invalidate_dcache_range(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_CACHELINE_SIZE);
if (readl((phys_addr_t)CONFIG_SYS_SDRAM_BASE) != MAGIC_DATA) {
printf("ddr rw test failed\n");
goto addrmap_err;
}
writel(MAGIC_DATA2, (phys_addr_t)CONFIG_SYS_SDRAM_BASE);
invalidate_dcache_range(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_CACHELINE_SIZE);
if (readl((phys_addr_t)CONFIG_SYS_SDRAM_BASE) != MAGIC_DATA2) {
printf("ddr rw test failed\n");
goto addrmap_err;
}
// try to find memory boundary
while (boundary >= (unsigned long)MINIMAL_DDR_DENSITY_MB * UNIT_MB) {
if (query_ddr_boundary(boundary) == 0) {
clear_ddr_pmp();
fixup_ddr_addrmap(boundary);
setup_ddr_pmp();
if (boundary_verify(boundary) == 0) {
gd->ram_size = boundary;
printf("found ddr boundary <0x%lx>\n", boundary);
return 0;
}
}
boundary = boundary >> 1;
}
gd->ram_size = get_ddr_density();
addrmap_err:
printf("failed to setup ddr addrmap\n");
return -1;
}
#endif
void cpu_performance_enable(void)
{
#define CSR_MHINT2_E 0x7cc
@@ -426,8 +308,8 @@ void cpu_performance_enable(void)
csr_write(CSR_MCCR2, 0xe2490009);
// FIXME: Clear bit[12] to disable L0BTB.
csr_write(CSR_MHCR, 0x17f); // clear bit7 to disable indirect brantch prediction
csr_write(CSR_MXSTATUS, 0x638000);
csr_write(CSR_MHINT, 0x6e30c | (1<<21) | (1<<22)); // set bit21 & bit 22 to close tlb & fence broadcast
mdelay(50); // workaround
}
static int bl1_img_have_head(unsigned long img_src_addr)
@@ -489,9 +371,9 @@ void board_init_f(ulong dummy)
preloader_console_init();
#ifdef CONFIG_PMIC_VOL_INIT
ret = aon_local_init();
ret = pmic_ddr_regu_init();
if (ret) {
printf("%s aon local init failed %d \n",__func__,ret);
printf("%s pmic init failed %d \n",__func__,ret);
hang();
}
@@ -506,6 +388,7 @@ void board_init_f(ulong dummy)
printf("%s set apcpu voltage failed \n",__func__);
hang();
}
#endif
ddr_clk_config(0);
cpu_clk_config(0);
@@ -514,12 +397,6 @@ void board_init_f(ulong dummy)
setup_ddr_scramble();
setup_ddr_parity();
setup_ddr_pmp();
#ifdef CONFIG_FIXUP_MEMORY_REGION
setup_ddr_addrmap();
#else
// update ram_size from board config
gd->ram_size = get_ddr_density();
#endif
printf("ddr initialized, jump to uboot\n");
light_board_init_r(NULL, 0);

12
cmd/Kconfig
View File

@@ -375,18 +375,6 @@ config CMD_FDT
help
Do FDT related setup before booting into the Operating System.
config SUPPORT_EXTENSION_SCAN
bool
config CMD_EXTENSION
bool "Extension board management command"
select CMD_FDT
depends on SUPPORT_EXTENSION_SCAN
help
Enables the "extension" command, which allows to detect
extension boards connected to the system, and apply
corresponding Device Tree overlays.
config CMD_GO
bool "go"
default y

1
cmd/Makefile
View File

@@ -48,7 +48,6 @@ ifdef CONFIG_POST
obj-$(CONFIG_CMD_DIAG) += diag.o
endif
obj-$(CONFIG_CMD_DTIMG) += dtimg.o
obj-$(CONFIG_CMD_EXTENSION) += extension_board.o
obj-$(CONFIG_CMD_ECHO) += echo.o
obj-$(CONFIG_ENV_IS_IN_EEPROM) += eeprom.o
obj-$(CONFIG_CMD_EEPROM) += eeprom.o

167
cmd/extension_board.c
View File

@@ -1,167 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2021
* Köry Maincent, Bootlin, <kory.maincent@bootlin.com>
*/
#include <common.h>
#include <command.h>
#include <malloc.h>
#include <extension_board.h>
#include <mapmem.h>
#include <linux/libfdt.h>
#include <fdt_support.h>
static LIST_HEAD(extension_list);
static int extension_apply(struct extension *extension)
{
char *overlay_cmd;
ulong extrasize, overlay_addr;
struct fdt_header *blob;
if (!working_fdt) {
printf("No FDT memory address configured. Please configure\n"
"the FDT address via \"fdt addr <address>\" command.\n");
return CMD_RET_FAILURE;
}
overlay_cmd = env_get("extension_overlay_cmd");
if (!overlay_cmd) {
printf("Environment extension_overlay_cmd is missing\n");
return CMD_RET_FAILURE;
}
overlay_addr = env_get_hex("extension_overlay_addr", 0);
if (!overlay_addr) {
printf("Environment extension_overlay_addr is missing\n");
return CMD_RET_FAILURE;
}
env_set("extension_overlay_name", extension->overlay);
if (run_command(overlay_cmd, 0) != 0)
return CMD_RET_FAILURE;
extrasize = env_get_hex("filesize", 0);
if (!extrasize)
return CMD_RET_FAILURE;
fdt_shrink_to_minimum(working_fdt, extrasize);
blob = map_sysmem(overlay_addr, 0);
if (!fdt_valid(&blob))
return CMD_RET_FAILURE;
/* apply method prints messages on error */
if (fdt_overlay_apply_verbose(working_fdt, blob))
return CMD_RET_FAILURE;
return CMD_RET_SUCCESS;
}
static int do_extension_list(struct cmd_tbl *cmdtp, int flag,
int argc, char *const argv[])
{
int i = 0;
struct extension *extension;
if (list_empty(&extension_list)) {
printf("No extension registered - Please run \"extension scan\"\n");
return CMD_RET_SUCCESS;
}
list_for_each_entry(extension, &extension_list, list) {
printf("Extension %d: %s\n", i++, extension->name);
printf("\tManufacturer: \t\t%s\n", extension->owner);
printf("\tVersion: \t\t%s\n", extension->version);
printf("\tDevicetree overlay: \t%s\n", extension->overlay);
printf("\tOther information: \t%s\n", extension->other);
}
return CMD_RET_SUCCESS;
}
static int do_extension_scan(struct cmd_tbl *cmdtp, int flag,
int argc, char *const argv[])
{
struct extension *extension, *next;
int extension_num;
list_for_each_entry_safe(extension, next, &extension_list, list) {
list_del(&extension->list);
free(extension);
}
extension_num = extension_board_scan(&extension_list);
if (extension_num < 0)
return CMD_RET_FAILURE;
printf("Found %d extension board(s).\n", extension_num);
return CMD_RET_SUCCESS;
}
static int do_extension_apply(struct cmd_tbl *cmdtp, int flag,
int argc, char *const argv[])
{
struct extension *extension = NULL;
struct list_head *entry;
int i = 0, extension_id, ret;
if (argc < 2)
return CMD_RET_USAGE;
if (strcmp(argv[1], "all") == 0) {
list_for_each_entry(extension, &extension_list, list) {
ret = extension_apply(extension);
if (ret != CMD_RET_SUCCESS)
break;
}
} else {
extension_id = simple_strtol(argv[1], NULL, 10);
list_for_each(entry, &extension_list) {
if (i == extension_id) {
extension = list_entry(entry, struct extension, list);
break;
}
i++;
}
if (!extension) {
printf("Wrong extension number\n");
return CMD_RET_FAILURE;
}
ret = extension_apply(extension);
}
return ret;
}
static struct cmd_tbl cmd_extension[] = {
U_BOOT_CMD_MKENT(scan, 1, 1, do_extension_scan, "", ""),
U_BOOT_CMD_MKENT(list, 1, 0, do_extension_list, "", ""),
U_BOOT_CMD_MKENT(apply, 2, 0, do_extension_apply, "", ""),
};
static int do_extensionops(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
{
struct cmd_tbl *cp;
/* Drop the extension command */
argc--;
argv++;
cp = find_cmd_tbl(argv[0], cmd_extension, ARRAY_SIZE(cmd_extension));
if (cp)
return cp->cmd(cmdtp, flag, argc, argv);
return CMD_RET_USAGE;
}
U_BOOT_CMD(extension, 3, 1, do_extensionops,
"Extension board management sub system",
"scan - scan plugged extension(s) board(s)\n"
"extension list - lists available extension(s) board(s)\n"
"extension apply <extension number|all> - applies DT overlays corresponding to extension boards\n"
);

49
cmd/fdt.c
View File

@@ -27,6 +27,7 @@
*/
DECLARE_GLOBAL_DATA_PTR;
static int fdt_valid(struct fdt_header **blobp);
static int fdt_parse_prop(char *const*newval, int count, char *data, int *len);
static int fdt_print(const char *pathp, char *prop, int depth);
static int is_printable_string(const void *data, int len);
@@ -731,6 +732,54 @@ static int do_fdt(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
/****************************************************************************/
/**
* fdt_valid() - Check if an FDT is valid. If not, change it to NULL
*
* @blobp: Pointer to FDT pointer
* @return 1 if OK, 0 if bad (in which case *blobp is set to NULL)
*/
static int fdt_valid(struct fdt_header **blobp)
{
const void *blob = *blobp;
int err;
if (blob == NULL) {
printf ("The address of the fdt is invalid (NULL).\n");
return 0;
}
err = fdt_check_header(blob);
if (err == 0)
return 1; /* valid */
if (err < 0) {
printf("libfdt fdt_check_header(): %s", fdt_strerror(err));
/*
* Be more informative on bad version.
*/
if (err == -FDT_ERR_BADVERSION) {
if (fdt_version(blob) <
FDT_FIRST_SUPPORTED_VERSION) {
printf (" - too old, fdt %d < %d",
fdt_version(blob),
FDT_FIRST_SUPPORTED_VERSION);
}
if (fdt_last_comp_version(blob) >
FDT_LAST_SUPPORTED_VERSION) {
printf (" - too new, fdt %d > %d",
fdt_version(blob),
FDT_LAST_SUPPORTED_VERSION);
}
}
printf("\n");
*blobp = NULL;
return 0;
}
return 1;
}
/****************************************************************************/
/*
* Parse the user's input, partially heuristic. Valid formats:
* <0x00112233 4 05> - an array of cells. Numbers follow standard

19
cmd/net.c
View File

@@ -458,22 +458,3 @@ U_BOOT_CMD(
);
#endif /* CONFIG_CMD_LINK_LOCAL */
/* moved from board_init_r sequence here to save normal boot time */
static int do_eth_init(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[])
{
puts("Net: ");
eth_initialize();
#if defined(CONFIG_RESET_PHY_R)
debug("Reset Ethernet PHY\n");
reset_phy();
#endif
return 0;
}
U_BOOT_CMD(
eth, 6, 1, do_eth_init,
"eth initialize",
""
);

103
cmd/pxe_utils.c
View File

@@ -9,8 +9,6 @@
#include <malloc.h>
#include <mapmem.h>
#include <lcd.h>
#include <fdt_support.h>
#include <linux/libfdt.h>
#include <linux/string.h>
#include <linux/ctype.h>
#include <errno.h>
@@ -281,9 +279,6 @@ static void label_destroy(struct pxe_label *label)
if (label->fdtdir)
free(label->fdtdir);
if (label->fdtoverlays)
free(label->fdtoverlays);
free(label);
}
@@ -331,92 +326,6 @@ static int label_localboot(struct pxe_label *label)
return run_command_list(localcmd, strlen(localcmd), 0);
}
/*
* Loads fdt overlays specified in 'fdtoverlays'.
*/
#ifdef CONFIG_OF_LIBFDT_OVERLAY
static void label_boot_fdtoverlay(struct cmd_tbl *cmdtp, struct pxe_label *label)
{
char *fdtoverlay = label->fdtoverlays;
struct fdt_header *working_fdt;
char *fdtoverlay_addr_env;
ulong fdtoverlay_addr;
ulong fdt_addr;
int err;
/* Get the main fdt and map it */
fdt_addr = simple_strtoul(env_get("fdt_addr_r"), NULL, 16);
working_fdt = map_sysmem(fdt_addr, 0);
err = fdt_check_header(working_fdt);
if (err)
return;
/* Get the specific overlay loading address */
fdtoverlay_addr_env = env_get("fdtoverlay_addr_r");
if (!fdtoverlay_addr_env) {
printf("Invalid fdtoverlay_addr_r for loading overlays\n");
return;
}
fdtoverlay_addr = simple_strtoul(fdtoverlay_addr_env, NULL, 16);
/* Cycle over the overlay files and apply them in order */
do {
struct fdt_header *blob;
char *overlayfile;
char *end;
int len;
/* Drop leading spaces */
while (*fdtoverlay == ' ')
++fdtoverlay;
/* Copy a single filename if multiple provided */
end = strstr(fdtoverlay, " ");
if (end) {
len = (int)(end - fdtoverlay);
overlayfile = malloc(len + 1);
strncpy(overlayfile, fdtoverlay, len);
overlayfile[len] = '\0';
} else
overlayfile = fdtoverlay;
if (!strlen(overlayfile))
goto skip_overlay;
/* Load overlay file */
err = get_relfile_envaddr(cmdtp, overlayfile,
"fdtoverlay_addr_r");
if (err < 0) {
printf("Failed loading overlay %s\n", overlayfile);
goto skip_overlay;
}
/* Resize main fdt */
fdt_shrink_to_minimum(working_fdt, 8192);
blob = map_sysmem(fdtoverlay_addr, 0);
err = fdt_check_header(blob);
if (err) {
printf("Invalid overlay %s, skipping\n",
overlayfile);
goto skip_overlay;
}
err = fdt_overlay_apply_verbose(working_fdt, blob);
if (err) {
printf("Failed to apply overlay %s, skipping\n",
overlayfile);
goto skip_overlay;
}
skip_overlay:
if (end)
free(overlayfile);
} while ((fdtoverlay = strstr(fdtoverlay, " ")));
}
#endif
/*
* Boot according to the contents of a pxe_label.
*
@@ -611,11 +520,6 @@ static int label_boot(cmd_tbl_t *cmdtp, struct pxe_label *label)
label->name);
goto cleanup;
}
#ifdef CONFIG_OF_LIBFDT_OVERLAY
if (label->fdtoverlays)
label_boot_fdtoverlay(cmdtp, label);
#endif
} else {
bootm_argv[3] = NULL;
}
@@ -673,7 +577,6 @@ enum token_type {
T_INCLUDE,
T_FDT,
T_FDTDIR,
T_FDTOVERLAYS,
T_ONTIMEOUT,
T_IPAPPEND,
T_BACKGROUND,
@@ -708,7 +611,6 @@ static const struct token keywords[] = {
{"fdt", T_FDT},
{"devicetreedir", T_FDTDIR},
{"fdtdir", T_FDTDIR},
{"fdtoverlays", T_FDTOVERLAYS},
{"ontimeout", T_ONTIMEOUT,},
{"ipappend", T_IPAPPEND,},
{"background", T_BACKGROUND,},
@@ -1141,11 +1043,6 @@ static int parse_label(char **c, struct pxe_menu *cfg)
err = parse_sliteral(c, &label->fdtdir);
break;
case T_FDTOVERLAYS:
if (!label->fdtoverlays)
err = parse_sliteral(c, &label->fdtoverlays);
break;
case T_LOCALBOOT:
label->localboot = 1;
err = parse_integer(c, &label->localboot_val);

1
cmd/pxe_utils.h
View File

@@ -43,7 +43,6 @@ struct pxe_label {
char *initrd;
char *fdt;
char *fdtdir;
char *fdtoverlays;
int ipappend;
int attempted;
int localboot;

46
common/fdt_support.c
View File

@@ -1822,49 +1822,3 @@ int fdt_overlay_apply_verbose(void *fdt, void *fdto)
return err;
}
#endif
/**
* fdt_valid() - Check if an FDT is valid. If not, change it to NULL
*
* @blobp: Pointer to FDT pointer
* @return 1 if OK, 0 if bad (in which case *blobp is set to NULL)
*/
int fdt_valid(struct fdt_header **blobp)
{
const void *blob = *blobp;
int err;
if (!blob) {
printf("The address of the fdt is invalid (NULL).\n");
return 0;
}
err = fdt_check_header(blob);
if (err == 0)
return 1; /* valid */
if (err < 0) {
printf("libfdt fdt_check_header(): %s", fdt_strerror(err));
/*
* Be more informative on bad version.
*/
if (err == -FDT_ERR_BADVERSION) {
if (fdt_version(blob) <
FDT_FIRST_SUPPORTED_VERSION) {
printf(" - too old, fdt %d < %d",
fdt_version(blob),
FDT_FIRST_SUPPORTED_VERSION);
}
if (fdt_last_comp_version(blob) >
FDT_LAST_SUPPORTED_VERSION) {
printf(" - too new, fdt %d > %d",
fdt_version(blob),
FDT_LAST_SUPPORTED_VERSION);
}
}
printf("\n");
*blobp = NULL;
return 0;
}
return 1;
}

4
common/image-fdt.c
View File

@@ -416,7 +416,7 @@ int boot_get_fdt(int flag, int argc, char * const argv[], uint8_t arch,
* FDT blob
*/
debug("* fdt: raw FDT blob\n");
debug("## Flattened Device Tree blob at %08lx\n",
printf("## Flattened Device Tree blob at %08lx\n",
(long)fdt_addr);
}
break;
@@ -425,7 +425,7 @@ int boot_get_fdt(int flag, int argc, char * const argv[], uint8_t arch,
goto no_fdt;
}
debug(" Booting using the fdt blob at %#08lx\n", fdt_addr);
printf(" Booting using the fdt blob at %#08lx\n", fdt_addr);
fdt_blob = map_sysmem(fdt_addr, 0);
} else if (images->legacy_hdr_valid &&
image_check_type(&images->legacy_hdr_os_copy,

26
common/spl/spl.c
View File

@@ -735,30 +735,6 @@ void board_init_r(gd_t *dummy1, ulong dummy2)
jump_to_image_no_args(&spl_image);
}
static void print_ruyisdk_logo(void)
{
// _____ _ _____ _____ _ __
// | __ \ (_)/ ____| __ \| |/ /
// | |__) | _ _ _ _| (___ | | | | ' /
// | _ / | | | | | | |\___ \| | | | <
// | | \ \ |_| | |_| | |____) | |__| | . \
// |_| \_\__,_|\__, |_|_____/|_____/|_|\_\
// __/ |
// |___/
printf("-----------------------------------------\n");
printf(" _____ _ _____ _____ _ __\n");
printf(" | __ \\ (_)/ ____| __ \\| |/ /\n");
printf(" | |__) | _ _ _ _| (___ | | | | ' / \n");
printf(" | _ / | | | | | | |\\___ \\| | | | < \n");
printf(" | | \\ \\ |_| | |_| | |____) | |__| | . \\ \n");
printf(" |_| \\_\\__,_|\\__, |_|_____/|_____/|_|\\_\\\n");
printf(" __/ | \n");
printf(" |___/ \n");
printf(" -- Presented by ISCAS\n");
printf("-----------------------------------------\n");
}
#ifdef CONFIG_SPL_SERIAL_SUPPORT
/*
* This requires UART clocks to be enabled. In order for this to work the
@@ -772,8 +748,6 @@ void preloader_console_init(void)
gd->have_console = 1;
print_ruyisdk_logo();
#if CONFIG_IS_ENABLED(BANNER_PRINT)
puts("\nU-Boot " SPL_TPL_NAME " " PLAIN_VERSION " (" U_BOOT_DATE " - "
U_BOOT_TIME " " U_BOOT_TZ ")\n");

1
configs/light_a_val_android_defconfig
View File

@@ -18,7 +18,6 @@ CONFIG_SYS_PROMPT="C910 Light# "
CONFIG_DDR_LP4X_3733_SINGLERANK=y
# CONFIG_DDR_LP4_3733_DUALRANK is not set
CONFIG_DDR_BOARD_CONFIG=y
CONFIG_FIXUP_MEMORY_REGION=n
CONFIG_CMD_BOOT_SLAVE=y
CONFIG_CMD_ERASEENV=y
CONFIG_CMD_GPT=y

17
configs/light_a_val_defconfig
View File

@@ -6,7 +6,6 @@ CONFIG_NR_DRAM_BANKS=8
CONFIG_SPL=y
CONFIG_SMP=y
CONFIG_TARGET_LIGHT_C910=y
CONFIG_TARGET_LIGHT_FM_C910_VAL_A=y
# CONFIG_THEAD_PLIC is not set
# CONFIG_THEAD_LIGHT_TIMER is not set
# CONFIG_THEAD_LIGHT_DIGITAL_SENSOR is not set
@@ -18,22 +17,21 @@ CONFIG_DISPLAY_BOARDINFO=y
# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
CONFIG_SPL_RAM_SUPPORT=y
CONFIG_SPL_RAM_DEVICE=y
CONFIG_SYS_PROMPT="Light VAL-A# "
CONFIG_SYS_PROMPT="C910 Light# "
CONFIG_DDR_LP4X_3733_SINGLERANK=y
# CONFIG_DDR_LP4_3733_DUALRANK is not set
CONFIG_DDR_BOARD_CONFIG=y
CONFIG_FIXUP_MEMORY_REGION=y
CONFIG_CMD_BOOT_SLAVE=y
CONFIG_CMD_ERASEENV=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MTD=y
CONFIG_CMD_USB=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_SPI=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MEMTEST=y
CONFIG_DDR_SCAN=y
CONFIG_DDR_PRBS_TEST=n
# CONFIG_DOS_PARTITION is not set
# CONFIG_ISO_PARTITION is not set
CONFIG_PARTITION_TYPE_GUID=y
CONFIG_OF_EMBED=y
@@ -64,7 +62,6 @@ CONFIG_MMC_SDHCI_SNPS=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_CMD_MMC=y
CONFIG_CMD_MMC_RPMB=y
CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_SUPPORT_EMMC_RPMB=y
CONFIG_DM_MTD=y
CONFIG_MTD_SPI_NAND=y
@@ -79,19 +76,14 @@ CONFIG_SPI=y
CONFIG_DESIGNWARE_SPI=y
CONFIG_DESIGNWARE_QSPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_DWC3=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="U-Boot-THEAD"
CONFIG_USB_GADGET_VENDOR_NUM=0x1234
CONFIG_USB_GADGET_PRODUCT_NUM=0x8888
CONFIG_USB_FUNCTION_MASS_STORAGE=y
# CONFIG_SPL_USE_TINY_PRINTF is not set
# CONFIG_EFI_LOADER is not set
# CONFIG_LIGHT_SEC_BOOT is not set
CONFIG_DEFAULT_FDT_FILE="light-a-val.dtb"
# CONFIG_LIGHT_BOOT_FORCE_SEQ is not set
CONFIG_BOARD_LATE_INIT=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_DM_VIDEO=y
@@ -111,6 +103,3 @@ CONFIG_PMIC_VOL_INIT=y
CONFIG_DDR_REGU_0V6=600000
CONFIG_DDR_REGU_0V8=800000
CONFIG_DDR_REGU_1V1=1100000
CONFIG_BOARD_RNG_SEED=y
CONFIG_MISC=y
CONFIG_LIGHT_AON_CONF=y

8
configs/light_a_val_sec_defconfig
View File

@@ -18,7 +18,6 @@ CONFIG_SYS_PROMPT="C910 Light# "
CONFIG_DDR_LP4X_3733_SINGLERANK=y
# CONFIG_DDR_LP4_3733_DUALRANK is not set
CONFIG_DDR_BOARD_CONFIG=y
CONFIG_FIXUP_MEMORY_REGION=y
# CONFIG_TPM is not set
# CONFIG_TPM_Z32H330TC_SPI is not set
# CONFIG_TPM_V2 is not set
@@ -35,6 +34,7 @@ CONFIG_CMD_I2C=y
CONFIG_CMD_MEMTEST=y
CONFIG_DDR_SCAN=y
CONFIG_DDR_PRBS_TEST=n
# CONFIG_DOS_PARTITION is not set
# CONFIG_ISO_PARTITION is not set
CONFIG_PARTITION_TYPE_GUID=y
CONFIG_OF_EMBED=y
@@ -79,9 +79,6 @@ CONFIG_SPI=y
CONFIG_DESIGNWARE_SPI=y
CONFIG_DESIGNWARE_QSPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_DWC3=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="U-Boot-THEAD"
@@ -99,7 +96,6 @@ CONFIG_PHY=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_CMD_BMP=y
CONFIG_CMD_USB=y
CONFIG_VIDEO_BRIDGE=y
CONFIG_DM_PCA953X=y
CONFIG_VIDEO_VS_DPU=y
@@ -112,5 +108,3 @@ CONFIG_PMIC_VOL_INIT=y
CONFIG_DDR_REGU_0V6=600000
CONFIG_DDR_REGU_0V8=800000
CONFIG_DDR_REGU_1V1=1100000
CONFIG_MISC=y
CONFIG_LIGHT_AON_CONF=y

1
configs/light_ant_ref_android_defconfig
View File

@@ -20,7 +20,6 @@ CONFIG_DDR_LP4X_3200_SINGLERANK=y
CONFIG_DDR_H32_MODE=y
# CONFIG_DDR_LP4_3733_DUALRANK is not set
CONFIG_DDR_BOARD_CONFIG=y
CONFIG_FIXUP_MEMORY_REGION=n
CONFIG_CMD_BOOT_SLAVE=y
CONFIG_CMD_ERASEENV=y
CONFIG_CMD_GPT=y

1
configs/light_ant_ref_defconfig
View File

@@ -20,7 +20,6 @@ CONFIG_DDR_LP4X_3200_SINGLERANK=y
CONFIG_DDR_H32_MODE=y
# CONFIG_DDR_LP4_3733_DUALRANK is not set
CONFIG_DDR_BOARD_CONFIG=y
CONFIG_FIXUP_MEMORY_REGION=y
CONFIG_CMD_BOOT_SLAVE=y
CONFIG_CMD_ERASEENV=y
CONFIG_CMD_GPT=y

1
configs/light_ant_ref_sec_defconfig
View File

@@ -20,7 +20,6 @@ CONFIG_DDR_LP4X_3200_SINGLERANK=y
CONFIG_DDR_H32_MODE=y
# CONFIG_DDR_LP4_3733_DUALRANK is not set
CONFIG_DDR_BOARD_CONFIG=y
CONFIG_FIXUP_MEMORY_REGION=y
CONFIG_CMD_BOOT_SLAVE=y
CONFIG_CMD_ERASEENV=y
CONFIG_CMD_GPT=y

1
configs/light_b_product_android_defconfig
View File

@@ -20,7 +20,6 @@ CONFIG_DDR_LP4X_3200_SINGLERANK=y
CONFIG_DDR_H32_MODE=y
# CONFIG_DDR_LP4_3733_DUALRANK is not set
CONFIG_DDR_BOARD_CONFIG=y
CONFIG_FIXUP_MEMORY_REGION=n
CONFIG_CMD_BOOT_SLAVE=y
CONFIG_CMD_ERASEENV=y
CONFIG_CMD_GPT=y

3
configs/light_b_product_defconfig
View File

@@ -20,7 +20,6 @@ CONFIG_DDR_LP4X_3200_SINGLERANK=y
CONFIG_DDR_H32_MODE=y
# CONFIG_DDR_LP4_3733_DUALRANK is not set
CONFIG_DDR_BOARD_CONFIG=y
CONFIG_FIXUP_MEMORY_REGION=y
CONFIG_CMD_BOOT_SLAVE=y
CONFIG_CMD_ERASEENV=y
CONFIG_CMD_GPT=y
@@ -105,5 +104,3 @@ CONFIG_PMIC_VOL_INIT=y
CONFIG_DDR_REGU_0V6=600000
CONFIG_DDR_REGU_0V8=800000
CONFIG_DDR_REGU_1V1=1100000
CONFIG_MISC=y
CONFIG_LIGHT_AON_CONF=y

3
configs/light_b_product_sec_defconfig
View File

@@ -20,7 +20,6 @@ CONFIG_DDR_LP4X_3200_SINGLERANK=y
CONFIG_DDR_H32_MODE=y
# CONFIG_DDR_LP4_3733_DUALRANK is not set
CONFIG_DDR_BOARD_CONFIG=y
CONFIG_FIXUP_MEMORY_REGION=y
CONFIG_CMD_BOOT_SLAVE=y
CONFIG_CMD_ERASEENV=y
CONFIG_CMD_GPT=y
@@ -105,5 +104,3 @@ CONFIG_PMIC_VOL_INIT=y
CONFIG_DDR_REGU_0V6=600000
CONFIG_DDR_REGU_0V8=800000
CONFIG_DDR_REGU_1V1=1100000
CONFIG_MISC=y
CONFIG_LIGHT_AON_CONF=y

3
configs/light_beagle_android_defconfig
View File

@@ -19,7 +19,6 @@ CONFIG_SYS_PROMPT="C910 Light# "
CONFIG_DDR_LP4X_3733_SINGLERANK=y
# CONFIG_DDR_LP4_3733_DUALRANK is not set
CONFIG_DDR_BOARD_CONFIG=y
CONFIG_FIXUP_MEMORY_REGION=n
CONFIG_CMD_BOOT_SLAVE=y
CONFIG_CMD_ERASEENV=y
CONFIG_CMD_GPT=y
@@ -115,4 +114,4 @@ CONFIG_ANDROID_AB=y
CONFIG_CMD_AB_SELECT=y
CONFIG_XBC=y
CONFIG_BOARD_RNG_SEED=y
CONFIG_SPL_TEXT_BASE=0xffe0000800
CONFIG_SPL_TEXT_BASE=0xffe0000800

68
configs/light_beagle_defconfig
View File

@@ -6,41 +6,39 @@ CONFIG_NR_DRAM_BANKS=8
CONFIG_SPL=y
CONFIG_SMP=y
CONFIG_TARGET_LIGHT_C910=y
CONFIG_PMIC_VOL_INIT=y
CONFIG_TARGET_LIGHT_FM_C910_BEAGLE=y
CONFIG_DDR_LP4X_3733_SINGLERANK=y
CONFIG_DDR_BOARD_CONFIG=y
# CONFIG_THEAD_PLIC is not set
# CONFIG_THEAD_LIGHT_TIMER is not set
# CONFIG_THEAD_LIGHT_DIGITAL_SENSOR is not set
CONFIG_ARCH_RV64I=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BUILD_TARGET="u-boot-with-spl.bin"
CONFIG_DEFAULT_FDT_FILE="thead/light-beagle.dtb"
CONFIG_BOARD_LATE_INIT=y
CONFIG_DISPLAY_CPUINFO=y
CONFIG_DISPLAY_BOARDINFO=y
# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
CONFIG_SPL_RAM_SUPPORT=y
CONFIG_SPL_RAM_DEVICE=y
CONFIG_SYS_PROMPT="Light AHead# "
CONFIG_SYS_PROMPT="C910 Light# "
CONFIG_DDR_LP4X_3733_SINGLERANK=y
# CONFIG_DDR_LP4_3733_DUALRANK is not set
CONFIG_DDR_BOARD_CONFIG=y
CONFIG_CMD_BOOT_SLAVE=y
CONFIG_CMD_ERASEENV=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MTD=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_SPI=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MEMTEST=y
CONFIG_DDR_SCAN=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MTD=y
CONFIG_CMD_SPI=y
CONFIG_CMD_BMP=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_DDR_PRBS_TEST=n
# CONFIG_DOS_PARTITION is not set
# CONFIG_ISO_PARTITION is not set
CONFIG_PARTITION_TYPE_GUID=y
CONFIG_OF_EMBED=y
CONFIG_DEFAULT_DEVICE_TREE="light-beagle"
CONFIG_DEFAULT_DEVICE_TREE="light-a-val"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_SPL_CLK=y
CONFIG_USB_FUNCTION_FASTBOOT=y
CONFIG_UDP_FUNCTION_FASTBOOT=y
@@ -49,12 +47,11 @@ CONFIG_FASTBOOT_FLASH=y
CONFIG_FASTBOOT_FLASH_MMC_DEV=0
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
CONFIG_DM_GPIO=y
CONFIG_DWAPB_GPIO=y
CONFIG_DM_PCA953X=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_DW=y
CONFIG_DWAPB_GPIO=y
# CONFIG_MMC_SPI is not set
CONFIG_SUPPORT_EMMC_RPMB=y
CONFIG_MMC_VERBOSE=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_IO_VOLTAGE=y
CONFIG_MMC_UHS_SUPPORT=y
@@ -62,21 +59,19 @@ CONFIG_MMC_HS400_SUPPORT=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_SNPS=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_SNPS=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_CMD_MMC=y
CONFIG_CMD_MMC_RPMB=y
CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_SUPPORT_EMMC_RPMB=y
CONFIG_DM_MTD=y
CONFIG_MTD_SPI_NAND=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_PHY_REALTEK=y
CONFIG_RTL8211E_PINE64_GIGABIT_FIX=y
CONFIG_RTL8211X_PHY_FORCE_MASTER=y
CONFIG_RTL8211F_PHY_FORCE_EEE_RXC_ON=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_PHY=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DESIGNWARE_SPI=y
@@ -87,18 +82,25 @@ CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="U-Boot-THEAD"
CONFIG_USB_GADGET_VENDOR_NUM=0x1234
CONFIG_USB_GADGET_PRODUCT_NUM=0x8888
CONFIG_USB_FUNCTION_MASS_STORAGE=y
# CONFIG_SPL_USE_TINY_PRINTF is not set
# CONFIG_EFI_LOADER is not set
# CONFIG_LIGHT_SEC_BOOT is not set
CONFIG_BOARD_LATE_INIT=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_DM_VIDEO=y
CONFIG_SYS_WHITE_ON_BLACK=y
CONFIG_VIDEO_LCD_ILITEK_ILI9881C=y
CONFIG_PHY=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_CMD_BMP=y
CONFIG_VIDEO_BRIDGE=y
CONFIG_DM_PCA953X=y
CONFIG_VIDEO_VS_DPU=y
CONFIG_VIDEO_LCD_ILITEK_ILI9881C=y
CONFIG_VIDEO_DW_DSI_LIGHT=y
CONFIG_VIDEO_DW_DPHY=y
# CONFIG_SPL_USE_TINY_PRINTF is not set
CONFIG_OF_LIBFDT_OVERLAY=y
# CONFIG_EFI_LOADER is not set
CONFIG_BOARD_RNG_SEED=y
CONFIG_FIXUP_MEMORY_REGION=y
CONFIG_MISC=y
CONFIG_LIGHT_AON_CONF=y
CONFIG_VIDEO_DW_DSI_HOST=y
CONFIG_SYS_WHITE_ON_BLACK=y
CONFIG_PMIC_VOL_INIT=y
CONFIG_DDR_REGU_0V6=600000
CONFIG_DDR_REGU_0V8=800000
CONFIG_DDR_REGU_1V1=1100000

137
configs/light_huiwei_defconfig
View File

@@ -1,137 +0,0 @@
CONFIG_RISCV=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_OFFSET=0xe0000
CONFIG_NR_DRAM_BANKS=8
CONFIG_SPL=y
CONFIG_SMP=y
CONFIG_TARGET_LIGHT_C910=y
CONFIG_TARGET_LIGHT_FM_C910_LPI4A=y
# CONFIG_THEAD_PLIC is not set
# CONFIG_THEAD_LIGHT_TIMER is not set
# CONFIG_THEAD_LIGHT_DIGITAL_SENSOR is not set
CONFIG_ARCH_RV64I=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BUILD_TARGET="u-boot-with-spl.bin"
CONFIG_DISPLAY_CPUINFO=y
CONFIG_DISPLAY_BOARDINFO=y
# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
CONFIG_SPL_RAM_SUPPORT=y
CONFIG_SPL_RAM_DEVICE=y
CONFIG_SYS_PROMPT="Light huiwei# "
CONFIG_DDR_LP4X_3733_DUALRANK=y
# CONFIG_DDR_LP4_3733_DUALRANK is not set
CONFIG_DDR_BOARD_CONFIG=y
CONFIG_FIXUP_MEMORY_REGION=y
CONFIG_CMD_BOOT_SLAVE=y
CONFIG_CMD_ERASEENV=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MTD=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_SPI=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MEMTEST=y
CONFIG_DDR_SCAN=y
CONFIG_DDR_PRBS_TEST=n
# CONFIG_ISO_PARTITION is not set
CONFIG_PARTITION_TYPE_GUID=y
CONFIG_OF_EMBED=y
CONFIG_DEFAULT_DEVICE_TREE="light-huiwei"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SPL_CLK=y
CONFIG_USB_FUNCTION_FASTBOOT=y
CONFIG_UDP_FUNCTION_FASTBOOT=y
CONFIG_FASTBOOT_BUF_ADDR=0x10000000
CONFIG_FASTBOOT_FLASH=y
CONFIG_FASTBOOT_FLASH_MMC_DEV=0
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
CONFIG_DM_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_DW=y
CONFIG_DWAPB_GPIO=y
# CONFIG_MMC_SPI is not set
CONFIG_MMC_VERBOSE=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_IO_VOLTAGE=y
CONFIG_MMC_UHS_SUPPORT=y
CONFIG_MMC_HS400_SUPPORT=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_SNPS=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SNPS=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_CMD_MMC=y
CONFIG_CMD_MMC_RPMB=y
CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_SUPPORT_EMMC_RPMB=y
CONFIG_DM_MTD=y
CONFIG_MTD_SPI_NAND=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_PHY_REALTEK=y
CONFIG_RTL8211E_PINE64_GIGABIT_FIX=y
CONFIG_RTL8211X_PHY_FORCE_MASTER=y
CONFIG_RTL8211F_PHY_FORCE_EEE_RXC_ON=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DESIGNWARE_SPI=y
CONFIG_DESIGNWARE_QSPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_DWC3=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="U-Boot-THEAD"
CONFIG_USB_GADGET_VENDOR_NUM=0x1234
CONFIG_USB_GADGET_PRODUCT_NUM=0x8888
CONFIG_USB_FUNCTION_MASS_STORAGE=y
# CONFIG_SPL_USE_TINY_PRINTF is not set
# CONFIG_EFI_LOADER is not set
# CONFIG_LIGHT_SEC_BOOT is not set
CONFIG_DEFAULT_FDT_FILE="thead/th1520-huiwei-product.dtb"
CONFIG_BOARD_LATE_INIT=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_DM_VIDEO=y
CONFIG_PHY=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_CMD_BMP=y
CONFIG_CMD_USB=y
CONFIG_VIDEO_BRIDGE=y
CONFIG_DM_PCA953X=y
CONFIG_VIDEO_VS_DPU=y
CONFIG_VIDEO_LCD_ILITEK_ILI9881C=n
CONFIG_VIDEO_LCD_JD9365DA=y
#CONFIG_VIDEO_LCD_CUSTOM_LOGO=y
CONFIG_VIDEO_DW_DSI_LIGHT=y
CONFIG_VIDEO_DW_DPHY=y
CONFIG_VIDEO_DW_DSI_HOST=y
CONFIG_SYS_WHITE_ON_BLACK=y
CONFIG_PMIC_VOL_INIT=y
CONFIG_DDR_REGU_0V6=600000
CONFIG_DDR_REGU_0V8=800000
CONFIG_DDR_REGU_1V1=1100000
CONFIG_BOARD_RNG_SEED=y
CONFIG_MISC=y
CONFIG_LIGHT_AON_CONF=y
CONFIG_TPM=y
CONFIG_TPM_V2=y
CONFIG_TPM_Z32H330TC_SPI=y
CONFIG_CMD_TPM=y
CONFIG_CMD_TPM_V2=y
CONFIG_CMD_TPM_TEST=y
CONFIG_DM_CHARGE_DISPLAY=y
CONFIG_CHARGE_ANIMATION=y
CONFIG_DM_FUEL_GAUGE=y
CONFIG_POWER_FG_CW201X=y
CONFIG_CHARGER_BQ25700=y
CONFIG_LED=y
CONFIG_LED_GPIO=y
CONFIG_DM_MCU=y
CONFIG_MCU_HC32fX=y
CONFIG_DM_POWER_DELIVERY=y
CONFIG_TYPEC_TCPM=y
CONFIG_TYPEC_TCPCI=y
CONFIG_TYPEC_HUSB311=y

114
configs/light_lpi4a_16g_defconfig
View File

@@ -1,114 +0,0 @@
CONFIG_RISCV=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_OFFSET=0xe0000
CONFIG_NR_DRAM_BANKS=8
CONFIG_SPL=y
CONFIG_SMP=y
CONFIG_TARGET_LIGHT_C910=y
CONFIG_TARGET_LIGHT_FM_C910_LPI4A=y
# CONFIG_THEAD_PLIC is not set
# CONFIG_THEAD_LIGHT_TIMER is not set
# CONFIG_THEAD_LIGHT_DIGITAL_SENSOR is not set
CONFIG_ARCH_RV64I=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BUILD_TARGET="u-boot-with-spl.bin"
CONFIG_DISPLAY_CPUINFO=y
CONFIG_DISPLAY_BOARDINFO=y
# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
CONFIG_SPL_RAM_SUPPORT=y
CONFIG_SPL_RAM_DEVICE=y
CONFIG_SYS_PROMPT="Light LPI4A 16G# "
CONFIG_DDR_LP4X_3733_DUALRANK=y
CONFIG_DDR_DDP=y
# CONFIG_DDR_LP4_3733_DUALRANK is not set
CONFIG_DDR_BOARD_CONFIG=y
CONFIG_CMD_BOOT_SLAVE=y
CONFIG_CMD_ERASEENV=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MTD=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_SPI=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MEMTEST=y
CONFIG_DDR_SCAN=y
CONFIG_DDR_PRBS_TEST=n
# CONFIG_DOS_PARTITION is not set
# CONFIG_ISO_PARTITION is not set
CONFIG_PARTITION_TYPE_GUID=y
CONFIG_OF_EMBED=y
CONFIG_DEFAULT_DEVICE_TREE="light-lpi4a"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SPL_CLK=y
CONFIG_USB_FUNCTION_FASTBOOT=y
CONFIG_UDP_FUNCTION_FASTBOOT=y
CONFIG_FASTBOOT_BUF_ADDR=0x10000000
CONFIG_FASTBOOT_FLASH=y
CONFIG_FASTBOOT_FLASH_MMC_DEV=0
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
CONFIG_DM_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_DW=y
CONFIG_DWAPB_GPIO=y
# CONFIG_MMC_SPI is not set
CONFIG_MMC_VERBOSE=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_IO_VOLTAGE=y
CONFIG_MMC_UHS_SUPPORT=y
CONFIG_MMC_HS400_SUPPORT=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_SNPS=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SNPS=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_CMD_MMC=y
CONFIG_CMD_MMC_RPMB=y
CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_SUPPORT_EMMC_RPMB=y
CONFIG_DM_MTD=y
CONFIG_MTD_SPI_NAND=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_PHY_REALTEK=y
CONFIG_RTL8211E_PINE64_GIGABIT_FIX=y
CONFIG_RTL8211X_PHY_FORCE_MASTER=y
CONFIG_RTL8211F_PHY_FORCE_EEE_RXC_ON=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DESIGNWARE_SPI=y
CONFIG_DESIGNWARE_QSPI=y
CONFIG_USB=y
CONFIG_USB_DWC3=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="U-Boot-THEAD"
CONFIG_USB_GADGET_VENDOR_NUM=0x1234
CONFIG_USB_GADGET_PRODUCT_NUM=0x8888
CONFIG_USB_FUNCTION_MASS_STORAGE=y
# CONFIG_SPL_USE_TINY_PRINTF is not set
# CONFIG_EFI_LOADER is not set
# CONFIG_LIGHT_SEC_BOOT is not set
CONFIG_DEFAULT_FDT_FILE="thead/light-lpi4a-16gb.dtb"
CONFIG_BOARD_LATE_INIT=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_DM_VIDEO=y
CONFIG_PHY=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_CMD_BMP=y
CONFIG_VIDEO_BRIDGE=y
CONFIG_DM_PCA953X=y
CONFIG_VIDEO_VS_DPU=y
CONFIG_VIDEO_LCD_ILITEK_ILI9881C=y
CONFIG_VIDEO_DW_DSI_LIGHT=y
CONFIG_VIDEO_DW_DPHY=y
CONFIG_VIDEO_DW_DSI_HOST=y
CONFIG_SYS_WHITE_ON_BLACK=y
CONFIG_PMIC_VOL_INIT=y
CONFIG_DDR_REGU_0V6=600000
CONFIG_DDR_REGU_0V8=800000
CONFIG_DDR_REGU_1V1=1100000
CONFIG_BOARD_RNG_SEED=y
CONFIG_FIXUP_MEMORY_REGION=y
CONFIG_MISC=y
CONFIG_LIGHT_AON_CONF=y

1
configs/light_lpi4a_android_defconfig
View File

@@ -19,7 +19,6 @@ CONFIG_SYS_PROMPT="C910 Light# "
CONFIG_DDR_LP4X_3733_DUALRANK=y
# CONFIG_DDR_LP4_3733_DUALRANK is not set
CONFIG_DDR_BOARD_CONFIG=y
CONFIG_FIXUP_MEMORY_REGION=n
CONFIG_CMD_BOOT_SLAVE=y
CONFIG_CMD_ERASEENV=y
CONFIG_CMD_GPT=y

114
configs/light_lpi4a_cluster_16g_defconfig
View File

@@ -1,114 +0,0 @@
CONFIG_RISCV=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_OFFSET=0xe0000
CONFIG_NR_DRAM_BANKS=8
CONFIG_SPL=y
CONFIG_SMP=y
CONFIG_TARGET_LIGHT_C910=y
CONFIG_TARGET_LIGHT_FM_C910_LPI4A=y
# CONFIG_THEAD_PLIC is not set
# CONFIG_THEAD_LIGHT_TIMER is not set
# CONFIG_THEAD_LIGHT_DIGITAL_SENSOR is not set
CONFIG_ARCH_RV64I=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BUILD_TARGET="u-boot-with-spl.bin"
CONFIG_DISPLAY_CPUINFO=y
CONFIG_DISPLAY_BOARDINFO=y
# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
CONFIG_SPL_RAM_SUPPORT=y
CONFIG_SPL_RAM_DEVICE=y
CONFIG_SYS_PROMPT="LicheeCluster4A 16G # "
CONFIG_DDR_LP4X_3733_DUALRANK=y
CONFIG_DDR_DDP=y
# CONFIG_DDR_LP4_3733_DUALRANK is not set
CONFIG_DDR_BOARD_CONFIG=y
CONFIG_CMD_BOOT_SLAVE=y
CONFIG_CMD_ERASEENV=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MTD=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_SPI=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MEMTEST=y
CONFIG_DDR_SCAN=y
CONFIG_DDR_PRBS_TEST=n
# CONFIG_DOS_PARTITION is not set
# CONFIG_ISO_PARTITION is not set
CONFIG_PARTITION_TYPE_GUID=y
CONFIG_OF_EMBED=y
CONFIG_DEFAULT_DEVICE_TREE="light-lpi4a"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SPL_CLK=y
CONFIG_USB_FUNCTION_FASTBOOT=y
CONFIG_UDP_FUNCTION_FASTBOOT=y
CONFIG_FASTBOOT_BUF_ADDR=0x10000000
CONFIG_FASTBOOT_FLASH=y
CONFIG_FASTBOOT_FLASH_MMC_DEV=0
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
CONFIG_DM_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_DW=y
CONFIG_DWAPB_GPIO=y
# CONFIG_MMC_SPI is not set
CONFIG_MMC_VERBOSE=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_IO_VOLTAGE=y
CONFIG_MMC_UHS_SUPPORT=y
CONFIG_MMC_HS400_SUPPORT=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_SNPS=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SNPS=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_CMD_MMC=y
CONFIG_CMD_MMC_RPMB=y
CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_SUPPORT_EMMC_RPMB=y
CONFIG_DM_MTD=y
CONFIG_MTD_SPI_NAND=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_PHY_REALTEK=y
CONFIG_RTL8211E_PINE64_GIGABIT_FIX=y
CONFIG_RTL8211X_PHY_FORCE_MASTER=y
CONFIG_RTL8211F_PHY_FORCE_EEE_RXC_ON=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DESIGNWARE_SPI=y
CONFIG_DESIGNWARE_QSPI=y
CONFIG_USB=y
CONFIG_USB_DWC3=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="U-Boot-THEAD"
CONFIG_USB_GADGET_VENDOR_NUM=0x1234
CONFIG_USB_GADGET_PRODUCT_NUM=0x8888
CONFIG_USB_FUNCTION_MASS_STORAGE=y
# CONFIG_SPL_USE_TINY_PRINTF is not set
# CONFIG_EFI_LOADER is not set
# CONFIG_LIGHT_SEC_BOOT is not set
CONFIG_DEFAULT_FDT_FILE="thead/light-lpi4a-cluster-16gb.dtb"
CONFIG_BOARD_LATE_INIT=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_DM_VIDEO=y
CONFIG_PHY=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_CMD_BMP=y
CONFIG_VIDEO_BRIDGE=y
CONFIG_DM_PCA953X=y
CONFIG_VIDEO_VS_DPU=y
CONFIG_VIDEO_LCD_ILITEK_ILI9881C=y
CONFIG_VIDEO_DW_DSI_LIGHT=y
CONFIG_VIDEO_DW_DPHY=y
CONFIG_VIDEO_DW_DSI_HOST=y
CONFIG_SYS_WHITE_ON_BLACK=y
CONFIG_PMIC_VOL_INIT=y
CONFIG_DDR_REGU_0V6=600000
CONFIG_DDR_REGU_0V8=800000
CONFIG_DDR_REGU_1V1=1100000
CONFIG_BOARD_RNG_SEED=y
CONFIG_FIXUP_MEMORY_REGION=y
CONFIG_MISC=y
CONFIG_LIGHT_AON_CONF=y

113
configs/light_lpi4a_cluster_defconfig
View File

@@ -1,113 +0,0 @@
CONFIG_RISCV=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_OFFSET=0xe0000
CONFIG_NR_DRAM_BANKS=8
CONFIG_SPL=y
CONFIG_SMP=y
CONFIG_TARGET_LIGHT_C910=y
CONFIG_TARGET_LIGHT_FM_C910_LPI4A=y
# CONFIG_THEAD_PLIC is not set
# CONFIG_THEAD_LIGHT_TIMER is not set
# CONFIG_THEAD_LIGHT_DIGITAL_SENSOR is not set
CONFIG_ARCH_RV64I=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BUILD_TARGET="u-boot-with-spl.bin"
CONFIG_DISPLAY_CPUINFO=y
CONFIG_DISPLAY_BOARDINFO=y
# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
CONFIG_SPL_RAM_SUPPORT=y
CONFIG_SPL_RAM_DEVICE=y
CONFIG_SYS_PROMPT="LicheeCluster4A # "
CONFIG_DDR_LP4X_3733_DUALRANK=y
# CONFIG_DDR_LP4_3733_DUALRANK is not set
CONFIG_DDR_BOARD_CONFIG=y
CONFIG_CMD_BOOT_SLAVE=y
CONFIG_CMD_ERASEENV=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MTD=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_SPI=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MEMTEST=y
CONFIG_DDR_SCAN=y
CONFIG_DDR_PRBS_TEST=n
# CONFIG_DOS_PARTITION is not set
# CONFIG_ISO_PARTITION is not set
CONFIG_PARTITION_TYPE_GUID=y
CONFIG_OF_EMBED=y
CONFIG_DEFAULT_DEVICE_TREE="light-lpi4a"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SPL_CLK=y
CONFIG_USB_FUNCTION_FASTBOOT=y
CONFIG_UDP_FUNCTION_FASTBOOT=y
CONFIG_FASTBOOT_BUF_ADDR=0x10000000
CONFIG_FASTBOOT_FLASH=y
CONFIG_FASTBOOT_FLASH_MMC_DEV=0
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
CONFIG_DM_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_DW=y
CONFIG_DWAPB_GPIO=y
# CONFIG_MMC_SPI is not set
CONFIG_MMC_VERBOSE=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_IO_VOLTAGE=y
CONFIG_MMC_UHS_SUPPORT=y
CONFIG_MMC_HS400_SUPPORT=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_SNPS=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SNPS=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_CMD_MMC=y
CONFIG_CMD_MMC_RPMB=y
CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_SUPPORT_EMMC_RPMB=y
CONFIG_DM_MTD=y
CONFIG_MTD_SPI_NAND=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_PHY_REALTEK=y
CONFIG_RTL8211E_PINE64_GIGABIT_FIX=y
CONFIG_RTL8211X_PHY_FORCE_MASTER=y
CONFIG_RTL8211F_PHY_FORCE_EEE_RXC_ON=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DESIGNWARE_SPI=y
CONFIG_DESIGNWARE_QSPI=y
CONFIG_USB=y
CONFIG_USB_DWC3=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="U-Boot-THEAD"
CONFIG_USB_GADGET_VENDOR_NUM=0x1234
CONFIG_USB_GADGET_PRODUCT_NUM=0x8888
CONFIG_USB_FUNCTION_MASS_STORAGE=y
# CONFIG_SPL_USE_TINY_PRINTF is not set
# CONFIG_EFI_LOADER is not set
# CONFIG_LIGHT_SEC_BOOT is not set
CONFIG_DEFAULT_FDT_FILE="thead/light-lpi4a-cluster.dtb"
CONFIG_BOARD_LATE_INIT=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_DM_VIDEO=y
CONFIG_PHY=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_CMD_BMP=y
CONFIG_VIDEO_BRIDGE=y
CONFIG_DM_PCA953X=y
CONFIG_VIDEO_VS_DPU=y
CONFIG_VIDEO_LCD_ILITEK_ILI9881C=y
CONFIG_VIDEO_DW_DSI_LIGHT=y
CONFIG_VIDEO_DW_DPHY=y
CONFIG_VIDEO_DW_DSI_HOST=y
CONFIG_SYS_WHITE_ON_BLACK=y
CONFIG_PMIC_VOL_INIT=y
CONFIG_DDR_REGU_0V6=600000
CONFIG_DDR_REGU_0V8=800000
CONFIG_DDR_REGU_1V1=1100000
CONFIG_BOARD_RNG_SEED=y
CONFIG_FIXUP_MEMORY_REGION=y
CONFIG_MISC=y
CONFIG_LIGHT_AON_CONF=y

114
configs/light_lpi4a_console_16g_defconfig
View File

@@ -1,114 +0,0 @@
CONFIG_RISCV=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_OFFSET=0xe0000
CONFIG_NR_DRAM_BANKS=8
CONFIG_SPL=y
CONFIG_SMP=y
CONFIG_TARGET_LIGHT_C910=y
CONFIG_TARGET_LIGHT_FM_C910_LPI4A=y
# CONFIG_THEAD_PLIC is not set
# CONFIG_THEAD_LIGHT_TIMER is not set
# CONFIG_THEAD_LIGHT_DIGITAL_SENSOR is not set
CONFIG_ARCH_RV64I=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BUILD_TARGET="u-boot-with-spl.bin"
CONFIG_DISPLAY_CPUINFO=y
CONFIG_DISPLAY_BOARDINFO=y
# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
CONFIG_SPL_RAM_SUPPORT=y
CONFIG_SPL_RAM_DEVICE=y
CONFIG_SYS_PROMPT="LicheeConsole4A 16G # "
CONFIG_DDR_LP4X_3733_DUALRANK=y
CONFIG_DDR_DDP=y
# CONFIG_DDR_LP4_3733_DUALRANK is not set
CONFIG_DDR_BOARD_CONFIG=y
CONFIG_CMD_BOOT_SLAVE=y
CONFIG_CMD_ERASEENV=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MTD=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_SPI=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MEMTEST=y
CONFIG_DDR_SCAN=y
CONFIG_DDR_PRBS_TEST=n
# CONFIG_DOS_PARTITION is not set
# CONFIG_ISO_PARTITION is not set
CONFIG_PARTITION_TYPE_GUID=y
CONFIG_OF_EMBED=y
CONFIG_DEFAULT_DEVICE_TREE="light-lpi4a-laptop"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SPL_CLK=y
CONFIG_USB_FUNCTION_FASTBOOT=y
CONFIG_UDP_FUNCTION_FASTBOOT=y
CONFIG_FASTBOOT_BUF_ADDR=0x10000000
CONFIG_FASTBOOT_FLASH=y
CONFIG_FASTBOOT_FLASH_MMC_DEV=0
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
CONFIG_DM_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_DW=y
CONFIG_DWAPB_GPIO=y
# CONFIG_MMC_SPI is not set
CONFIG_MMC_VERBOSE=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_IO_VOLTAGE=y
CONFIG_MMC_UHS_SUPPORT=y
CONFIG_MMC_HS400_SUPPORT=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_SNPS=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SNPS=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_CMD_MMC=y
CONFIG_CMD_MMC_RPMB=y
CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_SUPPORT_EMMC_RPMB=y
CONFIG_DM_MTD=y
CONFIG_MTD_SPI_NAND=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_PHY_REALTEK=y
CONFIG_RTL8211E_PINE64_GIGABIT_FIX=y
CONFIG_RTL8211X_PHY_FORCE_MASTER=y
CONFIG_RTL8211F_PHY_FORCE_EEE_RXC_ON=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DESIGNWARE_SPI=y
CONFIG_DESIGNWARE_QSPI=y
CONFIG_USB=y
CONFIG_USB_DWC3=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="U-Boot-THEAD"
CONFIG_USB_GADGET_VENDOR_NUM=0x1234
CONFIG_USB_GADGET_PRODUCT_NUM=0x8888
CONFIG_USB_FUNCTION_MASS_STORAGE=y
# CONFIG_SPL_USE_TINY_PRINTF is not set
# CONFIG_EFI_LOADER is not set
# CONFIG_LIGHT_SEC_BOOT is not set
CONFIG_DEFAULT_FDT_FILE="thead/light-lpi4a-console-16g.dtb"
CONFIG_BOARD_LATE_INIT=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_DM_VIDEO=y
CONFIG_PHY=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_CMD_BMP=y
CONFIG_VIDEO_BRIDGE=y
CONFIG_DM_PCA953X=y
CONFIG_VIDEO_VS_DPU=y
CONFIG_VIDEO_LCD_ILITEK_ILI9881C=y
CONFIG_VIDEO_DW_DSI_LIGHT=y
CONFIG_VIDEO_DW_DPHY=y
CONFIG_VIDEO_DW_DSI_HOST=y
CONFIG_SYS_WHITE_ON_BLACK=y
CONFIG_PMIC_VOL_INIT=y
CONFIG_DDR_REGU_0V6=600000
CONFIG_DDR_REGU_0V8=800000
CONFIG_DDR_REGU_1V1=1100000
CONFIG_BOARD_RNG_SEED=y
CONFIG_FIXUP_MEMORY_REGION=y
CONFIG_MISC=y
CONFIG_LIGHT_AON_CONF=y

113
configs/light_lpi4a_console_defconfig
View File

@@ -1,113 +0,0 @@
CONFIG_RISCV=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_OFFSET=0xe0000
CONFIG_NR_DRAM_BANKS=8
CONFIG_SPL=y
CONFIG_SMP=y
CONFIG_TARGET_LIGHT_C910=y
CONFIG_TARGET_LIGHT_FM_C910_LPI4A=y
# CONFIG_THEAD_PLIC is not set
# CONFIG_THEAD_LIGHT_TIMER is not set
# CONFIG_THEAD_LIGHT_DIGITAL_SENSOR is not set
CONFIG_ARCH_RV64I=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BUILD_TARGET="u-boot-with-spl.bin"
CONFIG_DISPLAY_CPUINFO=y
CONFIG_DISPLAY_BOARDINFO=y
# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
CONFIG_SPL_RAM_SUPPORT=y
CONFIG_SPL_RAM_DEVICE=y
CONFIG_SYS_PROMPT="LicheeConsole4A # "
CONFIG_DDR_LP4X_3733_DUALRANK=y
# CONFIG_DDR_LP4_3733_DUALRANK is not set
CONFIG_DDR_BOARD_CONFIG=y
CONFIG_CMD_BOOT_SLAVE=y
CONFIG_CMD_ERASEENV=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MTD=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_SPI=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MEMTEST=y
CONFIG_DDR_SCAN=y
CONFIG_DDR_PRBS_TEST=n
# CONFIG_DOS_PARTITION is not set
# CONFIG_ISO_PARTITION is not set
CONFIG_PARTITION_TYPE_GUID=y
CONFIG_OF_EMBED=y
CONFIG_DEFAULT_DEVICE_TREE="light-lpi4a-laptop"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SPL_CLK=y
CONFIG_USB_FUNCTION_FASTBOOT=y
CONFIG_UDP_FUNCTION_FASTBOOT=y
CONFIG_FASTBOOT_BUF_ADDR=0x10000000
CONFIG_FASTBOOT_FLASH=y
CONFIG_FASTBOOT_FLASH_MMC_DEV=0
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
CONFIG_DM_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_DW=y
CONFIG_DWAPB_GPIO=y
# CONFIG_MMC_SPI is not set
CONFIG_MMC_VERBOSE=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_IO_VOLTAGE=y
CONFIG_MMC_UHS_SUPPORT=y
CONFIG_MMC_HS400_SUPPORT=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_SNPS=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SNPS=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_CMD_MMC=y
CONFIG_CMD_MMC_RPMB=y
CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_SUPPORT_EMMC_RPMB=y
CONFIG_DM_MTD=y
CONFIG_MTD_SPI_NAND=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_PHY_REALTEK=y
CONFIG_RTL8211E_PINE64_GIGABIT_FIX=y
CONFIG_RTL8211X_PHY_FORCE_MASTER=y
CONFIG_RTL8211F_PHY_FORCE_EEE_RXC_ON=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DESIGNWARE_SPI=y
CONFIG_DESIGNWARE_QSPI=y
CONFIG_USB=y
CONFIG_USB_DWC3=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="U-Boot-THEAD"
CONFIG_USB_GADGET_VENDOR_NUM=0x1234
CONFIG_USB_GADGET_PRODUCT_NUM=0x8888
CONFIG_USB_FUNCTION_MASS_STORAGE=y
# CONFIG_SPL_USE_TINY_PRINTF is not set
# CONFIG_EFI_LOADER is not set
# CONFIG_LIGHT_SEC_BOOT is not set
CONFIG_DEFAULT_FDT_FILE="thead/light-lpi4a-console.dtb"
CONFIG_BOARD_LATE_INIT=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_DM_VIDEO=y
CONFIG_PHY=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_CMD_BMP=y
CONFIG_VIDEO_BRIDGE=y
CONFIG_DM_PCA953X=y
CONFIG_VIDEO_VS_DPU=y
CONFIG_VIDEO_LCD_ILITEK_ILI9881C=y
CONFIG_VIDEO_DW_DSI_LIGHT=y
CONFIG_VIDEO_DW_DPHY=y
CONFIG_VIDEO_DW_DSI_HOST=y
CONFIG_SYS_WHITE_ON_BLACK=y
CONFIG_PMIC_VOL_INIT=y
CONFIG_DDR_REGU_0V6=600000
CONFIG_DDR_REGU_0V8=800000
CONFIG_DDR_REGU_1V1=1100000
CONFIG_BOARD_RNG_SEED=y
CONFIG_FIXUP_MEMORY_REGION=y
CONFIG_MISC=y
CONFIG_LIGHT_AON_CONF=y

19
configs/light_lpi4a_defconfig
View File

@@ -18,11 +18,10 @@ CONFIG_DISPLAY_BOARDINFO=y
# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
CONFIG_SPL_RAM_SUPPORT=y
CONFIG_SPL_RAM_DEVICE=y
CONFIG_SYS_PROMPT="Light LPI4A# "
CONFIG_SYS_PROMPT="C910 Light# "
CONFIG_DDR_LP4X_3733_DUALRANK=y
# CONFIG_DDR_LP4_3733_DUALRANK is not set
CONFIG_DDR_BOARD_CONFIG=y
CONFIG_FIXUP_MEMORY_REGION=y
CONFIG_CMD_BOOT_SLAVE=y
CONFIG_CMD_ERASEENV=y
CONFIG_CMD_GPT=y
@@ -33,6 +32,7 @@ CONFIG_CMD_I2C=y
CONFIG_CMD_MEMTEST=y
CONFIG_DDR_SCAN=y
CONFIG_DDR_PRBS_TEST=n
# CONFIG_DOS_PARTITION is not set
# CONFIG_ISO_PARTITION is not set
CONFIG_PARTITION_TYPE_GUID=y
CONFIG_OF_EMBED=y
@@ -63,7 +63,6 @@ CONFIG_MMC_SDHCI_SNPS=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_CMD_MMC=y
CONFIG_CMD_MMC_RPMB=y
CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_SUPPORT_EMMC_RPMB=y
CONFIG_DM_MTD=y
CONFIG_MTD_SPI_NAND=y
@@ -78,19 +77,14 @@ CONFIG_SPI=y
CONFIG_DESIGNWARE_SPI=y
CONFIG_DESIGNWARE_QSPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_DWC3=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="U-Boot-THEAD"
CONFIG_USB_GADGET_VENDOR_NUM=0x1234
CONFIG_USB_GADGET_PRODUCT_NUM=0x8888
CONFIG_USB_FUNCTION_MASS_STORAGE=y
# CONFIG_SPL_USE_TINY_PRINTF is not set
# CONFIG_EFI_LOADER is not set
# CONFIG_LIGHT_SEC_BOOT is not set
CONFIG_DEFAULT_FDT_FILE="thead/light-lpi4a.dtb"
CONFIG_BOARD_LATE_INIT=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_DM_VIDEO=y
@@ -98,13 +92,11 @@ CONFIG_PHY=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_CMD_BMP=y
CONFIG_CMD_USB=y
CONFIG_VIDEO_BRIDGE=y
CONFIG_DM_PCA953X=y
CONFIG_VIDEO_VS_DPU=y
CONFIG_VIDEO_LCD_ILITEK_ILI9881C=n
CONFIG_VIDEO_LCD_JD9365DA=y
#CONFIG_VIDEO_LCD_CUSTOM_LOGO=y
CONFIG_VIDEO_LCD_ILITEK_ILI9881C=y
CONFIG_VIDEO_LCD_CUSTOM_LOGO=y
CONFIG_VIDEO_DW_DSI_LIGHT=y
CONFIG_VIDEO_DW_DPHY=y
CONFIG_VIDEO_DW_DSI_HOST=y
@@ -113,6 +105,3 @@ CONFIG_PMIC_VOL_INIT=y
CONFIG_DDR_REGU_0V6=600000
CONFIG_DDR_REGU_0V8=800000
CONFIG_DDR_REGU_1V1=1100000
CONFIG_BOARD_RNG_SEED=y
CONFIG_MISC=y
CONFIG_LIGHT_AON_CONF=y

13
configs/light_lpi4a_sec_defconfig
View File

@@ -22,7 +22,6 @@ CONFIG_SYS_PROMPT="C910 Light# "
CONFIG_DDR_LP4X_3733_DUALRANK=y
# CONFIG_DDR_LP4_3733_DUALRANK is not set
CONFIG_DDR_BOARD_CONFIG=y
CONFIG_FIXUP_MEMORY_REGION=y
CONFIG_CMD_BOOT_SLAVE=y
CONFIG_CMD_ERASEENV=y
CONFIG_CMD_GPT=y
@@ -33,6 +32,7 @@ CONFIG_CMD_I2C=y
CONFIG_CMD_MEMTEST=y
CONFIG_DDR_SCAN=y
CONFIG_DDR_PRBS_TEST=n
# CONFIG_DOS_PARTITION is not set
# CONFIG_ISO_PARTITION is not set
CONFIG_PARTITION_TYPE_GUID=y
CONFIG_OF_EMBED=y
@@ -77,9 +77,6 @@ CONFIG_SPI=y
CONFIG_DESIGNWARE_SPI=y
CONFIG_DESIGNWARE_QSPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_DWC3=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="U-Boot-THEAD"
@@ -96,13 +93,11 @@ CONFIG_PHY=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_CMD_BMP=y
CONFIG_CMD_USB=y
CONFIG_VIDEO_BRIDGE=y
CONFIG_DM_PCA953X=y
CONFIG_VIDEO_VS_DPU=y
CONFIG_VIDEO_LCD_ILITEK_ILI9881C=n
CONFIG_VIDEO_LCD_JD9365DA=y
#CONFIG_VIDEO_LCD_CUSTOM_LOGO=y
CONFIG_VIDEO_LCD_ILITEK_ILI9881C=y
CONFIG_VIDEO_LCD_CUSTOM_LOGO=y
CONFIG_VIDEO_DW_DSI_LIGHT=y
CONFIG_VIDEO_DW_DPHY=y
CONFIG_VIDEO_DW_DSI_HOST=y
@@ -111,5 +106,3 @@ CONFIG_PMIC_VOL_INIT=y
CONFIG_DDR_REGU_0V6=600000
CONFIG_DDR_REGU_0V8=800000
CONFIG_DDR_REGU_1V1=1100000
CONFIG_MISC=y
CONFIG_LIGHT_AON_CONF=y

89
configs/light_milkv_meles_defconfig
View File

@@ -1,89 +0,0 @@
CONFIG_RISCV=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_OFFSET=0xe0000
CONFIG_NR_DRAM_BANKS=8
CONFIG_SPL=y
CONFIG_SMP=y
CONFIG_TARGET_LIGHT_C910=y
CONFIG_PMIC_VOL_INIT=y
CONFIG_TARGET_LIGHT_FM_C910_MILKV_MELES=y
CONFIG_DDR_LP4X_3733_SINGLERANK=y
CONFIG_DDR_BOARD_CONFIG=y
CONFIG_ARCH_RV64I=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BUILD_TARGET="u-boot-with-spl.bin"
CONFIG_DEFAULT_FDT_FILE="thead/th1520-milkv-meles.dtb"
CONFIG_BOARD_LATE_INIT=y
CONFIG_DISPLAY_CPUINFO=y
CONFIG_DISPLAY_BOARDINFO=y
# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
CONFIG_SPL_RAM_SUPPORT=y
CONFIG_SPL_RAM_DEVICE=y
CONFIG_SYS_PROMPT="Milk-V Meles# "
CONFIG_CMD_BOOT_SLAVE=y
CONFIG_CMD_ERASEENV=y
CONFIG_CMD_MEMTEST=y
CONFIG_DDR_SCAN=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MTD=y
CONFIG_CMD_SPI=y
CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_CMD_EXT4_WRITE=y
# CONFIG_DOS_PARTITION is not set
# CONFIG_ISO_PARTITION is not set
CONFIG_PARTITION_TYPE_GUID=y
CONFIG_OF_EMBED=y
CONFIG_DEFAULT_DEVICE_TREE="light-milkv-meles"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_SPL_CLK=y
CONFIG_USB_FUNCTION_FASTBOOT=y
CONFIG_UDP_FUNCTION_FASTBOOT=y
CONFIG_FASTBOOT_BUF_ADDR=0x10000000
CONFIG_FASTBOOT_FLASH=y
CONFIG_FASTBOOT_FLASH_MMC_DEV=0
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
CONFIG_DM_GPIO=y
CONFIG_DWAPB_GPIO=y
CONFIG_DM_PCA953X=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_DW=y
# CONFIG_MMC_SPI is not set
CONFIG_SUPPORT_EMMC_RPMB=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_IO_VOLTAGE=y
CONFIG_MMC_UHS_SUPPORT=y
CONFIG_MMC_HS400_SUPPORT=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_SNPS=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_SNPS=y
CONFIG_DM_MTD=y
CONFIG_MTD_SPI_NAND=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_PHY_REALTEK=y
CONFIG_RTL8211E_PINE64_GIGABIT_FIX=y
CONFIG_RTL8211X_PHY_FORCE_MASTER=y
CONFIG_RTL8211F_PHY_FORCE_EEE_RXC_ON=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_PHY=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DESIGNWARE_SPI=y
CONFIG_DESIGNWARE_QSPI=y
CONFIG_USB=y
CONFIG_USB_DWC3=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="U-Boot-THEAD"
CONFIG_USB_GADGET_VENDOR_NUM=0x1234
CONFIG_USB_GADGET_PRODUCT_NUM=0x8888
CONFIG_SYS_WHITE_ON_BLACK=y
# CONFIG_SPL_USE_TINY_PRINTF is not set
CONFIG_OF_LIBFDT_OVERLAY=y
# CONFIG_EFI_LOADER is not set

93
configs/light_milkv_meles_dualrank_defconfig
View File

@@ -1,93 +0,0 @@
CONFIG_RISCV=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_OFFSET=0xe0000
CONFIG_NR_DRAM_BANKS=8
CONFIG_SPL=y
CONFIG_SMP=y
CONFIG_TARGET_LIGHT_C910=y
CONFIG_PMIC_VOL_INIT=y
CONFIG_TARGET_LIGHT_FM_C910_MILKV_MELES=y
CONFIG_DDR_LP4X_3733_DUALRANK=y
CONFIG_DDR_BOARD_CONFIG=y
CONFIG_ARCH_RV64I=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BUILD_TARGET="u-boot-with-spl.bin"
CONFIG_DEFAULT_FDT_FILE="thead/th1520-milkv-meles.dtb"
CONFIG_BOARD_LATE_INIT=y
CONFIG_DISPLAY_CPUINFO=y
CONFIG_DISPLAY_BOARDINFO=y
# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
CONFIG_SPL_RAM_SUPPORT=y
CONFIG_SPL_RAM_DEVICE=y
CONFIG_SYS_PROMPT="Milk-V Meles# "
CONFIG_CMD_BOOT_SLAVE=y
CONFIG_CMD_ERASEENV=y
CONFIG_CMD_MEMTEST=y
CONFIG_DDR_SCAN=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MTD=y
CONFIG_CMD_SPI=y
CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_CMD_EXT4_WRITE=y
# CONFIG_DOS_PARTITION is not set
# CONFIG_ISO_PARTITION is not set
CONFIG_PARTITION_TYPE_GUID=y
CONFIG_OF_EMBED=y
CONFIG_DEFAULT_DEVICE_TREE="light-milkv-meles"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_SPL_CLK=y
CONFIG_USB_FUNCTION_FASTBOOT=y
CONFIG_UDP_FUNCTION_FASTBOOT=y
CONFIG_FASTBOOT_BUF_ADDR=0x10000000
CONFIG_FASTBOOT_FLASH=y
CONFIG_FASTBOOT_FLASH_MMC_DEV=0
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
CONFIG_DM_GPIO=y
CONFIG_DWAPB_GPIO=y
CONFIG_DM_PCA953X=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_DW=y
# CONFIG_MMC_SPI is not set
CONFIG_SUPPORT_EMMC_RPMB=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_IO_VOLTAGE=y
CONFIG_MMC_UHS_SUPPORT=y
CONFIG_MMC_HS400_SUPPORT=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_SNPS=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_SNPS=y
CONFIG_DM_MTD=y
CONFIG_MTD_SPI_NAND=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_PHY_REALTEK=y
CONFIG_RTL8211E_PINE64_GIGABIT_FIX=y
CONFIG_RTL8211X_PHY_FORCE_MASTER=y
CONFIG_RTL8211F_PHY_FORCE_EEE_RXC_ON=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_PHY=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DESIGNWARE_SPI=y
CONFIG_DESIGNWARE_QSPI=y
CONFIG_USB=y
CONFIG_USB_DWC3=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="U-Boot-THEAD"
CONFIG_USB_GADGET_VENDOR_NUM=0x1234
CONFIG_USB_GADGET_PRODUCT_NUM=0x8888
CONFIG_SYS_WHITE_ON_BLACK=y
# CONFIG_SPL_USE_TINY_PRINTF is not set
CONFIG_OF_LIBFDT_OVERLAY=y
# CONFIG_EFI_LOADER is not set
CONFIG_BOARD_RNG_SEED=y
CONFIG_FIXUP_MEMORY_REGION=y
CONFIG_MISC=y
CONFIG_LIGHT_AON_CONF=y

93
configs/light_milkv_meles_singlerank_defconfig
View File

@@ -1,93 +0,0 @@
CONFIG_RISCV=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_OFFSET=0xe0000
CONFIG_NR_DRAM_BANKS=8
CONFIG_SPL=y
CONFIG_SMP=y
CONFIG_TARGET_LIGHT_C910=y
CONFIG_PMIC_VOL_INIT=y
CONFIG_TARGET_LIGHT_FM_C910_MILKV_MELES=y
CONFIG_DDR_LP4X_3733_SINGLERANK=y
CONFIG_DDR_BOARD_CONFIG=y
CONFIG_ARCH_RV64I=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BUILD_TARGET="u-boot-with-spl.bin"
CONFIG_DEFAULT_FDT_FILE="thead/th1520-milkv-meles-4g.dtb"
CONFIG_BOARD_LATE_INIT=y
CONFIG_DISPLAY_CPUINFO=y
CONFIG_DISPLAY_BOARDINFO=y
# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
CONFIG_SPL_RAM_SUPPORT=y
CONFIG_SPL_RAM_DEVICE=y
CONFIG_SYS_PROMPT="Milk-V Meles 4G# "
CONFIG_CMD_BOOT_SLAVE=y
CONFIG_CMD_ERASEENV=y
CONFIG_CMD_MEMTEST=y
CONFIG_DDR_SCAN=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MTD=y
CONFIG_CMD_SPI=y
CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_CMD_EXT4_WRITE=y
# CONFIG_DOS_PARTITION is not set
# CONFIG_ISO_PARTITION is not set
CONFIG_PARTITION_TYPE_GUID=y
CONFIG_OF_EMBED=y
CONFIG_DEFAULT_DEVICE_TREE="light-milkv-meles"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_SPL_CLK=y
CONFIG_USB_FUNCTION_FASTBOOT=y
CONFIG_UDP_FUNCTION_FASTBOOT=y
CONFIG_FASTBOOT_BUF_ADDR=0x10000000
CONFIG_FASTBOOT_FLASH=y
CONFIG_FASTBOOT_FLASH_MMC_DEV=0
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
CONFIG_DM_GPIO=y
CONFIG_DWAPB_GPIO=y
CONFIG_DM_PCA953X=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_DW=y
# CONFIG_MMC_SPI is not set
CONFIG_SUPPORT_EMMC_RPMB=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_IO_VOLTAGE=y
CONFIG_MMC_UHS_SUPPORT=y
CONFIG_MMC_HS400_SUPPORT=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_SNPS=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_SNPS=y
CONFIG_DM_MTD=y
CONFIG_MTD_SPI_NAND=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_PHY_REALTEK=y
CONFIG_RTL8211E_PINE64_GIGABIT_FIX=y
CONFIG_RTL8211X_PHY_FORCE_MASTER=y
CONFIG_RTL8211F_PHY_FORCE_EEE_RXC_ON=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_PHY=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DESIGNWARE_SPI=y
CONFIG_DESIGNWARE_QSPI=y
CONFIG_USB=y
CONFIG_USB_DWC3=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="U-Boot-THEAD"
CONFIG_USB_GADGET_VENDOR_NUM=0x1234
CONFIG_USB_GADGET_PRODUCT_NUM=0x8888
CONFIG_SYS_WHITE_ON_BLACK=y
# CONFIG_SPL_USE_TINY_PRINTF is not set
CONFIG_OF_LIBFDT_OVERLAY=y
# CONFIG_EFI_LOADER is not set
CONFIG_BOARD_RNG_SEED=y
CONFIG_FIXUP_MEMORY_REGION=y
CONFIG_MISC=y
CONFIG_LIGHT_AON_CONF=y

1
configs/tools-only_defconfig
View File

@@ -6,7 +6,6 @@ CONFIG_FIT_SIGNATURE=y
# CONFIG_CMD_BOOTD is not set
# CONFIG_CMD_BOOTM is not set
# CONFIG_CMD_ELF is not set
# CONFIG_CMD_EXTENSION is not set
# CONFIG_CMD_DATE is not set
CONFIG_OF_CONTROL=y
CONFIG_OF_HOSTFILE=y

9
doc/README.pxe
View File

@@ -89,9 +89,6 @@ pxe boot
fdt_addr - the location of a fdt blob. 'fdt_addr' will be passed to bootm
command if it is set and 'fdt_addr_r' is not passed to bootm command.
fdtoverlay_addr_r - location in RAM at which 'pxe boot' will temporarily store
fdt overlay(s) before applying them to the fdt blob stored at 'fdt_addr_r'.
pxe file format
===============
The pxe file format is nearly a subset of the PXELINUX file format; see
@@ -151,12 +148,6 @@ kernel <path> - if this label is chosen, use tftp to retrieve the kernel
It useful for overlay selection in pxe file
(see: doc/uImage.FIT/overlay-fdt-boot.txt)
fdtoverlays <path> [...] - if this label is chosen, use tftp to retrieve the DT
overlay(s) at <path>. it will be temporarily stored at the
address indicated in the fdtoverlay_addr_r environment variable,
and then applied in the load order to the fdt blob stored at the
address indicated in the fdt_addr_r environment variable.
append <string> - use <string> as the kernel command line when booting this
label.

111
doc/usage/extension.rst
View File

@@ -1,111 +0,0 @@
.. SPDX-License-Identifier: GPL-2.0+
.. Copyright 2021, Kory Maincent <kory.maincent@bootlin.com>
U-Boot extension board usage (CONFIG_EXTENSION)
===============================================
Synopsis
--------
::
extension scan
extension list
extension apply <extension number|all>
Description
-----------
The "extension" command proposes a generic U-Boot mechanism to detect
extension boards connected to the HW platform, and apply the appropriate
Device Tree overlays depending on the detected extension boards.
The "extension" command comes with three sub-commands:
- "extension scan" makes the generic code call the board-specific
extension_board_scan() function to retrieve the list of detected
extension boards.
- "extension list" allows to list the detected extension boards.
- "extension apply <number>|all" allows to apply the Device Tree
overlay(s) corresponding to one, or all, extension boards
The latter requires two environment variables to exist:
- extension_overlay_addr: the RAM address where to load the Device
Tree overlays
- extension_overlay_cmd: the U-Boot command to load one overlay.
Indeed, the location and mechanism to load DT overlays is very setup
specific.
In order to enable this mechanism, board-specific code must implement
the extension_board_scan() function that fills in a linked list of
"struct extension", each describing one extension board. In addition,
the board-specific code must select the SUPPORT_EXTENSION_SCAN Kconfig
boolean.
Usage example
-------------
1. Make sure your devicetree is loaded and set as the working fdt tree.
::
=> run loadfdt
=> fdt addr $fdtaddr
2. Prepare the environment variables
::
=> setenv extension_overlay_addr 0x88080000
=> setenv extension_overlay_cmd 'load mmc 0:1 ${extension_overlay_addr} /boot/${extension_overlay_name}'
3. Detect the plugged extension board
::
=> extension scan
4. List the plugged extension board information and the devicetree
overlay name
::
=> extension list
5. Apply the appropriate devicetree overlay
For apply the selected overlay:
::
=> extension apply 0
For apply all the overlays:
::
=> extension apply all
Simple extension_board_scan function example
--------------------------------------------
.. code-block:: c
int extension_board_scan(struct list_head *extension_list)
{
struct extension *extension;
extension = calloc(1, sizeof(struct extension));
snprintf(extension->overlay, sizeof(extension->overlay), "overlay.dtbo");
snprintf(extension->name, sizeof(extension->name), "extension board");
snprintf(extension->owner, sizeof(extension->owner), "sandbox");
snprintf(extension->version, sizeof(extension->version), "1.1");
snprintf(extension->other, sizeof(extension->other), "Extension board information");
list_add_tail(&extension->list, extension_list);
return 1;
}

2
drivers/Kconfig
View File

@@ -130,8 +130,6 @@ source "drivers/w1-eeprom/Kconfig"
source "drivers/watchdog/Kconfig"
source "drivers/mcu/Kconfig"
config PHYS_TO_BUS
bool "Custom physical to bus address mapping"
help

1
drivers/Makefile
View File

@@ -85,7 +85,6 @@ obj-y += misc/
obj-$(CONFIG_MMC) += mmc/
obj-$(CONFIG_NVME) += nvme/
obj-$(CONFIG_PCI_ENDPOINT) += pci_endpoint/
obj-$(CONFIG_DM_POWER_DELIVERY) += power/power_delivery/
obj-y += dfu/
obj-$(CONFIG_PCH) += pch/
obj-y += phy/allwinner/

20
drivers/fastboot/fb_command.c
View File

@@ -310,7 +310,6 @@ static void flash(char *cmd_parameter, char *response)
char cmdbuf[32];
u32 block_cnt;
struct blk_desc *dev_desc;
disk_partition_t info;
int ret = 0;
if (strcmp(cmd_parameter, "uboot") == 0) {
@@ -352,25 +351,8 @@ static void flash(char *cmd_parameter, char *response)
memcpy((void *)LIGHT_TF_FW_ADDR, fastboot_buf_addr, image_size);
} else if ((strcmp(cmd_parameter, TEE_PART_NAME) == 0)) {
memcpy((void *)LIGHT_TEE_FW_ADDR, fastboot_buf_addr, image_size);
} else if ((strcmp(cmd_parameter, "boot") == 0)) {
dev_desc = blk_get_dev("mmc", CONFIG_FASTBOOT_FLASH_MMC_DEV);
if (!dev_desc || dev_desc->type == DEV_TYPE_UNKNOWN) {
fastboot_fail("invalid mmc device", response);
return;
}
/* if fastresume partition exists, earse the old image header */
if(part_get_info_by_name(dev_desc, "fastresume", &info)) {
printf(" find fastresume partition , erase the header:\n");
char * buf = memalign(CONFIG_SYS_CACHELINE_SIZE,4096);
if(!buf) {
printf(" fastresume partition header mem alloc failed\n");
return;
}
memset(buf,0xff,4096);
blk_dwrite(dev_desc, info.start, 4096/info.blksz, buf);
free(buf);
}
}
if(strcmp(cmd_parameter, "uboot") == 0 || (strcmp(cmd_parameter, "fw") == 0) ||
(strcmp(cmd_parameter, "uImage") == 0) || (strcmp(cmd_parameter, "dtb") == 0) ||
(strcmp(cmd_parameter, "rootfs") == 0) || (strcmp(cmd_parameter, "aon") == 0)) {

15
drivers/mcu/Kconfig
View File

@@ -1,15 +0,0 @@
menu "MCU Support"
config DM_MCU
bool "Enable driver model for mcu device support"
depends on DM
help
This adds a simple uclass for mcu device.
config MCU_HC32fX
bool "Enable HC32fX MCU support"
depends on DM_MCU
help
This adds a driver for the HC32fX MCU support.
endmenu

9
drivers/mcu/Makefile
View File

@@ -1,9 +0,0 @@
#
# Copyright (c) 2015 Google, Inc
# Written by Simon Glass <sjg@chromium.org>
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-$(CONFIG_DM_MCU) += mcu-uclass.o
obj-$(CONFIG_MCU_HC32fX) += mcu_hc32fx.o

65
drivers/mcu/mcu-uclass.c
View File

@@ -1,65 +0,0 @@
/*
* Copyright (c) 2015 Google, Inc
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <dm.h>
#include <errno.h>
#include <mcu/mcu-uclass.h>
#include <dm/root.h>
#include <dm/uclass-internal.h>
int _mcu_shutdown(struct udevice *dev)
{
struct mcu_ops *ops = dev_get_driver_ops(dev);
if (!ops->shutdown)
return -ENOSYS;
return ops->shutdown(dev);
}
int _mcu_poweron(struct udevice *dev)
{
struct mcu_ops *ops = dev_get_driver_ops(dev);
if (!ops->poweron)
return -ENOSYS;
return ops->poweron(dev);
}
int mcu_poweron(void)
{
struct udevice *mcu;
int ret;
ret = uclass_get_device(UCLASS_MCU, 0, &mcu);
if (ret) {
printf("Get UCLASS_MCU failed, ret=%d\n", ret);
return ret;
}
return _mcu_poweron(mcu);
}
int mcu_shutdown(void)
{
struct udevice *mcu;
int ret;
ret = uclass_get_device(UCLASS_MCU, 0, &mcu);
if (ret) {
printf("Get charge display failed, ret=%d\n", ret);
return ret;
}
return _mcu_shutdown(mcu);
}
UCLASS_DRIVER(mcu) = {
.id = UCLASS_MCU,
.name = "mcu",
};

97
drivers/mcu/mcu_hc32fx.c
View File

@@ -1,97 +0,0 @@
#include <common.h>
#include <dm.h>
#include <errno.h>
#include <mcu/mcu-uclass.h>
#include <dm/lists.h>
DECLARE_GLOBAL_DATA_PTR;
#define HC32FX_POWEROFF_20 0x20
#define HC32FX_POWERON_30 0x30
#define POWER_OFF 0x55
#define POWER_ON 0x01
struct hc32fx_info {
struct udevice *dev;
};
static u8 hc32fx_read(struct hc32fx_info *hc32fx, u8 reg)
{
u8 val;
int ret;
ret = dm_i2c_read(hc32fx->dev, reg, &val, 1);
if (ret) {
printf("write error to device: %p register: %#x!",
hc32fx->dev, reg);
return ret;
}
return val;
}
static int hc32fx_write(struct hc32fx_info *hc32fx, u8 reg, u8 val)
{
int ret;
ret = dm_i2c_write(hc32fx->dev, reg, &val, 1);
if (ret) {
printf("write error to device: %p register: %#x!",
hc32fx->dev, reg);
return ret;
}
return 0;
}
static int mcu_hc32fx_poweron(struct udevice *dev)
{
struct hc32fx_info *hc32fx = dev_get_priv(dev);
int ret;
ret = hc32fx_write(hc32fx, HC32FX_POWERON_30, POWER_ON);
if(ret)
printf("set mcu POWERON fail\n");
return ret;
}
static int mcu_hc32fx_shutdown(struct udevice *dev)
{
struct hc32fx_info *hc32fx = dev_get_priv(dev);
int ret;
ret = hc32fx_write(hc32fx, HC32FX_POWEROFF_20, POWER_OFF);
if(ret)
printf("set mcu POWEROFF fail\n");
return ret;
}
static int mcu_gpio_probe(struct udevice *dev)
{
struct hc32fx_info *priv = dev_get_priv(dev);
priv->dev = dev;
return 0;
}
static const struct mcu_ops mcu_hc32fx_ops = {
.poweron = mcu_hc32fx_poweron,
.shutdown = mcu_hc32fx_shutdown,
};
static const struct udevice_id hc32fx_ops_ids[] = {
{ .compatible = "mcu_hc32fx" },
{ }
};
U_BOOT_DRIVER(mcu_gpio) = {
.name = "hc32fx-mcu",
.id = UCLASS_MCU,
.of_match = hc32fx_ops_ids,
.ops = &mcu_hc32fx_ops,
.priv_auto_alloc_size = sizeof(struct hc32fx_info),
.probe = mcu_gpio_probe,
};

6
drivers/misc/Kconfig
View File

@@ -439,10 +439,4 @@ config K3_AVS0
optimized voltage from the efuse, so that it can be programmed
to the PMIC on board.
config LIGHT_AON_CONF
bool "Light aon config support"
depends on MISC
help
Select this to enable aon config by dts.
endmenu

1
drivers/misc/Makefile
View File

@@ -68,4 +68,3 @@ obj-$(CONFIG_WINBOND_W83627) += winbond_w83627.o
obj-$(CONFIG_JZ4780_EFUSE) += jz4780_efuse.o
obj-$(CONFIG_MICROCHIP_FLEXCOM) += microchip_flexcom.o
obj-$(CONFIG_K3_AVS0) += k3_avs.o
obj-$(CONFIG_LIGHT_AON_CONF) += light_regu.o

1161
drivers/misc/light_regu.c
View File

File diff suppressed because it is too large Load Diff

271
drivers/misc/light_regu.h
View File

@@ -1,271 +0,0 @@
#ifndef __LIGHT_REGU_H__
#define __LIGHT_REGU_H__
typedef enum
{
SOC_DVDD18_AON, /*da9063: ldo-3 */
SOC_AVDD33_USB3, /*da9063: ldo-9 */
SOC_DVDD08_AON, /*da9063: ldo-2 */
SOC_APCPU_DVDD_DVDDM, /*da9063: vbcore1 & vbcore2*/
SOC_DVDD08_DDR, /*da9063: buckperi */
SOC_VDD_DDR_1V8, /*da9063: ldo-4 */
SOC_VDD_DDR_1V1, /*da9063: buckmem & buckio */
SOC_VDD_DDR_0V6, /*da9063: buckpro */
SOC_DVDD18_AP, /*da9063: ldo-11 */
SOC_DVDD08_AP, /*da9121: da9121_ex */
SOC_AVDD08_MIPI_HDMI, /*da9063: ldo-1 */
SOC_AVDD18_MIPI_HDMI, /*da9063: ldo-5 */
SOC_DVDD33_EMMC, /*da9063: ldo-10 */
SOC_DVDD18_EMMC, /*slg51000:ldo-3 */
SOC_DOVDD18_SCAN, /*da9063: ldo-6 */
SOC_VEXT_2V8, /*da9063: ldo-7 */
SOC_DVDD12_SCAN, /*da9063: ldo-8 */
SOC_AVDD28_SCAN_EN, /*da9063: gpio-4,SGM2019-ADJ */
SOC_AVDD28_RGB, /*slg51000:ldo-1 */
SOC_DOVDD18_RGB, /*slg51000:ldo-4 */
SOC_DVDD12_RGB, /*slg51000:ldo-5 */
SOC_AVDD25_IR, /*slg51000:ldo-2 */
SOC_DOVDD18_IR, /*slg51000:ldo-7 */
SOC_DVDD12_IR, /*slg51000:ldo-6 */
SOC_ADC_VREF,
SOC_LCD0_EN,
SOC_VEXT_1V8,
SOC_REGU_INVALID = 0xFF
} soc_virtual_id_en;
#define REGU_DTS_NAME "light-regu-reg"
#define AON_CONF_NAME "aon_pmic_config"
#define PMIC_DEV_DTS_NAME "pmic-dev"
#define PMIC_PARENT_CTRL_NAME "pmic_ctrl_info"
#define REGU_ID_CONF_NAME "regu_config"
#define REGU_ID_NAME "regu_id"
#define COUPLING_ID_INFO_NAME "coupling_info"
#define PMIC_DEV_ENABLE_WDT (1U << 0)
#define PMIC_DEV_ENABLE_ERR_IO (1U << 1)
#define PMIC_DEV_ENABLE_LPM_IO (1U << 2)
#define HW_ID_NO_SOFT_AUTO_ON (0xff)
#define HW_ID_NO_SOFT_AUTO_OFF (0xff)
#define HW_ID_INVALID (0xff)
#define PMIC_ID_INVALID (0xff)
#define REGU_SUB_ID_INVALID (0xff)
#define REGU_EXT_ID_NAME_LEN 30
#define PMIC_DEV_NAME_LEN 20
#define PMIC_DEV_VERSION_LEN 20
#define PMIC_MAX_HW_ID_NUM 3
#define PMIC_MAX_COUPLING_NUM 3
#define AON_WAKEUP_BY_GPIO (1 << 0)
#define AON_WAKEUP_BY_RTC (1 << 1)
#define AON_CONFIG_MAGIC "AON_CONFIG"
#define UBOOT_CONFIG_MAGIC "UBOOT_SET"
#define AON_CONFIG_VERSION "1.0.0"
typedef enum
{
HW_ID_ACTIVATE_HIGH = 0U,
HW_ID_ACTIVATE_LOW = 1U,
} hw_activate_status_en;
typedef struct __packed
{
uint8_t pmic_id;
uint8_t io_hw_id;
uint8_t activate_status;
} pmic_parent_hw_io_ctrl_info_t;
typedef struct __packed
{
uint8_t on_order;
uint8_t on_delay_ms;
uint32_t init_target_uv;
} regu_soft_power_ctrl_on_t;
typedef struct __packed
{
uint8_t off_order;
uint8_t off_delay_ms;
} regu_soft_power_ctrl_off_t;
typedef struct __packed
{
regu_soft_power_ctrl_on_t on_info;
regu_soft_power_ctrl_off_t off_info;
} regu_soft_power_ctrl_t;
typedef struct __packed
{
uint8_t id0;
uint8_t id1;
int8_t max_spread; // mv/10
int8_t min_spread; // mv/10
} coupling_desc_t;
typedef enum
{
GPIO_IRQ_MODE_RISING_EDGE = 0, ///< Interrupt mode for rising edge
GPIO_IRQ_MODE_FALLING_EDGE, ///< Interrupt mode for falling edge
GPIO_IRQ_MODE_BOTH_EDGE, ///< Interrupt mode for both edge
GPIO_IRQ_MODE_LOW_LEVEL, ///< Interrupt mode for low level
GPIO_IRQ_MODE_HIGH_LEVEL, ///< Interrupt mode for high level
} csi_gpio_irq_mode_t;
typedef enum
{
IIC_ADDRESS_7BIT = 0U, ///< 7-bit address mode
IIC_ADDRESS_10BIT ///< 10-bit address mode
} csi_iic_addr_mode_t;
typedef enum
{
IIC_BUS_SPEED_STANDARD = 0U, ///< Standard Speed (<=100kHz)
IIC_BUS_SPEED_FAST, ///< Fast Speed (<=400kHz)
IIC_BUS_SPEED_FAST_PLUS, ///< Fast plus Speed (<= 1MHz)
IIC_BUS_SPEED_HIGH ///< High Speed (<=3.4MHz)
} csi_iic_speed_t;
typedef struct __packed
{
uint8_t pmic_id;
uint8_t hw_id;
uint8_t benable;
pmic_parent_hw_io_ctrl_info_t parent_hw_info;
regu_soft_power_ctrl_t soft_power_ctrl_info;
} pmic_hw_info_t;
typedef struct __packed
{
coupling_desc_t coupling_list[PMIC_MAX_COUPLING_NUM];
pmic_hw_info_t id[PMIC_MAX_HW_ID_NUM]; ///< sub id1 for single-rail or first src of dual-rail
} pmic_hw_id_t;
typedef struct __packed
{
uint8_t regu_ext_id; ///< virtual global regulator id
char regu_ext_id_name[REGU_EXT_ID_NAME_LEN]; ///< vitual regu-id name
pmic_hw_id_t sub; ///< sub id set for dual-rail/single-rail regulator
} csi_regu_id_t;
typedef enum
{
PMIC_CTRL_BY_AON_GPIO = 0U,
PMIC_CTRL_BY_PMIC_GPIO = 1U,
PMIC_CTRL_BY_NOTHINTG = 0xFF,
} pmic_ctrl_info_en;
typedef struct __packed
{
uint8_t gpio_port;
uint8_t pin;
uint8_t activate_status;
} pmic_ctrl_by_aon_info_t;
typedef struct __packed
{
uint8_t pmic_id;
uint8_t io_hw_id;
uint8_t activate_status;
} pmic_ctrl_by_pmic_info_t;
typedef struct __packed
{
uint8_t pmic_ctrl_type;
union
{
pmic_ctrl_by_aon_info_t aon_io;
pmic_ctrl_by_pmic_info_t pmic_io;
} info;
} pmic_parent_ctrl_info_t;
typedef struct __packed
{
uint8_t gpio_port;
uint8_t pin;
uint8_t trigger_mode;
} pmic_interrupt_io_info_t;
typedef struct __packed
{
char device_name[PMIC_DEV_NAME_LEN];
char version_name[PMIC_DEV_VERSION_LEN];
uint8_t pmic_id;
uint8_t addr1;
uint8_t addr2;
uint8_t flag; /*support wdt|errio| lpm io*/
uint8_t slew_rate;
uint32_t wdt_len;
pmic_interrupt_io_info_t err_io_info;
pmic_interrupt_io_info_t lpm_io_info;
pmic_parent_ctrl_info_t ctrl_info;
} pmic_dev_info_t;
typedef struct
{
soc_virtual_id_en id;
char virtual_id_name[REGU_EXT_ID_NAME_LEN];
int min_uv;
int max_uv;
} soc_virtual_id_t;
typedef struct
{
int regu_num;
soc_virtual_id_t *regu_list;
} virtual_regu_list_t;
typedef struct
{
int pmic_num;
pmic_dev_info_t *pmic_list;
} pmic_dev_list_t;
typedef struct
{
int regu_id_num;
csi_regu_id_t *regu_id_list;
} regu_id_list_t;
typedef struct __packed
{
uint8_t iic_id; ///< iic id
uint8_t addr_mode; ///< iic addr_mode ---> csi_iic_addr_mode_t
uint8_t speed; ///< iic speed type ---> csi_iic_speed_t
uint8_t reserved[1];
} csi_pmic_if_config_t;
struct mic_regu_platdata
{
const char *name;
uint32_t wakeup_flag;
csi_pmic_if_config_t iic_config;
virtual_regu_list_t regu_list;
pmic_dev_list_t pmic_list;
regu_id_list_t regu_id_list;
};
typedef struct __packed
{
csi_pmic_if_config_t iic_config;
uint8_t pmic_dev_num;
uint8_t regu_num;
uint32_t pmic_dev_list_offset;
uint32_t regu_id_list_offset;
} aon_pmic_config_t;
typedef struct __packed
{
const char magic[11];
const char version[11];
const char uboot_set_magic[11];
uint8_t max_hw_id_num;
uint64_t aon_config_partition_size;
uint32_t wakeup_flag;
aon_pmic_config_t aon_pmic;
} aon_config_t;
#endif

1
drivers/misc/misc-uclass.c
View File

@@ -13,6 +13,7 @@
* general classes. A set of generic read, write and ioctl methods may
* be used to access the device.
*/
int misc_read(struct udevice *dev, int offset, void *buf, int size)
{
const struct misc_ops *ops = device_get_ops(dev);

4
drivers/mmc/sdhci.c
View File

@@ -38,7 +38,9 @@ static void sdhci_reset(struct sdhci_host *host, u8 mask)
timeout--;
udelay(1000);
}
#ifdef CONFIG_TARGET_LIGHT_C910
mdelay(50);
#endif
}
static void sdhci_cmd_done(struct sdhci_host *host, struct mmc_cmd *cmd)

19
drivers/power/Kconfig
View File

@@ -2,22 +2,10 @@ menu "Power"
source "drivers/power/domain/Kconfig"
source "drivers/power/fuel_gauge/Kconfig"
source "drivers/power/pmic/Kconfig"
source "drivers/power/regulator/Kconfig"
source "drivers/power/charge/Kconfig"
source "drivers/power/power_delivery/Kconfig"
config DM_CHARGE_DISPLAY
bool "Enable driver model for charge display support"
depends on DM
help
This adds a simple uclass for charge display.
choice
prompt "Select Sunxi PMIC Variant"
depends on ARCH_SUNXI
@@ -84,13 +72,6 @@ config SY8106A_POWER
endchoice
config CHARGE_ANIMATION
bool "Enable charge animation"
depends on DM_CHARGE_DISPLAY && DM_FUEL_GAUGE
select ARM_CPU_SUSPEND
help
This adds a simple function for charge animation display.
config AXP_DCDC1_VOLT
int "axp pmic dcdc1 voltage"
depends on AXP221_POWER || AXP809_POWER || AXP818_POWER

4
drivers/power/Makefile
View File

@@ -3,14 +3,11 @@
# Copyright (c) 2009 Wind River Systems, Inc.
# Tom Rix <Tom.Rix at windriver.com>
obj-$(CONFIG_DM_CHARGE_DISPLAY) += charge-display-uclass.o
obj-$(CONFIG_AXP152_POWER) += axp152.o
obj-$(CONFIG_AXP209_POWER) += axp209.o
obj-$(CONFIG_AXP221_POWER) += axp221.o
obj-$(CONFIG_AXP809_POWER) += axp809.o
obj-$(CONFIG_AXP818_POWER) += axp818.o
obj-$(CONFIG_CHARGE_ANIMATION) += charge_animation.o
obj-$(CONFIG_EXYNOS_TMU) += exynos-tmu.o
obj-$(CONFIG_FTPMU010_POWER) += ftpmu010.o
obj-$(CONFIG_SY8106A_POWER) += sy8106a.o
@@ -23,4 +20,3 @@ obj-$(CONFIG_DIALOG_POWER) += power_dialog.o
obj-$(CONFIG_POWER_FSL) += power_fsl.o
obj-$(CONFIG_POWER_I2C) += power_i2c.o
obj-$(CONFIG_POWER_SPI) += power_spi.o

40
drivers/power/charge-display-uclass.c
View File

@@ -1,40 +0,0 @@
/*
* (C) Copyright 2017 Rockchip Electronics Co., Ltd
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <command.h>
#include <common.h>
#include <dm.h>
#include <power/charge_display.h>
int charge_display_show(struct udevice *dev)
{
const struct dm_charge_display_ops *ops = dev_get_driver_ops(dev);
if (!ops || !ops->show)
return -ENOSYS;
return ops->show(dev);
}
int charge_display(void)
{
struct udevice *dev;
struct udevice *fg_dev;
int ret;
ret = uclass_get_device(UCLASS_CHARGE_DISPLAY, 0, &dev);
if (ret) {
debug("Get charge display failed, ret=%d\n", ret);
return ret;
}
return charge_display_show(dev);
}
UCLASS_DRIVER(charge_display) = {
.id = UCLASS_CHARGE_DISPLAY,
.name = "charge_display",
};

5
drivers/power/charge/Kconfig
View File

@@ -1,5 +0,0 @@
config CHARGER_BQ25700
bool "BQ25700 charger support"
depends on DM_FUEL_GAUGE
help
This adds support for BQ25700 charger support.

7
drivers/power/charge/Makefile
View File

@@ -1,7 +0,0 @@
#
# Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-$(CONFIG_CHARGER_BQ25700) += bq25700_charger.o

334
drivers/power/charge/bq25700_charger.c
View File

@@ -1,334 +0,0 @@
/*
* (C) Copyright 2019 Fuzhou Rockchip Electronics Co., Ltd
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/gpio.h>
#include <dm/device.h>
#include <dm/uclass.h>
#include <power/fuel_gauge.h>
#include <power/pmic.h>
#include <power/power_delivery/power_delivery.h>
DECLARE_GLOBAL_DATA_PTR;
#define BQ25700_ID 0x25700
#define BQ25703_ID 0x25703
#define COMPAT_BQ25700 "ti,bq25700"
#define COMPAT_BQ25703 "ti,bq25703"
#define BQ25700_I2C_SPEED 100000
#define BQ25700_CHARGE_CURRENT_1500MA 0x5C0
#define BQ25700_SDP_INPUT_CURRENT_500MA 0xA00
#define BQ25700_DCP_INPUT_CURRENT_1500MA 0x1E00
#define BQ25700_DCP_INPUT_CURRENT_2000MA 0x2800
#define BQ25700_DCP_INPUT_CURRENT_3000MA 0x3C00
#define WATCHDOG_ENSABLE (0x03 << 13)
#define BQ25700_CHARGEOPTION0_REG 0x12
#define BQ25700_CHARGECURREN_REG 0x14
#define BQ25700_CHARGERSTAUS_REG 0x20
#define BQ25700_INPUTVOLTAGE_REG 0x3D
#define BQ25700_INPUTCURREN_REG 0x3F
#define BQ25703_CHARGEOPTION0_REG 0x00
#define BQ25703_CHARGECURREN_REG 0x02
#define BQ25703_CHARGERSTAUS_REG 0x20
#define BQ25703_INPUTVOLTAGE_REG 0x0A
#define BQ25703_INPUTCURREN_REG 0x0E
#define PD_MUN 2
#define TYPEC0_I2C "i2c@ffe7f20000"
#define TYPEC1_I2C "i2c@ffe7f24000"
enum bq25700_table_ids {
/* range tables */
TBL_ICHG,
TBL_CHGMAX,
TBL_INPUTVOL,
TBL_INPUTCUR,
TBL_SYSVMIN,
TBL_OTGVOL,
TBL_OTGCUR,
TBL_EXTCON,
};
struct bq25700 {
struct udevice *dev;
u32 ichg;
u32 chip_id;
struct udevice *pd[PD_MUN];
};
struct bq25700_range {
u32 min;
u32 max;
u32 step;
};
static int bq25700_read(struct bq25700 *charger, uint reg)
{
u16 val;
int ret;
ret = dm_i2c_read(charger->dev, reg, (u8 *)&val, 2);
if (ret) {
printf("write error to device: %p register: %#x!",
charger->dev, reg);
return ret;
}
return val;
}
static int bq25700_write(struct bq25700 *charger, uint reg, u16 val)
{
int ret;
ret = dm_i2c_write(charger->dev, reg, (u8 *)&val, 2);
if (ret) {
printf("write error to device: %p register: %#x!",
charger->dev, reg);
return ret;
}
return 0;
}
static const union {
struct bq25700_range rt;
} bq25700_tables[] = {
/* range tables */
[TBL_ICHG] = {.rt = {0, 8128000, 64000}},
/* uV */
[TBL_CHGMAX] = {.rt = {0, 19200000, 16000}},
/* uV max charge voltage*/
[TBL_INPUTVOL] = {.rt = {3200000, 19520000, 64000}},
/* uV input charge voltage*/
[TBL_INPUTCUR] = {.rt = {0, 6350000, 50000}},
/*uA input current*/
[TBL_SYSVMIN] = {.rt = {1024000, 16182000, 256000}},
/* uV min system voltage*/
[TBL_OTGVOL] = {.rt = {4480000, 20800000, 64000}},
/*uV OTG volage*/
[TBL_OTGCUR] = {.rt = {0, 6350000, 50000}},
};
static u32 bq25700_find_idx(u32 value, enum bq25700_table_ids id)
{
const struct bq25700_range *rtbl = &bq25700_tables[id].rt;
u32 rtbl_size;
u32 idx;
rtbl_size = (rtbl->max - rtbl->min) / rtbl->step + 1;
for (idx = 1;
idx < rtbl_size && (idx * rtbl->step + rtbl->min <= value);
idx++)
;
return idx - 1;
}
static bool bq25700_charger_status(struct bq25700 *charger)
{
int state_of_charger;
u16 value;
value = bq25700_read(charger, BQ25700_CHARGERSTAUS_REG);
state_of_charger = value >> 15;
return state_of_charger;
}
static bool bq25703_charger_status(struct bq25700 *charger)
{
int state_of_charger;
u16 value;
value = bq25700_read(charger, BQ25703_CHARGERSTAUS_REG);
state_of_charger = value >> 15;
return state_of_charger;
}
static bool bq257xx_charger_status(struct udevice *dev)
{
struct bq25700 *charger = dev_get_priv(dev);
if (charger->chip_id == BQ25700_ID)
return bq25700_charger_status(charger);
else
return bq25703_charger_status(charger);
}
static int bq25700_charger_capability(struct udevice *dev)
{
return FG_CAP_CHARGER;
}
static int bq25700_get_usb_type(void)
{
#ifdef CONFIG_PHY_ROCKCHIP_INNO_USB2
return rockchip_chg_get_type();
#else
return 0;
#endif
}
static int bq25700_get_pd_output_val(struct bq25700 *charger,
int *vol, int *cur)
{
struct power_delivery_data pd_data;
int ret;
if (!charger->pd[0] && !charger->pd[1]) {
return -EINVAL;
}
memset(&pd_data, 0, sizeof(pd_data));
int i = 0;
for (i = 0; i < PD_MUN; i++) {
if (!charger->pd[i]) {
continue;
}
ret = power_delivery_get_data(charger->pd[i], &pd_data);
if (ret) {
continue;
}
if (!pd_data.online || !pd_data.voltage || !pd_data.current) {
continue;
}
*vol = pd_data.voltage;
*cur = pd_data.current;
printf("voltage is %d current is %d\n", *vol, *cur);
goto end;
}
return -EINVAL;
end:
return 0;
}
static void bq25703_charger_current_init(struct bq25700 *charger)
{
u16 charge_current = BQ25700_CHARGE_CURRENT_1500MA;
u16 sdp_inputcurrent = BQ25700_SDP_INPUT_CURRENT_500MA;
u16 dcp_inputcurrent = BQ25700_DCP_INPUT_CURRENT_1500MA;
int pd_inputvol, pd_inputcurrent;
u16 vol_idx = 0, cur_idx;
u16 temp;
temp = bq25700_read(charger, BQ25703_CHARGEOPTION0_REG);
temp &= (~WATCHDOG_ENSABLE);
bq25700_write(charger, BQ25703_CHARGEOPTION0_REG, temp);
if (!bq25700_get_pd_output_val(charger, &pd_inputvol,
&pd_inputcurrent)) {
if (pd_inputvol > 5000000) {
vol_idx = bq25700_find_idx(pd_inputvol - 1280000 - 3200000,
TBL_INPUTVOL);
vol_idx = vol_idx << 6;
}
cur_idx = bq25700_find_idx(pd_inputcurrent,
TBL_INPUTCUR);
cur_idx = cur_idx << 8;
if (pd_inputcurrent != 0)
{
bq25700_write(charger, BQ25703_INPUTCURREN_REG,
cur_idx);
if (vol_idx)
bq25700_write(charger, BQ25703_INPUTVOLTAGE_REG,
vol_idx);
charge_current = bq25700_find_idx(pd_inputcurrent,
TBL_ICHG);
charge_current = charge_current << 6;
}
} else {
bq25700_write(charger, BQ25703_INPUTCURREN_REG,
dcp_inputcurrent);
}
if (bq25703_charger_status(charger)) {
bq25700_write(charger, BQ25703_CHARGECURREN_REG,
charge_current);
}
}
static int bq25700_ofdata_to_platdata(struct udevice *dev)
{
struct bq25700 *charger = dev_get_priv(dev);
const void *blob = gd->fdt_blob;
int node, node1;
charger->dev = dev;
node = fdt_node_offset_by_compatible(blob, 0, COMPAT_BQ25700);
node1 = fdt_node_offset_by_compatible(blob, 0, COMPAT_BQ25703);
if ((node < 0) && (node1 < 0)) {
printf("Can't find dts node for charger bq25700\n");
return -ENODEV;
}
if (node < 0) {
node = node1;
charger->chip_id = BQ25703_ID;
} else {
charger->chip_id = BQ25700_ID;
}
return 0;
}
static int bq25700_probe(struct udevice *dev)
{
struct bq25700 *charger = dev_get_priv(dev);
int ret;
struct udevice *pd_tmp;
struct udevice *dev_tmp;
for (uclass_first_device(UCLASS_PD, &pd_tmp);
pd_tmp;
uclass_next_device(&pd_tmp))
{
dev_tmp = dev_get_parent(pd_tmp);
if (!strncmp(TYPEC0_I2C, dev_tmp->name, strlen(TYPEC0_I2C))) { // Ensure that typec0 has the highest priority
charger->pd[0] = pd_tmp;
} else if (!strncmp(TYPEC1_I2C, dev_tmp->name, strlen(TYPEC1_I2C))) {
charger->pd[1] = pd_tmp;
}
}
if (charger->chip_id == BQ25703_ID) {
bq25703_charger_current_init(charger);
}
return 0;
}
static const struct udevice_id charger_ids[] = {
{.compatible = "ti,bq25700"},
{.compatible = "ti,bq25703"},
{},
{ },
};
static struct dm_fuel_gauge_ops charger_ops = {
.get_chrg_online = bq257xx_charger_status,
.capability = bq25700_charger_capability,
};
U_BOOT_DRIVER(bq25700_charger) = {
.name = "bq25700_charger",
.id = UCLASS_FG,
.probe = bq25700_probe,
.of_match = charger_ids,
.ops = &charger_ops,
.ofdata_to_platdata = bq25700_ofdata_to_platdata,
.priv_auto_alloc_size = sizeof(struct bq25700),
};

366
drivers/power/charge_animation.c
View File

@@ -1,366 +0,0 @@
/*
* (C) Copyright 2017 Rockchip Electronics Co., Ltd
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <asm/io.h>
#include <asm/gpio.h>
#include <common.h>
#include <console.h>
#include <dm.h>
#include <errno.h>
#include <led.h>
#include <rtc.h>
#include <pwm.h>
#include <power/charge_display.h>
#include <power/charge_animation.h>
#include <power/fuel_gauge.h>
#include <power/pmic.h>
#include <mcu/mcu-uclass.h>
#ifdef CONFIG_IRQ
#include <irq-generic.h>
#include <rk_timer_irq.h>
#endif
DECLARE_GLOBAL_DATA_PTR;
#define IMAGE_RECALC_IDX -1
#define IMAGE_SOC_100_IDX(n) ((n) - 2)
#define IMAGE_LOWPOWER_IDX(n) ((n) - 1)
#define SYSTEM_SUSPEND_DELAY_MS 5000
#define FUEL_GAUGE_POLL_MS 1000
#define LED_CHARGING_NAME "battery_charging"
#define LED_CHARGING_FULL_NAME "battery_full"
#define LED_CHARGING_START_NAME "battery_start"
struct charge_image {
const char *name;
int soc;
int period; /* ms */
};
struct charge_animation_priv {
struct udevice *fg;
struct udevice *charger;
struct udevice *mcu;
#ifdef CONFIG_LED
struct udevice *led_charging;
struct udevice *led_full;
struct udevice *led_start;
#endif
const struct charge_image *image;
int image_num;
int auto_wakeup_key_state;
ulong auto_screen_off_timeout; /* ms */
ulong suspend_delay_timeout; /* ms */
};
struct gpio_desc powerkey_gpio;
static int leds_switch = 0;
#ifdef CONFIG_LED
static int leds_update(struct udevice *dev, int soc)
{
struct charge_animation_priv *priv = dev_get_priv(dev);
static int old_soc = -1;
int ret, ledst;
if (old_soc == soc)
return 0;
old_soc = soc;
if (priv->led_charging) {
ledst = (soc < 100) ? LEDST_ON : LEDST_OFF;
ret = led_set_state(priv->led_charging, ledst);
if (ret) {
printf("set charging led %s failed, ret=%d\n",
(ledst == LEDST_ON) ? "ON" : "OFF", ret);
return ret;
}
}
if (priv->led_full) {
ledst = (soc == 100) ? LEDST_ON : LEDST_OFF;
ret = led_set_state(priv->led_full, ledst);
if (ret) {
printf("set charging full led %s failed, ret=%d\n",
ledst == LEDST_ON ? "ON" : "OFF", ret);
return ret;
}
}
return 0;
}
static int leds_charge_on(struct udevice *dev, int soc)
{
struct charge_animation_priv *priv = dev_get_priv(dev);
int ret, ledst;
ledst = LEDST_ON;
ret = led_set_state(priv->led_full, ledst);
if (ret) {
printf("set charging full led %s failed, ret=%d\n",
ledst == LEDST_ON ? "ON" : "OFF", ret);
return ret;
}
return 0;
}
static int leds_charge_off(struct udevice *dev, int soc)
{
struct charge_animation_priv *priv = dev_get_priv(dev);
int ret, ledst;
ledst = LEDST_OFF;
ret = led_set_state(priv->led_charging, ledst);
if (ret) {
printf("set charging full led %s failed, ret=%d\n",
ledst == LEDST_ON ? "ON" : "OFF", ret);
return ret;
}
ret = led_set_state(priv->led_full, ledst);
if (ret) {
printf("set charging full led %s failed, ret=%d\n",
ledst == LEDST_ON ? "ON" : "OFF", ret);
return ret;
}
return 0;
}
static int leds_charge_update(struct udevice *dev, int soc)
{
struct charge_animation_priv *priv = dev_get_priv(dev);
int ret, ledst;
if (leds_switch > 5){
leds_charge_on(dev, soc);
} else {
leds_charge_off(dev, soc);
}
leds_switch++;
if (leds_switch > 10)
leds_switch = 0;
return 0;
}
#else
static int leds_update(struct udevice *dev, int soc) { return 0; }
static int leds_charge_on(struct udevice *dev, int soc) { return 0; }
static int leds_charge_off(struct udevice *dev, int soc) { return 0; }
static int leds_charge_update(struct udevice *dev, int soc) { return 0; }
#endif
static int charge_animation_ofdata_to_platdata(struct udevice *dev)
{
struct charge_animation_pdata *pdata = dev_get_platdata(dev);
pdata->low_power_voltage =
dev_read_u32_default(dev, "uboot-low-power-voltage", 0);
return 0;
}
static int fg_charger_get_chrg_online(struct udevice *dev)
{
struct charge_animation_priv *priv = dev_get_priv(dev);
struct udevice *charger;
charger = priv->charger ? : priv->fg;
return fuel_gauge_get_chrg_online(charger);
}
static int get_reboot_state(void){
const char *var_name = "battery_charge";
char *value = env_get(var_name);
if (value)
if (strcmp(value, "0") == 0) {
env_set(var_name, "1");
env_save();
return 0;
}
env_set(var_name, "1");
env_save();
return 1;
}
static int charge_animation_show(struct udevice *dev)
{
int soc, voltage, ret, charging = 0;
struct charge_animation_priv *priv = dev_get_priv(dev);
struct charge_animation_pdata *pdata = dev_get_platdata(dev);
struct udevice *fg = priv->fg;
struct udevice *mcu = priv->mcu;
voltage = fuel_gauge_get_voltage(fg);
if (voltage < 0)
return -EINVAL;
while (voltage < pdata->low_power_voltage + 50) {
soc = fuel_gauge_update_get_soc(fg);
if (soc < 0 || soc > 100) {
printf("get soc failed: %d\n", soc);
continue;
} else if (soc >= 1) {
printf("soc is: %d\n", soc);
break;
}
voltage = fuel_gauge_get_voltage(fg);
if (voltage < 0) {
printf("get voltage failed: %d\n", voltage);
continue;
}
ret = leds_update(dev, soc);
if (ret)
printf("update led failed: %d\n", ret);
printf("soc is: %d voltage is :%d\n", soc, voltage);
charging = fg_charger_get_chrg_online(dev);
if (charging <= 0) {
mcu_shutdown(); // shutdown system power
}
mdelay(100);
};
leds_charge_off(dev, soc);
ret = get_reboot_state();
charging = fg_charger_get_chrg_online(dev);
if (!(charging <= 0) && ret != 0)
while(1){
ret = dm_gpio_get_value(&powerkey_gpio);
if (ret == 0){
break;
}
charging = fg_charger_get_chrg_online(dev);
if (charging <= 0) {
mcu_shutdown(); // shutdown system power
}
soc = fuel_gauge_update_get_soc(fg);
if (soc == 100){
leds_charge_on(dev, soc);
}else if (soc < 100){
leds_charge_update(dev, soc);
}
mdelay(300);
}
leds_charge_off(dev, soc);
ret = led_set_state(priv->led_start, LEDST_ON);
if (!ret)
printf("Found Charging-Start LED\n");
return 0;
}
static int fg_charger_get_device(struct udevice **fuel_gauge,
struct udevice **charger)
{
struct udevice *dev;
struct uclass *uc;
int ret, cap;
*fuel_gauge = NULL,
*charger = NULL;
ret = uclass_get(UCLASS_FG, &uc);
if (ret)
return ret;
for (uclass_first_device(UCLASS_FG, &dev);
dev;
uclass_next_device(&dev)) {
cap = fuel_gauge_capability(dev);
if (cap == (FG_CAP_CHARGER | FG_CAP_FUEL_GAUGE)) {
*fuel_gauge = dev;
*charger = NULL;
} else if (cap == FG_CAP_FUEL_GAUGE) {
*fuel_gauge = dev;
} else if (cap == FG_CAP_CHARGER) {
*charger = dev;
}
}
return (*fuel_gauge) ? 0 : -ENODEV;
}
static const struct dm_charge_display_ops charge_animation_ops = {
.show = charge_animation_show,
};
static int charge_animation_probe(struct udevice *dev)
{
struct charge_animation_priv *priv = dev_get_priv(dev);
int ret, soc;
/* Get PMIC: used for power off system */
ret = uclass_get_device(UCLASS_MCU, 0, &priv->mcu);
if (ret) {
if (ret == -ENODEV)
printf("Can't find MCU\n");
else
printf("Get UCLASS MCU failed: %d\n", ret);
}
/* Get fuel gauge and charger(If need) */
ret = fg_charger_get_device(&priv->fg, &priv->charger);
if (ret) {
if (ret == -ENODEV)
debug("Can't find FG\n");
else
debug("Get UCLASS FG failed: %d\n", ret);
// return ret;
}
#ifdef CONFIG_LED
ret = led_get_by_label(LED_CHARGING_NAME, &priv->led_charging);
if (!ret)
printf("Found Charging LED \n");
ret = led_get_by_label(LED_CHARGING_FULL_NAME, &priv->led_full);
if (!ret)
printf("Found Charging-Full LED\n");
ret = led_get_by_label(LED_CHARGING_START_NAME, &priv->led_start);
if (!ret)
printf("Found Charging-Start LED\n");
#endif
ret = gpio_request_by_name(dev, "powerkey-gpio", 0, &powerkey_gpio, 0);
if (dm_gpio_is_valid(&powerkey_gpio)) {
dm_gpio_set_dir_flags(&powerkey_gpio, GPIOD_IS_IN);
}
printf("Enable charge animation display\n");
return 0;
}
static const struct udevice_id charge_animation_ids[] = {
{ .compatible = "rockchip,uboot-charge" },
{ },
};
U_BOOT_DRIVER(charge_animation) = {
.name = "charge-animation",
.id = UCLASS_CHARGE_DISPLAY,
.probe = charge_animation_probe,
.of_match = charge_animation_ids,
.ops = &charge_animation_ops,
.ofdata_to_platdata = charge_animation_ofdata_to_platdata,
.platdata_auto_alloc_size = sizeof(struct charge_animation_pdata),
.priv_auto_alloc_size = sizeof(struct charge_animation_priv),
};

11
drivers/power/fuel_gauge/Kconfig
View File

@@ -1,11 +0,0 @@
config DM_FUEL_GAUGE
bool "Enable driver model fuel gauge support"
depends on DM
help
This adds a simple uclass for fuel gauge.
config POWER_FG_CW201X
bool "CW201X Fuel gauge support"
depends on DM_FUEL_GAUGE
help
This adds support for CW201X fuel gauge support.

3
drivers/power/fuel_gauge/Makefile
View File

@@ -3,7 +3,4 @@
# Copyright (C) 2012 Samsung Electronics
# Lukasz Majewski <l.majewski@samsung.com>
obj-$(CONFIG_$(SPL_)DM_FUEL_GAUGE) += fuel_gauge_uclass.o
obj-$(CONFIG_POWER_FG_MAX17042) += fg_max17042.o
obj-$(CONFIG_POWER_FG_CW201X) += fg_cw201x.o

415
drivers/power/fuel_gauge/fg_cw201x.c
View File

@@ -1,415 +0,0 @@
/*
* (C) Copyright 2008-2015 Fuzhou Rockchip Electronics Co., Ltd
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/gpio.h>
#include <dm.h>
#include <dm/device.h>
#include <errno.h>
#include <fdtdec.h>
#include <i2c.h>
// #include <linux/usb/phy-rockchip-usb2.h>
#include <malloc.h>
#include <power/battery.h>
#include <power/fuel_gauge.h>
// #include <power/pmic.h>
#include "fg_regs.h"
DECLARE_GLOBAL_DATA_PTR;
#define COMPAT_ROCKCHIP_CW201X "cw201x"
#define REG_VERSION 0x0
#define REG_VCELL 0x2
#define REG_SOC 0x4
#define REG_RRT_ALERT 0x6
#define REG_CONFIG 0x8
#define REG_MODE 0xA
#define REG_BATINFO 0x10
#define MODE_SLEEP_MASK (0x3 << 6)
#define MODE_SLEEP (0x3 << 6)
#define MODE_NORMAL (0x0 << 6)
#define MODE_QUICK_START (0x3 << 4)
#define MODE_RESTART (0xf << 0)
#define CONFIG_UPDATE_FLG (0x1 << 1)
#define ATHD (0x0 << 3)
enum charger_type {
CHARGER_TYPE_NO = 0,
CHARGER_TYPE_USB,
CHARGER_TYPE_AC,
CHARGER_TYPE_DC,
CHARGER_TYPE_UNDEF,
};
struct cw201x_info {
struct udevice *dev;
int capacity;
u32 *cw_bat_config_info;
int divider_res1;
int divider_res2;
int hw_id_check;
struct gpio_desc hw_id0;
struct gpio_desc hw_id1;
int support_dc_adp;
struct gpio_desc dc_det_gpio;
int dc_det_flag;
bool dual_cell;
};
static u8 cw201x_read(struct cw201x_info *cw201x, u8 reg)
{
u8 val;
int ret;
ret = dm_i2c_read(cw201x->dev, reg, &val, 1);
if (ret) {
printf("write error to device: %p register: %#x!",
cw201x->dev, reg);
return ret;
}
return val;
}
static int cw201x_write(struct cw201x_info *cw201x, u8 reg, u8 val)
{
int ret;
ret = dm_i2c_write(cw201x->dev, reg, &val, 1);
if (ret) {
printf("write error to device: %p register: %#x!",
cw201x->dev, reg);
return ret;
}
return 0;
}
static u16 cw201x_read_half_word(struct cw201x_info *cw201x, int reg)
{
u8 vall, valh;
u16 val;
valh = cw201x_read(cw201x, reg);
vall = cw201x_read(cw201x, reg + 1);
val = ((u16)valh << 8) | vall;
return val;
}
static int cw201x_parse_config_info(struct cw201x_info *cw201x)
{
int ret;
int i, len, size;
const u8 *info;
struct udevice *dev = cw201x->dev;
if (dev_read_prop(dev, "bat_config_info", &len)) {
len /= sizeof(u32);
size = sizeof(*cw201x->cw_bat_config_info) * len;
cw201x->cw_bat_config_info = calloc(size, 1);
if (!cw201x->cw_bat_config_info) {
printf("calloc cw_bat_config_info fail\n");
return -EINVAL;
}
ret = dev_read_u32_array(dev, "bat_config_info",
cw201x->cw_bat_config_info, len);
if (ret) {
printf("fdtdec_get cw_bat_config_info fail\n");
return -EINVAL;
}
return 0;
}
if (!dev_read_prop(dev, "cellwise,battery-profile", &len))
return -EINVAL;
size = sizeof(*cw201x->cw_bat_config_info) * len;
cw201x->cw_bat_config_info = calloc(size, 1);
if (!cw201x->cw_bat_config_info) {
printf("calloc cw_bat_config_info fail\n");
return -EINVAL;
}
info = dev_read_u8_array_ptr(dev, "cellwise,battery-profile", len);
if (!info) {
printf("fdtdec_get battery profile fail\n");
return -EINVAL;
}
for (i = 0; i < len; i++) {
cw201x->cw_bat_config_info[i] = info[i];
printf("%#x ", cw201x->cw_bat_config_info[i]);
if ((i+1) % 8 == 0)
printf("\n");
}
return 0;
}
static int cw201x_ofdata_to_platdata(struct udevice *dev)
{
struct cw201x_info *cw201x = dev_get_priv(dev);
int ret;
int hw_id0_val, hw_id1_val;
cw201x->dev = dev;
ret = cw201x_parse_config_info(cw201x);
if (ret)
return ret;
cw201x->dual_cell = dev_read_bool(dev, "cellwise,dual-cell");
ret = gpio_request_by_name_nodev(dev_ofnode(dev), "dc_det_gpio",
0, &cw201x->dc_det_gpio, GPIOD_IS_IN);
if (!ret) {
cw201x->support_dc_adp = 1;
printf("DC is valid\n");
} else {
printf("DC is invalid, ret=%d\n", ret);
}
cw201x->hw_id_check = dev_read_u32_default(dev, "hw_id_check", 0);
if (cw201x->hw_id_check) {
ret = gpio_request_by_name_nodev(dev_ofnode(dev),
"hw_id0_gpio", 0,
&cw201x->hw_id0, GPIOD_IS_IN);
if (ret)
return -EINVAL;
hw_id0_val = dm_gpio_get_value(&cw201x->hw_id0);
ret = gpio_request_by_name_nodev(dev_ofnode(dev),
"hw_id1_gpio", 0,
&cw201x->hw_id1, GPIOD_IS_IN);
if (ret)
return -EINVAL;
hw_id1_val = dm_gpio_get_value(&cw201x->hw_id1);
/* ID1 = 0, ID0 = 1 : Battery */
if (!hw_id0_val || hw_id1_val)
return -EINVAL;
}
cw201x->divider_res1 = dev_read_u32_default(dev, "divider_res1", 0);
cw201x->divider_res2 = dev_read_u32_default(dev, "divider_res2", 0);
return 0;
}
static int cw201x_get_vol(struct cw201x_info *cw201x)
{
u16 value16, value16_1, value16_2, value16_3;
int voltage;
int res1, res2;
int retry = 0;
__retry:
value16 = cw201x_read_half_word(cw201x, REG_VCELL);
if (value16 < 0)
return -1;
value16_1 = cw201x_read_half_word(cw201x, REG_VCELL);
if (value16_1 < 0)
return -1;
value16_2 = cw201x_read_half_word(cw201x, REG_VCELL);
if (value16_2 < 0)
return -1;
if (value16 > value16_1) {
value16_3 = value16;
value16 = value16_1;
value16_1 = value16_3;
}
if (value16_1 > value16_2) {
value16_3 = value16_1;
value16_1 = value16_2;
value16_2 = value16_3;
}
if (value16 > value16_1) {
value16_3 = value16;
value16 = value16_1;
value16_1 = value16_3;
}
voltage = value16_1 * 312 / 1024;
if (voltage <= 0 && retry < 10) {
retry++;
mdelay(20);
goto __retry;
}
if (cw201x->divider_res1 &&
cw201x->divider_res2) {
res1 = cw201x->divider_res1;
res2 = cw201x->divider_res2;
voltage = voltage * (res1 + res2) / res2;
}
if (cw201x->dual_cell)
voltage *= 2;
// printf("the cw201x voltage=%d\n", voltage);
return voltage;
}
static int cw201x_dwc_otg_check_dpdm(void)
{
#if defined(CONFIG_PHY_ROCKCHIP_INNO_USB2) && !defined(CONFIG_SPL_BUILD)
return rockchip_chg_get_type();
#else
printf("rockchip_chg_get_type() is not implement\n");
return CHARGER_TYPE_NO;
#endif
}
static int cw201x_get_usb_state(struct cw201x_info *cw201x)
{
int charger_type;
switch (cw201x_dwc_otg_check_dpdm()) {
case 0:
charger_type = CHARGER_TYPE_NO;
break;
case 1:
case 3:
charger_type = CHARGER_TYPE_USB;
break;
case 2:
charger_type = CHARGER_TYPE_AC;
break;
default:
charger_type = CHARGER_TYPE_NO;
break;
}
return charger_type;
}
static bool cw201x_get_dc_state(struct cw201x_info *cw201x)
{
if (dm_gpio_get_value(&cw201x->dc_det_gpio))
return true;
return false;
}
static bool cw201x_check_charge(struct cw201x_info *cw201x)
{
if (cw201x_get_usb_state(cw201x) != CHARGER_TYPE_NO)
return true;
if (cw201x_get_dc_state(cw201x))
return true;
return false;
}
static int cw201x_get_soc(struct cw201x_info *cw201x)
{
int cap, i = 0;
while (i < 10) {
mdelay(30);
cap = cw201x_read(cw201x, REG_SOC);
if ((cap < 0) || (cap > 100))
cap = cw201x->capacity;
i++;
if (cap)
break;
}
cw201x->capacity = cap;
return cw201x->capacity;
}
static int cw201x_update_get_soc(struct udevice *dev)
{
struct cw201x_info *cw201x = dev_get_priv(dev);
return cw201x_get_soc(cw201x);
}
static int cw201x_update_get_voltage(struct udevice *dev)
{
struct cw201x_info *cw201x = dev_get_priv(dev);
return cw201x_get_vol(cw201x);
}
static int cw201x_update_get_current(struct udevice *dev)
{
return 0;
}
static bool cw201x_update_get_chrg_online(struct udevice *dev)
{
struct cw201x_info *cw201x = dev_get_priv(dev);
return cw201x_check_charge(cw201x);
}
static int cw201x_capability(struct udevice *dev)
{
return FG_CAP_FUEL_GAUGE;
}
static struct dm_fuel_gauge_ops cw201x_fg_ops = {
.capability = cw201x_capability,
.get_soc = cw201x_update_get_soc,
.get_voltage = cw201x_update_get_voltage,
.get_current = cw201x_update_get_current,
.get_chrg_online = cw201x_update_get_chrg_online,
};
static int cw201x_fg_cfg(struct cw201x_info *cw201x)
{
u8 val = MODE_SLEEP;
int i;
if ((val & MODE_SLEEP_MASK) == MODE_SLEEP) {
val = MODE_NORMAL;
cw201x_write(cw201x, REG_MODE, val);
}
for (i = 0; i < 64; i++) {
cw201x_write(cw201x, REG_BATINFO + i,
(u8)cw201x->cw_bat_config_info[i]);
}
return 0;
}
static int cw201x_fg_probe(struct udevice *dev)
{
struct cw201x_info *cw201x = dev_get_priv(dev);
cw201x->dev = dev;
cw201x_fg_cfg(cw201x);
printf("vol: %d, soc: %d\n",
cw201x_get_vol(cw201x), cw201x_get_soc(cw201x));
return 0;
}
static const struct udevice_id cw201x_ids[] = {
{ .compatible = "cw201x" },
{ .compatible = "cellwise,cw2015" },
{ }
};
U_BOOT_DRIVER(cw201x_fg) = {
.name = "cw201x_fg",
.id = UCLASS_FG,
.of_match = cw201x_ids,
.probe = cw201x_fg_probe,
.ofdata_to_platdata = cw201x_ofdata_to_platdata,
.ops = &cw201x_fg_ops,
.priv_auto_alloc_size = sizeof(struct cw201x_info),
};

95
drivers/power/fuel_gauge/fg_regs.h
View File

@@ -1,95 +0,0 @@
/*
* (C) Copyright 2017 Rockchip Electronics Co., Ltd
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _FG_RK8XX_H_
#define _FG_RK8XX_H_
/* register definition */
#define SECONDS_REG 0X00
#define VB_MON_REG 0x21
#define THERMAL_REG 0x22
#define SUP_STS_REG 0xA0
#define USB_CTRL_REG 0xA1
#define CHRG_CTRL_REG1 0xA3
#define CHRG_CTRL_REG2 0xA4
#define CHRG_CTRL_REG3 0xA5
#define BAT_CTRL_REG 0xA6
#define BAT_HTS_TS_REG 0xA8
#define BAT_LTS_TS_REG 0xA9
#define TS_CTRL_REG 0xAC
#define ADC_CTRL_REG 0xAD
#define GGCON_REG 0xB0
#define GGSTS_REG 0xB1
#define ZERO_CUR_ADC_REGH 0xB2
#define ZERO_CUR_ADC_REGL 0xB3
#define GASCNT_CAL_REG3 0xB4
#define GASCNT_CAL_REG2 0xB5
#define GASCNT_CAL_REG1 0xB6
#define GASCNT_CAL_REG0 0xB7
#define GASCNT_REG3 0xB8
#define GASCNT_REG2 0xB9
#define GASCNT_REG1 0xBA
#define GASCNT_REG0 0xBB
#define BAT_CUR_AVG_REGH 0xBC
#define BAT_CUR_AVG_REGL 0xBD
#define TS_ADC_REGH 0xBE
#define TS_ADC_REGL 0xBF
#define RK818_TS2_ADC_REGH 0xC0
#define RK818_TS2_ADC_REGL 0xC1
#define RK816_USB_ADC_REGH 0xC0
#define RK816_USB_ADC_REGL 0xC1
#define BAT_OCV_REGH 0xC2
#define BAT_OCV_REGL 0xC3
#define BAT_VOL_REGH 0xC4
#define BAT_VOL_REGL 0xC5
#define RELAX_ENTRY_THRES_REGH 0xC6
#define RELAX_ENTRY_THRES_REGL 0xC7
#define RELAX_EXIT_THRES_REGH 0xC8
#define RELAX_EXIT_THRES_REGL 0xC9
#define RELAX_VOL1_REGH 0xCA
#define RELAX_VOL1_REGL 0xCB
#define RELAX_VOL2_REGH 0xCC
#define RELAX_VOL2_REGL 0xCD
#define RELAX_CUR1_REGH 0xCE
#define RELAX_CUR1_REGL 0xCF
#define RELAX_CUR2_REGH 0xD0
#define RELAX_CUR2_REGL 0xD1
#define CAL_OFFSET_REGH 0xD2
#define CAL_OFFSET_REGL 0xD3
#define NON_ACT_TIMER_CNT_REG 0xD4
#define VCALIB0_REGH 0xD5
#define VCALIB0_REGL 0xD6
#define VCALIB1_REGH 0xD7
#define VCALIB1_REGL 0xD8
#define FCC_GASCNT_REG3 0xD9
#define FCC_GASCNT_REG2 0xDA
#define FCC_GASCNT_REG1 0xDB
#define FCC_GASCNT_REG0 0xDC
#define IOFFSET_REGH 0xDD
#define IOFFSET_REGL 0xDE
#define SLEEP_CON_SAMP_CUR_REG 0xDF
#define SOC_REG 0xE0
#define REMAIN_CAP_REG3 0xE1
#define REMAIN_CAP_REG2 0xE2
#define REMAIN_CAP_REG1 0xE3
#define REMAIN_CAP_REG0 0xE4
#define UPDAT_LEVE_REG 0xE5
#define NEW_FCC_REG3 0xE6
#define NEW_FCC_REG2 0xE7
#define NEW_FCC_REG1 0xE8
#define NEW_FCC_REG0 0xE9
#define NON_ACT_TIMER_CNT_SAVE_REG 0xEA
#define OCV_VOL_VALID_REG 0xEB
#define REBOOT_CNT_REG 0xEC
#define POFFSET_REG 0xED
#define MISC_MARK_REG 0xEE
#define HALT_CNT_REG 0xEF
#define DATA15_REG 0xEF
#define DATA16_REG 0xF0
#define DATA17_REG 0xF1
#define DATA18_REG 0xF2
#endif

136
drivers/power/fuel_gauge/fuel_gauge_uclass.c
View File

@@ -1,136 +0,0 @@
/*
* (C) Copyright 2017 Rockchip Electronics Co., Ltd
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <errno.h>
#include <dm.h>
#include <power/fuel_gauge.h>
DECLARE_GLOBAL_DATA_PTR;
int fuel_gauge_capability(struct udevice *dev)
{
const struct dm_fuel_gauge_ops *ops = dev_get_driver_ops(dev);
if (!ops || !ops->capability)
return (FG_CAP_CHARGER | FG_CAP_FUEL_GAUGE);
return ops->capability(dev);
}
int fuel_gauge_bat_is_exist(struct udevice *dev)
{
const struct dm_fuel_gauge_ops *ops = dev_get_driver_ops(dev);
if (!ops || !ops->bat_is_exist)
return -ENOSYS;
return ops->bat_is_exist(dev);
}
int fuel_gauge_get_current(struct udevice *dev)
{
const struct dm_fuel_gauge_ops *ops = dev_get_driver_ops(dev);
if (!ops || !ops->get_current)
return -ENOSYS;
return ops->get_current(dev);
}
int fuel_gauge_get_voltage(struct udevice *dev)
{
const struct dm_fuel_gauge_ops *ops = dev_get_driver_ops(dev);
if (!ops || !ops->get_voltage)
return -ENOSYS;
return ops->get_voltage(dev);
}
int fuel_gauge_update_get_soc(struct udevice *dev)
{
const struct dm_fuel_gauge_ops *ops = dev_get_driver_ops(dev);
if (!ops || !ops->get_soc)
return -ENOSYS;
return ops->get_soc(dev);
}
bool fuel_gauge_get_chrg_online(struct udevice *dev)
{
const struct dm_fuel_gauge_ops *ops = dev_get_driver_ops(dev);
if (!ops || !ops->get_chrg_online)
return -ENOSYS;
return ops->get_chrg_online(dev);
}
int fuel_gauge_get_temperature(struct udevice *dev, int *temp)
{
const struct dm_fuel_gauge_ops *ops = dev_get_driver_ops(dev);
if (!ops || !ops->get_temperature)
return -ENOSYS;
return ops->get_temperature(dev, temp);
}
int charger_set_charger_voltage(struct udevice *dev, int uV)
{
const struct dm_fuel_gauge_ops *ops = dev_get_driver_ops(dev);
if (!ops || !ops->set_charger_voltage)
return -ENOSYS;
return ops->set_charger_voltage(dev, uV);
}
int charger_set_current(struct udevice *dev, int ichrg_uA)
{
const struct dm_fuel_gauge_ops *ops = dev_get_driver_ops(dev);
if (!ops || !ops->set_charger_current)
return -ENOSYS;
return ops->set_charger_current(dev, ichrg_uA);
}
int charger_set_iprechg_current(struct udevice *dev, int iprechrg_uA)
{
const struct dm_fuel_gauge_ops *ops = dev_get_driver_ops(dev);
if (!ops || !ops->set_iprechg_current)
return -ENOSYS;
return ops->set_iprechg_current(dev, iprechrg_uA);
}
int charger_set_enable(struct udevice *dev)
{
const struct dm_fuel_gauge_ops *ops = dev_get_driver_ops(dev);
if (!ops || !ops->set_charger_enable)
return -ENOSYS;
return ops->set_charger_enable(dev);
}
int charger_set_disable(struct udevice *dev)
{
const struct dm_fuel_gauge_ops *ops = dev_get_driver_ops(dev);
if (!ops || !ops->set_charger_disable)
return -ENOSYS;
return ops->set_charger_disable(dev);
}
UCLASS_DRIVER(fuel_guage) = {
.id = UCLASS_FG,
.name = "fuel_gauge",
};

40
drivers/power/power_delivery/Kconfig
View File

@@ -1,40 +0,0 @@
# SPDX-License-Identifier: GPL-2.0
config DM_POWER_DELIVERY
bool "Enable driver model power delivery support"
depends on DM
help
This adds a simple uclass for power delivery.
config TYPEC_TCPM
tristate "USB Type-C Port Controller Manager"
depends on DM && DM_POWER_DELIVERY
help
The Type-C Port Controller Manager provides a USB PD and USB Type-C
state machine for use with Type-C Port Controllers.
config TYPEC_TCPCI
tristate "Type-C Port Controller Interface driver"
depends on DM && DM_POWER_DELIVERY && DM_I2C
help
Type-C Port Controller driver for TCPCI-compliant controller.
if TYPEC_TCPCI
config TYPEC_HUSB311
tristate "Hynetek HUSB311 Type-C chip driver"
depends on DM && DM_POWER_DELIVERY && DM_I2C
help
Hynetek HUSB311 Type-C chip driver that works with
Type-C Port Controller Manager to provide USB PD and USB
Type-C functionalities.
endif # TYPEC_TCPCI
config TYPEC_FUSB302
tristate "Fairchild FUSB302 Type-C chip driver"
depends on DM && DM_POWER_DELIVERY && DM_I2C
help
The Fairchild FUSB302 Type-C chip driver that works with
Type-C Port Controller Manager to provide USB PD and USB
Type-C functionalities.

7
drivers/power/power_delivery/Makefile
View File

@@ -1,7 +0,0 @@
# SPDX-License-Identifier: GPL-2.0
obj-$(CONFIG_$(SPL_)DM_POWER_DELIVERY) += power_delivery_uclass.o
obj-$(CONFIG_TYPEC_TCPM) += tcpm.o
obj-$(CONFIG_TYPEC_FUSB302) += fusb302.o
obj-$(CONFIG_TYPEC_TCPCI) += tcpci.o
obj-$(CONFIG_TYPEC_HUSB311) += tcpci_husb311.o

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