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base: t-head:Linux_SDK_V1.0.2
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t-head:lpi4a t-head:huiwei t-head:thead-sdk t-head:fix-toolchains t-head:merged-ahead t-head:update/1.4.2/gpu/dvfs t-head:ahead-new t-head:ov5693 t-head:develop t-head:master
t-head:Linux_SDK_V1.4.2 t-head:Linux_SDK_V1.3.3 t-head:Linux_SDK_V1.2.1 t-head:Linux_SDK_V1.2.0 t-head:Linux_SDK_V1.1.2 t-head:Linux_SDK_V1.0.3 t-head:Linux_SDK_V1.0.2 t-head:Linux_SDK_V0.9.5
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compare: t-head:Linux_SDK_V1.4.2
Branches Tags
t-head:lpi4a t-head:huiwei t-head:thead-sdk t-head:fix-toolchains t-head:merged-ahead t-head:update/1.4.2/gpu/dvfs t-head:ahead-new t-head:ov5693 t-head:develop t-head:master
t-head:Linux_SDK_V1.4.2 t-head:Linux_SDK_V1.3.3 t-head:Linux_SDK_V1.2.1 t-head:Linux_SDK_V1.2.0 t-head:Linux_SDK_V1.1.2 t-head:Linux_SDK_V1.0.3 t-head:Linux_SDK_V1.0.2 t-head:Linux_SDK_V0.9.5

8 Commits
Linux_SDK_ ... Linux_SDK_

Author SHA1 Message Date
thead_admin
a9b3178041 Linux_SDK_V1.4.2 
Signed-off-by: thead_admin <occ_thead@service.alibaba.com>
 2023-12-24 19:36:49 +08:00
thead_admin
c20ad6292d Linux_SDK_V1.3.3 
Signed-off-by: thead_admin <occ_thead@service.alibaba.com>
 2023-12-24 19:36:38 +08:00
thead_admin
f4327ba402 Linux_SDK_V1.2.1 
Signed-off-by: thead_admin <occ_thead@service.alibaba.com>
 2023-08-19 00:37:34 +08:00
jianghai
599b048690 eth: gmac: adapt to support DMA 32-bit in skb 2023-07-30 04:42:32 +08:00
thead_admin
b269dc8fa7 apply lpi4a patches 2023-07-30 04:42:27 +08:00
Han Gao
87e5c31f94 Linux_SDK_V1.2.0 2023-07-30 04:39:12 +08:00
thead_admin
ada47f394b Linux_SDK_V1.1.2 2023-03-05 22:36:24 +08:00
thead_admin
221913b496 Linux_SDK_V1.0.3 2023-01-04 13:12:21 +08:00
307 changed files with 18321 additions and 15712 deletions
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2
Documentation/devicetree/bindings/arm/msm/qcom,idle-state.txt
View File

@@ -81,4 +81,4 @@ Example:
};
};
[1]. Documentation/devicetree/bindings/arm/idle-states.yaml
[1]. Documentation/devicetree/bindings/cpu/idle-states.yaml

2
Documentation/devicetree/bindings/arm/psci.yaml
View File

@@ -101,7 +101,7 @@ properties:
bindings in [1]) must specify this property.
[1] Kernel documentation - ARM idle states bindings
Documentation/devicetree/bindings/arm/idle-states.yaml
Documentation/devicetree/bindings/cpu/idle-states.yaml
patternProperties:
"^power-domain-":

228
Documentation/devicetree/bindings/arm/idle-states.yaml → Documentation/devicetree/bindings/cpu/idle-states.yaml
View File

@@ -1,25 +1,30 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/idle-states.yaml#
$id: http://devicetree.org/schemas/cpu/idle-states.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: ARM idle states binding description
title: Idle states binding description
maintainers:
- Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
- Anup Patel <anup@brainfault.org>
description: |+
==========================================
1 - Introduction
==========================================
ARM systems contain HW capable of managing power consumption dynamically,
where cores can be put in different low-power states (ranging from simple wfi
to power gating) according to OS PM policies. The CPU states representing the
range of dynamic idle states that a processor can enter at run-time, can be
specified through device tree bindings representing the parameters required to
enter/exit specific idle states on a given processor.
ARM and RISC-V systems contain HW capable of managing power consumption
dynamically, where cores can be put in different low-power states (ranging
from simple wfi to power gating) according to OS PM policies. The CPU states
representing the range of dynamic idle states that a processor can enter at
run-time, can be specified through device tree bindings representing the
parameters required to enter/exit specific idle states on a given processor.
==========================================
2 - ARM idle states
==========================================
According to the Server Base System Architecture document (SBSA, [3]), the
power states an ARM CPU can be put into are identified by the following list:
@@ -43,8 +48,23 @@ description: |+
The device tree binding definition for ARM idle states is the subject of this
document.
==========================================
3 - RISC-V idle states
==========================================
On RISC-V systems, the HARTs (or CPUs) [6] can be put in platform specific
suspend (or idle) states (ranging from simple WFI, power gating, etc). The
RISC-V SBI v0.3 (or higher) [7] hart state management extension provides a
standard mechanism for OS to request HART state transitions.
The platform specific suspend (or idle) states of a hart can be either
retentive or non-rententive in nature. A retentive suspend state will
preserve HART registers and CSR values for all privilege modes whereas
a non-retentive suspend state will not preserve HART registers and CSR
values.
===========================================
2 - idle-states definitions
4 - idle-states definitions
===========================================
Idle states are characterized for a specific system through a set of
@@ -211,10 +231,10 @@ description: |+
properties specification that is the subject of the following sections.
===========================================
3 - idle-states node
5 - idle-states node
===========================================
ARM processor idle states are defined within the idle-states node, which is
The processor idle states are defined within the idle-states node, which is
a direct child of the cpus node [1] and provides a container where the
processor idle states, defined as device tree nodes, are listed.
@@ -223,7 +243,7 @@ description: |+
just supports idle_standby, an idle-states node is not required.
===========================================
4 - References
6 - References
===========================================
[1] ARM Linux Kernel documentation - CPUs bindings
@@ -238,9 +258,15 @@ description: |+
[4] ARM Architecture Reference Manuals
http://infocenter.arm.com/help/index.jsp
[6] ARM Linux Kernel documentation - Booting AArch64 Linux
[5] ARM Linux Kernel documentation - Booting AArch64 Linux
Documentation/arm64/booting.rst
[6] RISC-V Linux Kernel documentation - CPUs bindings
Documentation/devicetree/bindings/riscv/cpus.yaml
[7] RISC-V Supervisor Binary Interface (SBI)
http://github.com/riscv/riscv-sbi-doc/riscv-sbi.adoc
properties:
$nodename:
const: idle-states
@@ -253,7 +279,7 @@ properties:
On ARM 32-bit systems this property is optional
This assumes that the "enable-method" property is set to "psci" in the cpu
node[6] that is responsible for setting up CPU idle management in the OS
node[5] that is responsible for setting up CPU idle management in the OS
implementation.
const: psci
@@ -265,8 +291,8 @@ patternProperties:
as follows.
The idle state entered by executing the wfi instruction (idle_standby
SBSA,[3][4]) is considered standard on all ARM platforms and therefore
must not be listed.
SBSA,[3][4]) is considered standard on all ARM and RISC-V platforms and
therefore must not be listed.
In addition to the properties listed above, a state node may require
additional properties specific to the entry-method defined in the
@@ -275,7 +301,27 @@ patternProperties:
properties:
compatible:
const: arm,idle-state
enum:
- arm,idle-state
- riscv,idle-state
arm,psci-suspend-param:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
power_state parameter to pass to the ARM PSCI suspend call.
Device tree nodes that require usage of PSCI CPU_SUSPEND function
(i.e. idle states node with entry-method property is set to "psci")
must specify this property.
riscv,sbi-suspend-param:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
suspend_type parameter to pass to the RISC-V SBI HSM suspend call.
This property is required in idle state nodes of device tree meant
for RISC-V systems. For more details on the suspend_type parameter
refer the SBI specifiation v0.3 (or higher) [7].
local-timer-stop:
description:
@@ -317,6 +363,8 @@ patternProperties:
description:
A string used as a descriptive name for the idle state.
additionalProperties: false
required:
- compatible
- entry-latency-us
@@ -658,4 +706,150 @@ examples:
};
};
- |
// Example 3 (RISC-V 64-bit, 4-cpu systems, two clusters):
cpus {
#size-cells = <0>;
#address-cells = <1>;
cpu@0 {
device_type = "cpu";
compatible = "riscv";
reg = <0x0>;
riscv,isa = "rv64imafdc";
mmu-type = "riscv,sv48";
cpu-idle-states = <&CPU_RET_0_0 &CPU_NONRET_0_0
&CLUSTER_RET_0 &CLUSTER_NONRET_0>;
cpu_intc0: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
interrupt-controller;
};
};
cpu@1 {
device_type = "cpu";
compatible = "riscv";
reg = <0x1>;
riscv,isa = "rv64imafdc";
mmu-type = "riscv,sv48";
cpu-idle-states = <&CPU_RET_0_0 &CPU_NONRET_0_0
&CLUSTER_RET_0 &CLUSTER_NONRET_0>;
cpu_intc1: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
interrupt-controller;
};
};
cpu@10 {
device_type = "cpu";
compatible = "riscv";
reg = <0x10>;
riscv,isa = "rv64imafdc";
mmu-type = "riscv,sv48";
cpu-idle-states = <&CPU_RET_1_0 &CPU_NONRET_1_0
&CLUSTER_RET_1 &CLUSTER_NONRET_1>;
cpu_intc10: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
interrupt-controller;
};
};
cpu@11 {
device_type = "cpu";
compatible = "riscv";
reg = <0x11>;
riscv,isa = "rv64imafdc";
mmu-type = "riscv,sv48";
cpu-idle-states = <&CPU_RET_1_0 &CPU_NONRET_1_0
&CLUSTER_RET_1 &CLUSTER_NONRET_1>;
cpu_intc11: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
interrupt-controller;
};
};
idle-states {
CPU_RET_0_0: cpu-retentive-0-0 {
compatible = "riscv,idle-state";
riscv,sbi-suspend-param = <0x10000000>;
entry-latency-us = <20>;
exit-latency-us = <40>;
min-residency-us = <80>;
};
CPU_NONRET_0_0: cpu-nonretentive-0-0 {
compatible = "riscv,idle-state";
riscv,sbi-suspend-param = <0x90000000>;
entry-latency-us = <250>;
exit-latency-us = <500>;
min-residency-us = <950>;
};
CLUSTER_RET_0: cluster-retentive-0 {
compatible = "riscv,idle-state";
riscv,sbi-suspend-param = <0x11000000>;
local-timer-stop;
entry-latency-us = <50>;
exit-latency-us = <100>;
min-residency-us = <250>;
wakeup-latency-us = <130>;
};
CLUSTER_NONRET_0: cluster-nonretentive-0 {
compatible = "riscv,idle-state";
riscv,sbi-suspend-param = <0x91000000>;
local-timer-stop;
entry-latency-us = <600>;
exit-latency-us = <1100>;
min-residency-us = <2700>;
wakeup-latency-us = <1500>;
};
CPU_RET_1_0: cpu-retentive-1-0 {
compatible = "riscv,idle-state";
riscv,sbi-suspend-param = <0x10000010>;
entry-latency-us = <20>;
exit-latency-us = <40>;
min-residency-us = <80>;
};
CPU_NONRET_1_0: cpu-nonretentive-1-0 {
compatible = "riscv,idle-state";
riscv,sbi-suspend-param = <0x90000010>;
entry-latency-us = <250>;
exit-latency-us = <500>;
min-residency-us = <950>;
};
CLUSTER_RET_1: cluster-retentive-1 {
compatible = "riscv,idle-state";
riscv,sbi-suspend-param = <0x11000010>;
local-timer-stop;
entry-latency-us = <50>;
exit-latency-us = <100>;
min-residency-us = <250>;
wakeup-latency-us = <130>;
};
CLUSTER_NONRET_1: cluster-nonretentive-1 {
compatible = "riscv,idle-state";
riscv,sbi-suspend-param = <0x91000010>;
local-timer-stop;
entry-latency-us = <600>;
exit-latency-us = <1100>;
min-residency-us = <2700>;
wakeup-latency-us = <1500>;
};
};
};
...

6
Documentation/devicetree/bindings/riscv/cpus.yaml
View File

@@ -87,6 +87,12 @@ properties:
- compatible
- interrupt-controller
cpu-idle-states:
$ref: '/schemas/types.yaml#/definitions/phandle-array'
description: |
List of phandles to idle state nodes supported
by this hart (see ./idle-states.yaml).
required:
- riscv,isa
- interrupt-controller

14
MAINTAINERS
View File

@@ -4614,6 +4614,20 @@ S: Supported
F: drivers/cpuidle/cpuidle-psci.h
F: drivers/cpuidle/cpuidle-psci-domain.c
CPUIDLE DRIVER - DT IDLE PM DOMAIN
M: Ulf Hansson <ulf.hansson@linaro.org>
L: linux-pm@vger.kernel.org
S: Supported
F: drivers/cpuidle/dt_idle_genpd.c
F: drivers/cpuidle/dt_idle_genpd.h
CPUIDLE DRIVER - RISC-V SBI
M: Anup Patel <anup@brainfault.org>
L: linux-pm@vger.kernel.org
L: linux-riscv@lists.infradead.org
S: Maintained
F: drivers/cpuidle/cpuidle-riscv-sbi.c
CRAMFS FILESYSTEM
M: Nicolas Pitre <nico@fluxnic.net>
S: Maintained

20
arch/riscv/Kconfig
View File

@@ -21,7 +21,6 @@ config RISCV
select ARCH_HAS_GCOV_PROFILE_ALL
select ARCH_HAS_GIGANTIC_PAGE
select ARCH_HAS_KCOV
select ARCH_HAS_MMIOWB
select ARCH_HAS_PTE_SPECIAL
select ARCH_HAS_SET_DIRECT_MAP
select ARCH_HAS_SET_MEMORY
@@ -32,15 +31,18 @@ config RISCV
select ARCH_HAS_SYNC_DMA_FOR_DEVICE
select ARCH_HAS_DMA_WRITE_COMBINE
select ARCH_HAS_DMA_MMAP_PGPROT
select ARCH_KEEP_MEMBLOCK
select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX
select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT
select ARCH_USE_QUEUED_SPINLOCKS
select ARCH_USE_QUEUED_RWLOCKS
select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU
select ARCH_WANT_FRAME_POINTERS
select ARCH_WANT_HUGE_PMD_SHARE if 64BIT
select CLONE_BACKWARDS
select CLINT_TIMER if !MMU
select COMMON_CLK
select CPU_PM if (SUSPEND || CPU_IDLE)
select CPU_PM if CPU_IDLE || HIBERNATION
select COMPAT_BINFMT_ELF if BINFMT_ELF && COMPAT
select EDAC_SUPPORT
select DMA_DIRECT_REMAP
@@ -360,6 +362,8 @@ config RISCV_ISA_C
config NO_SFENCE_VMA
bool "Replace sfence.vma with CSR_SMCIR operation"
depends on !SMP
default y
config RISCV_SWIOTLB
bool "Enable SWIOTLB"
@@ -569,6 +573,18 @@ source "kernel/power/Kconfig"
config ARCH_SUSPEND_POSSIBLE
def_bool y
config ARCH_HIBERNATION_POSSIBLE
def_bool y
config ARCH_HIBERNATION_HEADER
def_bool HIBERNATION
endmenu
menu "CPU Power Management"
source "drivers/cpuidle/Kconfig"
endmenu
source "arch/riscv/kvm/Kconfig"

3
arch/riscv/Kconfig.socs
View File

@@ -19,6 +19,9 @@ config SOC_VIRT
select GOLDFISH
select RTC_DRV_GOLDFISH if RTC_CLASS
select SIFIVE_PLIC
select PM_GENERIC_DOMAINS if PM
select PM_GENERIC_DOMAINS_OF if PM && OF
select RISCV_SBI_CPUIDLE if CPU_IDLE
help
This enables support for QEMU Virt Machine.

84
arch/riscv/boot/dts/thead/Makefile
View File

@@ -1,35 +1,51 @@
# SPDX-License-Identifier: GPL-2.0
dtb-$(CONFIG_SOC_THEAD) += ice.dtb
dtb-$(CONFIG_SOC_THEAD) += light-fm-emu.dtb light_mpw.dtb
dtb-$(CONFIG_SOC_THEAD) += light-fm-emu-npu-fce.dtb
dtb-$(CONFIG_SOC_THEAD) += light-fm-emu-gpu.dtb
dtb-$(CONFIG_SOC_THEAD) += light-fm-emu-dsp.dtb
dtb-$(CONFIG_SOC_THEAD) += light-fm-emu-audio.dtb
dtb-$(CONFIG_SOC_THEAD) += light-fm-emu-hdmi.dtb
dtb-$(CONFIG_SOC_THEAD) += light-fm-emu-dsi0-hdmi.dtb
dtb-$(CONFIG_SOC_THEAD) += light-a-val.dtb light-a-val-sv.dtb
dtb-$(CONFIG_SOC_THEAD) += light-a-val-ddr2G.dtb light-a-val-ddr1G.dtb
dtb-$(CONFIG_SOC_THEAD) += light-a-val-npu-fce.dtb
dtb-$(CONFIG_SOC_THEAD) += light-a-val-iso7816.dtb
dtb-$(CONFIG_SOC_THEAD) += light-a-val-nand.dtb
dtb-$(CONFIG_SOC_THEAD) += light-a-val-audio.dtb
dtb-$(CONFIG_SOC_THEAD) += light-a-val-dsi0.dtb light-a-val-dsi1.dtb light-a-val-hdmi.dtb light-a-val-dsi0-dsi1.dtb light-a-val-dsi0-hdmi.dtb light-a-val-dpi0.dtb light-a-val-dpi0-dpi1.dtb
dtb-$(CONFIG_SOC_THEAD) += light-a-val-wcn.dtb
dtb-$(CONFIG_SOC_THEAD) += light-a-val-gpio-keys.dtb
dtb-$(CONFIG_SOC_THEAD) += light-a-val-khv.dtb
dtb-$(CONFIG_SOC_THEAD) += light-a-val-sec.dtb
dtb-$(CONFIG_SOC_THEAD) += light-a-val-miniapp-hdmi.dtb
dtb-$(CONFIG_SOC_THEAD) += light-a-product.dtb
dtb-$(CONFIG_SOC_THEAD) += light-b-product.dtb
dtb-$(CONFIG_SOC_THEAD) += light-b-product-ddr1G.dtb
dtb-$(CONFIG_SOC_THEAD) += light-b-product-miniapp-hdmi.dtb
dtb-$(CONFIG_SOC_THEAD) += light-a-val-full.dtb
dtb-$(CONFIG_SOC_THEAD) += light-ant-ref.dtb
dtb-$(CONFIG_SOC_THEAD) += light-ant-discrete.dtb
dtb-$(CONFIG_SOC_THEAD) += light-beagle.dtb
dtb-$(CONFIG_SOC_THEAD) += light-a-ref.dtb light-a-ref-dsi0.dtb light-a-ref-dsi0-hdmi.dtb
dtb-$(CONFIG_SOC_THEAD) += light-b-ref.dtb
dtb-$(CONFIG_SOC_THEAD) += light-a-val-crash.dtb light-b-product-crash.dtb light-ant-ref-crash.dtb light-ant-discrete-crash.dtb
dtb-$(CONFIG_SOC_THEAD) += light-b-power.dtb
dtb-$(CONFIG_SOC_THEAD) += light-a-val-android.dtb
dtb-$(CONFIG_SOC_THEAD_ICE) += ice.dtb
dtb-$(CONFIG_SOC_THEAD_TH1520_MPW) += th1520_mpw.dtb
dtb-$(CONFIG_SOC_THEAD_TH1520_EMU) += th1520-fm-emu.dtb
dtb-$(CONFIG_SOC_THEAD_TH1520_EMU) += th1520-fm-emu-npu-fce.dtb
dtb-$(CONFIG_SOC_THEAD_TH1520_EMU) += th1520-fm-emu-gpu.dtb
dtb-$(CONFIG_SOC_THEAD_TH1520_EMU) += th1520-fm-emu-dsp.dtb
dtb-$(CONFIG_SOC_THEAD_TH1520_EMU) += th1520-fm-emu-audio.dtb
dtb-$(CONFIG_SOC_THEAD_TH1520_EMU) += th1520-fm-emu-hdmi.dtb
dtb-$(CONFIG_SOC_THEAD_TH1520_EMU) += th1520-fm-emu-dsi0-hdmi.dtb
dtb-$(CONFIG_SOC_THEAD) += th1520-a-val.dtb th1520-a-val-sec.dtb
dtb-$(CONFIG_SOC_THEAD) += th1520-a-val-crash.dtb
dtb-$(CONFIG_SOC_THEAD) += th1520-a-val-audio.dtb
dtb-$(CONFIG_SOC_THEAD) += th1520-a-val-audio-i2s-8ch.dtb
dtb-$(CONFIG_SOC_THEAD) += th1520-a-val-audio-tdm.dtb
dtb-$(CONFIG_SOC_THEAD) += th1520-a-val-audio-spdif.dtb
dtb-$(CONFIG_SOC_THEAD) += th1520-a-val-dsi0-hdmi.dtb
dtb-$(CONFIG_SOC_THEAD) += th1520-a-val-dsi0-dsi1.dtb
dtb-$(CONFIG_SOC_THEAD_TH1520_DEV) += th1520-a-val-sv.dtb
dtb-$(CONFIG_SOC_THEAD_TH1520_DEV) += th1520-a-val-ddr2G.dtb th1520-a-val-ddr1G.dtb
dtb-$(CONFIG_SOC_THEAD_TH1520_DEV) += th1520-a-val-npu-fce.dtb
dtb-$(CONFIG_SOC_THEAD_TH1520_DEV) += th1520-a-val-iso7816.dtb
dtb-$(CONFIG_SOC_THEAD_TH1520_DEV) += th1520-a-val-nand.dtb
dtb-$(CONFIG_SOC_THEAD_TH1520_DEV) += th1520-a-val-dsi0.dtb th1520-a-val-dsi1.dtb th1520-a-val-hdmi.dtb th1520-a-val-dsi0-hdmi-audio.dtb th1520-a-val-dpi0.dtb th1520-a-val-dpi0-dpi1.dtb
dtb-$(CONFIG_SOC_THEAD_TH1520_DEV) += th1520-a-val-wcn.dtb
dtb-$(CONFIG_SOC_THEAD_TH1520_DEV) += th1520-a-val-gpio-keys.dtb
dtb-$(CONFIG_SOC_THEAD_TH1520_DEV) += th1520-a-val-khv.dtb
dtb-$(CONFIG_SOC_THEAD_TH1520_DEV) += th1520-a-val-miniapp-hdmi.dtb
dtb-$(CONFIG_SOC_THEAD_TH1520_PRD) += th1520-a-product.dtb
dtb-$(CONFIG_SOC_THEAD_TH1520_DEV) += th1520-a-val-full.dtb
dtb-$(CONFIG_SOC_THEAD_TH1520_DEV) += th1520-a-ref.dtb th1520-a-ref-dsi0.dtb th1520-a-ref-dsi0-hdmi.dtb
dtb-$(CONFIG_SOC_THEAD) += th1520-b-product.dtb th1520-b-product-sec.dtb
dtb-$(CONFIG_SOC_THEAD) += th1520-b-product-crash.dtb
dtb-$(CONFIG_SOC_THEAD_TH1520_DEV) += th1520-b-product-ddr1G.dtb
dtb-$(CONFIG_SOC_THEAD_TH1520_DEV) += th1520-b-product-miniapp-hdmi.dtb
dtb-$(CONFIG_SOC_THEAD_TH1520_DEV) += th1520-b-ref.dtb
dtb-$(CONFIG_SOC_THEAD_TH1520_DEV) += th1520-b-power.dtb
dtb-$(CONFIG_SOC_THEAD_TH1520_ANT) += th1520-ant-ref.dtb
dtb-$(CONFIG_SOC_THEAD_TH1520_ANT) += th1520-ant-ref-crash.dtb th1520-ant-discrete-crash.dtb
dtb-$(CONFIG_SOC_THEAD_TH1520_DEV) += th1520-ant-discrete.dtb
dtb-$(CONFIG_SOC_THEAD_TH1520_DEV) += th1520-beagle.dtb
dtb-$(CONFIG_SOC_THEAD) += th1520-lpi4a-product.dtb th1520-lpi4a-product-sec.dtb
dtb-$(CONFIG_SOC_THEAD) += th1520-lpi4a-product-crash.dtb
dtb-$(CONFIG_SOC_THEAD) += th1520-lpi4a-camera-tuning.dtb
dtb-$(CONFIG_SOC_THEAD) += th1520-lpi4a-hx8279.dtb
dtb-$(CONFIG_SOC_THEAD) += th1520-lpi4a-dsi0.dtb
dtb-$(CONFIG_SOC_THEAD_TH1520_DEV) += th1520-lpi4a-ddr2G.dtb
dtb-$(CONFIG_SOC_THEAD_TH1520_ANDROID) += th1520-a-val-android.dtb
dtb-$(CONFIG_SOC_THEAD_FIRE) += fire-emu.dtb fire-emu-crash.dtb
dtb-$(CONFIG_SOC_THEAD_FIRE) += fire-emu-soc-base.dtb fire-emu-soc-c910x4.dtb fire-emu-gpu-dpu-dsi0.dtb fire-emu-vi-dsp-vo.dtb fire-emu-vi-vp-vo.dtb
dtb-$(CONFIG_SOC_THEAD_FIRE) += fire-emu-soc-base-sec.dtb

399
arch/riscv/boot/dts/thead/ice.dts
View File

@@ -1,399 +0,0 @@
/dts-v1/;
/ {
model = "T-HEAD c910 ice";
compatible = "thead,c910_ice";
#address-cells = <2>;
#size-cells = <2>;
memory@0 {
device_type = "memory";
/*
* Total memory size: 4GB (0x00000000 0x100000000)
* 0x00200000 - 0x0e0000000: 3407MB for Linux system
* 0xe0000000 - 0x100000000: 512MB for GPU
*/
reg = <0x0 0x200000 0x0 0xdfe00000>;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
timebase-frequency = <3000000>;
cpu@0 {
device_type = "cpu";
reg = <0>;
status = "okay";
compatible = "riscv";
riscv,isa = "rv64imafdcsu";
mmu-type = "riscv,sv39";
cpu-freq = "1.2Ghz";
cpu-icache = "64KB";
cpu-dcache = "64KB";
cpu-l2cache = "2MB";
cpu-tlb = "1024 4-ways";
cpu-cacheline = "64Bytes";
cpu-vector = "0.7.1";
cpu0_intc: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
interrupt-controller;
};
};
cpu@1 {
device_type = "cpu";
reg = <1>;
status = "okay";
compatible = "riscv";
riscv,isa = "rv64imafdcsu";
mmu-type = "riscv,sv39";
cpu-freq = "1.2Ghz";
cpu-icache = "64KB";
cpu-dcache = "64KB";
cpu-l2cache = "2MB";
cpu-tlb = "1024 4-ways";
cpu-cacheline = "64Bytes";
cpu-vector = "0.7.1";
cpu1_intc: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
interrupt-controller;
};
};
};
soc {
#address-cells = <2>;
#size-cells = <2>;
compatible = "simple-bus";
ranges;
reset: reset-sample {
compatible = "thead,reset-sample";
plic-delegate = <0x3 0xf01ffffc>;
using-csr-reset;
csr-copy = <
0x7c0 0x7c1 0x7c2 0x7c3 0x7c5 0x7cc
0x3b0 0x3b1 0x3b2 0x3b3
0x3b4 0x3b5 0x3b6 0x3b7
0x3a0
>;
};
clint0: clint@3f4000000 {
compatible = "riscv,clint0";
interrupts-extended = <
&cpu0_intc 3 &cpu0_intc 7
&cpu1_intc 3 &cpu1_intc 7
>;
reg = <0x3 0xf4000000 0x0 0x04000000>;
clint,has-no-64bit-mmio;
};
intc: interrupt-controller@3f0000000 {
#interrupt-cells = <1>;
compatible = "riscv,plic0";
interrupt-controller;
interrupts-extended = <
&cpu0_intc 0xffffffff &cpu0_intc 9
&cpu1_intc 0xffffffff &cpu1_intc 9
>;
reg = <0x3 0xf0000000 0x0 0x04000000>;
reg-names = "control";
riscv,max-priority = <7>;
riscv,ndev = <80>;
};
dummy_apb: apb-clock {
compatible = "fixed-clock";
clock-frequency = <62500000>;
clock-output-names = "dummy_apb";
#clock-cells = <0>;
};
dummy_ahb: ahb-clock {
compatible = "fixed-clock";
clock-frequency = <250000000>;
clock-output-names = "dummy_ahb";
#clock-cells = <0>;
};
dummy_axi: axi-clock {
compatible = "fixed-clock";
clock-frequency = <500000000>;
clock-output-names = "dummy_axi";
#clock-cells = <0>;
};
dummy_gmac: gmac-clock {
compatible = "fixed-clock";
clock-frequency = <1000000000>;
clock-output-names = "dummy_gmac";
#clock-cells = <0>;
};
dummy_clk_sdio: dummy-clk-sdio {
compatible = "fixed-clock";
clock-frequency = <150000000>;
clock-output-names = "dummy_clk_sdio";
#clock-cells = <0>;
};
usb: dwc3@3fff10000 {
compatible = "snps,dwc3";
reg = <0x3 0xfff10000 0x0 0x10000>;
interrupt-parent = <&intc>;
interrupts = <44>;
clocks = <&dummy_ahb>, <&dummy_ahb>, <&dummy_ahb>;
clock-names = "ref", "bus_early", "suspend";
maximum-speed = "super-speed";
dr_mode = "peripheral";
snps,usb3_lpm_capable;
snps,dis_u3_susphy_quirk;
};
gpio0: gpio@3fff71000 {
compatible = "snps,dw-apb-gpio";
reg = <0x3 0xfff71000 0x0 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
/* GPIO0[0-31] */
gpio0_porta: gpio0-controller@0 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
snps,nr-gpios = <32>;
reg = <0>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&intc>;
interrupts = <27>;
};
/* GPIO0[32-63] */
gpio0_portb: gpio0-controller@1 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
snps,nr-gpios = <32>;
reg = <1>;
};
};
gpio1: gpio@3fff72000 {
compatible = "snps,dw-apb-gpio";
reg = <0x3 0xfff72000 0x0 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
/* GPIO1[0-31] */
gpio1_porta: gpio1-controller@0 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
snps,nr-gpios = <32>;
reg = <0>;
};
/* GPIO1[32-63] */
gpio1_portb: gpio1-controller@1 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
snps,nr-gpios = <32>;
reg = <1>;
};
/* GPIO1[64-95] */
gpio1_portc: gpio1-controller@2 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
snps,nr-gpios = <32>;
reg = <2>;
};
};
gpio-leds {
compatible = "gpio-leds";
led0 { /* GPIO0[11] - UART2_TXD */
label = "led0";
gpios = <&gpio0_porta 11 1>;
default-state = "off";
};
};
gpio-keys {
compatible = "gpio-keys";
/* autorepeat; */
key_0 { /* GPIO0[10] - UART2_RXD */
gpios = <&gpio0_porta 10 1>;
linux,code = <59>;
label = "key_0";
};
};
i2c@3fff74000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,designware-i2c-ice";
reg = <0x3 0xfff74000 0x0 0x1000>;
interrupts = <21>;
interrupt-parent = <&intc>;
clocks = <&dummy_apb>;
clock-frequency = <400000>;
eeprom@50 {
compatible = "atmel,24c64";
reg = <0x50>;
pagesize = <32>;
};
goodix_ts@14 {
#gpio-cells = <2>;
compatible = "goodix,gt917s";
reg = <0x14>;
interrupt-parent = <&gpio0_porta>;
interrupts = <31 0>;
irq-gpios = <&gpio0_porta 31 0>;
reset-gpios = <&gpio0_porta 30 0>;
touchscreen-size-x = <720>;
touchscreen-size-y = <1280>;
};
};
serial@3fff73000 {
compatible = "snps,dw-apb-uart";
reg = <0x3 0xfff73000 0x0 0x400>;
interrupt-parent = <&intc>;
interrupts = <23>;
clocks = <&dummy_apb>;
clock-names = "baudclk";
reg-shift = <2>;
reg-io-width = <4>;
};
pmu: pmu {
interrupt-parent = <&cpu0_intc>;
interrupts = <17>;
compatible = "riscv,c910_pmu";
};
dmac0: dmac@3fffd0000 {
compatible = "snps,axi-dma-1.01a";
reg = <0x3 0xfffd0000 0x0 0x1000>;
interrupt-parent = <&intc>;
interrupts = <65>;
clocks = <&dummy_axi>, <&dummy_ahb>;
clock-names = "core-clk", "cfgr-clk";
dma-channels = <8>;
snps,block-size = <65536 65536 65536 65536 65536 65536 65536 65536>;
snps,priority = <0 1 2 3 4 5 6 7>;
snps,dma-masters = <1>;
snps,data-width = <4>;
snps,axi-max-burst-len = <16>;
status = "disabled";
};
sdhc0: sdhc0@3fffb0000 {
compatible = "snps,dw-mshc";
reg = <0x3 0xfffb0000 0x0 0x1000>;
interrupt-parent = <&intc>;
interrupts = <37>;
clocks = <&dummy_clk_sdio>, <&dummy_clk_sdio>;
clock-names = "ciu", "biu";
num-slots = <1>;
card-detect-delay = <200>;
cap-mmc-highspeed;
cap-cmd23;
non-removable;
bus-width = <8>;
};
sdhc1: sdhc1@3fffa0000 {
compatible = "snps,dw-mshc";
reg = <0x3 0xfffa0000 0x0 0x1000>;
interrupt-parent = <&intc>;
interrupts = <38>;
clocks = <&dummy_clk_sdio>, <&dummy_clk_sdio>;
clock-names = "ciu", "biu";
num-slots = <1>;
card-detect-delay = <200>;
cap-sd-highspeed;
bus-width = <4>;
};
stmmac_axi_setup: stmmac-axi-config {
snps,wr_osr_lmt = <3>;
snps,rd_osr_lmt = <3>;
snps,blen = <16 8 4 0 0 0 0>;
};
gmac: ethernet@3fffc0000 {
compatible = "thead,dwmac";
reg = < 0x3 0xfffc0000 0x0 0x2000
0x3 0xfe83025c 0x0 0x4
0x3 0xfe83031c 0x0 0x4
0x3 0xfff770c0 0x0 0x1c>;
reg-names = "gmac", "phy_if_reg", "txclk_dir_reg", "clk_mgr_reg";
interrupt-parent = <&intc>;
interrupts = <40>;
interrupt-names = "macirq";
clocks = <&dummy_ahb>, <&dummy_gmac>;
clock-names = "stmmaceth", "gmac_pll_clk";
snps,pbl = <32>;
snps,fixed-burst;
snps,axi-config = <&stmmac_axi_setup>;
phy-mode = "rgmii-id";
rx-clk-delay = <0x1f>; /* for RGMII */
tx-clk-delay = <0x1f>; /* for RGMII */
phy-handle = <&eth_phy_0>;
mdio0 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,dwmac-mdio";
eth_phy_0: ethernet-phy@0 {
reg = <0>;
};
};
};
gpu: gpu@3fff27000 {
compatible = "verisilicon,gc8000ul";
reg = <0x3 0xfff27000 0x0 0x1000>;
interrupt-parent = <&intc>;
interrupts = <63>;
contiguous-base = <0x0 0xe0000000>;
contiguous-size = <0x0 0x20000000>;
};
watchdog: watchdog@3fffe3000 {
compatible = "ice,ice-wdt";
reg = <0x3 0xfffe3000 0x0 0x1000>;
interrupts = <20>;
};
dpu: dpu@3fff28000 {
compatible = "verisilicon,dc8000-fb";
reg = <0x3 0xfff28000 0x0 0x8000>;
interrupt-parent = <&intc>;
interrupts = <64>;
};
};
chosen {
/* bootargs = "console=ttyS0,115200 crashkernel=256M-:128M c910_mmu_v1"; */
/* linux,initrd-start = <0x2000000>; */
/* linux,initrd-end = <0x17000000>; */
bootargs = "console=ttyS0,115200 rdinit=/sbin/init root=/dev/mmcblk0p4 rw rootfstype=ext4 blkdevparts=mmcblk0:2M(table),2M(dtb),60M(kernel),-(rootfs) clk_ignore_unused loglevel=7 rootwait crashkernel=256M-:128M c910_mmu_v1";
stdout-path = "serial0@3fff73000:115200";
};
};

8
arch/riscv/boot/dts/thead/light-a-product-powergate.dts
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@@ -1,8 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2021 Alibaba Group Holding Limited.
*/
#include "light-a-product.dts"
#include "light-powergate.dts"

1108
arch/riscv/boot/dts/thead/light-a-product.dts
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File diff suppressed because it is too large Load Diff

5
arch/riscv/boot/dts/thead/light-a-ref.dts
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@@ -1,5 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2021 Alibaba Group Holding Limited.
*/
#include "light-a-val.dts"

111
arch/riscv/boot/dts/thead/light-a-val-android.dts
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@@ -1,111 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2021 Alibaba Group Holding Limited.
*/
/dts-v1/;
#include "light-a-val-dsi0.dts"
&dpu_enc1 {
ports {
/delete-node/ port@0;
};
};
&disp1_out {
remote-endpoint = <&hdmi_tx_in>;
};
&sdhci1 {
status = "okay";
};
&wcn_bt {
status = "okay";
};
&wcn_wifi {
status = "okay";
};
&lightsound {
status = "okay";
simple-audio-card,widgets =
"Microphone", "Mic Jack",
"Speaker", "Speaker",
"Headphone", "Headphone Jack";
simple-audio-card,routing =
"Headphone Jack", "HP_L",
"Headphone Jack", "HP_R",
"Speaker", "SPK_LP",
"Speaker", "SPK_LN",
"Speaker", "SPK_RP",
"Speaker", "SPK_RN",
"Mic Jack","MICB",
"LINPUT1", "Mic Jack",
"LINPUT3", "Mic Jack";
simple-audio-card,dai-link@0 { /* I2S - CODEC */
reg = <0>;
format = "i2s";
cpu {
sound-dai = <&light_i2s 0>;
};
codec {
sound-dai = <&codec>;
};
};
simple-audio-card,dai-link@1 { /* I2S - HDMI */
reg = <1>;
format = "i2s";
cpu {
sound-dai = <&light_i2s 1>;
};
codec {
sound-dai = <&dummy_codec 2>;
};
};
};
&light_i2s {
status = "okay";
};
&hdmi_tx {
status = "okay";
port@0 {
/* input */
hdmi_tx_in: endpoint {
remote-endpoint = <&disp1_out>;
};
};
};
/ {
firmware {
android {
compatible = "android,firmware";
boot_devices = "soc/ffe7080000.sdhci";
fstab {
compatible = "android,fstab";
system {
compatible = "android,system";
dev = "/dev/block/platform/soc/ffe7080000.sdhci/by-name/system";
type = "ext4";
mnt_flags = "ro,barrier=1";
fsmgr_flags = "wait";
};
vendor {
compatible = "android,vendor";
dev = "/dev/block/platform/soc/ffe7080000.sdhci/by-name/vendor";
type = "ext4";
mnt_flags = "ro,barrier=1";
fsmgr_flags = "wait";
};
};
};
};
};

8
arch/riscv/boot/dts/thead/light-a-val-audio-powergate.dts
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@@ -1,8 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2021 Alibaba Group Holding Limited.
*/
#include "light-a-val-audio.dts"
#include "light-powergate.dts"

8
arch/riscv/boot/dts/thead/light-a-val-ddr1G-powergate.dts
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@@ -1,8 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2021 Alibaba Group Holding Limited.
*/
#include "light-a-val-ddr1G.dts"
#include "light-powergate.dts"

21
arch/riscv/boot/dts/thead/light-a-val-ddr1G.dts
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@@ -1,21 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2022 Alibaba Group Holding Limited.
*/
#include "light-a-val-ddr2G.dts"
/ {
model = "T-HEAD Light VAL configuration for 1GB DDR board";
compatible = "thead,light-val", "thead,light-val-ddr1G", "thead,light";
memory@0 {
device_type = "memory";
reg = <0x0 0x00000000 0x0 0x40000000>;
};
};
&cmamem {
size = <0 0x8c00000>; // 140MB by default
alloc-ranges = <0 0x02000000 0 0x0cc00000>; // [0x0600_0000 ~ 0x0EC0_0000]
};

8
arch/riscv/boot/dts/thead/light-a-val-ddr2G-powergate.dts
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@@ -1,8 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2021 Alibaba Group Holding Limited.
*/
#include "light-a-val-ddr2G.dts"
#include "light-powergate.dts"

25
arch/riscv/boot/dts/thead/light-a-val-ddr2G.dts
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@@ -1,25 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2022 Alibaba Group Holding Limited.
*/
#include "light-a-val.dts"
/ {
model = "T-HEAD Light VAL configuration for 2GB DDR board";
compatible = "thead,light-val", "thead,light-val-ddr2G", "thead,light";
memory@0 {
device_type = "memory";
reg = <0x0 0x00000000 0x0 0x80000000>;
};
};
&cmamem {
alloc-ranges = <0 0x64000000 0 0x14000000>; // [0x6400_0000 ~ 0x7800_0000]
};
&facelib_mem {
reg = <0x0 0x22000000 0 0x02000000>;
no-map;
};

8
arch/riscv/boot/dts/thead/light-a-val-dpi0-dpi1-powergate.dts
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@@ -1,8 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2021 Alibaba Group Holding Limited.
*/
#include "light-a-val-dpi0-dpi1.dts"
#include "light-powergate.dts"

40
arch/riscv/boot/dts/thead/light-a-val-dpi0-dpi1.dts
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@@ -1,40 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2022 Alibaba Group Holding Limited.
*/
/dts-v1/;
#include "light-a-val-dpi0.dts"
/ {
dpi_panel1: dpi-panel@1 {
compatible = "light,dummy-panel";
port {
dpi1_in: endpoint {
remote-endpoint = <&enc1_out>;
};
};
};
};
&dpu_enc1 {
compatible = "verisilicon,dpi-encoder";
status = "okay";
ports {
/* output */
port@1 {
reg = <1>;
enc1_out: endpoint {
remote-endpoint = <&dpi1_in>;
};
};
};
};
&dpu {
status = "okay";
};

8
arch/riscv/boot/dts/thead/light-a-val-dpi0-powergate.dts
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@@ -1,8 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2021 Alibaba Group Holding Limited.
*/
#include "light-a-val-dpi0.dts"
#include "light-powergate.dts"

44
arch/riscv/boot/dts/thead/light-a-val-dpi0.dts
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@@ -1,44 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2022 Alibaba Group Holding Limited.
*/
/dts-v1/;
#include "light-a-val.dts"
/ {
display-subsystem {
status = "okay";
};
dpi_panel0: dpi-panel@0 {
compatible = "light,dummy-panel";
port {
dpi0_in: endpoint {
remote-endpoint = <&enc0_out>;
};
};
};
};
&dpu_enc0 {
compatible = "verisilicon,dpi-encoder";
status = "okay";
ports {
/* output */
port@1 {
reg = <1>;
enc0_out: endpoint {
remote-endpoint = <&dpi0_in>;
};
};
};
};
&dpu {
status = "okay";
};

8
arch/riscv/boot/dts/thead/light-a-val-dsi0-dsi1-powergate.dts
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@@ -1,8 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2021 Alibaba Group Holding Limited.
*/
#include "light-a-val-dsi0-dsi1.dts"
#include "light-powergate.dts"

8
arch/riscv/boot/dts/thead/light-a-val-dsi0-hdmi-powergate.dts
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@@ -1,8 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2021 Alibaba Group Holding Limited.
*/
#include "light-a-val-dsi0-hdmi.dts"
#include "light-powergate.dts"

29
arch/riscv/boot/dts/thead/light-a-val-dsi0-hdmi.dts
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@@ -1,29 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2021 Alibaba Group Holding Limited.
*/
/dts-v1/;
#include "light-a-val-dsi0.dts"
&dpu_enc1 {
ports {
/delete-node/ port@0;
};
};
&disp1_out {
remote-endpoint = <&hdmi_tx_in>;
};
&hdmi_tx {
status = "okay";
port@0 {
/* input */
hdmi_tx_in: endpoint {
remote-endpoint = <&disp1_out>;
};
};
};

8
arch/riscv/boot/dts/thead/light-a-val-dsi0-powergate.dts
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@@ -1,8 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2021 Alibaba Group Holding Limited.
*/
#include "light-a-val-dsi0.dts"
#include "light-powergate.dts"

75
arch/riscv/boot/dts/thead/light-a-val-dsi0.dts
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@@ -1,75 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2021 Alibaba Group Holding Limited.
*/
/dts-v1/;
#include "light-a-val.dts"
/ {
display-subsystem {
status = "okay";
};
};
&dpu_enc0 {
status = "okay";
ports {
/* output */
port@1 {
reg = <1>;
enc0_out: endpoint {
remote-endpoint = <&dsi0_in>;
};
};
};
};
&dpu {
status = "okay";
};
&dsi0 {
status = "okay";
};
&dhost_0 {
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dsi0_in: endpoint {
remote-endpoint = <&enc0_out>;
};
};
port@1 {
reg = <1>;
dsi0_out: endpoint {
remote-endpoint = <&panel0_in>;
};
};
};
panel0@0 {
compatible = "txd,dy800qwxpab";
reg = <0>;
backlight = <&lcd0_backlight>;
reset-gpio = <&gpio1_porta 5 1>; /* active low */
vdd1v8-supply = <&lcd0_1v8>;
vspn5v7-supply = <&lcd0_5v7>;
port {
panel0_in: endpoint {
remote-endpoint = <&dsi0_out>;
};
};
};
};

8
arch/riscv/boot/dts/thead/light-a-val-dsi1-powergate.dts
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@@ -1,8 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2021 Alibaba Group Holding Limited.
*/
#include "light-a-val-dsi1.dts"
#include "light-powergate.dts"

75
arch/riscv/boot/dts/thead/light-a-val-dsi1.dts
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@@ -1,75 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2021 Alibaba Group Holding Limited.
*/
/dts-v1/;
#include "light-a-val.dts"
/ {
display-subsystem {
status = "okay";
};
};
&dpu_enc1 {
status = "okay";
ports {
/* output */
port@1 {
reg = <1>;
enc1_out: endpoint {
remote-endpoint = <&dsi1_in>;
};
};
};
};
&dpu {
status = "okay";
};
&dsi1 {
status = "okay";
};
&dhost_1 {
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dsi1_in: endpoint {
remote-endpoint = <&enc1_out>;
};
};
port@1 {
reg = <1>;
dsi1_out: endpoint {
remote-endpoint = <&panel1_in>;
};
};
};
panel1@0 {
compatible = "txd,dy800qwxpab";
reg = <0>;
backlight = <&lcd1_backlight>;
reset-gpio = <&gpio1_porta 9 1>; /* active low */
vdd1v8-supply = <&lcd1_1v8>;
vspn5v7-supply = <&lcd1_5v7>;
port {
panel1_in: endpoint {
remote-endpoint = <&dsi1_out>;
};
};
};
};

8
arch/riscv/boot/dts/thead/light-a-val-dsp0-dsp1-powergate.dts
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@@ -1,8 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2021 Alibaba Group Holding Limited.
*/
#include "light-a-val-dsp0-dsp1.dts"
#include "light-powergate.dts"

13
arch/riscv/boot/dts/thead/light-a-val-dsp0-dsp1.dts
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@@ -1,13 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2021 Alibaba Group Holding Limited.
*/
/dts-v1/;
#include "light-a-val.dts"
&xtensa_dsp1 {
status = "okay";
};

8
arch/riscv/boot/dts/thead/light-a-val-full-powergate.dts
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@@ -1,8 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2021 Alibaba Group Holding Limited.
*/
#include "light-a-val-full.dts"
#include "light-powergate.dts"

161
arch/riscv/boot/dts/thead/light-a-val-full.dts
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@@ -1,161 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2022 Alibaba Group Holding Limited.
*/
#include "light-a-val.dts"
/ {
display-subsystem {
status = "okay";
};
};
&dpu_enc0 {
status = "okay";
ports {
/* output */
port@1 {
reg = <1>;
enc0_out: endpoint {
remote-endpoint = <&dsi0_in>;
};
};
};
};
&dpu_enc1 {
ports {
/delete-node/ port@0;
};
};
&dpu {
status = "okay";
};
&dsi0 {
status = "okay";
};
&dhost_0 {
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dsi0_in: endpoint {
remote-endpoint = <&enc0_out>;
};
};
port@1 {
reg = <1>;
dsi0_out: endpoint {
remote-endpoint = <&panel0_in>;
};
};
};
panel0@0 {
compatible = "txd,dy800qwxpab";
reg = <0>;
backlight = <&lcd0_backlight>;
reset-gpio = <&gpio1_porta 5 1>; /* active low */
vdd1v8-supply = <&lcd0_1v8>;
vspn5v7-supply = <&lcd0_5v7>;
port {
panel0_in: endpoint {
remote-endpoint = <&dsi0_out>;
};
};
};
};
&disp1_out {
remote-endpoint = <&hdmi_tx_in>;
};
&hdmi_tx {
status = "okay";
port@0 {
/* input */
hdmi_tx_in: endpoint {
remote-endpoint = <&disp1_out>;
};
};
};
&lightsound {
status = "okay";
simple-audio-card,dai-link@0 { /* I2S - AUDIO SYS CODEC 8156*/
reg = <0>;
format = "i2s";
cpu {
sound-dai = <&i2s0 0>;
};
codec {
sound-dai = <&es8156_audio_codec>;
};
};
simple-audio-card,dai-link@1 { /* I2S - AUDIO SYS CODEC 7210*/
reg = <1>;
format = "i2s";
cpu {
sound-dai = <&i2s3 0>;
};
codec {
sound-dai = <&es7210_audio_codec>;
};
};
};
&light_i2s {
status = "okay";
};
&i2s0 {
status = "okay";
};
&i2s3 {
status = "okay";
};
&qspi0 {
status = "okay";
};
&qspi1 {
status = "okay";
};
&uart2 {
status = "okay";
};
&uart3 {
status = "okay";
};
&sdhci1 {
status = "okay";
};
&wcn_bt {
status = "okay";
};
&wcn_wifi {
status = "okay";
};

15
arch/riscv/boot/dts/thead/light-a-val-gpio-keys.dts
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@@ -1,15 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2021 Alibaba Group Holding Limited.
*/
#include "light-a-val.dts"
/ {
model = "T-HEAD Light FM GPIO-KEYS VAL board";
compatible = "thead,light-val-gpio-keys", "thead,light";
};
&gpio_keys {
status = "okay";
};

8
arch/riscv/boot/dts/thead/light-a-val-hdmi-powergate.dts
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@@ -1,8 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2021 Alibaba Group Holding Limited.
*/
#include "light-a-val-hdmi.dts"
#include "light-powergate.dts"

8
arch/riscv/boot/dts/thead/light-a-val-iso7816-powergate.dts
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@@ -1,8 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2021 Alibaba Group Holding Limited.
*/
#include "light-a-val-iso7816.dts"
#include "light-powergate.dts"

10
arch/riscv/boot/dts/thead/light-a-val-iso7816.dts
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@@ -1,10 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2021 Alibaba Group Holding Limited.
*/
#include "light-a-val.dts"
&iso7816 {
status = "okay";
};

8
arch/riscv/boot/dts/thead/light-a-val-khv-powergate.dts
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@@ -1,8 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2021 Alibaba Group Holding Limited.
*/
#include "light-a-val-khv.dts"
#include "light-powergate.dts"

21
arch/riscv/boot/dts/thead/light-a-val-khv.dts
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@@ -1,21 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2021 Alibaba Group Holding Limited.
*/
#include "light-a-val.dts"
&resmem {
#address-cells = <2>;
#size-cells = <2>;
ranges;
/* 512M for guest memory */
guestmem: memory@50000000 {
reg = <0x0 0x50000000 0x0 0x20000000>;
};
};
&khvhost {
memory-region = <&guestmem>;
};

126
arch/riscv/boot/dts/thead/light-a-val-miniapp-dsi0.dts
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@@ -1,126 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2021 Alibaba Group Holding Limited.
*/
/dts-v1/;
#include "light-a-val.dts"
/ {
display-subsystem {
status = "okay";
};
};
&dpu_enc0 {
status = "okay";
ports {
/* output */
port@1 {
reg = <1>;
enc0_out: endpoint {
remote-endpoint = <&dsi0_in>;
};
};
};
};
&dpu {
status = "okay";
};
&dsi0 {
status = "okay";
};
&dhost_0 {
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dsi0_in: endpoint {
remote-endpoint = <&enc0_out>;
};
};
port@1 {
reg = <1>;
dsi0_out: endpoint {
remote-endpoint = <&panel0_in>;
};
};
};
panel0@0 {
compatible = "txd,dy800qwxpab";
reg = <0>;
backlight = <&lcd0_backlight>;
reset-gpio = <&gpio1_porta 5 1>; /* active low */
vdd1v8-supply = <&lcd0_1v8>;
vspn5v7-supply = <&lcd0_5v7>;
port {
panel0_in: endpoint {
remote-endpoint = <&dsi0_out>;
};
};
};
};
&lightsound {
status = "okay";
simple-audio-card,dai-link@0 { /* I2S - AUDIO SYS CODEC 8156*/
reg = <0>;
format = "i2s";
cpu {
sound-dai = <&i2s0 0>;
};
codec {
sound-dai = <&es8156_audio_codec>;
};
};
simple-audio-card,dai-link@1 { /* I2S - AUDIO SYS CODEC 7210*/
reg = <1>;
format = "i2s";
cpu {
sound-dai = <&i2s3 0>;
};
codec {
sound-dai = <&es7210_audio_codec>;
};
};
};
&light_i2s {
status = "okay";
};
&i2s0 {
status = "okay";
};
&i2s3 {
status = "okay";
};
&sdhci1 {
status = "okay";
};
&wcn_bt {
status = "okay";
};
&wcn_wifi {
status = "okay";
};

8
arch/riscv/boot/dts/thead/light-a-val-miniapp-hdmi-powergate.dts
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@@ -1,8 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2021 Alibaba Group Holding Limited.
*/
#include "light-a-val-miniapp-hdmi.dts"
#include "light-powergate.dts"

90
arch/riscv/boot/dts/thead/light-a-val-miniapp-hdmi.dts
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@@ -1,90 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2021 Alibaba Group Holding Limited.
*/
/dts-v1/;
#include "light-a-val.dts"
/ {
display-subsystem {
status = "okay";
};
};
&dpu_enc1 {
ports {
/delete-node/ port@0;
};
};
&disp1_out {
remote-endpoint = <&hdmi_tx_in>;
};
&dpu {
status = "okay";
};
&hdmi_tx {
status = "okay";
port@0 {
/* input */
hdmi_tx_in: endpoint {
remote-endpoint = <&disp1_out>;
};
};
};
&lightsound {
status = "okay";
simple-audio-card,dai-link@0 { /* I2S - AUDIO SYS CODEC 8156*/
reg = <0>;
format = "i2s";
cpu {
sound-dai = <&i2s0 0>;
};
codec {
sound-dai = <&es8156_audio_codec>;
};
};
simple-audio-card,dai-link@1 { /* I2S - AUDIO SYS CODEC 7210*/
reg = <1>;
format = "i2s";
cpu {
sound-dai = <&i2s3 0>;
};
codec {
sound-dai = <&es7210_audio_codec>;
};
};
};
&light_i2s {
status = "okay";
};
&i2s0 {
status = "okay";
};
&i2s3 {
status = "okay";
};
&sdhci1 {
status = "okay";
};
&wcn_bt {
status = "okay";
};
&wcn_wifi {
status = "okay";
};

8
arch/riscv/boot/dts/thead/light-a-val-nand-powergate.dts
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@@ -1,8 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2021 Alibaba Group Holding Limited.
*/
#include "light-a-val-nand.dts"
#include "light-powergate.dts"

14
arch/riscv/boot/dts/thead/light-a-val-nand.dts
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@@ -1,14 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2021 Alibaba Group Holding Limited.
*/
#include "light-a-val.dts"
&qspi0 {
status = "okay";
};
&qspi1 {
status = "okay";
};

12
arch/riscv/boot/dts/thead/light-a-val-npu-fce-powergate.dts
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@@ -1,12 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2021 Alibaba Group Holding Limited.
*/
#include "light-a-val-npu-fce.dts"
#include "light-powergate.dts"
&npu {
power-domains = <&pd LIGHT_AON_NPU_PD>;
};

28
arch/riscv/boot/dts/thead/light-a-val-npu-fce.dts
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@@ -1,28 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2021 Alibaba Group Holding Limited.
*/
#include "light-a-val.dts"
/ {
model = "T-HEAD Light FM NPU&FCE on VAL board";
compatible = "thead,light-val-npu-fce", "thead,light";
};
&facelib_mem {
reg = <0x0 0xd0000000 0 0x20000000>;
no-map;
};
&npu {
vha_clk_rate = <1000000000>;
status = "okay";
};
&fce {
memory-region = <&facelib_mem>;
status = "okay";
};

8
arch/riscv/boot/dts/thead/light-a-val-powergate.dts
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@@ -1,8 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2021 Alibaba Group Holding Limited.
*/
#include "light-a-val.dts"
#include "light-powergate.dts"

8
arch/riscv/boot/dts/thead/light-a-val-sec-powergate.dts
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@@ -1,8 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2021 Alibaba Group Holding Limited.
*/
#include "light-a-val-sec.dts"
#include "light-powergate.dts"

8
arch/riscv/boot/dts/thead/light-a-val-sv-powergate.dts
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@@ -1,8 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2021 Alibaba Group Holding Limited.
*/
#include "light-a-val-sv.dts"
#include "light-powergate.dts"

1640
arch/riscv/boot/dts/thead/light-a-val-sv.dts
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File diff suppressed because it is too large Load Diff

8
arch/riscv/boot/dts/thead/light-a-val-wcn-powergate.dts
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@@ -1,8 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2021 Alibaba Group Holding Limited.
*/
#include "light-a-val-wcn.dts"
#include "light-powergate.dts"

20
arch/riscv/boot/dts/thead/light-a-val-wcn.dts
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@@ -1,20 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2021 Alibaba Group Holding Limited.
*/
/dts-v1/;
#include "light-a-val.dts"
&sdhci1 {
status = "okay";
};
&wcn_bt {
status = "okay";
};
&wcn_wifi {
status = "okay";
};

88
arch/riscv/boot/dts/thead/light-ant-discrete-crash.dts
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@@ -1,88 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2022 Alibaba Group Holding Limited.
*/
#include "light-crash.dts"
&aon {
aon_reg_dialog: light-dialog-reg {
compatible = "thead,light-dialog-pmic-ant";
status = "okay";
dvdd_cpu_reg: appcpu_dvdd {
regulator-name = "appcpu_dvdd";
regulator-min-microvolt = <300000>;
regulator-max-microvolt = <1570000>;
regulator-boot-on;
regulator-always-on;
};
dvddm_cpu_reg: appcpu_dvddm {
regulator-name = "appcpu_dvddm";
regulator-min-microvolt = <300000>;
regulator-max-microvolt = <1570000>;
regulator-boot-on;
regulator-always-on;
};
};
};
&cpus {
c910_0: cpu@0 {
operating-points = <
/* kHz uV */
300000 720000
800000 720000
1500000 820000
>;
light,dvddm-operating-points = <
/* kHz uV */
300000 770000
800000 820000
1500000 820000
>;
};
c910_1: cpu@1 {
operating-points = <
/* kHz uV */
300000 720000
800000 720000
1500000 820000
>;
light,dvddm-operating-points = <
/* kHz uV */
300000 770000
800000 820000
1500000 820000
>;
};
c910_2: cpu@2 {
operating-points = <
/* kHz uV */
300000 720000
800000 720000
1500000 820000
>;
light,dvddm-operating-points = <
/* kHz uV */
300000 770000
800000 820000
1500000 820000
>;
};
c910_3: cpu@3 {
operating-points = <
/* kHz uV */
300000 720000
800000 720000
1500000 820000
>;
light,dvddm-operating-points = <
/* kHz uV */
300000 770000
800000 820000
1500000 820000
>;
};
};

2380
arch/riscv/boot/dts/thead/light-ant-ref.dts
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File diff suppressed because it is too large Load Diff

134
arch/riscv/boot/dts/thead/light-b-power.dts
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@@ -1,134 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2021 Alibaba Group Holding Limited.
*/
/dts-v1/;
#include "light-b-product.dts"
&aon {
/delete-node/light-ricoh-reg;
soc_vdd18_lcd0_bk_en_reg: soc_vdd18_lcd0_bk_en {
compatible = "regulator-fixed";
regulator-name = "soc_vdd18_lcd0_bk_en";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
gpio = <&gpio1_porta 9 1>;
enable-active-high;
};
aon_reg_dialog: light-dialog-reg {
compatible = "thead,light-dialog-pmic-ant";
status = "okay";
dvdd_cpu_reg: appcpu_dvdd {
regulator-name = "appcpu_dvdd";
regulator-min-microvolt = <300000>;
regulator-max-microvolt = <1570000>;
regulator-boot-on;
regulator-always-on;
};
dvddm_cpu_reg: appcpu_dvddm {
regulator-name = "appcpu_dvddm";
regulator-min-microvolt = <300000>;
regulator-max-microvolt = <1570000>;
regulator-boot-on;
regulator-always-on;
};
soc_dvdd18_aon_reg: soc_dvdd18_aon {
regulator-name = "soc_dvdd18_aon";
regulator-boot-on;
regulator-always-on;
};
soc_avdd33_usb3_reg: soc_avdd33_usb3 {
regulator-name = "soc_avdd33_usb3";
regulator-boot-on;
regulator-always-on;
};
soc_dvdd08_aon_reg: soc_dvdd08_aon {
regulator-name = "soc_dvdd08_aon";
regulator-boot-on;
regulator-always-on;
};
soc_dvdd08_ddr_reg: soc_dvdd08_ddr {
regulator-name = "soc_dvdd08_ddr";
regulator-boot-on;
regulator-always-on;
};
soc_vdd_ddr_1v8_reg: soc_vdd_ddr_1v8 {
regulator-name = "soc_vdd_ddr_1v8";
regulator-boot-on;
regulator-always-on;
};
soc_vdd_ddr_1v1_reg: soc_vdd_ddr_1v1 {
regulator-name = "soc_vdd_ddr_1v1";
regulator-boot-on;
regulator-always-on;
};
soc_vdd_ddr_0v6_reg: soc_vdd_ddr_0v6 {
regulator-name = "soc_vdd_ddr_0v6";
regulator-boot-on;
regulator-always-on;
};
soc_dvdd18_ap_reg: soc_dvdd18_ap {
regulator-name = "soc_dvdd18_ap";
regulator-boot-on;
regulator-always-on;
};
soc_avdd08_mipi_hdmi_reg: soc_avdd08_mipi_hdmi {
regulator-name = "soc_avdd08_mipi_hdmi";
regulator-boot-on;
regulator-always-on;
};
soc_avdd18_mipi_hdmi_reg: soc_avdd18_mipi_hdmi {
regulator-name = "soc_avdd18_mipi_hdmi";
regulator-boot-on;
regulator-always-on;
};
soc_vdd33_emmc_reg: soc_vdd33_emmc {
regulator-name = "soc_vdd33_emmc";
regulator-boot-on;
regulator-always-on;
};
soc_vdd18_emmc_reg: soc_vdd18_emmc {
regulator-name = "soc_vdd18_emmc";
regulator-boot-on;
regulator-always-on;
};
#if 0
soc_dovdd18_scan_reg: soc_dovdd18_scan {
regulator-name = "soc_dovdd18_scan";
};
soc_dvdd12_scan_reg: soc_dvdd12_scan {
regulator-name = "soc_dvdd12_scan";
};
soc_avdd28_scan_en_reg: soc_avdd28_scan_en {
regulator-name = "soc_avdd28_scan_en";
};
#endif
};
};
&panel0 {
vdd1v8-supply = <&soc_vdd18_lcd0_bk_en_reg>;
};

14
arch/riscv/boot/dts/thead/light-b-product-ddr1G-powergate.dts
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@@ -1,14 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2021 Alibaba Group Holding Limited.
*/
#include "light-b-product-ddr1G.dts"
#include "light-powergate.dts"
&soc_vdd18_lcd0_en_reg {
/delete-property/regulator-always-on;
};
&soc_lcd0_bias_en_reg {
/delete-property/regulator-always-on;
};

21
arch/riscv/boot/dts/thead/light-b-product-ddr1G.dts
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@@ -1,21 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2022 Alibaba Group Holding Limited.
*/
#include "light-b-product.dts"
/ {
model = "T-HEAD Light-B VAL configuration for 1GB DDR board";
compatible = "thead,light-val", "thead,light-val-ddr1G", "thead,light";
memory@0 {
device_type = "memory";
reg = <0x0 0x00000000 0x0 0x40000000>;
};
};
&cmamem {
size = <0 0x8c00000>; // 140MB by default
alloc-ranges = <0 0x02000000 0 0x0cc000000>; // [0x0600_0000 ~ 0x0EC0_0000]
};

28
arch/riscv/boot/dts/thead/light-b-product-miniapp-hdmi.dts
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@@ -1,28 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2021 Alibaba Group Holding Limited.
*/
/dts-v1/;
#include "light-b-product.dts"
&dpu_enc0 {
status = "disabled";
};
&dsi0 {
status = "disabled";
};
&dhost_0 {
status = "disabled";
};
&wcn_bt {
status = "okay";
};
&wcn_wifi {
status = "okay";
};

16
arch/riscv/boot/dts/thead/light-b-product-powergate.dts
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@@ -1,16 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2021 Alibaba Group Holding Limited.
*/
#include "light-b-product.dts"
#include "light-powergate.dts"
&soc_vdd18_lcd0_en_reg {
/delete-property/regulator-always-on;
};
&soc_lcd0_bias_en_reg {
/delete-property/regulator-always-on;
};

8
arch/riscv/boot/dts/thead/light-b-product-sec-powergate.dts
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@@ -1,8 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2021 Alibaba Group Holding Limited.
*/
#include "light-b-product-sec.dts"
#include "light-powergate.dts"

134
arch/riscv/boot/dts/thead/light-b-ref.dts
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@@ -1,134 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2021 Alibaba Group Holding Limited.
*/
/dts-v1/;
#include "light-b-product.dts"
&aon {
/delete-node/light-ricoh-reg;
soc_vdd18_lcd0_bk_en_reg: soc_vdd18_lcd0_bk_en {
compatible = "regulator-fixed";
regulator-name = "soc_vdd18_lcd0_bk_en";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
gpio = <&gpio1_porta 9 1>;
enable-active-high;
};
aon_reg_dialog: light-dialog-reg {
compatible = "thead,light-dialog-pmic-ant";
status = "okay";
dvdd_cpu_reg: appcpu_dvdd {
regulator-name = "appcpu_dvdd";
regulator-min-microvolt = <300000>;
regulator-max-microvolt = <1570000>;
regulator-boot-on;
regulator-always-on;
};
dvddm_cpu_reg: appcpu_dvddm {
regulator-name = "appcpu_dvddm";
regulator-min-microvolt = <300000>;
regulator-max-microvolt = <1570000>;
regulator-boot-on;
regulator-always-on;
};
soc_dvdd18_aon_reg: soc_dvdd18_aon {
regulator-name = "soc_dvdd18_aon";
regulator-boot-on;
regulator-always-on;
};
soc_avdd33_usb3_reg: soc_avdd33_usb3 {
regulator-name = "soc_avdd33_usb3";
regulator-boot-on;
regulator-always-on;
};
soc_dvdd08_aon_reg: soc_dvdd08_aon {
regulator-name = "soc_dvdd08_aon";
regulator-boot-on;
regulator-always-on;
};
soc_dvdd08_ddr_reg: soc_dvdd08_ddr {
regulator-name = "soc_dvdd08_ddr";
regulator-boot-on;
regulator-always-on;
};
soc_vdd_ddr_1v8_reg: soc_vdd_ddr_1v8 {
regulator-name = "soc_vdd_ddr_1v8";
regulator-boot-on;
regulator-always-on;
};
soc_vdd_ddr_1v1_reg: soc_vdd_ddr_1v1 {
regulator-name = "soc_vdd_ddr_1v1";
regulator-boot-on;
regulator-always-on;
};
soc_vdd_ddr_0v6_reg: soc_vdd_ddr_0v6 {
regulator-name = "soc_vdd_ddr_0v6";
regulator-boot-on;
regulator-always-on;
};
soc_dvdd18_ap_reg: soc_dvdd18_ap {
regulator-name = "soc_dvdd18_ap";
regulator-boot-on;
regulator-always-on;
};
soc_avdd08_mipi_hdmi_reg: soc_avdd08_mipi_hdmi {
regulator-name = "soc_avdd08_mipi_hdmi";
regulator-boot-on;
regulator-always-on;
};
soc_avdd18_mipi_hdmi_reg: soc_avdd18_mipi_hdmi {
regulator-name = "soc_avdd18_mipi_hdmi";
regulator-boot-on;
regulator-always-on;
};
soc_vdd33_emmc_reg: soc_vdd33_emmc {
regulator-name = "soc_vdd33_emmc";
regulator-boot-on;
regulator-always-on;
};
soc_vdd18_emmc_reg: soc_vdd18_emmc {
regulator-name = "soc_vdd18_emmc";
regulator-boot-on;
regulator-always-on;
};
#if 0
soc_dovdd18_scan_reg: soc_dovdd18_scan {
regulator-name = "soc_dovdd18_scan";
};
soc_dvdd12_scan_reg: soc_dvdd12_scan {
regulator-name = "soc_dvdd12_scan";
};
soc_avdd28_scan_en_reg: soc_avdd28_scan_en {
regulator-name = "soc_avdd28_scan_en";
};
#endif
};
};
&panel0 {
vdd1v8-supply = <&soc_vdd18_lcd0_bk_en_reg>;
};

608
arch/riscv/boot/dts/thead/light-beagle.dts
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@@ -1,608 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2021 Alibaba Group Holding Limited.
*/
/dts-v1/;
#include "light-ant-ref.dts"
&vvcam_sensor4 { // beagle board J5 CSI0 connector
sensor_name = "IMX219";
sensor_pdn = <&gpio2_porta 23 0>; //powerdown pin / shutdown pin
sensor_pdn_delay_us = <2000>; //powerdown pin / shutdown pin actived till I2C ready
i2c_addr = /bits/ 8 <0x10>;
i2c_bus = /bits/ 8 <1>;
i2c_reg_width = /bits/ 8 <2>;
i2c_data_width = /bits/ 8 <1>;
status = "okay";
};
&vvcam_sensor5 { // beagle board J4 CSI1 connector
sensor_name = "IMX219";
sensor_pdn = <&gpio2_porta 24 0>; //powerdown pin / shutdown pin
sensor_pdn_delay_us = <2000>; //powerdown pin / shutdown pin actived till I2C ready
i2c_addr = /bits/ 8 <0x10>;
i2c_bus = /bits/ 8 <3>;
i2c_reg_width = /bits/ 8 <2>;
i2c_data_width = /bits/ 8 <1>;
status = "okay";
};
/*
sensor imx219 mounted on beagle board J4
video0: sensor-vipre-isp0
video1: sensor-vipre-isp0-dw
video7: sensor-vipre-isp0-dsp1-ry-dw
video10: tuningtool
sensor imx219 mounted on beagle board J5
video2: sensor-vipre-isp1
video3: sensor-vipre-isp1-dw
video4: sensor-vipre-isp1-dsp0-ry
video5: sensor-vipre-isp1-dsp0-ry-dw
video12: tuningtool
*/
&video2 {
vi_mem_pool_region = <0>; // vi_mem: framebuffer, region[0]
status = "okay";
pipline0 {
pipline_id = <0>;
status = "okay";
sensor0 {
subdev_name = "vivcam";
idx = <4>; // imx219
csi_idx = <0>; //<0>=CSI2
mode_idx = <0>;
path_type = "SENSOR_1080P_RAW10_LINER";
};
sensor1 {
subdev_name = "vivcam";
idx = <0xff>; // invalid
csi_idx = <0xff>;
path_type = "SENSOR_VGA_RAW10_LINER";
};
dma {
subdev_name = "vipre";
idx = <0>;
path_type = "VIPRE_CSI0_ISP1";
};
isp {
subdev_name = "isp";
idx = <1>;
path_type = "ISP_MI_PATH_MP";
output {
max_width = <1920>;
max_height = <1088>;
bit_per_pixel = <16>;
frame_count = <3>;
};
};
};
pipline1 {
pipline_id = <1>;
status = "okay";
sensor0 {
subdev_name = "vivcam";
idx = <4>; // imx219
csi_idx = <0>; //<0>=CSI2
mode_idx = <0>;
path_type = "SENSOR_1080P_RAW10_LINER";
};
sensor1 {
subdev_name = "vivcam";
idx = <0xff>; // invalid
csi_idx = <0xff>;
path_type = "SENSOR_VGA_RAW10_LINER";
};
dma {
subdev_name = "vipre";
idx = <0>;
path_type = "VIPRE_CSI0_ISP1";
};
isp {
subdev_name = "isp";
idx = <1>;
path_type = "ISP_MI_PATH_SP";
output {
max_width = <1920>;
max_height = <1088>;
bit_per_pixel = <16>;
frame_count = <3>;
};
};
};
pipline2 {
pipline_id = <2>;
status = "okay";
sensor0 {
subdev_name = "vivcam";
idx = <4>; // imx219
csi_idx = <0>; //<0>=CSI2
mode_idx = <0>;
path_type = "SENSOR_1080P_RAW10_LINER";
};
sensor1 {
subdev_name = "vivcam";
idx = <0xff>; // invalid
csi_idx = <0xff>;
path_type = "SENSOR_VGA_RAW10_LINER";
};
dma {
subdev_name = "vipre";
idx = <0>;
path_type = "VIPRE_CSI0_ISP1";
};
isp {
subdev_name = "isp";
idx = <1>;
path_type = "ISP_MI_PATH_SP2_BP";
output {
max_width = <1920>;
max_height = <1088>;
bit_per_pixel = <16>;
frame_count = <3>;
};
};
};
};
&video3{
vi_mem_pool_region = <0>; // vi_mem: framebuffer, region[0]
pipline0 {
sensor0 {
subdev_name = "vivcam";
idx = <4>; // imx219
csi_idx = <0>; //<0>=CSI2
mode_idx = <0>;
path_type = "SENSOR_1080P_RAW10_LINER";
};
sensor1 {
subdev_name = "vivcam";
idx = <0xff>; // invalid
csi_idx = <0xff>;
path_type = "SENSOR_VGA_RAW10_LINER";
};
dma {
subdev_name = "vipre";
idx = <0>;
path_type = "VIPRE_CSI0_ISP1";
};
isp {
subdev_name = "isp";
idx = <1>;
path_type = "ISP_MI_PATH_MP";
output {
max_width = <1920>;
max_height = <1088>;
bit_per_pixel = <12>;
frame_count = <3>;
};
};
dw {
subdev_name = "dw";
idx = <0>;
path_type = "DW_DWE_VSE0";
dw_dst_depth = <2>;
};
};
pipline1 {
sensor0 {
subdev_name = "vivcam";
idx = <4>; // imx219
csi_idx = <0>; //<0>=CSI2
mode_idx = <0>;
path_type = "SENSOR_1080P_RAW10_LINER";
};
sensor1 {
subdev_name = "vivcam";
idx = <0xff>; // invalid
csi_idx = <0xff>;
path_type = "SENSOR_VGA_RAW10_LINER";
};
dma {
subdev_name = "vipre";
idx = <0>;
path_type = "VIPRE_CSI0_ISP1";
};
isp {
subdev_name = "isp";
idx = <1>;
path_type = "ISP_MI_PATH_MP";
output {
max_width = <1920>;
max_height = <1088>;
bit_per_pixel = <12>;
frame_count = <3>;
};
};
dw {
subdev_name = "dw";
idx = <0>;
path_type = "DW_DWE_VSE1";
dw_dst_depth = <2>;
};
};
pipline2 {
sensor0 {
subdev_name = "vivcam";
idx = <4>; // imx219
csi_idx = <0>; //<0>=CSI2
mode_idx = <0>;
path_type = "SENSOR_1080P_RAW10_LINER";
};
sensor1 {
subdev_name = "vivcam";
idx = <0xff>; // invalid
csi_idx = <0xff>;
path_type = "SENSOR_VGA_RAW10_LINER";
};
dma {
subdev_name = "vipre";
idx = <0>;
path_type = "VIPRE_CSI0_ISP1";
};
isp {
subdev_name = "isp";
idx = <1>;
path_type = "ISP_MI_PATH_MP";
output {
max_width = <1920>;
max_height = <1088>;
bit_per_pixel = <12>;
frame_count = <3>;
};
};
dw {
subdev_name = "dw";
idx = <0>;
path_type = "DW_DWE_VSE2";
dw_dst_depth = <2>;
};
};
};
&video4{
vi_mem_pool_region = <0>; // vi_mem: framebuffer, region[0]
pipline0 {
sensor0 {
subdev_name = "vivcam";
idx = <4>; // imx219
csi_idx = <0>; //<0>=CSI2
mode_idx = <0>;
path_type = "SENSOR_1080P_RAW10_LINER";
};
sensor1 {
subdev_name = "vivcam";
idx = <0xff>; // invalid
csi_idx = <0xff>;
path_type = "SENSOR_VGA_RAW10_LINER";
};
dma {
subdev_name = "vipre";
idx = <0>;
path_type = "VIPRE_CSI0_ISP1";
};
isp {
subdev_name = "isp";
idx = <1>;
path_type = "ISP_MI_PATH_PP";
output {
max_width = <1920>;
max_height = <1088>;
bit_per_pixel = <12>;
frame_count = <3>;
};
};
dsp {
subdev_name = "dsp";
idx = <0>;
path_type = "DSP_PATH_ISP_RY";
output {
max_width = <1920>;
max_height = <1088>;
bit_per_pixel = <12>;
frame_count = <3>;
};
};
ry {
subdev_name = "ry";
idx = <0>;
path_type = "ISP_RY_MI_PATH_MP";
output {
max_width = <1920>;
max_height = <1088>;
bit_per_pixel = <12>;
frame_count = <3>;
};
};
};
pipline1 {
sensor0 {
subdev_name = "vivcam";
idx = <4>; // imx219
csi_idx = <0>; //<0>=CSI2
mode_idx = <0>;
path_type = "SENSOR_1080P_RAW10_LINER";
};
sensor1 {
subdev_name = "vivcam";
idx = <0xff>; // invalid
csi_idx = <0xff>;
path_type = "SENSOR_VGA_RAW10_LINER";
};
dma {
subdev_name = "vipre";
idx = <0>;
path_type = "VIPRE_CSI0_ISP1";
};
isp {
subdev_name = "isp";
idx = <1>;
path_type = "ISP_MI_PATH_PP";
output {
max_width = <1920>;
max_height = <1088>;
bit_per_pixel = <12>;
frame_count = <3>;
};
};
dsp {
subdev_name = "dsp";
idx = <0>;
path_type = "DSP_PATH_ISP_RY";
output {
max_width = <1920>;
max_height = <1088>;
bit_per_pixel = <12>;
frame_count = <3>;
};
};
ry {
subdev_name = "ry";
idx = <0>;
path_type = "ISP_RY_MI_PATH_SP";
output {
max_width = <1920>;
max_height = <1088>;
bit_per_pixel = <12>;
frame_count = <3>;
};
};
};
pipline2 {
sensor0 {
subdev_name = "vivcam";
idx = <4>; // imx219
csi_idx = <0>; //<0>=CSI2
mode_idx = <0>;
path_type = "SENSOR_1080P_RAW10_LINER";
};
sensor1 {
subdev_name = "vivcam";
idx = <0xff>; // invalid
csi_idx = <0xff>;
path_type = "SENSOR_VGA_RAW10_LINER";
};
dma {
subdev_name = "vipre";
idx = <0>;
path_type = "VIPRE_CSI0_ISP1";
};
isp {
subdev_name = "isp";
idx = <1>;
path_type = "ISP_MI_PATH_PP";
output {
max_width = <1920>;
max_height = <1088>;
bit_per_pixel = <12>;
frame_count = <3>;
};
};
dsp {
subdev_name = "dsp";
idx = <0>;
path_type = "DSP_PATH_ISP_RY";
output {
max_width = <1920>;
max_height = <1088>;
bit_per_pixel = <12>;
frame_count = <3>;
};
};
ry {
subdev_name = "ry";
idx = <0>;
path_type = "ISP_RY_MI_PATH_SP2_BP";
output {
max_width = <1920>;
max_height = <1088>;
bit_per_pixel = <12>;
frame_count = <3>;
};
};
};
};
&video5{
vi_mem_pool_region = <0>; // vi_mem: framebuffer, region[0]
pipline0 {
sensor0 {
subdev_name = "vivcam";
idx = <4>; // imx219
csi_idx = <0>; //<0>=CSI2
mode_idx = <0>;
path_type = "SENSOR_1080P_RAW10_LINER";
};
sensor1 {
subdev_name = "vivcam";
idx = <0xff>; // invalid
csi_idx = <0xff>;
path_type = "SENSOR_VGA_RAW10_LINER";
};
dma {
subdev_name = "vipre";
idx = <0>;
path_type = "VIPRE_CSI0_ISP1";
};
isp {
subdev_name = "isp";
idx = <1>;
path_type = "ISP_MI_PATH_PP";
output {
max_width = <1920>;
max_height = <1088>;
bit_per_pixel = <12>;
frame_count = <3>;
};
};
dsp {
subdev_name = "dsp";
idx = <0>;
path_type = "DSP_PATH_ISP_RY";
output {
max_width = <1920>;
max_height = <1088>;
bit_per_pixel = <12>;
frame_count = <3>;
};
};
ry {
subdev_name = "ry";
idx = <0>;
path_type = "ISP_RY_MI_PATH_MP";
output {
max_width = <1920>;
max_height = <1088>;
bit_per_pixel = <12>;
frame_count = <3>;
};
};
dw {
subdev_name = "dw";
idx = <0>;
path_type = "DW_DWE_VSE0";
dw_dst_depth = <2>;
};
};
pipline1 {
sensor0 {
subdev_name = "vivcam";
idx = <4>; // imx219
csi_idx = <0>; //<0>=CSI2
mode_idx = <0>;
path_type = "SENSOR_1080P_RAW10_LINER";
};
sensor1 {
subdev_name = "vivcam";
idx = <0xff>; // invalid
csi_idx = <0xff>;
path_type = "SENSOR_VGA_RAW10_LINER";
};
dma {
subdev_name = "vipre";
idx = <0>;
path_type = "VIPRE_CSI0_ISP1";
};
isp {
subdev_name = "isp";
idx = <1>;
path_type = "ISP_MI_PATH_PP";
output {
max_width = <1920>;
max_height = <1088>;
bit_per_pixel = <12>;
frame_count = <3>;
};
};
dsp {
subdev_name = "dsp";
idx = <0>;
path_type = "DSP_PATH_ISP_RY";
output {
max_width = <1920>;
max_height = <1088>;
bit_per_pixel = <12>;
frame_count = <3>;
};
};
ry {
subdev_name = "ry";
idx = <0>;
path_type = "ISP_RY_MI_PATH_MP";
output {
max_width = <1920>;
max_height = <1088>;
bit_per_pixel = <12>;
frame_count = <3>;
};
};
dw {
subdev_name = "dw";
idx = <0>;
path_type = "DW_DWE_VSE1";
dw_dst_depth = <2>;
};
};
pipline2 {
sensor0 {
subdev_name = "vivcam";
idx = <4>; // imx219
csi_idx = <0>; //<0>=CSI2
mode_idx = <0>;
path_type = "SENSOR_1080P_RAW10_LINER";
};
sensor1 {
subdev_name = "vivcam";
idx = <0xff>; // invalid
csi_idx = <0xff>;
path_type = "SENSOR_VGA_RAW10_LINER";
};
dma {
subdev_name = "vipre";
idx = <0>;
path_type = "VIPRE_CSI0_ISP1";
};
isp {
subdev_name = "isp";
idx = <1>;
path_type = "ISP_MI_PATH_PP";
output {
max_width = <1920>;
max_height = <1088>;
bit_per_pixel = <12>;
frame_count = <3>;
};
};
dsp {
subdev_name = "dsp";
idx = <0>;
path_type = "DSP_PATH_ISP_RY";
output {
max_width = <1920>;
max_height = <1088>;
bit_per_pixel = <12>;
frame_count = <3>;
};
};
ry {
subdev_name = "ry";
idx = <0>;
path_type = "ISP_RY_MI_PATH_MP";
output {
max_width = <1920>;
max_height = <1088>;
bit_per_pixel = <12>;
frame_count = <3>;
};
};
dw {
subdev_name = "dw";
idx = <0>;
path_type = "DW_DWE_VSE2";
dw_dst_depth = <2>;
};
};
};

1536
arch/riscv/boot/dts/thead/light-emu.dtsi
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1941
arch/riscv/boot/dts/thead/light-evb.dtsi
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File diff suppressed because it is too large Load Diff

19
arch/riscv/boot/dts/thead/light-fm-emu-audio.dts
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@@ -1,19 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2021 Alibaba Group Holding Limited.
*/
#include "light-fm-emu.dts"
/ {
model = "T-HEAD Light FM EMP Audio FPGA board";
compatible = "thead,light-fm-emu-audio", "thead,light";
};
&lightsound {
status = "okay";
};
&light_i2s {
status = "okay";
};

16
arch/riscv/boot/dts/thead/light-fm-emu-dsi0-hdmi.dts
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@@ -1,16 +0,0 @@
#include "light-fm-emu-dsi0.dts"
&disp1_out {
remote-endpoint = <&hdmi_tx_in>;
};
&hdmi_tx {
status = "okay";
port@0 {
/* input */
hdmi_tx_in: endpoint {
remote-endpoint = <&disp1_out>;
};
};
};

64
arch/riscv/boot/dts/thead/light-fm-emu-dsi0.dts
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@@ -1,64 +0,0 @@
#include "light-fm-emu.dts"
/ {
display-subsystem {
status = "okay";
};
};
&dpu_enc0 {
status = "okay";
ports {
/* output */
port@1 {
reg = <1>;
enc0_out: endpoint {
remote-endpoint = <&dsi0_in>;
};
};
};
};
&dpu {
status = "okay";
};
&dsi0 {
status = "okay";
};
&dhost_0 {
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dsi0_in: endpoint {
remote-endpoint = <&enc0_out>;
};
};
port@1 {
reg = <1>;
dsi0_out: endpoint {
remote-endpoint = <&panel_in>;
};
};
};
panel@0 {
compatible = "hlt,hpk070h275";
reg = <0>;
port {
panel_in: endpoint {
remote-endpoint = <&dsi0_out>;
};
};
};
};

34
arch/riscv/boot/dts/thead/light-fm-emu-dsp.dts
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@@ -1,34 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2021 Alibaba Group Holding Limited.
*/
#include "light-fm-emu.dts"
/ {
model = "T-HEAD Light FM EMU DSP FPGA board";
compatible = "thead,light-fm-emu-dsp", "thead,light";
chosen {
linux,initrd-end = <0x0 0x1B000000>;
};
};
&resmem {
dsp_mem: memory@70000000 {
reg = <0x0 0x70000000 0 0x40000000>;
no-map;
};
};
&xtensa_dsp {
status = "okay";
};
&xtensa_dsp0 {
status = "okay";
};
&xtensa_dsp1 {
status = "disabled";
};

20
arch/riscv/boot/dts/thead/light-fm-emu-gpu.dts
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@@ -1,20 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2021 Alibaba Group Holding Limited.
*/
#include "light-fm-emu.dts"
/ {
model = "T-HEAD Light FM EMU GPU FPGA board";
compatible = "thead,light-fm-emu-gpu", "thead,light";
chosen {
linux,initrd-end = <0x0 0x18000000>;
};
};
&gpu {
status = "okay";
};

26
arch/riscv/boot/dts/thead/light-fm-emu-hdmi.dts
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@@ -1,26 +0,0 @@
#include "light-fm-emu.dts"
/ {
display-subsystem {
status = "okay";
};
};
&disp1_out {
remote-endpoint = <&hdmi_tx_in>;
};
&dpu {
status = "okay";
};
&hdmi_tx {
status = "okay";
port@0 {
/* input */
hdmi_tx_in: endpoint {
remote-endpoint = <&disp1_out>;
};
};
};

37
arch/riscv/boot/dts/thead/light-fm-emu-npu-fce.dts
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@@ -1,37 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2021 Alibaba Group Holding Limited.
*/
#include "light-fm-emu.dts"
/ {
model = "T-HEAD Light FM EMU NPU&FCE FPGA board";
compatible = "thead,light-fm-emu-npu-fce", "thead,light";
chosen {
linux,initrd-end = <0x0 0x1B000000>;
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
facelib_mem: memory@e0000000 {
reg = <0x1 0xe0000000 0 0x20000000>;
no-map;
};
};
};
&npu {
vha_clk_rate = <13000000>;
status = "okay";
};
&fce {
memory-region = <&facelib_mem>;
status = "okay";
};

511
arch/riscv/boot/dts/thead/light-fm-emu.dts
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@@ -1,511 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2021 Alibaba Group Holding Limited.
*/
/dts-v1/;
#include "light-emu.dtsi"
/ {
model = "T-HEAD Light FM EMU FPGA board";
compatible = "thead,light-fm-emu", "thead,light";
chosen {
bootargs = "console=ttyS0,115200 crashkernel=256M-:128M earlycon sram=0xffe0000000,0x180000";
linux,initrd-start = <0x0 0x2000000>;
linux,initrd-end = <0x0 0x4600000>;
stdout-path = "serial0:115200n8";
};
keys {
compatible = "gpio-keys";
key0 {
label = "key0";
gpios = <&gpio1_porta 7 1>; /* GPIO_ACTIVE_LOW: 1 */
linux,code = <59>; /* KEY_F1: 59 */
status = "okay";
};
};
leds {
compatible = "gpio-leds";
led0 {
label = "led0";
gpios = <&gpio1_porta 8 0>; /* GPIO_ACTIVE_HIGH: 0 */
default-state = "off";
};
};
iopmp {
compatible = "thead,light-iopmp";
/* config#1: multiple valid regions */
iopmp_emmc: IOPMP_EMMC {
regions = <0x000000 0x100000>,
<0x100000 0x200000>;
attr = <0xFFFFFFFF>;
dummy_slave= <0x800000>;
};
/* config#2: iopmp bypass */
iopmp_sdio0: IOPMP_SDIO0 {
bypass_en;
};
/* config#3: iopmp default region set */
iopmp_sdio1: IOPMP_SDIO1 {
attr = <0xFFFFFFFF>;
is_default_region;
};
iopmp_usb0: IOPMP_USB0 {
attr = <0xFFFFFFFF>;
is_default_region;
};
iopmp_ao: IOPMP_AO {
is_default_region;
};
iopmp_aud: IOPMP_AUD {
is_default_region;
};
iopmp_chip_dbg: IOPMP_CHIP_DBG {
is_default_region;
};
iopmp_eip120i: IOPMP_EIP120I {
is_default_region;
};
iopmp_eip120ii: IOPMP_EIP120II {
is_default_region;
};
iopmp_eip120iii: IOPMP_EIP120III {
is_default_region;
};
iopmp_isp0: IOPMP_ISP0 {
is_default_region;
};
iopmp_isp1: IOPMP_ISP1 {
is_default_region;
};
iopmp_dsp: IOPMP_DSP {
is_default_region;
};
iopmp_dw200: IOPMP_DW200 {
is_default_region;
};
iopmp_venc: IOPMP_VENC {
is_default_region;
};
iopmp_vdec: IOPMP_VDEC {
is_default_region;
};
iopmp_g2d: IOPMP_G2D {
is_default_region;
};
iopmp_fce: IOPMP_FCE {
is_default_region;
};
iopmp_npu: IOPMP_NPU {
is_default_region;
};
iopmp0_dpu: IOPMP0_DPU {
bypass_en;
};
iopmp1_dpu: IOPMP1_DPU {
bypass_en;
};
iopmp_gpu: IOPMP_GPU {
is_default_region;
};
iopmp_gmac1: IOPMP_GMAC1 {
is_default_region;
};
iopmp_gmac2: IOPMP_GMAC2 {
is_default_region;
};
iopmp_dmac: IOPMP_DMAC {
is_default_region;
};
iopmp_tee_dmac: IOPMP_TEE_DMAC {
is_default_region;
};
};
mbox_910t_client1: mbox_910t_client1 {
compatible = "thead,light-mbox-client";
mbox-names = "902";
mboxes = <&mbox_910t 1 0>;
status = "disabled";
};
mbox_910t_client2: mbox_910t_client2 {
compatible = "thead,light-mbox-client";
mbox-names = "906";
mboxes = <&mbox_910t 2 0>;
status = "disabled";
};
lightsound: lightsound@1 {
compatible = "simple-audio-card";
simple-audio-card,name = "Light-Sound-Card";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
simple-audio-card,dai-link@0 { /* I2S - CODEC */
reg = <0>;
format = "i2s";
cpu {
sound-dai = <&light_i2s 0>;
};
codec {
sound-dai = <&dummy_codec 2>;
};
};
simple-audio-card,dai-link@1 { /* I2S - HDMI */
reg = <1>;
format = "i2s";
cpu {
sound-dai = <&light_i2s 1>;
};
codec {
sound-dai = <&dummy_codec 2>;
};
};
};
dummy_codec: dummy_codec {
#sound-dai-cells = <1>;
compatible = "linux,bt-sco";
status = "okay";
};
};
&i2c0 {
clock-frequency = <100000>;
status = "okay";
eeprom@50 {
compatible = "atmel,24c32";
reg = <0x50>;
pagesize = <32>;
};
};
&spi0 {
num-cs = <2>;
cs-gpios = <&gpio2_porta 15 0>, // GPIO_ACTIVE_HIGH: 0
<&gpio2_porta 23 0>; // GPIO_ACTIVE_LOW: 1
status = "okay";
spi_norflash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "winbond,w25q64", "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <8000000>;
w25q,fast-read;
};
spidev@1 {
compatible = "spidev";
#address-cells = <1>;
#size-cells = <1>;
reg = <1>;
spi-max-frequency = <12500000>;
};
};
&uart0 {
clock-frequency = <50000000>;
};
&qspi0 {
num-cs = <2>;
cs-gpios = <&gpio2_porta 3 0>, // GPIO_ACTIVE_HIGH: 0
<&gpio2_porta 26 0>;
status = "okay";
spi-flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spi-nand";
spi-max-frequency = <10000000>;
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
reg = <0>;
partition@0 {
label = "ubi1";
reg = <0x00000000 0x08000000>;
};
};
spidev@1 {
compatible = "spidev";
#address-cells = <1>;
#size-cells = <1>;
reg = <1>;
spi-max-frequency = <6250000>;
};
};
&gmac0 {
max-speed = <100>;
phy-mode = "mii";
phy-handle = <&phy_88E1111_0>;
status = "okay";
mdio0 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,dwmac-mdio";
phy_88E1111_0: ethernet-phy@0 {
reg = <0x0 0x0>;
};
};
};
&gmac1 {
max-speed = <100>;
phy-mode = "mii";
phy-handle = <&phy_88E1111_1>;
status = "disabled";
mdio0 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,dwmac-mdio";
phy_88E1111_1: ethernet-phy@0 {
reg = <0x0 0x0>;
};
};
};
&emmc {
max-frequency = <50000000>;
non-removable;
no-sdio;
no-sd;
bus-width = <8>;
status = "okay";
};
&sdhci0 {
max-frequency = <50000000>;
no-1-8-v;
bus-width = <4>;
status = "okay";
};
&padctrl0_apsys {
light-fm-evb {
/*
* Pin Configuration Node:
* Format: <pin_id mux_node config>
*/
pinctrl_uart0: uart0grp {
thead,pins = <
FM_UART0_TXD 0x0 0x72
FM_UART0_RXD 0x0 0x72
>;
};
pinctrl_spi0: spi0grp {
thead,pins = <
FM_SPI_CSN 0x0 0x72
>;
};
pinctrl_qspi0: qspi0grp {
thead,pins = <
FM_QSPI0_CSN0 0x0 0x72
>;
};
};
};
&padctrl1_apsys {
light-fm-evb {
/*
* Pin Configuration Node:
* Format: <pin_id mux_node config>
*/
pinctrl_uart3: uart3grp {
thead,pins = <
FM_UART3_TXD 0x0 0x72
FM_UART3_RXD 0x0 0x72
>;
};
pinctrl_uart4: uart4grp {
thead,pins = <
FM_UART4_TXD 0x0 0x72
FM_UART4_RXD 0x0 0x72
FM_UART4_CTSN 0x0 0x72
FM_UART4_RTSN 0x0 0x72
>;
};
};
};
&padctrl_aosys {
light-fm-evb {
/*
* Pin Configuration Node:
* Format: <pin_id mux_node config>
*/
pinctrl_audiopa1: audiopa1_grp {
thead,pins = <
FM_AUDIO_PA1 0x3 0x72
>;
};
pinctrl_audiopa2: audiopa2_grp {
thead,pins = <
FM_AUDIO_PA2 0x0 0x72
>;
};
};
};
&i2c2 {
status = "okay";
};
&isp0 {
status = "okay";
};
&isp1 {
status = "okay";
};
&isp_ry0 {
status = "okay";
};
&dewarp {
status = "okay";
};
&dec400_isp0 {
status = "okay";
};
&dec400_isp1 {
status = "okay";
};
&dec400_isp2 {
status = "okay";
};
&bm_visys {
status = "okay";
};
&bm_csi0 {
status = "okay";
};
&vi_pre {
status = "okay";
};
&vvcam_sensor0 {
sensor_name = "OV5693";
status = "okay";
};
&video{
status = "okay";
piplane0 {
pipline_id = <0>;
status = "okay";
sensor0 {
subdev_name = "vivcam";
idx = <0>;
csi_idx = <0>;
path_type = "SENSOR_VGA_RAW10_LINER";
};
/*
csi0 {
subdev_name = "bm_csi";
idx = <0>;
};
*/
dma {
subdev_name = "vipre";
idx = <0>;
path_type = "VIPRE_CSI0_ISP0";
};
isp {
subdev_name = "isp";
idx = <0>;
path_type = "ISP_MI_PATH_PP";
};
dsp {
subdev_name = "dsp";
idx = <0>;
path_type = "DSP_PATH_ISP_RY";
};
ry {
subdev_name = "ry";
idx = <0>;
path_type = "ISP_RY_MI_PATH_MP";
};
dw {
subdev_name = "dw";
idx = <0>;
path_type = "DW_PATH_MEM_DW_SC_MEM";
};
};
};
&vdec {
status = "okay";
};
&venc {
status = "okay";
};
&isp_venc_shake {
status = "okay";
};
&vidmem {
status = "okay";
};

99
arch/riscv/boot/dts/thead/light-powergate.dts
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@@ -1,99 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2021 Alibaba Group Holding Limited.
*/
&npu {
power-domains = <&pd LIGHT_AON_NPU_PD>;
};
&gpu {
power-domains = <&pd LIGHT_AON_GPU_PD>;
};
&vdec {
power-domains = <&pd LIGHT_AON_VDEC_PD>;
};
&venc {
power-domains = <&pd LIGHT_AON_VENC_PD>;
};
&xtensa_dsp0 {
power-domains = <&pd LIGHT_AON_DSP0_PD>;
clocks = <&dspsys_clk_gate CLKGEN_DSP0_PCLK>, <&dspsys_clk_gate CLKGEN_DSP0_CCLK>;
clock-names = "pclk", "cclk";
};
&xtensa_dsp1 {
power-domains = <&pd LIGHT_AON_DSP1_PD>;
clocks = <&dspsys_clk_gate CLKGEN_DSP1_PCLK>, <&dspsys_clk_gate CLKGEN_DSP1_CCLK>;
clock-names = "pclk", "cclk";
};
&isp0 {
clocks = <&visys_clk_gate LIGHT_CLKGEN_ISP0_ACLK>,
<&visys_clk_gate LIGHT_CLKGEN_ISP0_HCLK>,
<&visys_clk_gate LIGHT_CLKGEN_ISP0_PIXELCLK>,
<&visys_clk_gate LIGHT_CLKGEN_ISP0_CLK>;
clock-names = "aclk", "hclk", "isp0_pclk", "cclk";
};
&isp1 {
clocks = <&visys_clk_gate LIGHT_CLKGEN_ISP0_ACLK>,
<&visys_clk_gate LIGHT_CLKGEN_ISP0_HCLK>,
<&visys_clk_gate LIGHT_CLKGEN_ISP0_PIXELCLK>,
<&visys_clk_gate LIGHT_CLKGEN_ISP1_CLK>,
<&visys_clk_gate LIGHT_CLKGEN_ISP1_PIXELCLK>;
clock-names = "aclk", "hclk", "isp0_pclk", "cclk", "isp1_pclk";
};
&isp_ry0 {
clocks = <&visys_clk_gate LIGHT_CLKGEN_ISP_RY_ACLK>,
<&visys_clk_gate LIGHT_CLKGEN_ISP_RY_HCLK>,
<&visys_clk_gate LIGHT_CLKGEN_ISP_RY_CCLK>;
clock-names = "aclk", "hclk", "cclk";
};
&dewarp {
clocks = <&visys_clk_gate LIGHT_CLKGEN_DW200_ACLK>,
<&visys_clk_gate LIGHT_CLKGEN_DW200_HCLK>,
<&visys_clk_gate LIGHT_CLKGEN_DW200_CLK_VSE>,
<&visys_clk_gate LIGHT_CLKGEN_DW200_CLK_DWE>;
clock-names = "aclk", "hclk", "vseclk", "dweclk";
};
&bm_csi0 { //CSI2
clocks = <&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI0_PCLK>,
<&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI0_PIXCLK>,
<&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI0_CFG_CLK>,
<&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI1_CFG_CLK>,
<&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI2_CFG_CLK>;
clock-names = "pclk", "pixclk", "cfg_clk0", "cfg_clk1", "cfg_clk2";
};
&bm_csi1 { //CSI2X2_B
clocks = <&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI1_PCLK>,
<&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI1_PIXCLK>,
<&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI0_CFG_CLK>,
<&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI1_CFG_CLK>,
<&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI2_CFG_CLK>;
clock-names = "pclk", "pixclk", "cfg_clk0", "cfg_clk1", "cfg_clk2";
};
&bm_csi2 { //CSI2X2_A
clocks = <&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI2_PCLK>,
<&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI2_PIXCLK>,
<&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI0_CFG_CLK>,
<&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI1_CFG_CLK>,
<&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI2_CFG_CLK>;
clock-names = "pclk", "pixclk", "cfg_clk0", "cfg_clk1", "cfg_clk2";
};
&vi_pre {
clocks = <&visys_clk_gate LIGHT_CLKGEN_VIPRE_ACLK>,
<&visys_clk_gate LIGHT_CLKGEN_VIPRE_PCLK>,
<&visys_clk_gate LIGHT_CLKGEN_VIPRE_PIXELCLK>;
clock-names ="aclk", "pclk", "pixclk";
};

259
arch/riscv/boot/dts/thead/light_mpw.dts
View File

@@ -1,259 +0,0 @@
/dts-v1/;
/ {
model = "T-HEAD c910 light mpw";
compatible = "thead,c910_light_mpw";
#address-cells = <2>;
#size-cells = <2>;
memory@0 {
device_type = "memory";
reg = <0x0 0x00200000 0x0 0xf0000000>;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
timebase-frequency = <0x2dc6c0>;
cpu@0 {
device_type = "cpu";
reg = <0>;
status = "okay";
compatible = "riscv";
riscv,isa = "rv64imafdcvsu";
mmu-type = "riscv,sv39";
cpu-freq = "1.5Ghz";
cpu-icache = "64KB";
cpu-dcache = "64KB";
cpu-l2cache = "2MB";
cpu-tlb = "1024 4-ways";
cpu-cacheline = "64Bytes";
cpu-vector = "0.7.1";
cpu0_intc: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
interrupt-controller;
};
};
cpu@1 {
device_type = "cpu";
reg = <1>;
status = "okay";
compatible = "riscv";
riscv,isa = "rv64imafdcvsu";
mmu-type = "riscv,sv39";
cpu-freq = "1.5Ghz";
cpu-icache = "64KB";
cpu-dcache = "64KB";
cpu-l2cache = "2MB";
cpu-tlb = "1024 4-ways";
cpu-cacheline = "64Bytes";
cpu-vector = "0.7.1";
cpu1_intc: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
interrupt-controller;
};
};
cpu@2 {
device_type = "cpu";
reg = <2>;
status = "okay";
compatible = "riscv";
riscv,isa = "rv64imafdcvsu";
mmu-type = "riscv,sv39";
cpu-freq = "1.5Ghz";
cpu-icache = "64KB";
cpu-dcache = "64KB";
cpu-l2cache = "2MB";
cpu-tlb = "1024 4-ways";
cpu-cacheline = "64Bytes";
cpu-vector = "0.7.1";
cpu2_intc: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
interrupt-controller;
};
};
cpu@3 {
device_type = "cpu";
reg = <3>;
status = "okay";
compatible = "riscv";
riscv,isa = "rv64imafdcvsu";
mmu-type = "riscv,sv39";
cpu-freq = "1.5Ghz";
cpu-icache = "64KB";
cpu-dcache = "64KB";
cpu-l2cache = "2MB";
cpu-tlb = "1024 4-ways";
cpu-cacheline = "64Bytes";
cpu-vector = "0.7.1";
cpu3_intc: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
interrupt-controller;
};
};
};
soc {
#address-cells = <2>;
#size-cells = <2>;
compatible = "simple-bus";
ranges;
reset: reset-sample {
compatible = "thead,reset-sample";
plic-delegate = <0xff 0xd81ffffc>;
using-csr-reset;
csr-copy = <
0x7c0 0x7c1 0x7c2 0x7c3 0x7c5 0x7cc
0x3b0 0x3b1 0x3b2 0x3b3
0x3b4 0x3b5 0x3b6 0x3b7
0x3a0
>;
};
clint0: clint@ffdc000000 {
compatible = "riscv,clint0";
interrupts-extended = <
&cpu0_intc 3 &cpu0_intc 7
&cpu1_intc 3 &cpu1_intc 7
&cpu2_intc 3 &cpu2_intc 7
&cpu3_intc 3 &cpu3_intc 7
>;
reg = <0xff 0xdc000000 0x0 0x04000000>;
clint,has-no-64bit-mmio;
};
intc: interrupt-controller@ffd8000000 {
#interrupt-cells = <1>;
compatible = "riscv,plic0";
interrupt-controller;
interrupts-extended = <
&cpu0_intc 0xffffffff &cpu0_intc 9
&cpu1_intc 0xffffffff &cpu1_intc 9
&cpu2_intc 0xffffffff &cpu2_intc 9
&cpu3_intc 0xffffffff &cpu3_intc 9
>;
reg = <0xff 0xd8000000 0x0 0x08000000>;
reg-names = "control";
riscv,max-priority = <7>;
riscv,ndev = <80>;
};
clocks {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
dummy_apb: apb-clock {
compatible = "fixed-clock";
clock-frequency = <62500000>;
clock-output-names = "dummy_apb";
#clock-cells = <0>;
};
dummy_clock_sdhci: sdhci-clock {
compatible = "fixed-clock";
reg = <4>; /* Not address, just for index */
clock-frequency = <198000000>;
clock-output-names = "dummy_clock_sdhci";
#clock-cells = <0>;
};
dummy_clock_gmac: gmac-clock {
compatible = "fixed-clock";
clock-frequency = <1000000000>;
clock-output-names = "dummy_clock_gmac";
#clock-cells = <0>;
};
};
serial@ffe7014000 {
compatible = "snps,dw-apb-uart";
reg = <0xff 0xe7014000 0x0 0x4000>;
interrupt-parent = <&intc>;
interrupts = <36>;
clocks = <&dummy_apb>;
clock-names = "baudclk";
reg-shift = <2>;
reg-io-width = <4>;
};
stmmac_axi_setup: stmmac-axi-config {
snps,wr_osr_lmt = <3>;
snps,rd_osr_lmt = <3>;
snps,blen = <16 8 4 0 0 0 0>;
};
gmac: ethernet@ffe7070000 {
compatible = "snps,dwmac";
reg = <0xff 0xe7070000 0x0 0x2000>;
interrupt-parent = <&intc>;
interrupts = <66>;
interrupt-names = "macirq";
clocks = <&dummy_clock_gmac>;
clock-names = "stmmaceth";
snps,pbl = <32>;
snps,fixed-burst;
snps,axi-config = <&stmmac_axi_setup>;
phy-mode = "rgmii-txid";
phy-handle = <&phy_88E1111>;
mdio0 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,dwmac-mdio";
phy_88E1111: ethernet-phy@0 {
reg = <0x1>;
};
};
};
emmc: sdhci@ffe7080000 {
compatible = "snps,dwcmshc-sdhci-light-mpw";
reg = <0xff 0xe7080000 0x0 0x10000
0xff 0xEF014060 0x0 0x4>;
interrupt-parent = <&intc>;
interrupts = <62>;
interrupt-names = "sdhciirq";
clocks = <&dummy_clock_sdhci>;
clock-names = "core";
max-frequency = <198000000>;
non-removable;
is_emmc;
no-sdio;
no-sd;
no-1-8-v;
bus-width = <8>;
status = "okay";
};
sdcard: sd@ffe7090000 {
compatible = "snps,dwcmshc-sdhci-light-mpw";
reg = <0xff 0xe7090000 0x0 0x10000
0xff 0xEF014064 0x0 0x4>;
interrupt-parent = <&intc>;
interrupts = <64>;
interrupt-names = "sdhci0irq";
clocks = <&dummy_clock_sdhci>;
clock-names = "core";
max-frequency = <198000000>;
bus-width = <4>;
status = "okay";
};
pmu: pmu {
interrupt-parent = <&cpu0_intc>;
interrupts = <17>;
compatible = "riscv,c910_pmu";
};
};
chosen {
bootargs = "console=ttyS0,115200 root=PARTUUID=80a5a8e9-c744-491a-93c1-4f4194fd690b rootfstype=ext4 rdinit=/sbin/init rootwait rw earlyprintk clk_ignore_unused loglevel=7 eth=00:a0:a0:a0:a0:a1";
stdout-path = "/soc/serial@ffe7014000:115200";
};
};

100
arch/riscv/boot/dts/thead/th1520-a-val-audio-i2s-8ch.dts Normal file
View File

@@ -0,0 +1,100 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2021 Alibaba Group Holding Limited.
*/
#include "th1520-a-val-audio.dts"
/ {
model = "T-HEAD Light FM Audio VAL board";
compatible = "thead,light-val-audio-i2s-8ch", "thead,light";
};
&lightsound {
status = "okay";
simple-audio-card,dai-link@1 { /* I2S - AUDIO SYS CODEC 7210*/
reg = <1>;
format = "i2s";
cpu {
sound-dai = <&i2s_8ch_sd2>;
};
codec {
mclk-fs = <512>;
sound-dai = <&es7210_audio_codec_adc0>;
};
};
simple-audio-card,dai-link@2 { /* I2S - AUDIO SYS CODEC 7210*/
reg = <2>;
format = "i2s";
cpu {
sound-dai = <&i2s_8ch_sd3>;
};
codec {
mclk-fs = <512>;
sound-dai = <&es7210_audio_codec_adc0>;
};
};
simple-audio-card,dai-link@3 { /* I2S - AUDIO SYS CODEC 7210_1*/
reg = <3>;
format = "i2s";
cpu {
sound-dai = <&i2s_8ch_sd0>;
};
codec {
mclk-fs = <512>;
sound-dai = <&es7210_audio_codec_adc1>;
};
};
simple-audio-card,dai-link@4 { /* I2S - AUDIO SYS CODEC 7210_1*/
reg = <4>;
format = "i2s";
cpu {
sound-dai = <&i2s_8ch_sd1>;
};
codec {
mclk-fs = <512>;
sound-dai = <&es7210_audio_codec_adc1>;
};
};
};
&i2s_8ch_sd0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_audiopa4>,
<&pinctrl_audio_i2s_8ch_sd0>,
<&pinctrl_audiopa2>,
<&pinctrl_audiopa3>,
<&pinctrl_audiopa8>,
<&pinctrl_audio_i2s_8ch_bus>;
};
&i2s_8ch_sd1 {
status = "okay";
};
&i2s_8ch_sd2 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_audiopa0>,
<&pinctrl_audio_i2s_8ch_sd2>;
};
&i2s_8ch_sd3 {
status = "okay";
};
&es7210_audio_codec_adc0 {
status = "okay";
channels-max = <8>;
};
&es7210_audio_codec_adc1 {
status = "okay";
channels-max = <8>;
};

42
arch/riscv/boot/dts/thead/th1520-a-val-audio-spdif.dts Normal file
View File

@@ -0,0 +1,42 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2021 Alibaba Group Holding Limited.
*/
#include "th1520-a-val.dtsi"
&spdif0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_audio_spdif0>;
status = "okay";
};
&spdif1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_audio_spdif1>;
status = "okay";
};
&lightsound {
status = "okay";
simple-audio-card,dai-link@0 { /* SPDIF0 */
reg = <1>;
format = "i2s";
cpu {
sound-dai = <&spdif0>;
};
codec {
sound-dai = <&dummy_codec>;
};
};
simple-audio-card,dai-link@1 { /* SPDIF1 */
reg = <1>;
format = "i2s";
cpu {
sound-dai = <&spdif1>;
};
codec {
sound-dai = <&dummy_codec>;
};
};
};

182
arch/riscv/boot/dts/thead/th1520-a-val-audio-tdm.dts Normal file
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@@ -0,0 +1,182 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2021 Alibaba Group Holding Limited.
*/
#include "th1520-a-val.dtsi"
&tdm_slot1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_audio_tdm>;
status = "okay";
};
&tdm_slot2 {
status = "okay";
};
&tdm_slot3 {
status = "okay";
};
&tdm_slot4 {
status = "okay";
};
&tdm_slot5 {
status = "okay";
};
&tdm_slot6 {
status = "okay";
};
&tdm_slot7 {
status = "okay";
};
&tdm_slot8 {
status = "okay";
};
&audio_i2c0 {
clock-frequency = <100000>;
status = "okay";
es7210_adc2: es7210@42 {
#sound-dai-cells = <0>;
compatible = "MicArray_0";
reg = <0x42>;
work-mode = "ES7210_TDM_1LRCK_DSPB";
channels-max = <8>;
sound-name-prefix = "ES7210_ADC2";
MVDD-supply = <&soc_aud_adc_3v3_en_reg>;
AVDD-supply = <&soc_aud_adc_3v3_en_reg>;
DVDD-supply = <&soc_dvdd18_aon_reg>;
PVDD-supply = <&soc_dvdd18_aon_reg>;
};
es7210_adc3: es7210@43 {
#sound-dai-cells = <0>;
compatible = "MicArray_1";
reg = <0x43>;
work-mode = "ES7210_TDM_1LRCK_DSPB";
channels-max = <8>;
sound-name-prefix = "ES7210_ADC3";
MVDD-supply = <&soc_aud_adc_3v3_en_reg>;
AVDD-supply = <&soc_aud_adc_3v3_en_reg>;
DVDD-supply = <&soc_dvdd18_aon_reg>;
PVDD-supply = <&soc_dvdd18_aon_reg>;
};
};
&lightsound {
status = "okay";
simple-audio-card,widgets = "Speaker", "Speaker";
simple-audio-card,routing =
"AW87519 IN", "ES8156 ROUT",
"Speaker", "AW87519 VO";
simple-audio-card,aux-devs = <&audio_aw87519_pa>;
simple-audio-card,dai-link@0 { /* I2S - AUDIO SYS CODEC 8156*/
reg = <0>;
format = "i2s";
cpu {
sound-dai = <&i2s0 0>;
};
codec {
sound-dai = <&es8156_audio_codec>;
};
};
simple-audio-card,dai-link@1 { /* TDM - AUDIO SYS CODEC 7210*/
reg = <1>;
format = "dsp_b";
cpu {
sound-dai = <&tdm_slot1>;
};
codec {
sound-dai = <&es7210_adc2>;
};
};
simple-audio-card,dai-link@2 {
reg = <1>;
format = "dsp_b";
cpu {
sound-dai = <&tdm_slot2>;
};
codec {
sound-dai = <&es7210_adc2>;
};
};
simple-audio-card,dai-link@3 {
reg = <1>;
format = "dsp_b";
cpu {
sound-dai = <&tdm_slot3>;
};
codec {
sound-dai = <&es7210_adc2>;
};
};
simple-audio-card,dai-link@4 {
reg = <1>;
format = "dsp_b";
cpu {
sound-dai = <&tdm_slot4>;
};
codec {
sound-dai = <&es7210_adc2>;
};
};
simple-audio-card,dai-link@5 {
reg = <1>;
format = "dsp_b";
cpu {
sound-dai = <&tdm_slot5>;
};
codec {
sound-dai = <&es7210_adc2>;
};
};
simple-audio-card,dai-link@6 {
reg = <1>;
format = "dsp_b";
cpu {
sound-dai = <&tdm_slot6>;
};
codec {
sound-dai = <&es7210_adc2>;
};
};
simple-audio-card,dai-link@7 {
reg = <1>;
format = "dsp_b";
cpu {
sound-dai = <&tdm_slot7>;
};
codec {
sound-dai = <&es7210_adc2>;
};
};
simple-audio-card,dai-link@8 {
reg = <1>;
format = "dsp_b";
cpu {
sound-dai = <&tdm_slot8>;
};
codec {
sound-dai = <&es7210_adc2>;
};
};
};
&i2s0 {
status = "okay";
};

26
arch/riscv/boot/dts/thead/light-a-val-audio.dts → arch/riscv/boot/dts/thead/th1520-a-val-audio.dts
View File

@@ -3,7 +3,7 @@
* Copyright (C) 2021 Alibaba Group Holding Limited.
*/
#include "light-a-val.dts"
#include "th1520-a-val.dtsi"
/ {
model = "T-HEAD Light FM Audio VAL board";
@@ -11,8 +11,12 @@
};
&lightsound {
status = "okay";
status = "okay";
simple-audio-card,widgets = "Speaker", "Speaker";
simple-audio-card,routing =
"Speaker", "AW87519 VO",
"AW87519 IN", "ES8156 ROUT";
simple-audio-card,aux-devs = <&audio_aw87519_pa>;
simple-audio-card,dai-link@0 { /* I2S - AUDIO SYS CODEC 8156*/
reg = <0>;
format = "i2s";
@@ -28,22 +32,24 @@
reg = <1>;
format = "i2s";
cpu {
sound-dai = <&i2s3 0>;
sound-dai = <&i2s_8ch_sd2 2>;
};
codec {
sound-dai = <&es7210_audio_codec>;
sound-dai = <&es7210_audio_codec_adc0>;
};
};
};
&light_i2s {
status = "okay";
};
&i2s0 {
status = "okay";
};
&i2s3 {
&i2s_8ch_sd2 {
status = "okay";
};
&es7210_audio_codec_adc0 {
status = "okay";
};

2
arch/riscv/boot/dts/thead/light-a-val-crash.dts → arch/riscv/boot/dts/thead/th1520-a-val-crash.dts
View File

@@ -3,7 +3,7 @@
* Copyright (C) 2021 Alibaba Group Holding Limited.
*/
#include "light-crash.dts"
#include "th1520-crash.dtsi"
&aon {
aon_reg_dialog: light-dialog-reg {

2
arch/riscv/boot/dts/thead/light-a-val-dsi0-dsi1.dts → arch/riscv/boot/dts/thead/th1520-a-val-dsi0-dsi1.dts
View File

@@ -5,7 +5,7 @@
/dts-v1/;
#include "light-a-val-dsi0.dts"
#include "th1520-a-val-dsi0.dts"
&dpu_enc1 {
status = "okay";

2
arch/riscv/boot/dts/thead/light-a-ref-dsi0-hdmi.dts → arch/riscv/boot/dts/thead/th1520-a-val-dsi0-hdmi.dts
View File

@@ -5,7 +5,7 @@
/dts-v1/;
#include "light-a-ref-dsi0.dts"
#include "th1520-a-val-dsi0.dts"
&dpu_enc1 {
ports {

2
arch/riscv/boot/dts/thead/light-a-ref-dsi0.dts → arch/riscv/boot/dts/thead/th1520-a-val-dsi0.dts
View File

@@ -5,7 +5,7 @@
/dts-v1/;
#include "light-a-ref.dts"
#include "th1520-a-val.dtsi"
/ {
display-subsystem {

5
arch/riscv/boot/dts/thead/light-b-product-sec.dts → arch/riscv/boot/dts/thead/th1520-a-val-sec.dts
View File

@@ -5,14 +5,13 @@
/dts-v1/;
#include "light-b-product.dts"
#include "th1520-a-val.dts"
&light_iopmp {
status = "disabled";
};
&qspi1 {
&eip_28 {
status = "disabled";
};

10
arch/riscv/boot/dts/thead/light-a-val-hdmi.dts → arch/riscv/boot/dts/thead/th1520-a-val.dts
View File

@@ -5,7 +5,7 @@
/dts-v1/;
#include "light-a-val.dts"
#include "th1520-a-val-audio.dts"
/ {
display-subsystem {
@@ -40,15 +40,15 @@
&lightsound {
status = "okay";
simple-audio-card,dai-link@1 { /* I2S - HDMI */
reg = <1>;
simple-audio-card,dai-link@2 { /* I2S - HDMI */
reg = <2>;
format = "i2s";
cpu {
sound-dai = <&light_i2s 1>;
};
codec {
sound-dai = <&dummy_codec 2>;
sound-dai = <&dummy_codec>;
};
};
};

711
arch/riscv/boot/dts/thead/light-a-val.dts → arch/riscv/boot/dts/thead/th1520-a-val.dtsi
View File

File diff suppressed because it is too large Load Diff

2
arch/riscv/boot/dts/thead/light-b-product-crash.dts → arch/riscv/boot/dts/thead/th1520-b-product-crash.dts
View File

@@ -3,7 +3,7 @@
* Copyright (C) 2021 Alibaba Group Holding Limited.
*/
#include "light-crash.dts"
#include "th1520-crash.dtsi"
&aon {
aon_reg_ricoh: light-ricoh-reg {

6
arch/riscv/boot/dts/thead/light-ant-ref-sec.dts → arch/riscv/boot/dts/thead/th1520-b-product-sec.dts
View File

@@ -5,7 +5,7 @@
/dts-v1/;
#include "light-ant-ref.dts"
#include "th1520-b-product.dts"
@@ -13,8 +13,6 @@
status = "disabled";
};
&qspi1 {
&eip_28 {
status = "disabled";
};

347
arch/riscv/boot/dts/thead/light-b-product.dts → arch/riscv/boot/dts/thead/th1520-b-product.dts
View File

@@ -5,17 +5,17 @@
/dts-v1/;
#include "light.dtsi"
#include "th1520.dtsi"
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/gpio/gpio.h>
#include "light-vi-devices.dtsi"
#include "th1520-vi-devices.dtsi"
/ {
model = "T-HEAD Light val board";
compatible = "thead,light-val", "thead,light";
memory@0 {
device_type = "memory";
reg = <0x0 0x00000000 0x0 0x80000000>;
reg = <0x0 0x200000 0x0 0x7fe00000>;
};
chosen {
@@ -166,6 +166,14 @@
iopmp_dsp1: IOPMP_DSP1 {
is_default_region;
};
iopmp_audio0: IOPMP_AUDIO0 {
is_default_region;
};
iopmp_audio1: IOPMP_AUDIO1 {
is_default_region;
};
};
mbox_910t_client1: mbox_910t_client1 {
@@ -180,7 +188,8 @@
compatible = "thead,light-mbox-client";
mbox-names = "906";
mboxes = <&mbox_910t 2 0>;
status = "disabled";
audio-mbox-regmap = <&audio_mbox>;
status = "okay";
};
lightsound: lightsound@1 {
@@ -193,10 +202,25 @@
status = "disabled";
};
light_rpmsg: light_rpmsg {
compatible = "light,rpmsg-bus", "simple-bus";
memory-region = <&rpmsgmem>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
rpmsg: rpmsg{
vdev-nums = <1>;
reg = <0x0 0x1E000000 0 0x10000>;
compatible = "light,light-rpmsg";
status = "okay";
};
};
dummy_codec: dummy_codec {
#sound-dai-cells = <1>;
compatible = "linux,bt-sco";
#sound-dai-cells = <0>;
compatible = "thead,light-dummy-pcm";
status = "okay";
sound-name-prefix = "DUMMY";
};
reg_vref_1v8: regulator-adc-verf {
@@ -242,12 +266,14 @@
pinctrl-names = "default";
key-volumedown {
label = "Volume Down Key";
wakeup-source;
linux,code = <KEY_VOLUMEDOWN>;
debounce-interval = <1>;
gpios = <&ao_gpio_porta 11 0x1>;
};
key-volumeup {
label = "Volume Up Key";
wakeup-source;
linux,code = <KEY_VOLUMEUP>;
debounce-interval = <1>;
gpios = <&ao_gpio_porta 10 0x1>;
@@ -270,6 +296,8 @@
regulator-name = "soc_aud_3v3_en";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_audio_3v3_en>;
gpio = <&ao_gpio_porta 7 1>;
enable-active-high;
regulator-always-on;
@@ -280,6 +308,8 @@
regulator-name = "soc_aud_1v8_en";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_audio_1v8_en>;
gpio = <&ao_gpio_porta 8 1>;
enable-active-high;
regulator-always-on;
@@ -549,14 +579,14 @@
0x0 0x20280000 0x0 0x00001000 /* DSP communication area 4K*/
0x0 0x20281000 0x0 0x00007000 /* Panic/log page 28K */
0x0 0x20288000 0x0 0x00178000>; /* DSP shared memory 1.5M-32K*/
no-map;
//no-map;
};
dsp1_mem: memory@20400000 { /**0x2040_0000~0x2080_0000 4M**/
reg = <0x0 0x20400000 0x0 0x00280000 /* DSP FW code&data section */
0x0 0x20680000 0x0 0x00001000 /* DSP communication area */
0x0 0x20681000 0x0 0x00007000 /* Panic/log page*/
0x0 0x20688000 0x0 0x00178000>; /* DSP shared memory */
no-map;
//no-map;
};
vi_mem: framebuffer@10000000 {
reg = <0x0 0x10000000 0x0 0x02C00000 /* vi_mem_pool_region[0] 44 MB (default) */
@@ -567,9 +597,17 @@
facelib_mem: memory@17000000 {
reg = <0x0 0x17000000 0 0x02000000>;
no-map;
//no-map;
};
audio_mem: memory@32000000 {
reg = <0x0 0x32000000 0x0 0x6400000>;
//no-map;
};
rpmsgmem: memory@1E000000 {
reg = <0x0 0x1E000000 0x0 0x10000>;
//no-map;
};
};
@@ -591,7 +629,7 @@
irq-gpios = <&gpio1_porta 8 0>;
reset-gpios = <&gpio1_porta 7 0>;
AVDD28-supply = <&reg_tp_pwr_en>;
touchscreen-size-x = <720>;
touchscreen-size-x = <800>;
touchscreen-size-y = <1280>;
};
@@ -600,23 +638,43 @@
&audio_i2c0 {
clock-frequency = <100000>;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_audiopa6>,
<&pinctrl_audiopa7>,
<&pinctrl_audio_i2c0>;
es8156_audio_codec: es8156@8 {
#sound-dai-cells = <0>;
compatible = "everest,es8156";
reg = <0x08>;
};
es8156_audio_codec: es8156@8 {
#sound-dai-cells = <0>;
compatible = "everest,es8156";
reg = <0x08>;
sound-name-prefix = "ES8156";
AVDD-supply = <&soc_aud_3v3_en_reg>;
DVDD-supply = <&soc_aud_1v8_en_reg>;
PVDD-supply = <&soc_aud_1v8_en_reg>;
mclk-sclk-ratio = <4>;
};
es7210_audio_codec: es7210@40 {
#sound-dai-cells = <0>;
compatible = "MicArray_0";
reg = <0x40>;
work-mode = "ES7210_NORMAL_I2S";
channels-max = <2>;
mclk-sclk-ratio = <4>;
sound-name-prefix = "ES7210_ADC0";
MVDD-supply = <&soc_aud_3v3_en_reg>;
AVDD-supply = <&soc_aud_3v3_en_reg>;
DVDD-supply = <&soc_aud_1v8_en_reg>;
PVDD-supply = <&soc_aud_1v8_en_reg>;
};
audio_aw87519_pa@58 {
audio_aw87519_pa: amp@58 {
compatible = "awinic,aw87519_pa";
reg = <0x58>;
pingctrl-names = "default";
pinctrl-0 = <&pinctrl_audio_pa_rst0>;
reset-gpio = <&ao_gpio4_porta 9 0x1>;
sound-name-prefix = "AW87519";
status = "okay";
};
};
@@ -750,6 +808,7 @@
no-mmc;
non-removable;
io_fixed_1v8;
rxclk-sample-delay = <80>;
post-power-on-delay-ms = <50>;
wprtn_ignore;
cap-sd-highspeed;
@@ -792,7 +851,7 @@
>;
};
pinctrl_audio_i2s0: i2s0grp {
pinctrl_light_i2s0: i2s0grp {
thead,pins = <
FM_QSPI0_SCLK 0x2 0x208
FM_QSPI0_CSN0 0x2 0x238
@@ -866,27 +925,103 @@
* Format: <pin_id mux_node config>
*/
pinctrl_audiopa1: audiopa1_grp {
thead,pins = <
FM_AUDIO_PA1 0x3 0x72
>;
pinctrl_audiopa0: audiopa0 {
thead,pins = < FM_AUDIO_PA0 LIGHT_PIN_FUNC_0 0x000 >;
};
pinctrl_audiopa2: audiopa2_grp {
thead,pins = <
FM_AUDIO_PA2 0x0 0x72
>;
pinctrl_audiopa1: audiopa1 {
thead,pins = < FM_AUDIO_PA1 LIGHT_PIN_FUNC_0 0x000 >;
};
pinctrl_audiopa2: audiopa2 {
thead,pins = < FM_AUDIO_PA2 LIGHT_PIN_FUNC_0 0x000 >;
};
pinctrl_audiopa3: audiopa3 {
thead,pins = < FM_AUDIO_PA3 LIGHT_PIN_FUNC_0 0x000 >;
};
pinctrl_audiopa6: audiopa6 {
thead,pins = < FM_AUDIO_PA6 LIGHT_PIN_FUNC_0 0x000 >;
};
pinctrl_audiopa7: audiopa7 {
thead,pins = < FM_AUDIO_PA7 LIGHT_PIN_FUNC_0 0x000 >;
};
pinctrl_audiopa8: audiopa8 {
thead,pins = < FM_AUDIO_PA8 LIGHT_PIN_FUNC_0 0x000 >;
};
pinctrl_audio_pa_rst0: audio_pa_rst0 {
thead,pins = < FM_AUDIO_PA9 LIGHT_PIN_FUNC_3 0x000 >;
};
pinctrl_audiopa13: audiopa13 {
thead,pins = < FM_AUDIO_PA13 LIGHT_PIN_FUNC_0 0x000 >;
};
pinctrl_audiopa14: audiopa14 {
thead,pins = < FM_AUDIO_PA14 LIGHT_PIN_FUNC_0 0x000 >;
};
pinctrl_audiopa15: audiopa15 {
thead,pins = < FM_AUDIO_PA15 LIGHT_PIN_FUNC_0 0x000 >;
};
pinctrl_audiopa17: audiopa17 {
thead,pins = < FM_AUDIO_PA17 LIGHT_PIN_FUNC_0 0x000 >;
};
pinctrl_audio_3v3_en: audio_3v3_en {
thead,pins = < FM_AOGPIO_7 LIGHT_PIN_FUNC_3 0x008 >;
};
pinctrl_audio_1v8_en: audio_1v8_en {
thead,pins = < FM_AOGPIO_8 LIGHT_PIN_FUNC_3 0x008 >;
};
pinctrl_volume: volume_grp {
thead,pins = <
FM_AOGPIO_11 0x0 0x208
FM_AOGPIO_10 0x3 0x208
FM_AOGPIO_11 0x0 0x238
FM_AOGPIO_10 0x3 0x238
>;
};
};
};
&padctrl_audiosys {
status = "okay";
light-audio-padctrl {
/*
* Pin Configuration Node:
* Format: <pin_id mux_node config>
*/
pinctrl_audio_i2c0: audio_i2c0_grp {
thead,pins = <
FM_AUDIO_IO_PA6 LIGHT_PIN_FUNC_0 0x004
FM_AUDIO_IO_PA7 LIGHT_PIN_FUNC_0 0x004
>;
};
pinctrl_audio_i2s1: audio_i2s1_grp {
thead,pins = <
FM_AUDIO_IO_PA13 LIGHT_PIN_FUNC_0 0x008
FM_AUDIO_IO_PA14 LIGHT_PIN_FUNC_0 0x008
FM_AUDIO_IO_PA15 LIGHT_PIN_FUNC_0 0x008
FM_AUDIO_IO_PA17 LIGHT_PIN_FUNC_0 0x008
>;
};
pinctrl_audio_i2s_8ch_bus: audio_i2s_8ch_bus_grp {
thead,pins = <
FM_AUDIO_IO_PA2 LIGHT_PIN_FUNC_3 0x008
FM_AUDIO_IO_PA3 LIGHT_PIN_FUNC_3 0x008
FM_AUDIO_IO_PA8 LIGHT_PIN_FUNC_3 0x008
>;
};
pinctrl_audio_i2s_8ch_sd2: audio_i2s_8ch_sd2_grp {
thead,pins = <
FM_AUDIO_IO_PA0 LIGHT_PIN_FUNC_3 0x008
>;
};
pinctrl_audio_i2s_8ch_sd3: audio_i2s_8ch_sd3_grp {
thead,pins = <
FM_AUDIO_IO_PA1 LIGHT_PIN_FUNC_3 0x008
>;
};
};
};
&i2c0 {
clock-frequency = <400000>;
status = "okay";
@@ -1054,6 +1189,9 @@
DVDD12_SCAN-supply = <&soc_dvdd12_scan_reg>;
AVDD28_SCAN-supply = <&soc_avdd28_scan_en_reg>;
i2c_bus = /bits/ 8 <4>;
i2c_reg_width = /bits/ 8 <2>;
i2c_data_width = /bits/ 8 <1>;
i2c_addr = /bits/ 8 <0x30>;
status = "okay";
};
@@ -1107,7 +1245,7 @@
&video0{
vi_mem_pool_region = <2>; // vi_mem: framebuffer, region[2]
pipline0 {
channel0 {
sensor0 {
subdev_name = "vivcam";
idx = <2>; //<2>=vivcam2 : gc5035
@@ -1134,7 +1272,7 @@
};
};
};
pipline1 {
channel1 {
sensor0 {
subdev_name = "vivcam";
idx = <2>; //<2>=vivcam2 : gc5035
@@ -1161,7 +1299,7 @@
};
};
};
pipline2 {
channel2 {
sensor0 {
subdev_name = "vivcam";
idx = <2>; //<2>=vivcam2 : gc5035
@@ -1193,7 +1331,7 @@
&video1{
vi_mem_pool_region = <2>; // vi_mem: framebuffer, region[2]
pipline0 {
channel0 {
sensor0 {
subdev_name = "vivcam";
idx = <2>; //<2>=vivcam2 : gc5035
@@ -1226,7 +1364,7 @@
dw_dst_depth = <2>;
};
};
pipline1 {
channel1 {
sensor0 {
subdev_name = "vivcam";
idx = <2>; //<2>=vivcam2 : gc5035
@@ -1259,7 +1397,7 @@
dw_dst_depth = <2>;
};
};
pipline2 {
channel2 {
sensor0 {
subdev_name = "vivcam";
idx = <2>; //<2>=vivcam2 : gc5035
@@ -1296,7 +1434,7 @@
&video2{
vi_mem_pool_region = <0>; // vi_mem: framebuffer, region[0]
pipline0 {
channel0 {
sensor0 {
subdev_name = "vivcam";
idx = <0>; //sc2310
@@ -1323,7 +1461,7 @@
};
};
};
pipline1 {
channel1 {
sensor0 {
subdev_name = "vivcam";
idx = <0>; //sc2310
@@ -1350,7 +1488,7 @@
};
};
};
pipline2 {
channel2 {
sensor0 {
subdev_name = "vivcam";
idx = <0>; //sc2310
@@ -1381,7 +1519,7 @@
&video3{
vi_mem_pool_region = <0>; // vi_mem: framebuffer, region[0]
pipline0 {
channel0 {
sensor0 {
subdev_name = "vivcam";
idx = <0>; //sc2310
@@ -1414,7 +1552,7 @@
dw_dst_depth = <2>;
};
};
pipline1 {
channel1 {
sensor0 {
subdev_name = "vivcam";
idx = <0>; //sc2310
@@ -1447,7 +1585,7 @@
dw_dst_depth = <2>;
};
};
pipline2 {
channel2 {
sensor0 {
subdev_name = "vivcam";
idx = <0>; //sc2310
@@ -1484,7 +1622,7 @@
&video4{
vi_mem_pool_region = <0>; // vi_mem: framebuffer, region[0]
pipline0 {
channel0 {
sensor0 {
subdev_name = "vivcam";
idx = <0>; //sc2310
@@ -1533,7 +1671,7 @@
};
};
};
pipline1 {
channel1 {
sensor0 {
subdev_name = "vivcam";
idx = <0>; //sc2310
@@ -1582,7 +1720,7 @@
};
};
};
pipline2 {
channel2 {
sensor0 {
subdev_name = "vivcam";
idx = <0>; //sc2310
@@ -1635,7 +1773,7 @@
&video5{
vi_mem_pool_region = <0>; // vi_mem: framebuffer, region[0]
pipline0 {
channel0 {
sensor0 {
subdev_name = "vivcam";
idx = <0>; //sc2310
@@ -1690,7 +1828,7 @@
dw_dst_depth = <2>;
};
};
pipline1 {
channel1 {
sensor0 {
subdev_name = "vivcam";
idx = <0>; //sc2310
@@ -1745,7 +1883,7 @@
dw_dst_depth = <2>;
};
};
pipline2 {
channel2 {
sensor0 {
subdev_name = "vivcam";
idx = <0>; //sc2310
@@ -1804,7 +1942,7 @@
&video6{
vi_mem_pool_region = <1>; // vi_mem: framebuffer, region[1]
pipline0 {
channel0 {
sensor0 {
subdev_name = "vivcam";
idx = <4>; //sc132gs
@@ -1822,7 +1960,7 @@
};
};
};
pipline1 {
channel1 {
sensor0 {
subdev_name = "vivcam";
idx = <4>; //sc132gs
@@ -1844,7 +1982,7 @@
};
&video7{
pipline0 {
channel0 {
sensor0 {
subdev_name = "vivcam";
idx = <2>; //<2>=vivcam2 : gc5035
@@ -1899,7 +2037,7 @@
dw_dst_depth = <2>;
};
};
pipline1 {
channel1 {
sensor0 {
subdev_name = "vivcam";
idx = <2>; //<2>=vivcam2 : gc5035
@@ -1954,7 +2092,7 @@
dw_dst_depth = <2>;
};
};
pipline2 {
channel2 {
sensor0 {
subdev_name = "vivcam";
idx = <2>; //<2>=vivcam2 : gc5035
@@ -2014,7 +2152,7 @@
&video8{
vi_mem_pool_region = <1>; // vi_mem: framebuffer, region[1]
pipline0 {
channel0 {
sensor0 {
subdev_name = "vivcam";
idx = <2>; //<2>=vivcam2 : gc5035
@@ -2044,7 +2182,7 @@
};
&video9{
pipline0 {
channel0 {
sensor0 {
subdev_name = "vivcam";
idx = <4>; //sc132gs
@@ -2065,7 +2203,7 @@
&video10{ // TUNINGTOOL
pipline0 {
channel0 {
sensor0 {
subdev_name = "vivcam";
idx = <2>; //<2>=vivcam2 : gc5035
@@ -2086,8 +2224,8 @@
};
&video11{
pipline0 {
pipline_id = <0>;
channel0 {
channel_id = <0>;
status = "okay";
sensor0 {
subdev_name = "vivcam";
@@ -2112,7 +2250,7 @@
};
&video12{ // TUNINGTOOL
pipline0 { // CSI2
channel0 { // CSI2
sensor0 {
subdev_name = "vivcam";
idx = <0>; //sc2310
@@ -2135,8 +2273,8 @@
&video14{
vi_mem_pool_region = <2>; // vi_mem: framebuffer, region[0]
status = "okay";
pipline0 {
pipline_id = <0>;
channel0 {
channel_id = <0>;
status = "okay";
sensor0 {
subdev_name = "vivcam";
@@ -2168,8 +2306,8 @@
&video15{
status = "okay";
//vi_mem_pool_region = <0>;
pipline0 {
pipline_id = <0>;
channel0 {
channel_id = <0>;
status = "okay";
sensor0 {
subdev_name = "vivcam";
@@ -2226,21 +2364,6 @@
status = "okay";
};
&dpu_enc0 {
status = "okay";
ports {
/* output */
port@1 {
reg = <1>;
enc0_out: endpoint {
remote-endpoint = <&dsi0_in>;
};
};
};
};
&dpu_enc1 {
ports {
/delete-node/ port@0;
@@ -2251,48 +2374,6 @@
status = "okay";
};
&dsi0 {
status = "okay";
};
&dhost_0 {
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dsi0_in: endpoint {
remote-endpoint = <&enc0_out>;
};
};
port@1 {
reg = <1>;
dsi0_out: endpoint {
remote-endpoint = <&panel0_in>;
};
};
};
panel0: panel0@0 {
compatible = "txd,dy800qwxpab";
reg = <0>;
backlight = <&lcd0_backlight>;
reset-gpio = <&gpio1_porta 5 1>; /* active low */
vdd1v8-supply = <&soc_vdd18_lcd0_en_reg>;
vspn5v7-supply = <&soc_lcd0_bias_en_reg>;
port {
panel0_in: endpoint {
remote-endpoint = <&dsi0_out>;
};
};
};
};
&disp1_out {
remote-endpoint = <&hdmi_tx_in>;
};
@@ -2310,6 +2391,11 @@
&lightsound {
status = "okay";
simple-audio-card,widgets = "Speaker", "Speaker";
simple-audio-card,routing =
"Speaker", "AW87519 VO",
"AW87519 IN", "ES8156 ROUT";
simple-audio-card,aux-devs = <&audio_aw87519_pa>;
simple-audio-card,dai-link@0 { /* I2S - AUDIO SYS CODEC 8156*/
reg = <0>;
format = "i2s";
@@ -2324,7 +2410,7 @@
reg = <1>;
format = "i2s";
cpu {
sound-dai = <&i2s3 0>;
sound-dai = <&i2s_8ch_sd2 2>;
};
codec {
sound-dai = <&es7210_audio_codec>;
@@ -2337,7 +2423,7 @@
sound-dai = <&light_i2s 1>;
};
codec {
sound-dai = <&dummy_codec 2>;
sound-dai = <&dummy_codec>;
};
};
};
@@ -2352,10 +2438,29 @@
&i2s1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_audiopa13>,
<&pinctrl_audiopa14>,
<&pinctrl_audiopa15>,
<&pinctrl_audiopa17>,
<&pinctrl_audio_i2s1>;
};
&i2s3 {
&i2s_8ch_sd2 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_audiopa0>,
<&pinctrl_audio_i2s_8ch_sd2>,
<&pinctrl_audiopa2>,
<&pinctrl_audiopa3>,
<&pinctrl_audiopa8>,
<&pinctrl_audio_i2s_8ch_bus>;
};
&i2s_8ch_sd3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_audiopa1>,
<&pinctrl_audio_i2s_8ch_sd3>;
};
&cpus {

53
arch/riscv/boot/dts/thead/light-crash.dts → arch/riscv/boot/dts/thead/th1520-crash.dtsi
View File

@@ -5,10 +5,10 @@
/dts-v1/;
#include "light.dtsi"
#include "th1520.dtsi"
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/gpio/gpio.h>
#include "light-vi-devices.dtsi"
#include "th1520-vi-devices.dtsi"
/ {
model = "T-HEAD Light val board";
compatible = "thead,light-val", "thead,light";
@@ -163,6 +163,14 @@
iopmp_dsp1: IOPMP_DSP1 {
is_default_region;
};
iopmp_audio0: IOPMP_AUDIO0 {
is_default_region;
};
iopmp_audio1: IOPMP_AUDIO1 {
is_default_region;
};
};
mbox_910t_client1: mbox_910t_client1 {
@@ -191,8 +199,9 @@
};
dummy_codec: dummy_codec {
#sound-dai-cells = <1>;
compatible = "linux,bt-sco";
#sound-dai-cells = <0>;
compatible = "thead,light-dummy-pcm";
sound-name-prefix = "DUMMY";
status = "okay";
};
@@ -288,14 +297,14 @@
0x0 0x20280000 0x0 0x00001000 /* DSP communication area 4K*/
0x0 0x20281000 0x0 0x00007000 /* Panic/log page 28K */
0x0 0x20288000 0x0 0x00178000>; /* DSP shared memory 1.5M-32K*/
no-map;
//no-map;
};
dsp1_mem: memory@20400000 { /**0x2040_0000~0x2080_0000 4M**/
reg = <0x0 0x20400000 0x0 0x00280000 /* DSP FW code&data section */
0x0 0x20680000 0x0 0x00001000 /* DSP communication area */
0x0 0x20681000 0x0 0x00007000 /* Panic/log page*/
0x0 0x20688000 0x0 0x00178000>; /* DSP shared memory */
no-map;
//no-map;
};
vi_mem: framebuffer@10000000 {
reg = <0x0 0x10000000 0x0 0x02C00000 /* vi_mem_pool_region[0] 44 MB (default) */
@@ -305,7 +314,7 @@
};
facelib_mem: memory@17000000 {
reg = <0x0 0x17000000 0 0x02000000>;
no-map;
//no-map;
};
};
@@ -327,7 +336,7 @@
irq-gpios = <&gpio1_porta 8 0>;
reset-gpios = <&gpio1_porta 7 0>;
AVDD28-supply = <&reg_tp_pwr_en>;
touchscreen-size-x = <720>;
touchscreen-size-x = <800>;
touchscreen-size-y = <1280>;
};
@@ -341,18 +350,23 @@
#sound-dai-cells = <0>;
compatible = "everest,es8156";
reg = <0x08>;
sound-name-prefix = "ES8156";
status = "disabled";
};
es7210_audio_codec: es7210@40 {
#sound-dai-cells = <0>;
compatible = "MicArray_0";
reg = <0x40>;
sound-name-prefix = "ES7210";
status = "disabled";
};
audio_aw87519_pa@58 {
audio_aw87519_pa: amp@58 {
compatible = "awinic,aw87519_pa";
reg = <0x58>;
reset-gpio = <&ao_gpio4_porta 9 0x1>;
sound-name-prefix = "AW87519";
status = "okay";
};
};
@@ -456,7 +470,7 @@
rx-clk-delay = <0x00>; /* for RGMII */
tx-clk-delay = <0x00>; /* for RGMII */
phy-handle = <&phy_88E1111_1>;
status = "disabled";
status = "okay";
};
&emmc {
@@ -488,6 +502,7 @@
no-mmc;
non-removable;
io_fixed_1v8;
rxclk-sample-delay = <80>;
post-power-on-delay-ms = <50>;
wprtn_ignore;
cap-sd-highspeed;
@@ -530,7 +545,7 @@
>;
};
pinctrl_audio_i2s0: i2s0grp {
pinctrl_light_i2s0: i2s0grp {
thead,pins = <
FM_QSPI0_SCLK 0x2 0x208
FM_QSPI0_CSN0 0x2 0x238
@@ -862,22 +877,6 @@
status = "disabled";
};
&light_i2s {
status = "okay";
};
&i2s0 {
status = "okay";
};
&i2s1 {
status = "okay";
};
&i2s3 {
status = "okay";
};
&khvhost {
status = "disabled";
};

53
arch/riscv/boot/dts/thead/th1520-lpi4a-camera-tuning.dts Normal file
View File

@@ -0,0 +1,53 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2021 Alibaba Group Holding Limited.
*/
/dts-v1/;
#include "th1520-lpi4a-dsi0.dts"
&video10{ // TUNINGTOOL
status = "okay";
channel0 {
sensor1 {
subdev_name = "vivcam";
idx = <3>;
csi_idx = <0>;
mode_idx = <1>; // 0=640 480 1=2592x1944
path_type = "SENSOR_2592x1944_LINER";
};
dma {
path_type = "VIPRE_CSI0_ISP0";
};
};
};
&video15{
status = "okay";
vi_mem_pool_region = <0>; // vi_mem: framebuffer, region[0]
channel0 {
status = "okay";
sensor0 {
subdev_name = "vivcam";
idx = <0>;
csi_idx = <0>;
mode_idx = <0>;
path_type = "SENSOR_VGA_RAW12_LINER";
};
sensor1 {
subdev_name = "vivcam";
idx = <3>;
csi_idx = <0>;
mode_idx = <1>;
path_type = "SENSOR_2592x1944_LINER";
};
dma {
subdev_name = "vipre";
idx = <0>;
path_type = "VIPRE_CSI0_DDR";
};
};
};

59
arch/riscv/boot/dts/thead/th1520-lpi4a-dsi0.dts Normal file
View File

@@ -0,0 +1,59 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2022-2023 Alibaba Group Holding Limited.
*/
#include "th1520-lpi4a.dtsi"
/ {
model = "T-HEAD Light Lichee Pi 4A configuration for 8GB DDR board";
compatible = "thead,light-val", "thead,light-lpi4a", "thead,light";
memory@0 {
device_type = "memory";
reg = <0x0 0x200000 0x1 0xffe00000>;
};
};
&cmamem {
size = <0 0x20000000>; // 512MB on lpi4a (SOM)
alloc-ranges = <0 0xd8000000 0 0x20000000>; // [0x0D800_0000 ~ 0x0F800_0000]
};
&i2c3 {
touch@14 {
#gpio-cells = <2>;
compatible = "goodix,gt9271";
reg = <0x14>;
interrupt-parent = <&ao_gpio_porta>;
interrupts = <3 0>;
irq-gpios = <&ao_gpio_porta 3 0>;
reset-gpios = <&pcal6408ahk_d 0 0>;
AVDD28-supply = <&reg_tp_pwr_en>;
touchscreen-size-x = <800>;
touchscreen-size-y = <1200>;
tp-size = <9271>;
status = "okay";
};
};
&dsi0 {
status = "okay";
};
&dhost_0 {
panel0@0 {
compatible = "chongzhou,cz101b4001", "jadard,jd9365da-h3";
reg = <0>;
backlight = <&lcd0_backlight>;
reset-gpio = <&pcal6408ahk_d 7 0>; /* active low */
hsvcc-supply = <&soc_vdd18_lcd0_en_reg>;
vspn3v3-supply = <&soc_vdd33_lcd0_en_reg>;
port {
panel0_in: endpoint {
remote-endpoint = <&dsi0_out>;
};
};
};
};

60
arch/riscv/boot/dts/thead/th1520-lpi4a-hx8279.dts Normal file
View File

@@ -0,0 +1,60 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2022-2023 Alibaba Group Holding Limited.
*/
#include "th1520-lpi4a.dtsi"
/ {
model = "T-HEAD Light Lichee Pi 4A configuration for 8GB DDR board";
compatible = "thead,light-val", "thead,light-lpi4a", "thead,light";
memory@0 {
device_type = "memory";
reg = <0x0 0x200000 0x1 0xffe00000>;
};
};
&cmamem {
size = <0 0x20000000>; // 512MB on lpi4a (SOM)
alloc-ranges = <0 0xd8000000 0 0x20000000>; // [0x0D800_0000 ~ 0x0F800_0000]
};
&i2c3 {
touch@14 {
#gpio-cells = <2>;
compatible = "goodix,gt9271";
reg = <0x14>;
interrupt-parent = <&ao_gpio_porta>;
interrupts = <3 0>;
irq-gpios = <&ao_gpio_porta 3 0>;
reset-gpios = <&pcal6408ahk_d 0 0>;
AVDD28-supply = <&reg_tp_pwr_en>;
touchscreen-size-x = <1200>;
touchscreen-size-y = <1920>;
tp-size = <9271>;
status = "okay";
};
};
&dsi0 {
status = "okay";
};
&dhost_0 {
panel0@0 {
compatible = "himax,hx8279";
reg = <0>;
backlight = <&lcd0_backlight>;
reset-gpio = <&pcal6408ahk_d 7 0>; /* active low */
hsvcc-supply = <&soc_vdd18_lcd0_en_reg>;
vspn3v3-supply = <&soc_vdd33_lcd0_en_reg>;
port {
panel0_in: endpoint {
remote-endpoint = <&dsi0_out>;
};
};
};
};

20
arch/riscv/boot/dts/thead/light-ant-ref-crash.dts → arch/riscv/boot/dts/thead/th1520-lpi4a-product-crash.dts
View File

@@ -1,9 +1,9 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2022 Alibaba Group Holding Limited.
* Copyright (C) 2023 Alibaba Group Holding Limited.
*/
#include "light-crash.dts"
#include "th1520-crash.dtsi"
&aon {
aon_reg_dialog: light-dialog-reg {
@@ -32,59 +32,67 @@
c910_0: cpu@0 {
operating-points = <
/* kHz uV */
300000 650000
300000 600000
800000 700000
1500000 800000
1848000 1000000
>;
light,dvddm-operating-points = <
/* kHz uV */
300000 800000
800000 800000
1500000 800000
1848000 1000000
>;
};
c910_1: cpu@1 {
operating-points = <
/* kHz uV */
300000 650000
300000 600000
800000 700000
1500000 800000
1848000 1000000
>;
light,dvddm-operating-points = <
/* kHz uV */
300000 800000
800000 800000
1500000 800000
1848000 1000000
>;
};
c910_2: cpu@2 {
operating-points = <
/* kHz uV */
300000 650000
300000 600000
800000 700000
1500000 800000
1848000 1000000
>;
light,dvddm-operating-points = <
/* kHz uV */
300000 800000
800000 800000
1500000 800000
1848000 1000000
>;
};
c910_3: cpu@3 {
operating-points = <
/* kHz uV */
300000 650000
300000 600000
800000 700000
1500000 800000
1848000 1000000
>;
light,dvddm-operating-points = <
/* kHz uV */
300000 800000
800000 800000
1500000 800000
1848000 1000000
>;
};
};

6
arch/riscv/boot/dts/thead/light-a-val-sec.dts → arch/riscv/boot/dts/thead/th1520-lpi4a-product-sec.dts
View File

@@ -5,9 +5,13 @@
/dts-v1/;
#include "light-a-val-dsi0-hdmi.dts"
#include "th1520-lpi4a-product.dts"
&light_iopmp {
status = "disabled";
};
&eip_28 {
status = "disabled";
};

50
arch/riscv/boot/dts/thead/th1520-lpi4a-product.dts Normal file
View File

@@ -0,0 +1,50 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2021 Alibaba Group Holding Limited.
*/
/dts-v1/;
#include "th1520-lpi4a-dsi0.dts"
&lightsound {
status = "okay";
simple-audio-card,dai-link@0 { /* I2S - HDMI*/
reg = <0>;
format = "i2s";
cpu {
sound-dai = <&light_i2s 1>;
};
codec {
sound-dai = <&dummy_codec>;
};
};
simple-audio-card,dai-link@1 { /* I2S - AUDIO SYS CODEC 7210*/
reg = <1>;
format = "i2s";
cpu {
sound-dai = <&i2s1 0>;
};
codec {
sound-dai = <&es7210_audio_codec>;
};
};
simple-audio-card,dai-link@2 { /* I2S - AUDIO SYS CODEC 8156*/
reg = <2>;
format = "i2s";
cpu {
sound-dai = <&i2s1 0>;
};
codec {
sound-dai = <&es8156_audio_codec>;
};
};
};
&dpu_enc0 {
status = "disabled";
};
&dsi0 {
status = "disabled";
};

1811
arch/riscv/boot/dts/thead/light-ant-discrete.dts → arch/riscv/boot/dts/thead/th1520-lpi4a.dtsi
View File

File diff suppressed because it is too large Load Diff

140
arch/riscv/boot/dts/thead/light-vi-devices.dtsi → arch/riscv/boot/dts/thead/th1520-vi-devices.dtsi
View File

@@ -4,9 +4,9 @@
*/
&video0{
status = "okay";
pipline0 {
pipline_id = <0>;
status = "disabled";
channel0 {
channel_id = <0>;
status = "okay";
sensor0 {
subdev_name = "vivcam";
@@ -31,8 +31,8 @@
path_type = "ISP_MI_PATH_MP";
};
};
pipline1 {
pipline_id = <1>;
channel1 {
channel_id = <1>;
status = "okay";
sensor0 {
subdev_name = "vivcam";
@@ -57,8 +57,8 @@
path_type = "ISP_MI_PATH_SP";
};
};
pipline2 {
pipline_id = <2>;
channel2 {
channel_id = <2>;
status = "okay";
sensor0 {
subdev_name = "vivcam";
@@ -86,9 +86,9 @@
};
&video1{
status = "okay";
pipline0 { // VSE0
pipline_id = <0>;
status = "disabled";
channel0 { // VSE0
channel_id = <0>;
status = "okay";
sensor0 {
subdev_name = "vivcam";
@@ -118,8 +118,8 @@
path_type = "DW_DWE_VSE0";
};
};
pipline1 { // VSE1
pipline_id = <1>;
channel1 { // VSE1
channel_id = <1>;
status = "okay";
sensor0 {
subdev_name = "vivcam";
@@ -149,8 +149,8 @@
path_type = "DW_DWE_VSE1";
};
};
pipline2 { // VSE2
pipline_id = <2>;
channel2 { // VSE2
channel_id = <2>;
status = "okay";
sensor0 {
subdev_name = "vivcam";
@@ -183,9 +183,9 @@
};
&video2 {
status = "okay";
pipline0 {
pipline_id = <0>;
status = "disabled";
channel0 {
channel_id = <0>;
status = "okay";
sensor0 {
subdev_name = "vivcam";
@@ -199,6 +199,12 @@
csi_idx = <0xff>;
path_type = "SENSOR_VGA_RAW10_LINER";
};
sensor2 {
subdev_name = "vivcam";
idx = <0xff>; // invalid
csi_idx = <0xff>;
path_type = "SENSOR_VGA_RAW10_LINER";
};
dma {
subdev_name = "vipre";
idx = <0>;
@@ -210,8 +216,8 @@
path_type = "ISP_MI_PATH_MP";
};
};
pipline1 {
pipline_id = <1>;
channel1 {
channel_id = <1>;
status = "okay";
sensor0 {
subdev_name = "vivcam";
@@ -236,8 +242,8 @@
path_type = "ISP_MI_PATH_SP";
};
};
pipline2 {
pipline_id = <2>;
channel2 {
channel_id = <2>;
status = "okay";
sensor0 {
subdev_name = "vivcam";
@@ -266,9 +272,9 @@
};
&video3 {
status = "okay";
pipline0 {
pipline_id = <0>;
status = "disabled";
channel0 {
channel_id = <0>;
status = "okay";
sensor0 {
subdev_name = "vivcam";
@@ -298,8 +304,8 @@
path_type = "DW_DWE_VSE0";
};
};
pipline1 {
pipline_id = <1>;
channel1 {
channel_id = <1>;
status = "okay";
sensor0 {
subdev_name = "vivcam";
@@ -330,8 +336,8 @@
path_type = "DW_DWE_VSE1";
};
};
pipline2 {
pipline_id = <2>;
channel2 {
channel_id = <2>;
status = "okay";
sensor0 {
subdev_name = "vivcam";
@@ -364,9 +370,9 @@
};
&video4 {
status = "okay";
pipline0 {
pipline_id = <0>;
status = "disabled";
channel0 {
channel_id = <0>;
status = "okay";
sensor0 {
subdev_name = "vivcam";
@@ -402,8 +408,8 @@
path_type = "ISP_RY_MI_PATH_MP";
};
};
pipline1 {
pipline_id = <1>;
channel1 {
channel_id = <1>;
status = "okay";
sensor0 {
subdev_name = "vivcam";
@@ -438,8 +444,8 @@
path_type = "ISP_RY_MI_PATH_SP";
};
};
pipline2 {
pipline_id = <2>;
channel2 {
channel_id = <2>;
status = "okay";
sensor0 {
subdev_name = "vivcam";
@@ -477,9 +483,9 @@
};
&video5 {
status = "okay";
pipline0 {
pipline_id = <0>;
status = "disabled";
channel0 {
channel_id = <0>;
status = "okay";
sensor0 {
subdev_name = "vivcam";
@@ -520,8 +526,8 @@
path_type = "DW_DWE_VSE0";
};
};
pipline1 {
pipline_id = <1>;
channel1 {
channel_id = <1>;
status = "okay";
sensor0 {
subdev_name = "vivcam";
@@ -561,8 +567,8 @@
path_type = "DW_DWE_VSE1";
};
};
pipline2 {
pipline_id = <2>;
channel2 {
channel_id = <2>;
status = "okay";
sensor0 {
subdev_name = "vivcam";
@@ -606,9 +612,9 @@
&video6 {
status = "okay";
pipline0 {
pipline_id = <0>;
status = "disabled";
channel0 {
channel_id = <0>;
status = "okay";
sensor0 {
subdev_name = "vivcam";
@@ -633,8 +639,8 @@
path_type = "DSP_PATH_VIPRE_ODD";
};
};
pipline1 {
pipline_id = <1>;
channel1 {
channel_id = <1>;
status = "okay";
sensor0 {
subdev_name = "vivcam";
@@ -663,9 +669,9 @@
&video7{
status = "okay";
pipline0 {
pipline_id = <0>;
status = "disabled";
channel0 {
channel_id = <0>;
status = "okay";
sensor0 {
subdev_name = "vivcam";
@@ -706,8 +712,8 @@
};
};
pipline1 {
pipline_id = <1>;
channel1 {
channel_id = <1>;
status = "okay";
sensor0 {
subdev_name = "vivcam";
@@ -747,8 +753,8 @@
path_type = "DW_DWE_VSE1";
};
};
pipline2 {
pipline_id = <2>;
channel2 {
channel_id = <2>;
status = "okay";
sensor0 {
subdev_name = "vivcam";
@@ -792,9 +798,9 @@
&video8{
status = "okay";
pipline0 {
pipline_id = <0>;
status = "disabled";
channel0 {
channel_id = <0>;
status = "okay";
sensor0 {
subdev_name = "vivcam";
@@ -823,9 +829,9 @@
&video9 { //IR debug
status = "okay";
pipline0 {
pipline_id = <0>;
status = "disabled";
channel0 {
channel_id = <0>;
status = "okay";
sensor0 {
subdev_name = "vivcam";
@@ -856,8 +862,8 @@
&video10{ // TUNING TOOL
status = "okay";
pipline0 { // CSI2X2_B
status = "disabled";
channel0 { // CSI2X2_B
status = "okay";
sensor0 {
subdev_name = "vivcam";
@@ -883,9 +889,9 @@
&video11{
status = "okay";
pipline0 {
pipline_id = <0>;
status = "disabled";
channel0 {
channel_id = <0>;
status = "okay";
sensor0 {
subdev_name = "vivcam";
@@ -914,8 +920,8 @@
&video12{ // TUNING TOOL
status = "okay";
pipline0 { // CSI2
status = "disabled";
channel0 { // CSI2
status = "okay";
sensor0 {
subdev_name = "vivcam";

913
arch/riscv/boot/dts/thead/light.dtsi → arch/riscv/boot/dts/thead/th1520.dtsi
View File

File diff suppressed because it is too large Load Diff

7
arch/riscv/configs/defconfig
View File

@@ -17,6 +17,12 @@ CONFIG_PERF_EVENTS=y
CONFIG_SOC_THEAD=y
CONFIG_SMP=y
CONFIG_VECTOR=y
CONFIG_HOTPLUG_CPU=y
CONFIG_PM=y
CONFIG_CPU_IDLE=y
CONFIG_VIRTUALIZATION=y
CONFIG_KVM=m
CONFIG_JUMP_LABEL=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
CONFIG_PARTITION_ADVANCED=y
@@ -183,6 +189,5 @@ CONFIG_DEBUG_INFO=y
CONFIG_MAGIC_SYSRQ=y
CONFIG_DEBUG_FS=y
CONFIG_DETECT_HUNG_TASK=y
CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=60
CONFIG_DEBUG_ATOMIC_SLEEP=y
# CONFIG_RCU_TRACE is not set

311
arch/riscv/configs/fire_defconfig Normal file
View File

@@ -0,0 +1,311 @@
CONFIG_SYSVIPC=y
CONFIG_POSIX_MQUEUE=y
CONFIG_NO_HZ_IDLE=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_PREEMPT=y
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_CGROUPS=y
CONFIG_NAMESPACES=y
CONFIG_USER_NS=y
CONFIG_CHECKPOINT_RESTORE=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_EXPERT=y
# CONFIG_BUG is not set
CONFIG_BPF_SYSCALL=y
CONFIG_PERF_EVENTS=y
CONFIG_FORCE_MAX_ZONEORDER=15
CONFIG_SOC_SIFIVE=y
CONFIG_SOC_THEAD=y
CONFIG_SMP=y
CONFIG_VECTOR=y
CONFIG_VECTOR_0_7=y
CONFIG_KEXEC=y
CONFIG_CRASH_DUMP=y
CONFIG_VIRTUALIZATION=y
CONFIG_KVM=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
CONFIG_CMA=y
CONFIG_CMA_DEBUGFS=y
CONFIG_CMA_AREAS=16
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_INET=y
CONFIG_IP_MULTICAST=y
CONFIG_IP_ADVANCED_ROUTER=y
CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y
CONFIG_IP_PNP_BOOTP=y
CONFIG_IP_PNP_RARP=y
CONFIG_BRIDGE=y
CONFIG_VSOCKETS=y
# CONFIG_VSOCKETS_LOOPBACK is not set
CONFIG_VIRTIO_VSOCKETS=y
CONFIG_NETLINK_DIAG=y
CONFIG_BT=y
CONFIG_BT_RFCOMM=y
CONFIG_BT_RFCOMM_TTY=y
CONFIG_BT_BNEP=y
CONFIG_BT_HIDP=y
CONFIG_BT_HCIUART=y
CONFIG_BT_HCIUART_H4=y
CONFIG_BT_HCIUART_RTL3WIRE=y
CONFIG_CFG80211=y
CONFIG_RFKILL=y
CONFIG_NET_9P=y
CONFIG_NET_9P_VIRTIO=y
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
CONFIG_MTD=y
CONFIG_MTD_TESTS=m
CONFIG_MTD_BLOCK=y
CONFIG_MTD_SLRAM=m
CONFIG_MTD_PHRAM=m
CONFIG_MTD_SPI_NAND=y
CONFIG_MTD_SPI_NOR=y
CONFIG_MTD_UBI=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_VIRTIO_BLK=y
CONFIG_LIGHT_DSMART_CARD=y
CONFIG_EEPROM_AT24=y
CONFIG_SCSI=y
CONFIG_BLK_DEV_SD=y
CONFIG_NETDEVICES=y
CONFIG_TUN=y
CONFIG_VIRTIO_NET=y
CONFIG_MACB=y
CONFIG_STMMAC_ETH=y
CONFIG_DWMAC_LIGHT=y
CONFIG_MICROSEMI_PHY=y
CONFIG_REALTEK_PHY=y
CONFIG_MARVELL_PHY=y
CONFIG_USB_USBNET=m
# CONFIG_USB_NET_AX8817X is not set
# CONFIG_USB_NET_AX88179_178A is not set
# CONFIG_USB_NET_NET1080 is not set
CONFIG_RTL8723DS=y
CONFIG_INPUT_MOUSEDEV=y
CONFIG_INPUT_EVDEV=y
CONFIG_KEYBOARD_GPIO=y
# CONFIG_INPUT_MOUSE is not set
CONFIG_INPUT_TOUCHSCREEN=y
CONFIG_TOUCHSCREEN_GOODIX=y
CONFIG_INPUT_MISC=y
CONFIG_INPUT_UINPUT=y
CONFIG_SERIAL_8250=y
# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_8250_NR_UARTS=6
CONFIG_SERIAL_8250_RUNTIME_UARTS=6
CONFIG_SERIAL_8250_DW=y
CONFIG_SERIAL_OF_PLATFORM=y
CONFIG_SERIAL_EARLYCON_RISCV_SBI=y
CONFIG_VIRTIO_CONSOLE=y
CONFIG_HW_RANDOM=y
CONFIG_HW_RANDOM_VIRTIO=y
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_DESIGNWARE_PLATFORM=y
CONFIG_SPI=y
CONFIG_SPI_DW_QUAD=y
CONFIG_SPI_DESIGNWARE=y
CONFIG_SPI_DW_MMIO=y
CONFIG_SPI_SPIDEV=y
# CONFIG_PTP_1588_CLOCK is not set
CONFIG_PINCTRL=y
CONFIG_GPIOLIB=y
CONFIG_GPIO_SYSFS=y
CONFIG_GPIO_DWAPB=y
CONFIG_GPIO_PCA953X=y
CONFIG_GPIO_PCA953X_IRQ=y
CONFIG_POWER_SUPPLY=y
CONFIG_SENSORS_MR75203=y
CONFIG_THERMAL=y
CONFIG_CPU_THERMAL=y
CONFIG_THERMAL_EMULATION=y
CONFIG_WATCHDOG=y
CONFIG_DW_WATCHDOG=y
CONFIG_LIGHT_PMIC_WATCHDOG=y
CONFIG_WATCHDOG_PRETIMEOUT_GOV=y
CONFIG_WATCHDOG_PRETIMEOUT_GOV_SEL=m
CONFIG_WATCHDOG_PRETIMEOUT_GOV_PANIC=y
#CONFIG_WATCHDOG_PRETIMEOUT_DEFAULT_GOV_PANIC=y
CONFIG_WATCHDOG_PRETIMEOUT_DEFAULT_GOV_NOOP=y
CONFIG_WATCHDOG_OPEN_TIMEOUT=32
CONFIG_ABX500_CORE=y
CONFIG_REGULATOR=y
CONFIG_REGULATOR_FIXED_VOLTAGE=y
CONFIG_MEDIA_SUPPORT=y
# CONFIG_MEDIA_ANALOG_TV_SUPPORT is not set
# CONFIG_MEDIA_DIGITAL_TV_SUPPORT is not set
CONFIG_MEDIA_USB_SUPPORT=y
CONFIG_USB_VIDEO_CLASS=m
CONFIG_V4L_PLATFORM_DRIVERS=y
CONFIG_VIDEO_ASPEED=y
CONFIG_V4L_MEM2MEM_DRIVERS=y
# CONFIG_MEDIA_TUNER_SIMPLE is not set
# CONFIG_MEDIA_TUNER_TDA18250 is not set
# CONFIG_MEDIA_TUNER_TDA8290 is not set
# CONFIG_MEDIA_TUNER_TDA827X is not set
# CONFIG_MEDIA_TUNER_TDA18271 is not set
# CONFIG_MEDIA_TUNER_TDA9887 is not set
# CONFIG_MEDIA_TUNER_TEA5761 is not set
# CONFIG_MEDIA_TUNER_TEA5767 is not set
# CONFIG_MEDIA_TUNER_MSI001 is not set
# CONFIG_MEDIA_TUNER_MT20XX is not set
# CONFIG_MEDIA_TUNER_MT2060 is not set
# CONFIG_MEDIA_TUNER_MT2063 is not set
# CONFIG_MEDIA_TUNER_MT2266 is not set
# CONFIG_MEDIA_TUNER_MT2131 is not set
# CONFIG_MEDIA_TUNER_QT1010 is not set
# CONFIG_MEDIA_TUNER_XC2028 is not set
# CONFIG_MEDIA_TUNER_XC5000 is not set
# CONFIG_MEDIA_TUNER_XC4000 is not set
# CONFIG_MEDIA_TUNER_MXL5005S is not set
# CONFIG_MEDIA_TUNER_MXL5007T is not set
# CONFIG_MEDIA_TUNER_MC44S803 is not set
# CONFIG_MEDIA_TUNER_MAX2165 is not set
# CONFIG_MEDIA_TUNER_TDA18218 is not set
# CONFIG_MEDIA_TUNER_FC0011 is not set
# CONFIG_MEDIA_TUNER_FC0012 is not set
# CONFIG_MEDIA_TUNER_FC0013 is not set
# CONFIG_MEDIA_TUNER_TDA18212 is not set
# CONFIG_MEDIA_TUNER_E4000 is not set
# CONFIG_MEDIA_TUNER_FC2580 is not set
# CONFIG_MEDIA_TUNER_M88RS6000T is not set
# CONFIG_MEDIA_TUNER_TUA9001 is not set
# CONFIG_MEDIA_TUNER_SI2157 is not set
# CONFIG_MEDIA_TUNER_IT913X is not set
# CONFIG_MEDIA_TUNER_R820T is not set
# CONFIG_MEDIA_TUNER_MXL301RF is not set
# CONFIG_MEDIA_TUNER_QM1D1C0042 is not set
# CONFIG_MEDIA_TUNER_QM1D1B0004 is not set
CONFIG_DRM=y
CONFIG_DRM_PANEL_SIMPLE=y
CONFIG_DRM_PANEL_ILITEK_ILI9881C=y
CONFIG_DRM_PANEL_ILI9881D=y
CONFIG_DRM_VERISILICON=y
CONFIG_BACKLIGHT_CLASS_DEVICE=y
CONFIG_BACKLIGHT_PWM=y
CONFIG_FRAMEBUFFER_CONSOLE=y
CONFIG_LOGO=y
CONFIG_SOUND=y
CONFIG_SND=y
CONFIG_SND_USB_AUDIO=m
CONFIG_SND_SOC=y
CONFIG_SND_SOC_THEAD_LIGHT=y
CONFIG_SND_SOC_AW87519=y
CONFIG_SND_SOC_BT_SCO=y
CONFIG_SND_SOC_ES7210=y
CONFIG_SND_SOC_ES8156=y
CONFIG_SND_SOC_WM8960=y
CONFIG_SND_SIMPLE_CARD=y
CONFIG_SND_AUDIO_GRAPH_CARD=y
CONFIG_UHID=y
CONFIG_HID_PID=y
CONFIG_USB_HIDDEV=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_PLATFORM=y
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_USB_STORAGE_SDDR09=y
CONFIG_USB_STORAGE_SDDR55=y
CONFIG_USB_DWC3=m
# CONFIG_USB_DWC3_OF_SIMPLE is not set
CONFIG_USB_GADGET=y
CONFIG_USB_CONFIGFS=y
CONFIG_USB_CONFIGFS_F_FS=y
CONFIG_USB_CONFIGFS_F_ACC=y
CONFIG_USB_ZERO=m
CONFIG_USB_ETH=m
CONFIG_USB_ETH_EEM=y
CONFIG_USB_G_NCM=m
CONFIG_USB_MASS_STORAGE=m
CONFIG_USB_G_SERIAL=m
CONFIG_USB_G_MULTI=m
CONFIG_USB_G_MULTI_CDC=y
CONFIG_USB_ROLE_SWITCH=m
CONFIG_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_PLTFM=y
CONFIG_MMC_SDHCI_OF_DWCMSHC=y
CONFIG_NEW_LEDS=y
CONFIG_LEDS_CLASS=y
CONFIG_LEDS_GPIO=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_DRV_XGENE=y
CONFIG_DMADEVICES=y
CONFIG_DW_AXI_DMAC=y
CONFIG_DMATEST=y
CONFIG_SW_SYNC=y
CONFIG_UDMABUF=y
CONFIG_DMABUF_SELFTESTS=m
CONFIG_VIRTIO_MMIO=y
CONFIG_VIRTIO_KHV_MMIO=y
CONFIG_VHOST_NET=y
CONFIG_VHOST_VSOCK=y
CONFIG_CLK_LIGHT_FM=y
CONFIG_HWSPINLOCK=y
CONFIG_HWSPINLOCK_LIGHT=y
CONFIG_HWSPINLOCK_LIGHT_TEST=m
CONFIG_MAILBOX=y
CONFIG_EXTCON=y
CONFIG_IIO=y
CONFIG_IIO_SW_DEVICE=y
CONFIG_PWM=y
CONFIG_PWM_LIGHT=y
CONFIG_NVMEM_THEAD_LIGHT_EFUSE=y
CONFIG_TEE=y
CONFIG_OPTEE=y
CONFIG_OPTEE_BENCHMARK=y
CONFIG_LIGHT_GPU_VIV=m
# CONFIG_LIGHT_NET is not set
CONFIG_EXT4_FS=y
CONFIG_EXT4_FS_POSIX_ACL=y
CONFIG_AUTOFS4_FS=y
CONFIG_FUSE_FS=y
CONFIG_MSDOS_FS=y
CONFIG_VFAT_FS=y
CONFIG_TMPFS=y
CONFIG_TMPFS_POSIX_ACL=y
CONFIG_HUGETLBFS=y
CONFIG_JFFS2_FS=y
CONFIG_UBIFS_FS=y
CONFIG_NFS_FS=y
CONFIG_NFS_V4=y
CONFIG_NFS_V4_1=y
CONFIG_NFS_V4_2=y
CONFIG_ROOT_NFS=y
CONFIG_9P_FS=y
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_ISO8859_1=y
CONFIG_CRYPTO_AUTHENC=y
CONFIG_CRYPTO_DH=y
CONFIG_CRYPTO_CURVE25519=y
CONFIG_CRYPTO_CHACHA20POLY1305=y
CONFIG_CRYPTO_OFB=y
CONFIG_CRYPTO_MD5=y
CONFIG_CRYPTO_SHA512=y
CONFIG_CRYPTO_SHA3=y
CONFIG_CRYPTO_SM3=y
CONFIG_CRYPTO_DES=y
CONFIG_CRYPTO_USER_API_HASH=y
CONFIG_DMA_CMA=y
CONFIG_DMA_PERNUMA_CMA=y
CONFIG_CMA_SIZE_MBYTES=32
CONFIG_PRINTK_TIME=y
CONFIG_DYNAMIC_DEBUG=y
CONFIG_DEBUG_INFO=y
CONFIG_MAGIC_SYSRQ=y
CONFIG_DEBUG_FS=y
CONFIG_DETECT_HUNG_TASK=y
CONFIG_DEBUG_ATOMIC_SLEEP=y
# CONFIG_RCU_TRACE is not set
CONFIG_OVERLAY_FS=y
CONFIG_LOCKUP_DETECTOR=y
CONFIG_SOFTLOCKUP_DETECTOR=y
CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
# CONFIG_SUSPEND is not set
# CONFIG_PM_SLEEP is not set

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