feat: enable BT_RTKBT as module

Signed-off-by: Han Gao/Revy/Rabenda <gaohan@iscas.ac.cn>

.github/workflows/kernel.yml

@@ -0,0 +1,97 @@
+name: revyos-kernel-build
+
+on:
+  push:
+  pull_request:
+  workflow_dispatch:
+  schedule:
+    - cron: "0 2 * * *"
+
+env:
+  xuantie_toolchain: https://occ-oss-prod.oss-cn-hangzhou.aliyuncs.com/resource//1705395627867
+  toolchain_file_name: Xuantie-900-gcc-linux-5.10.4-glibc-x86_64-V2.8.1-20240115.tar.gz
+  mainline_toolchain: https://github.com/riscv-collab/riscv-gnu-toolchain/releases/download/2024.03.01
+  mainline_toolchain_file_name: riscv64-glibc-ubuntu-22.04-gcc-nightly-2024.03.01-nightly.tar.gz
+  wget_alias: 'wget --retry-connrefused --waitretry=1 --read-timeout=20 --timeout=15 -t 0'
+  ARCH: riscv
+  board: th1520
+  KBUILD_BUILD_USER: builder
+  KBUILD_BUILD_HOST: revyos-riscv-builder
+  KDEB_COMPRESS: none
+  KDEB_CHANGELOG_DIST: unstable
+
+jobs:
+  kernel:
+    strategy:
+      fail-fast: false
+      matrix:
+        include:
+          - name: gcc-13
+            cross: riscv64-unknown-linux-gnu-
+            machine: ubuntu-22.04
+            run_image: ghcr.io/revyos/revyos-kernel-builder:amd64-2024.04.02
+          - name: thead-gcc
+            cross: riscv64-unknown-linux-gnu-
+            machine: ubuntu-22.04
+            run_image: ghcr.io/revyos/revyos-kernel-builder:amd64-2024.04.02
+          - name: native
+            cross: riscv64-linux-gnu-
+            machine: [ self-hosted, Linux, riscv64 ]
+            run_image: ghcr.io/revyos/revyos-kernel-builder:riscv64-2024.04.02
+
+    runs-on: ${{ matrix.machine }}
+    container:
+      image: ${{ matrix.run_image }}
+    env:
+      CROSS_COMPILE: ${{ matrix.cross }}
+
+    steps:
+      - name: Checkout kernel
+        uses: actions/checkout@v4
+        with:
+            path: 'kernel'
+
+      - name: Compile Kernel && Install
+        run: |
+              mkdir -p rootfs
+              if [[ ${{ matrix.name }} = "thead-gcc" ]]; then
+                ${wget_alias} ${xuantie_toolchain}/${toolchain_file_name}
+                tar -xvf ${toolchain_file_name} -C /opt
+                export PATH="/opt/Xuantie-900-gcc-linux-5.10.4-glibc-x86_64-V2.8.1/bin:$PATH"
+              elif [[ ${{ matrix.name }} = "gcc-13" ]]; then
+                ${wget_alias} ${mainline_toolchain}/${mainline_toolchain_file_name}
+                tar -xvf ${mainline_toolchain_file_name} -C /opt
+                export PATH="/opt/riscv/bin:$PATH"
+              else
+                echo "No download toolchain."
+              fi
+              ${CROSS_COMPILE}gcc -v
+
+              pushd kernel
+                make revyos_defconfig
+                export KDEB_PKGVERSION="$(make kernelversion)-$(date "+%Y.%m.%d.%H.%M")+$(git rev-parse --short HEAD)"
+                sed -i '/CONFIG_LOCALVERSION_AUTO/d' .config && echo "CONFIG_LOCALVERSION_AUTO=n" >> .config
+                cat .config | grep "CONFIG_THEAD_ISA"
+                if [ `uname -m` = "riscv64" ]; then
+                  # FIXME: force use 32 thread
+                  make -j32 bindeb-pkg LOCALVERSION="-${board}"
+                else
+                  make -j$(nproc) bindeb-pkg LOCALVERSION="-${board}"
+                fi
+                
+                # Copy deb
+                dcmd cp -v ../*.changes ${GITHUB_WORKSPACE}/rootfs/
+
+                # record commit-id
+                git rev-parse HEAD > kernel-commitid
+                cp -v kernel-commitid ${GITHUB_WORKSPACE}/rootfs/
+
+                ls -al ${GITHUB_WORKSPACE}/rootfs/
+              popd
+
+      - name: 'Upload Artifact'
+        uses: actions/upload-artifact@v4
+        with:
+          name: thead-kernel-${{ matrix.name }}
+          path: rootfs/*
+          retention-days: 30

.gitignore

@@ -18,6 +18,7 @@
 *.c.[012]*.*
 *.dt.yaml
 *.dtb
+*.dtbo
 *.dtb.S
 *.dwo
 *.elf

Documentation/devicetree/bindings/arm/msm/qcom,idle-state.txt

@@ -81,4 +81,4 @@ Example:
 		};
 	};
 
-[1]. Documentation/devicetree/bindings/arm/idle-states.yaml
+[1]. Documentation/devicetree/bindings/cpu/idle-states.yaml

Documentation/devicetree/bindings/arm/psci.yaml

@@ -101,7 +101,7 @@ properties:
       bindings in [1]) must specify this property.
 
       [1] Kernel documentation - ARM idle states bindings
-        Documentation/devicetree/bindings/arm/idle-states.yaml
+        Documentation/devicetree/bindings/cpu/idle-states.yaml
 
 patternProperties:
   "^power-domain-":

Documentation/devicetree/bindings/cpu/idle-states.yaml

@@ -1,25 +1,30 @@
 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
 %YAML 1.2
 ---
-$id: http://devicetree.org/schemas/arm/idle-states.yaml#
+$id: http://devicetree.org/schemas/cpu/idle-states.yaml#
 $schema: http://devicetree.org/meta-schemas/core.yaml#
 
-title: ARM idle states binding description
+title: Idle states binding description
 
 maintainers:
   - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
+  - Anup Patel <anup@brainfault.org>
 
 description: |+
   ==========================================
   1 - Introduction
   ==========================================
 
-  ARM systems contain HW capable of managing power consumption dynamically,
-  where cores can be put in different low-power states (ranging from simple wfi
-  to power gating) according to OS PM policies. The CPU states representing the
-  range of dynamic idle states that a processor can enter at run-time, can be
-  specified through device tree bindings representing the parameters required to
-  enter/exit specific idle states on a given processor.
+  ARM and RISC-V systems contain HW capable of managing power consumption
+  dynamically, where cores can be put in different low-power states (ranging
+  from simple wfi to power gating) according to OS PM policies. The CPU states
+  representing the range of dynamic idle states that a processor can enter at
+  run-time, can be specified through device tree bindings representing the
+  parameters required to enter/exit specific idle states on a given processor.
+
+  ==========================================
+  2 - ARM idle states
+  ==========================================
 
   According to the Server Base System Architecture document (SBSA, [3]), the
   power states an ARM CPU can be put into are identified by the following list:
@@ -43,8 +48,23 @@ description: |+
   The device tree binding definition for ARM idle states is the subject of this
   document.
 
+  ==========================================
+  3 - RISC-V idle states
+  ==========================================
+
+  On RISC-V systems, the HARTs (or CPUs) [6] can be put in platform specific
+  suspend (or idle) states (ranging from simple WFI, power gating, etc). The
+  RISC-V SBI v0.3 (or higher) [7] hart state management extension provides a
+  standard mechanism for OS to request HART state transitions.
+
+  The platform specific suspend (or idle) states of a hart can be either
+  retentive or non-rententive in nature. A retentive suspend state will
+  preserve HART registers and CSR values for all privilege modes whereas
+  a non-retentive suspend state will not preserve HART registers and CSR
+  values.
+
   ===========================================
-  2 - idle-states definitions
+  4 - idle-states definitions
   ===========================================
 
   Idle states are characterized for a specific system through a set of
@@ -211,10 +231,10 @@ description: |+
   properties specification that is the subject of the following sections.
 
   ===========================================
-  3 - idle-states node
+  5 - idle-states node
   ===========================================
 
-  ARM processor idle states are defined within the idle-states node, which is
+  The processor idle states are defined within the idle-states node, which is
   a direct child of the cpus node [1] and provides a container where the
   processor idle states, defined as device tree nodes, are listed.
 
@@ -223,7 +243,7 @@ description: |+
   just supports idle_standby, an idle-states node is not required.
 
   ===========================================
-  4 - References
+  6 - References
   ===========================================
 
   [1] ARM Linux Kernel documentation - CPUs bindings
@@ -238,9 +258,15 @@ description: |+
   [4] ARM Architecture Reference Manuals
       http://infocenter.arm.com/help/index.jsp
 
-  [6] ARM Linux Kernel documentation - Booting AArch64 Linux
+  [5] ARM Linux Kernel documentation - Booting AArch64 Linux
       Documentation/arm64/booting.rst
 
+  [6] RISC-V Linux Kernel documentation - CPUs bindings
+      Documentation/devicetree/bindings/riscv/cpus.yaml
+
+  [7] RISC-V Supervisor Binary Interface (SBI)
+      http://github.com/riscv/riscv-sbi-doc/riscv-sbi.adoc
+
 properties:
   $nodename:
     const: idle-states
@@ -253,7 +279,7 @@ properties:
       On ARM 32-bit systems this property is optional
 
       This assumes that the "enable-method" property is set to "psci" in the cpu
-      node[6] that is responsible for setting up CPU idle management in the OS
+      node[5] that is responsible for setting up CPU idle management in the OS
       implementation.
     const: psci
 
@@ -265,8 +291,8 @@ patternProperties:
       as follows.
 
       The idle state entered by executing the wfi instruction (idle_standby
-      SBSA,[3][4]) is considered standard on all ARM platforms and therefore
-      must not be listed.
+      SBSA,[3][4]) is considered standard on all ARM and RISC-V platforms and
+      therefore must not be listed.
 
       In addition to the properties listed above, a state node may require
       additional properties specific to the entry-method defined in the
@@ -275,7 +301,27 @@ patternProperties:
 
     properties:
       compatible:
-        const: arm,idle-state
+        enum:
+          - arm,idle-state
+          - riscv,idle-state
+
+      arm,psci-suspend-param:
+        $ref: /schemas/types.yaml#/definitions/uint32
+        description: |
+          power_state parameter to pass to the ARM PSCI suspend call.
+
+          Device tree nodes that require usage of PSCI CPU_SUSPEND function
+          (i.e. idle states node with entry-method property is set to "psci")
+          must specify this property.
+
+      riscv,sbi-suspend-param:
+        $ref: /schemas/types.yaml#/definitions/uint32
+        description: |
+          suspend_type parameter to pass to the RISC-V SBI HSM suspend call.
+
+          This property is required in idle state nodes of device tree meant
+          for RISC-V systems. For more details on the suspend_type parameter
+          refer the SBI specifiation v0.3 (or higher) [7].
 
       local-timer-stop:
         description:
@@ -317,6 +363,8 @@ patternProperties:
         description:
           A string used as a descriptive name for the idle state.
 
+    additionalProperties: false
+
     required:
       - compatible
       - entry-latency-us
@@ -658,4 +706,150 @@ examples:
         };
     };
 
+  - |
+    // Example 3 (RISC-V 64-bit, 4-cpu systems, two clusters):
+
+    cpus {
+        #size-cells = <0>;
+        #address-cells = <1>;
+
+        cpu@0 {
+            device_type = "cpu";
+            compatible = "riscv";
+            reg = <0x0>;
+            riscv,isa = "rv64imafdc";
+            mmu-type = "riscv,sv48";
+            cpu-idle-states = <&CPU_RET_0_0 &CPU_NONRET_0_0
+                            &CLUSTER_RET_0 &CLUSTER_NONRET_0>;
+
+            cpu_intc0: interrupt-controller {
+                #interrupt-cells = <1>;
+                compatible = "riscv,cpu-intc";
+                interrupt-controller;
+            };
+        };
+
+        cpu@1 {
+            device_type = "cpu";
+            compatible = "riscv";
+            reg = <0x1>;
+            riscv,isa = "rv64imafdc";
+            mmu-type = "riscv,sv48";
+            cpu-idle-states = <&CPU_RET_0_0 &CPU_NONRET_0_0
+                            &CLUSTER_RET_0 &CLUSTER_NONRET_0>;
+
+            cpu_intc1: interrupt-controller {
+                #interrupt-cells = <1>;
+                compatible = "riscv,cpu-intc";
+                interrupt-controller;
+            };
+        };
+
+        cpu@10 {
+            device_type = "cpu";
+            compatible = "riscv";
+            reg = <0x10>;
+            riscv,isa = "rv64imafdc";
+            mmu-type = "riscv,sv48";
+            cpu-idle-states = <&CPU_RET_1_0 &CPU_NONRET_1_0
+                            &CLUSTER_RET_1 &CLUSTER_NONRET_1>;
+
+            cpu_intc10: interrupt-controller {
+                #interrupt-cells = <1>;
+                compatible = "riscv,cpu-intc";
+                interrupt-controller;
+            };
+        };
+
+        cpu@11 {
+            device_type = "cpu";
+            compatible = "riscv";
+            reg = <0x11>;
+            riscv,isa = "rv64imafdc";
+            mmu-type = "riscv,sv48";
+            cpu-idle-states = <&CPU_RET_1_0 &CPU_NONRET_1_0
+                            &CLUSTER_RET_1 &CLUSTER_NONRET_1>;
+
+            cpu_intc11: interrupt-controller {
+                #interrupt-cells = <1>;
+                compatible = "riscv,cpu-intc";
+                interrupt-controller;
+            };
+        };
+
+        idle-states {
+            CPU_RET_0_0: cpu-retentive-0-0 {
+                compatible = "riscv,idle-state";
+                riscv,sbi-suspend-param = <0x10000000>;
+                entry-latency-us = <20>;
+                exit-latency-us = <40>;
+                min-residency-us = <80>;
+            };
+
+            CPU_NONRET_0_0: cpu-nonretentive-0-0 {
+                compatible = "riscv,idle-state";
+                riscv,sbi-suspend-param = <0x90000000>;
+                entry-latency-us = <250>;
+                exit-latency-us = <500>;
+                min-residency-us = <950>;
+            };
+
+            CLUSTER_RET_0: cluster-retentive-0 {
+                compatible = "riscv,idle-state";
+                riscv,sbi-suspend-param = <0x11000000>;
+                local-timer-stop;
+                entry-latency-us = <50>;
+                exit-latency-us = <100>;
+                min-residency-us = <250>;
+                wakeup-latency-us = <130>;
+            };
+
+            CLUSTER_NONRET_0: cluster-nonretentive-0 {
+                compatible = "riscv,idle-state";
+                riscv,sbi-suspend-param = <0x91000000>;
+                local-timer-stop;
+                entry-latency-us = <600>;
+                exit-latency-us = <1100>;
+                min-residency-us = <2700>;
+                wakeup-latency-us = <1500>;
+            };
+
+            CPU_RET_1_0: cpu-retentive-1-0 {
+                compatible = "riscv,idle-state";
+                riscv,sbi-suspend-param = <0x10000010>;
+                entry-latency-us = <20>;
+                exit-latency-us = <40>;
+                min-residency-us = <80>;
+            };
+
+            CPU_NONRET_1_0: cpu-nonretentive-1-0 {
+                compatible = "riscv,idle-state";
+                riscv,sbi-suspend-param = <0x90000010>;
+                entry-latency-us = <250>;
+                exit-latency-us = <500>;
+                min-residency-us = <950>;
+            };
+
+            CLUSTER_RET_1: cluster-retentive-1 {
+                compatible = "riscv,idle-state";
+                riscv,sbi-suspend-param = <0x11000010>;
+                local-timer-stop;
+                entry-latency-us = <50>;
+                exit-latency-us = <100>;
+                min-residency-us = <250>;
+                wakeup-latency-us = <130>;
+            };
+
+            CLUSTER_NONRET_1: cluster-nonretentive-1 {
+                compatible = "riscv,idle-state";
+                riscv,sbi-suspend-param = <0x91000010>;
+                local-timer-stop;
+                entry-latency-us = <600>;
+                exit-latency-us = <1100>;
+                min-residency-us = <2700>;
+                wakeup-latency-us = <1500>;
+            };
+        };
+    };
+
 ...

Documentation/devicetree/bindings/riscv/cpus.yaml

@@ -87,6 +87,12 @@ properties:
       - compatible
       - interrupt-controller
 
+  cpu-idle-states:
+    $ref: '/schemas/types.yaml#/definitions/phandle-array'
+    description: |
+      List of phandles to idle state nodes supported
+      by this hart (see ./idle-states.yaml).
+
 required:
   - riscv,isa
   - interrupt-controller

MAINTAINERS

@@ -4614,6 +4614,20 @@ S:	Supported
 F:	drivers/cpuidle/cpuidle-psci.h
 F:	drivers/cpuidle/cpuidle-psci-domain.c
 
+CPUIDLE DRIVER - DT IDLE PM DOMAIN
+M:	Ulf Hansson <ulf.hansson@linaro.org>
+L:	linux-pm@vger.kernel.org
+S:	Supported
+F:	drivers/cpuidle/dt_idle_genpd.c
+F:	drivers/cpuidle/dt_idle_genpd.h
+
+CPUIDLE DRIVER - RISC-V SBI
+M:	Anup Patel <anup@brainfault.org>
+L:	linux-pm@vger.kernel.org
+L:	linux-riscv@lists.infradead.org
+S:	Maintained
+F:	drivers/cpuidle/cpuidle-riscv-sbi.c
+
 CRAMFS FILESYSTEM
 M:	Nicolas Pitre <nico@fluxnic.net>
 S:	Maintained

Makefile

@@ -480,6 +480,8 @@ LZ4		= lz4
 XZ		= xz
 ZSTD		= zstd
 
+PAHOLE_FLAGS	= $(shell PAHOLE=$(PAHOLE) $(srctree)/scripts/pahole-flags.sh)
+
 CHECKFLAGS     := -D__linux__ -Dlinux -D__STDC__ -Dunix -D__unix__ \
 		  -Wbitwise -Wno-return-void -Wno-unknown-attribute $(CF)
 NOSTDINC_FLAGS :=
@@ -534,6 +536,7 @@ export KBUILD_CFLAGS CFLAGS_KERNEL CFLAGS_MODULE
 export KBUILD_AFLAGS AFLAGS_KERNEL AFLAGS_MODULE
 export KBUILD_AFLAGS_MODULE KBUILD_CFLAGS_MODULE KBUILD_LDFLAGS_MODULE
 export KBUILD_AFLAGS_KERNEL KBUILD_CFLAGS_KERNEL
+export PAHOLE_FLAGS
 
 # Files to ignore in find ... statements
 

arch/riscv/Kconfig

@@ -18,10 +18,10 @@ config RISCV
 	select ARCH_HAS_DEBUG_VM_PGTABLE
 	select ARCH_HAS_DEBUG_VIRTUAL if MMU
 	select ARCH_HAS_DEBUG_WX
+	select ARCH_HAS_FAST_MULTIPLIER
 	select ARCH_HAS_GCOV_PROFILE_ALL
 	select ARCH_HAS_GIGANTIC_PAGE
 	select ARCH_HAS_KCOV
-	select ARCH_HAS_MMIOWB
 	select ARCH_HAS_PTE_SPECIAL
 	select ARCH_HAS_SET_DIRECT_MAP
 	select ARCH_HAS_SET_MEMORY
@@ -32,15 +32,19 @@ config RISCV
 	select ARCH_HAS_SYNC_DMA_FOR_DEVICE
 	select ARCH_HAS_DMA_WRITE_COMBINE
 	select ARCH_HAS_DMA_MMAP_PGPROT
+	select ARCH_KEEP_MEMBLOCK
 	select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX
 	select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT
+	select ARCH_USE_CMPXCHG_LOCKREF
+	select ARCH_USE_QUEUED_SPINLOCKS
+	select ARCH_USE_QUEUED_RWLOCKS
 	select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU
 	select ARCH_WANT_FRAME_POINTERS
 	select ARCH_WANT_HUGE_PMD_SHARE if 64BIT
 	select CLONE_BACKWARDS
 	select CLINT_TIMER if !MMU
 	select COMMON_CLK
-	select CPU_PM if (SUSPEND || CPU_IDLE)
+	select CPU_PM if CPU_IDLE || HIBERNATION
 	select COMPAT_BINFMT_ELF if BINFMT_ELF && COMPAT
 	select EDAC_SUPPORT
 	select DMA_DIRECT_REMAP
@@ -360,6 +364,8 @@ config RISCV_ISA_C
 
 config NO_SFENCE_VMA
 	bool "Replace sfence.vma with CSR_SMCIR operation"
+	depends on !SMP
+	default y
 
 config RISCV_SWIOTLB
 	bool "Enable SWIOTLB"
@@ -389,45 +395,19 @@ config FPU
 	  If you don't know what to do here, say Y.
 
 config VECTOR
-	bool "VECTOR support"
-	default n
-
-choice VECTOR_VERSION
-	prompt "Vector Version"
-	depends on VECTOR
-	default VECTOR_1_0
-
-config VECTOR_1_0
-	bool "VECTOR 1.0 support"
-	help
-	  Say N here if you want to disable all vector 1.0 related procedure
-	  in the kernel.
-
-	  If you don't know what to do here, say Y.
-
-config VECTOR_0_7
 	bool "VECTOR 0.7 support"
+	default y
 	help
 	  Say N here if you want to disable all vector 0.7 related procedure
 	  in the kernel.
 
 	  If you don't know what to do here, say Y.
 
-endchoice
-
-config VLEN_256
-	bool "VECTOR VLEN 256"
-	depends on VECTOR
-	default n
-
-config VECTOR_EMU
-	bool "VECTOR e64 emulate for c906 v1"
-	depends on VECTOR
-	default n
-
 config THEAD_ISA
 	bool "T-HEAD extension ISA in AFLAGS with -march=_xtheadc"
-	default n
+	default y
+	help
+	  Say N here if you want to disable xtheadc in the kernel.
 
 endmenu
 
@@ -569,6 +549,18 @@ source "kernel/power/Kconfig"
 config ARCH_SUSPEND_POSSIBLE
 	def_bool y
 
+config ARCH_HIBERNATION_POSSIBLE
+	def_bool y
+
+config ARCH_HIBERNATION_HEADER
+	def_bool HIBERNATION
+
+endmenu
+
+menu "CPU Power Management"
+
+source "drivers/cpuidle/Kconfig"
+
 endmenu
 
 source "arch/riscv/kvm/Kconfig"

arch/riscv/Kconfig.socs

@@ -19,6 +19,9 @@ config SOC_VIRT
 	select GOLDFISH
 	select RTC_DRV_GOLDFISH if RTC_CLASS
 	select SIFIVE_PLIC
+	select PM_GENERIC_DOMAINS if PM
+	select PM_GENERIC_DOMAINS_OF if PM && OF
+	select RISCV_SBI_CPUIDLE if CPU_IDLE
 	help
 	  This enables support for QEMU Virt Machine.
 

arch/riscv/Makefile

@@ -48,25 +48,25 @@ endif
 endif
 
 # ISA string setting
+riscv-march-$(CONFIG_ARCH_RV32I)	:= rv32ima
+riscv-march-$(CONFIG_ARCH_RV64I)	:= rv64ima
+riscv-march-$(CONFIG_FPU)		:= $(riscv-march-y)fd
+riscv-march-$(CONFIG_RISCV_ISA_C)	:= $(riscv-march-y)c
+
+# Fix mainline build
+toolchain-have-v0p7 := $(call cc-option-yn, -march=$(riscv-march-y)v0p7)
+riscv-march-$(toolchain-have-v0p7) := $(riscv-march-y)v0p7
+
+toolchain-have-xtheadc := $(call cc-option-yn, -march=$(riscv-march-y)_xtheadc)
+riscv-march-$(toolchain-have-xtheadc) := $(riscv-march-y)_xtheadc
+
 # Newer binutils versions default to ISA spec version 20191213 which moves some
 # instructions from the I extension to the Zicsr and Zifencei extensions.
 toolchain-need-zicsr-zifencei := $(call cc-option-yn, -march=$(riscv-march-y)_zicsr_zifencei)
 riscv-march-$(toolchain-need-zicsr-zifencei) := $(riscv-march-y)_zicsr_zifencei
 
-riscv-march-cflags-$(CONFIG_ARCH_RV32I)		:= rv32ima
-riscv-march-cflags-$(CONFIG_ARCH_RV64I)		:= rv64ima
-riscv-march-cflags-$(CONFIG_RISCV_ISA_C)	:= $(riscv-march-cflags-y)c
-
-riscv-march-aflags-$(CONFIG_ARCH_RV32I)		:= rv32ima
-riscv-march-aflags-$(CONFIG_ARCH_RV64I)		:= rv64ima
-riscv-march-aflags-$(CONFIG_FPU)		:= $(riscv-march-aflags-y)fd
-riscv-march-aflags-$(CONFIG_RISCV_ISA_C)	:= $(riscv-march-aflags-y)c
-riscv-march-aflags-$(CONFIG_VECTOR_1_0)		:= $(riscv-march-aflags-y)v
-riscv-march-aflags-$(CONFIG_VECTOR_0_7)		:= $(riscv-march-aflags-y)v0p7
-riscv-march-aflags-$(CONFIG_THEAD_ISA)		:= $(riscv-march-aflags-y)_xtheadc
-
-KBUILD_CFLAGS += -march=$(riscv-march-cflags-y) -Wa,-march=$(riscv-march-aflags-y)
-KBUILD_AFLAGS += -march=$(riscv-march-aflags-y)
+KBUILD_CFLAGS += -march=$(subst _xtheadc,,$(subst v0p7,,$(subst fd,,$(riscv-march-y))))
+KBUILD_AFLAGS += -march=$(riscv-march-y)
 
 KBUILD_CFLAGS += -mno-save-restore
 KBUILD_CFLAGS += -DCONFIG_PAGE_OFFSET=$(CONFIG_PAGE_OFFSET)
@@ -124,7 +124,7 @@ endif
 ifeq ($(CONFIG_RISCV_M_MODE)$(CONFIG_SOC_KENDRYTE),yy)
 KBUILD_IMAGE := $(boot)/loader.bin
 else
-KBUILD_IMAGE := $(boot)/Image.gz
+KBUILD_IMAGE := $(boot)/Image
 endif
 BOOT_TARGETS := Image Image.gz loader loader.bin
 

arch/riscv/boot/dts/Makefile

@@ -1,4 +1,9 @@
 # SPDX-License-Identifier: GPL-2.0
+
+ifeq ($(CONFIG_OF_OVERLAY),y)
+DTC_FLAGS += -@
+endif
+
 subdir-y += sifive
 subdir-y += kendryte
 subdir-y += thead

arch/riscv/boot/dts/thead/Makefile

@@ -1,35 +1,79 @@
 # SPDX-License-Identifier: GPL-2.0
-dtb-$(CONFIG_SOC_THEAD) += ice.dtb
-dtb-$(CONFIG_SOC_THEAD) += light-fm-emu.dtb light_mpw.dtb
-dtb-$(CONFIG_SOC_THEAD) += light-fm-emu-npu-fce.dtb
-dtb-$(CONFIG_SOC_THEAD) += light-fm-emu-gpu.dtb
-dtb-$(CONFIG_SOC_THEAD) += light-fm-emu-dsp.dtb
-dtb-$(CONFIG_SOC_THEAD) += light-fm-emu-audio.dtb
-dtb-$(CONFIG_SOC_THEAD) += light-fm-emu-hdmi.dtb
-dtb-$(CONFIG_SOC_THEAD) += light-fm-emu-dsi0-hdmi.dtb
-dtb-$(CONFIG_SOC_THEAD) += light-a-val.dtb light-a-val-sv.dtb
-dtb-$(CONFIG_SOC_THEAD) += light-a-val-ddr2G.dtb light-a-val-ddr1G.dtb
-dtb-$(CONFIG_SOC_THEAD) += light-a-val-npu-fce.dtb
-dtb-$(CONFIG_SOC_THEAD) += light-a-val-iso7816.dtb
-dtb-$(CONFIG_SOC_THEAD) += light-a-val-nand.dtb
-dtb-$(CONFIG_SOC_THEAD) += light-a-val-audio.dtb
-dtb-$(CONFIG_SOC_THEAD) += light-a-val-dsi0.dtb light-a-val-dsi1.dtb light-a-val-hdmi.dtb light-a-val-dsi0-dsi1.dtb light-a-val-dsi0-hdmi.dtb light-a-val-dpi0.dtb light-a-val-dpi0-dpi1.dtb
-dtb-$(CONFIG_SOC_THEAD) += light-a-val-wcn.dtb
-dtb-$(CONFIG_SOC_THEAD) += light-a-val-gpio-keys.dtb
-dtb-$(CONFIG_SOC_THEAD) += light-a-val-khv.dtb
-dtb-$(CONFIG_SOC_THEAD) += light-a-val-sec.dtb
-dtb-$(CONFIG_SOC_THEAD) += light-a-val-miniapp-hdmi.dtb
-dtb-$(CONFIG_SOC_THEAD) += light-a-product.dtb
-dtb-$(CONFIG_SOC_THEAD) += light-b-product.dtb
-dtb-$(CONFIG_SOC_THEAD) += light-b-product-ddr1G.dtb
-dtb-$(CONFIG_SOC_THEAD) += light-b-product-miniapp-hdmi.dtb
-dtb-$(CONFIG_SOC_THEAD) += light-a-val-full.dtb
-dtb-$(CONFIG_SOC_THEAD) += light-ant-ref.dtb
-dtb-$(CONFIG_SOC_THEAD) += light-ant-discrete.dtb
-dtb-$(CONFIG_SOC_THEAD) += light-beagle.dtb
-dtb-$(CONFIG_SOC_THEAD) += light-a-ref.dtb light-a-ref-dsi0.dtb light-a-ref-dsi0-hdmi.dtb
-dtb-$(CONFIG_SOC_THEAD) += light-b-ref.dtb
-dtb-$(CONFIG_SOC_THEAD) += light-a-val-crash.dtb light-b-product-crash.dtb light-ant-ref-crash.dtb light-ant-discrete-crash.dtb
-dtb-$(CONFIG_SOC_THEAD) += light-b-power.dtb
 
-dtb-$(CONFIG_SOC_THEAD) += light-a-val-android.dtb
+ifeq ($(CONFIG_OF_OVERLAY),y)
+DTC_FLAGS += -@
+endif
+
+dtb-$(CONFIG_SOC_THEAD_ICE) += ice.dtb
+dtb-$(CONFIG_SOC_THEAD_TH1520_MPW) += th1520_mpw.dtb
+dtb-$(CONFIG_SOC_THEAD_TH1520_EMU) += th1520-fm-emu.dtb
+dtb-$(CONFIG_SOC_THEAD_TH1520_EMU) += th1520-fm-emu-npu-fce.dtb
+dtb-$(CONFIG_SOC_THEAD_TH1520_EMU) += th1520-fm-emu-gpu.dtb
+dtb-$(CONFIG_SOC_THEAD_TH1520_EMU) += th1520-fm-emu-dsp.dtb
+dtb-$(CONFIG_SOC_THEAD_TH1520_EMU) += th1520-fm-emu-audio.dtb
+dtb-$(CONFIG_SOC_THEAD_TH1520_EMU) += th1520-fm-emu-hdmi.dtb
+dtb-$(CONFIG_SOC_THEAD_TH1520_EMU) += th1520-fm-emu-dsi0-hdmi.dtb
+dtb-$(CONFIG_SOC_THEAD) += th1520-a-val.dtb th1520-a-val-sec.dtb
+dtb-$(CONFIG_SOC_THEAD) += th1520-a-val-crash.dtb
+dtb-$(CONFIG_SOC_THEAD) += th1520-a-val-audio.dtb
+dtb-$(CONFIG_SOC_THEAD) += th1520-a-val-audio-i2s-8ch.dtb
+dtb-$(CONFIG_SOC_THEAD) += th1520-a-val-audio-tdm.dtb
+dtb-$(CONFIG_SOC_THEAD) += th1520-a-val-audio-spdif.dtb
+dtb-$(CONFIG_SOC_THEAD) += th1520-a-val-dsi0-hdmi.dtb
+dtb-$(CONFIG_SOC_THEAD) += th1520-a-val-dsi0-dsi1.dtb
+dtb-$(CONFIG_SOC_THEAD_TH1520_DEV) += th1520-a-val-sv.dtb
+dtb-$(CONFIG_SOC_THEAD_TH1520_DEV) += th1520-a-val-ddr2G.dtb th1520-a-val-ddr1G.dtb
+dtb-$(CONFIG_SOC_THEAD_TH1520_DEV) += th1520-a-val-npu-fce.dtb
+dtb-$(CONFIG_SOC_THEAD_TH1520_DEV) += th1520-a-val-iso7816.dtb
+dtb-$(CONFIG_SOC_THEAD_TH1520_DEV) += th1520-a-val-nand.dtb
+dtb-$(CONFIG_SOC_THEAD_TH1520_DEV) += th1520-a-val-dsi0.dtb th1520-a-val-dsi1.dtb th1520-a-val-hdmi.dtb th1520-a-val-dsi0-hdmi-audio.dtb th1520-a-val-dpi0.dtb th1520-a-val-dpi0-dpi1.dtb
+dtb-$(CONFIG_SOC_THEAD_TH1520_DEV) += th1520-a-val-wcn.dtb
+dtb-$(CONFIG_SOC_THEAD_TH1520_DEV) += th1520-a-val-gpio-keys.dtb
+dtb-$(CONFIG_SOC_THEAD_TH1520_DEV) += th1520-a-val-khv.dtb
+dtb-$(CONFIG_SOC_THEAD_TH1520_DEV) += th1520-a-val-miniapp-hdmi.dtb
+dtb-$(CONFIG_SOC_THEAD_TH1520_PRD) += th1520-a-product.dtb
+dtb-$(CONFIG_SOC_THEAD_TH1520_DEV) += th1520-a-val-full.dtb
+dtb-$(CONFIG_SOC_THEAD_TH1520_DEV) += th1520-a-ref.dtb th1520-a-ref-dsi0.dtb th1520-a-ref-dsi0-hdmi.dtb
+dtb-$(CONFIG_SOC_THEAD) += th1520-b-product.dtb th1520-b-product-sec.dtb
+dtb-$(CONFIG_SOC_THEAD) += th1520-b-product-crash.dtb
+dtb-$(CONFIG_SOC_THEAD_TH1520_DEV) += th1520-b-product-ddr1G.dtb
+dtb-$(CONFIG_SOC_THEAD_TH1520_DEV) += th1520-b-product-miniapp-hdmi.dtb
+dtb-$(CONFIG_SOC_THEAD_TH1520_DEV) += th1520-b-ref.dtb
+dtb-$(CONFIG_SOC_THEAD_TH1520_DEV) += th1520-b-power.dtb
+dtb-$(CONFIG_SOC_THEAD_TH1520_ANT) += th1520-ant-ref.dtb
+dtb-$(CONFIG_SOC_THEAD_TH1520_ANT) += th1520-ant-ref-crash.dtb th1520-ant-discrete-crash.dtb
+dtb-$(CONFIG_SOC_THEAD_TH1520_DEV) += th1520-ant-discrete.dtb
+dtb-$(CONFIG_SOC_THEAD_TH1520_DEV) += th1520-beagle.dtb
+dtb-$(CONFIG_SOC_THEAD) += th1520-lpi4a-product.dtb th1520-lpi4a-product-sec.dtb
+dtb-$(CONFIG_SOC_THEAD) += th1520-lpi4a-product-crash.dtb
+dtb-$(CONFIG_SOC_THEAD) += th1520-lpi4a-camera-tuning.dtb
+dtb-$(CONFIG_SOC_THEAD) += th1520-lpi4a-hx8279.dtb
+dtb-$(CONFIG_SOC_THEAD) += th1520-lpi4a-dsi0.dtb
+dtb-$(CONFIG_SOC_THEAD_TH1520_DEV) += th1520-lpi4a-ddr2G.dtb
+dtb-$(CONFIG_SOC_THEAD_TH1520_ANDROID) += th1520-a-val-android.dtb
+dtb-$(CONFIG_SOC_THEAD_FIRE) += fire-emu.dtb fire-emu-crash.dtb
+dtb-$(CONFIG_SOC_THEAD_FIRE) += fire-emu-soc-base.dtb fire-emu-soc-c910x4.dtb fire-emu-gpu-dpu-dsi0.dtb fire-emu-vi-dsp-vo.dtb fire-emu-vi-vp-vo.dtb
+dtb-$(CONFIG_SOC_THEAD_FIRE) += fire-emu-soc-base-sec.dtb
+
+dtb-$(CONFIG_SOC_THEAD) += th1520-beagle.dtb
+dtb-$(CONFIG_SOC_THEAD) += th1520-lpi4a-16gb.dtb
+dtb-$(CONFIG_SOC_THEAD) += th1520-lpi4a-laptop.dtb
+dtb-$(CONFIG_SOC_THEAD) += th1520-lpi4a-console.dtb th1520-lpi4a-console-16g.dtb
+dtb-$(CONFIG_SOC_THEAD) += th1520-lpi4a-cluster.dtb th1520-lpi4a-cluster-16gb.dtb
+dtb-$(CONFIG_SOC_THEAD) += th1520-lpi4a-z14inch-m0.dtb th1520-lpi4a-z14inch-m0-16g.dtb
+dtb-$(CONFIG_SOC_THEAD) += th1520-milkv-meles.dtb th1520-milkv-meles-4g.dtb th1520-milkv-meles-dsi0.dtb
+
+# compat old name
+dtb-$(CONFIG_SOC_THEAD) += light-lpi4a.dtb light-lpi4a-16gb.dtb
+dtb-$(CONFIG_SOC_THEAD) += light-lpi4a-console.dtb light-lpi4a-console-16g.dtb
+dtb-$(CONFIG_SOC_THEAD) += light-beagle.dtb
+
+# compat mainline name
+dtb-$(CONFIG_SOC_THEAD) += th1520-lichee-pi-4a.dtb th1520-lichee-pi-4a-16g.dtb
+dtb-$(CONFIG_SOC_THEAD) += th1520-lichee-cluster-4a.dtb th1520-lichee-cluster-4a-16g.dtb
+dtb-$(CONFIG_SOC_THEAD) += th1520-beaglev-ahead.dtb
+
+targets += dtbs dtbs_install
+targets += $(dtb-y)
+
+subdir-y	:= overlays

arch/riscv/boot/dts/thead/ice.dts

@@ -1,399 +0,0 @@
-/dts-v1/;
-/ {
-	model = "T-HEAD c910 ice";
-	compatible = "thead,c910_ice";
-	#address-cells = <2>;
-	#size-cells = <2>;
-
-	memory@0 {
-		device_type = "memory";
-		/*
-		 * Total memory size: 4GB (0x00000000 0x100000000)
-		 * 0x00200000 - 0x0e0000000: 3407MB for Linux system
-		 * 0xe0000000 - 0x100000000:  512MB for GPU
-		 */
-		reg = <0x0 0x200000 0x0 0xdfe00000>;
-	};
-
-	cpus {
-		#address-cells = <1>;
-		#size-cells = <0>;
-		timebase-frequency = <3000000>;
-		cpu@0 {
-			device_type = "cpu";
-			reg = <0>;
-			status = "okay";
-			compatible = "riscv";
-			riscv,isa = "rv64imafdcsu";
-			mmu-type = "riscv,sv39";
-			cpu-freq = "1.2Ghz";
-			cpu-icache = "64KB";
-			cpu-dcache = "64KB";
-			cpu-l2cache = "2MB";
-			cpu-tlb = "1024 4-ways";
-			cpu-cacheline = "64Bytes";
-			cpu-vector = "0.7.1";
-			cpu0_intc: interrupt-controller {
-				#interrupt-cells = <1>;
-				compatible = "riscv,cpu-intc";
-				interrupt-controller;
-			};
-		};
-		cpu@1 {
-			device_type = "cpu";
-			reg = <1>;
-			status = "okay";
-			compatible = "riscv";
-			riscv,isa = "rv64imafdcsu";
-			mmu-type = "riscv,sv39";
-			cpu-freq = "1.2Ghz";
-			cpu-icache = "64KB";
-			cpu-dcache = "64KB";
-			cpu-l2cache = "2MB";
-			cpu-tlb = "1024 4-ways";
-			cpu-cacheline = "64Bytes";
-			cpu-vector = "0.7.1";
-			cpu1_intc: interrupt-controller {
-				#interrupt-cells = <1>;
-				compatible = "riscv,cpu-intc";
-				interrupt-controller;
-			};
-		};
-	};
-
-	soc {
-		#address-cells = <2>;
-		#size-cells = <2>;
-		compatible = "simple-bus";
-		ranges;
-
-		reset: reset-sample {
-			compatible = "thead,reset-sample";
-			plic-delegate = <0x3 0xf01ffffc>;
-			using-csr-reset;
-			csr-copy = <
-				0x7c0 0x7c1 0x7c2 0x7c3 0x7c5 0x7cc
-				0x3b0 0x3b1 0x3b2 0x3b3
-				0x3b4 0x3b5 0x3b6 0x3b7
-				0x3a0
-				>;
-		};
-
-		clint0: clint@3f4000000 {
-			compatible = "riscv,clint0";
-			interrupts-extended = <
-				&cpu0_intc  3 &cpu0_intc  7
-				&cpu1_intc  3 &cpu1_intc  7
-				>;
-			reg = <0x3 0xf4000000 0x0 0x04000000>;
-			clint,has-no-64bit-mmio;
-		};
-
-		intc: interrupt-controller@3f0000000 {
-			#interrupt-cells = <1>;
-			compatible = "riscv,plic0";
-			interrupt-controller;
-			interrupts-extended = <
-				&cpu0_intc  0xffffffff &cpu0_intc  9
-				&cpu1_intc  0xffffffff &cpu1_intc  9
-				>;
-			reg = <0x3 0xf0000000 0x0 0x04000000>;
-			reg-names = "control";
-			riscv,max-priority = <7>;
-			riscv,ndev = <80>;
-		};
-
-		dummy_apb: apb-clock {
-			compatible = "fixed-clock";
-			clock-frequency = <62500000>;
-			clock-output-names = "dummy_apb";
-			#clock-cells = <0>;
-		};
-
-		dummy_ahb: ahb-clock {
-			compatible = "fixed-clock";
-			clock-frequency = <250000000>;
-			clock-output-names = "dummy_ahb";
-			#clock-cells = <0>;
-		};
-
-		dummy_axi: axi-clock {
-			compatible = "fixed-clock";
-			clock-frequency = <500000000>;
-			clock-output-names = "dummy_axi";
-			#clock-cells = <0>;
-		};
-
-		dummy_gmac: gmac-clock {
-			compatible = "fixed-clock";
-			clock-frequency = <1000000000>;
-			clock-output-names = "dummy_gmac";
-			#clock-cells = <0>;
-		};
-
-		dummy_clk_sdio: dummy-clk-sdio {
-			compatible = "fixed-clock";
-			clock-frequency = <150000000>;
-			clock-output-names = "dummy_clk_sdio";
-			#clock-cells = <0>;
-		};
-
-		usb: dwc3@3fff10000 {
-			compatible = "snps,dwc3";
-			reg = <0x3 0xfff10000 0x0 0x10000>;
-			interrupt-parent = <&intc>;
-			interrupts = <44>;
-			clocks = <&dummy_ahb>, <&dummy_ahb>, <&dummy_ahb>;
-			clock-names = "ref", "bus_early", "suspend";
-			maximum-speed = "super-speed";
-			dr_mode = "peripheral";
-			snps,usb3_lpm_capable;
-			snps,dis_u3_susphy_quirk;
-		};
-
-		gpio0: gpio@3fff71000 {
-			compatible = "snps,dw-apb-gpio";
-			reg = <0x3 0xfff71000 0x0 0x1000>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			/* GPIO0[0-31] */
-			gpio0_porta: gpio0-controller@0 {
-				compatible = "snps,dw-apb-gpio-port";
-				gpio-controller;
-				#gpio-cells = <2>;
-				snps,nr-gpios = <32>;
-				reg = <0>;
-
-				interrupt-controller;
-				#interrupt-cells = <2>;
-				interrupt-parent = <&intc>;
-				interrupts = <27>;
-			};
-
-			/* GPIO0[32-63] */
-			gpio0_portb: gpio0-controller@1 {
-				compatible = "snps,dw-apb-gpio-port";
-				gpio-controller;
-				#gpio-cells = <2>;
-				snps,nr-gpios = <32>;
-				reg = <1>;
-			};
-		};
-
-		gpio1: gpio@3fff72000 {
-			compatible = "snps,dw-apb-gpio";
-			reg = <0x3 0xfff72000 0x0 0x1000>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			/* GPIO1[0-31] */
-			gpio1_porta: gpio1-controller@0 {
-				compatible = "snps,dw-apb-gpio-port";
-				gpio-controller;
-				#gpio-cells = <2>;
-				snps,nr-gpios = <32>;
-				reg = <0>;
-			};
-
-			/* GPIO1[32-63] */
-			gpio1_portb: gpio1-controller@1 {
-				compatible = "snps,dw-apb-gpio-port";
-				gpio-controller;
-				#gpio-cells = <2>;
-				snps,nr-gpios = <32>;
-				reg = <1>;
-			};
-
-			/* GPIO1[64-95] */
-			gpio1_portc: gpio1-controller@2 {
-				compatible = "snps,dw-apb-gpio-port";
-				gpio-controller;
-				#gpio-cells = <2>;
-				snps,nr-gpios = <32>;
-				reg = <2>;
-			};
-		};
-
-		gpio-leds {
-			compatible = "gpio-leds";
-
-			led0 { /* GPIO0[11] - UART2_TXD */
-				label = "led0";
-				gpios = <&gpio0_porta 11 1>;
-				default-state = "off";
-			};
-		};
-
-		gpio-keys {
-			compatible = "gpio-keys";
-			/* autorepeat; */
-
-			key_0 { /* GPIO0[10] - UART2_RXD */
-				gpios = <&gpio0_porta 10 1>;
-				linux,code = <59>;
-				label = "key_0";
-			};
-		};
-
-		i2c@3fff74000 {
-			#address-cells = <1>;
-			#size-cells = <0>;
-			compatible = "snps,designware-i2c-ice";
-			reg = <0x3 0xfff74000 0x0 0x1000>;
-			interrupts = <21>;
-			interrupt-parent = <&intc>;
-			clocks = <&dummy_apb>;
-			clock-frequency = <400000>;
-
-			eeprom@50 {
-				compatible = "atmel,24c64";
-				reg = <0x50>;
-				pagesize = <32>;
-			};
-
-			goodix_ts@14 {
-				#gpio-cells = <2>;
-				compatible = "goodix,gt917s";
-				reg = <0x14>;
-				interrupt-parent = <&gpio0_porta>;
-				interrupts = <31 0>;
-				irq-gpios = <&gpio0_porta 31 0>;
-				reset-gpios = <&gpio0_porta 30 0>;
-				touchscreen-size-x = <720>;
-				touchscreen-size-y = <1280>;
-			};
-		};
-
-		serial@3fff73000 {
-			compatible = "snps,dw-apb-uart";
-			reg = <0x3 0xfff73000 0x0 0x400>;
-			interrupt-parent = <&intc>;
-			interrupts = <23>;
-			clocks = <&dummy_apb>;
-			clock-names = "baudclk";
-			reg-shift = <2>;
-			reg-io-width = <4>;
-		};
-
-		pmu: pmu {
-			interrupt-parent = <&cpu0_intc>;
-			interrupts = <17>;
-			compatible = "riscv,c910_pmu";
-		};
-
-		dmac0: dmac@3fffd0000 {
-			compatible = "snps,axi-dma-1.01a";
-			reg = <0x3 0xfffd0000 0x0 0x1000>;
-			interrupt-parent = <&intc>;
-			interrupts = <65>;
-			clocks = <&dummy_axi>, <&dummy_ahb>;
-			clock-names = "core-clk", "cfgr-clk";
-
-			dma-channels = <8>;
-			snps,block-size = <65536 65536 65536 65536 65536 65536 65536 65536>;
-			snps,priority = <0 1 2 3 4 5 6 7>;
-			snps,dma-masters = <1>;
-			snps,data-width = <4>;
-			snps,axi-max-burst-len = <16>;
-
-			status = "disabled";
-		};
-
-		sdhc0: sdhc0@3fffb0000 {
-			compatible = "snps,dw-mshc";
-			reg = <0x3 0xfffb0000 0x0 0x1000>;
-			interrupt-parent = <&intc>;
-			interrupts = <37>;
-			clocks = <&dummy_clk_sdio>, <&dummy_clk_sdio>;
-			clock-names = "ciu", "biu";
-			num-slots = <1>;
-			card-detect-delay = <200>;
-			cap-mmc-highspeed;
-			cap-cmd23;
-			non-removable;
-			bus-width = <8>;
-		};
-
-		sdhc1: sdhc1@3fffa0000 {
-			compatible = "snps,dw-mshc";
-			reg = <0x3 0xfffa0000 0x0 0x1000>;
-			interrupt-parent = <&intc>;
-			interrupts = <38>;
-			clocks = <&dummy_clk_sdio>, <&dummy_clk_sdio>;
-			clock-names = "ciu", "biu";
-			num-slots = <1>;
-			card-detect-delay = <200>;
-			cap-sd-highspeed;
-			bus-width = <4>;
-		};
-
-		stmmac_axi_setup: stmmac-axi-config {
-			snps,wr_osr_lmt = <3>;
-			snps,rd_osr_lmt = <3>;
-			snps,blen = <16 8 4 0 0 0 0>;
-		};
-
-		gmac: ethernet@3fffc0000 {
-			compatible = "thead,dwmac";
-			reg = < 0x3 0xfffc0000 0x0 0x2000
-				0x3 0xfe83025c 0x0 0x4
-				0x3 0xfe83031c 0x0 0x4
-				0x3 0xfff770c0 0x0 0x1c>;
-			reg-names = "gmac", "phy_if_reg", "txclk_dir_reg", "clk_mgr_reg";
-			interrupt-parent = <&intc>;
-			interrupts = <40>;
-			interrupt-names = "macirq";
-			clocks = <&dummy_ahb>, <&dummy_gmac>;
-			clock-names = "stmmaceth", "gmac_pll_clk";
-			snps,pbl = <32>;
-			snps,fixed-burst;
-			snps,axi-config = <&stmmac_axi_setup>;
-
-			phy-mode = "rgmii-id";
-			rx-clk-delay = <0x1f>; /* for RGMII */
-			tx-clk-delay = <0x1f>; /* for RGMII */
-
-			phy-handle = <&eth_phy_0>;
-			mdio0 {
-				#address-cells = <1>;
-				#size-cells = <0>;
-				compatible = "snps,dwmac-mdio";
-
-				eth_phy_0: ethernet-phy@0 {
-					reg = <0>;
-				};
-			};
-		};
-
-		gpu: gpu@3fff27000 {
-			compatible = "verisilicon,gc8000ul";
-			reg = <0x3 0xfff27000 0x0 0x1000>;
-			interrupt-parent = <&intc>;
-			interrupts = <63>;
-			contiguous-base = <0x0 0xe0000000>;
-			contiguous-size = <0x0 0x20000000>;
-		};
-
-		watchdog: watchdog@3fffe3000 {
-			compatible = "ice,ice-wdt";
-			reg = <0x3 0xfffe3000 0x0 0x1000>;
-			interrupts = <20>;
-		};
-
-		dpu: dpu@3fff28000 {
-			compatible = "verisilicon,dc8000-fb";
-			reg = <0x3 0xfff28000 0x0 0x8000>;
-			interrupt-parent = <&intc>;
-			interrupts = <64>;
-		};
-	};
-
-	chosen {
-		/* bootargs = "console=ttyS0,115200 crashkernel=256M-:128M c910_mmu_v1"; */
-		/* linux,initrd-start = <0x2000000>; */
-		/* linux,initrd-end = <0x17000000>; */
-		bootargs = "console=ttyS0,115200 rdinit=/sbin/init root=/dev/mmcblk0p4 rw rootfstype=ext4 blkdevparts=mmcblk0:2M(table),2M(dtb),60M(kernel),-(rootfs) clk_ignore_unused loglevel=7 rootwait crashkernel=256M-:128M c910_mmu_v1";
-		stdout-path = "serial0@3fff73000:115200";
-	};
-};

arch/riscv/boot/dts/thead/light-a-product-powergate.dts

@@ -1,8 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (C) 2021 Alibaba Group Holding Limited.
- */
-
-#include "light-a-product.dts"
-#include "light-powergate.dts"
-

arch/riscv/boot/dts/thead/light-a-ref.dts

@@ -1,5 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (C) 2021 Alibaba Group Holding Limited.
- */
-#include "light-a-val.dts"

arch/riscv/boot/dts/thead/light-a-val-android.dts

@@ -1,111 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (C) 2021 Alibaba Group Holding Limited.
- */
-
-/dts-v1/;
-
-#include "light-a-val-dsi0.dts"
-
-&dpu_enc1 {
-        ports {
-                /delete-node/ port@0;
-        };
-};
-
-&disp1_out {
-	remote-endpoint = <&hdmi_tx_in>;
-};
-&sdhci1 {
-	status = "okay";
-};
-
-&wcn_bt {
-	status = "okay";
-};
-
-&wcn_wifi {
-	status = "okay";
-};
-
-&lightsound {
-	status = "okay";
-	
-	simple-audio-card,widgets =
-		"Microphone", "Mic Jack",
-		"Speaker", "Speaker",
-		"Headphone", "Headphone Jack";
-	simple-audio-card,routing =
-		"Headphone Jack", "HP_L",
-		"Headphone Jack", "HP_R",
-		"Speaker", "SPK_LP",
-		"Speaker", "SPK_LN",
-		"Speaker", "SPK_RP",
-		"Speaker", "SPK_RN",
-		"Mic Jack","MICB",
-		"LINPUT1", "Mic Jack",
-		"LINPUT3", "Mic Jack";
-
-	simple-audio-card,dai-link@0 {          /* I2S - CODEC */
-		reg = <0>;
-		format = "i2s";
-		cpu {
-			sound-dai = <&light_i2s 0>;
-		};
-		codec {
-			sound-dai = <&codec>;
-		};
-	};
-	simple-audio-card,dai-link@1 {          /* I2S - HDMI */
-                reg = <1>;
-                format = "i2s";
-                cpu {
-                        sound-dai = <&light_i2s 1>;
-                };
-                codec {
-                        sound-dai = <&dummy_codec 2>;
-                };
-    };
-};
-
-&light_i2s {
-        status = "okay";
-};
-
-&hdmi_tx {
-	status = "okay";
-
-	port@0 {
-		/* input */
-		hdmi_tx_in: endpoint {
-			remote-endpoint = <&disp1_out>;
-		};
-	};
-};
-
-/ {
-       firmware {
-               android {
-                       compatible = "android,firmware";
-                       boot_devices = "soc/ffe7080000.sdhci";
-                       fstab {
-                               compatible = "android,fstab";
-                               system {
-                                       compatible = "android,system";
-                                       dev = "/dev/block/platform/soc/ffe7080000.sdhci/by-name/system";
-                                       type = "ext4";
-                                       mnt_flags = "ro,barrier=1";
-                                       fsmgr_flags = "wait";
-                               };
-                               vendor {
-                                       compatible = "android,vendor";
-                                       dev = "/dev/block/platform/soc/ffe7080000.sdhci/by-name/vendor";
-                                       type = "ext4";
-                                       mnt_flags = "ro,barrier=1";
-                                       fsmgr_flags = "wait";
-                               };
-                       };
-               };
-       };
-};
-

arch/riscv/boot/dts/thead/light-a-val-audio-powergate.dts

@@ -1,8 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (C) 2021 Alibaba Group Holding Limited.
- */
-
-#include "light-a-val-audio.dts"
-#include "light-powergate.dts"
-

arch/riscv/boot/dts/thead/light-a-val-ddr1G-powergate.dts

@@ -1,8 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (C) 2021 Alibaba Group Holding Limited.
- */
-
-#include "light-a-val-ddr1G.dts"
-#include "light-powergate.dts"
-

arch/riscv/boot/dts/thead/light-a-val-ddr1G.dts

@@ -1,21 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (C) 2022 Alibaba Group Holding Limited.
- */
-
-#include "light-a-val-ddr2G.dts"
-
-/ {
-	model = "T-HEAD Light VAL configuration for 1GB DDR board";
-	compatible = "thead,light-val", "thead,light-val-ddr1G", "thead,light";
-
-	memory@0 {
-		device_type = "memory";
-		reg = <0x0 0x00000000 0x0 0x40000000>;
-	};
-};
-
-&cmamem {
-	size = <0 0x8c00000>; // 140MB by default
-	alloc-ranges = <0 0x02000000 0 0x0cc00000>; // [0x0600_0000 ~ 0x0EC0_0000]
-};

arch/riscv/boot/dts/thead/light-a-val-ddr2G-powergate.dts

@@ -1,8 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (C) 2021 Alibaba Group Holding Limited.
- */
-
-#include "light-a-val-ddr2G.dts"
-#include "light-powergate.dts"
-

arch/riscv/boot/dts/thead/light-a-val-ddr2G.dts

@@ -1,25 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (C) 2022 Alibaba Group Holding Limited.
- */
-
-#include "light-a-val.dts"
-
-/ {
-	model = "T-HEAD Light VAL configuration for 2GB DDR board";
-	compatible = "thead,light-val", "thead,light-val-ddr2G", "thead,light";
-
-	memory@0 {
-		device_type = "memory";
-		reg = <0x0 0x00000000 0x0 0x80000000>;
-	};
-};
-
-&cmamem {
-	alloc-ranges = <0 0x64000000 0 0x14000000>; // [0x6400_0000 ~ 0x7800_0000]
-};
-
-&facelib_mem {
-	reg = <0x0 0x22000000 0 0x02000000>;
-	no-map;
-};

arch/riscv/boot/dts/thead/light-a-val-dpi0-dpi1-powergate.dts

@@ -1,8 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (C) 2021 Alibaba Group Holding Limited.
- */
-
-#include "light-a-val-dpi0-dpi1.dts"
-#include "light-powergate.dts"
-

arch/riscv/boot/dts/thead/light-a-val-dpi0-dpi1.dts

@@ -1,40 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (C) 2022 Alibaba Group Holding Limited.
- */
-
-/dts-v1/;
-
-#include "light-a-val-dpi0.dts"
-
-/ {
-	dpi_panel1: dpi-panel@1 {
-		compatible = "light,dummy-panel";
-
-		port {
-			dpi1_in: endpoint {
-				remote-endpoint = <&enc1_out>;
-			};
-		};
-	};
-};
-
-&dpu_enc1 {
-	compatible = "verisilicon,dpi-encoder";
-	status = "okay";
-
-	ports {
-		/* output */
-		port@1 {
-			reg = <1>;
-
-			enc1_out: endpoint {
-				remote-endpoint = <&dpi1_in>;
-			};
-		};
-	};
-};
-
-&dpu {
-	status = "okay";
-};

arch/riscv/boot/dts/thead/light-a-val-dpi0-powergate.dts

@@ -1,8 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (C) 2021 Alibaba Group Holding Limited.
- */
-
-#include "light-a-val-dpi0.dts"
-#include "light-powergate.dts"
-

arch/riscv/boot/dts/thead/light-a-val-dpi0.dts

@@ -1,44 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (C) 2022 Alibaba Group Holding Limited.
- */
-
-/dts-v1/;
-
-#include "light-a-val.dts"
-
-/ {
-	display-subsystem {
-		status = "okay";
-	};
-
-	dpi_panel0: dpi-panel@0 {
-		compatible = "light,dummy-panel";
-
-		port {
-			dpi0_in: endpoint {
-				remote-endpoint = <&enc0_out>;
-			};
-		};
-	};
-};
-
-&dpu_enc0 {
-	compatible = "verisilicon,dpi-encoder";
-	status = "okay";
-
-	ports {
-		/* output */
-		port@1 {
-			reg = <1>;
-
-			enc0_out: endpoint {
-				remote-endpoint = <&dpi0_in>;
-			};
-		};
-	};
-};
-
-&dpu {
-	status = "okay";
-};

arch/riscv/boot/dts/thead/light-a-val-dsi0-dsi1-powergate.dts

@@ -1,8 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (C) 2021 Alibaba Group Holding Limited.
- */
-
-#include "light-a-val-dsi0-dsi1.dts"
-#include "light-powergate.dts"
-

arch/riscv/boot/dts/thead/light-a-val-dsi0-hdmi-powergate.dts

@@ -1,8 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (C) 2021 Alibaba Group Holding Limited.
- */
-
-#include "light-a-val-dsi0-hdmi.dts"
-#include "light-powergate.dts"
-

arch/riscv/boot/dts/thead/light-a-val-dsi0-hdmi.dts

@@ -1,29 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (C) 2021 Alibaba Group Holding Limited.
- */
-
-/dts-v1/;
-
-#include "light-a-val-dsi0.dts"
-
-&dpu_enc1 {
-        ports {
-                /delete-node/ port@0;
-        };
-};
-
-&disp1_out {
-	remote-endpoint = <&hdmi_tx_in>;
-};
-
-&hdmi_tx {
-	status = "okay";
-
-	port@0 {
-		/* input */
-		hdmi_tx_in: endpoint {
-			remote-endpoint = <&disp1_out>;
-		};
-	};
-};

arch/riscv/boot/dts/thead/light-a-val-dsi0-powergate.dts

@@ -1,8 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (C) 2021 Alibaba Group Holding Limited.
- */
-
-#include "light-a-val-dsi0.dts"
-#include "light-powergate.dts"
-

arch/riscv/boot/dts/thead/light-a-val-dsi0.dts

@@ -1,75 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (C) 2021 Alibaba Group Holding Limited.
- */
-
-/dts-v1/;
-
-#include "light-a-val.dts"
-
-/ {
-	display-subsystem {
-		status = "okay";
-	};
-};
-
-&dpu_enc0 {
-	status = "okay";
-
-	ports {
-		/* output */
-		port@1 {
-			reg = <1>;
-
-			enc0_out: endpoint {
-				remote-endpoint = <&dsi0_in>;
-			};
-		};
-	};
-};
-
-&dpu {
-        status = "okay";
-};
-
-&dsi0 {
-        status = "okay";
-};
-
-&dhost_0 {
-	ports {
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		port@0 {
-			reg = <0>;
-
-			dsi0_in: endpoint {
-				remote-endpoint = <&enc0_out>;
-			};
-		};
-
-		port@1 {
-			reg = <1>;
-
-			dsi0_out: endpoint {
-				remote-endpoint = <&panel0_in>;
-			};
-		};
-	};
-
-	panel0@0 {
-		compatible = "txd,dy800qwxpab";
-		reg = <0>;
-		backlight = <&lcd0_backlight>;
-		reset-gpio = <&gpio1_porta 5 1>; /* active low */
-		vdd1v8-supply = <&lcd0_1v8>;
-		vspn5v7-supply = <&lcd0_5v7>;
-
-		port {
-			panel0_in: endpoint {
-				remote-endpoint = <&dsi0_out>;
-			};
-		};
-	};
-};

arch/riscv/boot/dts/thead/light-a-val-dsi1-powergate.dts

@@ -1,8 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (C) 2021 Alibaba Group Holding Limited.
- */
-
-#include "light-a-val-dsi1.dts"
-#include "light-powergate.dts"
-

arch/riscv/boot/dts/thead/light-a-val-dsi1.dts

@@ -1,75 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (C) 2021 Alibaba Group Holding Limited.
- */
-
-/dts-v1/;
-
-#include "light-a-val.dts"
-
-/ {
-	display-subsystem {
-		status = "okay";
-	};
-};
-
-&dpu_enc1 {
-	status = "okay";
-
-	ports {
-		/* output */
-		port@1 {
-			reg = <1>;
-
-			enc1_out: endpoint {
-				remote-endpoint = <&dsi1_in>;
-			};
-		};
-	};
-};
-
-&dpu {
-        status = "okay";
-};
-
-&dsi1 {
-        status = "okay";
-};
-
-&dhost_1 {
-	ports {
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		port@0 {
-			reg = <0>;
-
-			dsi1_in: endpoint {
-				remote-endpoint = <&enc1_out>;
-			};
-		};
-
-		port@1 {
-			reg = <1>;
-
-			dsi1_out: endpoint {
-				remote-endpoint = <&panel1_in>;
-			};
-		};
-	};
-
-	panel1@0 {
-		compatible = "txd,dy800qwxpab";
-		reg = <0>;
-		backlight = <&lcd1_backlight>;
-		reset-gpio = <&gpio1_porta 9 1>;		/* active low */
-		vdd1v8-supply = <&lcd1_1v8>;
-		vspn5v7-supply = <&lcd1_5v7>;
-
-		port {
-			panel1_in: endpoint {
-				remote-endpoint = <&dsi1_out>;
-			};
-		};
-	};
-};

arch/riscv/boot/dts/thead/light-a-val-dsp0-dsp1-powergate.dts

@@ -1,8 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (C) 2021 Alibaba Group Holding Limited.
- */
-
-#include "light-a-val-dsp0-dsp1.dts"
-#include "light-powergate.dts"
-

arch/riscv/boot/dts/thead/light-a-val-dsp0-dsp1.dts

@@ -1,13 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (C) 2021 Alibaba Group Holding Limited.
- */
-
-/dts-v1/;
-
-#include "light-a-val.dts"
-
-
-&xtensa_dsp1 {
-	status = "okay";
-};

arch/riscv/boot/dts/thead/light-a-val-full-powergate.dts

@@ -1,8 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (C) 2021 Alibaba Group Holding Limited.
- */
-
-#include "light-a-val-full.dts"
-#include "light-powergate.dts"
-

arch/riscv/boot/dts/thead/light-a-val-full.dts

@@ -1,161 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (C) 2022 Alibaba Group Holding Limited.
- */
-
-#include "light-a-val.dts"
-
-/ {
-	display-subsystem {
-		status = "okay";
-	};
-};
-
-&dpu_enc0 {
-	status = "okay";
-
-	ports {
-		/* output */
-		port@1 {
-			reg = <1>;
-
-			enc0_out: endpoint {
-				remote-endpoint = <&dsi0_in>;
-			};
-		};
-	};
-};
-
-&dpu_enc1 {
-        ports {
-                /delete-node/ port@0;
-        };
-};
-
-&dpu {
-        status = "okay";
-};
-
-&dsi0 {
-        status = "okay";
-};
-
-&dhost_0 {
-	ports {
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		port@0 {
-			reg = <0>;
-
-			dsi0_in: endpoint {
-				remote-endpoint = <&enc0_out>;
-			};
-		};
-
-		port@1 {
-			reg = <1>;
-
-			dsi0_out: endpoint {
-				remote-endpoint = <&panel0_in>;
-			};
-		};
-	};
-
-	panel0@0 {
-		compatible = "txd,dy800qwxpab";
-		reg = <0>;
-		backlight = <&lcd0_backlight>;
-		reset-gpio = <&gpio1_porta 5 1>; /* active low */
-		vdd1v8-supply = <&lcd0_1v8>;
-		vspn5v7-supply = <&lcd0_5v7>;
-
-		port {
-			panel0_in: endpoint {
-				remote-endpoint = <&dsi0_out>;
-			};
-		};
-	};
-};
-
-&disp1_out {
-	remote-endpoint = <&hdmi_tx_in>;
-};
-
-&hdmi_tx {
-	status = "okay";
-
-	port@0 {
-		/* input */
-		hdmi_tx_in: endpoint {
-			remote-endpoint = <&disp1_out>;
-		};
-	};
-};
-
-&lightsound {
-        status = "okay";
-
-        simple-audio-card,dai-link@0 {          /* I2S - AUDIO SYS CODEC 8156*/
-                reg = <0>;
-                format = "i2s";
-                cpu {
-                        sound-dai = <&i2s0 0>;
-                };
-                codec {
-                        sound-dai = <&es8156_audio_codec>;
-                };
-        };
-
-        simple-audio-card,dai-link@1 {          /* I2S - AUDIO SYS CODEC 7210*/
-                reg = <1>;
-                format = "i2s";
-                cpu {
-                        sound-dai = <&i2s3 0>;
-                };
-                codec {
-                        sound-dai = <&es7210_audio_codec>;
-                };
-        };
-};
-
-&light_i2s {
-        status = "okay";
-};
-
-&i2s0 {
-        status = "okay";
-};
-
-&i2s3 {
-        status = "okay";
-};
-
-&qspi0 {
-	status = "okay";
-};
-
-
-&qspi1 {
-	status = "okay";
-};
-
-&uart2 {
-	status = "okay";
-};
-
-&uart3 {
-	status = "okay";
-};
-
-&sdhci1 {
-	status = "okay";
-};
-
-&wcn_bt {
-	status = "okay";
-};
-
-&wcn_wifi {
-	status = "okay";
-};

arch/riscv/boot/dts/thead/light-a-val-gpio-keys.dts

@@ -1,15 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (C) 2021 Alibaba Group Holding Limited.
- */
-
-#include "light-a-val.dts"
-
-/ {
-	model = "T-HEAD Light FM GPIO-KEYS VAL board";
-	compatible = "thead,light-val-gpio-keys", "thead,light";
-};
-
-&gpio_keys {
-	status = "okay";
-};

arch/riscv/boot/dts/thead/light-a-val-hdmi-powergate.dts

@@ -1,8 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (C) 2021 Alibaba Group Holding Limited.
- */
-
-#include "light-a-val-hdmi.dts"
-#include "light-powergate.dts"
-

arch/riscv/boot/dts/thead/light-a-val-iso7816-powergate.dts

@@ -1,8 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (C) 2021 Alibaba Group Holding Limited.
- */
-
-#include "light-a-val-iso7816.dts"
-#include "light-powergate.dts"
-

arch/riscv/boot/dts/thead/light-a-val-iso7816.dts

@@ -1,10 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (C) 2021 Alibaba Group Holding Limited.
- */
-
-#include "light-a-val.dts"
-
-&iso7816 {
-	status = "okay";
-};

arch/riscv/boot/dts/thead/light-a-val-khv-powergate.dts

@@ -1,8 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (C) 2021 Alibaba Group Holding Limited.
- */
-
-#include "light-a-val-khv.dts"
-#include "light-powergate.dts"
-

arch/riscv/boot/dts/thead/light-a-val-khv.dts

@@ -1,21 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (C) 2021 Alibaba Group Holding Limited.
- */
-
-#include "light-a-val.dts"
-
-&resmem {
-        #address-cells = <2>;
-        #size-cells = <2>;
-        ranges;
-
-	/* 512M for guest memory */
-	guestmem: memory@50000000 {
-		reg = <0x0 0x50000000 0x0 0x20000000>;
-	};
-};
-
-&khvhost {
-	memory-region = <&guestmem>;
-};

arch/riscv/boot/dts/thead/light-a-val-miniapp-dsi0.dts

@@ -1,126 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (C) 2021 Alibaba Group Holding Limited.
- */
-
-/dts-v1/;
-
-#include "light-a-val.dts"
-
-/ {
-	display-subsystem {
-		status = "okay";
-	};
-};
-
-&dpu_enc0 {
-	status = "okay";
-
-	ports {
-		/* output */
-		port@1 {
-			reg = <1>;
-
-			enc0_out: endpoint {
-				remote-endpoint = <&dsi0_in>;
-			};
-		};
-	};
-};
-
-&dpu {
-        status = "okay";
-};
-
-&dsi0 {
-        status = "okay";
-};
-
-&dhost_0 {
-	ports {
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		port@0 {
-			reg = <0>;
-
-			dsi0_in: endpoint {
-				remote-endpoint = <&enc0_out>;
-			};
-		};
-
-		port@1 {
-			reg = <1>;
-
-			dsi0_out: endpoint {
-				remote-endpoint = <&panel0_in>;
-			};
-		};
-	};
-
-	panel0@0 {
-		compatible = "txd,dy800qwxpab";
-		reg = <0>;
-		backlight = <&lcd0_backlight>;
-		reset-gpio = <&gpio1_porta 5 1>; /* active low */
-		vdd1v8-supply = <&lcd0_1v8>;
-		vspn5v7-supply = <&lcd0_5v7>;
-
-		port {
-			panel0_in: endpoint {
-				remote-endpoint = <&dsi0_out>;
-			};
-		};
-	};
-};
-
-&lightsound {
-	status = "okay";
-
-        simple-audio-card,dai-link@0 {          /* I2S - AUDIO SYS CODEC 8156*/
-                reg = <0>;
-                format = "i2s";
-                cpu {
-                        sound-dai = <&i2s0 0>;
-                };
-                codec {
-                        sound-dai = <&es8156_audio_codec>;
-                };
-        };
-
-        simple-audio-card,dai-link@1 {          /* I2S - AUDIO SYS CODEC 7210*/
-                reg = <1>;
-                format = "i2s";
-                cpu {
-                        sound-dai = <&i2s3 0>;
-                };
-                codec {
-                        sound-dai = <&es7210_audio_codec>;
-                };
-        };
-};
-
-
-&light_i2s {
-	status = "okay";
-};
-
-&i2s0 {
-        status = "okay";
-};
-
-&i2s3 {
-        status = "okay";
-};
-
-&sdhci1 {
-	status = "okay";
-};
-
-&wcn_bt {
-	status = "okay";
-};
-
-&wcn_wifi {
-	status = "okay";
-};

arch/riscv/boot/dts/thead/light-a-val-miniapp-hdmi-powergate.dts

@@ -1,8 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (C) 2021 Alibaba Group Holding Limited.
- */
-
-#include "light-a-val-miniapp-hdmi.dts"
-#include "light-powergate.dts"
-

arch/riscv/boot/dts/thead/light-a-val-miniapp-hdmi.dts

@@ -1,90 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (C) 2021 Alibaba Group Holding Limited.
- */
-
-/dts-v1/;
-
-#include "light-a-val.dts"
-
-/ {
-	display-subsystem {
-		status = "okay";
-	};
-};
-
-&dpu_enc1 {
-	ports {
-		/delete-node/ port@0;
-	};
-};
-
-&disp1_out {
-	remote-endpoint = <&hdmi_tx_in>;
-};
-
-&dpu {
-	status = "okay";
-};
-
-&hdmi_tx {
-	status = "okay";
-
-	port@0 {
-		/* input */
-		hdmi_tx_in: endpoint {
-			remote-endpoint = <&disp1_out>;
-		};
-	};
-};
-
-&lightsound {
-	status = "okay";
-
-        simple-audio-card,dai-link@0 {          /* I2S - AUDIO SYS CODEC 8156*/
-                reg = <0>;
-                format = "i2s";
-                cpu {
-                        sound-dai = <&i2s0 0>;
-                };
-                codec {
-                        sound-dai = <&es8156_audio_codec>;
-                };
-        };
-
-        simple-audio-card,dai-link@1 {          /* I2S - AUDIO SYS CODEC 7210*/
-                reg = <1>;
-                format = "i2s";
-                cpu {
-                        sound-dai = <&i2s3 0>;
-                };
-                codec {
-                        sound-dai = <&es7210_audio_codec>;
-                };
-        };
-};
-
-
-&light_i2s {
-	status = "okay";
-};
-
-&i2s0 {
-        status = "okay";
-};
-
-&i2s3 {
-        status = "okay";
-};
-
-&sdhci1 {
-	status = "okay";
-};
-
-&wcn_bt {
-	status = "okay";
-};
-
-&wcn_wifi {
-	status = "okay";
-};

arch/riscv/boot/dts/thead/light-a-val-nand-powergate.dts

@@ -1,8 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (C) 2021 Alibaba Group Holding Limited.
- */
-
-#include "light-a-val-nand.dts"
-#include "light-powergate.dts"
-

arch/riscv/boot/dts/thead/light-a-val-nand.dts

@@ -1,14 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (C) 2021 Alibaba Group Holding Limited.
- */
-
-#include "light-a-val.dts"
-
-&qspi0 {
-	status = "okay";
-};
-
-&qspi1 {
-	status = "okay";
-};

arch/riscv/boot/dts/thead/light-a-val-npu-fce-powergate.dts

@@ -1,12 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (C) 2021 Alibaba Group Holding Limited.
- */
-
-#include "light-a-val-npu-fce.dts"
-#include "light-powergate.dts"
-
-&npu {
-	power-domains = <&pd LIGHT_AON_NPU_PD>;
-};
-

arch/riscv/boot/dts/thead/light-a-val-npu-fce.dts

@@ -1,28 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (C) 2021 Alibaba Group Holding Limited.
- */
-
-#include "light-a-val.dts"
-
-/ {
-	model = "T-HEAD Light FM NPU&FCE on VAL board";
-	compatible = "thead,light-val-npu-fce", "thead,light";
-
-};
-
-&facelib_mem {
-	reg = <0x0 0xd0000000 0 0x20000000>;
-	no-map;
-};
-
-&npu {
-	vha_clk_rate = <1000000000>;
-	status = "okay";
-};
-
-&fce {
-	memory-region = <&facelib_mem>;
-	status = "okay";
-};
-

arch/riscv/boot/dts/thead/light-a-val-powergate.dts

@@ -1,8 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (C) 2021 Alibaba Group Holding Limited.
- */
-
-#include "light-a-val.dts"
-#include "light-powergate.dts"
-

arch/riscv/boot/dts/thead/light-a-val-sec-powergate.dts

@@ -1,8 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (C) 2021 Alibaba Group Holding Limited.
- */
-
-#include "light-a-val-sec.dts"
-#include "light-powergate.dts"
-

arch/riscv/boot/dts/thead/light-a-val-sv-powergate.dts

@@ -1,8 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (C) 2021 Alibaba Group Holding Limited.
- */
-
-#include "light-a-val-sv.dts"
-#include "light-powergate.dts"
-

arch/riscv/boot/dts/thead/light-a-val-wcn-powergate.dts

@@ -1,8 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (C) 2021 Alibaba Group Holding Limited.
- */
-
-#include "light-a-val-wcn.dts"
-#include "light-powergate.dts"
-

arch/riscv/boot/dts/thead/light-a-val-wcn.dts

@@ -1,20 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (C) 2021 Alibaba Group Holding Limited.
- */
-
-/dts-v1/;
-
-#include "light-a-val.dts"
-
-&sdhci1 {
-	status = "okay";
-};
-
-&wcn_bt {
-	status = "okay";
-};
-
-&wcn_wifi {
-	status = "okay";
-};

arch/riscv/boot/dts/thead/light-ant-discrete-crash.dts

@@ -1,88 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (C) 2022 Alibaba Group Holding Limited.
- */
-
-#include "light-crash.dts"
-
-&aon {
-	aon_reg_dialog: light-dialog-reg {
-		compatible = "thead,light-dialog-pmic-ant";
-		status = "okay";
-
-		dvdd_cpu_reg: appcpu_dvdd {
-			regulator-name = "appcpu_dvdd";
-			regulator-min-microvolt = <300000>;
-			regulator-max-microvolt = <1570000>;
-			regulator-boot-on;
-			regulator-always-on;
-		};
-
-		dvddm_cpu_reg: appcpu_dvddm {
-			regulator-name = "appcpu_dvddm";
-			regulator-min-microvolt = <300000>;
-			regulator-max-microvolt = <1570000>;
-			regulator-boot-on;
-			regulator-always-on;
-		};
-	};
-};
-
-&cpus {
-	c910_0: cpu@0 {
-		operating-points = <
-			/* kHz    uV */
-			300000	720000
-			800000	720000
-			1500000	820000
-		>;
-		light,dvddm-operating-points = <
-			/* kHz   uV */
-			300000	770000
-			800000	820000
-			1500000	820000
-		>;
-	};
-	c910_1: cpu@1 {
-		operating-points = <
-			/* kHz    uV */
-			300000	720000
-			800000	720000
-			1500000	820000
-		>;
-		light,dvddm-operating-points = <
-			/* kHz   uV */
-			300000	770000
-			800000	820000
-			1500000	820000
-		>;
-	};
-	c910_2: cpu@2 {
-		operating-points = <
-			/* kHz    uV */
-			300000	720000
-			800000	720000
-			1500000	820000
-		>;
-		light,dvddm-operating-points = <
-			/* kHz   uV */
-			300000	770000
-			800000	820000
-			1500000	820000
-		>;
-	};
-	c910_3: cpu@3 {
-		operating-points = <
-			/* kHz    uV */
-			300000	720000
-			800000	720000
-			1500000	820000
-		>;
-		light,dvddm-operating-points = <
-			/* kHz   uV */
-			300000	770000
-			800000	820000
-			1500000	820000
-		>;
-	};
-};

arch/riscv/boot/dts/thead/light-b-power.dts

@@ -1,134 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (C) 2021 Alibaba Group Holding Limited.
- */
-
-/dts-v1/;
-
-#include "light-b-product.dts"
-
-&aon {
-	/delete-node/light-ricoh-reg;
-
-       	soc_vdd18_lcd0_bk_en_reg: soc_vdd18_lcd0_bk_en {
-		compatible = "regulator-fixed";
-		regulator-name = "soc_vdd18_lcd0_bk_en";
-		regulator-min-microvolt = <1800000>;
-		regulator-max-microvolt = <1800000>;
-		gpio = <&gpio1_porta 9 1>;
-		enable-active-high;
-	};
-
-	aon_reg_dialog: light-dialog-reg {
-		compatible = "thead,light-dialog-pmic-ant";
-		status = "okay";
-	
-		dvdd_cpu_reg: appcpu_dvdd {
-			regulator-name = "appcpu_dvdd";
-			regulator-min-microvolt = <300000>;
-			regulator-max-microvolt = <1570000>;
-			regulator-boot-on;
-			regulator-always-on;
-		};
-	
-		dvddm_cpu_reg: appcpu_dvddm {
-			regulator-name = "appcpu_dvddm";
-			regulator-min-microvolt = <300000>;
-			regulator-max-microvolt = <1570000>;
-			regulator-boot-on;
-			regulator-always-on;
-		};
-	
-		soc_dvdd18_aon_reg: soc_dvdd18_aon {
-			regulator-name = "soc_dvdd18_aon";
-			regulator-boot-on;
-			regulator-always-on;
-		};
-	
-		soc_avdd33_usb3_reg: soc_avdd33_usb3 {
-			regulator-name = "soc_avdd33_usb3";
-			regulator-boot-on;
-			regulator-always-on;
-		};
-	
-		soc_dvdd08_aon_reg: soc_dvdd08_aon {
-			regulator-name = "soc_dvdd08_aon";
-			regulator-boot-on;
-			regulator-always-on;
-		};
-	
-		soc_dvdd08_ddr_reg: soc_dvdd08_ddr {
-			regulator-name = "soc_dvdd08_ddr";
-			regulator-boot-on;
-			regulator-always-on;
-		};
-	
-		soc_vdd_ddr_1v8_reg: soc_vdd_ddr_1v8 {
-			regulator-name = "soc_vdd_ddr_1v8";
-			regulator-boot-on;
-			regulator-always-on;
-		};
-	
-		soc_vdd_ddr_1v1_reg: soc_vdd_ddr_1v1 {
-			regulator-name = "soc_vdd_ddr_1v1";
-			regulator-boot-on;
-			regulator-always-on;
-		};
-	
-		soc_vdd_ddr_0v6_reg: soc_vdd_ddr_0v6 {
-			regulator-name = "soc_vdd_ddr_0v6";
-			regulator-boot-on;
-			regulator-always-on;
-		};
-	
-		soc_dvdd18_ap_reg: soc_dvdd18_ap {
-			regulator-name = "soc_dvdd18_ap";
-			regulator-boot-on;
-			regulator-always-on;
-		};
-	
-		soc_avdd08_mipi_hdmi_reg: soc_avdd08_mipi_hdmi {
-			regulator-name = "soc_avdd08_mipi_hdmi";
-			regulator-boot-on;
-			regulator-always-on;
-		};
-	
-		soc_avdd18_mipi_hdmi_reg: soc_avdd18_mipi_hdmi {
-			regulator-name = "soc_avdd18_mipi_hdmi";
-			regulator-boot-on;
-			regulator-always-on;
-		};
-	
-		soc_vdd33_emmc_reg: soc_vdd33_emmc {
-			regulator-name = "soc_vdd33_emmc";
-			regulator-boot-on;
-			regulator-always-on;
-		};
-	
-		soc_vdd18_emmc_reg: soc_vdd18_emmc {
-			regulator-name = "soc_vdd18_emmc";
-			regulator-boot-on;
-			regulator-always-on;
-		};
-#if 0	
-		soc_dovdd18_scan_reg: soc_dovdd18_scan {
-			regulator-name = "soc_dovdd18_scan";
-		};
-	
-		soc_dvdd12_scan_reg: soc_dvdd12_scan {
-			regulator-name = "soc_dvdd12_scan";
-		};
-	
-		soc_avdd28_scan_en_reg: soc_avdd28_scan_en {
-			regulator-name = "soc_avdd28_scan_en";
-		};
-#endif
-	
-	};
-};
-
-
-&panel0 {
-
-	vdd1v8-supply = <&soc_vdd18_lcd0_bk_en_reg>;
-};

arch/riscv/boot/dts/thead/light-b-product-ddr1G-powergate.dts

@@ -1,14 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (C) 2021 Alibaba Group Holding Limited.
- */
-
-#include "light-b-product-ddr1G.dts"
-#include "light-powergate.dts"
-
-&soc_vdd18_lcd0_en_reg {
-	/delete-property/regulator-always-on;
-};
-&soc_lcd0_bias_en_reg {
-	/delete-property/regulator-always-on;
-};

arch/riscv/boot/dts/thead/light-b-product-ddr1G.dts

@@ -1,21 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (C) 2022 Alibaba Group Holding Limited.
- */
-
-#include "light-b-product.dts"
-
-/ {
-	model = "T-HEAD Light-B VAL configuration for 1GB DDR board";
-	compatible = "thead,light-val", "thead,light-val-ddr1G", "thead,light";
-
-	memory@0 {
-		device_type = "memory";
-		reg = <0x0 0x00000000 0x0 0x40000000>;
-	};
-};
-
-&cmamem {
-	size = <0 0x8c00000>; // 140MB by default
-	alloc-ranges = <0 0x02000000 0 0x0cc000000>; // [0x0600_0000 ~ 0x0EC0_0000]
-};

arch/riscv/boot/dts/thead/light-b-product-miniapp-hdmi.dts

@@ -1,28 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (C) 2021 Alibaba Group Holding Limited.
- */
-
-/dts-v1/;
-
-#include "light-b-product.dts"
-
-&dpu_enc0 {
-        status = "disabled";
-};
-
-&dsi0 {
-        status = "disabled";
-};
-
-&dhost_0 {
-        status = "disabled";
-};
-
-&wcn_bt {
-        status = "okay";
-};
-
-&wcn_wifi {
-        status = "okay";
-};

arch/riscv/boot/dts/thead/light-b-product-powergate.dts

@@ -1,16 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (C) 2021 Alibaba Group Holding Limited.
- */
-
-#include "light-b-product.dts"
-#include "light-powergate.dts"
-
-
-&soc_vdd18_lcd0_en_reg {
-	/delete-property/regulator-always-on;
-};
-
-&soc_lcd0_bias_en_reg {
-	/delete-property/regulator-always-on;
-};

arch/riscv/boot/dts/thead/light-b-product-sec-powergate.dts

@@ -1,8 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (C) 2021 Alibaba Group Holding Limited.
- */
-
-#include "light-b-product-sec.dts"
-#include "light-powergate.dts"
-

arch/riscv/boot/dts/thead/light-b-ref.dts

@@ -1,134 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (C) 2021 Alibaba Group Holding Limited.
- */
-
-/dts-v1/;
-
-#include "light-b-product.dts"
-
-&aon {
-	/delete-node/light-ricoh-reg;
-
-       	soc_vdd18_lcd0_bk_en_reg: soc_vdd18_lcd0_bk_en {
-		compatible = "regulator-fixed";
-		regulator-name = "soc_vdd18_lcd0_bk_en";
-		regulator-min-microvolt = <1800000>;
-		regulator-max-microvolt = <1800000>;
-		gpio = <&gpio1_porta 9 1>;
-		enable-active-high;
-	};
-
-	aon_reg_dialog: light-dialog-reg {
-		compatible = "thead,light-dialog-pmic-ant";
-		status = "okay";
-	
-		dvdd_cpu_reg: appcpu_dvdd {
-			regulator-name = "appcpu_dvdd";
-			regulator-min-microvolt = <300000>;
-			regulator-max-microvolt = <1570000>;
-			regulator-boot-on;
-			regulator-always-on;
-		};
-	
-		dvddm_cpu_reg: appcpu_dvddm {
-			regulator-name = "appcpu_dvddm";
-			regulator-min-microvolt = <300000>;
-			regulator-max-microvolt = <1570000>;
-			regulator-boot-on;
-			regulator-always-on;
-		};
-	
-		soc_dvdd18_aon_reg: soc_dvdd18_aon {
-			regulator-name = "soc_dvdd18_aon";
-			regulator-boot-on;
-			regulator-always-on;
-		};
-	
-		soc_avdd33_usb3_reg: soc_avdd33_usb3 {
-			regulator-name = "soc_avdd33_usb3";
-			regulator-boot-on;
-			regulator-always-on;
-		};
-	
-		soc_dvdd08_aon_reg: soc_dvdd08_aon {
-			regulator-name = "soc_dvdd08_aon";
-			regulator-boot-on;
-			regulator-always-on;
-		};
-	
-		soc_dvdd08_ddr_reg: soc_dvdd08_ddr {
-			regulator-name = "soc_dvdd08_ddr";
-			regulator-boot-on;
-			regulator-always-on;
-		};
-	
-		soc_vdd_ddr_1v8_reg: soc_vdd_ddr_1v8 {
-			regulator-name = "soc_vdd_ddr_1v8";
-			regulator-boot-on;
-			regulator-always-on;
-		};
-	
-		soc_vdd_ddr_1v1_reg: soc_vdd_ddr_1v1 {
-			regulator-name = "soc_vdd_ddr_1v1";
-			regulator-boot-on;
-			regulator-always-on;
-		};
-	
-		soc_vdd_ddr_0v6_reg: soc_vdd_ddr_0v6 {
-			regulator-name = "soc_vdd_ddr_0v6";
-			regulator-boot-on;
-			regulator-always-on;
-		};
-	
-		soc_dvdd18_ap_reg: soc_dvdd18_ap {
-			regulator-name = "soc_dvdd18_ap";
-			regulator-boot-on;
-			regulator-always-on;
-		};
-	
-		soc_avdd08_mipi_hdmi_reg: soc_avdd08_mipi_hdmi {
-			regulator-name = "soc_avdd08_mipi_hdmi";
-			regulator-boot-on;
-			regulator-always-on;
-		};
-	
-		soc_avdd18_mipi_hdmi_reg: soc_avdd18_mipi_hdmi {
-			regulator-name = "soc_avdd18_mipi_hdmi";
-			regulator-boot-on;
-			regulator-always-on;
-		};
-	
-		soc_vdd33_emmc_reg: soc_vdd33_emmc {
-			regulator-name = "soc_vdd33_emmc";
-			regulator-boot-on;
-			regulator-always-on;
-		};
-	
-		soc_vdd18_emmc_reg: soc_vdd18_emmc {
-			regulator-name = "soc_vdd18_emmc";
-			regulator-boot-on;
-			regulator-always-on;
-		};
-#if 0	
-		soc_dovdd18_scan_reg: soc_dovdd18_scan {
-			regulator-name = "soc_dovdd18_scan";
-		};
-	
-		soc_dvdd12_scan_reg: soc_dvdd12_scan {
-			regulator-name = "soc_dvdd12_scan";
-		};
-	
-		soc_avdd28_scan_en_reg: soc_avdd28_scan_en {
-			regulator-name = "soc_avdd28_scan_en";
-		};
-#endif
-	
-	};
-};
-
-
-&panel0 {
-
-	vdd1v8-supply = <&soc_vdd18_lcd0_bk_en_reg>;
-};

arch/riscv/boot/dts/thead/light-beagle.dts

@@ -1,608 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0 */
 /*
- * Copyright (C) 2021 Alibaba Group Holding Limited.
+ * Copyright (C) 2024 ISCAS.
  */
 
-/dts-v1/;
-
-#include "light-ant-ref.dts"
-
-&vvcam_sensor4 { // beagle board J5 CSI0 connector
-	sensor_name = "IMX219";
-	sensor_pdn = <&gpio2_porta 23 0>; //powerdown pin / shutdown pin 
-	sensor_pdn_delay_us = <2000>; //powerdown pin / shutdown pin actived till I2C ready
-	i2c_addr = /bits/ 8 <0x10>;
-	i2c_bus = /bits/ 8 <1>;
-	i2c_reg_width = /bits/ 8 <2>;
-	i2c_data_width = /bits/ 8 <1>;
-	status = "okay";
-};
-
-&vvcam_sensor5 { // beagle board J4 CSI1 connector
-	sensor_name = "IMX219";
-	sensor_pdn = <&gpio2_porta 24 0>; //powerdown pin / shutdown pin 
-	sensor_pdn_delay_us = <2000>; //powerdown pin / shutdown pin actived till I2C ready
-	i2c_addr = /bits/ 8 <0x10>;
-	i2c_bus = /bits/ 8 <3>;
-	i2c_reg_width = /bits/ 8 <2>;
-	i2c_data_width = /bits/ 8 <1>;
-	status = "okay";
-};
-
-/*
-sensor imx219 mounted on beagle board J4
-video0: sensor-vipre-isp0
-video1: sensor-vipre-isp0-dw
-video7: sensor-vipre-isp0-dsp1-ry-dw
-video10: tuningtool
-
-sensor imx219 mounted on beagle board J5
-video2: sensor-vipre-isp1   
-video3: sensor-vipre-isp1-dw   
-video4: sensor-vipre-isp1-dsp0-ry
-video5: sensor-vipre-isp1-dsp0-ry-dw
-video12: tuningtool
-*/
-
-&video2 {
-    vi_mem_pool_region = <0>;	// vi_mem: framebuffer, region[0]
-	status = "okay";
-	pipline0 {
-		pipline_id = <0>;
-		status = "okay";
-		sensor0 {
-			subdev_name = "vivcam";
-			idx = <4>; // imx219
-			csi_idx = <0>; //<0>=CSI2
-			mode_idx = <0>;
-			path_type = "SENSOR_1080P_RAW10_LINER";
-		};
-		sensor1 {
-			subdev_name = "vivcam";
-			idx = <0xff>; // invalid
-			csi_idx = <0xff>;
-			path_type = "SENSOR_VGA_RAW10_LINER";
-		};
-		dma {
-			subdev_name = "vipre";
-			idx = <0>;
-			path_type = "VIPRE_CSI0_ISP1";
-		};
-		isp {
-			subdev_name = "isp";
-			idx = <1>;
-			path_type = "ISP_MI_PATH_MP";
-			output {
-				max_width = <1920>;
-				max_height = <1088>;
-				bit_per_pixel = <16>;
-				frame_count = <3>;
-			};
-		};
-	};
-	pipline1 {
-		pipline_id = <1>;
-		status = "okay";
-		sensor0 {
-			subdev_name = "vivcam";
-			idx = <4>; // imx219
-			csi_idx = <0>; //<0>=CSI2
-			mode_idx = <0>;
-			path_type = "SENSOR_1080P_RAW10_LINER";
-		};
-		sensor1 {
-			subdev_name = "vivcam";
-			idx = <0xff>; // invalid
-			csi_idx = <0xff>;
-			path_type = "SENSOR_VGA_RAW10_LINER";
-		};
-		dma {
-			subdev_name = "vipre";
-			idx = <0>;
-			path_type = "VIPRE_CSI0_ISP1";
-		};
-		isp {
-			subdev_name = "isp";
-			idx = <1>;
-			path_type = "ISP_MI_PATH_SP";
-			output {
-				max_width = <1920>;
-				max_height = <1088>;
-				bit_per_pixel = <16>;
-				frame_count = <3>;
-			};
-		};
-	};
-	pipline2 {
-		pipline_id = <2>;
-		status = "okay";
-		sensor0 {
-			subdev_name = "vivcam";
-			idx = <4>; // imx219
-			csi_idx = <0>; //<0>=CSI2
-			mode_idx = <0>;
-			path_type = "SENSOR_1080P_RAW10_LINER";
-		};
-		sensor1 {
-			subdev_name = "vivcam";
-			idx = <0xff>; // invalid
-			csi_idx = <0xff>;
-			path_type = "SENSOR_VGA_RAW10_LINER";
-		};
-		dma {
-			subdev_name = "vipre";
-			idx = <0>;
-			path_type = "VIPRE_CSI0_ISP1";
-		};
-		isp {
-			subdev_name = "isp";
-			idx = <1>;
-			path_type = "ISP_MI_PATH_SP2_BP";
-			output {
-				max_width = <1920>;
-				max_height = <1088>;
-				bit_per_pixel = <16>;
-				frame_count = <3>;
-			};
-		};
-	};
-};
-
-&video3{
-    vi_mem_pool_region = <0>;	// vi_mem: framebuffer, region[0]
-	pipline0 {
-		sensor0 {
-			subdev_name = "vivcam";
-			idx = <4>; // imx219
-			csi_idx = <0>; //<0>=CSI2
-			mode_idx = <0>;
-			path_type = "SENSOR_1080P_RAW10_LINER";
-		};
-		sensor1 {
-			subdev_name = "vivcam";
-			idx = <0xff>; // invalid
-			csi_idx = <0xff>;
-			path_type = "SENSOR_VGA_RAW10_LINER";
-		};
-		dma {
-			subdev_name = "vipre";
-			idx = <0>;
-			path_type = "VIPRE_CSI0_ISP1";
-		};
-		isp {
-			subdev_name = "isp";
-			idx = <1>;
-			path_type = "ISP_MI_PATH_MP";
-			output {
-				max_width = <1920>;
-				max_height = <1088>;
-				bit_per_pixel = <12>;
-				frame_count = <3>;
-			};
-		};
-		dw {
-			subdev_name = "dw";
-			idx = <0>;
-			path_type = "DW_DWE_VSE0";
-			dw_dst_depth = <2>;
-		};
-	};
-	pipline1 {
-		sensor0 {
-			subdev_name = "vivcam";
-			idx = <4>; // imx219
-			csi_idx = <0>; //<0>=CSI2
-			mode_idx = <0>;
-			path_type = "SENSOR_1080P_RAW10_LINER";
-		};
-		sensor1 {
-			subdev_name = "vivcam";
-			idx = <0xff>; // invalid
-			csi_idx = <0xff>;
-			path_type = "SENSOR_VGA_RAW10_LINER";
-		};
-		dma {
-			subdev_name = "vipre";
-			idx = <0>;
-			path_type = "VIPRE_CSI0_ISP1";
-		};
-		isp {
-			subdev_name = "isp";
-			idx = <1>;
-			path_type = "ISP_MI_PATH_MP";
-			output {
-				max_width = <1920>;
-				max_height = <1088>;
-				bit_per_pixel = <12>;
-				frame_count = <3>;
-			};
-		};
-		dw {
-			subdev_name = "dw";
-			idx = <0>;
-			path_type = "DW_DWE_VSE1";
-			dw_dst_depth = <2>;
-		};
-	};
-	pipline2 {
-		sensor0 {
-			subdev_name = "vivcam";
-			idx = <4>; // imx219
-			csi_idx = <0>; //<0>=CSI2
-			mode_idx = <0>;
-			path_type = "SENSOR_1080P_RAW10_LINER";
-		};
-		sensor1 {
-			subdev_name = "vivcam";
-			idx = <0xff>; // invalid
-			csi_idx = <0xff>;
-			path_type = "SENSOR_VGA_RAW10_LINER";
-		};
-		dma {
-			subdev_name = "vipre";
-			idx = <0>;
-			path_type = "VIPRE_CSI0_ISP1";
-		};
-		isp {
-			subdev_name = "isp";
-			idx = <1>;
-			path_type = "ISP_MI_PATH_MP";
-			output {
-				max_width = <1920>;
-				max_height = <1088>;
-				bit_per_pixel = <12>;
-				frame_count = <3>;
-			};
-		};
-		dw {
-			subdev_name = "dw";
-			idx = <0>;
-			path_type = "DW_DWE_VSE2";
-			dw_dst_depth = <2>;
-		};
-	};
-};
-
-&video4{
-    vi_mem_pool_region = <0>;	// vi_mem: framebuffer, region[0]
-	pipline0 {
-		sensor0 {
-			subdev_name = "vivcam";
-			idx = <4>; // imx219
-			csi_idx = <0>; //<0>=CSI2
-			mode_idx = <0>;
-			path_type = "SENSOR_1080P_RAW10_LINER";
-		};
-		sensor1 {
-			subdev_name = "vivcam";
-			idx = <0xff>; // invalid
-			csi_idx = <0xff>;
-			path_type = "SENSOR_VGA_RAW10_LINER";
-		};
-		dma {
-			subdev_name = "vipre";
-			idx = <0>;
-			path_type = "VIPRE_CSI0_ISP1";
-		};
-		isp {
-			subdev_name = "isp";
-			idx = <1>;
-			path_type = "ISP_MI_PATH_PP";
-			output {
-				max_width = <1920>;
-				max_height = <1088>;
-				bit_per_pixel = <12>;
-				frame_count = <3>;
-			};
-		};
-		dsp {
-			subdev_name = "dsp";
-			idx = <0>;
-			path_type = "DSP_PATH_ISP_RY";
-			output {
-				max_width = <1920>;
-				max_height = <1088>;
-				bit_per_pixel = <12>;
-				frame_count = <3>;
-			};
-		};
-		ry {
-			subdev_name = "ry";
-			idx = <0>;
-			path_type = "ISP_RY_MI_PATH_MP";
-			output {
-				max_width = <1920>;
-				max_height = <1088>;
-				bit_per_pixel = <12>;
-				frame_count = <3>;
-			};
-		};
-	};
-	pipline1 {
-		sensor0 {
-			subdev_name = "vivcam";
-			idx = <4>; // imx219
-			csi_idx = <0>; //<0>=CSI2
-			mode_idx = <0>;
-			path_type = "SENSOR_1080P_RAW10_LINER";
-		};
-		sensor1 {
-			subdev_name = "vivcam";
-			idx = <0xff>; // invalid
-			csi_idx = <0xff>;
-			path_type = "SENSOR_VGA_RAW10_LINER";
-		};
-		dma {
-			subdev_name = "vipre";
-			idx = <0>;
-			path_type = "VIPRE_CSI0_ISP1";
-		};
-		isp {
-			subdev_name = "isp";
-			idx = <1>;
-			path_type = "ISP_MI_PATH_PP";
-			output {
-				max_width = <1920>;
-				max_height = <1088>;
-				bit_per_pixel = <12>;
-				frame_count = <3>;
-			};
-		};
-		dsp {
-			subdev_name = "dsp";
-			idx = <0>;
-			path_type = "DSP_PATH_ISP_RY";
-			output {
-				max_width = <1920>;
-				max_height = <1088>;
-				bit_per_pixel = <12>;
-				frame_count = <3>;
-			};
-		};
-		ry {
-			subdev_name = "ry";
-			idx = <0>;
-			path_type = "ISP_RY_MI_PATH_SP";
-			output {
-				max_width = <1920>;
-				max_height = <1088>;
-				bit_per_pixel = <12>;
-				frame_count = <3>;
-			};
-		};
-	};
-	pipline2 {
-		sensor0 {
-			subdev_name = "vivcam";
-			idx = <4>; // imx219
-			csi_idx = <0>; //<0>=CSI2
-			mode_idx = <0>;
-			path_type = "SENSOR_1080P_RAW10_LINER";
-		};
-		sensor1 {
-			subdev_name = "vivcam";
-			idx = <0xff>; // invalid
-			csi_idx = <0xff>;
-			path_type = "SENSOR_VGA_RAW10_LINER";
-		};
-		dma {
-			subdev_name = "vipre";
-			idx = <0>;
-			path_type = "VIPRE_CSI0_ISP1";
-		};
-		isp {
-			subdev_name = "isp";
-			idx = <1>;
-			path_type = "ISP_MI_PATH_PP";
-			output {
-				max_width = <1920>;
-				max_height = <1088>;
-				bit_per_pixel = <12>;
-				frame_count = <3>;
-			};
-		};
-		dsp {
-			subdev_name = "dsp";
-			idx = <0>;
-			path_type = "DSP_PATH_ISP_RY";
-			output {
-				max_width = <1920>;
-				max_height = <1088>;
-				bit_per_pixel = <12>;
-				frame_count = <3>;
-			};
-		};
-		ry {
-			subdev_name = "ry";
-			idx = <0>;
-			path_type = "ISP_RY_MI_PATH_SP2_BP";
-			output {
-				max_width = <1920>;
-				max_height = <1088>;
-				bit_per_pixel = <12>;
-				frame_count = <3>;
-			};
-		};
-	};
-};
-
-&video5{
-	vi_mem_pool_region = <0>;	// vi_mem: framebuffer, region[0]
-	pipline0 {
-		sensor0 {
-			subdev_name = "vivcam";
-			idx = <4>; // imx219
-			csi_idx = <0>; //<0>=CSI2
-			mode_idx = <0>;
-			path_type = "SENSOR_1080P_RAW10_LINER";
-		};
-		sensor1 {
-			subdev_name = "vivcam";
-			idx = <0xff>; // invalid
-			csi_idx = <0xff>;
-			path_type = "SENSOR_VGA_RAW10_LINER";
-		};
-		dma {
-			subdev_name = "vipre";
-			idx = <0>;
-			path_type = "VIPRE_CSI0_ISP1";
-		};
-		isp {
-			subdev_name = "isp";
-			idx = <1>;
-			path_type = "ISP_MI_PATH_PP";
-			output {
-				max_width = <1920>;
-				max_height = <1088>;
-				bit_per_pixel = <12>;
-				frame_count = <3>;
-			};
-		};
-		dsp {
-			subdev_name = "dsp";
-			idx = <0>;
-			path_type = "DSP_PATH_ISP_RY";
-			output {
-				max_width = <1920>;
-				max_height = <1088>;
-				bit_per_pixel = <12>;
-				frame_count = <3>;
-			};
-		};
-		ry {
-			subdev_name = "ry";
-			idx = <0>;
-			path_type = "ISP_RY_MI_PATH_MP";
-			output {
-				max_width = <1920>;
-				max_height = <1088>;
-				bit_per_pixel = <12>;
-				frame_count = <3>;
-			};
-		};
-		dw {
-			subdev_name = "dw";
-			idx = <0>;
-			path_type = "DW_DWE_VSE0";
-			dw_dst_depth = <2>;
-		};
-	};
-	pipline1 {
-		sensor0 {
-			subdev_name = "vivcam";
-			idx = <4>; // imx219
-			csi_idx = <0>; //<0>=CSI2
-			mode_idx = <0>;
-			path_type = "SENSOR_1080P_RAW10_LINER";
-		};
-		sensor1 {
-			subdev_name = "vivcam";
-			idx = <0xff>; // invalid
-			csi_idx = <0xff>;
-			path_type = "SENSOR_VGA_RAW10_LINER";
-		};
-		dma {
-			subdev_name = "vipre";
-			idx = <0>;
-			path_type = "VIPRE_CSI0_ISP1";
-		};
-		isp {
-			subdev_name = "isp";
-			idx = <1>;
-			path_type = "ISP_MI_PATH_PP";
-			output {
-				max_width = <1920>;
-				max_height = <1088>;
-				bit_per_pixel = <12>;
-				frame_count = <3>;
-			};
-		};
-		dsp {
-			subdev_name = "dsp";
-			idx = <0>;
-			path_type = "DSP_PATH_ISP_RY";
-			output {
-				max_width = <1920>;
-				max_height = <1088>;
-				bit_per_pixel = <12>;
-				frame_count = <3>;
-			};
-		};
-		ry {
-			subdev_name = "ry";
-			idx = <0>;
-			path_type = "ISP_RY_MI_PATH_MP";
-			output {
-				max_width = <1920>;
-				max_height = <1088>;
-				bit_per_pixel = <12>;
-				frame_count = <3>;
-			};
-		};
-		dw {
-			subdev_name = "dw";
-			idx = <0>;
-			path_type = "DW_DWE_VSE1";
-			dw_dst_depth = <2>;
-		};
-	};
-	pipline2 {
-		sensor0 {
-			subdev_name = "vivcam";
-			idx = <4>; // imx219
-			csi_idx = <0>; //<0>=CSI2
-			mode_idx = <0>;
-			path_type = "SENSOR_1080P_RAW10_LINER";
-		};
-		sensor1 {
-			subdev_name = "vivcam";
-			idx = <0xff>; // invalid
-			csi_idx = <0xff>;
-			path_type = "SENSOR_VGA_RAW10_LINER";
-		};
-		dma {
-			subdev_name = "vipre";
-			idx = <0>;
-			path_type = "VIPRE_CSI0_ISP1";
-		};
-		isp {
-			subdev_name = "isp";
-			idx = <1>;
-			path_type = "ISP_MI_PATH_PP";
-			output {
-				max_width = <1920>;
-				max_height = <1088>;
-				bit_per_pixel = <12>;
-				frame_count = <3>;
-			};
-		};
-		dsp {
-			subdev_name = "dsp";
-			idx = <0>;
-			path_type = "DSP_PATH_ISP_RY";
-			output {
-				max_width = <1920>;
-				max_height = <1088>;
-				bit_per_pixel = <12>;
-				frame_count = <3>;
-			};
-		};
-		ry {
-			subdev_name = "ry";
-			idx = <0>;
-			path_type = "ISP_RY_MI_PATH_MP";
-			output {
-				max_width = <1920>;
-				max_height = <1088>;
-				bit_per_pixel = <12>;
-				frame_count = <3>;
-			};
-		};
-		dw {
-			subdev_name = "dw";
-			idx = <0>;
-			path_type = "DW_DWE_VSE2";
-			dw_dst_depth = <2>;
-		};
-	};
-};
+#include "th1520-beagle.dts"

arch/riscv/boot/dts/thead/light-fm-emu-audio.dts

@@ -1,19 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (C) 2021 Alibaba Group Holding Limited.
- */
-
-#include "light-fm-emu.dts"
-
-/ {
-	model = "T-HEAD Light FM EMP Audio FPGA board";
-	compatible = "thead,light-fm-emu-audio", "thead,light";
-};
-
-&lightsound {
-	status = "okay";
-};
-
-&light_i2s {
-	status = "okay";
-};

arch/riscv/boot/dts/thead/light-fm-emu-dsi0-hdmi.dts

@@ -1,16 +0,0 @@
-#include "light-fm-emu-dsi0.dts"
-
-&disp1_out {
-	remote-endpoint = <&hdmi_tx_in>;
-};
-
-&hdmi_tx {
-	status = "okay";
-
-	port@0 {
-		/* input */
-		hdmi_tx_in: endpoint {
-			remote-endpoint = <&disp1_out>;
-		};
-	};
-};

arch/riscv/boot/dts/thead/light-fm-emu-dsi0.dts

@@ -1,64 +0,0 @@
-#include "light-fm-emu.dts"
-
-/ {
-	display-subsystem {
-		status = "okay";
-	};
-};
-
-&dpu_enc0 {
-	status = "okay";
-
-	ports {
-		/* output */
-		port@1 {
-			reg = <1>;
-
-			enc0_out: endpoint {
-				remote-endpoint = <&dsi0_in>;
-			};
-		};
-	};
-};
-
-&dpu {
-        status = "okay";
-};
-
-&dsi0 {
-        status = "okay";
-};
-
-&dhost_0 {
-	ports {
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		port@0 {
-			reg = <0>;
-
-			dsi0_in: endpoint {
-				remote-endpoint = <&enc0_out>;
-			};
-		};
-
-		port@1 {
-			reg = <1>;
-
-			dsi0_out: endpoint {
-				remote-endpoint = <&panel_in>;
-			};
-		};
-	};
-
-	panel@0 {
-		compatible = "hlt,hpk070h275";
-		reg = <0>;
-
-		port {
-			panel_in: endpoint {
-				remote-endpoint = <&dsi0_out>;
-			};
-		};
-	};
-};

arch/riscv/boot/dts/thead/light-fm-emu-dsp.dts

@@ -1,34 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (C) 2021 Alibaba Group Holding Limited.
- */
-
-#include "light-fm-emu.dts"
-
-/ {
-	model = "T-HEAD Light FM EMU DSP FPGA board";
-	compatible = "thead,light-fm-emu-dsp", "thead,light";
-
-	chosen {
-		linux,initrd-end = <0x0 0x1B000000>;
-	};
-};
-
-&resmem {
-	dsp_mem: memory@70000000 {
-		reg = <0x0 0x70000000 0 0x40000000>;
-		no-map;
-	};
-};
-
-&xtensa_dsp {
-	status = "okay";
-};
-
-&xtensa_dsp0 {
-	status = "okay";
-};
-
-&xtensa_dsp1 {
-	status = "disabled";
-};

arch/riscv/boot/dts/thead/light-fm-emu-gpu.dts

@@ -1,20 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (C) 2021 Alibaba Group Holding Limited.
- */
-
-#include "light-fm-emu.dts"
-
-/ {
-	model = "T-HEAD Light FM EMU GPU FPGA board";
-	compatible = "thead,light-fm-emu-gpu", "thead,light";
-
-	chosen {
-		linux,initrd-end = <0x0 0x18000000>;
-	};
-};
-
-&gpu {
-	status = "okay";
-};
-

arch/riscv/boot/dts/thead/light-fm-emu-hdmi.dts

@@ -1,26 +0,0 @@
-#include "light-fm-emu.dts"
-
-/ {
-	display-subsystem {
-		status = "okay";
-	};
-};
-
-&disp1_out {
-	remote-endpoint = <&hdmi_tx_in>;
-};
-
-&dpu {
-	status = "okay";
-};
-
-&hdmi_tx {
-	status = "okay";
-
-	port@0 {
-		/* input */
-		hdmi_tx_in: endpoint {
-			remote-endpoint = <&disp1_out>;
-		};
-	};
-};

arch/riscv/boot/dts/thead/light-fm-emu-npu-fce.dts

@@ -1,37 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (C) 2021 Alibaba Group Holding Limited.
- */
-
-#include "light-fm-emu.dts"
-
-/ {
-	model = "T-HEAD Light FM EMU NPU&FCE FPGA board";
-	compatible = "thead,light-fm-emu-npu-fce", "thead,light";
-
-	chosen {
-		linux,initrd-end = <0x0 0x1B000000>;
-	};
-
-	reserved-memory {
-		#address-cells = <2>;
-		#size-cells = <2>;
-		ranges;
-
-		facelib_mem: memory@e0000000 {
-			reg = <0x1 0xe0000000 0 0x20000000>;
-			no-map;
-		};
-	};
-};
-
-&npu {
-	vha_clk_rate = <13000000>;
-	status = "okay";
-};
-
-&fce {
-	memory-region = <&facelib_mem>;
-	status = "okay";
-};
-

arch/riscv/boot/dts/thead/light-fm-emu.dts

@@ -1,511 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (C) 2021 Alibaba Group Holding Limited.
- */
-
-/dts-v1/;
-
-#include "light-emu.dtsi"
-
-/ {
-	model = "T-HEAD Light FM EMU FPGA board";
-	compatible = "thead,light-fm-emu", "thead,light";
-
-	chosen {
-		bootargs = "console=ttyS0,115200 crashkernel=256M-:128M earlycon sram=0xffe0000000,0x180000";
-		linux,initrd-start = <0x0 0x2000000>;
-		linux,initrd-end = <0x0 0x4600000>;
-		stdout-path = "serial0:115200n8";
-	};
-
-	keys {
-		compatible = "gpio-keys";
-
-		key0 {
-			label = "key0";
-			gpios = <&gpio1_porta 7 1>;	/* GPIO_ACTIVE_LOW: 1 */
-			linux,code = <59>;		/* KEY_F1: 59 */
-			status = "okay";
-		};
-	};
-
-	leds {
-		compatible = "gpio-leds";
-
-		led0 {
-			label = "led0";
-			gpios = <&gpio1_porta 8 0>;	/* GPIO_ACTIVE_HIGH: 0 */
-			default-state = "off";
-		};
-	};
-
-	iopmp {
-		compatible = "thead,light-iopmp";
-
-		/* config#1: multiple valid regions */
-		iopmp_emmc: IOPMP_EMMC {
-			regions = <0x000000 0x100000>,
-				  <0x100000 0x200000>;
-			attr = <0xFFFFFFFF>;
-			dummy_slave= <0x800000>;
-		};
-
-		/* config#2: iopmp bypass */
-		iopmp_sdio0: IOPMP_SDIO0 {
-			bypass_en;
-		};
-
-		/* config#3: iopmp default region set */
-		iopmp_sdio1: IOPMP_SDIO1 {
-			attr = <0xFFFFFFFF>;
-			is_default_region;
-		};
-
-		iopmp_usb0: IOPMP_USB0 {
-			attr = <0xFFFFFFFF>;
-			is_default_region;
-		};
-
-		iopmp_ao: IOPMP_AO {
-			is_default_region;
-		};
-
-		iopmp_aud: IOPMP_AUD {
-			is_default_region;
-		};
-
-		iopmp_chip_dbg: IOPMP_CHIP_DBG {
-			is_default_region;
-		};
-
-		iopmp_eip120i: IOPMP_EIP120I {
-			is_default_region;
-		};
-
-		iopmp_eip120ii: IOPMP_EIP120II {
-			is_default_region;
-		};
-
-		iopmp_eip120iii: IOPMP_EIP120III {
-			is_default_region;
-		};
-
-		iopmp_isp0: IOPMP_ISP0 {
-			is_default_region;
-		};
-
-		iopmp_isp1: IOPMP_ISP1 {
-			is_default_region;
-		};
-
-		iopmp_dsp: IOPMP_DSP {
-			is_default_region;
-		};
-
-		iopmp_dw200: IOPMP_DW200 {
-			is_default_region;
-		};
-
-		iopmp_venc: IOPMP_VENC {
-			is_default_region;
-		};
-
-		iopmp_vdec: IOPMP_VDEC {
-			is_default_region;
-		};
-
-		iopmp_g2d: IOPMP_G2D {
-			is_default_region;
-		};
-
-		iopmp_fce: IOPMP_FCE {
-			is_default_region;
-		};
-
-		iopmp_npu: IOPMP_NPU {
-			is_default_region;
-		};
-
-		iopmp0_dpu: IOPMP0_DPU {
-			bypass_en;
-		};
-
-		iopmp1_dpu: IOPMP1_DPU {
-			bypass_en;
-		};
-
-		iopmp_gpu: IOPMP_GPU {
-			is_default_region;
-		};
-
-		iopmp_gmac1: IOPMP_GMAC1 {
-			is_default_region;
-		};
-
-		iopmp_gmac2: IOPMP_GMAC2 {
-			is_default_region;
-		};
-
-		iopmp_dmac: IOPMP_DMAC {
-			is_default_region;
-		};
-
-		iopmp_tee_dmac: IOPMP_TEE_DMAC {
-			is_default_region;
-		};
-	};
-
-	mbox_910t_client1: mbox_910t_client1 {
-		compatible = "thead,light-mbox-client";
-		mbox-names = "902";
-		mboxes = <&mbox_910t 1 0>;
-		status = "disabled";
-	};
-
-
-	mbox_910t_client2: mbox_910t_client2 {
-		compatible = "thead,light-mbox-client";
-		mbox-names = "906";
-		mboxes = <&mbox_910t 2 0>;
-		status = "disabled";
-	};
-
-	lightsound: lightsound@1 {
-		compatible = "simple-audio-card";
-		simple-audio-card,name = "Light-Sound-Card";
-
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		status = "disabled";
-		simple-audio-card,dai-link@0 {          /* I2S - CODEC */
-			reg = <0>;
-			format = "i2s";
-			cpu {
-				sound-dai = <&light_i2s 0>;
-			};
-			codec {
-				sound-dai = <&dummy_codec 2>;
-			};
-		};
-
-		simple-audio-card,dai-link@1 {          /* I2S - HDMI */
-			reg = <1>;
-			format = "i2s";
-			cpu {
-				sound-dai = <&light_i2s 1>;
-			};
-			codec {
-				sound-dai = <&dummy_codec 2>;
-			};
-		};
-	};
-
-	dummy_codec: dummy_codec {
-		#sound-dai-cells = <1>;
-		compatible = "linux,bt-sco";
-		status = "okay";
-	};
-};
-
-&i2c0 {
-	clock-frequency = <100000>;
-	status = "okay";
-
-	eeprom@50 {
-		compatible = "atmel,24c32";
-		reg = <0x50>;
-		pagesize = <32>;
-	};
-};
-
-&spi0 {
-	num-cs = <2>;
-	cs-gpios = <&gpio2_porta 15 0>, // GPIO_ACTIVE_HIGH: 0
-		   <&gpio2_porta 23 0>; // GPIO_ACTIVE_LOW: 1
-	status = "okay";
-
-	spi_norflash@0 {
-		#address-cells = <1>;
-		#size-cells = <1>;
-		compatible = "winbond,w25q64", "jedec,spi-nor";
-		reg = <0>;
-		spi-max-frequency = <8000000>;
-		w25q,fast-read;
-	};
-
-	spidev@1 {
-		compatible = "spidev";
-		#address-cells = <1>;
-		#size-cells = <1>;
-		reg = <1>;
-		spi-max-frequency = <12500000>;
-	};
-};
-
-&uart0 {
-	clock-frequency = <50000000>;
-};
-
-&qspi0 {
-	num-cs = <2>;
-	cs-gpios = <&gpio2_porta 3 0>, // GPIO_ACTIVE_HIGH: 0
-		   <&gpio2_porta 26 0>;
-	status = "okay";
-
-	spi-flash@0 {
-		#address-cells = <1>;
-		#size-cells = <1>;
-		compatible = "spi-nand";
-		spi-max-frequency = <10000000>;
-		spi-tx-bus-width = <4>;
-		spi-rx-bus-width = <4>;
-		reg = <0>;
-
-		partition@0 {
-			label = "ubi1";
-			reg = <0x00000000 0x08000000>;
-		};
-	};
-
-	spidev@1 {
-		compatible = "spidev";
-		#address-cells = <1>;
-		#size-cells = <1>;
-		reg = <1>;
-		spi-max-frequency = <6250000>;
-	};
-};
-
-&gmac0 {
-	max-speed = <100>;
-	phy-mode = "mii";
-	phy-handle = <&phy_88E1111_0>;
-	status = "okay";
-
-	mdio0 {
-		#address-cells = <1>;
-		#size-cells = <0>;
-		compatible = "snps,dwmac-mdio";
-
-		phy_88E1111_0: ethernet-phy@0 {
-			reg = <0x0 0x0>;
-		};
-	};
-};
-
-&gmac1 {
-	max-speed = <100>;
-	phy-mode = "mii";
-	phy-handle = <&phy_88E1111_1>;
-	status = "disabled";
-
-	mdio0 {
-		#address-cells = <1>;
-		#size-cells = <0>;
-		compatible = "snps,dwmac-mdio";
-
-		phy_88E1111_1: ethernet-phy@0 {
-			reg = <0x0 0x0>;
-		};
-	};
-};
-
-&emmc {
-	max-frequency = <50000000>;
-	non-removable;
-	no-sdio;
-	no-sd;
-	bus-width = <8>;
-	status = "okay";
-};
-
-&sdhci0 {
-	max-frequency = <50000000>;
-	no-1-8-v;
-	bus-width = <4>;
-	status = "okay";
-};
-
-&padctrl0_apsys {
-	light-fm-evb {
-			/*
-			 * Pin Configuration Node:
-			 * Format: <pin_id mux_node config>
-			 */
-			pinctrl_uart0: uart0grp {
-				thead,pins = <
-					FM_UART0_TXD	0x0	0x72
-					FM_UART0_RXD	0x0	0x72
-				>;
-			};
-
-			pinctrl_spi0: spi0grp {
-				thead,pins = <
-					FM_SPI_CSN	0x0	0x72
-				>;
-			};
-
-			pinctrl_qspi0: qspi0grp {
-				thead,pins = <
-					FM_QSPI0_CSN0	0x0	0x72
-				>;
-			};
-		};
-};
-
-&padctrl1_apsys {
-	light-fm-evb {
-			/*
-			 * Pin Configuration Node:
-			 * Format: <pin_id mux_node config>
-			 */
-			pinctrl_uart3: uart3grp {
-				thead,pins = <
-					FM_UART3_TXD	0x0	0x72
-					FM_UART3_RXD	0x0	0x72
-				>;
-			};
-
-			pinctrl_uart4: uart4grp {
-				thead,pins = <
-					FM_UART4_TXD	0x0	0x72
-					FM_UART4_RXD	0x0	0x72
-					FM_UART4_CTSN	0x0	0x72
-					FM_UART4_RTSN	0x0	0x72
-				>;
-			};
-		};
-};
-
-&padctrl_aosys {
-	light-fm-evb {
-			/*
-			 * Pin Configuration Node:
-			 * Format: <pin_id mux_node config>
-			 */
-
-			pinctrl_audiopa1: audiopa1_grp {
-				thead,pins = <
-					FM_AUDIO_PA1	0x3	0x72
-				>;
-			};
-
-			pinctrl_audiopa2: audiopa2_grp {
-				thead,pins = <
-					FM_AUDIO_PA2	0x0	0x72
-				>;
-			};
-
-	};
-};
-
-&i2c2 {
-	status = "okay";
-};
-
-&isp0 {
-	status = "okay";
-};
-
-&isp1 {
-	status = "okay";
-};
-
-&isp_ry0 {
-	status = "okay";
-};
-
-&dewarp {
-	status = "okay";
-};
-
-&dec400_isp0 {
-	status = "okay";
-};
-
-&dec400_isp1 {
-	status = "okay";
-};
-
-&dec400_isp2 {
-	status = "okay";
-};
-
-&bm_visys {
-	status = "okay";
-};
-
-&bm_csi0 {
-	status = "okay";
-};
-
-&vi_pre {
-	status = "okay";
-};
-
-&vvcam_sensor0 {
-	sensor_name = "OV5693";
-	status = "okay";
-};
-
-&video{
-	status = "okay";
-	piplane0 {
-				pipline_id = <0>;
-				status = "okay";
-				sensor0 {
-					subdev_name = "vivcam";
-					idx = <0>;
-					csi_idx = <0>;
-					path_type = "SENSOR_VGA_RAW10_LINER";
-				};
-				/*
-				csi0 {
-					subdev_name = "bm_csi";
-					idx = <0>;
-				};
-				*/
-				dma {
-					subdev_name = "vipre";
-					idx = <0>;
-					path_type = "VIPRE_CSI0_ISP0";
-				};
-				isp {
-					subdev_name = "isp";
-					idx = <0>;
-						path_type = "ISP_MI_PATH_PP";
-				};
-				dsp {
-					subdev_name = "dsp";
-					idx = <0>;
-					path_type = "DSP_PATH_ISP_RY";
-				};
-				ry {
-					subdev_name = "ry";
-					idx = <0>;
-					path_type = "ISP_RY_MI_PATH_MP";
-				};
-				dw {
-					subdev_name = "dw";
-					idx = <0>;
-					path_type = "DW_PATH_MEM_DW_SC_MEM";
-				};
-	};
-};
-
-&vdec {
-	status = "okay";
-};
-
-&venc {
-	status = "okay";
-};
-
-&isp_venc_shake {
-	status = "okay";
-};
-
-&vidmem {
-	status = "okay";
-};

arch/riscv/boot/dts/thead/light-lpi4a-16gb.dts

@@ -0,0 +1,6 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2024 ISCAS.
+ */
+
+#include "th1520-lpi4a-16gb.dts"

arch/riscv/boot/dts/thead/light-lpi4a-console-16g.dts

@@ -0,0 +1,6 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2024 ISCAS.
+ */
+
+#include "th1520-lpi4a-console-16g.dts"

arch/riscv/boot/dts/thead/light-lpi4a-console.dts

@@ -0,0 +1,6 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2024 ISCAS.
+ */
+
+#include "th1520-lpi4a-console.dts"

arch/riscv/boot/dts/thead/light-lpi4a.dts

@@ -0,0 +1,6 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2024 ISCAS.
+ */
+
+#include "th1520-lpi4a-product.dts"

arch/riscv/boot/dts/thead/light-powergate.dts

@@ -1,99 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (C) 2021 Alibaba Group Holding Limited.
- */
-
-&npu {
-	power-domains = <&pd LIGHT_AON_NPU_PD>;
-};
-
-&gpu {
-	power-domains = <&pd LIGHT_AON_GPU_PD>;
-};
-
-&vdec {
-	power-domains = <&pd LIGHT_AON_VDEC_PD>;
-};
-
-&venc {
-	power-domains = <&pd LIGHT_AON_VENC_PD>;
-};
-
-&xtensa_dsp0 {
-	power-domains = <&pd LIGHT_AON_DSP0_PD>;
-	clocks = <&dspsys_clk_gate CLKGEN_DSP0_PCLK>, <&dspsys_clk_gate CLKGEN_DSP0_CCLK>;
-	clock-names = "pclk", "cclk";
-};
-
-&xtensa_dsp1 {
-	power-domains = <&pd LIGHT_AON_DSP1_PD>;
-	clocks = <&dspsys_clk_gate CLKGEN_DSP1_PCLK>, <&dspsys_clk_gate CLKGEN_DSP1_CCLK>;
-	clock-names = "pclk", "cclk";
-};
-
-&isp0 {
-	clocks =  <&visys_clk_gate LIGHT_CLKGEN_ISP0_ACLK>,
-	       <&visys_clk_gate LIGHT_CLKGEN_ISP0_HCLK>,
-	       <&visys_clk_gate LIGHT_CLKGEN_ISP0_PIXELCLK>,
-	       <&visys_clk_gate LIGHT_CLKGEN_ISP0_CLK>;
-	clock-names = "aclk", "hclk", "isp0_pclk", "cclk";
-};
-
-&isp1 {
-	clocks = <&visys_clk_gate LIGHT_CLKGEN_ISP0_ACLK>,
-	       <&visys_clk_gate LIGHT_CLKGEN_ISP0_HCLK>,
-	       <&visys_clk_gate LIGHT_CLKGEN_ISP0_PIXELCLK>,
-	       <&visys_clk_gate LIGHT_CLKGEN_ISP1_CLK>,
-	       <&visys_clk_gate LIGHT_CLKGEN_ISP1_PIXELCLK>;
-	clock-names = "aclk", "hclk", "isp0_pclk", "cclk", "isp1_pclk";
-};
-
-&isp_ry0 {
-	clocks = <&visys_clk_gate LIGHT_CLKGEN_ISP_RY_ACLK>,
-	       <&visys_clk_gate LIGHT_CLKGEN_ISP_RY_HCLK>,
-	        <&visys_clk_gate LIGHT_CLKGEN_ISP_RY_CCLK>;
-	clock-names = "aclk", "hclk", "cclk";
-};
-
-&dewarp {
-	clocks = <&visys_clk_gate LIGHT_CLKGEN_DW200_ACLK>,
-		<&visys_clk_gate LIGHT_CLKGEN_DW200_HCLK>,
-		<&visys_clk_gate LIGHT_CLKGEN_DW200_CLK_VSE>,
-		<&visys_clk_gate LIGHT_CLKGEN_DW200_CLK_DWE>;
-	clock-names = "aclk", "hclk", "vseclk", "dweclk";
-};
-
-&bm_csi0 { //CSI2
-    clocks = <&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI0_PCLK>,
-		<&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI0_PIXCLK>,
-		<&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI0_CFG_CLK>,
-		<&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI1_CFG_CLK>,
-		<&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI2_CFG_CLK>;
-	clock-names = "pclk", "pixclk", "cfg_clk0", "cfg_clk1", "cfg_clk2";
-};
-
-&bm_csi1 { //CSI2X2_B
-    clocks = <&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI1_PCLK>,
-		<&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI1_PIXCLK>,
-		<&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI0_CFG_CLK>,
-		<&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI1_CFG_CLK>,
-		<&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI2_CFG_CLK>;
-	clock-names = "pclk", "pixclk", "cfg_clk0", "cfg_clk1", "cfg_clk2";
-};
-
-&bm_csi2 { //CSI2X2_A
-    clocks = <&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI2_PCLK>,
-		<&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI2_PIXCLK>,
-		<&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI0_CFG_CLK>,
-		<&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI1_CFG_CLK>,
-		<&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI2_CFG_CLK>;
-	clock-names = "pclk", "pixclk", "cfg_clk0", "cfg_clk1", "cfg_clk2";
-};
-
-&vi_pre {
-    clocks = <&visys_clk_gate LIGHT_CLKGEN_VIPRE_ACLK>,
-             <&visys_clk_gate LIGHT_CLKGEN_VIPRE_PCLK>,
-             <&visys_clk_gate LIGHT_CLKGEN_VIPRE_PIXELCLK>;
-    clock-names ="aclk", "pclk", "pixclk";
-};
-

arch/riscv/boot/dts/thead/light_mpw.dts

@@ -1,259 +0,0 @@
-/dts-v1/;
-/ {
-	model = "T-HEAD c910 light mpw";
-	compatible = "thead,c910_light_mpw";
-	#address-cells = <2>;
-	#size-cells = <2>;
-
-	memory@0 {
-		device_type = "memory";
-		reg = <0x0 0x00200000 0x0 0xf0000000>;
-	};
-
-	cpus {
-		#address-cells = <1>;
-		#size-cells = <0>;
-		timebase-frequency = <0x2dc6c0>;
-		cpu@0 {
-			device_type = "cpu";
-			reg = <0>;
-			status = "okay";
-			compatible = "riscv";
-			riscv,isa = "rv64imafdcvsu";
-			mmu-type = "riscv,sv39";
-			cpu-freq = "1.5Ghz";
-			cpu-icache = "64KB";
-			cpu-dcache = "64KB";
-			cpu-l2cache = "2MB";
-			cpu-tlb = "1024 4-ways";
-			cpu-cacheline = "64Bytes";
-			cpu-vector = "0.7.1";
-			cpu0_intc: interrupt-controller {
-				#interrupt-cells = <1>;
-				compatible = "riscv,cpu-intc";
-				interrupt-controller;
-			};
-		};
-		cpu@1 {
-			device_type = "cpu";
-			reg = <1>;
-			status = "okay";
-			compatible = "riscv";
-			riscv,isa = "rv64imafdcvsu";
-			mmu-type = "riscv,sv39";
-			cpu-freq = "1.5Ghz";
-			cpu-icache = "64KB";
-			cpu-dcache = "64KB";
-			cpu-l2cache = "2MB";
-			cpu-tlb = "1024 4-ways";
-			cpu-cacheline = "64Bytes";
-			cpu-vector = "0.7.1";
-			cpu1_intc: interrupt-controller {
-				#interrupt-cells = <1>;
-				compatible = "riscv,cpu-intc";
-				interrupt-controller;
-			};
-		};
-		cpu@2 {
-			device_type = "cpu";
-			reg = <2>;
-			status = "okay";
-			compatible = "riscv";
-			riscv,isa = "rv64imafdcvsu";
-			mmu-type = "riscv,sv39";
-			cpu-freq = "1.5Ghz";
-			cpu-icache = "64KB";
-			cpu-dcache = "64KB";
-			cpu-l2cache = "2MB";
-			cpu-tlb = "1024 4-ways";
-			cpu-cacheline = "64Bytes";
-			cpu-vector = "0.7.1";
-			cpu2_intc: interrupt-controller {
-				#interrupt-cells = <1>;
-				compatible = "riscv,cpu-intc";
-				interrupt-controller;
-			};
-		};
-		cpu@3 {
-			device_type = "cpu";
-			reg = <3>;
-			status = "okay";
-			compatible = "riscv";
-			riscv,isa = "rv64imafdcvsu";
-			mmu-type = "riscv,sv39";
-			cpu-freq = "1.5Ghz";
-			cpu-icache = "64KB";
-			cpu-dcache = "64KB";
-			cpu-l2cache = "2MB";
-			cpu-tlb = "1024 4-ways";
-			cpu-cacheline = "64Bytes";
-			cpu-vector = "0.7.1";
-			cpu3_intc: interrupt-controller {
-				#interrupt-cells = <1>;
-				compatible = "riscv,cpu-intc";
-				interrupt-controller;
-			};
-		};
-	};
-
-	soc {
-		#address-cells = <2>;
-		#size-cells = <2>;
-		compatible = "simple-bus";
-		ranges;
-
-		reset: reset-sample {
-			compatible = "thead,reset-sample";
-			plic-delegate = <0xff 0xd81ffffc>;
-			using-csr-reset;
-			csr-copy = <
-				0x7c0 0x7c1 0x7c2 0x7c3 0x7c5 0x7cc
-				0x3b0 0x3b1 0x3b2 0x3b3
-				0x3b4 0x3b5 0x3b6 0x3b7
-				0x3a0
-				>;
-		};
-
-		clint0: clint@ffdc000000 {
-			compatible = "riscv,clint0";
-			interrupts-extended = <
-				&cpu0_intc  3 &cpu0_intc  7
-				&cpu1_intc  3 &cpu1_intc  7
-				&cpu2_intc  3 &cpu2_intc  7
-				&cpu3_intc  3 &cpu3_intc  7
-				>;
-			reg = <0xff 0xdc000000 0x0 0x04000000>;
-			clint,has-no-64bit-mmio;
-		};
-
-		intc: interrupt-controller@ffd8000000 {
-			#interrupt-cells = <1>;
-			compatible = "riscv,plic0";
-			interrupt-controller;
-			interrupts-extended = <
-				&cpu0_intc  0xffffffff &cpu0_intc  9
-				&cpu1_intc  0xffffffff &cpu1_intc  9
-				&cpu2_intc  0xffffffff &cpu2_intc  9
-				&cpu3_intc  0xffffffff &cpu3_intc  9
-				>;
-			reg = <0xff 0xd8000000 0x0 0x08000000>;
-			reg-names = "control";
-			riscv,max-priority = <7>;
-			riscv,ndev = <80>;
-		};
-
-                clocks {
-			compatible = "simple-bus";
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			dummy_apb: apb-clock {
-				compatible = "fixed-clock";
-				clock-frequency = <62500000>;
-				clock-output-names = "dummy_apb";
-				#clock-cells = <0>;
-			};
-
-			dummy_clock_sdhci: sdhci-clock {
-				compatible = "fixed-clock";
-				reg = <4>;	/* Not address, just for index */
-				clock-frequency = <198000000>;
-				clock-output-names = "dummy_clock_sdhci";
-				#clock-cells = <0>;
-			};
-
-			dummy_clock_gmac: gmac-clock {
-				compatible = "fixed-clock";
-				clock-frequency = <1000000000>;
-				clock-output-names = "dummy_clock_gmac";
-				#clock-cells = <0>;
-			};
-		};
-
-		serial@ffe7014000 {
-			compatible = "snps,dw-apb-uart";
-			reg = <0xff 0xe7014000 0x0 0x4000>;
-			interrupt-parent = <&intc>;
-			interrupts = <36>;
-			clocks = <&dummy_apb>;
-			clock-names = "baudclk";
-			reg-shift = <2>;
-			reg-io-width = <4>;
-		};
-
-		stmmac_axi_setup: stmmac-axi-config {
-			snps,wr_osr_lmt = <3>;
-			snps,rd_osr_lmt = <3>;
-			snps,blen = <16 8 4 0 0 0 0>;
-		};
-
-		gmac: ethernet@ffe7070000 {
-			compatible = "snps,dwmac";
-			reg = <0xff 0xe7070000 0x0 0x2000>;
-			interrupt-parent = <&intc>;
-			interrupts = <66>;
-			interrupt-names = "macirq";
-			clocks = <&dummy_clock_gmac>;
-			clock-names = "stmmaceth";
-			snps,pbl = <32>;
-			snps,fixed-burst;
-			snps,axi-config = <&stmmac_axi_setup>;
-
-			phy-mode = "rgmii-txid";
-			phy-handle = <&phy_88E1111>;
-			mdio0 {
-				#address-cells = <1>;
-				#size-cells = <0>;
-				compatible = "snps,dwmac-mdio";
-
-				phy_88E1111: ethernet-phy@0 {
-					reg = <0x1>;
-				};
-			};
-		};
-
-		emmc: sdhci@ffe7080000 {
-			compatible = "snps,dwcmshc-sdhci-light-mpw";
-			reg = <0xff 0xe7080000 0x0 0x10000
-			       0xff 0xEF014060 0x0 0x4>;
-			interrupt-parent = <&intc>;
-			interrupts = <62>;
-			interrupt-names = "sdhciirq";
-			clocks = <&dummy_clock_sdhci>;
-			clock-names = "core";
-			max-frequency = <198000000>;
-			non-removable;
-			is_emmc;
-			no-sdio;
-			no-sd;
-			no-1-8-v;
-			bus-width = <8>;
-			status = "okay";
-		};
-
-		sdcard: sd@ffe7090000 {
-			compatible = "snps,dwcmshc-sdhci-light-mpw";
-			reg = <0xff 0xe7090000 0x0 0x10000
-                   	       0xff 0xEF014064 0x0 0x4>;
-			interrupt-parent = <&intc>;
-			interrupts = <64>;
-			interrupt-names = "sdhci0irq";
-			clocks = <&dummy_clock_sdhci>;
-			clock-names = "core";
-			max-frequency = <198000000>;
-			bus-width = <4>;
-			status = "okay";
-		};
-
-		pmu: pmu {
-			interrupt-parent = <&cpu0_intc>;
-			interrupts = <17>;
-			compatible = "riscv,c910_pmu";
-		};
-	};
-
-	chosen {
-		bootargs = "console=ttyS0,115200 root=PARTUUID=80a5a8e9-c744-491a-93c1-4f4194fd690b rootfstype=ext4 rdinit=/sbin/init rootwait rw earlyprintk clk_ignore_unused loglevel=7 eth=00:a0:a0:a0:a0:a1";
-		stdout-path = "/soc/serial@ffe7014000:115200";
-	};
-};

arch/riscv/boot/dts/thead/overlays/BBORG_LOAD-00A2.dts

@@ -0,0 +1,71 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2020 - 2022 Deepak Khatri <lorforlinux@beagleboard.org>
+ * See Cape Interface Spec page for more info on Bone Buses
+ * https://docs.beagleboard.org/0.0/boards/capes/cape-interface-spec.html#beaglebone-cape-interface-spec
+ *
+ */
+
+/dts-v1/;
+/plugin/;
+
+/*
+ * Helper to show loaded overlays under: /proc/device-tree/chosen/overlays/
+ */
+&{/chosen} {
+	overlays {
+		BBORG_LOAD-00A2 = __TIMESTAMP__;
+	};
+};
+
+/*
+ * Easy load control through sysfs (/sys/class/leds/) using gpio-leds driver 
+ */
+
+&bone_led_P9_42 {
+    status = "okay";
+    label = "load-sink1";
+    default-state = "keep";
+};
+
+&bone_led_P9_41 {
+    status = "okay";
+    label = "load-sink2";
+    default-state = "keep";
+};
+
+&bone_led_P9_30 {
+    status = "okay";
+    label = "load-sink3";
+    default-state = "keep";
+};
+
+&bone_led_P9_27 {
+    status = "okay";
+    label = "load-sink4";
+    default-state = "keep";
+};
+
+&bone_led_P8_12 {
+    status = "okay";
+    label = "load-sink5";
+    default-state = "keep";
+};
+
+&bone_led_P8_11 {
+    status = "okay";
+    label = "load-sink6";
+    default-state = "keep";
+};
+
+&bone_led_P8_15 {
+    status = "okay";
+    label = "load-sink7";
+    default-state = "keep";
+};
+
+&bone_led_P8_17 {
+    status = "okay";
+    label = "load-sink8";
+    default-state = "keep";
+};

arch/riscv/boot/dts/thead/overlays/BBORG_RELAY-00A2.dts

@@ -0,0 +1,58 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2015 Robert Nelson <robertcnelson@gmail.com>
+ * Copyright (C) 2019 Amilcar Lucas <amilcar.lucas@iav.de>
+ * Copyright (C) 2020 - 2023 Deepak Khatri <lorforlinux@beagleboard.org>
+ *
+ * See Cape Interface Spec page for more info on Bone Buses
+ * https://docs.beagleboard.org/0.0/boards/capes/cape-interface-spec.html#beaglebone-cape-interface-spec
+ *
+ */
+
+/dts-v1/;
+/plugin/;
+
+/*
+ * Helper to show loaded overlays under: /proc/device-tree/chosen/overlays/
+ */
+&{/chosen} {
+	overlays {
+		BBORG_RELAY-00A2.kernel = __TIMESTAMP__;
+	};
+};
+
+/*
+ * Easy load control through sysfs (/sys/class/leds/) using gpio-leds driver
+ */
+
+// relay1
+&bone_led_P9_41 {
+	status = "okay";
+	// access: sys/class/leds/relay1
+	label = "relay1";
+	default-state = "keep";
+};
+
+// relay2
+&bone_led_P9_42 {
+	status = "okay";
+	// access: sys/class/leds/relay2
+	label = "relay2";
+	default-state = "keep";
+};
+
+// realy3
+&bone_led_P9_30 {
+	status = "okay";
+	// access: sys/class/leds/relay3
+	label = "relay3";
+	default-state = "keep";
+};
+
+// realy4
+&bone_led_P9_27 {
+	status = "okay";
+	// access: sys/class/leds/relay4
+	label = "relay4";
+	default-state = "keep";
+};

arch/riscv/boot/dts/thead/overlays/BONE-LED_P8_03.dts

@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2020 - 2022 Deepak Khatri <lorforlinux@beagleboard.org>
+ *
+ * See Cape Interface Spec page for more info on Bone Buses
+ * https://docs.beagleboard.org/0.0/boards/capes/cape-interface-spec.html#beaglebone-cape-interface-spec
+ *
+ * Virtual cape for LED on P8_03 
+ * Supports BBB, BBBWL, BBAI, and BBAI-64
+ *
+ */
+ 
+/dts-v1/;
+/plugin/;
+ 
+&{/chosen} {
+	overlays {
+		BONE-LED_P8_03 = __TIMESTAMP__;
+	};
+};
+
+/*
+ * Easy LED control through sysfs (/sys/class/leds/) using gpio-leds driver
+ */
+
+&bone_led_P8_03 {
+    status = "okay";
+    // access: sys/class/leds/led_P8_03
+    label = "led_P8_03";
+    linux,default-trigger = "heartbeat";
+    default-state = "on";
+};

arch/riscv/boot/dts/thead/overlays/BONE-LED_P9_11.dts

@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2020 - 2022 Deepak Khatri <lorforlinux@beagleboard.org>
+ *
+ * See Cape Interface Spec page for more info on Bone Buses
+ * https://docs.beagleboard.org/0.0/boards/capes/cape-interface-spec.html#beaglebone-cape-interface-spec
+ *
+ * Virtual cape for LED on P9_11 
+ * Supports BBB, BBBWL, BBAI, and BBAI-64
+ *
+ */
+ 
+/dts-v1/;
+/plugin/;
+ 
+&{/chosen} {
+	overlays {
+		BONE-LED_P9_11 = __TIMESTAMP__;
+	};
+};
+
+/*
+ * Easy LED control through sysfs (/sys/class/leds/) using gpio-leds driver
+ */
+
+&bone_led_P9_11 {
+    status = "okay";
+    // access: sys/class/leds/led_P9_11
+    label = "led_P9_11";
+    linux,default-trigger = "heartbeat";
+    default-state = "on";
+};

arch/riscv/boot/dts/thead/overlays/BVA-MIKROBUS-0.dts

@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2023 BeagleBoard.org - https://beagleboard.org/
+ * Copyright (C) 2023 Deepak Khatri <lorforlinux@beagleboard.org>
+ *
+ * See Cape Interface Spec page for more info on Bone Buses
+ * https://docs.beagleboard.org/0.0/boards/capes/cape-interface-spec.html
+ *
+ */
+
+/dts-v1/;
+/plugin/;
+
+ /*
+ * Helper to show loaded overlays under: /proc/device-tree/chosen/overlays/
+ */
+ 
+&{/chosen} {
+	overlays {
+		BBORG_LOAD-00A2 = __TIMESTAMP__;
+	};
+};
+
+/*
+ * Enable mikroBus port
+ */
+
+&bone_mikrobus0 {
+    status = "okay";
+};

arch/riscv/boot/dts/thead/overlays/Makefile

@@ -0,0 +1,15 @@
+# Overlays for the CONFIG_SOC_THEAD platform
+
+dtbo-$(CONFIG_SOC_THEAD) += \
+	BBORG_LOAD-00A2.dtbo	\
+	BBORG_RELAY-00A2.dtbo	\
+	BONE-LED_P8_03.dtbo	\
+	BONE-LED_P9_11.dtbo	\
+	BVA-MIKROBUS-0.dtbo \
+	meles-wifibt-external-antenna.dtbo
+
+targets += dtbs dtbs_install
+targets += $(dtbo-y)
+
+always-y	:= $(dtbo-y)
+clean-files	:= *.dtbo

arch/riscv/boot/dts/thead/overlays/meles-wifibt-external-antenna.dts

@@ -0,0 +1,28 @@
+/dts-v1/;
+/plugin/;
+
+/ {
+	fragment@0 {
+		target-path = "/";
+
+		__overlay__ {
+			ext_antenna: ext-antenna {
+				status = "okay";
+				compatible = "regulator-fixed";
+				enable-active-low;
+				gpio = <&gpio1_porta 24 1>;
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-name = "ext_antenna";
+			};
+		};
+	};
+
+	fragment@1 {
+		target = <&board_antenna>;
+
+		__overlay__ {
+			status = "disabled";
+		};
+	};
+};

arch/riscv/boot/dts/thead/th1520-a-val-audio-i2s-8ch.dts

@@ -0,0 +1,100 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2021 Alibaba Group Holding Limited.
+ */
+
+#include "th1520-a-val-audio.dts"
+
+/ {
+	model = "T-HEAD Light FM Audio VAL board";
+	compatible = "thead,light-val-audio-i2s-8ch", "thead,light";
+};
+
+
+&lightsound {
+        status = "okay";
+
+	simple-audio-card,dai-link@1 {          /* I2S - AUDIO SYS CODEC 7210*/
+                reg = <1>;
+                format = "i2s";
+                cpu {
+                        sound-dai = <&i2s_8ch_sd2>;
+                };
+                codec {
+                        mclk-fs = <512>;
+                        sound-dai = <&es7210_audio_codec_adc0>;
+                };
+        };
+
+	simple-audio-card,dai-link@2 {          /* I2S - AUDIO SYS CODEC 7210*/
+                reg = <2>;
+                format = "i2s";
+                cpu {
+                        sound-dai = <&i2s_8ch_sd3>;
+                };
+                codec {
+                        mclk-fs = <512>;
+                        sound-dai = <&es7210_audio_codec_adc0>;
+                };
+        };
+
+        simple-audio-card,dai-link@3 {          /* I2S - AUDIO SYS CODEC 7210_1*/
+                reg = <3>;
+                format = "i2s";
+                cpu {
+                        sound-dai = <&i2s_8ch_sd0>;
+                };
+                codec {
+                        mclk-fs = <512>;
+                        sound-dai = <&es7210_audio_codec_adc1>;
+                };
+        };
+
+        simple-audio-card,dai-link@4 {          /* I2S - AUDIO SYS CODEC 7210_1*/
+                reg = <4>;
+                format = "i2s";
+                cpu {
+                        sound-dai = <&i2s_8ch_sd1>;
+                };
+                codec {
+                        mclk-fs = <512>;
+                        sound-dai = <&es7210_audio_codec_adc1>;
+                };
+        };
+};
+
+&i2s_8ch_sd0 {
+        status = "okay";
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_audiopa4>,
+                    <&pinctrl_audio_i2s_8ch_sd0>,
+                    <&pinctrl_audiopa2>,
+                    <&pinctrl_audiopa3>,
+                    <&pinctrl_audiopa8>,
+                    <&pinctrl_audio_i2s_8ch_bus>;
+};
+
+&i2s_8ch_sd1 {
+        status = "okay";
+};
+
+&i2s_8ch_sd2 {
+        status = "okay";
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_audiopa0>,
+                    <&pinctrl_audio_i2s_8ch_sd2>;
+};
+
+&i2s_8ch_sd3 {
+        status = "okay";
+};
+
+&es7210_audio_codec_adc0 {
+        status = "okay";
+        channels-max = <8>;
+};
+
+&es7210_audio_codec_adc1 {
+        status = "okay";
+        channels-max = <8>;
+};

arch/riscv/boot/dts/thead/th1520-a-val-audio-spdif.dts

@@ -0,0 +1,42 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2021 Alibaba Group Holding Limited.
+ */
+
+#include "th1520-a-val.dtsi"
+
+&spdif0 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_audio_spdif0>;
+	status = "okay";
+};
+
+&spdif1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_audio_spdif1>;
+	status = "okay";
+};
+
+&lightsound {
+        status = "okay";
+        simple-audio-card,dai-link@0 {          /* SPDIF0 */
+                reg = <1>;
+                format = "i2s";
+                cpu {
+                        sound-dai = <&spdif0>;
+                };
+                codec {
+                        sound-dai = <&dummy_codec>;
+                };
+        };
+        simple-audio-card,dai-link@1 {          /* SPDIF1 */
+                reg = <1>;
+                format = "i2s";
+                cpu {
+                        sound-dai = <&spdif1>;
+                };
+                codec {
+                        sound-dai = <&dummy_codec>;
+                };
+        };
+};

arch/riscv/boot/dts/thead/th1520-a-val-audio-tdm.dts

@@ -0,0 +1,182 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2021 Alibaba Group Holding Limited.
+ */
+
+#include "th1520-a-val.dtsi"
+
+&tdm_slot1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_audio_tdm>;
+	status = "okay";
+};
+
+&tdm_slot2 {
+	status = "okay";
+};
+
+&tdm_slot3 {
+	status = "okay";
+};
+
+&tdm_slot4 {
+	status = "okay";
+};
+
+&tdm_slot5 {
+	status = "okay";
+};
+
+&tdm_slot6 {
+	status = "okay";
+};
+
+&tdm_slot7 {
+	status = "okay";
+};
+
+&tdm_slot8 {
+	status = "okay";
+};
+
+&audio_i2c0 {
+        clock-frequency = <100000>;
+        status = "okay";
+
+        es7210_adc2: es7210@42 {
+                #sound-dai-cells = <0>;
+                compatible = "MicArray_0";
+                reg = <0x42>;
+                work-mode = "ES7210_TDM_1LRCK_DSPB";
+                channels-max = <8>;
+                sound-name-prefix = "ES7210_ADC2";
+                MVDD-supply = <&soc_aud_adc_3v3_en_reg>;
+                AVDD-supply = <&soc_aud_adc_3v3_en_reg>;
+                DVDD-supply = <&soc_dvdd18_aon_reg>;
+                PVDD-supply = <&soc_dvdd18_aon_reg>;
+        };
+
+        es7210_adc3: es7210@43 {
+                #sound-dai-cells = <0>;
+                compatible = "MicArray_1";
+                reg = <0x43>;
+                work-mode = "ES7210_TDM_1LRCK_DSPB";
+                channels-max = <8>;
+                sound-name-prefix = "ES7210_ADC3";
+                MVDD-supply = <&soc_aud_adc_3v3_en_reg>;
+                AVDD-supply = <&soc_aud_adc_3v3_en_reg>;
+                DVDD-supply = <&soc_dvdd18_aon_reg>;
+                PVDD-supply = <&soc_dvdd18_aon_reg>;
+        };
+};
+
+&lightsound {
+        status = "okay";
+        simple-audio-card,widgets = "Speaker", "Speaker";
+        simple-audio-card,routing = 
+        	"AW87519 IN", "ES8156 ROUT",
+        	"Speaker", "AW87519 VO";
+        simple-audio-card,aux-devs = <&audio_aw87519_pa>;
+        simple-audio-card,dai-link@0 {          /* I2S - AUDIO SYS CODEC 8156*/
+                reg = <0>;
+                format = "i2s";
+                cpu {
+                        sound-dai = <&i2s0 0>;
+                };
+                codec {
+                        sound-dai = <&es8156_audio_codec>;
+                };
+        };
+
+        simple-audio-card,dai-link@1 {          /* TDM - AUDIO SYS CODEC 7210*/
+                reg = <1>;
+                format = "dsp_b";
+                cpu {
+                        sound-dai = <&tdm_slot1>;
+                };
+                codec {
+                        sound-dai = <&es7210_adc2>;
+                };
+        };
+
+        simple-audio-card,dai-link@2 {
+                reg = <1>;
+                format = "dsp_b";
+                cpu {
+                        sound-dai = <&tdm_slot2>;
+                };
+                codec {
+                        sound-dai = <&es7210_adc2>;
+                };
+        };
+
+        simple-audio-card,dai-link@3 {
+                reg = <1>;
+                format = "dsp_b";
+                cpu {
+                        sound-dai = <&tdm_slot3>;
+                };
+                codec {
+                        sound-dai = <&es7210_adc2>;
+                };
+        };
+
+        simple-audio-card,dai-link@4 {
+                reg = <1>;
+                format = "dsp_b";
+                cpu {
+                        sound-dai = <&tdm_slot4>;
+                };
+                codec {
+                        sound-dai = <&es7210_adc2>;
+                };
+        };
+
+        simple-audio-card,dai-link@5 {
+                reg = <1>;
+                format = "dsp_b";
+                cpu {
+                        sound-dai = <&tdm_slot5>;
+                };
+                codec {
+                        sound-dai = <&es7210_adc2>;
+                };
+        };
+
+        simple-audio-card,dai-link@6 {
+                reg = <1>;
+                format = "dsp_b";
+                cpu {
+                        sound-dai = <&tdm_slot6>;
+                };
+                codec {
+                        sound-dai = <&es7210_adc2>;
+                };
+        };
+
+        simple-audio-card,dai-link@7 {
+                reg = <1>;
+                format = "dsp_b";
+                cpu {
+                        sound-dai = <&tdm_slot7>;
+                };
+                codec {
+                        sound-dai = <&es7210_adc2>;
+                };
+        };
+
+        simple-audio-card,dai-link@8 {
+                reg = <1>;
+                format = "dsp_b";
+                cpu {
+                        sound-dai = <&tdm_slot8>;
+                };
+                codec {
+                        sound-dai = <&es7210_adc2>;
+                };
+        };
+};
+
+&i2s0 {
+        status = "okay";
+};

arch/riscv/boot/dts/thead/th1520-a-val-audio.dts

@@ -3,7 +3,7 @@
  * Copyright (C) 2021 Alibaba Group Holding Limited.
  */
 
-#include "light-a-val.dts"
+#include "th1520-a-val.dtsi"
 
 / {
 	model = "T-HEAD Light FM Audio VAL board";
@@ -11,8 +11,12 @@
 };
 
 &lightsound {
-	status = "okay";
-
+        status = "okay";
+        simple-audio-card,widgets = "Speaker", "Speaker";
+        simple-audio-card,routing = 
+        	"Speaker", "AW87519 VO",
+        	"AW87519 IN", "ES8156 ROUT";
+        simple-audio-card,aux-devs = <&audio_aw87519_pa>;
         simple-audio-card,dai-link@0 {          /* I2S - AUDIO SYS CODEC 8156*/
                 reg = <0>;
                 format = "i2s";
@@ -28,22 +32,24 @@
                 reg = <1>;
                 format = "i2s";
                 cpu {
-                        sound-dai = <&i2s3 0>;
+                        sound-dai = <&i2s_8ch_sd2 2>;
                 };
                 codec {
-                        sound-dai = <&es7210_audio_codec>;
+                        sound-dai = <&es7210_audio_codec_adc0>;
                 };
         };
 };
 
-&light_i2s {
-	status = "okay";
-};
-
 &i2s0 {
         status = "okay";
 };
 
-&i2s3 {
+&i2s_8ch_sd2 {
         status = "okay";
 };
+
+&es7210_audio_codec_adc0 {
+        status = "okay";
+};
+
+

arch/riscv/boot/dts/thead/th1520-a-val-crash.dts

@@ -3,7 +3,7 @@
  * Copyright (C) 2021 Alibaba Group Holding Limited.
  */
 
-#include "light-crash.dts"
+#include "th1520-crash.dtsi"
 
 &aon {
 	aon_reg_dialog: light-dialog-reg {

arch/riscv/boot/dts/thead/th1520-a-val-dsi0-dsi1.dts

@@ -5,7 +5,7 @@
 
 /dts-v1/;
 
-#include "light-a-val-dsi0.dts"
+#include "th1520-a-val-dsi0.dts"
 
 &dpu_enc1 {
 	status = "okay";

arch/riscv/boot/dts/thead/th1520-a-val-dsi0-hdmi.dts

@@ -5,7 +5,7 @@
 
 /dts-v1/;
 
-#include "light-a-ref-dsi0.dts"
+#include "th1520-a-val-dsi0.dts"
 
 &dpu_enc1 {
         ports {

arch/riscv/boot/dts/thead/th1520-a-val-dsi0.dts

@@ -5,7 +5,7 @@
 
 /dts-v1/;
 
-#include "light-a-ref.dts"
+#include "th1520-a-val.dtsi"
 
 / {
 	display-subsystem {

arch/riscv/boot/dts/thead/th1520-a-val-sec.dts

@@ -5,14 +5,13 @@
 
 /dts-v1/;
 
-#include "light-b-product.dts"
-
+#include "th1520-a-val.dts"
 
 
 &light_iopmp {
         status = "disabled";
 };
 
-&qspi1 {
+&eip_28 {
         status = "disabled";
 };

arch/riscv/boot/dts/thead/th1520-a-val.dts

@@ -5,7 +5,7 @@
 
 /dts-v1/;
 
-#include "light-a-val.dts"
+#include "th1520-a-val-audio.dts"
 
 / {
 	display-subsystem {
@@ -40,15 +40,15 @@
 
 &lightsound {
 	status = "okay";
-
-	simple-audio-card,dai-link@1 {          /* I2S - HDMI */
-		reg = <1>;
+	
+	simple-audio-card,dai-link@2 {          /* I2S - HDMI */
+		reg = <2>;
 		format = "i2s";
 		cpu {
 			sound-dai = <&light_i2s 1>;
 		};
 		codec {
-			sound-dai = <&dummy_codec 2>;
+			sound-dai = <&dummy_codec>;
 		};
 	};
 };