riscv: dts: thead: downclock SD card for LPi4A

It's reported that @198MHz some R/W error will happen.

215f2c97bd.patch

Signed-off-by: Han Gao <gaohan@iscas.ac.cn>

.github/workflows/build.yml

@@ -0,0 +1,137 @@
+name: thead-u-boot-build
+
+on:
+  push:
+    tags:
+      - '*'
+    branches:
+      - '*'
+  pull_request:
+  workflow_dispatch:
+  schedule:
+    - cron: "0 2 * * *"
+
+env:
+  xuantie_toolchain: https://occ-oss-prod.oss-cn-hangzhou.aliyuncs.com/resource//1698113812618
+  toolchain_file_name: Xuantie-900-gcc-linux-5.10.4-glibc-x86_64-V2.8.0-20231018.tar.gz
+  mainline_toolchain: https://github.com/riscv-collab/riscv-gnu-toolchain/releases/download/2023.10.18
+  mainline_toolchain_file_name: riscv64-glibc-ubuntu-22.04-gcc-nightly-2023.10.18-nightly.tar.gz
+  wget_alias: 'wget --retry-connrefused --waitretry=1 --read-timeout=20 --timeout=15 -t 0'
+  ARCH: riscv
+  CROSS_COMPILE: riscv64-unknown-linux-gnu-
+
+jobs:
+  build:
+    strategy:
+      fail-fast: false
+      matrix:
+        name: [thead-gcc, gcc-13]
+
+    runs-on: ubuntu-22.04
+
+    steps:
+      - name: Install software
+        run: |
+              sudo apt update && \
+              sudo apt install -y gdisk dosfstools g++-12-riscv64-linux-gnu build-essential \
+                                  libncurses-dev gawk flex bison openssl libssl-dev tree \
+                                  dkms libelf-dev libudev-dev libpci-dev libiberty-dev autoconf device-tree-compiler
+
+      - name: Checkout uboot
+        uses: actions/checkout@v4
+
+      - name: uboot compile
+        run: |
+              mkdir output
+              if [[ ${{ matrix.name }} = "thead-gcc" ]]; then
+                ${wget_alias} ${xuantie_toolchain}/${toolchain_file_name}
+                tar -xvf ${toolchain_file_name} -C /opt
+                export PATH="/opt/Xuantie-900-gcc-linux-5.10.4-glibc-x86_64-V2.8.0/bin:$PATH"
+              else
+                ${wget_alias} ${mainline_toolchain}/${mainline_toolchain_file_name}
+                tar -xvf ${mainline_toolchain_file_name} -C /opt
+                export PATH="/opt/riscv/bin:$PATH"
+              fi
+              ${CROSS_COMPILE}gcc -v
+
+              pushd $PWD
+                make light_lpi4a_16g_defconfig
+                make -j$(nproc)
+                find . -name "u-boot-with-spl.bin" | xargs -I{} cp -av {} ${GITHUB_WORKSPACE}/output/u-boot-with-spl-lpi4a-16g.bin
+                make clean
+                make light_lpi4a_defconfig
+                make -j$(nproc)
+                find . -name "u-boot-with-spl.bin" | xargs -I{} cp -av {} ${GITHUB_WORKSPACE}/output/u-boot-with-spl-lpi4a.bin
+                make clean
+                make light_lpi4a_console_defconfig
+                make -j$(nproc)
+                find . -name "u-boot-with-spl.bin" | xargs -I{} cp -av {} ${GITHUB_WORKSPACE}/output/u-boot-with-spl-lcon4a.bin
+                make clean
+                make light_lpi4a_console_16g_defconfig
+                make -j$(nproc)
+                find . -name "u-boot-with-spl.bin" | xargs -I{} cp -av {} ${GITHUB_WORKSPACE}/output/u-boot-with-spl-lcon4a-16g.bin
+                make clean
+                make light_lpi4a_cluster_defconfig
+                make -j$(nproc)
+                find . -name "u-boot-with-spl.bin" | xargs -I{} cp -av {} ${GITHUB_WORKSPACE}/output/u-boot-with-spl-lc4a.bin
+                make clean
+                make light_lpi4a_cluster_16g_defconfig
+                make -j$(nproc)
+                find . -name "u-boot-with-spl.bin" | xargs -I{} cp -av {} ${GITHUB_WORKSPACE}/output/u-boot-with-spl-lc4a-16g.bin
+                make clean
+                make light_beagle_defconfig
+                make -j$(nproc)
+                find . -name "u-boot-with-spl.bin" | xargs -I{} cp -av {} ${GITHUB_WORKSPACE}/output/u-boot-with-spl-beagle.bin
+                make clean
+                make light_a_val_defconfig
+                make -j$(nproc)
+                find . -name "u-boot-with-spl.bin" | xargs -I{} cp -av {} ${GITHUB_WORKSPACE}/output/u-boot-with-spl-vala.bin
+                make clean
+                make light_milkv_meles_dualrank_defconfig
+                make -j$(nproc)
+                find . -name "u-boot-with-spl.bin" | xargs -I{} cp -av {} ${GITHUB_WORKSPACE}/output/u-boot-with-spl-meles.bin
+                make clean
+                make light_milkv_meles_singlerank_defconfig
+                make -j$(nproc)
+                find . -name "u-boot-with-spl.bin" | xargs -I{} cp -av {} ${GITHUB_WORKSPACE}/output/u-boot-with-spl-meles-4g.bin
+
+                # mainline support
+                make clean
+                make light_lpi4a_defconfig
+                sed -i 's#thead/light-lpi4a.dtb#thead/th1520-lichee-pi-4a.dtb#' .config
+                make -j$(nproc)
+                find . -name "u-boot-with-spl.bin" | xargs -I{} cp -av {} ${GITHUB_WORKSPACE}/output/u-boot-with-spl-lpi4a-main.bin
+
+                make clean
+                make light_lpi4a_16g_defconfig
+                sed -i 's#thead/light-lpi4a-16gb.dtb#thead/th1520-lichee-pi-4a-16g.dtb#' .config
+                make -j$(nproc)
+                find . -name "u-boot-with-spl.bin" | xargs -I{} cp -av {} ${GITHUB_WORKSPACE}/output/u-boot-with-spl-lpi4a-16g-main.bin
+
+                make clean
+                make light_lpi4a_cluster_defconfig
+                sed -i 's#thead/light-lpi4a-cluster.dtb#thead/th1520-lichee-cluster-4a.dtb#' .config
+                make -j$(nproc)
+                find . -name "u-boot-with-spl.bin" | xargs -I{} cp -av {} ${GITHUB_WORKSPACE}/output/u-boot-with-spl-lc4a-main.bin
+
+                make clean
+                make light_lpi4a_cluster_16g_defconfig
+                sed -i 's#thead/light-lpi4a-cluster-16gb.dtb#thead/th1520-lichee-cluster-4a-16g.dtb#' .config
+                make -j$(nproc)
+                find . -name "u-boot-with-spl.bin" | xargs -I{} cp -av {} ${GITHUB_WORKSPACE}/output/u-boot-with-spl-lc4a-16g-main.bin
+              popd
+              tree ${GITHUB_WORKSPACE}/output
+
+      - name: 'Upload Artifact'
+        uses: actions/upload-artifact@v3
+        with:
+          name: thead-u-uboot-${{ matrix.name }}
+          path: output/*.bin
+          retention-days: 30
+
+      - name: 'Create release by tag'
+        uses: softprops/action-gh-release@v1
+        if: ${{ startsWith(github.ref, 'refs/tags/') && matrix.name == 'thead-gcc' }}
+        with:
+          files: output/*.bin
+          token: ${{ secrets.GITHUB_TOKEN }}

Kconfig

@@ -302,7 +302,7 @@ menu "Boot images"
 
 config ANDROID_BOOT_IMAGE
 	bool "Enable support for Android Boot Images"
-	default y if FASTBOOT
+	default n if FASTBOOT
 	help
 	  This enables support for booting images which use the Android
 	  image format header.

Makefile

@@ -219,7 +219,7 @@ endif
 
 ifeq ($(KBUILD_SRC),)
         # building in the source tree
-        srctree := .
+        srctree := $(shell pwd)
 else
         ifeq ($(KBUILD_SRC)/,$(dir $(CURDIR)))
                 # building in a subdirectory of the source tree
@@ -726,6 +726,7 @@ UBOOTINCLUDE    := \
 			$(if $(CONFIG_HAS_THUMB2),, \
 				-I$(srctree)/arch/$(ARCH)/thumb1/include),) \
 		-I$(srctree)/arch/$(ARCH)/include \
+		$(if $(CONFIG_TARGET_LIGHT_C910), -I$(srctree)/lib/sec_library/include) \
 		-include $(srctree)/include/linux/kconfig.h
 
 NOSTDINC_FLAGS += -nostdinc -isystem $(shell $(CC) -print-file-name=include)
@@ -811,7 +812,7 @@ PLATFORM_LIBGCC := -L $(shell dirname `$(CC) $(c_flags) -print-libgcc-file-name`
 endif
 PLATFORM_LIBS += $(PLATFORM_LIBGCC)
 ifeq ($(CONFIG_TARGET_LIGHT_C910),y)
-PLATFORM_LIBS += -L $(shell pwd)/lib/sec_library -lsec_library
+PLATFORM_LIBS += -L $(srctree)/lib/sec_library -lsec_library
 endif
 
 ifdef CONFIG_CC_COVERAGE

arch/Kconfig

@@ -119,6 +119,7 @@ config SANDBOX
 	select SPI
 	select SUPPORT_OF_CONTROL
 	select SYSRESET_CMD_POWEROFF if CMD_POWEROFF
+	select SUPPORT_EXTENSION_SCAN
 	imply BITREVERSE
 	select BLOBLIST
 	imply CMD_DM
@@ -152,6 +153,7 @@ config SANDBOX
 	imply PHYLIB
 	imply DM_MDIO
 	imply DM_MDIO_MUX
+	imply CMD_EXTENSION
 
 config SH
 	bool "SuperH architecture"

arch/riscv/Makefile

@@ -24,7 +24,16 @@ ifeq ($(CONFIG_CMODEL_MEDANY),y)
 	CMODEL = medany
 endif
 
-ARCH_FLAGS = -march=$(ARCH_BASE)$(ARCH_A)$(ARCH_C) -mabi=$(ABI) \
+RISCV_MARCH = $(ARCH_BASE)$(ARCH_A)$(ARCH_C)
+
+# Newer binutils versions default to ISA spec version 20191213 which moves some
+# instructions from the I extension to the Zicsr and Zifencei extensions.
+toolchain-need-zicsr-zifencei := $(call cc-option-yn, -mabi=$(ABI) -march=$(RISCV_MARCH)_zicsr_zifencei)
+ifeq ($(toolchain-need-zicsr-zifencei),y)
+	RISCV_MARCH := $(RISCV_MARCH)_zicsr_zifencei
+endif
+
+ARCH_FLAGS = -march=$(RISCV_MARCH) -mabi=$(ABI) \
 	     -mcmodel=$(CMODEL)
 
 PLATFORM_CPPFLAGS	+= $(ARCH_FLAGS)

arch/riscv/cpu/c9xx/Makefile

@@ -6,3 +6,4 @@
 
 obj-y += dram.o
 obj-y += cpu.o
+obj-y += feature.o

arch/riscv/cpu/c9xx/cpu.c

@@ -122,25 +122,31 @@ void invalid_dcache_range(unsigned long start, unsigned long end)
 
 void icache_enable(void)
 {
+#ifdef CONFIG_SPL_BUILD
 #ifdef CONFIG_SPL_RISCV_MMODE
 #ifdef CONFIG_TARGET_LIGHT_C910
+// mhcr is 0x7c1
 	asm volatile (
-        "csrr x29, mhcr\n\t"
+        "csrr x29, 0x7c1\n\t"
         "ori x28, x29, 0x1\n\t"
-        "csrw mhcr, x28\n\t"
+        "csrw 0x7c1, x28\n\t"
     );
 #endif
 #endif
+#endif
 }
 
 void dcache_enable(void)
 {
+#ifdef CONFIG_SPL_BUILD
 #ifdef CONFIG_SPL_RISCV_MMODE
 #ifdef CONFIG_TARGET_LIGHT_C910
 	asm volatile (
-        "li x29, 0x11ff\n\t"
-        "csrw mhcr, x29\n\t"
+	"csrr x29, 0x7c1\n\t"
+	"ori x28, x29, 0x2\n\t"
+	"csrw 0x7c1, x28\n\t"
     );
 #endif
 #endif
+#endif
 }

arch/riscv/cpu/c9xx/feature.c

@@ -0,0 +1,114 @@
+#include <common.h>
+#include <asm/types.h>
+#include <asm/asm.h>
+#include <asm/csr.h>
+
+void setup_features(void)
+{
+	unsigned int i, cpu_type, cpu_ver;
+	unsigned long version[8];
+
+	for (i = 0; i < 8; i++)
+		version[i] = csr_read(CSR_MCPUID);
+
+	cpu_type = (version[0] >> 18) & 0xf;
+	cpu_ver  = (version[1] >> 12) & 0xffff;
+
+	/*
+	 * Warning: CSR_MCCR2 contains an L2 cache latency setting,
+	 * you need to confirm it by your own soc design.
+	 */
+	switch (cpu_type) {
+	case 0x3:
+		if (cpu_ver >= 0x1080 && cpu_ver <= 0x10bf) { //1.2.0~1.2.x
+			csr_write(CSR_MCCR2, 0xe0010009);
+			csr_write(CSR_MXSTATUS, 0x638000);
+			csr_write(CSR_MHINT, 0x6e30c);
+			csr_write(CSR_MHCR, 0x1ff);
+		} else if (cpu_ver == 0x10ca) { //1.3.10
+			csr_write(CSR_MSMPR, 0x1);
+			csr_write(CSR_MCCR2, 0xe2490009);
+			csr_write(CSR_MXSTATUS, 0x638000);
+			csr_write(CSR_MHINT, 0x66e30c);
+			csr_write(CSR_MHCR, 0x17f);
+			csr_write(CSR_MHINT2, 0x420000);
+			csr_write(CSR_MHINT4, 0x410);
+		} else if (cpu_ver >= 0x1100 && cpu_ver <= 0x113f) { //1.4.0~1.4.x
+			csr_write(CSR_MSMPR, 0x1);
+			csr_write(CSR_MCCR2, 0xe2490009);
+			csr_write(CSR_MXSTATUS, 0x638000);
+			csr_write(CSR_MHINT, 0x16e30c);
+			csr_write(CSR_MHCR, 0x1ff);
+		} else if (cpu_ver >= 0x1140 && cpu_ver <= 0x117f) { //1.5.0~1.5.x
+			csr_write(CSR_MSMPR, 0x1);
+			csr_write(CSR_MCCR2, 0xe2490009);
+			csr_write(CSR_MXSTATUS, 0x638000);
+			csr_write(CSR_MHINT, 0xe6e30c);
+			csr_write(CSR_MHINT2, 0x180);
+			csr_write(CSR_MHCR, 0x1ff);
+		} else if (cpu_ver >= 0x1180 && cpu_ver <= 0x1183) { //1.6.0~1.6.3
+			csr_write(CSR_MSMPR, 0x1);
+			csr_write(CSR_MCCR2, 0xe249000b);
+			csr_write(CSR_MXSTATUS, 0x638000);
+			csr_write(CSR_MHINT, 0x1ee30c);
+			csr_write(CSR_MHINT2, 0x180);
+			csr_write(CSR_MHCR, 0x1ff);
+		} else if (cpu_ver >= 0x1184 && cpu_ver <= 0x123f) { //1.6.4~1.8.x
+			csr_write(CSR_MSMPR, 0x1);
+			csr_write(CSR_MCCR2, 0xe249000b);
+			csr_write(CSR_MXSTATUS, 0x638000);
+			csr_write(CSR_MHINT, 0x1ee30c);
+			csr_write(CSR_MHINT2, 0x180);
+			csr_write(CSR_MHCR, 0x11ff);
+		} else if (cpu_ver >= 0x2000 && cpu_ver <= 0xffff) { //2.0.0~
+			csr_write(CSR_MSMPR, 0x1);
+			csr_write(CSR_MCCR2, 0xe249000b);
+			csr_write(CSR_MXSTATUS, 0x438000);
+			csr_write(CSR_MHINT, 0x31ea32c);
+			csr_write(CSR_MHINT2, 0x180);
+			csr_write(CSR_MHCR, 0x11ff);
+		} else {
+			while(1);
+		}
+		break;
+	case 0x4:
+		if (cpu_ver >= 0x1002 && cpu_ver <= 0xffff) {
+			csr_write(CSR_MHCR, 0x17f);
+			csr_write(CSR_MXSTATUS, 0x638000);
+			csr_write(CSR_MHINT, 0x650c);
+		} else {
+			while(1);
+		}
+		break;
+	case 0x5:
+		if (cpu_ver >= 0x0000 && cpu_ver <= 0x0007) { //0.0.0~0.0.7
+			csr_write(CSR_MSMPR, 0x1);
+			csr_write(CSR_MCCR2, 0xe0420008);
+			csr_write(CSR_MXSTATUS, 0x638000);
+			csr_write(CSR_MHINT, 0x2c50c);
+			csr_write(CSR_MHCR, 0x11ff);
+		} else if (cpu_ver >= 0x0040 && cpu_ver <= 0xffff) { //0.1.0~
+			csr_write(CSR_MSMPR, 0x1);
+			csr_write(CSR_MCCR2, 0xa042000a);
+			csr_write(CSR_MXSTATUS, 0x438000);
+			csr_write(CSR_MHINT, 0x21aa10c);
+			csr_write(CSR_MHCR, 0x10011ff);
+		} else {
+			while(1);
+		}
+		break;
+	case 0x6:
+		if (cpu_ver >= 0x0) {
+			csr_write(CSR_MSMPR, 0x1);
+			csr_write(CSR_MCCR2, 0xA042000A);
+			csr_write(CSR_MXSTATUS, 0x638001);
+			csr_write(CSR_MHINT, 0x3A1AA10C);
+			csr_write(CSR_MHCR, 0x10011BF);
+		} else {
+			while(1);
+		}
+		break;
+	default:
+		while(1);
+	}
+}

arch/riscv/cpu/mtrap.S

@@ -30,7 +30,9 @@
 	.align 2
 	.global trap_entry
 trap_entry:
+#ifndef CONFIG_THEAD_PLIC
 	ebreak
+#endif
 	addi sp, sp, -32 * REGBYTES
 	SREG x1,   1 * REGBYTES(sp)
 	SREG x2,   2 * REGBYTES(sp)
@@ -102,3 +104,45 @@ trap_entry:
 	LREG x2,   2 * REGBYTES(sp)
 	addi sp, sp, 32 * REGBYTES
 	MODE_PREFIX(ret)
+
+	/* trap secondary_entry */
+	.align 10
+	.global secondary_entry
+secondary_entry:
+	/*
+	 * Clear L1 cache & BTB & BHT ...
+	 */
+	li      t0, 0x70013
+	csrw    CSR_MCOR, t0
+
+	/*
+	 * Enable cache coherency
+	 */
+	li	t0, 1
+	csrw	CSR_MSMPR, t0
+
+	/*
+	 *Prepare percpu stack
+	 */
+	csrr	t0, mhartid
+	li	t1, 0x100
+	mul	t1, t1, t0
+	lla	sp, stacks
+	add	sp, sp, t1
+
+	/*
+	 * Call C routine
+	 */
+	call	setup_features
+	call	next_stage
+
+	/*
+	 * Never get here, dead loop
+	 */
+	j .
+
+	.align 10
+stacks:
+	.rept 0x1000
+	.long
+	.endr

arch/riscv/cpu/start.S

@@ -41,6 +41,12 @@ secondary_harts_relocation_error:
 _start:
 
 #if (defined CONFIG_SPL_BUILD) && (defined CONFIG_TARGET_LIGHT_C910)
+	/* Disable indirect branch prediction once entering into uboot world */
+	li t0, 0x117f
+	csrw 0x7c1, t0
+	/* Disable fence broadcase and HW TLB */
+	li t0, 0x66e30c
+	csrw 0x7c5, t0
 	/* Enable cache ASAP as LIGHT's requirement */
 	jal	icache_enable
 	jal	dcache_enable

arch/riscv/dts/Makefile

@@ -5,7 +5,8 @@ dtb-$(CONFIG_TARGET_SIFIVE_FU540) += hifive-unleashed-a00.dtb
 dtb-$(CONFIG_TARGET_ICE_C910) += ice-c910.dtb
 dtb-$(CONFIG_TARGET_LIGHT_EVB_MPW_C910) += light-evb-mpw-c910.dtb
 dtb-$(CONFIG_TARGET_LIGHT_FPGA_FM_C910) += light-fpga-fm-c910.dtb
-dtb-$(CONFIG_TARGET_LIGHT_C910) += light-a-val.dtb light-b-product.dtb light-a-product.dtb light-ant-evt.dtb
+dtb-$(CONFIG_TARGET_LIGHT_C910) += light-a-ref.dtb light-b-ref.dtb light-a-val.dtb light-b-product.dtb light-a-product.dtb light-ant-ref.dtb light-beagle.dtb light-b-power.dtb light-lpi4a.dtb light-milkv-meles.dtb
+dtb-$(CONFIG_TARGET_LIGHT_C910) += light-lpi4a-laptop.dtb
 
 targets += $(dtb-y)
 

arch/riscv/dts/light-a-ref.dts

@@ -0,0 +1,482 @@
+/dts-v1/;
+/ {
+	model = "T-HEAD c910 light";
+	compatible = "thead,c910_light";
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	memory@0 {
+		device_type = "memory";
+		reg = <0x0 0xc0000000 0x0 0x40000000>;
+	};
+
+	aliases {
+		spi0 = &spi0;
+		spi1 = &qspi0;
+		spi2 = &qspi1;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		timebase-frequency = <3000000>;
+		u-boot,dm-pre-reloc;
+		cpu@0 {
+			device_type = "cpu";
+			reg = <0>;
+			status = "okay";
+			compatible = "riscv";
+			riscv,isa = "rv64imafdcvsu";
+			mmu-type = "riscv,sv39";
+			u-boot,dm-pre-reloc;
+		};
+	};
+
+	soc {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		compatible = "simple-bus";
+		ranges;
+		u-boot,dm-pre-reloc;
+
+		dummy_apb: apb-clock {
+			compatible = "fixed-clock";
+			clock-frequency = <62500000>;
+			clock-output-names = "dummy_apb";
+			#clock-cells = <0>;
+			u-boot,dm-pre-reloc;
+		};
+
+		dummy_ahb: ahb-clock {
+			compatible = "fixed-clock";
+			clock-frequency = <250000000>;
+			clock-output-names = "core";
+			#clock-cells = <0>;
+			u-boot,dm-pre-reloc;
+		};
+
+		dummy_spi: spi-clock {
+			compatible = "fixed-clock";
+			clock-frequency = <396000000>;
+			clock-output-names = "dummy_spi";
+			#clock-cells = <0>;
+			u-boot,dm-pre-reloc;
+		};
+
+		dummy_qspi0: qspi0-clock {
+			compatible = "fixed-clock";
+			clock-frequency = <792000000>;
+			clock-output-names = "dummy_qspi0";
+			#clock-cells = <0>;
+			u-boot,dm-pre-reloc;
+		};
+
+		dummy_uart_sclk: uart-sclk-clock {
+			compatible = "fixed-clock";
+			clock-frequency = <100000000>;
+			clock-output-names = "dummy_uart_sclk";
+			#clock-cells = <0>;
+			u-boot,dm-pre-reloc;
+		};
+
+		dummy_i2c_icclk: i2c-icclk-clock {
+			compatible = "fixed-clock";
+			clock-frequency = <50000000>;
+			clock-output-names = "dummy_i2c_icclk";
+			#clock-cells = <0>;
+			u-boot,dm-pre-reloc;
+		};
+
+		dummy_dpu_pixclk: dpu-pix-clock {
+			compatible = "fixed-clock";
+			clock-frequency = <74250000>;
+			clock-output-names = "dummy_dpu_pixclk";
+			#clock-cells = <0>;
+			u-boot,dm-pre-reloc;
+		};
+
+		dummy_dphy_refclk: dphy-ref-clock {
+			compatible = "fixed-clock";
+			clock-frequency = <24000000>;
+			clock-output-names = "dummy_dpu_refclk";
+			#clock-cells = <0>;
+			u-boot,dm-pre-reloc;
+		};
+
+		i2c0: i2c@ffe7f20000 {
+			compatible = "snps,designware-i2c";
+			reg = <0xff 0xe7f20000 0x0 0x4000>;
+			clocks = <&dummy_i2c_icclk>;
+			clock-frequency = <100000>;
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c1: i2c@ffe7f24000{
+			compatible = "snps,designware-i2c";
+			reg = <0xff 0xe7f24000 0x0 0x4000>;
+			clocks = <&dummy_i2c_icclk>;
+			clock-frequency = <100000>;
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c2: i2c@ffec00c000{
+			compatible = "snps,designware-i2c";
+			reg = <0xff 0xec00c000 0x0 0x4000>;
+			clocks = <&dummy_i2c_icclk>;
+			clock-frequency = <100000>;
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c3: i2c@ffec014000{
+			compatible = "snps,designware-i2c";
+			reg = <0xff 0xec014000 0x0 0x4000>;
+			clocks = <&dummy_i2c_icclk>;
+			clock-frequency = <100000>;
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c4: i2c@ffe7f28000{
+			compatible = "snps,designware-i2c";
+			reg = <0xff 0xe7f28000 0x0 0x4000>;
+			clocks = <&dummy_i2c_icclk>;
+			clock-frequency = <100000>;
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			pcal6408ahk_a: gpio@20 {
+				compatible = "nxp,pca9554";
+				reg = <0x20>;
+				gpio-controller;
+				#gpio-cells = <2>;
+			};
+		};
+
+		i2c5: i2c@fff7f2c000{
+			compatible = "snps,designware-i2c";
+			reg = <0xff 0xf7f2c000 0x0 0x4000>;
+			clocks = <&dummy_i2c_icclk>;
+			clock-frequency = <100000>;
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		serial@ffe7014000 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0xff 0xe7014000 0x0 0x400>;
+			clocks = <&dummy_uart_sclk>;
+			clock-frequency = <100000000>;
+			clock-names = "baudclk";
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			u-boot,dm-pre-reloc;
+		};
+
+		gmac0: ethernet@ffe7070000 {
+			compatible = "snps,dwmac";
+			reg = <0xff 0xe7070000 0x0 0x2000>;
+			clocks = <&dummy_apb>;
+			clock-names = "stmmaceth";
+			snps,pbl = <32>;
+			snps,fixed-burst;
+
+			phy-mode = "rgmii-id";
+			phy-handle = <&phy_88E1111_a>;
+			status = "okay";
+			mdio0 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "snps,dwmac-mdio";
+
+				phy_88E1111_a: ethernet-phy@1 {
+					reg = <0x1>;
+				};
+
+				phy_88E1111_b: ethernet-phy@2 {
+					reg = <0x2>;
+				};
+			};
+		};
+
+		gmac1: ethernet@ffe7060000 {
+			compatible = "snps,dwmac";
+			reg = <0xff 0xe7060000 0x0 0x2000>;
+			clocks = <&dummy_apb>;
+			clock-names = "stmmaceth";
+			snps,pbl = <32>;
+			snps,fixed-burst;
+			phy-mode = "rgmii-id";
+			phy-handle = <&phy_88E1111_b>;
+			status = "okay";
+		};
+
+		emmc: sdhci@ffe7080000 {
+			compatible = "snps,dwcmshc-sdhci";
+			reg = <0xff 0xe7080000 0x0 0x10000>;
+			index = <0x0>;
+			clocks = <&dummy_ahb>;
+			clock-frequency = <198000000>;
+			clock-names = "core";
+			max-frequency = <198000000>;
+			sdhci-caps-mask = <0x0 0x1000000>;
+			mmc-hs400-1_8v;
+			non-removable;
+			no-sdio;
+			no-sd;
+			bus-width = <8>;
+			voltage= "1.8v";
+			pull_up;
+			io_fixed_1v8;
+			fifo-mode;
+			u-boot,dm-pre-reloc;
+		};
+
+		sdhci0: sd@ffe7090000 {
+			compatible = "snps,dwcmshc-sdhci";
+			reg = <0xff 0xe7090000 0x0 0x10000>;
+			index = <0x1>;
+			clocks = <&dummy_ahb>;
+			clock-frequency = <198000000>;
+			max-frequency = <198000000>;
+			sd-uhs-sdr104;
+			pull_up;
+			clock-names = "core";
+			bus-width = <4>;
+			voltage= "3.3v";
+		};
+
+		qspi0: spi@ffea000000 {
+			compatible = "snps,dw-apb-ssi-quad";
+			reg = <0xff 0xea000000 0x0 0x1000>;
+			clocks = <&dummy_qspi0>;
+			num-cs = <1>;
+			cs-gpio = <&gpio2_porta 3 0>; // GPIO_ACTIVE_HIGH: 0
+			spi-max-frequency = <100000000>;
+			#address-cells = <1>;
+			#size-cells =<0>;
+			spi-flash@0 {
+				#address-cells = <1>;
+				#size-cells = <1>;
+				compatible = "spi-nand";
+				spi-tx-bus-width = <4>;
+				spi-rx-bus-width = <4>;
+				reg = <0>;
+			};
+		};
+
+		qspi1: spi@fff8000000 {
+			compatible = "snps,dw-apb-ssi-quad";
+			reg = <0xff 0xf8000000 0x0 0x1000>;
+			clocks = <&dummy_spi>;
+			num-cs = <1>;
+			cs-gpio = <&gpio0_porta 1 0>; // GPIO_ACTIVE_HIGH: 0
+			spi-max-frequency = <66000000>;
+			#address-cells = <1>;
+			#size-cells =<0>;
+			spi-flash@0 {
+				#address-cells = <1>;
+				#size-cells = <1>;
+				compatible = "spi-nand";
+				spi-tx-bus-width = <4>;
+				spi-rx-bus-width = <4>;
+				reg = <0>;
+			};
+		};
+
+		spi0: spi@ffe700c000 {
+			compatible = "snps,dw-apb-ssi";
+			reg = <0xff 0xe700c000 0x0 0x1000>;
+			clocks = <&dummy_spi>;
+			cs-gpio = <&gpio2_porta 15 0>;
+			spi-max-frequency = <100000000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			flash@0 {
+				compatible = "jedec,spi-nor";
+				reg = <0>;
+				spi-max-frequency = <40000000>;
+			};
+		};
+
+		gpio2: gpio@ffe7f34000 {
+			compatible = "snps,dw-apb-gpio";
+			reg = <0xff 0xe7f34000 0x0 0x1000>;
+			clocks = <&dummy_apb>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			gpio2_porta: gpio-controller@0 {
+				compatible = "snps,dw-apb-gpio-port";
+				gpio-controller;
+				#gpio-cells = <2>;
+				snps,nr-gpios = <32>;
+				reg = <0>;
+			};
+		};
+
+		gpio0: gpio@ffec005000 {
+			compatible = "snps,dw-apb-gpio";
+			reg = <0xff 0xec005000 0x0 0x1000>;
+			clocks = <&dummy_apb>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			gpio0_porta: gpio-controller@0 {
+				compatible = "snps,dw-apb-gpio-port";
+				gpio-controller;
+				#gpio-cells = <2>;
+				snps,nr-gpios = <32>;
+				reg = <0>;
+			};
+		};
+
+		gpio1: gpio@ffec006000 {
+			compatible = "snps,dw-apb-gpio";
+			reg = <0xff 0xec006000 0x0 0x1000>;
+			clocks = <&dummy_apb>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			gpio1_porta: gpio-controller@0 {
+				compatible = "snps,dw-apb-gpio-port";
+				gpio-controller;
+				#gpio-cells = <2>;
+				snps,nr-gpios = <32>;
+				reg = <0>;
+			};
+		};
+
+		pwm: pwm@ffec01c000 {
+			compatible = "thead,pwm-light";
+			reg = <0xff 0xec01c000 0x0 0x4000>;
+			#pwm-cells = <2>;
+		};
+
+		dsi_regs: dsi-controller@ffef500000 {
+			compatible = "thead,light-dsi-regs", "syscon";
+			reg = <0xff 0xef500000 0x0 0x10000>;
+			status = "okay";
+		};
+
+		vosys_regs: vosys@ffef528000 {
+			compatible = "thead,light-vo-subsys", "syscon";
+			reg = <0xff 0xef528000 0x0 0x1000>;
+			status = "okay";
+		};
+
+		dpu: dc8200@ffef600000 {
+			compatible = "verisilicon,dc8200";
+			reg = <0xff 0xef600000 0x0 0x100>;
+		};
+
+		axiscr {
+			compatible = "thead,axiscr";
+			reg = <0xff 0xff004000 0x0 0x1000>;
+			lock-read = "okay";
+			lock-write = "okay";
+			#address-cells = <2>;
+			#size-cells = <2>;
+			u-boot,dm-pre-reloc;
+			axiscr0: axisrc@0 {
+				device_type = "axiscr";
+				region = <0x00 0x00000000 0x00 0x80000000>; // 4KB align
+				status = "disabled";
+				#address-cells = <2>;
+				#size-cells = <2>;
+				u-boot,dm-pre-reloc;
+			};
+			axiscr1: axisrc@1 {
+				device_type = "axiscr";
+				region = <0x00 0x80000000 0x00 0x80000000>; // 4KB align
+				status = "disabled";
+				#address-cells = <2>;
+				#size-cells = <2>;
+				u-boot,dm-pre-reloc;
+			};
+			axiscr2: axisrc@2 {
+				device_type = "axiscr";
+				region = <0x01 0x00000000 0x00 0x80000000>; // 4KB align
+				status = "disabled";
+				#address-cells = <2>;
+				#size-cells = <2>;
+				u-boot,dm-pre-reloc;
+			};
+		};
+
+		axiparity {
+			compatible = "thead,axiparity";
+			reg = <0xff 0xff00c000 0x0 0x1000>;
+			lock = "okay";
+			#address-cells = <2>;
+			#size-cells = <2>;
+			u-boot,dm-pre-reloc;
+			axiparity0: axiparity@0 {
+				device_type = "axiparity";
+				region = <0x00 0x00000000 0x01 0x0000000>; // 4KB align
+				status = "disabled";
+				#address-cells = <2>;
+				#size-cells = <2>;
+				u-boot,dm-pre-reloc;
+			};
+			axiparity1: axiparity@1 {
+				device_type = "axiparity";
+				region = <0x01 0x00000000 0x01 0x00000000>; // 4KB align
+				status = "disabled";
+				#address-cells = <2>;
+				#size-cells = <2>;
+				u-boot,dm-pre-reloc;
+			};
+		};
+
+		dsi_bridge: dsi-bridge {
+			compatible = "thead,light-dsi-bridge";
+			clocks = <&dummy_dpu_pixclk>;
+			clock-names = "pix-clk";
+			phys = <&dsi_dphy>;
+			phy-names = "dphy";
+		};
+
+		dsi_host: dsi-host {
+			compatible = "synopsys,dw-mipi-dsi";
+			regmap = <&dsi_regs>;
+			status = "okay";
+		};
+
+		dsi_dphy: dsi-dphy {
+			compatible = "synopsys,dw-dphy";
+			regmap = <&dsi_regs>;
+			vosys-regmap = <&vosys_regs>;
+			clocks = <&dummy_dpu_pixclk>, <&dummy_dphy_refclk>;
+			clock-names = "pix-clk", "ref-clk";
+			#phy-cells = <0>;
+			status = "okay";
+		};
+
+		lcd_backlight: pwm-backlight {
+			compatible = "pwm-backlight";
+			pwms = <&pwm 0 5000000>;
+			brightness-levels = <0 4 8 16 32 64 128 255>;
+			default-brightness-level = <7>;
+		};
+
+		ili9881c_panel {
+			compatible      = "ilitek,ili9881c";
+			backlight       = <&lcd_backlight>;
+			reset-gpios     = <&gpio1_porta 5 1>;   /* active low  */
+			lcd-en-gpios    = <&pcal6408ahk_a 2 0>; /* active high */
+			lcd-bias-en-gpios = <&pcal6408ahk_a 4 0>;/* active high */
+		};
+	};
+
+	chosen {
+		bootargs = "console=ttyS0,115200";
+		stdout-path = "/soc/serial@ffe7014000:115200";
+	};
+};

arch/riscv/dts/light-a-val.dts

@@ -39,6 +39,12 @@
 		ranges;
 		u-boot,dm-pre-reloc;
 
+		intc: interrupt-controller@ffd8000000 {
+			compatible = "riscv,plic0";
+			reg = <0xff 0xd8000000 0x0 0x04000000>;
+			status = "disabled";
+		};
+
 		dummy_apb: apb-clock {
 			compatible = "fixed-clock";
 			clock-frequency = <62500000>;
@@ -300,8 +306,8 @@
 			spi-max-frequency = <100000000>;
 			#address-cells = <1>;
 			#size-cells = <0>;
-			flash@0 {
-				compatible = "jedec,spi-nor";
+			tpm@0{
+				compatible = "z32h330tc,z32h330tc-spi";
 				reg = <0>;
 				spi-max-frequency = <40000000>;
 			};

arch/riscv/dts/light-b-power.dts

@@ -0,0 +1,478 @@
+/dts-v1/;
+/ {
+	model = "T-HEAD c910 light";
+	compatible = "thead,c910_light";
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	memory@0 {
+		device_type = "memory";
+		reg = <0x0 0xc0000000 0x0 0x40000000>;
+	};
+
+	aliases {
+		spi0 = &spi0;
+		spi1 = &qspi0;
+		spi2 = &qspi1;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		timebase-frequency = <3000000>;
+		u-boot,dm-pre-reloc;
+		cpu@0 {
+			device_type = "cpu";
+			reg = <0>;
+			status = "okay";
+			compatible = "riscv";
+			riscv,isa = "rv64imafdcvsu";
+			mmu-type = "riscv,sv39";
+			u-boot,dm-pre-reloc;
+		};
+	};
+
+	soc {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		compatible = "simple-bus";
+		ranges;
+		u-boot,dm-pre-reloc;
+
+		dummy_apb: apb-clock {
+			compatible = "fixed-clock";
+			clock-frequency = <62500000>;
+			clock-output-names = "dummy_apb";
+			#clock-cells = <0>;
+			u-boot,dm-pre-reloc;
+		};
+
+		dummy_ahb: ahb-clock {
+			compatible = "fixed-clock";
+			clock-frequency = <250000000>;
+			clock-output-names = "core";
+			#clock-cells = <0>;
+			u-boot,dm-pre-reloc;
+		};
+
+		dummy_spi: spi-clock {
+			compatible = "fixed-clock";
+			clock-frequency = <396000000>;
+			clock-output-names = "dummy_spi";
+			#clock-cells = <0>;
+			u-boot,dm-pre-reloc;
+		};
+
+		dummy_qspi0: qspi0-clock {
+			compatible = "fixed-clock";
+			clock-frequency = <792000000>;
+			clock-output-names = "dummy_qspi0";
+			#clock-cells = <0>;
+			u-boot,dm-pre-reloc;
+		};
+
+		dummy_uart_sclk: uart-sclk-clock {
+			compatible = "fixed-clock";
+			clock-frequency = <100000000>;
+			clock-output-names = "dummy_uart_sclk";
+			#clock-cells = <0>;
+			u-boot,dm-pre-reloc;
+		};
+
+		dummy_i2c_icclk: i2c-icclk-clock {
+			compatible = "fixed-clock";
+			clock-frequency = <50000000>;
+			clock-output-names = "dummy_i2c_icclk";
+			#clock-cells = <0>;
+			u-boot,dm-pre-reloc;
+		};
+
+		dummy_dpu_pixclk: dpu-pix-clock {
+			compatible = "fixed-clock";
+			clock-frequency = <74250000>;
+			clock-output-names = "dummy_dpu_pixclk";
+			#clock-cells = <0>;
+			u-boot,dm-pre-reloc;
+		};
+
+		dummy_dphy_refclk: dphy-ref-clock {
+			compatible = "fixed-clock";
+			clock-frequency = <24000000>;
+			clock-output-names = "dummy_dpu_refclk";
+			#clock-cells = <0>;
+			u-boot,dm-pre-reloc;
+		};
+
+		i2c0: i2c@ffe7f20000 {
+			compatible = "snps,designware-i2c";
+			reg = <0xff 0xe7f20000 0x0 0x4000>;
+			clocks = <&dummy_i2c_icclk>;
+			clock-frequency = <100000>;
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c1: i2c@ffe7f24000{
+			compatible = "snps,designware-i2c";
+			reg = <0xff 0xe7f24000 0x0 0x4000>;
+			clocks = <&dummy_i2c_icclk>;
+			clock-frequency = <100000>;
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c2: i2c@ffec00c000{
+			compatible = "snps,designware-i2c";
+			reg = <0xff 0xec00c000 0x0 0x4000>;
+			clocks = <&dummy_i2c_icclk>;
+			clock-frequency = <100000>;
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c3: i2c@ffec014000{
+			compatible = "snps,designware-i2c";
+			reg = <0xff 0xec014000 0x0 0x4000>;
+			clocks = <&dummy_i2c_icclk>;
+			clock-frequency = <100000>;
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c4: i2c@ffe7f28000{
+			compatible = "snps,designware-i2c";
+			reg = <0xff 0xe7f28000 0x0 0x4000>;
+			clocks = <&dummy_i2c_icclk>;
+			clock-frequency = <100000>;
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c5: i2c@fff7f2c000{
+			compatible = "snps,designware-i2c";
+			reg = <0xff 0xf7f2c000 0x0 0x4000>;
+			clocks = <&dummy_i2c_icclk>;
+			clock-frequency = <100000>;
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		serial@ffe7014000 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0xff 0xe7014000 0x0 0x400>;
+			clocks = <&dummy_uart_sclk>;
+			clock-frequency = <100000000>;
+			clock-names = "baudclk";
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			u-boot,dm-pre-reloc;
+		};
+
+		gmac0: ethernet@ffe7070000 {
+			compatible = "snps,dwmac";
+			reg = <0xff 0xe7070000 0x0 0x2000>;
+			clocks = <&dummy_apb>;
+			clock-names = "stmmaceth";
+			snps,pbl = <32>;
+			snps,fixed-burst;
+
+			phy-mode = "rgmii-id";
+			phy-handle = <&phy_88E1111_a>;
+			status = "okay";
+			mdio0 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "snps,dwmac-mdio";
+
+				phy_88E1111_a: ethernet-phy@1 {
+					reg = <0x1>;
+				};
+
+				phy_88E1111_b: ethernet-phy@2 {
+					reg = <0x2>;
+				};
+			};
+		};
+
+		gmac1: ethernet@ffe7060000 {
+			compatible = "snps,dwmac";
+			reg = <0xff 0xe7060000 0x0 0x2000>;
+			clocks = <&dummy_apb>;
+			clock-names = "stmmaceth";
+			snps,pbl = <32>;
+			snps,fixed-burst;
+			phy-mode = "rgmii-id";
+			phy-handle = <&phy_88E1111_b>;
+			status = "disabled";
+		};
+
+		emmc: sdhci@ffe7080000 {
+			compatible = "snps,dwcmshc-sdhci";
+			reg = <0xff 0xe7080000 0x0 0x10000>;
+			index = <0x0>;
+			clocks = <&dummy_ahb>;
+			clock-frequency = <198000000>;
+			clock-names = "core";
+			max-frequency = <198000000>;
+			sdhci-caps-mask = <0x0 0x1000000>;
+			mmc-hs400-1_8v;
+			non-removable;
+			no-sdio;
+			no-sd;
+			bus-width = <8>;
+			voltage= "1.8v";
+			pull_up;
+			io_fixed_1v8;
+			fifo-mode;
+			u-boot,dm-pre-reloc;
+		};
+
+		sdhci0: sd@ffe7090000 {
+			compatible = "snps,dwcmshc-sdhci";
+			reg = <0xff 0xe7090000 0x0 0x10000>;
+			index = <0x1>;
+			clocks = <&dummy_ahb>;
+			clock-frequency = <198000000>;
+			max-frequency = <198000000>;
+			sd-uhs-sdr104;
+			pull_up;
+			clock-names = "core";
+			bus-width = <4>;
+			voltage= "3.3v";
+		};
+
+		qspi0: spi@ffea000000 {
+			compatible = "snps,dw-apb-ssi-quad";
+			reg = <0xff 0xea000000 0x0 0x1000>;
+			clocks = <&dummy_qspi0>;
+			num-cs = <1>;
+			cs-gpio = <&gpio2_porta 3 0>; // GPIO_ACTIVE_HIGH: 0
+			spi-max-frequency = <100000000>;
+			#address-cells = <1>;
+			#size-cells =<0>;
+			status = "disabled";
+			spi-flash@0 {
+				#address-cells = <1>;
+				#size-cells = <1>;
+				compatible = "spi-nand";
+				spi-tx-bus-width = <4>;
+				spi-rx-bus-width = <4>;
+				reg = <0>;
+			};
+		};
+
+		qspi1: spi@fff8000000 {
+			compatible = "snps,dw-apb-ssi-quad";
+			reg = <0xff 0xf8000000 0x0 0x1000>;
+			clocks = <&dummy_spi>;
+			num-cs = <1>;
+			cs-gpio = <&gpio0_porta 1 0>; // GPIO_ACTIVE_HIGH: 0
+			spi-max-frequency = <66000000>;
+			#address-cells = <1>;
+			#size-cells =<0>;
+			status = "disabled";
+			spi-flash@0 {
+				#address-cells = <1>;
+				#size-cells = <1>;
+				compatible = "spi-nand";
+				spi-tx-bus-width = <4>;
+				spi-rx-bus-width = <4>;
+				reg = <0>;
+			};
+		};
+
+		spi0: spi@ffe700c000 {
+			compatible = "snps,dw-apb-ssi";
+			reg = <0xff 0xe700c000 0x0 0x1000>;
+			clocks = <&dummy_spi>;
+			cs-gpio = <&gpio2_porta 15 0>;
+			spi-max-frequency = <100000000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+			flash@0 {
+				compatible = "jedec,spi-nor";
+				reg = <0>;
+				spi-max-frequency = <40000000>;
+			};
+		};
+
+		gpio2: gpio@ffe7f34000 {
+			compatible = "snps,dw-apb-gpio";
+			reg = <0xff 0xe7f34000 0x0 0x1000>;
+			clocks = <&dummy_apb>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			gpio2_porta: gpio-controller@0 {
+				compatible = "snps,dw-apb-gpio-port";
+				gpio-controller;
+				#gpio-cells = <2>;
+				snps,nr-gpios = <32>;
+				reg = <0>;
+			};
+		};
+
+		gpio0: gpio@ffec005000 {
+			compatible = "snps,dw-apb-gpio";
+			reg = <0xff 0xec005000 0x0 0x1000>;
+			clocks = <&dummy_apb>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			gpio0_porta: gpio-controller@0 {
+				compatible = "snps,dw-apb-gpio-port";
+				gpio-controller;
+				#gpio-cells = <2>;
+				snps,nr-gpios = <32>;
+				reg = <0>;
+			};
+		};
+
+		gpio1: gpio@ffec006000 {
+			compatible = "snps,dw-apb-gpio";
+			reg = <0xff 0xec006000 0x0 0x1000>;
+			clocks = <&dummy_apb>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			gpio1_porta: gpio-controller@0 {
+				compatible = "snps,dw-apb-gpio-port";
+				gpio-controller;
+				#gpio-cells = <2>;
+				snps,nr-gpios = <32>;
+				reg = <0>;
+			};
+		};
+
+		pwm: pwm@ffec01c000 {
+			compatible = "thead,pwm-light";
+			reg = <0xff 0xec01c000 0x0 0x4000>;
+			#pwm-cells = <2>;
+		};
+
+		dsi_regs: dsi-controller@ffef500000 {
+			compatible = "thead,light-dsi-regs", "syscon";
+			reg = <0xff 0xef500000 0x0 0x10000>;
+			status = "okay";
+		};
+
+		vosys_regs: vosys@ffef528000 {
+			compatible = "thead,light-vo-subsys", "syscon";
+			reg = <0xff 0xef528000 0x0 0x1000>;
+			status = "okay";
+		};
+
+		dpu: dc8200@ffef600000 {
+			compatible = "verisilicon,dc8200";
+			reg = <0xff 0xef600000 0x0 0x100>;
+		};
+
+		axiscr {
+			compatible = "thead,axiscr";
+			reg = <0xff 0xff004000 0x0 0x1000>;
+			lock-read = "okay";
+			lock-write = "okay";
+			#address-cells = <2>;
+			#size-cells = <2>;
+			u-boot,dm-pre-reloc;
+			axiscr0: axisrc@0 {
+				device_type = "axiscr";
+				region = <0x00 0x00000000 0x00 0x80000000>; // 4KB align
+				status = "disabled";
+				#address-cells = <2>;
+				#size-cells = <2>;
+				u-boot,dm-pre-reloc;
+			};
+			axiscr1: axisrc@1 {
+				device_type = "axiscr";
+				region = <0x00 0x80000000 0x00 0x80000000>; // 4KB align
+				status = "disabled";
+				#address-cells = <2>;
+				#size-cells = <2>;
+				u-boot,dm-pre-reloc;
+			};
+			axiscr2: axisrc@2 {
+				device_type = "axiscr";
+				region = <0x01 0x00000000 0x00 0x80000000>; // 4KB align
+				status = "disabled";
+				#address-cells = <2>;
+				#size-cells = <2>;
+				u-boot,dm-pre-reloc;
+			};
+		};
+
+		axiparity {
+			compatible = "thead,axiparity";
+			reg = <0xff 0xff00c000 0x0 0x1000>;
+			lock = "okay";
+			#address-cells = <2>;
+			#size-cells = <2>;
+			u-boot,dm-pre-reloc;
+			axiparity0: axiparity@0 {
+				device_type = "axiparity";
+				region = <0x00 0x00000000 0x01 0x0000000>; // 4KB align
+				status = "disabled";
+				#address-cells = <2>;
+				#size-cells = <2>;
+				u-boot,dm-pre-reloc;
+			};
+			axiparity1: axiparity@1 {
+				device_type = "axiparity";
+				region = <0x01 0x00000000 0x01 0x00000000>; // 4KB align
+				status = "disabled";
+				#address-cells = <2>;
+				#size-cells = <2>;
+				u-boot,dm-pre-reloc;
+			};
+		};
+
+		dsi_bridge: dsi-bridge {
+			compatible = "thead,light-dsi-bridge";
+			clocks = <&dummy_dpu_pixclk>;
+			clock-names = "pix-clk";
+			phys = <&dsi_dphy>;
+			phy-names = "dphy";
+		};
+
+		dsi_host: dsi-host {
+			compatible = "synopsys,dw-mipi-dsi";
+			regmap = <&dsi_regs>;
+			status = "okay";
+		};
+
+		dsi_dphy: dsi-dphy {
+			compatible = "synopsys,dw-dphy";
+			regmap = <&dsi_regs>;
+			vosys-regmap = <&vosys_regs>;
+			clocks = <&dummy_dpu_pixclk>, <&dummy_dphy_refclk>;
+			clock-names = "pix-clk", "ref-clk";
+			#phy-cells = <0>;
+			status = "okay";
+		};
+
+		lcd_backlight: pwm-backlight {
+			compatible = "pwm-backlight";
+			pwms = <&pwm 0 5000000>;
+			brightness-levels = <0 4 8 16 32 64 128 255>;
+			default-brightness-level = <7>;
+		};
+
+		ili9881c_panel {
+			compatible      = "ilitek,ili9881c";
+			backlight       = <&lcd_backlight>;
+			reset-gpios     = <&gpio1_porta 5 1>;   /* active low  */
+			lcd-en-gpios    = <&gpio1_porta 9 0>; /* active high */
+			lcd-bias-en-gpios = <&gpio1_porta 10 0>;/* active high */
+		};
+	};
+
+	chosen {
+		bootargs = "console=ttyS0,115200";
+		stdout-path = "/soc/serial@ffe7014000:115200";
+	};
+};

arch/riscv/dts/light-b-product.dts

@@ -151,13 +151,6 @@
 
 			#address-cells = <1>;
 			#size-cells = <0>;
-
-			pcal6408ahk_a: gpio@20 {
-				compatible = "nxp,pca9554";
-				reg = <0x20>;
-				gpio-controller;
-				#gpio-cells = <2>;
-			};
 		};
 
 		i2c5: i2c@fff7f2c000{

arch/riscv/dts/light-b-ref.dts

@@ -0,0 +1,485 @@
+/dts-v1/;
+/ {
+	model = "T-HEAD c910 light";
+	compatible = "thead,c910_light";
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	memory@0 {
+		device_type = "memory";
+		reg = <0x0 0xc0000000 0x0 0x40000000>;
+	};
+
+	aliases {
+		spi0 = &spi0;
+		spi1 = &qspi0;
+		spi2 = &qspi1;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		timebase-frequency = <3000000>;
+		u-boot,dm-pre-reloc;
+		cpu@0 {
+			device_type = "cpu";
+			reg = <0>;
+			status = "okay";
+			compatible = "riscv";
+			riscv,isa = "rv64imafdcvsu";
+			mmu-type = "riscv,sv39";
+			u-boot,dm-pre-reloc;
+		};
+	};
+
+	soc {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		compatible = "simple-bus";
+		ranges;
+		u-boot,dm-pre-reloc;
+
+		dummy_apb: apb-clock {
+			compatible = "fixed-clock";
+			clock-frequency = <62500000>;
+			clock-output-names = "dummy_apb";
+			#clock-cells = <0>;
+			u-boot,dm-pre-reloc;
+		};
+
+		dummy_ahb: ahb-clock {
+			compatible = "fixed-clock";
+			clock-frequency = <250000000>;
+			clock-output-names = "core";
+			#clock-cells = <0>;
+			u-boot,dm-pre-reloc;
+		};
+
+		dummy_spi: spi-clock {
+			compatible = "fixed-clock";
+			clock-frequency = <396000000>;
+			clock-output-names = "dummy_spi";
+			#clock-cells = <0>;
+			u-boot,dm-pre-reloc;
+		};
+
+		dummy_qspi0: qspi0-clock {
+			compatible = "fixed-clock";
+			clock-frequency = <792000000>;
+			clock-output-names = "dummy_qspi0";
+			#clock-cells = <0>;
+			u-boot,dm-pre-reloc;
+		};
+
+		dummy_uart_sclk: uart-sclk-clock {
+			compatible = "fixed-clock";
+			clock-frequency = <100000000>;
+			clock-output-names = "dummy_uart_sclk";
+			#clock-cells = <0>;
+			u-boot,dm-pre-reloc;
+		};
+
+		dummy_i2c_icclk: i2c-icclk-clock {
+			compatible = "fixed-clock";
+			clock-frequency = <50000000>;
+			clock-output-names = "dummy_i2c_icclk";
+			#clock-cells = <0>;
+			u-boot,dm-pre-reloc;
+		};
+
+		dummy_dpu_pixclk: dpu-pix-clock {
+			compatible = "fixed-clock";
+			clock-frequency = <74250000>;
+			clock-output-names = "dummy_dpu_pixclk";
+			#clock-cells = <0>;
+			u-boot,dm-pre-reloc;
+		};
+
+		dummy_dphy_refclk: dphy-ref-clock {
+			compatible = "fixed-clock";
+			clock-frequency = <24000000>;
+			clock-output-names = "dummy_dpu_refclk";
+			#clock-cells = <0>;
+			u-boot,dm-pre-reloc;
+		};
+
+		i2c0: i2c@ffe7f20000 {
+			compatible = "snps,designware-i2c";
+			reg = <0xff 0xe7f20000 0x0 0x4000>;
+			clocks = <&dummy_i2c_icclk>;
+			clock-frequency = <100000>;
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c1: i2c@ffe7f24000{
+			compatible = "snps,designware-i2c";
+			reg = <0xff 0xe7f24000 0x0 0x4000>;
+			clocks = <&dummy_i2c_icclk>;
+			clock-frequency = <100000>;
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c2: i2c@ffec00c000{
+			compatible = "snps,designware-i2c";
+			reg = <0xff 0xec00c000 0x0 0x4000>;
+			clocks = <&dummy_i2c_icclk>;
+			clock-frequency = <100000>;
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c3: i2c@ffec014000{
+			compatible = "snps,designware-i2c";
+			reg = <0xff 0xec014000 0x0 0x4000>;
+			clocks = <&dummy_i2c_icclk>;
+			clock-frequency = <100000>;
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c4: i2c@ffe7f28000{
+			compatible = "snps,designware-i2c";
+			reg = <0xff 0xe7f28000 0x0 0x4000>;
+			clocks = <&dummy_i2c_icclk>;
+			clock-frequency = <100000>;
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			pcal6408ahk_a: gpio@20 {
+				compatible = "nxp,pca9554";
+				reg = <0x20>;
+				gpio-controller;
+				#gpio-cells = <2>;
+			};
+		};
+
+		i2c5: i2c@fff7f2c000{
+			compatible = "snps,designware-i2c";
+			reg = <0xff 0xf7f2c000 0x0 0x4000>;
+			clocks = <&dummy_i2c_icclk>;
+			clock-frequency = <100000>;
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		serial@ffe7014000 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0xff 0xe7014000 0x0 0x400>;
+			clocks = <&dummy_uart_sclk>;
+			clock-frequency = <100000000>;
+			clock-names = "baudclk";
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			u-boot,dm-pre-reloc;
+		};
+
+		gmac0: ethernet@ffe7070000 {
+			compatible = "snps,dwmac";
+			reg = <0xff 0xe7070000 0x0 0x2000>;
+			clocks = <&dummy_apb>;
+			clock-names = "stmmaceth";
+			snps,pbl = <32>;
+			snps,fixed-burst;
+
+			phy-mode = "rgmii-id";
+			phy-handle = <&phy_88E1111_a>;
+			status = "okay";
+			mdio0 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "snps,dwmac-mdio";
+
+				phy_88E1111_a: ethernet-phy@1 {
+					reg = <0x1>;
+				};
+
+				phy_88E1111_b: ethernet-phy@2 {
+					reg = <0x2>;
+				};
+			};
+		};
+
+		gmac1: ethernet@ffe7060000 {
+			compatible = "snps,dwmac";
+			reg = <0xff 0xe7060000 0x0 0x2000>;
+			clocks = <&dummy_apb>;
+			clock-names = "stmmaceth";
+			snps,pbl = <32>;
+			snps,fixed-burst;
+			phy-mode = "rgmii-id";
+			phy-handle = <&phy_88E1111_b>;
+			status = "disabled";
+		};
+
+		emmc: sdhci@ffe7080000 {
+			compatible = "snps,dwcmshc-sdhci";
+			reg = <0xff 0xe7080000 0x0 0x10000>;
+			index = <0x0>;
+			clocks = <&dummy_ahb>;
+			clock-frequency = <198000000>;
+			clock-names = "core";
+			max-frequency = <198000000>;
+			sdhci-caps-mask = <0x0 0x1000000>;
+			mmc-hs400-1_8v;
+			non-removable;
+			no-sdio;
+			no-sd;
+			bus-width = <8>;
+			voltage= "1.8v";
+			pull_up;
+			io_fixed_1v8;
+			fifo-mode;
+			u-boot,dm-pre-reloc;
+		};
+
+		sdhci0: sd@ffe7090000 {
+			compatible = "snps,dwcmshc-sdhci";
+			reg = <0xff 0xe7090000 0x0 0x10000>;
+			index = <0x1>;
+			clocks = <&dummy_ahb>;
+			clock-frequency = <198000000>;
+			max-frequency = <198000000>;
+			sd-uhs-sdr104;
+			pull_up;
+			clock-names = "core";
+			bus-width = <4>;
+			voltage= "3.3v";
+		};
+
+		qspi0: spi@ffea000000 {
+			compatible = "snps,dw-apb-ssi-quad";
+			reg = <0xff 0xea000000 0x0 0x1000>;
+			clocks = <&dummy_qspi0>;
+			num-cs = <1>;
+			cs-gpio = <&gpio2_porta 3 0>; // GPIO_ACTIVE_HIGH: 0
+			spi-max-frequency = <100000000>;
+			#address-cells = <1>;
+			#size-cells =<0>;
+			status = "disabled";
+			spi-flash@0 {
+				#address-cells = <1>;
+				#size-cells = <1>;
+				compatible = "spi-nand";
+				spi-tx-bus-width = <4>;
+				spi-rx-bus-width = <4>;
+				reg = <0>;
+			};
+		};
+
+		qspi1: spi@fff8000000 {
+			compatible = "snps,dw-apb-ssi-quad";
+			reg = <0xff 0xf8000000 0x0 0x1000>;
+			clocks = <&dummy_spi>;
+			num-cs = <1>;
+			cs-gpio = <&gpio0_porta 1 0>; // GPIO_ACTIVE_HIGH: 0
+			spi-max-frequency = <66000000>;
+			#address-cells = <1>;
+			#size-cells =<0>;
+			status = "disabled";
+			spi-flash@0 {
+				#address-cells = <1>;
+				#size-cells = <1>;
+				compatible = "spi-nand";
+				spi-tx-bus-width = <4>;
+				spi-rx-bus-width = <4>;
+				reg = <0>;
+			};
+		};
+
+		spi0: spi@ffe700c000 {
+			compatible = "snps,dw-apb-ssi";
+			reg = <0xff 0xe700c000 0x0 0x1000>;
+			clocks = <&dummy_spi>;
+			cs-gpio = <&gpio2_porta 15 0>;
+			spi-max-frequency = <100000000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+			flash@0 {
+				compatible = "jedec,spi-nor";
+				reg = <0>;
+				spi-max-frequency = <40000000>;
+			};
+		};
+
+		gpio2: gpio@ffe7f34000 {
+			compatible = "snps,dw-apb-gpio";
+			reg = <0xff 0xe7f34000 0x0 0x1000>;
+			clocks = <&dummy_apb>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			gpio2_porta: gpio-controller@0 {
+				compatible = "snps,dw-apb-gpio-port";
+				gpio-controller;
+				#gpio-cells = <2>;
+				snps,nr-gpios = <32>;
+				reg = <0>;
+			};
+		};
+
+		gpio0: gpio@ffec005000 {
+			compatible = "snps,dw-apb-gpio";
+			reg = <0xff 0xec005000 0x0 0x1000>;
+			clocks = <&dummy_apb>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			gpio0_porta: gpio-controller@0 {
+				compatible = "snps,dw-apb-gpio-port";
+				gpio-controller;
+				#gpio-cells = <2>;
+				snps,nr-gpios = <32>;
+				reg = <0>;
+			};
+		};
+
+		gpio1: gpio@ffec006000 {
+			compatible = "snps,dw-apb-gpio";
+			reg = <0xff 0xec006000 0x0 0x1000>;
+			clocks = <&dummy_apb>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			gpio1_porta: gpio-controller@0 {
+				compatible = "snps,dw-apb-gpio-port";
+				gpio-controller;
+				#gpio-cells = <2>;
+				snps,nr-gpios = <32>;
+				reg = <0>;
+			};
+		};
+
+		pwm: pwm@ffec01c000 {
+			compatible = "thead,pwm-light";
+			reg = <0xff 0xec01c000 0x0 0x4000>;
+			#pwm-cells = <2>;
+		};
+
+		dsi_regs: dsi-controller@ffef500000 {
+			compatible = "thead,light-dsi-regs", "syscon";
+			reg = <0xff 0xef500000 0x0 0x10000>;
+			status = "okay";
+		};
+
+		vosys_regs: vosys@ffef528000 {
+			compatible = "thead,light-vo-subsys", "syscon";
+			reg = <0xff 0xef528000 0x0 0x1000>;
+			status = "okay";
+		};
+
+		dpu: dc8200@ffef600000 {
+			compatible = "verisilicon,dc8200";
+			reg = <0xff 0xef600000 0x0 0x100>;
+		};
+
+		axiscr {
+			compatible = "thead,axiscr";
+			reg = <0xff 0xff004000 0x0 0x1000>;
+			lock-read = "okay";
+			lock-write = "okay";
+			#address-cells = <2>;
+			#size-cells = <2>;
+			u-boot,dm-pre-reloc;
+			axiscr0: axisrc@0 {
+				device_type = "axiscr";
+				region = <0x00 0x00000000 0x00 0x80000000>; // 4KB align
+				status = "disabled";
+				#address-cells = <2>;
+				#size-cells = <2>;
+				u-boot,dm-pre-reloc;
+			};
+			axiscr1: axisrc@1 {
+				device_type = "axiscr";
+				region = <0x00 0x80000000 0x00 0x80000000>; // 4KB align
+				status = "disabled";
+				#address-cells = <2>;
+				#size-cells = <2>;
+				u-boot,dm-pre-reloc;
+			};
+			axiscr2: axisrc@2 {
+				device_type = "axiscr";
+				region = <0x01 0x00000000 0x00 0x80000000>; // 4KB align
+				status = "disabled";
+				#address-cells = <2>;
+				#size-cells = <2>;
+				u-boot,dm-pre-reloc;
+			};
+		};
+
+		axiparity {
+			compatible = "thead,axiparity";
+			reg = <0xff 0xff00c000 0x0 0x1000>;
+			lock = "okay";
+			#address-cells = <2>;
+			#size-cells = <2>;
+			u-boot,dm-pre-reloc;
+			axiparity0: axiparity@0 {
+				device_type = "axiparity";
+				region = <0x00 0x00000000 0x01 0x0000000>; // 4KB align
+				status = "disabled";
+				#address-cells = <2>;
+				#size-cells = <2>;
+				u-boot,dm-pre-reloc;
+			};
+			axiparity1: axiparity@1 {
+				device_type = "axiparity";
+				region = <0x01 0x00000000 0x01 0x00000000>; // 4KB align
+				status = "disabled";
+				#address-cells = <2>;
+				#size-cells = <2>;
+				u-boot,dm-pre-reloc;
+			};
+		};
+
+		dsi_bridge: dsi-bridge {
+			compatible = "thead,light-dsi-bridge";
+			clocks = <&dummy_dpu_pixclk>;
+			clock-names = "pix-clk";
+			phys = <&dsi_dphy>;
+			phy-names = "dphy";
+		};
+
+		dsi_host: dsi-host {
+			compatible = "synopsys,dw-mipi-dsi";
+			regmap = <&dsi_regs>;
+			status = "okay";
+		};
+
+		dsi_dphy: dsi-dphy {
+			compatible = "synopsys,dw-dphy";
+			regmap = <&dsi_regs>;
+			vosys-regmap = <&vosys_regs>;
+			clocks = <&dummy_dpu_pixclk>, <&dummy_dphy_refclk>;
+			clock-names = "pix-clk", "ref-clk";
+			#phy-cells = <0>;
+			status = "okay";
+		};
+
+		lcd_backlight: pwm-backlight {
+			compatible = "pwm-backlight";
+			pwms = <&pwm 0 5000000>;
+			brightness-levels = <0 4 8 16 32 64 128 255>;
+			default-brightness-level = <7>;
+		};
+
+		ili9881c_panel {
+			compatible      = "ilitek,ili9881c";
+			backlight       = <&lcd_backlight>;
+			reset-gpios     = <&gpio1_porta 5 1>;   /* active low  */
+			lcd-en-gpios    = <&gpio1_porta 9 0>; /* active high */
+			lcd-bias-en-gpios = <&gpio1_porta 10 0>;/* active high */
+		};
+	};
+
+	chosen {
+		bootargs = "console=ttyS0,115200";
+		stdout-path = "/soc/serial@ffe7014000:115200";
+	};
+};

arch/riscv/dts/light-beagle.dts

@@ -0,0 +1,488 @@
+/dts-v1/;
+/ {
+	model = "T-HEAD c910 light";
+	compatible = "thead,c910_light";
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	memory@0 {
+		device_type = "memory";
+		reg = <0x0 0xc0000000 0x0 0x40000000>;
+	};
+
+	aliases {
+		spi0 = &spi0;
+		spi1 = &qspi0;
+		spi2 = &qspi1;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		timebase-frequency = <3000000>;
+		u-boot,dm-pre-reloc;
+		cpu@0 {
+			device_type = "cpu";
+			reg = <0>;
+			status = "okay";
+			compatible = "riscv";
+			riscv,isa = "rv64imafdcvsu";
+			mmu-type = "riscv,sv39";
+			u-boot,dm-pre-reloc;
+		};
+	};
+
+	soc {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		compatible = "simple-bus";
+		ranges;
+		u-boot,dm-pre-reloc;
+
+		intc: interrupt-controller@ffd8000000 {
+			compatible = "riscv,plic0";
+			reg = <0xff 0xd8000000 0x0 0x04000000>;
+			status = "disabled";
+		};
+
+		dummy_apb: apb-clock {
+			compatible = "fixed-clock";
+			clock-frequency = <62500000>;
+			clock-output-names = "dummy_apb";
+			#clock-cells = <0>;
+			u-boot,dm-pre-reloc;
+		};
+
+		dummy_ahb: ahb-clock {
+			compatible = "fixed-clock";
+			clock-frequency = <250000000>;
+			clock-output-names = "core";
+			#clock-cells = <0>;
+			u-boot,dm-pre-reloc;
+		};
+
+		dummy_spi: spi-clock {
+			compatible = "fixed-clock";
+			clock-frequency = <396000000>;
+			clock-output-names = "dummy_spi";
+			#clock-cells = <0>;
+			u-boot,dm-pre-reloc;
+		};
+
+		dummy_qspi0: qspi0-clock {
+			compatible = "fixed-clock";
+			clock-frequency = <792000000>;
+			clock-output-names = "dummy_qspi0";
+			#clock-cells = <0>;
+			u-boot,dm-pre-reloc;
+		};
+
+		dummy_uart_sclk: uart-sclk-clock {
+			compatible = "fixed-clock";
+			clock-frequency = <100000000>;
+			clock-output-names = "dummy_uart_sclk";
+			#clock-cells = <0>;
+			u-boot,dm-pre-reloc;
+		};
+
+		dummy_i2c_icclk: i2c-icclk-clock {
+			compatible = "fixed-clock";
+			clock-frequency = <50000000>;
+			clock-output-names = "dummy_i2c_icclk";
+			#clock-cells = <0>;
+			u-boot,dm-pre-reloc;
+		};
+
+		dummy_dpu_pixclk: dpu-pix-clock {
+			compatible = "fixed-clock";
+			clock-frequency = <74250000>;
+			clock-output-names = "dummy_dpu_pixclk";
+			#clock-cells = <0>;
+			u-boot,dm-pre-reloc;
+		};
+
+		dummy_dphy_refclk: dphy-ref-clock {
+			compatible = "fixed-clock";
+			clock-frequency = <24000000>;
+			clock-output-names = "dummy_dpu_refclk";
+			#clock-cells = <0>;
+			u-boot,dm-pre-reloc;
+		};
+
+		i2c0: i2c@ffe7f20000 {
+			compatible = "snps,designware-i2c";
+			reg = <0xff 0xe7f20000 0x0 0x4000>;
+			clocks = <&dummy_i2c_icclk>;
+			clock-frequency = <100000>;
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c1: i2c@ffe7f24000{
+			compatible = "snps,designware-i2c";
+			reg = <0xff 0xe7f24000 0x0 0x4000>;
+			clocks = <&dummy_i2c_icclk>;
+			clock-frequency = <100000>;
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c2: i2c@ffec00c000{
+			compatible = "snps,designware-i2c";
+			reg = <0xff 0xec00c000 0x0 0x4000>;
+			clocks = <&dummy_i2c_icclk>;
+			clock-frequency = <100000>;
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c3: i2c@ffec014000{
+			compatible = "snps,designware-i2c";
+			reg = <0xff 0xec014000 0x0 0x4000>;
+			clocks = <&dummy_i2c_icclk>;
+			clock-frequency = <100000>;
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c4: i2c@ffe7f28000{
+			compatible = "snps,designware-i2c";
+			reg = <0xff 0xe7f28000 0x0 0x4000>;
+			clocks = <&dummy_i2c_icclk>;
+			clock-frequency = <100000>;
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			pcal6408ahk_a: gpio@20 {
+				compatible = "nxp,pca9554";
+				reg = <0x20>;
+				gpio-controller;
+				#gpio-cells = <2>;
+			};
+		};
+
+		i2c5: i2c@fff7f2c000{
+			compatible = "snps,designware-i2c";
+			reg = <0xff 0xf7f2c000 0x0 0x4000>;
+			clocks = <&dummy_i2c_icclk>;
+			clock-frequency = <100000>;
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		serial@ffe7014000 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0xff 0xe7014000 0x0 0x400>;
+			clocks = <&dummy_uart_sclk>;
+			clock-frequency = <100000000>;
+			clock-names = "baudclk";
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			u-boot,dm-pre-reloc;
+		};
+
+		gmac0: ethernet@ffe7070000 {
+			compatible = "snps,dwmac";
+			reg = <0xff 0xe7070000 0x0 0x2000>;
+			clocks = <&dummy_apb>;
+			clock-names = "stmmaceth";
+			snps,pbl = <32>;
+			snps,fixed-burst;
+
+			phy-mode = "rgmii-id";
+			phy-handle = <&phy_88E1111_a>;
+			status = "okay";
+			mdio0 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "snps,dwmac-mdio";
+
+				phy_88E1111_a: ethernet-phy@1 {
+					reg = <0x1>;
+				};
+
+				phy_88E1111_b: ethernet-phy@2 {
+					reg = <0x2>;
+				};
+			};
+		};
+
+		gmac1: ethernet@ffe7060000 {
+			compatible = "snps,dwmac";
+			reg = <0xff 0xe7060000 0x0 0x2000>;
+			clocks = <&dummy_apb>;
+			clock-names = "stmmaceth";
+			snps,pbl = <32>;
+			snps,fixed-burst;
+			phy-mode = "rgmii-id";
+			phy-handle = <&phy_88E1111_b>;
+			status = "okay";
+		};
+
+		emmc: sdhci@ffe7080000 {
+			compatible = "snps,dwcmshc-sdhci";
+			reg = <0xff 0xe7080000 0x0 0x10000>;
+			index = <0x0>;
+			clocks = <&dummy_ahb>;
+			clock-frequency = <198000000>;
+			clock-names = "core";
+			max-frequency = <198000000>;
+			sdhci-caps-mask = <0x0 0x1000000>;
+			mmc-hs400-1_8v;
+			non-removable;
+			no-sdio;
+			no-sd;
+			bus-width = <8>;
+			voltage= "1.8v";
+			pull_up;
+			io_fixed_1v8;
+			fifo-mode;
+			u-boot,dm-pre-reloc;
+		};
+
+		sdhci0: sd@ffe7090000 {
+			compatible = "snps,dwcmshc-sdhci";
+			reg = <0xff 0xe7090000 0x0 0x10000>;
+			index = <0x1>;
+			clocks = <&dummy_ahb>;
+			clock-frequency = <198000000>;
+			max-frequency = <198000000>;
+			sd-uhs-sdr104;
+			pull_up;
+			clock-names = "core";
+			bus-width = <4>;
+			voltage= "3.3v";
+		};
+
+		qspi0: spi@ffea000000 {
+			compatible = "snps,dw-apb-ssi-quad";
+			reg = <0xff 0xea000000 0x0 0x1000>;
+			clocks = <&dummy_qspi0>;
+			num-cs = <1>;
+			cs-gpio = <&gpio2_porta 3 0>; // GPIO_ACTIVE_HIGH: 0
+			spi-max-frequency = <100000000>;
+			#address-cells = <1>;
+			#size-cells =<0>;
+			spi-flash@0 {
+				#address-cells = <1>;
+				#size-cells = <1>;
+				compatible = "spi-nand";
+				spi-tx-bus-width = <4>;
+				spi-rx-bus-width = <4>;
+				reg = <0>;
+			};
+		};
+
+		qspi1: spi@fff8000000 {
+			compatible = "snps,dw-apb-ssi-quad";
+			reg = <0xff 0xf8000000 0x0 0x1000>;
+			clocks = <&dummy_spi>;
+			num-cs = <1>;
+			cs-gpio = <&gpio0_porta 1 0>; // GPIO_ACTIVE_HIGH: 0
+			spi-max-frequency = <66000000>;
+			#address-cells = <1>;
+			#size-cells =<0>;
+			spi-flash@0 {
+				#address-cells = <1>;
+				#size-cells = <1>;
+				compatible = "spi-nand";
+				spi-tx-bus-width = <4>;
+				spi-rx-bus-width = <4>;
+				reg = <0>;
+			};
+		};
+
+		spi0: spi@ffe700c000 {
+			compatible = "snps,dw-apb-ssi";
+			reg = <0xff 0xe700c000 0x0 0x1000>;
+			clocks = <&dummy_spi>;
+			cs-gpio = <&gpio2_porta 15 0>;
+			spi-max-frequency = <100000000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			flash@0 {
+				compatible = "jedec,spi-nor";
+				reg = <0>;
+				spi-max-frequency = <40000000>;
+			};
+		};
+
+		gpio2: gpio@ffe7f34000 {
+			compatible = "snps,dw-apb-gpio";
+			reg = <0xff 0xe7f34000 0x0 0x1000>;
+			clocks = <&dummy_apb>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			gpio2_porta: gpio-controller@0 {
+				compatible = "snps,dw-apb-gpio-port";
+				gpio-controller;
+				#gpio-cells = <2>;
+				snps,nr-gpios = <32>;
+				reg = <0>;
+			};
+		};
+
+		gpio0: gpio@ffec005000 {
+			compatible = "snps,dw-apb-gpio";
+			reg = <0xff 0xec005000 0x0 0x1000>;
+			clocks = <&dummy_apb>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			gpio0_porta: gpio-controller@0 {
+				compatible = "snps,dw-apb-gpio-port";
+				gpio-controller;
+				#gpio-cells = <2>;
+				snps,nr-gpios = <32>;
+				reg = <0>;
+			};
+		};
+
+		gpio1: gpio@ffec006000 {
+			compatible = "snps,dw-apb-gpio";
+			reg = <0xff 0xec006000 0x0 0x1000>;
+			clocks = <&dummy_apb>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			gpio1_porta: gpio-controller@0 {
+				compatible = "snps,dw-apb-gpio-port";
+				gpio-controller;
+				#gpio-cells = <2>;
+				snps,nr-gpios = <32>;
+				reg = <0>;
+			};
+		};
+
+		pwm: pwm@ffec01c000 {
+			compatible = "thead,pwm-light";
+			reg = <0xff 0xec01c000 0x0 0x4000>;
+			#pwm-cells = <2>;
+		};
+
+		dsi_regs: dsi-controller@ffef500000 {
+			compatible = "thead,light-dsi-regs", "syscon";
+			reg = <0xff 0xef500000 0x0 0x10000>;
+			status = "okay";
+		};
+
+		vosys_regs: vosys@ffef528000 {
+			compatible = "thead,light-vo-subsys", "syscon";
+			reg = <0xff 0xef528000 0x0 0x1000>;
+			status = "okay";
+		};
+
+		dpu: dc8200@ffef600000 {
+			compatible = "verisilicon,dc8200";
+			reg = <0xff 0xef600000 0x0 0x100>;
+		};
+
+		axiscr {
+			compatible = "thead,axiscr";
+			reg = <0xff 0xff004000 0x0 0x1000>;
+			lock-read = "okay";
+			lock-write = "okay";
+			#address-cells = <2>;
+			#size-cells = <2>;
+			u-boot,dm-pre-reloc;
+			axiscr0: axisrc@0 {
+				device_type = "axiscr";
+				region = <0x00 0x00000000 0x00 0x80000000>; // 4KB align
+				status = "disabled";
+				#address-cells = <2>;
+				#size-cells = <2>;
+				u-boot,dm-pre-reloc;
+			};
+			axiscr1: axisrc@1 {
+				device_type = "axiscr";
+				region = <0x00 0x80000000 0x00 0x80000000>; // 4KB align
+				status = "disabled";
+				#address-cells = <2>;
+				#size-cells = <2>;
+				u-boot,dm-pre-reloc;
+			};
+			axiscr2: axisrc@2 {
+				device_type = "axiscr";
+				region = <0x01 0x00000000 0x00 0x80000000>; // 4KB align
+				status = "disabled";
+				#address-cells = <2>;
+				#size-cells = <2>;
+				u-boot,dm-pre-reloc;
+			};
+		};
+
+		axiparity {
+			compatible = "thead,axiparity";
+			reg = <0xff 0xff00c000 0x0 0x1000>;
+			lock = "okay";
+			#address-cells = <2>;
+			#size-cells = <2>;
+			u-boot,dm-pre-reloc;
+			axiparity0: axiparity@0 {
+				device_type = "axiparity";
+				region = <0x00 0x00000000 0x01 0x0000000>; // 4KB align
+				status = "disabled";
+				#address-cells = <2>;
+				#size-cells = <2>;
+				u-boot,dm-pre-reloc;
+			};
+			axiparity1: axiparity@1 {
+				device_type = "axiparity";
+				region = <0x01 0x00000000 0x01 0x00000000>; // 4KB align
+				status = "disabled";
+				#address-cells = <2>;
+				#size-cells = <2>;
+				u-boot,dm-pre-reloc;
+			};
+		};
+
+		dsi_bridge: dsi-bridge {
+			compatible = "thead,light-dsi-bridge";
+			clocks = <&dummy_dpu_pixclk>;
+			clock-names = "pix-clk";
+			phys = <&dsi_dphy>;
+			phy-names = "dphy";
+		};
+
+		dsi_host: dsi-host {
+			compatible = "synopsys,dw-mipi-dsi";
+			regmap = <&dsi_regs>;
+			status = "okay";
+		};
+
+		dsi_dphy: dsi-dphy {
+			compatible = "synopsys,dw-dphy";
+			regmap = <&dsi_regs>;
+			vosys-regmap = <&vosys_regs>;
+			clocks = <&dummy_dpu_pixclk>, <&dummy_dphy_refclk>;
+			clock-names = "pix-clk", "ref-clk";
+			#phy-cells = <0>;
+			status = "okay";
+		};
+
+		lcd_backlight: pwm-backlight {
+			compatible = "pwm-backlight";
+			pwms = <&pwm 0 5000000>;
+			brightness-levels = <0 4 8 16 32 64 128 255>;
+			default-brightness-level = <7>;
+		};
+
+		ili9881c_panel {
+			compatible      = "ilitek,ili9881c";
+			backlight       = <&lcd_backlight>;
+			reset-gpios     = <&gpio1_porta 5 1>;   /* active low  */
+			lcd-en-gpios    = <&pcal6408ahk_a 2 0>; /* active high */
+			lcd-bias-en-gpios = <&pcal6408ahk_a 4 0>;/* active high */
+		};
+	};
+
+	chosen {
+		bootargs = "console=ttyS0,115200";
+		stdout-path = "/soc/serial@ffe7014000:115200";
+	};
+};

arch/riscv/dts/light-lpi4a-laptop.dts

@@ -0,0 +1,50 @@
+#include "light-lpi4a.dts"
+
+/ {
+};
+
+&i2c1 {
+	clock-frequency = <400000>;
+        status = "okay";
+
+        pcal6408ahk_c: gpio@20 {
+                compatible = "nxp,pca9557";
+                reg = <0x18>;
+                gpio-controller;
+                #gpio-cells = <2>;
+        };
+};
+
+&i2c3 {
+	clock-frequency = <400000>;
+	status = "okay";
+	pcal6408ahk_d: gpio@20 {
+		compatible = "nxp,pca9557";
+		reg = <0x18>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+};
+
+&lcd_backlight {
+	pwms = <&pwm 0 50000>;
+	brightness-levels = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35
+	36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75
+	76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100>;
+	default-brightness-level = <2>;
+};
+
+&panel0 {
+	status = "okay";
+	backlight = <&lcd_backlight>;
+	// 5v power cycle
+	// TODO: move into regulator
+	reset-gpios     = <&pcal6408ahk_c 0 0>; /* active low  */
+	/delete-property/ lcd-en-gpios;
+	/delete-property/ lcd-bias-en-gpios;
+};
+
+&sdhci0 {
+	max-frequency = <35000000>;
+	status = "okay";
+};

arch/riscv/dts/light-lpi4a.dts

@@ -0,0 +1,488 @@
+/dts-v1/;
+/ {
+	model = "T-HEAD c910 light";
+	compatible = "thead,c910_light";
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	memory@0 {
+		device_type = "memory";
+		reg = <0x0 0xc0000000 0x0 0x40000000>;
+	};
+
+	aliases {
+		spi0 = &spi0;
+		spi1 = &qspi0;
+		spi2 = &qspi1;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		timebase-frequency = <3000000>;
+		u-boot,dm-pre-reloc;
+		cpu@0 {
+			device_type = "cpu";
+			reg = <0>;
+			status = "okay";
+			compatible = "riscv";
+			riscv,isa = "rv64imafdcvsu";
+			mmu-type = "riscv,sv39";
+			u-boot,dm-pre-reloc;
+		};
+	};
+
+	soc {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		compatible = "simple-bus";
+		ranges;
+		u-boot,dm-pre-reloc;
+
+		intc: interrupt-controller@ffd8000000 {
+			compatible = "riscv,plic0";
+			reg = <0xff 0xd8000000 0x0 0x04000000>;
+			status = "disabled";
+		};
+
+		dummy_apb: apb-clock {
+			compatible = "fixed-clock";
+			clock-frequency = <62500000>;
+			clock-output-names = "dummy_apb";
+			#clock-cells = <0>;
+			u-boot,dm-pre-reloc;
+		};
+
+		dummy_ahb: ahb-clock {
+			compatible = "fixed-clock";
+			clock-frequency = <250000000>;
+			clock-output-names = "core";
+			#clock-cells = <0>;
+			u-boot,dm-pre-reloc;
+		};
+
+		dummy_spi: spi-clock {
+			compatible = "fixed-clock";
+			clock-frequency = <396000000>;
+			clock-output-names = "dummy_spi";
+			#clock-cells = <0>;
+			u-boot,dm-pre-reloc;
+		};
+
+		dummy_qspi0: qspi0-clock {
+			compatible = "fixed-clock";
+			clock-frequency = <792000000>;
+			clock-output-names = "dummy_qspi0";
+			#clock-cells = <0>;
+			u-boot,dm-pre-reloc;
+		};
+
+		dummy_uart_sclk: uart-sclk-clock {
+			compatible = "fixed-clock";
+			clock-frequency = <100000000>;
+			clock-output-names = "dummy_uart_sclk";
+			#clock-cells = <0>;
+			u-boot,dm-pre-reloc;
+		};
+
+		dummy_i2c_icclk: i2c-icclk-clock {
+			compatible = "fixed-clock";
+			clock-frequency = <50000000>;
+			clock-output-names = "dummy_i2c_icclk";
+			#clock-cells = <0>;
+			u-boot,dm-pre-reloc;
+		};
+
+		dummy_dpu_pixclk: dpu-pix-clock {
+			compatible = "fixed-clock";
+			clock-frequency = <74250000>;
+			clock-output-names = "dummy_dpu_pixclk";
+			#clock-cells = <0>;
+			u-boot,dm-pre-reloc;
+		};
+
+		dummy_dphy_refclk: dphy-ref-clock {
+			compatible = "fixed-clock";
+			clock-frequency = <24000000>;
+			clock-output-names = "dummy_dpu_refclk";
+			#clock-cells = <0>;
+			u-boot,dm-pre-reloc;
+		};
+
+		i2c0: i2c@ffe7f20000 {
+			compatible = "snps,designware-i2c";
+			reg = <0xff 0xe7f20000 0x0 0x4000>;
+			clocks = <&dummy_i2c_icclk>;
+			clock-frequency = <100000>;
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c1: i2c@ffe7f24000{
+			compatible = "snps,designware-i2c";
+			reg = <0xff 0xe7f24000 0x0 0x4000>;
+			clocks = <&dummy_i2c_icclk>;
+			clock-frequency = <100000>;
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c2: i2c@ffec00c000{
+			compatible = "snps,designware-i2c";
+			reg = <0xff 0xec00c000 0x0 0x4000>;
+			clocks = <&dummy_i2c_icclk>;
+			clock-frequency = <100000>;
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c3: i2c@ffec014000{
+			compatible = "snps,designware-i2c";
+			reg = <0xff 0xec014000 0x0 0x4000>;
+			clocks = <&dummy_i2c_icclk>;
+			clock-frequency = <100000>;
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c4: i2c@ffe7f28000{
+			compatible = "snps,designware-i2c";
+			reg = <0xff 0xe7f28000 0x0 0x4000>;
+			clocks = <&dummy_i2c_icclk>;
+			clock-frequency = <100000>;
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			pcal6408ahk_a: gpio@20 {
+				compatible = "nxp,pca9554";
+				reg = <0x20>;
+				gpio-controller;
+				#gpio-cells = <2>;
+			};
+		};
+
+		i2c5: i2c@fff7f2c000{
+			compatible = "snps,designware-i2c";
+			reg = <0xff 0xf7f2c000 0x0 0x4000>;
+			clocks = <&dummy_i2c_icclk>;
+			clock-frequency = <100000>;
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		serial@ffe7014000 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0xff 0xe7014000 0x0 0x400>;
+			clocks = <&dummy_uart_sclk>;
+			clock-frequency = <100000000>;
+			clock-names = "baudclk";
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			u-boot,dm-pre-reloc;
+		};
+
+		gmac0: ethernet@ffe7070000 {
+			compatible = "snps,dwmac";
+			reg = <0xff 0xe7070000 0x0 0x2000>;
+			clocks = <&dummy_apb>;
+			clock-names = "stmmaceth";
+			snps,pbl = <32>;
+			snps,fixed-burst;
+
+			phy-mode = "rgmii-id";
+			phy-handle = <&phy_88E1111_a>;
+			status = "okay";
+			mdio0 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "snps,dwmac-mdio";
+
+				phy_88E1111_a: ethernet-phy@1 {
+					reg = <0x1>;
+				};
+
+				phy_88E1111_b: ethernet-phy@2 {
+					reg = <0x2>;
+				};
+			};
+		};
+
+		gmac1: ethernet@ffe7060000 {
+			compatible = "snps,dwmac";
+			reg = <0xff 0xe7060000 0x0 0x2000>;
+			clocks = <&dummy_apb>;
+			clock-names = "stmmaceth";
+			snps,pbl = <32>;
+			snps,fixed-burst;
+			phy-mode = "rgmii-id";
+			phy-handle = <&phy_88E1111_b>;
+			status = "okay";
+		};
+
+		emmc: sdhci@ffe7080000 {
+			compatible = "snps,dwcmshc-sdhci";
+			reg = <0xff 0xe7080000 0x0 0x10000>;
+			index = <0x0>;
+			clocks = <&dummy_ahb>;
+			clock-frequency = <198000000>;
+			clock-names = "core";
+			max-frequency = <198000000>;
+			sdhci-caps-mask = <0x0 0x1000000>;
+			mmc-hs400-1_8v;
+			non-removable;
+			no-sdio;
+			no-sd;
+			bus-width = <8>;
+			voltage= "1.8v";
+			pull_up;
+			io_fixed_1v8;
+			fifo-mode;
+			u-boot,dm-pre-reloc;
+		};
+
+		sdhci0: sd@ffe7090000 {
+			compatible = "snps,dwcmshc-sdhci";
+			reg = <0xff 0xe7090000 0x0 0x10000>;
+			index = <0x1>;
+			clocks = <&dummy_ahb>;
+			clock-frequency = <198000000>;
+			max-frequency = <198000000>;
+			sd-uhs-sdr104;
+			pull_up;
+			clock-names = "core";
+			bus-width = <4>;
+			voltage= "3.3v";
+		};
+
+		qspi0: spi@ffea000000 {
+			compatible = "snps,dw-apb-ssi-quad";
+			reg = <0xff 0xea000000 0x0 0x1000>;
+			clocks = <&dummy_qspi0>;
+			num-cs = <1>;
+			cs-gpio = <&gpio2_porta 3 0>; // GPIO_ACTIVE_HIGH: 0
+			spi-max-frequency = <100000000>;
+			#address-cells = <1>;
+			#size-cells =<0>;
+			spi-flash@0 {
+				#address-cells = <1>;
+				#size-cells = <1>;
+				compatible = "spi-nand";
+				spi-tx-bus-width = <4>;
+				spi-rx-bus-width = <4>;
+				reg = <0>;
+			};
+		};
+
+		qspi1: spi@fff8000000 {
+			compatible = "snps,dw-apb-ssi-quad";
+			reg = <0xff 0xf8000000 0x0 0x1000>;
+			clocks = <&dummy_spi>;
+			num-cs = <1>;
+			cs-gpio = <&gpio0_porta 1 0>; // GPIO_ACTIVE_HIGH: 0
+			spi-max-frequency = <66000000>;
+			#address-cells = <1>;
+			#size-cells =<0>;
+			spi-flash@0 {
+				#address-cells = <1>;
+				#size-cells = <1>;
+				compatible = "spi-nand";
+				spi-tx-bus-width = <4>;
+				spi-rx-bus-width = <4>;
+				reg = <0>;
+			};
+		};
+
+		spi0: spi@ffe700c000 {
+			compatible = "snps,dw-apb-ssi";
+			reg = <0xff 0xe700c000 0x0 0x1000>;
+			clocks = <&dummy_spi>;
+			cs-gpio = <&gpio2_porta 15 0>;
+			spi-max-frequency = <100000000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			flash@0 {
+				compatible = "jedec,spi-nor";
+				reg = <0>;
+				spi-max-frequency = <40000000>;
+			};
+		};
+
+		gpio2: gpio@ffe7f34000 {
+			compatible = "snps,dw-apb-gpio";
+			reg = <0xff 0xe7f34000 0x0 0x1000>;
+			clocks = <&dummy_apb>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			gpio2_porta: gpio-controller@0 {
+				compatible = "snps,dw-apb-gpio-port";
+				gpio-controller;
+				#gpio-cells = <2>;
+				snps,nr-gpios = <32>;
+				reg = <0>;
+			};
+		};
+
+		gpio0: gpio@ffec005000 {
+			compatible = "snps,dw-apb-gpio";
+			reg = <0xff 0xec005000 0x0 0x1000>;
+			clocks = <&dummy_apb>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			gpio0_porta: gpio-controller@0 {
+				compatible = "snps,dw-apb-gpio-port";
+				gpio-controller;
+				#gpio-cells = <2>;
+				snps,nr-gpios = <32>;
+				reg = <0>;
+			};
+		};
+
+		gpio1: gpio@ffec006000 {
+			compatible = "snps,dw-apb-gpio";
+			reg = <0xff 0xec006000 0x0 0x1000>;
+			clocks = <&dummy_apb>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			gpio1_porta: gpio-controller@0 {
+				compatible = "snps,dw-apb-gpio-port";
+				gpio-controller;
+				#gpio-cells = <2>;
+				snps,nr-gpios = <32>;
+				reg = <0>;
+			};
+		};
+
+		pwm: pwm@ffec01c000 {
+			compatible = "thead,pwm-light";
+			reg = <0xff 0xec01c000 0x0 0x4000>;
+			#pwm-cells = <2>;
+		};
+
+		dsi_regs: dsi-controller@ffef500000 {
+			compatible = "thead,light-dsi-regs", "syscon";
+			reg = <0xff 0xef500000 0x0 0x10000>;
+			status = "okay";
+		};
+
+		vosys_regs: vosys@ffef528000 {
+			compatible = "thead,light-vo-subsys", "syscon";
+			reg = <0xff 0xef528000 0x0 0x1000>;
+			status = "okay";
+		};
+
+		dpu: dc8200@ffef600000 {
+			compatible = "verisilicon,dc8200";
+			reg = <0xff 0xef600000 0x0 0x100>;
+		};
+
+		axiscr {
+			compatible = "thead,axiscr";
+			reg = <0xff 0xff004000 0x0 0x1000>;
+			lock-read = "okay";
+			lock-write = "okay";
+			#address-cells = <2>;
+			#size-cells = <2>;
+			u-boot,dm-pre-reloc;
+			axiscr0: axisrc@0 {
+				device_type = "axiscr";
+				region = <0x00 0x00000000 0x00 0x80000000>; // 4KB align
+				status = "disabled";
+				#address-cells = <2>;
+				#size-cells = <2>;
+				u-boot,dm-pre-reloc;
+			};
+			axiscr1: axisrc@1 {
+				device_type = "axiscr";
+				region = <0x00 0x80000000 0x00 0x80000000>; // 4KB align
+				status = "disabled";
+				#address-cells = <2>;
+				#size-cells = <2>;
+				u-boot,dm-pre-reloc;
+			};
+			axiscr2: axisrc@2 {
+				device_type = "axiscr";
+				region = <0x01 0x00000000 0x00 0x80000000>; // 4KB align
+				status = "disabled";
+				#address-cells = <2>;
+				#size-cells = <2>;
+				u-boot,dm-pre-reloc;
+			};
+		};
+
+		axiparity {
+			compatible = "thead,axiparity";
+			reg = <0xff 0xff00c000 0x0 0x1000>;
+			lock = "okay";
+			#address-cells = <2>;
+			#size-cells = <2>;
+			u-boot,dm-pre-reloc;
+			axiparity0: axiparity@0 {
+				device_type = "axiparity";
+				region = <0x00 0x00000000 0x01 0x0000000>; // 4KB align
+				status = "disabled";
+				#address-cells = <2>;
+				#size-cells = <2>;
+				u-boot,dm-pre-reloc;
+			};
+			axiparity1: axiparity@1 {
+				device_type = "axiparity";
+				region = <0x01 0x00000000 0x01 0x00000000>; // 4KB align
+				status = "disabled";
+				#address-cells = <2>;
+				#size-cells = <2>;
+				u-boot,dm-pre-reloc;
+			};
+		};
+
+		dsi_bridge: dsi-bridge {
+			compatible = "thead,light-dsi-bridge";
+			clocks = <&dummy_dpu_pixclk>;
+			clock-names = "pix-clk";
+			phys = <&dsi_dphy>;
+			phy-names = "dphy";
+		};
+
+		dsi_host: dsi-host {
+			compatible = "synopsys,dw-mipi-dsi";
+			regmap = <&dsi_regs>;
+			status = "okay";
+		};
+
+		dsi_dphy: dsi-dphy {
+			compatible = "synopsys,dw-dphy";
+			regmap = <&dsi_regs>;
+			vosys-regmap = <&vosys_regs>;
+			clocks = <&dummy_dpu_pixclk>, <&dummy_dphy_refclk>;
+			clock-names = "pix-clk", "ref-clk";
+			#phy-cells = <0>;
+			status = "okay";
+		};
+
+		lcd_backlight: pwm-backlight {
+			compatible = "pwm-backlight";
+			pwms = <&pwm 0 5000000>;
+			brightness-levels = <0 4 8 16 32 64 128 255>;
+			default-brightness-level = <7>;
+		};
+
+		panel0: dsi_panel0 {
+			compatible      = "ilitek,ili9881c";
+			backlight       = <&lcd_backlight>;
+			reset-gpios     = <&gpio1_porta 5 1>;   /* active low  */
+			lcd-en-gpios    = <&pcal6408ahk_a 2 0>; /* active high */
+			lcd-bias-en-gpios = <&pcal6408ahk_a 4 0>;/* active high */
+		};
+	};
+
+	chosen {
+		bootargs = "console=ttyS0,115200";
+		stdout-path = "/soc/serial@ffe7014000:115200";
+	};
+};

arch/riscv/dts/light-milkv-meles.dts

@@ -0,0 +1,288 @@
+/dts-v1/;
+/ {
+	model = "Milk-V Meles";
+	compatible = "milkv,meles", "thead,c910_light";
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	config {
+		select-gpio = <&gpio1_porta 16 0>;
+	};
+
+	memory@0 {
+		device_type = "memory";
+		reg = <0x0 0xc0000000 0x0 0x40000000>;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		timebase-frequency = <3000000>;
+		u-boot,dm-pre-reloc;
+		cpu@0 {
+			device_type = "cpu";
+			reg = <0>;
+			status = "okay";
+			compatible = "riscv";
+			riscv,isa = "rv64imafdcvsu";
+			mmu-type = "riscv,sv39";
+			u-boot,dm-pre-reloc;
+		};
+	};
+
+	soc {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		compatible = "simple-bus";
+		ranges;
+		u-boot,dm-pre-reloc;
+
+		intc: interrupt-controller@ffd8000000 {
+			compatible = "riscv,plic0";
+			reg = <0xff 0xd8000000 0x0 0x04000000>;
+			status = "disabled";
+		};
+
+		dummy_apb: apb-clock {
+			compatible = "fixed-clock";
+			clock-frequency = <62500000>;
+			clock-output-names = "dummy_apb";
+			#clock-cells = <0>;
+			u-boot,dm-pre-reloc;
+		};
+
+		dummy_ahb: ahb-clock {
+			compatible = "fixed-clock";
+			clock-frequency = <250000000>;
+			clock-output-names = "core";
+			#clock-cells = <0>;
+			u-boot,dm-pre-reloc;
+		};
+
+		dummy_spi: spi-clock {
+			compatible = "fixed-clock";
+			clock-frequency = <396000000>;
+			clock-output-names = "dummy_spi";
+			#clock-cells = <0>;
+			u-boot,dm-pre-reloc;
+		};
+
+		dummy_qspi0: qspi0-clock {
+			compatible = "fixed-clock";
+			clock-frequency = <792000000>;
+			clock-output-names = "dummy_qspi0";
+			#clock-cells = <0>;
+			u-boot,dm-pre-reloc;
+		};
+
+		dummy_uart_sclk: uart-sclk-clock {
+			compatible = "fixed-clock";
+			clock-frequency = <100000000>;
+			clock-output-names = "dummy_uart_sclk";
+			#clock-cells = <0>;
+			u-boot,dm-pre-reloc;
+		};
+
+		dummy_i2c_icclk: i2c-icclk-clock {
+			compatible = "fixed-clock";
+			clock-frequency = <50000000>;
+			clock-output-names = "dummy_i2c_icclk";
+			#clock-cells = <0>;
+			u-boot,dm-pre-reloc;
+		};
+
+		dummy_dpu_pixclk: dpu-pix-clock {
+			compatible = "fixed-clock";
+			clock-frequency = <74250000>;
+			clock-output-names = "dummy_dpu_pixclk";
+			#clock-cells = <0>;
+			u-boot,dm-pre-reloc;
+		};
+
+		dummy_dphy_refclk: dphy-ref-clock {
+			compatible = "fixed-clock";
+			clock-frequency = <24000000>;
+			clock-output-names = "dummy_dpu_refclk";
+			#clock-cells = <0>;
+			u-boot,dm-pre-reloc;
+		};
+
+		serial@ffe7014000 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0xff 0xe7014000 0x0 0x400>;
+			clocks = <&dummy_uart_sclk>;
+			clock-frequency = <100000000>;
+			clock-names = "baudclk";
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			u-boot,dm-pre-reloc;
+		};
+
+		gmac0: ethernet@ffe7070000 {
+			compatible = "snps,dwmac";
+			reg = <0xff 0xe7070000 0x0 0x2000>;
+			clocks = <&dummy_apb>;
+			clock-names = "stmmaceth";
+			snps,pbl = <32>;
+			snps,fixed-burst;
+
+			phy-mode = "rgmii-id";
+			phy-handle = <&phy_88E1111_a>;
+			status = "okay";
+			mdio0 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "snps,dwmac-mdio";
+
+				phy_88E1111_a: ethernet-phy@1 {
+					reg = <0x1>;
+				};
+			};
+		};
+
+		emmc: sdhci@ffe7080000 {
+			compatible = "snps,dwcmshc-sdhci";
+			reg = <0xff 0xe7080000 0x0 0x10000>;
+			index = <0x0>;
+			clocks = <&dummy_ahb>;
+			clock-frequency = <198000000>;
+			clock-names = "core";
+			max-frequency = <198000000>;
+			sdhci-caps-mask = <0x0 0x1000000>;
+			mmc-hs400-1_8v;
+			non-removable;
+			no-sdio;
+			no-sd;
+			bus-width = <8>;
+			voltage= "1.8v";
+			pull_up;
+			io_fixed_1v8;
+			fifo-mode;
+			u-boot,dm-pre-reloc;
+		};
+
+		sdhci0: sd@ffe7090000 {
+			compatible = "snps,dwcmshc-sdhci";
+			reg = <0xff 0xe7090000 0x0 0x10000>;
+			index = <0x1>;
+			clocks = <&dummy_ahb>;
+			clock-frequency = <198000000>;
+			max-frequency = <198000000>;
+			sd-uhs-sdr104;
+			pull_up;
+			clock-names = "core";
+			bus-width = <4>;
+			voltage= "3.3v";
+		};
+
+		gpio2: gpio@ffe7f34000 {
+			compatible = "snps,dw-apb-gpio";
+			reg = <0xff 0xe7f34000 0x0 0x1000>;
+			clocks = <&dummy_apb>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			gpio2_porta: gpio-controller@0 {
+				compatible = "snps,dw-apb-gpio-port";
+				gpio-controller;
+				#gpio-cells = <2>;
+				snps,nr-gpios = <32>;
+				reg = <0>;
+			};
+		};
+
+		gpio0: gpio@ffec005000 {
+			compatible = "snps,dw-apb-gpio";
+			reg = <0xff 0xec005000 0x0 0x1000>;
+			clocks = <&dummy_apb>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			gpio0_porta: gpio-controller@0 {
+				compatible = "snps,dw-apb-gpio-port";
+				gpio-controller;
+				#gpio-cells = <2>;
+				snps,nr-gpios = <32>;
+				reg = <0>;
+			};
+		};
+
+		gpio1: gpio@ffec006000 {
+			compatible = "snps,dw-apb-gpio";
+			reg = <0xff 0xec006000 0x0 0x1000>;
+			clocks = <&dummy_apb>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			gpio1_porta: gpio-controller@0 {
+				compatible = "snps,dw-apb-gpio-port";
+				gpio-controller;
+				#gpio-cells = <2>;
+				snps,nr-gpios = <32>;
+				reg = <0>;
+			};
+		};
+
+		axiscr {
+			compatible = "thead,axiscr";
+			reg = <0xff 0xff004000 0x0 0x1000>;
+			lock-read = "okay";
+			lock-write = "okay";
+			#address-cells = <2>;
+			#size-cells = <2>;
+			u-boot,dm-pre-reloc;
+			axiscr0: axisrc@0 {
+				device_type = "axiscr";
+				region = <0x00 0x00000000 0x00 0x80000000>; // 4KB align
+				status = "disabled";
+				#address-cells = <2>;
+				#size-cells = <2>;
+				u-boot,dm-pre-reloc;
+			};
+			axiscr1: axisrc@1 {
+				device_type = "axiscr";
+				region = <0x00 0x80000000 0x00 0x80000000>; // 4KB align
+				status = "disabled";
+				#address-cells = <2>;
+				#size-cells = <2>;
+				u-boot,dm-pre-reloc;
+			};
+			axiscr2: axisrc@2 {
+				device_type = "axiscr";
+				region = <0x01 0x00000000 0x00 0x80000000>; // 4KB align
+				status = "disabled";
+				#address-cells = <2>;
+				#size-cells = <2>;
+				u-boot,dm-pre-reloc;
+			};
+		};
+
+		axiparity {
+			compatible = "thead,axiparity";
+			reg = <0xff 0xff00c000 0x0 0x1000>;
+			lock = "okay";
+			#address-cells = <2>;
+			#size-cells = <2>;
+			u-boot,dm-pre-reloc;
+			axiparity0: axiparity@0 {
+				device_type = "axiparity";
+				region = <0x00 0x00000000 0x01 0x0000000>; // 4KB align
+				status = "disabled";
+				#address-cells = <2>;
+				#size-cells = <2>;
+				u-boot,dm-pre-reloc;
+			};
+			axiparity1: axiparity@1 {
+				device_type = "axiparity";
+				region = <0x01 0x00000000 0x01 0x00000000>; // 4KB align
+				status = "disabled";
+				#address-cells = <2>;
+				#size-cells = <2>;
+				u-boot,dm-pre-reloc;
+			};
+		};
+	};
+
+	chosen {
+		bootargs = "console=ttyS0,115200";
+		stdout-path = "/soc/serial@ffe7014000:115200";
+	};
+};

arch/riscv/include/asm/arch-thead/boot_mode.h

@@ -34,7 +34,9 @@ typedef enum image_type {
 	T_ROOTFS = 4,
 	T_TF = 2,
 	T_TEE = 5,
-	T_UBOOT = 6
+	T_UBOOT = 6,
+	T_USER = 7,
+	T_SBMETA = 8,
 } img_type_t;
 
 static const char header_magic[4] = {'T', 'H', 'E', 'D'};

arch/riscv/include/asm/arch-thead/light-plic.h

@@ -0,0 +1,51 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2022, Liuw  <lw312886@alibaba-inc.com>
+ *
+ * U-Boot syscon driver for Thead's Platform Level Interrupt Controller (PLIC)
+ */
+
+#ifndef _LIGHT_PLIC_H
+#define _LIGHT_PLIC_H
+
+/*
+ * M-mode
+ *	hart id: 0, 2, 4, 6
+ * S-mode
+ *	hart id: 1, 3, 5, 7
+ */
+
+/* interrupt priority register */
+#define PLIC_PRIO_REG(base, id)			((void __iomem *)(base) + 0x00 + (id) * 4)
+
+/* enable register */
+#define PLIC_ENABLE_REG(base, hart)		((void __iomem *)(base) + 0x2000 + (hart) * 0x80)
+
+/* pending registr */
+#define PLIC_PENDING_REG(base, hart)		((void __iomem *)(base) + 0x1000 + ((hart) / 4) * 4)
+
+/* threshold register */
+#define PLIC_THRESHOLD_REG(base, hart)		((void __iomem *)(base) + 0x200000 + (hart) * 0x1000 + 0x00)
+
+/* claim/complete register */
+#define PLIC_CLAIM_REG(base, hart)		((void __iomem *)(base) + 0x200000 + (hart) * 0x1000 + 0x04)
+
+#define MAX_IRQ_NUM	256
+typedef void (*irq_handler_t)(void);
+
+
+int irq_handler_register(int irq, irq_handler_t handler);
+
+void arch_local_irq_enable(void);
+
+void arch_local_irq_disable(void);
+
+void irq_enable(int hwirq);
+
+void irq_disable(int hwirq);
+
+void irq_priority_set(int prio);
+
+int plic_init(void);
+
+#endif

arch/riscv/include/asm/arch-thead/light-reset.h

@@ -0,0 +1,17 @@
+#ifndef __LIGHT_RESET_H__
+#define __LIGHT_RESET_H__
+
+#define APSYS_RSTGEN_BASE	0xFFEF014000
+#define REG_C910_SWRST		(APSYS_RSTGEN_BASE + 0x4)
+#define APSYS_REG_BASE		0xFFEF018000
+#define REG_C910_CORE0_RVBA_L	(APSYS_REG_BASE + 0x50)
+#define REG_C910_CORE0_RVBA_H	(APSYS_REG_BASE + 0x54)
+#define REG_C910_CORE1_RVBA_L	(APSYS_REG_BASE + 0x58)
+#define REG_C910_CORE1_RVBA_H	(APSYS_REG_BASE + 0x5C)
+#define REG_C910_CORE2_RVBA_L	(APSYS_REG_BASE + 0x60)
+#define REG_C910_CORE2_RVBA_H	(APSYS_REG_BASE + 0x64)
+#define REG_C910_CORE3_RVBA_L	(APSYS_REG_BASE + 0x68)
+#define REG_C910_CORE3_RVBA_H	(APSYS_REG_BASE + 0x6C)
+#define REG_PLIC_DELEGATE	0xffd81ffffc
+
+#endif /* __LIGHT_RESET_H__ */

arch/riscv/include/asm/atomic.h

@@ -0,0 +1,53 @@
+#ifndef _ASM_RISCV_ATOMIC_H
+#define _ASM_RISCV_ATOMIC_H
+
+#include <linux/types.h>
+#include <asm/barrier.h>
+
+typedef struct {
+	volatile long counter;
+} atomic_t;
+
+#define ATOMIC_INIT(_lptr, val) (_lptr)->counter = (val)
+
+#define ATOMIC_INITIALIZER(val)   \
+	{                         \
+		.counter = (val), \
+	}
+
+long atomic_read(atomic_t *atom)
+{
+	long ret = atom->counter;
+	rmb();
+	return ret;
+}
+
+void atomic_write(atomic_t *atom, long value)
+{
+	atom->counter = value;
+	wmb();
+}
+
+long atomic_add_return(atomic_t *atom, long value)
+{
+	long ret;
+#if __SIZEOF_LONG__ == 4
+	__asm__ __volatile__("	amoadd.w.aqrl  %1, %2, %0"
+			     : "+A"(atom->counter), "=r"(ret)
+			     : "r"(value)
+			     : "memory");
+#elif __SIZEOF_LONG__ == 8
+	__asm__ __volatile__("	amoadd.d.aqrl  %1, %2, %0"
+			     : "+A"(atom->counter), "=r"(ret)
+			     : "r"(value)
+			     : "memory");
+#endif
+	return ret + value;
+}
+
+long atomic_sub_return(atomic_t *atom, long value)
+{
+	return atomic_add_return(atom, -value);
+}
+
+#endif /* _ASM_RISCV_ATOMIC_H */

arch/riscv/include/asm/bitops.h

@@ -90,6 +90,16 @@ static inline int __test_and_clear_bit(int nr, void *addr)
 	return retval;
 }
 
+static inline int test_and_clear_bit(int nr, volatile void * addr)
+{
+	unsigned long flags = 0;
+	int out;
+
+	out = __test_and_clear_bit(nr, addr);
+
+	return out;
+}
+
 static inline int __test_and_change_bit(int nr, void *addr)
 {
 	int mask, retval;

arch/riscv/include/asm/csr.h

@@ -12,6 +12,7 @@
 #include <linux/const.h>
 
 /* Status register flags */
+#define SR_MIE          _AC(0x00000008, UL) /* Machine Interrupt Enable */
 #define SR_SIE		_AC(0x00000002, UL) /* Supervisor Interrupt Enable */
 #define SR_SPIE		_AC(0x00000020, UL) /* Previous Supervisor IE */
 #define SR_SPP		_AC(0x00000100, UL) /* Previously Supervisor */
@@ -71,6 +72,7 @@
 
 /* SIE (Interrupt Enable) and SIP (Interrupt Pending) flags */
 #define MIE_MSIE		(_AC(0x1, UL) << IRQ_M_SOFT)
+#define MIE_MEIE		(_AC(0x1, UL) << IRQ_M_EXT)
 #define SIE_SSIE		(_AC(0x1, UL) << IRQ_S_SOFT)
 #define SIE_STIE		(_AC(0x1, UL) << IRQ_S_TIMER)
 #define SIE_SEIE		(_AC(0x1, UL) << IRQ_S_EXT)
@@ -102,15 +104,23 @@
 #define CSR_CYCLEH		0xc80
 #define CSR_TIMEH		0xc81
 #define CSR_INSTRETH		0xc82
+#define CSR_MVENDORID		0xf11
+#define CSR_MARCHID		0xf12
+#define CSR_MIMPID		0xf13
 #define CSR_MHARTID		0xf14
+#define CSR_MCPUID		0xfc0
 
-#define CSR_SMPEN			0x7f3
-#define CSR_MTEE			0x7f4
+#define CSR_SMPEN        0x7f3
+#define CSR_MTEE         0x7f4
 #define CSR_MCOR         0x7c2
 #define CSR_MHCR         0x7c1
 #define CSR_MCCR2        0x7c3
 #define CSR_MHINT        0x7c5
+#define CSR_MHINT2       0x7cc
+#define CSR_MHINT3       0x7cd
+#define CSR_MHINT4       0x7ce
 #define CSR_MXSTATUS     0x7c0
+#define CSR_MSMPR        0x7f3
 #define CSR_PLIC_BASE    0xfc1
 
 #define sync_is()   asm volatile (".long 0x01b0000b")

arch/riscv/include/asm/dma-mapping.h

@@ -10,12 +10,13 @@
 #define __ASM_RISCV_DMA_MAPPING_H
 
 #include <linux/dma-direction.h>
+#include "common.h"
 
 #define dma_mapping_error(x, y)	0
 
 static inline void *dma_alloc_coherent(size_t len, unsigned long *handle)
 {
-	*handle = (unsigned long)memalign(ARCH_DMA_MINALIGN, len);
+	*handle = (unsigned long)memalign(ARCH_DMA_MINALIGN, ROUND(len, ARCH_DMA_MINALIGN));
 	return (void *)*handle;
 }
 

arch/riscv/include/asm/global_data.h

@@ -18,7 +18,7 @@ struct arch_global_data {
 #ifdef CONFIG_SIFIVE_CLINT
 	void __iomem *clint;	/* clint base address */
 #endif
-#ifdef CONFIG_ANDES_PLIC
+#if (defined CONFIG_ANDES_PLIC) || (defined CONFIG_THEAD_PLIC)
 	void __iomem *plic;	/* plic base address */
 #endif
 #ifdef CONFIG_ANDES_PLMT

arch/riscv/lib/Makefile

@@ -15,6 +15,7 @@ obj-$(CONFIG_SIFIVE_CLINT) += sifive_clint.o
 obj-$(CONFIG_ANDES_PLIC) += andes_plic.o
 obj-$(CONFIG_ANDES_PLMT) += andes_plmt.o
 obj-$(CONFIG_THEAD_IPI) += thead_ipi.o
+obj-$(CONFIG_THEAD_PLIC) += thead_plic.o
 else
 obj-$(CONFIG_SBI_IPI) += sbi_ipi.o
 endif

arch/riscv/lib/bootm.c

@@ -14,7 +14,11 @@
 #include <opensbi.h>
 #include <asm/byteorder.h>
 #include <asm/csr.h>
+#include <asm/io.h>
 #include <asm/smp.h>
+#include <asm/barrier.h>
+#include <asm/atomic.h>
+#include <asm/arch-thead/light-reset.h>
 #include <dm/device.h>
 #include <dm/root.h>
 #include <u-boot/zlib.h>
@@ -22,6 +26,12 @@
 DECLARE_GLOBAL_DATA_PTR;
 
 static struct fw_dynamic_info opensbi_info;
+static atomic_t _harts_count = ATOMIC_INITIALIZER(3);
+static ulong _load_start;
+static ulong _dtb_addr;
+static ulong _dyn_info_addr;
+
+extern void secondary_entry();
 
 __weak void board_quiesce_devices(void)
 {
@@ -81,6 +91,58 @@ static void boot_prep_linux(bootm_headers_t *images)
 	}
 }
 
+void next_stage(void)
+{
+	void (*next_entry)(unsigned long arg0,unsigned long arg1,unsigned long arg2);
+
+	next_entry	= (void (*))(_load_start);
+	ulong hartid = csr_read(CSR_MHARTID);
+
+	atomic_sub_return(&_harts_count, 1);
+	/*
+	 * set $a0 = hartid
+	 * set $a1 = $dtb_addr
+	 * set $a2 = $dyn_info_addr
+	 */
+	next_entry(hartid, _dtb_addr , _dyn_info_addr);
+}
+
+bool has_reset_sample(ulong dtb_addr)
+{
+	int node_offset;
+	node_offset = fdt_path_offset(dtb_addr, "/soc/reset-sample");
+	if (node_offset < 0) {
+		printf("## fdt has no reset_sample\n");
+		return false;
+	} else {
+		printf("## fdt has reset_sample\n");
+		return true;
+	}
+}
+
+static void reset_sample(void)
+{
+	ulong addr;
+	uint addr_l, addr_h;
+
+	// RESET ADDR
+	addr = (unsigned long)(void *)secondary_entry;
+	addr_h = (uint)(addr >> 32);
+	addr_l = (uint)(addr & 0xFFFFFFFF);
+	// writel(addr_h, (volatile void *)REG_C910_CORE0_RVBA_H);
+	// writel(addr_l, (volatile void *)REG_C910_CORE0_RVBA_L);
+	writel(addr_h, (volatile void *)REG_C910_CORE1_RVBA_H);
+	writel(addr_l, (volatile void *)REG_C910_CORE1_RVBA_L);
+	writel(addr_h, (volatile void *)REG_C910_CORE2_RVBA_H);
+	writel(addr_l, (volatile void *)REG_C910_CORE2_RVBA_L);
+	writel(addr_h, (volatile void *)REG_C910_CORE3_RVBA_H);
+	writel(addr_l, (volatile void *)REG_C910_CORE3_RVBA_L);
+
+	// RESET
+	writel(0x1F, (volatile void *)REG_C910_SWRST);
+	writel(0x1, (volatile void *)REG_PLIC_DELEGATE);
+}
+
 static void boot_jump_linux(bootm_headers_t *images, int flag)
 {
 	void (*kernel)(ulong hart, void *dtb, struct fw_dynamic_info *p);
@@ -98,12 +160,25 @@ static void boot_jump_linux(bootm_headers_t *images, int flag)
 
 	announce_and_cleanup(fake);
 
-	opensbi_info.magic = FW_DYNAMIC_INFO_MAGIC_VALUE;
-	opensbi_info.version = 0x1;
-	opensbi_info.next_addr = images->os.start;
-	opensbi_info.next_mode = FW_DYNAMIC_INFO_NEXT_MODE_S;
-	opensbi_info.options = 0;
-	opensbi_info.boot_hart = 0;
+	_load_start = kernel;
+	_dtb_addr = images->ft_addr;
+	_dyn_info_addr = (ulong)&opensbi_info;
+	if (!has_reset_sample(_dtb_addr)) {
+		opensbi_info.magic = FW_DYNAMIC_INFO_MAGIC_VALUE;
+		opensbi_info.version = 0x2;
+		opensbi_info.next_addr = images->os.start;
+		opensbi_info.next_mode = FW_DYNAMIC_INFO_NEXT_MODE_S;
+		opensbi_info.options = 0;
+		opensbi_info.boot_hart = 0;
+		reset_sample();
+	} else {
+		opensbi_info.magic = FW_DYNAMIC_INFO_MAGIC_VALUE;
+		opensbi_info.version = 0x1;
+		opensbi_info.next_addr = images->os.start;
+		opensbi_info.next_mode = FW_DYNAMIC_INFO_NEXT_MODE_S;
+		opensbi_info.options = 0;
+		opensbi_info.boot_hart = 0;
+	}
 
 	if (!fake) {
 		if (IMAGE_ENABLE_OF_LIBFDT && images->ft_len) {

arch/riscv/lib/interrupts.c

@@ -13,6 +13,11 @@
 #include <asm/system.h>
 #include <asm/encoding.h>
 
+__attribute__((weak)) int plic_init(void)
+{
+	return 0;
+}
+
 static void _exit_trap(ulong code, ulong epc, struct pt_regs *regs)
 {
 	static const char * const exception_code[] = {
@@ -47,6 +52,8 @@ static void _exit_trap(ulong code, ulong epc, struct pt_regs *regs)
 
 int interrupt_init(void)
 {
+	debug("[%s,%d]Initialize the plic\n", __func__, __LINE__);
+	plic_init();
 	return 0;
 }
 
@@ -72,10 +79,12 @@ ulong handle_trap(ulong cause, ulong epc, struct pt_regs *regs)
 	is_irq = (cause & MCAUSE_INT);
 	irq = (cause & ~MCAUSE_INT);
 
+	debug("[%s,%d]\n", __func__, __LINE__);
 	if (is_irq) {
 		switch (irq) {
 		case IRQ_M_EXT:
 		case IRQ_S_EXT:
+			debug("[%s,%d]\n", __func__, __LINE__);
 			external_interrupt(0);	/* handle external interrupt */
 			break;
 		case IRQ_M_TIMER:
@@ -90,6 +99,7 @@ ulong handle_trap(ulong cause, ulong epc, struct pt_regs *regs)
 		_exit_trap(cause, epc, regs);
 	}
 
+	debug("[%s,%d]\n", __func__, __LINE__);
 	return epc;
 }
 

arch/riscv/lib/reset.c

@@ -5,9 +5,21 @@
 
 #include <common.h>
 #include <command.h>
+#include <asm/io.h>
+
+#define AONSYS_RSTGEN_BASE			((void __iomem *)0xFFFFF44000UL)
+#define REG_RST_REQ_EN_0			(AONSYS_RSTGEN_BASE + 0x140)
+#define WDT0_SYS_RST_REQ			(1 << 8)
 
 static __attribute__((naked))void sys_wdt_reset(void)
 {
+    uint32_t data;
+
+	/* wdt0 reset enable */
+    data = readl(REG_RST_REQ_EN_0);
+	data |= WDT0_SYS_RST_REQ;
+	writel(data, REG_RST_REQ_EN_0);
+
     asm volatile (
     "1: \n\r"
         "li      a0, 0xFFEFC30000 \n\r"
@@ -21,7 +33,7 @@ static __attribute__((naked))void sys_wdt_reset(void)
 
 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
-	printf("resetting ...\n");
+    printf("resetting ...\n");
 
 	sys_wdt_reset();
 	hang();

arch/riscv/lib/thead_plic.c

@@ -0,0 +1,155 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2022, Liuw  <lw312886@alibaba-inc.com>
+ *
+ * U-Boot syscon driver for Thead's Platform Level Interrupt Controller (PLIC)
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <dm/device-internal.h>
+#include <dm/lists.h>
+#include <dm/uclass-internal.h>
+#include <regmap.h>
+#include <syscon.h>
+#include <asm/csr.h>
+#include <asm/io.h>
+#include <asm/syscon.h>
+#include <asm/global_data.h>
+#include <cpu.h>
+#include <linux/err.h>
+#include <asm/arch-thead/light-plic.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define PLIC_BASE_GET(void)						\
+	do {								\
+		long *ret;						\
+									\
+		if (!gd->arch.plic) {					\
+			ret = syscon_get_first_range(RISCV_SYSCON_PLIC); \
+			gd->arch.plic = ret;				\
+		}							\
+	} while (0)
+
+irq_handler_t irq_table[MAX_IRQ_NUM];
+
+void __iomem *plic_base = NULL;
+
+void external_interrupt(struct pt_regs *regs)
+{
+	void __iomem *claim;
+	irq_handler_t handler;
+	u32 irq_num;
+
+	debug("[%s,%d]\n", __func__, __LINE__);
+	if (!plic_base)
+		return;
+
+	debug("[%s,%d]\n", __func__, __LINE__);
+	claim = PLIC_CLAIM_REG(plic_base, 0);
+
+	while ((irq_num = readl(claim))) {
+		if (irq_num >= MAX_IRQ_NUM)
+			debug("Cannot find irq:%d\n", irq_num);
+		else {
+			handler = irq_table[irq_num];
+			if (handler)
+				handler();
+			writel(irq_num, claim);
+		}
+	}
+	debug("[%s,%d]\n", __func__, __LINE__);
+}
+
+static void plic_toggle(void __iomem *enable_base, int hwirq, int enable)
+{
+	u32 __iomem *reg = enable_base + (hwirq / 32) * sizeof(u32);
+	u32 hwirq_mask = 1 << (hwirq % 32);
+
+	if (enable)
+		writel(readl(reg) | hwirq_mask, reg);
+	else
+		writel(readl(reg) & ~hwirq_mask, reg);
+
+	debug("[%s,%d][0x%lx] = 0x%x\n", __func__, __LINE__,
+			(unsigned long)reg, readl(reg));
+}
+
+static void plic_set_threshold(void __iomem *thre_base, u32 threshold)
+{
+	writel(threshold, thre_base);
+	debug("[%s,%d][0x%lx] = 0x%x\n", __func__, __LINE__,
+			(unsigned long)thre_base, readl(thre_base));
+}
+
+static void plic_set_irq_priority(void __iomem *prio_base, int prio)
+{
+	writel(prio, prio_base);
+}
+
+int irq_handler_register(int irq, irq_handler_t handler)
+{
+	if (irq < 0 || irq >= MAX_IRQ_NUM) {
+		debug("invalid irq number to register\n");
+		return -EINVAL;
+	}
+
+	irq_table[irq] = handler;
+
+	return 0;
+}
+
+void arch_local_irq_enable(void)
+{
+	csr_set(CSR_MIE, MIE_MEIE);
+	csr_set(CSR_MSTATUS, SR_MIE);
+}
+
+void arch_local_irq_disable(void)
+{
+	csr_clear(CSR_MIE, MIE_MEIE);
+	csr_clear(CSR_MSTATUS, SR_MIE);
+}
+
+void irq_priority_set(int irq_id)
+{
+	plic_set_irq_priority(PLIC_PRIO_REG(gd->arch.plic, irq_id), 4);
+}
+
+void irq_enable(int hwirq)
+{
+	plic_toggle(PLIC_ENABLE_REG(gd->arch.plic, 0), hwirq, 1);
+}
+
+void irq_disable(int hwirq)
+{
+	plic_toggle(PLIC_ENABLE_REG(gd->arch.plic, 0), hwirq, 0);
+}
+
+int plic_init()
+{
+	PLIC_BASE_GET();
+	if (IS_ERR(gd->arch.plic))
+		return PTR_ERR(gd->arch.plic);
+
+	plic_base = gd->arch.plic;
+	debug("THEAD PLIC BASE: 0x%lx\n", (unsigned long)gd->arch.plic);
+
+	plic_set_threshold(PLIC_THRESHOLD_REG(gd->arch.plic, 0), 0);
+
+	arch_local_irq_enable(); //enale the global interrupt
+
+	return 0;
+}
+
+static const struct udevice_id thead_plic_ids[] = {
+	{ .compatible = "riscv,plic0", .data = RISCV_SYSCON_PLIC},
+	{ }
+};
+
+U_BOOT_DRIVER(thead_plic) = {
+	.name		= "thead_light_plic",
+	.id		= UCLASS_SYSCON,
+	.of_match	= thead_plic_ids,
+};

arch/sandbox/dts/Makefile

@@ -6,6 +6,7 @@ else
 dtb-$(CONFIG_SANDBOX) += sandbox.dtb
 endif
 dtb-$(CONFIG_UT_DM) += test.dtb
+dtb-$(CONFIG_CMD_EXTENSION) += overlay0.dtbo overlay1.dtbo
 
 targets += $(dtb-y)
 

arch/sandbox/dts/overlay0.dts

@@ -0,0 +1,9 @@
+/dts-v1/;
+/plugin/;
+
+&{/buttons} {
+	btn3 {
+		gpios = <&gpio_a 5 0>;
+		label = "button3";
+	};
+};

arch/sandbox/dts/overlay1.dts

@@ -0,0 +1,9 @@
+/dts-v1/;
+/plugin/;
+
+&{/buttons} {
+	btn4 {
+		gpios = <&gpio_a 5 0>;
+		label = "button4";
+	};
+};

board/sandbox/sandbox.c

@@ -12,6 +12,9 @@
 #include <os.h>
 #include <asm/test.h>
 #include <asm/u-boot-sandbox.h>
+#include <malloc.h>
+
+#include <extension_board.h>
 
 /*
  * Pointer to initial global data area
@@ -58,6 +61,26 @@ int board_init(void)
 	return 0;
 }
 
+#ifdef CONFIG_CMD_EXTENSION
+int extension_board_scan(struct list_head *extension_list)
+{
+	struct extension *extension;
+	int i;
+
+	for (i = 0; i < 2; i++) {
+		extension = calloc(1, sizeof(struct extension));
+		snprintf(extension->overlay, sizeof(extension->overlay), "overlay%d.dtbo", i);
+		snprintf(extension->name, sizeof(extension->name), "extension board %d", i);
+		snprintf(extension->owner, sizeof(extension->owner), "sandbox");
+		snprintf(extension->version, sizeof(extension->version), "1.1");
+		snprintf(extension->other, sizeof(extension->other), "Fictionnal extension board");
+		list_add_tail(&extension->list, extension_list);
+	}
+
+	return i;
+}
+#endif
+
 #ifdef CONFIG_BOARD_LATE_INIT
 int board_late_init(void)
 {

board/thead/light-c910/Kconfig

@@ -12,15 +12,15 @@ config PMIC_VOL_INIT
 
 config DDR_REGU_0V6
     int "uint in uv"
-    default 640000
+    default 600000
 
 config DDR_REGU_0V8
     int "uint in uv"
-    default 820000
+    default 800000
 
 config DDR_REGU_1V1
     int "uint in uv"
-    default 1200000
+    default 1100000
 
 config SYS_CPU
     default "c9xx"
@@ -34,19 +34,57 @@ config SYS_BOARD
 config SYS_CONFIG_NAME
     default "light-c910"
 
+config LIGHT_BOOT_FORCE_SEQ
+	bool "light boot force sequence"
+	default n
+
 config LIGHT_SEC_UPGRADE
     bool "light secure upgrade"
     default n
 
+config LIGHT_ANDROID_BOOT_IMAGE_VAL_A
+    bool "light board-a android image"
+    default n
+
+config AVB_USE_OEM_KEY
+    bool "AVB signature with OEM key"
+    default n
+
+config AVB_ROLLBACK_ENABLE
+    bool "AVB rollback index in RPMB"
+    default n
+
+config AVB_HW_ENGINE_ENABLE
+    bool "AVB Hardware cryptographic engine enable"
+    default n
+
+config LIGHT_ANDROID_BOOT_IMAGE_VAL_B
+    bool "light board-b android image"
+    default n
+
+config LIGHT_ANDROID_BOOT_IMAGE_VAL_LPI4A
+    bool "light board-lpi4a android image"
+    default n
+
+config LIGHT_ANDROID_BOOT_IMAGE_ANT_REF
+    bool "light board ant ref android image"
+    default n
+
 config LIGHT_SEC_BOOT_WITH_VERIFY_VAL_A
     bool "light board-a security boot with verification"
     default n
 
 config LIGHT_SEC_BOOT_WITH_VERIFY_VAL_B
-	bool "light board-b security boot with verification"
+    bool "light board-b security boot with verification"
+    default n
 
-config LIGHT_SEC_BOOT_WITH_VERIFY_ANT_EVT
-	bool "light ant evt security boot with verification"
+config LIGHT_SEC_BOOT_WITH_VERIFY_ANT_REF
+    bool "light ant ref security boot with verification"
+    default n
+
+config LIGHT_SEC_BOOT_WITH_VERIFY_LPI4A
+    bool "light lpi4a security boot with verification"
+    default n
 
 config TARGET_LIGHT_FPGA_FM_C910
     bool "light fullmask FPGA board"
@@ -60,16 +98,40 @@ config TARGET_LIGHT_FM_C910_VAL_A
     bool "light fullmask VAL board-a for system validation"
     default n
 
+config TARGET_LIGHT_FM_C910_A_REF
+    bool "light fullmask reference A board"
+    default n
+
 config TARGET_LIGHT_FM_C910_VAL_B
     bool "light fullmask VAL board-b for system validation"
     default n
 
-config TARGET_LIGHT_FM_C910_VAL_ANT_EVT
-    bool "light fullmask for ant-evt board "
+config TARGET_LIGHT_FM_C910_B_REF
+    bool "light fullmask reference B board"
+    default n
+
+config TARGET_LIGHT_FM_C910_VAL_ANT_REF
+    bool "light fullmask for ant-ref board "
     default n
 
 config TARGET_LIGHT_FM_C910_VAL_ANT_DISCRETE
-    bool "light fullmask for ant-evt board "
+    bool "light fullmask for ant-discrete board "
+    default n
+
+config TARGET_LIGHT_FM_C910_BEAGLE
+    bool "light fullmask for beagle board "
+    default n
+
+config TARGET_LIGHT_FM_C910_LPI4A
+    bool "light fullmask for Lichee Pi 4A board "
+    default n
+
+config TARGET_LIGHT_FM_C910_B_POWER
+    bool "light fullmask for light-b-power board "
+    default n
+
+config TARGET_LIGHT_FM_C910_MILKV_MELES
+    bool "light fullmask for Milk-V Meles board "
     default n
 
 config SYS_TEXT_BASE
@@ -78,13 +140,37 @@ config SYS_TEXT_BASE
 
 config SPL_TEXT_BASE
     hex
-    default 0xffe0000800 if LIGHT_SEC_BOOT_WITH_VERIFY_VAL_A || LIGHT_SEC_BOOT_WITH_VERIFY_VAL_B || LIGHT_SEC_BOOT_WITH_VERIFY_ANT_EVT
-    default 0xffe0000000 if !(LIGHT_SEC_BOOT_WITH_VERIFY_VAL_A || LIGHT_SEC_BOOT_WITH_VERIFY_VAL_B || LIGHT_SEC_BOOT_WITH_VERIFY_ANT_EVT)
+    default 0xffe0000800 if LIGHT_SEC_BOOT_WITH_VERIFY_VAL_A || LIGHT_SEC_BOOT_WITH_VERIFY_VAL_B || LIGHT_SEC_BOOT_WITH_VERIFY_ANT_REF || LIGHT_SEC_BOOT_WITH_VERIFY_LPI4A
+    default 0xffe0000000 if !(LIGHT_SEC_BOOT_WITH_VERIFY_VAL_A || LIGHT_SEC_BOOT_WITH_VERIFY_VAL_B || LIGHT_SEC_BOOT_WITH_VERIFY_ANT_REF || LIGHT_SEC_BOOT_WITH_VERIFY_LPI4A)
 
 config SPL_MAX_SIZE
     hex
     default 0x2f000
 
+config THEAD_PLIC
+	bool "Light PLIC Setting"
+	depends on RISCV_MMODE || SPL_RISCV_MMODE
+	select REGMAP
+	select SYSCON
+	default n
+	help
+	  The Thead PLIC block holds memory-mapped claim and pending registers
+	  associated with software interrupt.
+
+config THEAD_LIGHT_TIMER
+	bool "Light TIMER0 driver and test"
+	depends on THEAD_PLIC
+	default n
+	help
+	  The timer driver to verify the plic interrupt framework is ready
+
+config THEAD_LIGHT_DIGITAL_SENSOR
+	bool "Light Digital Sensor Setting"
+	depends on THEAD_PLIC
+	default n
+	help
+	  The security digital sensor driver
+
 config BOARD_SPECIFIC_OPTIONS
     def_bool y
     select RISCV_THEAD
@@ -166,6 +252,12 @@ config DDR_LP4_2133_SINGLERANK
         help
           Enabling this will support lpddr4 2133 singlerank configuration.
 
+config DDR_DDP
+	bool "LPDDR4/4X Dual Die Package support"
+	help
+	  Enabling this will support ddr Dual Die Package configuration.
+	  e.g. to support 8GB ddr device with 17-bit row address (16:0)
+
 config DDR_H32_MODE
         bool "LPDDR4/4X 32bit mode configuration"
         help

board/thead/light-c910/Makefile

@@ -55,9 +55,12 @@ endif # // CONFIG_TARGET_LIGHT_FPGA_FM_C910
 else # // CONFIG_SPL_BUILD
 obj-y += light.o
 obj-y += board.o
+obj-$(CONFIG_THEAD_LIGHT_TIMER) += timer.o
+obj-$(CONFIG_THEAD_LIGHT_DIGITAL_SENSOR) += digital_sensor.o digital_sensor_test.o
 obj-y += clock_config.o
 obj-y += sec_check.o
 obj-y += boot.o
+obj-y += sbmeta/sbmeta.o
 ifndef CONFIG_TARGET_LIGHT_FPGA_FM_C910
 obj-$(CONFIG_LPDDR) += $(DDR_SRC_PATH)/ddr_common_func.o
 obj-$(CONFIG_LPDDR) += $(DDR_SRC_PATH)/common_lib.o
@@ -65,4 +68,6 @@ endif
 
 obj-y += light-sv/pll_io_test.o
 obj-y += light-sv/adc_test.o
+obj-y += version_rollback.o
+obj-$(CONFIG_AVB_VERIFY) += secimg_load.o
 endif

board/thead/light-c910/board.c

@@ -9,10 +9,13 @@
 #include <dwc3-uboot.h>
 #include <usb.h>
 #include <cpu_func.h>
+#include <asm/gpio.h>
+#include <abuf.h>
+#include "sec_library.h"
 
 #ifdef CONFIG_USB_DWC3
 static struct dwc3_device dwc3_device_data = {
-	.maximum_speed = USB_SPEED_HIGH,
+	.maximum_speed = USB_SPEED_SUPER,
 	.dr_mode = USB_DR_MODE_PERIPHERAL,
 	.index = 0,
 };
@@ -50,9 +53,11 @@ int g_dnl_board_usb_cable_connected(void)
 
 #define C906_RST_ADDR_L		0xfffff48048
 #define C906_RST_ADDR_H		0xfffff4804C
-#define C906_START_ADDRESS_L	0xc0000000
-#define C906_START_ADDRESS_H	0xff
-#define C910_C906_START_ADDRESS	0xffc0000000
+
+#define C906_START_ADDRESS_L	0x32000000
+#define C906_START_ADDRESS_H	0x00
+#define C910_C906_START_ADDRESS	0x0032000000
+
 #define C906_CPR_IPCG_ADDRESS   0xFFCB000010
 #define C906_IOCTL_GPIO_SEL_ADDRESS     0xFFCB01D000
 #define C906_IOCTL_AF_SELH_ADDRESS      0xFFCB01D008
@@ -111,3 +116,76 @@ int do_bootslave(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
 	return 0;
 }
 #endif
+
+static void light_c910_set_gpio_output_high(void)
+{
+	ofnode node;
+	struct gpio_desc select_gpio;
+
+	printf("%s: trying to set gpio output high\n", __func__);
+
+	node = ofnode_path("/config");
+	if (!ofnode_valid(node)) {
+		printf("%s: no /config node?\n", __func__);
+		return;
+	}
+
+	if (gpio_request_by_name_nodev(node, "select-gpio", 0,
+				       &select_gpio, GPIOD_IS_OUT)) {
+		printf("%s: could not find a /config/select-gpio\n", __func__);
+		return;
+	}
+
+	dm_gpio_set_value(&select_gpio, 1);
+}
+
+int misc_init_r(void)
+{
+	light_c910_set_gpio_output_high();
+
+	return 0;
+}
+
+#ifdef CONFIG_BOARD_RNG_SEED
+const char pre_gen_seed[128] = {211, 134, 226, 116, 1, 13, 224, 196, 88, 213, 188, 219, 128, 41, 231, 228, 129, 123, 173, 234, 219, 79, 152, 154, 169, 27, 183, 166, 52, 21, 118, 7, 155, 89, 124, 156, 102, 92, 96, 190, 49, 28, 154, 177, 69, 129, 149, 199, 253, 66, 177, 216, 146, 73, 114, 59, 100, 41, 225, 152, 62, 88, 160, 217, 177, 28, 117, 23, 120, 213, 213, 169, 242, 111, 90, 55, 241, 239, 254, 238, 50, 175, 198, 196, 248, 56, 255, 92, 97, 224, 245, 160, 56, 149, 121, 233, 177, 239, 0, 41, 196, 214, 210, 182, 69, 44, 238, 54, 27, 236, 36, 77, 156, 234, 17, 148, 34, 16, 241, 132, 241, 230, 36, 41, 123, 157, 19, 44};
+/* Use hardware rng to seed Linux random. */
+int board_rng_seed(struct abuf *buf)
+{
+	size_t len = 128;
+	uint8_t *data = NULL;
+	int sc_err = SC_FAIL;
+
+	/* abuf is working up in asynchronization mode, so the memory usage for random data storage must
+	   be allocated first. */
+	data = malloc(len);
+	if (!data) {
+		printf("Fail to allocate memory, using pre-defined entropy\n");
+		return -1;
+	}
+
+#if defined(CONFIG_AVB_HW_ENGINE_ENABLE)
+	/* We still use pre-define entropy data in case hardware random engine does not work */
+	sc_err = csi_sec_library_init();
+	if (sc_err != SC_OK) {
+		printf("Fail to initialize sec library, using pre-defined entropy\n");
+		goto _err;
+	}
+
+	sc_err = sc_rng_get_random_bytes(data, len);
+	if (sc_err != SC_OK) {
+		printf("Fail to retrieve random data, using pre-defined entropy\n");
+		goto _err;
+	}
+
+	abuf_init_set(buf, data, len);
+	return 0;
+
+_err:
+#endif
+	/* use pre-defined random data in case of the random engine is disable */
+	memcpy(data, pre_gen_seed, len);
+	abuf_init_set(buf, data, len);
+
+	return 0;
+}
+#endif

board/thead/light-c910/boot.c

@@ -7,26 +7,31 @@
 #include <dm.h>
 #include <fdt_support.h>
 #include <fdtdec.h>
+#include <mmc.h>
 #include <opensbi.h>
 #include <asm/csr.h>
 #include <asm/arch-thead/boot_mode.h>
 #include "../../../lib/sec_library/include/csi_efuse_api.h"
-
-
+#include "../../../lib/sec_library/include/sec_crypto_sha.h"
+#include "../../../lib/sec_library/include/kdf.h"
+#include "../../../lib/sec_library/include/sec_crypto_mac.h"
 
 #if CONFIG_IS_ENABLED(LIGHT_SEC_UPGRADE)
 
-/* The micro is used to enable NON-COT boot with non-signed image */
+/* The macro is used to enable NON-COT boot with non-signed image */
 #define LIGHT_NON_COT_BOOT	1
 
-/* The micro is used to enable uboot version in efuse */
+/* The macro is used to enable uboot version in efuse */
 #define	LIGHT_UBOOT_VERSION_IN_ENV	1
 
-/* The micro is used to enble RPMB ACCESS KEY from KDF */
+/* The macro is used to enble RPMB ACCESS KEY from KDF */
 //#define LIGHT_KDF_RPMB_KEY	1
 
+/* The macro is used to enable secure image version check in boot */
+//#define LIGHT_IMG_VERSION_CHECK_IN_BOOT	1
+
 /* the sample rpmb key is only used for testing */
-#ifndef LIGHT_KDF_RPMB_KEY 
+#ifndef LIGHT_KDF_RPMB_KEY
 static const unsigned char emmc_rpmb_key_sample[32] = {0x33, 0x22, 0x11, 0x00, 0x77, 0x66, 0x55, 0x44, \
 												0xbb, 0xaa, 0x99, 0x88, 0xff, 0xee, 0xdd, 0xcc, \
 												0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, \
@@ -34,17 +39,131 @@ static const unsigned char emmc_rpmb_key_sample[32] = {0x33, 0x22, 0x11, 0x00, 0
 #endif
 static unsigned int upgrade_image_version = 0;
 
+#define RPMB_EMMC_CID_SIZE 16
+#define RPMB_CID_PRV_OFFSET             9
+#define RPMB_CID_CRC_OFFSET             15
+#ifdef LIGHT_KDF_RPMB_KEY
+static int tee_rpmb_key_gen(uint8_t* key, uint32_t * length)
+{
+	uint32_t data[RPMB_EMMC_CID_SIZE / 4];
+    uint8_t huk[32];
+    uint32_t huk_len;
+	struct mmc *mmc = find_mmc_device(0);
+	int i;
+	sc_mac_t mac_handle;
+	int ret = 0;
+
+	if (!mmc)
+		return -1;
+
+	if (!mmc->ext_csd)
+		return -1;
+
+	for (i = 0; i < ARRAY_SIZE(mmc->cid); i++)
+		data[i] = cpu_to_be32(mmc->cid[i]);
+	/*
+	 * PRV/CRC would be changed when doing eMMC FFU
+	 * The following fields should be masked off when deriving RPMB key
+	 *
+	 * CID [55: 48]: PRV (Product revision)
+	 * CID [07: 01]: CRC (CRC7 checksum)
+	 * CID [00]: not used
+	 */
+	memset((void *)((uint64_t)data + RPMB_CID_PRV_OFFSET), 0, 1);
+	memset((void *)((uint64_t)data + RPMB_CID_CRC_OFFSET), 0, 1);
+
+    /* Step1: Derive HUK from KDF function */
+	ret = csi_kdf_gen_hmac_key(huk, &huk_len);
+	if (ret) {
+		printf("kdf gen hmac key faild[%d]\r\n", ret);
+		return -1;
+	}
+
+    /* Step2: Using HUK and data to generate RPMB key */
+	ret = sc_mac_init(&mac_handle, 0);
+	if (ret) {
+		printf("mac init faild[%d]\r\n", ret);
+		ret = -1;
+		return -1;
+	}
+
+	/* LSB 16 bytes are used as key */
+	ret = sc_mac_set_key(&mac_handle, huk, 16);
+	if (ret) {
+		printf("mac set key faild[%d]\r\n", ret);
+		ret = -1;
+		goto func_exit;
+	}
+
+	ret = sc_mac_calc(&mac_handle, SC_SHA_MODE_256, (uint8_t *)&data, sizeof(data), key, length);
+	if (ret) {
+		printf("mac calc faild[%d]\r\n", ret);
+		ret = -1;
+		goto func_exit;
+	}
+
+func_exit:
+	sc_mac_uninit(&mac_handle);
+
+	return ret;
+
+}
+#endif
+
+int csi_rpmb_write_access_key(void)
+{
+#ifdef LIGHT_KDF_RPMB_KEY
+    unsigned long *temp_rpmb_key_addr = NULL;
+    char runcmd[64] = {0};
+    uint8_t blkdata[256] = {0};
+    __attribute__((__aligned__(8))) uint8_t kdf_rpmb_key[32];
+    uint32_t kdf_rpmb_key_length = 0;
+	int ret = 0;
+    /* Step1: retrive RPMB key from KDF function */
+	ret = tee_rpmb_key_gen(kdf_rpmb_key, &kdf_rpmb_key_length);
+	if (ret != 0) {
+		return -1;
+	}
+    /* Make sure rpmb key length must be 32*/
+    if (kdf_rpmb_key_length != 32) {
+        return -1;
+    }
+
+	temp_rpmb_key_addr = (unsigned long *)kdf_rpmb_key;
+
+    /* Step2: check whether RPMB key is available */
+    sprintf(runcmd, "mmc rpmb read 0x%lx 0 1 0x%lx", (unsigned long)blkdata, (unsigned long)temp_rpmb_key_addr);
+	ret = run_command(runcmd, 0);
+    if (ret == CMD_RET_SUCCESS) {
+        return -1;
+    }
+
+    /* Step3: Write RPMB key at once */
+    sprintf(runcmd, "mmc rpmb key 0x%lx", (unsigned long)temp_rpmb_key_addr);
+	ret = run_command(runcmd, 0);
+    if (ret != CMD_RET_SUCCESS) {
+        return -1;
+    }
+    return 0;
+#else
+    return 1;
+#endif
+}
+
 int csi_tf_get_image_version(unsigned int *ver)
 {
 	char runcmd[64] = {0};
 	unsigned char blkdata[256];
+	int ret = 0;
 
 	/* tf version reside in RPMB block#0, offset#16*/
 	sprintf(runcmd, "mmc rpmb read 0x%lx 0 1", (unsigned long)blkdata);
-	run_command(runcmd, 0);
-	*ver = (blkdata[16] << 8) + blkdata[17];
+	ret = run_command(runcmd, 0);
+	if (ret == 0) {
+		*ver = (blkdata[16] << 8) + blkdata[17];
+	}
 
-	return 0;
+	return ret;
 }
 
 int csi_tf_set_image_version(unsigned int ver)
@@ -60,9 +179,9 @@ int csi_tf_set_image_version(unsigned int ver)
 	blkdata[17] = ver & 0xFF;
 
 	/* tf version reside in RPMB block#0, offset#16*/
-#ifndef LIGHT_KDF_RPMB_KEY 
+#ifndef LIGHT_KDF_RPMB_KEY
 	temp_rpmb_key_addr = (unsigned long *)emmc_rpmb_key_sample;
-#else 
+#else
 	uint8_t kdf_rpmb_key[32];
 	uint32_t kdf_rpmb_key_length = 0;
 	int ret = 0;
@@ -88,11 +207,27 @@ int csi_tee_get_image_version(unsigned int *ver)
 {
 	char runcmd[64] = {0};
 	unsigned char blkdata[256];
+	int ret = 0;
 
 	/* tf version reside in RPMB block#0, offset#0*/
 	sprintf(runcmd, "mmc rpmb read 0x%lx 0 1", (unsigned long)blkdata);
+	ret = run_command(runcmd, 0);
+	if (ret == 0) {
+		*ver = (blkdata[0] << 8) + blkdata[1];
+	}
+
+	return ret;
+}
+
+int csi_kernel_get_image_version(unsigned int *ver)
+{
+	char runcmd[64] = {0};
+	unsigned char blkdata[256];
+
+	/* kernel version reside in RPMB block#0, offset#32*/
+	sprintf(runcmd, "mmc rpmb read 0x%lx 0 1", (unsigned long)blkdata);
 	run_command(runcmd, 0);
-	*ver = (blkdata[0] << 8) + blkdata[1];
+	*ver = (blkdata[32] << 8) + blkdata[33];
 
 	return 0;
 }
@@ -110,9 +245,9 @@ int csi_tee_set_image_version(unsigned int ver)
 	blkdata[1] = ver & 0xFF;
 
 	/* tf version reside in RPMB block#0, offset#16*/
-#ifndef LIGHT_KDF_RPMB_KEY 
+#ifndef LIGHT_KDF_RPMB_KEY
 	temp_rpmb_key_addr = (unsigned long *)emmc_rpmb_key_sample;
-#else 
+#else
 	uint8_t kdf_rpmb_key[32];
 	uint32_t kdf_rpmb_key_length = 0;
 	int ret = 0;
@@ -133,6 +268,57 @@ int csi_tee_set_upgrade_version(void)
 	return csi_tee_set_image_version(upgrade_image_version);
 }
 
+int csi_sbmeta_get_image_version(unsigned int *ver)
+{
+	char runcmd[64] = {0};
+	unsigned char blkdata[256];
+	int ret = 0;
+
+	/* sbmeta version reside in RPMB block#0, offset#48*/
+	sprintf(runcmd, "mmc rpmb read 0x%lx 0 1", (unsigned long)blkdata);
+	ret = run_command(runcmd, 0);
+	if (ret == 0) {
+		*ver = (blkdata[48] << 8) + blkdata[49];
+	}
+
+	return ret;
+}
+
+int csi_sbmeta_set_image_version(unsigned int ver)
+{
+	char runcmd[64] = {0};
+	unsigned char blkdata[256];
+	unsigned long *temp_rpmb_key_addr = NULL;
+
+	/* sbmeta version reside in RPMB block#0, offset#48*/
+	sprintf(runcmd, "mmc rpmb read 0x%lx 0 1", (unsigned long)blkdata);
+	run_command(runcmd, 0);
+	blkdata[48] = (ver & 0xFF00) >> 8;
+	blkdata[49] = ver & 0xFF;
+	/* sbmeta version reside in RPMB block#0, offset#48*/
+#ifndef LIGHT_KDF_RPMB_KEY
+	temp_rpmb_key_addr = (unsigned long *)emmc_rpmb_key_sample;
+#else
+	uint8_t kdf_rpmb_key[32];
+	uint32_t kdf_rpmb_key_length = 0;
+	int ret = 0;
+	ret = csi_kdf_gen_hmac_key(kdf_rpmb_key, &kdf_rpmb_key_length);
+	if (ret != 0) {
+		return -1;
+	}
+	temp_rpmb_key_addr = (unsigned long *)kdf_rpmb_key;
+#endif
+	sprintf(runcmd, "mmc rpmb write 0x%lx 0 1 0x%lx", (unsigned long)blkdata, (unsigned long)temp_rpmb_key_addr);
+	run_command(runcmd, 0);
+
+	return 0;
+}
+
+int csi_sbmeta_set_upgrade_version(void)
+{
+	return csi_sbmeta_set_image_version(upgrade_image_version);
+}
+
 int csi_uboot_get_image_version(unsigned int *ver)
 {
 #ifdef	LIGHT_UBOOT_VERSION_IN_ENV
@@ -160,7 +346,7 @@ int csi_uboot_get_image_version(unsigned int *ver)
 	unsigned int ver_x = 0;
 	int ret = 0;
 
-	ret = csi_efuse_api_int();
+	ret = csi_efuse_api_init();
 	if (ret) {
 		printf("efuse api init fail \n");
 		return -1;
@@ -186,7 +372,6 @@ int csi_uboot_set_image_version(unsigned int ver)
 	//TODO
 	unsigned long long uboot_ver = 0;
 	unsigned char ver_x = (ver & 0xff00) >> 8;
-    char ver_str[32] = {0};
 
 	uboot_ver = env_get_hex("uboot_version", 0xffffffffffffffff);
 
@@ -209,7 +394,7 @@ int csi_uboot_set_image_version(unsigned int ver)
 		return 0;
 	}
 
-	ret = csi_efuse_api_int();
+	ret = csi_efuse_api_init();
 	if (ret) {
 		printf("efuse api init fail \n");
 		return -1;
@@ -266,6 +451,109 @@ int verify_image_version_rule(unsigned int new_ver, unsigned int cur_ver)
 	return 0;
 }
 
+int check_image_version_rule(unsigned int new_ver, unsigned int cur_ver)
+{
+	unsigned char new_ver_x = 0, new_ver_y = 0;
+	unsigned char cur_ver_x = 0, cur_ver_y = 0;
+
+	/* Get secure version X from image version X.Y */
+	new_ver_x = (new_ver & 0xFF00) >> 8;
+	new_ver_y = new_ver & 0xFF;
+	cur_ver_x = (cur_ver & 0xFF00) >> 8;
+	cur_ver_y = cur_ver & 0xFF;
+
+    (void)new_ver_y;
+    (void)cur_ver_y;
+
+	/* Ensure image version must be less than expected version */
+	if (new_ver_x < cur_ver_x) {
+		return -1;
+	}
+
+	return 0;
+}
+
+int check_tf_version_in_boot(unsigned long tf_addr)
+{
+	int ret = 0;
+	unsigned int img_version = 0;
+	unsigned int expected_img_version = 0;
+	
+	img_version = get_image_version(tf_addr);
+	if (img_version == 0) {
+		printf("get tf image version fail\n");
+		return -1;
+	}
+
+	ret = csi_tf_get_image_version(&expected_img_version);
+	if (ret != 0) {
+		printf("Get tf expected img version fail\n");
+		return -1;
+	}
+
+	ret = check_image_version_rule(img_version, expected_img_version);
+	if (ret != 0) {
+		printf("Image version breaks the rule\n");
+		return -1;
+	}
+
+	return 0;
+}
+
+int check_tee_version_in_boot(unsigned long tee_addr)
+{
+	int ret = 0;
+	unsigned int img_version = 0;
+	unsigned int expected_img_version = 0;
+	
+	img_version = get_image_version(tee_addr);
+	if (img_version == 0) {
+		printf("get tee image version fail\n");
+		return -1;
+	}
+
+	ret = csi_tee_get_image_version(&expected_img_version);
+	if (ret != 0) {
+		printf("Get tee expected img version fail\n");
+		return -1;
+	}
+
+	ret = check_image_version_rule(img_version, expected_img_version);
+	if (ret != 0) {
+		printf("Image version breaks the rule\n");
+		return -1;
+	}
+
+	return 0;
+}
+
+int check_sbmeta_version_in_boot(unsigned long sbmeta_addr)
+{
+	int ret = 0;
+	unsigned int img_version = 0;
+	unsigned int expected_img_version = 0;
+
+	img_version = get_image_version(sbmeta_addr);
+	if (img_version == 0) {
+		printf("get sbmeta image version fail\n");
+		return -1;
+	}
+
+	ret = csi_sbmeta_get_image_version(&expected_img_version);
+	if (ret != 0) {
+		printf("Get sbmeta expected img version fail\n");
+		return -1;
+	}
+
+	ret = check_image_version_rule(img_version, expected_img_version);
+	if (ret != 0) {
+		printf("Image version breaks the rule\n");
+		return -1;
+	}
+
+	return 0;
+}
+
 int light_vimage(int argc, char *const argv[])
 {
 	int ret = 0;
@@ -273,14 +561,14 @@ int light_vimage(int argc, char *const argv[])
 	unsigned int new_img_version = 0;
 	unsigned int cur_img_version = 0;
     char imgname[32] = {0};
-    
-	if (argc < 3) 
+
+	if (argc < 3)
 		return CMD_RET_USAGE;
-	
+
 	/* Parse input parameters */
 	vimage_addr = simple_strtoul(argv[1], NULL, 16);
 	strcpy(imgname, argv[2]);
-	
+
 	/* Retrieve desired information from image header */
 	new_img_version = get_image_version(vimage_addr);
 	if (new_img_version == 0) {
@@ -307,13 +595,27 @@ int light_vimage(int argc, char *const argv[])
 			printf("Get tee img version fail\n");
 			return CMD_RET_FAILURE;
 		}
-	} else if (strcmp(imgname, UBOOT_PART_NAME) == 0) {
+	} else if (strcmp(imgname, KERNEL_PART_NAME) == 0){
+
+		ret = csi_kernel_get_image_version(&cur_img_version);
+		if (ret != 0) {
+			printf("Get kernel img version fail\n");
+			return CMD_RET_FAILURE;
+		}
+	} else if (strcmp(imgname, SBMETA_PART_NAME) == 0){
+
+		ret = csi_sbmeta_get_image_version(&cur_img_version);
+		if (ret != 0) {
+			printf("Get sbmeta img version fail\n");
+			return CMD_RET_FAILURE;
+		}
+	}  else if (strcmp(imgname, UBOOT_PART_NAME) == 0) {
 		ret = csi_uboot_get_image_version(&cur_img_version);
 		if (ret != 0) {
 			printf("Get uboot img version fail\n");
 			return CMD_RET_FAILURE;
-		} 
-		
+		}
+
 		// Check uboot maximization version > 64
 		if (((new_img_version & 0xFF00) >> 8) > UBOOT_MAX_VER) {
 			printf("UBOOT Image version has reached to max-version\n");
@@ -351,11 +653,21 @@ int light_vimage(int argc, char *const argv[])
 		if (ret != 0) {
 			return CMD_RET_FAILURE;
 		}
+	} else if (strcmp(imgname, KERNEL_PART_NAME) == 0) {
+		ret = verify_customer_image(T_KRLIMG, vimage_addr);
+		if (ret != 0) {
+			return CMD_RET_FAILURE;
+		}
 	} else if (strcmp(imgname, UBOOT_PART_NAME) == 0) {
 		ret = verify_customer_image(T_UBOOT, vimage_addr);
 		if (ret != 0) {
 			return CMD_RET_FAILURE;
 		}
+	} else if (strcmp(imgname, SBMETA_PART_NAME) == 0) {
+		ret = verify_customer_image(T_SBMETA, vimage_addr);
+		if (ret != 0) {
+			return CMD_RET_FAILURE;
+		}
 	} else {
 		printf("Error: unknow image name\n");
 		return CMD_RET_FAILURE;
@@ -375,6 +687,9 @@ int light_secboot(int argc, char * const argv[])
 	printf("\n\n");
 	printf("Now, we start to verify all trust firmware before boot kernel !\n");
 
+    /* Enject RPMB KEY directly in startup */
+    csi_rpmb_write_access_key();
+
 	/* Initialize secure basis of functions */
 	ret = csi_sec_init();
 	if (ret != 0) {
@@ -383,6 +698,13 @@ int light_secboot(int argc, char * const argv[])
 
 	/* Step1. Check and verify TF image */
 	if (image_have_head(LIGHT_TF_FW_TMP_ADDR) == 1) {
+#ifdef LIGHT_IMG_VERSION_CHECK_IN_BOOT
+		printf("check TF version in boot \n");
+		ret = check_tf_version_in_boot(LIGHT_TF_FW_TMP_ADDR);
+		if (ret != 0) {
+			return CMD_RET_FAILURE;
+		}
+#endif
 
 		printf("Process TF image verification ...\n");
 		ret = verify_customer_image(T_TF, LIGHT_TF_FW_TMP_ADDR);
@@ -408,6 +730,14 @@ int light_secboot(int argc, char * const argv[])
 
 	/* Step2. Check and verify TEE image */
 	if (image_have_head(tee_addr) == 1) {
+#ifdef LIGHT_IMG_VERSION_CHECK_IN_BOOT
+		printf("check TEE version in boot \n");
+		ret = check_tee_version_in_boot(tee_addr);
+		if (ret != 0) {
+			return CMD_RET_FAILURE;
+		}
+#endif
+
 		printf("Process TEE image verification ...\n");
 		ret = verify_customer_image(T_TEE, tee_addr);
 		if (ret != 0) {
@@ -427,6 +757,29 @@ int light_secboot(int argc, char * const argv[])
 			return CMD_RET_FAILURE;
 		#endif
 	}
+
+    // /* Step3. Check and verify light kernel image */
+	// if (image_have_head(kernel_addr) == 1) {
+	// 	printf("Process kernel image verification ...\n");
+	// 	ret = verify_customer_image(T_KRLIMG, kernel_addr);
+	// 	if (ret != 0) {
+	// 		return CMD_RET_FAILURE;
+	// 	}
+
+	// 	kernel_image_size = get_image_size(kernel_addr);
+	// 	printf("Kernel image size: %d\n", kernel_image_size);
+	// 	if (kernel_image_size < 0) {
+	// 		printf("GET kernel image size error\n");
+	// 		return CMD_RET_FAILURE;
+	// 	}
+
+	// 	memmove((void *)kernel_addr, (const void *)(kernel_addr + HEADER_SIZE), kernel_image_size);
+	// } else {
+	// 	#ifndef LIGHT_NON_COT_BOOT
+	// 		return CMD_RET_FAILURE;
+	// 	#endif
+	// }
+
 	return 0;
 }
 
@@ -435,16 +788,40 @@ void sec_firmware_version_dump(void)
 	unsigned int tf_ver = 0;
 	unsigned int tee_ver = 0;
 	unsigned int uboot_ver = 0;
+	unsigned int sbmeta_ver = 0;
+	unsigned int tf_ver_env = 0;
+	unsigned int tee_ver_env = 0;
+	unsigned int sbmeta_ver_env = 0;
 
 	csi_uboot_get_image_version(&uboot_ver);
 	csi_tf_get_image_version(&tf_ver);
 	csi_tee_get_image_version(&tee_ver);
+	csi_sbmeta_get_image_version(&sbmeta_ver);
+	/* Keep sync with version in RPMB, the Following version could be leveraged by OTA client */
+	tee_ver_env = env_get_hex("tee_version", 0);
+	tf_ver_env = env_get_hex("tf_version", 0);
+	sbmeta_ver_env = env_get_hex("sbmeta_version", 0);
+	if ((tee_ver_env != tee_ver) && (tee_ver != 0)) {
+		env_set_hex("tee_version", tee_ver);
+		run_command("saveenv", 0);
+	}
+
+	if ((tf_ver_env != tf_ver) && (tf_ver != 0)) {
+		env_set_hex("tf_version", tf_ver);
+		run_command("saveenv", 0);
+	}
+
+	if ((sbmeta_ver_env != sbmeta_ver) && (sbmeta_ver != 0)) {
+		env_set_hex("sbmeta_version", sbmeta_ver);
+		run_command("saveenv", 0);
+	}
 
 	printf("\n\n");
 	printf("Secure Firmware image version info: \n");
 	printf("uboot Firmware v%d.0\n", (uboot_ver & 0xff00) >> 8);
 	printf("Trust Firmware v%d.%d\n", (tf_ver & 0xff00) >> 8, tf_ver & 0xff);
 	printf("TEE OS v%d.%d\n", (tee_ver & 0xff00) >> 8, tee_ver & 0xff);
+	printf("SBMETA v%d.%d\n", (sbmeta_ver & 0xff00) >> 8, sbmeta_ver & 0xff);
 	printf("\n\n");
 }
 
@@ -452,6 +829,8 @@ void sec_upgrade_thread(void)
 {
 	const unsigned long temp_addr=0x200000;
 	char runcmd[80];
+    uint8_t * image_buffer = NULL;
+    uint8_t * image_malloc_buffer = NULL;
 	int ret = 0;
 	unsigned int sec_upgrade_flag = 0;
 	unsigned int upgrade_file_size = 0;
@@ -459,13 +838,11 @@ void sec_upgrade_thread(void)
 	sec_upgrade_flag = env_get_hex("sec_upgrade_mode", 0);
 	if (sec_upgrade_flag == 0)
 		return;
-	
 	printf("bootstrap: sec_upgrade_flag: %x\n", sec_upgrade_flag);
 	if (sec_upgrade_flag == TF_SEC_UPGRADE_FLAG) {
-		
 		/* STEP 1: read upgrade image (trust_firmware.bin) from stash partition */
 		printf("read upgrade image (trust_firmware.bin) from stash partition \n");
-		sprintf(runcmd, "ext4load mmc 0:5 0x%p trust_firmware.bin", (void *)temp_addr);
+		sprintf(runcmd, "ext4load mmc 0:4 0x%p trust_firmware.bin", (void *)temp_addr);
 		printf("runcmd:%s\n", runcmd);
 		ret = run_command(runcmd, 0);
 		if (ret != 0) {
@@ -476,6 +853,15 @@ void sec_upgrade_thread(void)
 		upgrade_file_size = env_get_hex("filesize", 0);
 		printf("upgrade file size: %d\n", upgrade_file_size);
 
+        /*store image to temp buffer as temp_addr may be decrypted*/
+        image_malloc_buffer = malloc(upgrade_file_size);
+        if ( image_malloc_buffer == NULL ) {
+			image_buffer = (uint8_t*)temp_addr + upgrade_file_size;
+		} else {
+            image_buffer = image_malloc_buffer;
+        }
+        memcpy(image_buffer, (void*)temp_addr, upgrade_file_size);
+
 		/* STEP 2: verify its authentiticy here */
 		sprintf(runcmd, "vimage 0x%p tf", (void *)temp_addr);
 		printf("runcmd:%s\n", runcmd);
@@ -487,7 +873,7 @@ void sec_upgrade_thread(void)
 
 		/* STEP 3: update tf partition */
 		printf("read upgrade image (trust_firmware.bin) into tf partition \n");
-		sprintf(runcmd, "ext4write mmc 0:3 0x%p /trust_firmware.bin 0x%x", (void *)temp_addr, upgrade_file_size);
+		sprintf(runcmd, "ext4write mmc 0:3 0x%p /trust_firmware.bin 0x%x", (void *)image_buffer, upgrade_file_size);
 		printf("runcmd:%s\n", runcmd);
 		ret = run_command(runcmd, 0);
 		if (ret != 0) {
@@ -509,11 +895,15 @@ _upgrade_tf_exit:
 		run_command("saveenv", 0);
 		run_command("reset", 0);
 
+        if ( image_malloc_buffer != NULL ) {
+            free(image_malloc_buffer);
+            image_malloc_buffer = NULL;
+        }
 	} else if (sec_upgrade_flag == TEE_SEC_UPGRADE_FLAG) {
 
  		/* STEP 1: read upgrade image (tee.bin) from stash partition */
 		printf("read upgrade image (tee.bin) from stash partition \n");
-		sprintf(runcmd, "ext4load mmc 0:5 0x%p tee.bin", (void *)temp_addr);
+		sprintf(runcmd, "ext4load mmc 0:4 0x%p tee.bin", (void *)temp_addr);
 		printf("runcmd:%s\n", runcmd);
 		ret = run_command(runcmd, 0);
 		if (ret != 0) {
@@ -524,6 +914,15 @@ _upgrade_tf_exit:
 		upgrade_file_size = env_get_hex("filesize", 0);
 		printf("TEE upgrade file size: %d\n", upgrade_file_size);
 
+        /*store image to temp buffer as temp_addr may be decrypted*/
+        image_malloc_buffer = malloc(upgrade_file_size);
+        if ( image_malloc_buffer == NULL ) {
+			image_buffer = (uint8_t*)temp_addr + upgrade_file_size;
+		} else {
+            image_buffer = image_malloc_buffer;
+        }
+        memcpy(image_buffer, (void*)temp_addr, upgrade_file_size);
+
 		/* STEP 2: verify its authentiticy here */
 		sprintf(runcmd, "vimage 0x%p tee", (void *)temp_addr);
 		printf("runcmd:%s\n", runcmd);
@@ -534,8 +933,8 @@ _upgrade_tf_exit:
 		}
 
 		/* STEP 3: update tee partition */
-		printf("read upgrade image (tee.bin) into tf partition \n");
-		sprintf(runcmd, "ext4write mmc 0:4 0x%p /tee.bin 0x%x", (void *)temp_addr, upgrade_file_size);
+		printf("read upgrade image (tee.bin) into sbmeta partition \n");
+		sprintf(runcmd, "ext4write mmc 0:3 0x%p /tee.bin 0x%x", (void *)image_buffer, upgrade_file_size);
 		printf("runcmd:%s\n", runcmd);
 		ret = run_command(runcmd, 0);
 		if (ret != 0) {
@@ -557,7 +956,72 @@ _upgrade_tee_exit:
 		run_command("saveenv", 0);
 		run_command("reset", 0);
 
-	} else if (sec_upgrade_flag == UBOOT_SEC_UPGRADE_FLAG) { 
+        if ( image_malloc_buffer != NULL ) {
+            free(image_malloc_buffer);
+            image_malloc_buffer = NULL;
+        }
+	} else if (sec_upgrade_flag == SBMETA_SEC_UPGRADE_FLAG) {
+
+ 		/* STEP 1: read upgrade image (sbmeta.bin) from stash partition */
+		printf("read upgrade image (sbmeta.bin) from stash partition \n");
+		sprintf(runcmd, "ext4load mmc 0:4 0x%p sbmeta.bin", (void *)temp_addr);
+		printf("runcmd:%s\n", runcmd);
+		ret = run_command(runcmd, 0);
+		if (ret != 0) {
+			printf("SBMETA Upgrade process is terminated due to some reason\n");
+			goto _upgrade_sbmeta_exit;
+		}
+		/* Fetch the total file size after read out operation end */
+		upgrade_file_size = env_get_hex("filesize", 0);
+		printf("SBMETA upgrade file size: %d\n", upgrade_file_size);
+
+        /*store image to temp buffer as temp_addr may be decrypted*/
+        image_malloc_buffer = malloc(upgrade_file_size);
+        if ( image_malloc_buffer == NULL ) {
+			image_buffer = (uint8_t*)temp_addr + upgrade_file_size;
+		} else {
+            image_buffer = image_malloc_buffer;
+        }
+        memcpy(image_buffer, (void*)temp_addr, upgrade_file_size);
+
+		/* STEP 2: verify its authentiticy here */
+		sprintf(runcmd, "vimage 0x%p sbmeta", (void *)temp_addr);
+		printf("runcmd:%s\n", runcmd);
+		ret = run_command(runcmd, 0);
+		if (ret != 0) {
+			printf("SBMETA Image verification fail and upgrade process terminates\n");
+			goto _upgrade_sbmeta_exit;
+		}
+
+		/* STEP 3: update sbmeta partition */
+		printf("read upgrade image (SBMETA.bin) into sbmeta partition \n");
+		sprintf(runcmd, "ext4write mmc 0:3 0x%p /sbmeta.bin 0x%x", (void *)image_buffer, upgrade_file_size);
+		printf("runcmd:%s\n", runcmd);
+		ret = run_command(runcmd, 0);
+		if (ret != 0) {
+			printf("SBMETA upgrade process is terminated due to some reason\n");
+			goto _upgrade_sbmeta_exit;
+		}
+
+		/* STEP 4: update sbmeta version */
+		ret = csi_sbmeta_set_upgrade_version();
+		if (ret != 0) {
+			printf("Set sbmeta upgrade version fail\n");
+			goto _upgrade_sbmeta_exit;
+		}
+
+		printf("\n\nSBMETA image ugprade process is successful\n\n");
+_upgrade_sbmeta_exit:
+		/* set secure upgrade flag to 0 that indicate upgrade over */
+		run_command("env set sec_upgrade_mode 0", 0);
+		run_command("saveenv", 0);
+		run_command("reset", 0);
+
+        if ( image_malloc_buffer != NULL ) {
+            free(image_malloc_buffer);
+            image_malloc_buffer = NULL;
+        }
+	} else if (sec_upgrade_flag == UBOOT_SEC_UPGRADE_FLAG) {
 		unsigned int block_cnt;
 		struct blk_desc *dev_desc;
 		const unsigned long uboot_temp_addr=0x80000000;
@@ -566,7 +1030,7 @@ _upgrade_tee_exit:
 
 		/* STEP 1: read upgrade image (u-boot-with-spl.bin) from stash partition */
 		printf("read upgrade image (u-boot-with-spl.bin) from stash partition \n");
-		sprintf(runcmd, "ext4load mmc 0:5 0x%p u-boot-with-spl.bin", (void *)temp_addr);
+		sprintf(runcmd, "ext4load mmc 0:4 0x%p u-boot-with-spl.bin", (void *)temp_addr);
 		printf("runcmd:%s\n", runcmd);
 		ret = run_command(runcmd, 0);
 		if (ret != 0) {

board/thead/light-c910/clock_config.c

@@ -29,6 +29,19 @@
 #define VOSYS_SYSREG_BASE	(0xffef528000)
 #define VOSYS_CLK_GATE_REG	(VOSYS_SYSREG_BASE + 0x50)
 #define VOSYS_CLK_GATE1_REG	(VOSYS_SYSREG_BASE + 0x54)
+#define VOSYS_DPU_CCLK_CFG	(VOSYS_SYSREG_BASE + 0x64)
+
+/* VISYS_SYSREG_R */
+#define VISYS_SYSREG_BASE		(0xffe4040000)
+#define VISYS_MIPI_CSI0_PIXELCLK	(VISYS_SYSREG_BASE + 0x30)
+#define VISYS_ISP0_CLK_CFG		(VISYS_SYSREG_BASE + 0x24)
+#define VISYS_ISP1_CLK_CFG              (VISYS_SYSREG_BASE + 0x28)
+#define VISYS_ISP_RY_CLK_CFG            (VISYS_SYSREG_BASE + 0x2c)
+
+/* APSYS_SYSREG_R */
+#define APSYS_CLKGEN_BASE		(0xffef010000)
+#define APSYS_DPU0_PLL_DIV_CFG		(APSYS_CLKGEN_BASE + 0x1e8)
+#define APSYS_DPU1_PLL_DIV_CFG          (APSYS_CLKGEN_BASE + 0x1ec)
 
 /* AP_DPU0_PLL_CFG1 */
 #define AP_DPU0_PLL_RST		BIT(29)
@@ -105,6 +118,51 @@
 /* VOSYS_CLK_GATE1_REG */
 #define CLKCTRL_HDMI_PIXCLK_EN		BIT(0)
 
+/* VOSYS_DPU_CCLK_CFG */
+#define VOSYS_DPU_CCLK_DIV_NUM_MASK	0xf
+#define VOSYS_DPU_CCLK_DIV_NUM_SHIFT	0
+#define VOSYS_DPU_CCLK_DIV_EN		BIT(4)
+
+/* VISYS_MIPI_CSI0_PIXELCLK  */
+#define VISYS_MIPI_CSI0_PIXELCLK_DIV_NUM_SHIFT	0
+#define VISYS_MIPI_CSI0_PIXELCLK_DIV_NUM_MASK	0xf
+#define VISYS_MIPI_CSI0_PIXELCLK_DIV_EN		BIT(4)
+
+/* VISYS_ISP0_CLK_CFG */
+#define VISYS_ISP0_CLK_DIV_EN			BIT(4)
+#define VISYS_ISP0_CLK_DIV_NUM_SHIFT		(0)
+#define VISYS_ISP0_CLK_DIV_NUM_MASK		0xf
+
+/* VISYS_ISP1_CLK_CFG */
+#define VISYS_ISP1_CLK_DIV_EN			BIT(4)
+#define VISYS_ISP1_CLK_DIV_NUM_SHIFT		(0)
+#define VISYS_ISP1_CLK_DIV_NUM_MASK		0xf
+
+/* VISYS_ISP_RY_CLK_CFG */
+#define VISYS_ISP_RY_CLK_DIV_EN			BIT(4)
+#define VISYS_ISP_RY_CLK_DIV_NUM_SHIFT		(0)
+#define VISYS_ISP_RY_CLK_DIV_NUM_MASK		0xf
+
+/* APSYS_DPU0_PLL_DIV_CFG  */
+#define APSYS_DPU0_PLL_DIV_CLK_DIV_EN		BIT(8)
+#define APSYS_DPU0_PLL_DIV_CLK_DIV_NUM_MASK	0xff
+#define APSYS_DPU0_PLL_DIV_CLK_DIV_NUM_SHIFT	0
+
+/* APSYS_DPU1_PLL_DIV_CFG  */
+#define APSYS_DPU1_PLL_DIV_CLK_DIV_EN		BIT(8)
+#define APSYS_DPU1_PLL_DIV_CLK_DIV_NUM_MASK	0xff
+#define APSYS_DPU1_PLL_DIV_CLK_DIV_NUM_SHIFT	0
+
+enum multimedia_div_type {
+	VI_MIPI_CSI0_DIV,
+	VI_ISP0_CORE_DIV,
+	VI_ISP1_CORE_DIV,
+	VI_ISP_RY_CORE_DIV,
+	VO_DPU_CORE_DIV,
+	VO_DPU_PLL0_DIV,
+	VO_DPU_PLL1_DIV,
+};
+
 #define C910_CCLK	0
 #define C910_CCLK_I0	1
 #define CLK_END		16
@@ -189,6 +247,10 @@ static const struct light_pll_rate_table light_cpupll_tbl[] = {
 	LIGHT_PLL_RATE(3000000000U, 1000000000U, 1, 125, 0, 3, 1),
 	LIGHT_PLL_RATE(3000000000U, 1500000000U, 1, 125, 0, 2, 1),
 	LIGHT_PLL_RATE(1800000000U, 1800000000U, 1, 75,  0, 1, 1),
+	LIGHT_PLL_RATE(2256000000U, 752000000U,  1, 94,  0, 3, 1),
+	LIGHT_PLL_RATE(3000000000U, 300000000U,  1, 125, 0, 5, 2),
+	LIGHT_PLL_RATE(1848000000U, 1848000000U, 1, 77,  0, 1, 1),
+	LIGHT_PLL_RATE(1872000000U, 1872000000U, 1, 78,  0, 1, 1),
 };
 
 static const struct light_pll_rate_table light_audio_pll_tbl[] = {
@@ -605,11 +667,6 @@ struct clk_lightmux {
 	enum clk_device_type clk_dev_type;
 };
 
-struct clk_info {
-	const char *clk_name;
-	enum clk_device_type clk_dev_type;
-};
-
 static const struct clk_info c910_cclk_sels[] = {
 	{"c910_cclk_i0", CLK_DEV_MUX},
 	{"cpu_pll1_foutpostdiv", CLK_DEV_PLL},
@@ -686,7 +743,7 @@ int clk_light_set_parent(const char *clk_name, const char *parent)
 	if (!strcmp(clk->clk_name, parent))
 		return 0;
 
-	printf("clk->num_parents = %d\n", clk->num_parents);
+	debug("clk->num_parents = %d\n", clk->num_parents);
 
 	for (i = 0; i < clk->num_parents; i++) {
 		pr_debug("parent%d:%s\n", i, clk->parents[i].clk_name);
@@ -1007,7 +1064,7 @@ void ap_peri_clk_disable(void)
 {
 	unsigned int clk_cfg;
 
-#if (defined CONFIG_TARGET_LIGHT_FM_C910_VAL_B) || (defined CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_EVT) || (defined CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_DISCRETE)
+#if (defined CONFIG_TARGET_LIGHT_FM_C910_VAL_B) || (defined CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_REF) || (defined CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_DISCRETE) || (defined CONFIG_TARGET_LIGHT_FM_C910_B_POWER)
 	clk_cfg = readl((void __iomem *)AP_PERI_CLK_CFG);
 	clk_cfg &= ~(GMAC1_CLK_EN);
 	writel(clk_cfg, (void __iomem *)AP_PERI_CLK_CFG);
@@ -1089,6 +1146,72 @@ void ap_mipi_dsi1_clk_endisable(bool en)
 	writel(cfg1, (void __iomem *)AP_DPU1_PLL_CFG1);
 }
 
+#if defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_DISCRETE) || defined (CONFIG_TARGET_LIGHT_FM_C910_BEAGLE) || defined (CONFIG_TARGET_LIGHT_FM_C910_B_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_B_POWER) || defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_B) || defined (CONFIG_TARGET_LIGHT_FM_C910_LPI4A) || defined (CONFIG_TARGET_LIGHT_FM_C910_MILKV_MELES)
+static void ap_multimedia_div_num_set(enum multimedia_div_type type, unsigned int div_num)
+{
+	unsigned long div_reg;
+	unsigned int div_num_shift, div_num_mask, div_en;
+	unsigned int div_cfg;
+
+	switch (type) {
+	case VI_MIPI_CSI0_DIV:
+		div_reg = VISYS_MIPI_CSI0_PIXELCLK;
+		div_num_shift = VISYS_MIPI_CSI0_PIXELCLK_DIV_NUM_SHIFT;
+		div_num_mask = VISYS_MIPI_CSI0_PIXELCLK_DIV_NUM_MASK;
+		div_en = VISYS_MIPI_CSI0_PIXELCLK_DIV_EN;
+		break;
+	case VI_ISP0_CORE_DIV:
+		div_reg = VISYS_ISP0_CLK_CFG;
+		div_num_shift = VISYS_ISP0_CLK_DIV_NUM_SHIFT;
+		div_num_mask = VISYS_ISP0_CLK_DIV_NUM_MASK;
+		div_en = VISYS_ISP0_CLK_DIV_EN;
+		break;
+	case VI_ISP1_CORE_DIV:
+		div_reg = VISYS_ISP1_CLK_CFG;
+		div_num_shift = VISYS_ISP1_CLK_DIV_NUM_SHIFT;
+		div_num_mask = VISYS_ISP1_CLK_DIV_NUM_MASK;
+		div_en = VISYS_ISP1_CLK_DIV_EN;
+		break;
+	case VI_ISP_RY_CORE_DIV:
+		div_reg = VISYS_ISP_RY_CLK_CFG;
+		div_num_shift = VISYS_ISP_RY_CLK_DIV_NUM_SHIFT;
+		div_num_mask = VISYS_ISP_RY_CLK_DIV_NUM_MASK;
+		div_en = VISYS_ISP_RY_CLK_DIV_EN;
+		break;
+	case VO_DPU_CORE_DIV:
+		div_reg = VOSYS_DPU_CCLK_CFG;
+		div_num_shift = VOSYS_DPU_CCLK_DIV_NUM_SHIFT;
+		div_num_mask = VOSYS_DPU_CCLK_DIV_NUM_MASK;
+		div_en = VOSYS_DPU_CCLK_DIV_EN;
+		break;
+	case VO_DPU_PLL0_DIV:
+		div_reg =APSYS_DPU0_PLL_DIV_CFG;
+		div_num_shift = APSYS_DPU0_PLL_DIV_CLK_DIV_NUM_SHIFT;
+		div_num_mask = APSYS_DPU0_PLL_DIV_CLK_DIV_NUM_MASK;
+		div_en = APSYS_DPU0_PLL_DIV_CLK_DIV_EN;
+		break;
+	case VO_DPU_PLL1_DIV:
+		div_reg =APSYS_DPU1_PLL_DIV_CFG;
+		div_num_shift = APSYS_DPU1_PLL_DIV_CLK_DIV_NUM_SHIFT;
+		div_num_mask = APSYS_DPU1_PLL_DIV_CLK_DIV_NUM_MASK;
+		div_en = APSYS_DPU1_PLL_DIV_CLK_DIV_EN;
+		break;
+	default:
+		printf("invalid ap multimedia divider type\n");
+		return;
+	}
+
+	div_cfg = readl((void __iomem *)div_reg);
+	div_cfg &= ~div_en;
+	writel(div_cfg, (void __iomem *)div_reg);
+
+	div_cfg &= ~(div_num_mask << div_num_shift);
+	div_cfg |= (div_num & div_num_mask) << div_num_shift;
+	div_cfg |= div_en;
+	writel(div_cfg, (void __iomem *)div_reg);
+}
+#endif
+
 int clk_config(void)
 {
 	unsigned long rate = clk_light_get_rate("c910_cclk", CLK_DEV_MUX);
@@ -1178,6 +1301,18 @@ int clk_config(void)
 	if (ret)
 		return ret;
 #endif
+
+	/* The boards other than the LightA board perform the bus down-speed operation */
+
+#if defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_DISCRETE) || defined (CONFIG_TARGET_LIGHT_FM_C910_BEAGLE) || defined (CONFIG_TARGET_LIGHT_FM_C910_B_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_B_POWER) || defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_B) || defined (CONFIG_TARGET_LIGHT_FM_C910_LPI4A) || defined (CONFIG_TARGET_LIGHT_FM_C910_MILKV_MELES)
+	ap_multimedia_div_num_set(VI_MIPI_CSI0_DIV, 12); /* Input frquency: 2376MHZ */
+	ap_multimedia_div_num_set(VI_ISP0_CORE_DIV, 12); /* Input frquency: 2376MHZ */
+	ap_multimedia_div_num_set(VI_ISP1_CORE_DIV, 12); /* Input frquency: 2376MHZ */
+	ap_multimedia_div_num_set(VI_ISP_RY_CORE_DIV, 12); /* Input frquency: 2376MHZ */
+	ap_multimedia_div_num_set(VO_DPU_CORE_DIV, 4);	/* Input frquency: 2376MHZ */
+	ap_multimedia_div_num_set(VO_DPU_PLL0_DIV, 16);
+	ap_multimedia_div_num_set(VO_DPU_PLL1_DIV, 4);
+#endif
 	ap_hdmi_clk_endisable(false);
 	ap_mipi_dsi1_clk_endisable(false);
 

board/thead/light-c910/digital_sensor.c

@@ -0,0 +1,449 @@
+/*
+ * Copyright (C) 2017-2020 Alibaba Group Holding Limited
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/types.h>
+#include <thead/clock_config.h>
+#include <linux/bitops.h>
+#include <asm/arch-thead/light-iopmp.h>
+#include <asm/arch-thead/light-plic.h>
+
+#define LIGHT_TEE_SYSREG_BASE	((void __iomem*)0xffff200000)
+#define REG_SECURITY_ERR_3	(LIGHT_TEE_SYSREG_BASE + 0x30)
+
+/* id: 0~8 */
+#define DS_C910_BASE(id)	(0xffffc57000 + (id) * 0x40)
+#define DS_APB_BASE(id)		(0xffff270000 + ((id) - 4) * 0x1000)
+
+#define DS_BASE(id)		(((id) > 3) ? (DS_APB_BASE(id)) : (DS_C910_BASE(id)))
+
+#define REG_HW_VERSION(id)			((void __iomem *)DS_BASE(id) + 0x00)	//RO
+#define REG_SENSOR_ALARM(id)			((void __iomem *)DS_BASE(id) + 0x04)	//RO
+#define REG_HEALTH_TEST_ALARM(id)		((void __iomem *)DS_BASE(id) + 0x08)	//RO
+#define REG_HEALTH_TEST_STATUS(id)		((void __iomem *)DS_BASE(id) + 0x0C)	//RO
+#define REG_CONTROL(id)				((void __iomem *)DS_BASE(id) + 0x10)	//WO
+#define REG_IRQ_STATUS(id)			((void __iomem *)DS_BASE(id) + 0x14)	//RO
+#define REG_IRQ_CLEAR(id)			((void __iomem *)DS_BASE(id) + 0x18)	//WO
+#define REG_IRQ_CONFIG(id)			((void __iomem *)DS_BASE(id) + 0x1C)	//RW
+#define REG_STATUS_DSX(id, x)			((void __iomem *)DS_BASE(id) + 0x20 + 0x04 * x)	//RO
+
+#define LIGHT_SEC_IRQ_NUM			91
+
+#define MAX_DIGITAL_SENSOR_NUM			9
+#define MAX_HW_MACRO_NUM_PER_DS			16
+
+#define DS_HW_MACRO_TL_MASK			0xffff
+
+#define DS_INVALID_MACRO_ID			MAX_HW_MACRO_NUM_PER_DS
+
+#define DS_1_ERR				BIT(16)	//digital_sensor_C910_0 ~ digital_sensor_C910_3
+#define DS_3_ERR				BIT(18) //digital_sensor_apb_3
+#define DS_4_ERR				BIT(19) //digital_sensor_apb_4
+#define DS_5_ERR				BIT(20) //digital_sensor_apb_5
+#define DS_6_ERR				BIT(21) //digital_sensor_apb_6
+#define DS_7_ERR				BIT(22) //digital_sensor_apb_7
+#define DS_ERR					(DS_1_ERR | DS_3_ERR | DS_4_ERR | DS_5_ERR | DS_6_ERR | DS_7_ERR)
+
+#define CFG_DS_CPU_THREAT_LEVEL			0
+#define CFG_APB0_THREAT_LEVEL			0
+#define CFG_APB1_THREAT_LEVEL			0
+
+#define AONSYS_RSTGEN_BASE			((void __iomem *)0xFFFFF44000UL)
+#define REG_SYS_RST_CFG				(AONSYS_RSTGEN_BASE + 0x10)
+#define SW_SYS_RST_REQ				(1 << 0)
+#define REG_RST_REQ_EN_0			(AONSYS_RSTGEN_BASE + 0x140)
+#define SW_GLB_RST_EN				(1 << 0)
+
+struct ds_data {
+	int id;
+	u32 hw_macro_num;
+};
+
+struct ds_data ds_array[MAX_DIGITAL_SENSOR_NUM] = {
+	{0, 4},		//digital_sensor_C910_0
+	{1, 4},		//digital_sensor_C910_1
+	{2, 4},		//digital_sensor_C910_2
+	{3, 4},		//digital_sensor_C910_3
+	{4, 16},	//digital_sensor_apb_3
+	{5, 11},	//digital_sensor_apb_4
+	{6, 4},		//digital_sensor_apb_5
+	{7, 16},	//digital_sensor_apb_6
+	{8, 8},		//digital_sensor_apb_7
+};
+
+static void system_reset(void)
+{
+	u32 data = readl(REG_RST_REQ_EN_0);
+
+	/* global reset enable */
+	data |= SW_GLB_RST_EN;
+	writel(data, REG_RST_REQ_EN_0);
+
+	/* global reset request */
+	writel(SW_SYS_RST_REQ, REG_SYS_RST_CFG);
+	mdelay(1000);
+}
+
+static u32 ds_hw_macro_threat_level_get(int ds_id, u32 macro_id)
+{
+	return readl(REG_STATUS_DSX(ds_id, macro_id)) & DS_HW_MACRO_TL_MASK;
+}
+
+static __maybe_unused int ds_health_test_done_status(int ds_id, u32 macro_id)
+{
+	return readl(REG_HEALTH_TEST_STATUS(ds_id)) & (1 << macro_id) ? 1 : 0;
+}
+
+static __maybe_unused int ds_health_test_alarm_status(int ds_id, u32 macro_id)
+{
+	return readl(REG_HEALTH_TEST_ALARM(ds_id)) & (1 << macro_id) ? 1 : 0;
+}
+
+static __maybe_unused bool ds_sensor_alarm_event_hw_macro_get(int ds_id, u32 *event_macro)
+{
+	u32 alarm_status = readl(REG_SENSOR_ALARM(ds_id));
+	int num = ds_array[ds_id].hw_macro_num;
+	int s_alarm_bit = 0, j = 0;
+	bool sensor_alarm_event_occured = false;
+
+	for (int i = 0; i < num; i++) {
+		s_alarm_bit = 1 << i;
+		if (alarm_status & s_alarm_bit) {
+			event_macro[j] = i;
+			j++;
+			sensor_alarm_event_occured = true;
+		}
+	}
+
+	return sensor_alarm_event_occured;
+}
+
+static __maybe_unused bool ds_health_alarm_event_hw_macro_get(int ds_id, u32 *event_macro)
+{
+	u32 h_alarm_status = readl(REG_HEALTH_TEST_ALARM(ds_id));
+	int num = ds_array[ds_id].hw_macro_num;
+	int h_alarm_bit = 0, j = 0;
+	bool health_alarm_event_occured = false;
+
+	for (int i = 0; i < num; i++) {
+		h_alarm_bit = 1 << i;
+		if (h_alarm_status & h_alarm_bit) {
+			event_macro[j] = i;
+			j++;
+			health_alarm_event_occured = true;
+		}
+	}
+
+	return health_alarm_event_occured;
+}
+
+static bool ds_sensor_irq_hw_macro_get(int ds_id, u32 *irq_macro)
+{
+	u32 irq_status = readl(REG_IRQ_STATUS(ds_id));
+	int num = ds_array[ds_id].hw_macro_num;
+	int s_alarm_bit = 0, j = 0;
+	bool sensor_alarm_irq_occured = false;
+
+	for (int i = 0; i < num; i++) {
+		s_alarm_bit = 1 << ((i << 1) + 1);
+		if (irq_status & s_alarm_bit) {
+			irq_macro[j] = i;
+			debug("[%s,%d]irq_macro[%d] = %d\n", __func__, __LINE__,
+							j, irq_macro[j]);
+			j++;
+			sensor_alarm_irq_occured = true;
+		}
+	}
+
+	debug("[%s,%d] sensor_alarm_irq_occured = %d\n", __func__, __LINE__,
+							sensor_alarm_irq_occured);
+	return sensor_alarm_irq_occured;
+}
+
+static __maybe_unused bool ds_health_irq_hw_macro_get(int ds_id, u32 *irq_macro)
+{
+	u32 irq_status = readl(REG_IRQ_STATUS(ds_id));
+	int num = ds_array[ds_id].hw_macro_num;
+	int h_alarm_bit = 0, j = 0;
+	bool health_alarm_irq_occured = false;
+
+	for (int i = 0; i < num; i++) {
+		h_alarm_bit = 1 << (i << 1);
+		if (irq_status & h_alarm_bit) {
+			irq_macro[j] = i;
+			j++;
+			health_alarm_irq_occured = true;
+		}
+	}
+
+	return health_alarm_irq_occured;
+}
+
+static void ds_sensor_irq_clear(int ds_id, u32 macro_id)
+{
+	int s_alarm_bit = 1 << ((macro_id << 1) + 1);
+
+	debug("[%s,%d]reg: 0x%lx, s_alarm_bit = 0x%x\n", __func__, __LINE__,
+							(unsigned long)REG_IRQ_CLEAR(ds_id), s_alarm_bit);
+
+	writel(s_alarm_bit, REG_IRQ_CLEAR(ds_id));
+}
+
+static __maybe_unused void ds_health_irq_clear(int ds_id, u32 macro_id)
+{
+	int h_alarm_bit = 1 << (macro_id << 1);
+
+	writel(h_alarm_bit, REG_IRQ_CLEAR(ds_id));
+}
+
+static void ds_hw_macro_sensor_alarm_endisable(int ds_id, u32 macro_id, bool en)
+{
+	int s_alarm_bit = 1 << ((macro_id << 1) + 1);
+	u32 bitmap = readl(REG_IRQ_CONFIG(ds_id));
+
+	if (en)
+		bitmap |= s_alarm_bit;
+	else
+		bitmap &= ~s_alarm_bit;
+
+	writel(bitmap, REG_IRQ_CONFIG(ds_id));
+}
+
+static __maybe_unused void ds_hw_macro_health_alarm_endisable(int ds_id, u32 macro_id, bool en)
+{
+	int h_alarm_bit = 1 <<  (macro_id << 1);
+	u32 bitmap = readl(REG_IRQ_CONFIG(ds_id));
+
+	if (en)
+		bitmap |= h_alarm_bit;
+	else
+		bitmap &= ~h_alarm_bit;
+
+	writel(bitmap, REG_IRQ_CONFIG(ds_id));
+}
+
+static void ds_hw_macro_rearm(int ds_id, u32 macro_id, int macro_size)
+{
+	int rearm_bit = 1 << (macro_id + macro_size);
+
+	debug("[%s,%d]rearm_bit = 0x%x\n", __func__, __LINE__, rearm_bit);
+	writel(rearm_bit, REG_CONTROL(ds_id));
+}
+
+static __maybe_unused void ds_hw_macro_health_test_start(int ds_id, u32 macro_id)
+{
+	int start_bit = 1 << macro_id;
+
+	writel(start_bit, REG_CONTROL(ds_id));
+}
+
+static void light_sec_irq_handler(void)
+{
+	u32 id, i, j = 0, t = 0, size;
+	u32 tl;
+	u32 irq_macro[MAX_HW_MACRO_NUM_PER_DS] = {0};
+	u32 apb_ds[8] = {0};
+	u32 status = readl(REG_SECURITY_ERR_3);
+
+	if (!status)
+		return;
+
+	if (!(status & DS_ERR)) {
+		printf("Unexpected security interrupt but not ditital sensor alarm occured\n");
+		return; //drop other security interrupts, how to clear ?
+	}
+
+	if (status & DS_1_ERR) {
+		printf("C910 cpu digital sensor detect error event\n");
+
+		for (id = 0; id < 4; id++) {
+			for (i = 0; i < ARRAY_SIZE(irq_macro); i++)
+				irq_macro[i] = DS_INVALID_MACRO_ID;
+
+			if (!ds_sensor_irq_hw_macro_get(id, irq_macro))
+				continue;
+
+			size = ds_array[id].hw_macro_num;
+
+			i = 0;
+			while (i < MAX_HW_MACRO_NUM_PER_DS && irq_macro[i] != DS_INVALID_MACRO_ID) {
+
+				tl = ds_hw_macro_threat_level_get(id, irq_macro[i]);
+
+				printf("DS%d-MACRO%d Threat Level: 0x%x\n", id, irq_macro[i], tl);
+
+				if (tl >= CFG_DS_CPU_THREAT_LEVEL) {
+#if 0
+					run_command("ds_cpu_alarm 1500000000", 0);
+#else
+					system_reset();
+#endif
+				} else {
+#if 0
+					run_command("ds_cpu_alarm 1500000000", 0);
+#else
+					system_reset();
+#endif
+				}
+
+				//Fixmed: before irq clear !!!
+				ds_hw_macro_rearm(id, irq_macro[i], size);
+
+				ds_sensor_irq_clear(id, irq_macro[i]);
+
+				i++;
+			}
+		}
+	}
+
+	if (status & DS_3_ERR) {
+		printf("apb digital sensor3 detect error event\n");
+		apb_ds[j++] = 4;
+	}
+
+	if (status & DS_4_ERR) {
+		printf("apb digital sensor4 detect error event\n");
+		apb_ds[j++] = 5;
+	}
+
+	if (status & DS_5_ERR) {
+		printf("apb digital sensor5 detect error event\n");
+		apb_ds[j++] = 6;
+	}
+
+	if (status & DS_6_ERR) {
+		printf("apb digital sensor6 detect error event\n");
+		apb_ds[j++] = 7;
+	}
+
+	if (status & DS_7_ERR) {
+		printf("apb digital sensor7 detect error event\n");
+		apb_ds[j++] = 8;
+	}
+
+
+	while (apb_ds[t]) {
+		if (apb_ds[t] < 4 || apb_ds[t] > 8) {
+			printf("invalid digial sensor id(%d)\n", apb_ds[t]);
+			return;
+		}
+
+		for (i = 0; i < ARRAY_SIZE(irq_macro); i++)
+			irq_macro[i] = DS_INVALID_MACRO_ID;
+
+		size = ds_array[apb_ds[t]].hw_macro_num;
+
+		if (ds_sensor_irq_hw_macro_get(apb_ds[t], irq_macro)) {
+
+			i = 0;
+			while (i < MAX_HW_MACRO_NUM_PER_DS && irq_macro[i] != DS_INVALID_MACRO_ID) {//hardware macro
+
+				debug("[%s,%d]irq_status = 0x%x, alarm_status = 0x%x\n", __func__, __LINE__,
+						readl(REG_IRQ_STATUS(apb_ds[t])), readl(REG_SENSOR_ALARM(apb_ds[t])));
+
+				tl = ds_hw_macro_threat_level_get(apb_ds[t], irq_macro[i]);
+				if (tl)
+					printf("DS%d-MACRO%d Threat Level: 0x%x\n", apb_ds[t], irq_macro[i], tl);
+
+				if (apb_ds[t] == 8 && tl >= CFG_APB1_THREAT_LEVEL) {
+					//handle1
+					run_command("ds_3to6_alarm 4", 0);
+				} else if (tl >= CFG_APB0_THREAT_LEVEL) {
+					//handle2
+					run_command("ds_3to6_alarm 4", 0);
+				} else {
+					//handle3
+					run_command("ds_3to6_alarm 4", 0);
+				}
+
+				//Fixmed: before irq clear !!!
+				ds_hw_macro_rearm(apb_ds[t], irq_macro[i], size);
+
+				ds_sensor_irq_clear(apb_ds[t], irq_macro[i]);
+
+				i++;
+			}
+		}
+
+		t++; //digital number
+	}
+}
+
+static int ds_platform_init(void)
+{
+	int ds_id, macro_id, ret = 0;
+
+	for (ds_id = 0; ds_id < MAX_DIGITAL_SENSOR_NUM; ds_id++) {
+
+		printf("Digital Sensor%d HW Version: 0x%x\n", ds_id, readl(REG_HW_VERSION(ds_id)));
+
+		for (macro_id = 0; macro_id < ds_array[ds_id].hw_macro_num; macro_id++) {
+			ds_hw_macro_sensor_alarm_endisable(ds_id,
+					                   macro_id, true);
+			ds_hw_macro_health_test_start(ds_id, macro_id);
+			udelay(5);
+			ret = ds_health_test_done_status(ds_id, macro_id);
+			if (!ret) {
+				printf("health test failed for DS%d-Macro%d\n", ds_id, macro_id);
+				ds_hw_macro_sensor_alarm_endisable(ds_id,
+								   macro_id, false);
+			} else {
+				ret = ds_health_test_alarm_status(ds_id, macro_id);
+				if (ret) {
+					ds_hw_macro_sensor_alarm_endisable(ds_id,
+								   macro_id, false);
+					printf("health test failed for DS%d-Macro%d\n", ds_id, macro_id);
+				}
+			}
+		}
+	}
+
+	return 0;
+}
+
+static int ds_sec_interrupt_init(void)
+{
+	int ret;
+
+	ret = irq_handler_register(LIGHT_SEC_IRQ_NUM, light_sec_irq_handler);
+	if (ret) {
+		printf("failed to register security interrupt handler\n");
+		return ret;
+	}
+
+	irq_priority_set(LIGHT_SEC_IRQ_NUM);
+	irq_enable(LIGHT_SEC_IRQ_NUM);
+
+	return 0;
+}
+
+void ds_uninit(void)
+{
+	int ds_id, macro_id;
+
+	irq_disable(LIGHT_SEC_IRQ_NUM);
+
+	for (ds_id = 0; ds_id < MAX_DIGITAL_SENSOR_NUM; ds_id++) {
+		for (macro_id = 0; macro_id < ds_array[ds_id].hw_macro_num; macro_id++)
+			ds_hw_macro_sensor_alarm_endisable(ds_id, macro_id, false);
+	}
+
+	irq_handler_register(LIGHT_SEC_IRQ_NUM, NULL);
+}
+
+int ds_init(void)
+{
+	int ret;
+
+	ds_platform_init();
+
+	ret = ds_sec_interrupt_init();
+	if (ret)
+		return ret;
+
+	return 0;
+}

board/thead/light-c910/digital_sensor_test.c

@@ -0,0 +1,153 @@
+/*
+ * Copyright (C) 2017-2022 Alibaba Group Holding Limited
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/types.h>
+#include <thead/clock_config.h>
+#include <linux/bitops.h>
+#include <asm/arch-thead/light-iopmp.h>
+#include <asm/arch-thead/light-plic.h>
+#include <thead/clock_config.h>
+
+#define TEE_LIGHT_APCLK_ADDRBASE	((void __iomem *)0xffff011000)
+#define REG_TEESYS_CLK_TEECFG		((void __iomem *)TEE_LIGHT_APCLK_ADDRBASE + 0x1cc)
+
+/* VIDEO PLL */
+#define	TEESYS_I1_HCLK_DIV_EN		BIT(12)
+#define TEESYS_I1_HCLK_DIV_NUM_SHIFT	8
+#define TEESYS_I1_HCLK_DIV_NUM_MASK	0xf
+
+#define LIGHT_CPUFREQ_THRE              1500000
+#define LIGHT_C910_BUS_CLK_SYNC         BIT(11)
+#define LIGHT_C910_BUS_CLK_RATIO_MASK   0x700
+#define LIGHT_C910_BUS_CLK_DIV_RATIO_2  0x100
+#define LIGHT_C910_BUS_CLK_DIV_RATIO_3  0x200
+
+extern int ds_init(void);
+
+bool global_ds_init = false;
+
+static int ds_cpu_alarm_clk_set(cmd_tbl_t *cmdtp, int flag, int argc,
+				char * const argv[])
+{
+	unsigned long new_freq;
+	int ret = 0;
+	u32 val;
+	const struct clk_info *parent;
+
+	if (argc != 2) {
+		printf("invalid input parameters\n");
+		return -EINVAL;
+	}
+
+	if (strict_strtoul(argv[1], 10, &new_freq) < 0)
+		return CMD_RET_USAGE;
+
+	val = readl(TEE_LIGHT_APCLK_ADDRBASE + 0x100);
+	val &= ~LIGHT_C910_BUS_CLK_RATIO_MASK;
+	val |= LIGHT_C910_BUS_CLK_DIV_RATIO_3;
+
+	writel(val, TEE_LIGHT_APCLK_ADDRBASE + 0x100);
+	val &= ~LIGHT_C910_BUS_CLK_SYNC;
+	writel(val, TEE_LIGHT_APCLK_ADDRBASE + 0x100);
+	udelay(1);
+	val |= LIGHT_C910_BUS_CLK_SYNC;
+	writel(val, TEE_LIGHT_APCLK_ADDRBASE + 0x100);
+	udelay(1);
+
+	printf("wait for cpu frequency alarm, rate: %ld\n", new_freq);
+
+	parent = clk_light_get_parent("c910_cclk");
+	if (!strcmp(parent->clk_name,  "cpu_pll1_foutpostdiv")) {
+		ret = clk_light_set_rate("c910_cclk_i0", CLK_DEV_MUX, new_freq);
+		if (ret) {
+			printf("failed to set cpu frequency\n");
+			ret = -EINVAL;
+			goto out;
+		}
+		udelay(3);
+		ret = clk_light_set_parent("c910_cclk", "c910_cclk_i0");
+		if (ret) {
+			printf("failed to set parent clock for cpu\n");
+			ret = -EINVAL;
+			goto out;
+		}
+	} else {
+		ret = clk_light_set_rate("cpu_pll1_foutpostdiv", CLK_DEV_PLL, new_freq);
+		if (ret) {
+			printf("failed to set cpu frequency\n");
+			ret = -EINVAL;
+			goto out;
+		}
+		udelay(3);
+		ret = clk_light_set_parent("c910_cclk", "cpu_pll1_foutpostdiv");
+		if (ret) {
+			printf("failed to set parent clock for cpu\n");
+			ret = -EINVAL;
+			goto out;
+		}
+	}
+
+	printf("C910 CPU FREQ: %ldMHz\n", new_freq / 1000000);
+
+out:
+	return ret;
+}
+
+static int ds_3to6_alarm_clk_set(cmd_tbl_t *cmdtp, int flag, int argc,
+				 char * const argv[])
+{
+	unsigned long div;
+	int ret = 0;
+	u32 cfg;
+
+	if (argc != 2) {
+		printf("invalid input parameters\n");
+		return -EINVAL;
+	}
+
+	if (strict_strtoul(argv[1], 10, &div) < 0)
+		return CMD_RET_USAGE;
+
+	if (div < 2 || div > 15) {
+		printf("invalid teesys clock divider number(%ld)\n", div);
+		return -EINVAL;
+	}
+
+	cfg = readl(REG_TEESYS_CLK_TEECFG);
+	cfg &= ~TEESYS_I1_HCLK_DIV_EN;
+	writel(cfg, REG_TEESYS_CLK_TEECFG);
+
+	cfg &= ~(TEESYS_I1_HCLK_DIV_NUM_MASK << TEESYS_I1_HCLK_DIV_NUM_SHIFT);
+	cfg |= (div & TEESYS_I1_HCLK_DIV_NUM_MASK) << TEESYS_I1_HCLK_DIV_NUM_SHIFT;
+	cfg |= TEESYS_I1_HCLK_DIV_EN;
+	writel(cfg, REG_TEESYS_CLK_TEECFG);
+
+	return ret;
+}
+
+static int ds_7_alarm_clk_set(cmd_tbl_t *cmdtp, int flag, int argc,
+			      char * const argv[])
+{
+	return ds_3to6_alarm_clk_set(cmdtp, flag, argc, argv);
+}
+
+static int ds_init_cfg(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	if (!global_ds_init) {
+		global_ds_init = true;
+		return ds_init();
+	}
+
+	return 0;
+}
+
+U_BOOT_CMD(ds_init, 1, 0, ds_init_cfg, "ds_init", "Initalize the digital sensor controller");
+U_BOOT_CMD(ds_cpu_alarm, 2, 0, ds_cpu_alarm_clk_set, "ds_cpu_alarm 1500000000", "digital sensor cpu0~cpu3 alarm test");
+U_BOOT_CMD(ds_3to6_alarm, 2, 0, ds_3to6_alarm_clk_set, "ds_3to6_alarm 3", "digital sensor for digital3~digital6 alarm test");
+U_BOOT_CMD(ds_7_alarm, 2, 0, ds_7_alarm_clk_set, "ds_7_alarm 3", "digital sensor for digital7 alarm test");
+

board/thead/light-c910/lpddr-regu/ddr_regu.c

@@ -136,9 +136,9 @@ static const struct regulator_t g_apcpu_regu_id_list[] = {
 		REGU_ID_DEF(IIC_IDX_AONIIC,APCPU_REGU_VDDM,0x31,0x39,0,1,800000,600000,3500000,12500,1),
 	},
 };
-#elif defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_EVT)
+#elif defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_A_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_B_REF) || (CONFIG_TARGET_LIGHT_FM_C910_BEAGLE) || defined (CONFIG_TARGET_LIGHT_FM_C910_LPI4A) || defined (CONFIG_TARGET_LIGHT_FM_C910_MILKV_MELES)
 /**
- * board for ant-evt
+ * board for ant-ref
  *
  */
 static const struct regulator_t g_regu_id_list[] = {
@@ -165,6 +165,7 @@ static const struct regulator_t g_apcpu_regu_id_list[] = {
 	}
 };
 #else
+#if defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_B)
 /**
  * board for EB064A10/EB064A11
  *
@@ -183,6 +184,7 @@ static const struct regulator_t g_regu_id_list[] = {
 		REGU_ID_DEF(IIC_IDX_AONIIC,DDR_VDD_REGU_1V1,0x5A,0xA7,0,1,CONFIG_DDR_REGU_1V1,800000,1500000,20000,0),
 	}
 };
+#endif
 
 static const struct regulator_t g_apcpu_regu_id_list[] = {
 	{
@@ -236,7 +238,7 @@ static int wait_iic_receive(dw_iic_regs_t *iic_base, uint32_t wait_data_num, uin
 }
 
 
-unsigned long soc_get_iic_freq(uint32_t idx)
+static unsigned long soc_get_iic_freq(uint32_t idx)
 {
 	if (idx == IIC_IDX_AONIIC){
 		return 49152000U;
@@ -651,6 +653,7 @@ int32_t csi_iic_mem_receive_sr(csi_iic_t *iic, uint32_t devaddr, uint16_t memadd
     return read_count;
 }
 
+#if defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_A) ||defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_B)
 static int pmic_read_reg_sr(csi_iic_t *iic_handle,uint16_t dev_addr,uint32_t offset, uint32_t *val)
 {
 	int32_t num;
@@ -662,6 +665,7 @@ static int pmic_read_reg_sr(csi_iic_t *iic_handle,uint16_t dev_addr,uint32_t off
 	*val = temp[0];
 	return 0;
 }
+#endif
 
 static int pmic_write_reg(csi_iic_t *iic_handle,uint16_t dev_addr,uint32_t offset, uint32_t val)
 {
@@ -688,6 +692,7 @@ static int pmic_write_reg(csi_iic_t *iic_handle,uint16_t dev_addr,uint32_t offse
 	return 0;
 }
 
+#if !defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_A) && !defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_B)
 static int pmic_read_reg(csi_iic_t *iic_handle,uint16_t dev_addr,uint32_t offset, uint32_t *val)
 {
 	int32_t num;
@@ -716,6 +721,7 @@ static int pmic_read_reg(csi_iic_t *iic_handle,uint16_t dev_addr,uint32_t offset
 	*val = temp[0];
 	return 0;
 }
+#endif 
 
 static int _pmic_ddr_regu_init(uint32_t idx)
 {
@@ -817,7 +823,9 @@ int pmic_ddr_regu_init(void)
 
 int pmic_ddr_set_voltage(void)
 {
-	int ret = -1;
+	int ret = 0;
+
+#if 0 //currently,no need to modify ddr regulator voltage
 	uint32_t val = 0;
 	uint32_t regu_num = ARRAY_SIZE(g_regu_id_list);
 	uint32_t i;
@@ -834,7 +842,13 @@ int pmic_ddr_set_voltage(void)
 		if (ret)
 			return ret;
 	}
+#endif
+
 #if defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_B)
+	uint32_t val = 0;
+	struct regulator_t *pregu;
+	csi_iic_t          *dev_handle;
+
 	/*enable lcd0_en ldo*/
 	pregu = (struct regulator_t*)&g_regu_id_list[LCD0_EN];
 	dev_handle = pmic_get_iic_handle(pregu->iic_id);
@@ -941,7 +955,7 @@ int pmic_reset_apcpu_voltage(void)
 		return ret;
 	return 0;
 }
-#elif defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_EVT)
+#elif defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_A_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_B_REF)|| (CONFIG_TARGET_LIGHT_FM_C910_BEAGLE) || defined (CONFIG_TARGET_LIGHT_FM_C910_LPI4A) || defined (CONFIG_TARGET_LIGHT_FM_C910_MILKV_MELES)
 int pmic_reset_apcpu_voltage(void)
 {
 	int                ret = -1;

board/thead/light-c910/lpddr4/include/ddr_common_func.h

@@ -48,5 +48,5 @@ void ctrl_init(int rank_num, int speed);
 void addrmap(int rank_num, enum DDR_BITWIDTH bits);
 void ctrl_en(enum DDR_BITWIDTH bits);
 void enable_auto_refresh(void);
-
+void lpddr4_auto_selref(void);
 #endif // DDR_COMMON_FUNCE_H

board/thead/light-c910/lpddr4/src/ddr_common_func.c

@@ -14,6 +14,9 @@ unsigned long get_ddr_density() {
 #ifdef CONFIG_DDR_DUAL_RANK
 	mul = 2;
 #endif
+#ifdef CONFIG_DDR_DDP
+	mul *= 2;
+#endif
 #ifdef CONFIG_DDR_H32_MODE
     div = 2;
 #endif
@@ -873,7 +876,11 @@ if(bits==64) {
 #endif
   wr(ADDRMAP0,0x0004001f);  // +2
   if(rank_num==2) {
+#ifdef CONFIG_DDR_DDP
+  wr(ADDRMAP0,0x00040019);//16GB
+#else
   wr(ADDRMAP0,0x00040018);//8GB
+#endif
   }
   wr(ADDRMAP1,0x00090909); //bank +2
   wr(ADDRMAP2,0x00000000); //col b5+5 ~ col b2  +2
@@ -881,7 +888,11 @@ if(bits==64) {
   wr(ADDRMAP4,0x00001f1f); //col b11~ col b10
   wr(ADDRMAP5,0x080f0808); //row_b11 row b2_10 row b1 row b0  +6
   wr(ADDRMAP6,0x08080808);
+#ifdef CONFIG_DDR_DDP
+  wr(ADDRMAP7,0x00000f08);
+#else
   wr(ADDRMAP7,0x00000f0f);
+#endif
   wr(ADDRMAP9,0x08080808);
   wr(ADDRMAP10,0x08080808);
   wr(ADDRMAP11,0x00000008);
@@ -1121,7 +1132,7 @@ void ddr_soc_pll_disable () {
   printf("DDR SOC PLL PowerDown \n");
 #endif
 }
-void lpddr4_auto_selref()
+void lpddr4_auto_selref(void)
 {
   ddr_sysreg_wr(DDR_CFG1,0xa0000);   //remove core clock after xx
   wr(SWCTL,0);

board/thead/light-c910/lpddr4/src/lpddr4_init.c

@@ -26,11 +26,993 @@ void lpddr4_init(enum DDR_TYPE type, int rank_num, int speed, enum DDR_BITWIDTH
 
   lp4_phy_train1d2d(type, speed, bits);
 
+  dwc_ddrphy_phyinit_regInterface();
+
   ctrl_en(bits);
 
   enable_axi_port(0x1f);
-  
+
   enable_auto_refresh();
 
   lpddr4_auto_selref();
 }
+
+static const uint32_t RetRegList_addr[934] =
+{
+    0x1005f,
+    0x1015f,
+    0x1105f,
+    0x1115f,
+    0x1205f,
+    0x1215f,
+    0x1305f,
+    0x1315f,
+    0x55,
+    0x1055,
+    0x2055,
+    0x3055,
+    0x4055,
+    0x5055,
+    0x200c5,
+    0x2002e,
+    0x90204,
+    0x20024,
+    0x2003a,
+    0x2007d,
+    0x2007c,
+    0x20056,
+    0x1004d,
+    0x1014d,
+    0x1104d,
+    0x1114d,
+    0x1204d,
+    0x1214d,
+    0x1304d,
+    0x1314d,
+    0x10049,
+    0x10149,
+    0x11049,
+    0x11149,
+    0x12049,
+    0x12149,
+    0x13049,
+    0x13149,
+    0x43,
+    0x1043,
+    0x2043,
+    0x3043,
+    0x4043,
+    0x5043,
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+    0x11140,
+    0x11240,
+    0x11340,
+    0x11440,
+    0x11540,
+    0x11640,
+    0x11740,
+    0x11840,
+    0x12040,
+    0x12140,
+    0x12240,
+    0x12340,
+    0x12440,
+    0x12540,
+    0x12640,
+    0x12740,
+    0x12840,
+    0x13040,
+    0x13140,
+    0x13240,
+    0x13340,
+    0x13440,
+    0x13540,
+    0x13640,
+    0x13740,
+    0x13840,
+};
+
+typedef struct Reg_Addr_Val {
+  uint32_t Address; ///< register address
+  uint16_t Value0;   ///< register value phy0
+  uint16_t Value1;   ///< register value phy1
+} Reg_Addr_Val_t;
+
+typedef struct Reg_Addr_Value {
+  uint32_t reg_num;
+  Reg_Addr_Val_t reg[0];
+} Reg_Addr_Value_t;
+
+int NumRegSaved = 934;    ///< Current Number of registers saved.
+#define SRAM_E902_BASEADDR 0xFFFFEF8000
+#define DDR_PHY_REG_SAVEADDR (SRAM_E902_BASEADDR + 0xDF00)
+Reg_Addr_Value_t *pRetRegList = (Reg_Addr_Value_t *)DDR_PHY_REG_SAVEADDR;
+
+int dwc_ddrphy_phyinit_regInterface() {
+    ddr_phy_reg_wr(0xd0000, 0x0);
+    ddr_phy_reg_wr(0xc0080, 0x3);
+    pRetRegList->reg_num = NumRegSaved;
+    // go through all the tracked registers, issue a register read and place
+    // the result in the data structure for future recovery.
+    int regIndx = 0;
+    uint16_t data;
+    for (regIndx = 0; regIndx < NumRegSaved; regIndx++)
+    {
+      data = ddr_phy0_reg_rd(RetRegList_addr[regIndx]);
+      pRetRegList->reg[regIndx].Value0 = data;
+      pRetRegList->reg[regIndx].Address = RetRegList_addr[regIndx];
+    }
+#ifndef CONFIG_DDR_H32_MODE
+    for (regIndx = 0; regIndx < NumRegSaved; regIndx++)
+    {
+      data = ddr_phy1_reg_rd(RetRegList_addr[regIndx]);
+      pRetRegList->reg[regIndx].Value1 = data;
+    }
+#endif
+    ddr_phy_reg_wr(0xc0080, 0x2);
+    ddr_phy_reg_wr(0xd0000, 0x1);
+    return 1;
+}

board/thead/light-c910/sbmeta/sbmeta.c

@@ -0,0 +1,436 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2021 Alibaba Group Holding Limited
+ */
+
+#include "sbmeta.h"
+#include "sec_crypto_sha.h"
+
+#define LOGLEVEL_ERROR          1
+#define LOGLEVEL_INFO           2
+#define LOGLEVEL_DEBUG          3
+#define SBMETA_LOGLEVEL         1
+#define trace_printer(level, fmt,...)   printf("%s"fmt, level, ##__VA_ARGS__)
+#if (SBMETA_LOGLEVEL < 1)
+#define EMSG(...)
+#else
+#define EMSG(fmt, args...)      trace_printer("error: ", fmt, ##args)
+#endif
+
+#if (SBMETA_LOGLEVEL < 2)
+#define IMSG(...)
+#else
+#define IMSG(fmt, args...)      trace_printer("info: ", fmt, ##args)
+#endif
+
+#if (SBMETA_LOGLEVEL < 3)
+#define DMSG(...)
+#else
+#define DMSG(fmt, args...)      trace_printer("", fmt, ##args)
+#endif
+
+#if CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_VAL_A) || CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_VAL_B) || CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_LPI4A)
+#if CONFIG_IS_ENABLED(LIGHT_SEC_UPGRADE)
+/* digest_size corresponding to digest_scheme specified in sbmeta_info_t */
+static const int digest_size[] = {0, 20, 16, 28, 32, 48, 64, 32};
+static const char* image_name_s[] = {
+    "dtb", "kernel", "tf", "aon", "rootfs", "tee", "uboot", "user"
+};
+/* index to get sc_sha_mode_t value */
+static const int sha_idx2ctl[] = {0, 1, 8, 3, 2, 5, 4, 9};
+
+static const unsigned long image_addrs[] = {
+    LIGHT_DTB_ADDR,
+    LIGHT_KERNEL_ADDR,
+    LIGHT_TF_FW_TMP_ADDR,
+    LIGHT_AON_FW_ADDR,
+    LIGHT_ROOTFS_ADDR,
+    LIGHT_TEE_FW_ADDR,
+    CONFIG_SYS_TEXT_BASE,
+};
+
+typedef struct {
+    int         magiccode;
+    uint8_t     dev;
+    uint8_t     part;
+    uint8_t     image_type;
+    uint8_t     digest_scheme;
+    uint8_t     sign_scheme;
+    uint8_t     isencrypted;
+    uint8_t     medium_type;
+    uint8_t     checksum_scheme;
+    char        filename[MAX_NAME_SIZE];
+    uint8_t     digest[MAX_DIGEST_SIZE];
+    uint32_t    relocated_addr;
+    uint32_t    reserved[4];
+} sbmeta_info_t;
+
+static int is_sbmeta_info(uint32_t entry_src_addr)
+{
+    uint32_t *buffer = (uint32_t *)(uintptr_t)entry_src_addr;
+
+    /* sbmeta_info_t entry should start with magic code 'S''B''M''T' */
+    if (*buffer != SBMETA_MAGIC) {
+        return CMD_RET_FAILURE;
+    }
+
+    return 0;
+}
+
+static int dump_sbmeta_info(sbmeta_info_t *sbmeta_info)
+{
+    if (sbmeta_info == NULL) {
+        return CMD_RET_FAILURE;
+    }
+    /* only support emmc now */
+    if (sbmeta_info->medium_type != 0) {
+        EMSG("medium type %d is not supported now\r\n", sbmeta_info->medium_type);
+        return CMD_RET_FAILURE;
+    }
+    /* only support dtb, krlimg/tf, sbi, aon, rootfs, tee, uboot and user-defined type */
+    if (sbmeta_info->image_type > IMAGE_TYPE_NUM || sbmeta_info->image_type < 0) {
+        EMSG("image type is out of range\r\n");
+        return CMD_RET_FAILURE;
+    }
+    /* only support none, sha1, md5, sha224, sha256, sha384, sha512, sm3 and reserved scheme */
+    if (sbmeta_info->digest_scheme > DIGEST_TYPE_NUM || sbmeta_info->digest_scheme < 0) {
+        EMSG("digest type is out of range\r\n");
+        return CMD_RET_FAILURE;
+    }
+    /* only support none, rsa1024, rsa2048, ecc256, ecc160, sm2 and reserved scheme */
+    if (sbmeta_info->sign_scheme > SIGN_TYPE_NUM || sbmeta_info->sign_scheme < 0) {
+        EMSG("signature type is out of range\r\n");
+        return CMD_RET_FAILURE;
+    }
+    /* DTB, TF, TEE, Kernel will be loaded from default partitions specified in env */
+    if (sbmeta_info->image_type != T_ROOTFS && sbmeta_info->image_type != T_USER) {
+        IMSG("Image has been loaded\r\n");
+    }
+
+    /* dump sbmeta_info_t */
+    DMSG("image medium type: %d\n", sbmeta_info->medium_type);
+    DMSG("image load part: mmc %d:%d\n", sbmeta_info->dev, sbmeta_info->part);
+    DMSG("image type: %d \n", sbmeta_info->image_type);
+    DMSG("image digest scheme: %d\n", sbmeta_info->digest_scheme);
+    DMSG("image sign scheme: %d\n", sbmeta_info->sign_scheme);
+    DMSG("image enable encryption: %s\n", sbmeta_info->isencrypted ? "en" : "dis");
+    DMSG("image file name: %s\n", sbmeta_info->filename);
+    DMSG("image digest:");
+    for (int i = 0; i < digest_size[sbmeta_info->digest_scheme]; i++) {
+        DMSG("%02X", sbmeta_info->digest[i]);
+    }
+    DMSG("\r\n");
+    DMSG("\n\n");
+
+    return 0;
+}
+
+static int sbmeta_field_verify(sbmeta_info_t *sbmeta_info, unsigned long img_src_addr)
+{
+    uint8_t digest_scheme = 0;
+    uint8_t sign_scheme = 0;
+    uint8_t is_encrypted = 0;
+    img_header_t *phead = NULL;
+
+    if (sbmeta_info == NULL) {
+        return CMD_RET_FAILURE;
+    }
+
+    /* if image has secure header, check with sbmeta field */
+    if (image_have_head(img_src_addr)) {
+        phead = (img_header_t *)img_src_addr;
+        digest_scheme = phead->digest_scheme;
+        sign_scheme = phead->signature_scheme;
+        is_encrypted = (phead->option_flag & 0x2) >> 1;
+    }
+
+    if (sbmeta_info->digest_scheme != digest_scheme) {
+        EMSG("digest type %d is not expected: %d\r\n", digest_scheme, sbmeta_info->digest_scheme);
+        return CMD_RET_FAILURE;
+    }
+
+    /* only support none, rsa1024, rsa2048, ecc256, ecc160, sm2 and reserved scheme */
+    if (sbmeta_info->sign_scheme != sign_scheme) {
+        EMSG("signature type %d is not expected: %d\r\n", sign_scheme, sbmeta_info->sign_scheme);
+        return CMD_RET_FAILURE;
+    }
+
+    if (sbmeta_info->isencrypted != is_encrypted) {
+        EMSG("encryption %d is not expected: %d\r\n", is_encrypted, sbmeta_info->isencrypted);
+        return CMD_RET_FAILURE;
+    }
+
+    return 0;
+}
+
+static int check_digest(uint8_t *buffer, uint32_t buffer_size, uint8_t digest_scheme, uint8_t *digest)
+{
+    uint32_t len = 0;
+    uint8_t sum[64];
+    sc_sha_t sha;
+    sc_sha_context_t ctx;
+    int mode = 0;
+
+    if (!buffer || digest_scheme > DIGEST_TYPE_NUM) {
+        EMSG("wrong parameter\r\n");
+        return CMD_RET_FAILURE;
+    }
+
+    if (digest_scheme == 0) {
+        return 0;
+    }
+    mode = sha_idx2ctl[digest_scheme];
+
+    if (sc_sha_init(&sha, 0) != 0) {
+        EMSG("sha initialize failed\r\n");
+        return CMD_RET_FAILURE;
+    }
+
+    if (sc_sha_start(&sha, &ctx, mode) != 0) {
+        EMSG("sha start failed\r\n");
+        return CMD_RET_FAILURE;
+    }
+
+    if (sc_sha_update(&sha, &ctx, buffer, buffer_size) != 0) {
+        EMSG("sha update failed\r\n");
+        return CMD_RET_FAILURE;
+    }
+
+    if (sc_sha_finish(&sha, &ctx, sum, &len) != 0) {
+        EMSG("sha finish failed\r\n");
+        return CMD_RET_FAILURE;
+    }
+
+	sc_sha_uninit(&sha);
+
+    /* check digest value */
+    if (memcmp(digest, sum, len) != 0) {
+        EMSG("check digest failed\r\n");
+        return CMD_RET_FAILURE;
+    }
+
+    return 0;
+}
+
+/* Verify image specified in sbmeta_info_t. The image has been loaded to memory before */
+static int sbmeta_verify_image(uint32_t image_load_addr, sbmeta_info_t *sbmeta_info)
+{
+    uint32_t image_size = 0;
+    const char *image_name;
+    uint8_t image_type = sbmeta_info->image_type;
+    uint8_t checksum_scheme = sbmeta_info->checksum_scheme;
+    uint8_t *digest = sbmeta_info->digest;
+    uint8_t is_encrypted = sbmeta_info->isencrypted;
+    uint32_t security_level = env_get_hex("sbmeta_security_level", 3);
+    uint32_t filesize = 0;
+    char buf[64] = {0};
+
+    /* check image_type to avoid array index out of bounds */
+    if (image_type > IMAGE_TYPE_NUM || image_type < 0) {
+        EMSG("image type is out of range\r\n");
+        return CMD_RET_FAILURE;
+    }
+    image_name = image_name_s[image_type];
+
+    /* check tee/tf version if needed */
+#ifdef LIGHT_IMG_VERSION_CHECK_IN_BOOT
+   if (image_have_head(image_load_addr) == 1) {
+        if (image_type == T_TF) {
+            IMSG("check TF version in boot \n");
+            if (check_tf_version_in_boot(LIGHT_TF_FW_TMP_ADDR) != 0) {
+                return CMD_RET_FAILURE;
+            }
+        }
+
+        if (image_type == T_TEE) {
+            IMSG("check TEE version in boot \n");
+            if (check_tee_version_in_boot(LIGHT_TEE_FW_ADDR) != 0) {
+                return CMD_RET_FAILURE;
+            }
+        }
+   }
+#endif
+
+    /* start verifying images */
+    IMSG("Process %s image verification ...\n", image_name);
+    if (security_level == 3 || is_encrypted != 0) {
+        if (verify_customer_image(image_type, image_load_addr) != 0) {
+            return CMD_RET_FAILURE;
+        }
+    } else if (security_level == 2) {
+        if (memcmp(digest, buf, 64) == 0) {
+            EMSG("sbmeta info doesn't specify digest value in security level 2\r\n");
+            return CMD_RET_FAILURE;
+        }
+
+        snprintf(buf, sizeof(buf), "ext4size mmc %x:%x %s", sbmeta_info->dev, sbmeta_info->part, sbmeta_info->filename);
+        if (run_command(buf, 0) != 0) {
+            EMSG("get file size error\r\n");
+            return CMD_RET_FAILURE;
+        }
+
+        filesize = env_get_hex("filesize", 0);
+        if (check_digest((uint8_t *)(uintptr_t)image_load_addr, filesize, checksum_scheme, digest) != 0) {
+            return CMD_RET_FAILURE;
+        }
+    }
+
+    /* move image headers always */
+    if (image_have_head(image_load_addr) == 1) {
+        image_size = get_image_size(image_load_addr);
+        IMSG("%s image size: %d\n", image_name, image_size);
+        if (image_size < 0) {
+            EMSG("GET %s image size error\n", image_name);
+            return CMD_RET_FAILURE;
+        }
+        if (image_type == T_TF) {
+            memmove((void *)(uintptr_t)LIGHT_TF_FW_ADDR, (const void *)(uintptr_t)(image_load_addr + HEADER_SIZE), image_size);
+        } else {
+            memmove((void *)(uintptr_t)image_load_addr, (const void *)(uintptr_t)(image_load_addr + HEADER_SIZE), image_size);
+        }
+    } else {
+        /* TF should be moved to LIGHT_TF_FW_ADDR all the cases*/
+        if (image_type == T_TF) {
+            /* while image_size is unknown, reload the image */
+            run_command("ext4load mmc 0:3 0x0 trust_firmware.bin", 0);
+        }
+    }
+
+    return 0;
+}
+
+static int light_sbmetaboot(int argc, char *const argv[])
+{
+    int count = 0;
+    uint32_t sbmeta_size = 0;
+    uint32_t info_addr = 0;
+    uint32_t image_load_addr = 0;
+    char cmd[64] = {0};
+    sbmeta_info_t *sbmeta_info = NULL;
+
+    /* Load sbmeta image to memory */
+    snprintf(cmd, sizeof(cmd), "ext4load mmc $mmcdev:%x 0x%p %s", SBMETA_PART, (void *)(uintptr_t)LIGHT_SBMETA_ADDR, SBMETA_FILENAME);
+    if (run_command(cmd, 0) != 0) {
+        /* if sbmeta doesn't exist, do secboot by default */
+        IMSG("SBMETA doesn't exist, go to verify tf/tee\r\n");
+
+        /*
+        * Verify tf and tee by command secboot.
+        * Note that tf and tee has been loaded in "run bootcmd_load"
+        */
+        if (run_command("secboot", 0) != 0) {
+            return CMD_RET_FAILURE;
+        }
+
+        return 0;
+    }
+
+    /* initialize crypto algorithm interfaces */
+    if (csi_sec_init() != 0) {
+        return CMD_RET_FAILURE;
+    }
+
+    /* Check and verify sbmeta image */
+    if (image_have_head(LIGHT_SBMETA_ADDR) == 1) {
+#ifdef LIGHT_IMG_VERSION_CHECK_IN_BOOT
+		IMSG("check SBMETA version in boot \n");
+		ret = check_sbmeta_version_in_boot(LIGHT_SBMETA_ADDR);
+		if (ret != 0) {
+			return CMD_RET_FAILURE;
+		}
+#endif
+        IMSG("Process SBMETA image verification...\r\n");
+        if (verify_customer_image(T_SBMETA, LIGHT_SBMETA_ADDR) != 0) {
+            return CMD_RET_FAILURE;
+        }
+
+        sbmeta_size = get_image_size(LIGHT_SBMETA_ADDR);
+        IMSG("sbmeta_size:%d\r\n", sbmeta_size);
+        if (sbmeta_size != SBMETA_SIZE) {
+            EMSG("SBMETA header is wrong! Size must equal to %d bytes!\r\n", SBMETA_SIZE);
+            return CMD_RET_FAILURE;
+        }
+        /* move image headers always */
+        memmove((void *)LIGHT_SBMETA_ADDR, (const void *)(LIGHT_SBMETA_ADDR + HEADER_SIZE), sbmeta_size);
+    } else {
+        /* if sbmeta image is not secure, reset */
+        IMSG("SBMETA image must be with signature\r\n");
+        return CMD_RET_FAILURE;
+    }
+
+    /* Parse sbmeta_info_t in image sbmeta, then load and verify specified images */
+    info_addr = LIGHT_SBMETA_ADDR;
+    for (count = 0; count < MAX_ENTRY_NUM; count++) {
+        if (is_sbmeta_info(info_addr) == 0) {
+            /* Dump and check sbmeta info */
+            sbmeta_info = (sbmeta_info_t *)(uintptr_t)info_addr;
+            if (dump_sbmeta_info(sbmeta_info) != 0) {
+                return CMD_RET_FAILURE;
+            }
+
+            info_addr += ENTRY_SIZE;
+
+            /*
+             * If image_type != T_USER, load to address specified in light-c910.h;
+             * otherwise, load to user-specified address.
+            */
+            if (sbmeta_info->image_type != T_USER) {
+                image_load_addr = image_addrs[sbmeta_info->image_type];
+            } else {
+                image_load_addr = sbmeta_info->relocated_addr;
+            }
+
+            /*
+            * Load image specified in sbmeta info
+            * Note: only load images don't exist in env "bootcmd_load"
+            */
+            if (sbmeta_info->image_type == T_ROOTFS || sbmeta_info->image_type == T_USER) {
+                snprintf(cmd, sizeof(cmd), "ext4load mmc %x:%x %p %s", sbmeta_info->dev,
+                         sbmeta_info->part, \
+                         (void *)(uintptr_t)image_load_addr, sbmeta_info->filename);
+                if (run_command(cmd, 0) != 0) {
+                    return CMD_RET_FAILURE;
+                }
+            }
+
+            if (sbmeta_field_verify(sbmeta_info, image_load_addr) != 0) {
+                return CMD_RET_FAILURE;
+            }
+
+            /* Check and verify user-specified image */
+            if (sbmeta_verify_image(image_load_addr, sbmeta_info) != 0) {
+                return CMD_RET_FAILURE;
+            }
+        } else {
+            break;
+        }
+    }
+
+    /* if sbmeta didn't specify images, reset */
+    if (count == 0) {
+        EMSG("SBMETA doesn't specify any images!\r\n");
+        return CMD_RET_FAILURE;
+    }
+
+    /* Clear sbmeta buffer in memory */
+    memset((void *)LIGHT_SBMETA_ADDR, 0, PLAIN_SBMETA_TEXT);
+    return 0;
+}
+
+static int do_sbmetaboot(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+{
+    if (light_sbmetaboot(argc, argv) != 0) {
+        EMSG("sbmetaboot failed\r\n");
+        while (1);
+        return CMD_RET_FAILURE;
+    }
+    return 0;
+}
+
+U_BOOT_CMD(
+    sbmetaboot, CONFIG_SYS_MAXARGS, 1, do_sbmetaboot,
+    "load and verify image sbmeta, then verify image files specified in sbmeta",
+    ""
+);
+#endif
+#endif

board/thead/light-c910/sbmeta/sbmeta.h

@@ -0,0 +1,34 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2021 Alibaba Group Holding Limited
+ */
+
+#ifndef _LIGHT_SBMETA_H
+#define _LIGHT_SBMETA_H
+
+#include "common.h"
+#include "command.h"
+#include <asm/arch-thead/boot_mode.h>
+
+#define MAX_NAME_SIZE       32
+#define MAX_DIGEST_SIZE     64
+#define SBMETA_MAGIC        0x544D4253  /* = {'S', 'B', 'M', 'T'} */
+
+#if CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_VAL_A) || CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_VAL_B) || CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_LPI4A)
+#define LIGHT_SBMETA_ADDR   0x10000000
+#endif
+#define SBMETA_PART         5
+#define ENTRY_SIZE          128
+#define PLAIN_SBMETA_TEXT   4096
+#define SBMETA_SIZE         4736  /* 4K SMBETA image + 640 footer */
+#define MAX_ENTRY_NUM       PLAIN_SBMETA_TEXT / ENTRY_SIZE  /* 4K/128=32 */
+#define IMAGE_TYPE_NUM      7
+#define DIGEST_TYPE_NUM     8
+#define SIGN_TYPE_NUM       6
+#define SBMETA_FILENAME     "sbmeta.bin"
+
+#define SBMETA_SECURITY_LEVEL_H      3   /* verify signature and hash */
+#define SBMETA_SECURITY_LEVEL_M      2   /* verify checksum */
+#define SBMETA_SECURITY_LEVEL_L      1   /* no verification */
+
+#endif

board/thead/light-c910/sec_check.c

@@ -12,7 +12,7 @@
 #include <asm/arch-thead/boot_mode.h>
 #include "../../../lib/sec_library/include/csi_sec_img_verify.h"
 
-extern int csi_efuse_api_int(void);
+extern int csi_efuse_api_init(void);
 extern int csi_efuse_api_unint(void);
 extern int csi_efuse_read_raw(uint32_t addr, void *data, uint32_t cnt);
 extern int csi_efuse_write_raw(uint32_t addr, const void *data, uint32_t cnt);
@@ -35,7 +35,7 @@ int csi_sec_init(void)
 	char *version;
 
 	/* Initialize eFuse module */
-	ret = csi_efuse_api_int();
+	ret = csi_efuse_api_init();
 	if (ret) {
 		printf("efuse init faild[%d]\n", ret);
 		 goto exit;
@@ -62,7 +62,7 @@ void designware_get_mac_from_fuse(unsigned char *mac)
 	int ret;
 
 	/* Initialize eFuse module */
-	ret = csi_efuse_api_int();
+	ret = csi_efuse_api_init();
 	if (ret) {
 		printf("efuse init faild[%d]\n", ret);
 		return;
@@ -75,6 +75,89 @@ void designware_get_mac_from_fuse(unsigned char *mac)
 	}
 }
 
+#if CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_VAL_A) || CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_VAL_B) || CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_ANT_REF) || CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_LPI4A)
+/* Secure function for image verificaiton here */
+int get_image_version(unsigned long img_src_addr)
+{
+	img_header_t *img = (img_header_t *)img_src_addr;
+	uint8_t magiccode[4] = {0};
+	
+	magiccode[3] = img->magic_num & 0xff;
+	magiccode[2] = (img->magic_num & 0xff00) >> 8;
+	magiccode[1] = (img->magic_num & 0xff0000) >> 16;
+	magiccode[0] = (img->magic_num & 0xff000000) >> 24;
+	if (memcmp(header_magic, magiccode, 4) == 0) {
+		return -1;
+	}
+	
+	return img->image_version;
+}
+
+int get_image_size(unsigned long img_src_addr)
+{
+	img_header_t *img = (img_header_t *)img_src_addr;
+	uint8_t magiccode[4] = {0};
+	
+	magiccode[3] = img->magic_num & 0xff;
+	magiccode[2] = (img->magic_num & 0xff00) >> 8;
+	magiccode[1] = (img->magic_num & 0xff0000) >> 16;
+	magiccode[0] = (img->magic_num & 0xff000000) >> 24;
+	if (memcmp(header_magic, magiccode, 4) == 0) {
+		return -1;
+	}
+	
+	return img->image_size;
+}
+
+void dump_image_header_info(long addr)
+{
+	img_header_t *phead = (img_header_t *)addr;
+
+	printf("\n---------------------------------------------\n");
+	printf("entry point: 0x%x\n", phead->entry_point);
+	printf("image size: %d Bytes\n", phead->image_size);
+	printf("head version: 0x%x\n", phead->head_version);
+	printf("image version: 0x%x\n", phead->image_version);
+	printf("image checksum: 0x%x\n", phead->image_checksum);
+	printf("image run addr: 0x%llx\n", phead->image_run_addr);
+	printf("image offset: 0x%x\n", phead->image_offset);
+	printf("image digest scheme: %d\n", phead->digest_scheme);
+	printf("image sign scheme: %d\n", phead->signature_scheme);
+	printf("image encrypt type: %d\n", phead->encrypt_type);
+	printf("\n---------------------------------------------\n");
+}
+
+int verify_customer_image(img_type_t type, long addr)
+{
+	int ret;
+
+	/* Double check image number */
+	if (image_have_head(addr) == 0) {
+		printf("error: image has no secure header\r\n");
+		return -1;
+	}
+
+	/* Dump image header information here */
+	dump_image_header_info(addr);
+
+	/* Call customer image verification function */
+	if ((type == T_TF) || (type == T_TEE) || (type == T_KRLIMG) || (type == T_DTB) || (type == T_SBMETA)) {
+		ret = csi_sec_custom_image_verify(addr, UBOOT_STAGE_ADDR);
+		if (ret) {
+			printf("Image(%d) is verified fail, Please go to check!\n\n", type);
+			return ret;
+		}
+	} else if (type == T_UBOOT) {
+		ret = csi_sec_uboot_image_verify(addr, addr - PUBKEY_HEADER_SIZE);
+		if (ret) {
+			printf("Image(%s) is verified fail, Please go to check!\n\n", "uboot");
+			return ret;
+		}
+	}
+
+	return 0;
+}
+#else
 static int strtou32(const char *str, unsigned int base, u32 *result)
 {
 	char *ep;
@@ -110,7 +193,7 @@ static int do_fuse(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
 	int ret, i;
 
 	/* Initialize eFuse module */
-	ret = csi_efuse_api_int();
+	ret = csi_efuse_api_init();
 	if (ret) {
 		printf("efuse init faild[%d]\n", ret);
 		goto err;
@@ -188,86 +271,4 @@ U_BOOT_CMD(
 	"efuse write [-y] <addr> <hexval> [<hexval>...]  - program 1 or\n"
 	" several fuse bytes, starting at 'addr'\n"
 );
-
-#if CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_VAL_A) || CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_VAL_B) || CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_ANT_EVT)
-/* Secure function for image verificaiton here */
-int get_image_version(unsigned long img_src_addr)
-{
-	img_header_t *img = (img_header_t *)img_src_addr;
-	uint8_t magiccode[4] = {0};
-	
-	magiccode[3] = img->magic_num & 0xff;
-	magiccode[2] = (img->magic_num & 0xff00) >> 8;
-	magiccode[1] = (img->magic_num & 0xff0000) >> 16;
-	magiccode[0] = (img->magic_num & 0xff000000) >> 24;
-	if (memcmp(header_magic, magiccode, 4) == 0) {
-		return -1;
-	}
-	
-	return img->image_version;
-}
-
-int get_image_size(unsigned long img_src_addr)
-{
-	img_header_t *img = (img_header_t *)img_src_addr;
-	uint8_t magiccode[4] = {0};
-	
-	magiccode[3] = img->magic_num & 0xff;
-	magiccode[2] = (img->magic_num & 0xff00) >> 8;
-	magiccode[1] = (img->magic_num & 0xff0000) >> 16;
-	magiccode[0] = (img->magic_num & 0xff000000) >> 24;
-	if (memcmp(header_magic, magiccode, 4) == 0) {
-		return -1;
-	}
-	
-	return img->image_size;
-}
-
-void dump_image_header_info(long addr)
-{
-	img_header_t *phead = (img_header_t *)addr;
-
-	printf("\n---------------------------------------------\n");
-	printf("entry point: 0x%x\n", phead->entry_point);
-	printf("image size: %d Bytes\n", phead->image_size);
-	printf("head version: 0x%x\n", phead->head_version);
-	printf("image version: 0x%x\n", phead->image_version);
-	printf("image checksum: 0x%x\n", phead->image_checksum);
-	printf("image run addr: 0x%llx\n", phead->image_run_addr);
-	printf("image offset: 0x%x\n", phead->image_offset);
-	printf("image digest scheme: %d\n", phead->digest_scheme);
-	printf("image sign scheme: %d\n", phead->signature_scheme);
-	printf("image encrypt type: %d\n", phead->encrypt_type);
-	printf("\n---------------------------------------------\n");
-}
-
-int verify_customer_image(img_type_t type, long addr)
-{
-	int ret;
-
-	/* Double check image number */
-	if (image_have_head(addr) == 0)
-		return -1;
-
-	/* Dump image header information here */
-	dump_image_header_info(addr);
-
-	/* Call customer image verification function */
-	if ((type == T_TF) || (type == T_TEE)) {
-		ret = csi_sec_custom_image_verify(addr, UBOOT_STAGE_ADDR);
-		if (ret) {
-			printf("Image(%s) is verified fail, Please go to check!\n\n", (type == T_TF)?"tf":"tee");
-			return ret;
-		}
-	} else if (type == T_UBOOT) {
-		ret = csi_sec_uboot_image_verify(addr, addr - PUBKEY_HEADER_SIZE);
-		if (ret) {
-			printf("Image(%s) is verified fail, Please go to check!\n\n", "uboot");
-			return ret;
-		}
-	}
-
-	return 0;
-}
-
 #endif

board/thead/light-c910/secimg_load.c

@@ -0,0 +1,239 @@
+/*
+ * (C) Copyright 2018, Linaro Limited
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#include <command.h>
+#include <env.h>
+#include <configs/light-c910.h>
+#include <asm/arch-thead/boot_mode.h>
+#include "sec_library.h"
+
+#define ENV_SECIMG_LOAD     "sec_m_load"
+#define VAL_SECIMG_LOAD     "ext4load mmc ${mmcdev}:${mmcteepart} $tf_addr trust_firmware.bin; ext4load mmc ${mmcdev}:${mmcteepart} $tee_addr tee.bin\0"
+
+#define RPMB_BLOCK_SIZE 256
+#define RPMB_ROLLBACK_BLOCK_START 1
+
+#ifndef LIGHT_KDF_RPMB_KEY
+static const unsigned char emmc_rpmb_key_sample[32] = {0x33, 0x22, 0x11, 0x00, 0x77, 0x66, 0x55, 0x44, \
+												0xbb, 0xaa, 0x99, 0x88, 0xff, 0xee, 0xdd, 0xcc, \
+												0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, \
+												0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
+#endif
+
+extern int sprintf(char *buf, const char *fmt, ...);
+extern char * get_slot_name_suffix(void);
+
+static int get_rpmb_key(uint8_t key[32])
+{
+#ifndef LIGHT_KDF_RPMB_KEY
+    memcpy(key, emmc_rpmb_key_sample, sizeof(emmc_rpmb_key_sample));
+
+    return 0;
+#else
+	uint32_t kdf_rpmb_key_length = 0;
+	int ret = 0;
+	ret = csi_kdf_gen_hmac_key(key, &kdf_rpmb_key_length);
+	if (ret != 0) {
+		return -1;
+	}
+
+    return 0;
+#endif
+}
+
+static int get_image_file_size(unsigned long img_src_addr)
+{
+	img_header_t *img = (img_header_t *)img_src_addr;
+	uint8_t magiccode[4] = {0};
+
+	magiccode[3] = img->magic_num & 0xff;
+	magiccode[2] = (img->magic_num & 0xff00) >> 8;
+	magiccode[1] = (img->magic_num & 0xff0000) >> 16;
+	magiccode[0] = (img->magic_num & 0xff000000) >> 24;
+	if (memcmp(header_magic, magiccode, 4) == 0) {
+		return -1;
+	}
+
+	return img->image_size;
+}
+
+static int verify_and_load_image(unsigned long image_addr_src, unsigned long image_addr_dst)
+{
+    int ret = 0;
+	unsigned int image_size = 0;
+
+	if (image_have_head(image_addr_src) == 1) {
+        ret = csi_sec_init();
+        if (ret != 0) {
+			return -1;
+		}
+
+        ret = csi_sec_custom_image_verify(image_addr_src, UBOOT_STAGE_ADDR);
+        if (ret != 0) {
+            printf("image verify error\r\n");
+            return -2;
+        }
+
+		image_size = get_image_file_size(image_addr_src);
+		if (image_size  < 0) {
+            printf("image get size error\r\n");
+			return -3;
+		}
+
+		memmove((void *)image_addr_dst, (const void *)(image_addr_src + HEADER_SIZE), image_size);
+	} else {
+        printf("in secure mode but image has no header\r\n");
+		return -4;
+	}
+
+    return 0;
+}
+
+int verify_and_load_tee_tf_image(void)
+{
+    int ret = 0;
+
+    ret = verify_and_load_image(LIGHT_TF_FW_TMP_ADDR, LIGHT_TF_FW_ADDR);
+    if (ret != 0) {
+        printf("verify tf image failed\r\n");
+        return ret;
+    }
+    printf("verify trust firmware image success\r\n");
+
+    ret = verify_and_load_image(LIGHT_TEE_FW_ADDR, LIGHT_TEE_FW_ADDR);
+    if (ret != 0) {
+        printf("verify tee image failed\r\n");
+        return ret;
+    }
+    printf("verify tee image success\r\n");
+
+    return 0;
+}
+
+/* In order to use common bootloader for both secure boot and non-secure boot,
+   we only know the boot type through reading the sec_boot field in efuse. Due to
+   the efuse is only accessed in lifecycle(DEV/OEM/PRO/RMP), we ensure it must be
+   non-secure boot in lifecycle(INIT) */
+bool get_system_boot_type(void)
+{
+	bool btype = true; /* false: non-secure boot | true: secure boot */
+#if 0
+	int lc = 0;
+	sboot_st_t sb_flag = SECURE_BOOT_DIS;
+	int ret = 0;
+#endif
+	int sb_emulater = 0;
+
+	sb_emulater = env_get_ulong("sb_emulater", 10, 0);
+	if (sb_emulater == 0) {
+		btype = false;
+	}
+# if 0
+	ret = csi_efuse_get_lc(&lc);
+	/* 0: LC_INIT, 1: LC_DEV, 2: LC_OEM, 3: LC_PRO */
+	if ((ret == 0) && (lc != 0)) {
+		csi_efuse_api_init();
+
+		/* Check platform secure boot enable ? */
+		ret = csi_efuse_get_secure_boot_st(&sb_flag);
+		if ((ret == 0) && (sb_flag == SECURE_BOOT_EN))
+			btype = true;
+
+		csi_efuse_api_uninit();
+	}
+#endif
+	return btype;
+}
+
+int sec_read_rollback_index(size_t rollback_index_slot, uint64_t *out_rollback_index)
+{
+	char runcmd[64] = {0};
+	unsigned char blkdata[RPMB_BLOCK_SIZE];
+    size_t rpmb_block = (rollback_index_slot * sizeof(uint64_t)) / RPMB_BLOCK_SIZE + RPMB_ROLLBACK_BLOCK_START;
+    size_t rpmb_offset = (rollback_index_slot * sizeof(uint64_t)) % RPMB_BLOCK_SIZE;
+
+    sprintf(runcmd, "mmc rpmb read 0x%lx %ld 1", (unsigned long)blkdata, rpmb_block);
+	if(run_command(runcmd, 0)) {
+        printf("read_rollback_index failed, mmc read error\r\n");
+        return -1;
+    }
+
+    *out_rollback_index = *(uint64_t*)(blkdata + rpmb_offset);
+	return 0;
+}
+
+int sec_write_rollback_index(size_t rollback_index_slot, uint64_t rollback_index)
+{
+    char runcmd[64] = {0};
+	unsigned char blkdata[RPMB_BLOCK_SIZE];
+    size_t rpmb_block = (rollback_index_slot * sizeof(uint64_t)) / RPMB_BLOCK_SIZE + RPMB_ROLLBACK_BLOCK_START;
+    size_t rpmb_offset = (rollback_index_slot * sizeof(uint64_t)) % RPMB_BLOCK_SIZE;
+    uint8_t rpmb_key[32];
+
+    sprintf(runcmd, "mmc rpmb read 0x%lx %ld 1", (unsigned long)blkdata, rpmb_block);
+	if(run_command(runcmd, 0)) {
+        printf("read_rollback_index failed, mmc read error\r\n");
+        return -1;
+    }
+
+    *(uint64_t*)(blkdata + rpmb_offset) = rollback_index;
+
+    if (get_rpmb_key(rpmb_key) != 0) {
+        return -2;
+    }
+
+	sprintf(runcmd, "mmc rpmb write 0x%lx %ld 1 0x%lx", (unsigned long)blkdata, rpmb_block, (unsigned long)rpmb_key);
+    if(run_command(runcmd, 0)) {
+        printf("read_rollback_index failed, mmc write error\r\n");
+        return -3;
+    }
+
+    return 0;
+}
+
+static int do_secimg_load(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+    bool sb_enable = false;
+    const char *secimgs_load_str = VAL_SECIMG_LOAD;
+    int ret = -1;
+    int teepart = 0;
+
+#ifdef CONFIG_ANDROID_AB
+	char *slot_suffix = get_slot_name_suffix();
+    teepart = env_get_ulong("mmcteepart", 10, 8);
+	if ((strcmp(slot_suffix, "_a") == 0) && (teepart != 8)) {
+		/* Switch mmcbootpart to "_b" */
+		env_set_ulong("mmcbootpart", 2);
+		/* Switch mmcteepart to "_b" */
+		env_set_ulong("mmcteepart", 8);
+	} else if ((strcmp(slot_suffix, "_b") == 0) && (teepart != 9)){
+		/* Switch mmcbootpart to "_b" */
+		env_set_ulong("mmcbootpart", 3);
+		/* Switch mmcteepart to "_b" */
+		env_set_ulong("mmcteepart", 9);
+	}
+#endif
+
+	sb_enable = get_system_boot_type();
+	if (sb_enable) {
+		/* By default, the value for ENV-SEC-M-LOAD is always to load opensbi image.
+		* if secure boot is enable, we force to change the value to load tee image.
+		* but Never to save it in volatile-RAM
+		*/
+		ret = env_set(ENV_SECIMG_LOAD, secimgs_load_str);
+		if (ret != 0) {
+			printf("Rewrite ENV (%s) fails\n", ENV_SECIMG_LOAD);
+			return CMD_RET_FAILURE;
+		}
+	}
+
+	return CMD_RET_SUCCESS;
+}
+
+U_BOOT_CMD(
+	secimg_load, 1, 1,	do_secimg_load,
+	"Runtime-load secure image if secure system is enable",
+	NULL
+);

board/thead/light-c910/spl.c

@@ -48,6 +48,7 @@ static struct light_reset_list light_post_reset_lists[] = {
 	{0x00000002, 0xFFEF528000}, /* VO sys_reg: GPU rst */
 	{0x00000003, 0xFFEF528000}, /* VO sys_reg: GPU rst */
 	{0x00000007, 0xFFFF529004}, /* VO sys_reg: DPU rst */
+	{0x07FFFF18, 0xFFCB000014}, /* Audio sys_reg: DMA rst */
 };
 
 static void light_pre_reset_config(void)
@@ -301,12 +302,15 @@ void cpu_performance_enable(void)
 #define CSR_MHINT2_E	0x7cc
 #define CSR_MHINT4	0x7ce
 	csr_write(CSR_SMPEN, 0x1);
-	csr_write(CSR_MHINT2_E, csr_read(CSR_MHINT2_E) | 0x20000);
+	// FIXME set mhint2[22] to enable core icg en
+	csr_write(CSR_MHINT2_E, csr_read(CSR_MHINT2_E) | 0x420000);
 	csr_write(CSR_MHINT4, csr_read(CSR_MHINT4) | 0x410);
 	csr_write(CSR_MCCR2, 0xe2490009);
-	csr_write(CSR_MHCR, 0x11ff);
+	// FIXME: Clear bit[12] to disable L0BTB.
+	csr_write(CSR_MHCR, 0x17f); // clear bit7 to disable indirect brantch prediction
 	csr_write(CSR_MXSTATUS, 0x638000);
-	csr_write(CSR_MHINT, 0x6e30c);
+	csr_write(CSR_MHINT, 0x6e30c | (1<<21) | (1<<22)); // set bit21 & bit 22 to close tlb & fence broadcast
+	mdelay(50); // workaround
 }
 
 static int bl1_img_have_head(unsigned long img_src_addr)
@@ -399,9 +403,20 @@ void board_init_f(ulong dummy)
 	light_board_init_r(NULL, 0);
 }
 
+static uint32_t get_custom_boot_seq(void)
+{
+	/* boot media definition */
+	/* BOOT_DEVICE_MMC1 - boot from eMMC or SD card */
+	/* BOOT_DEVICE_NAND - boot from nand flash */
+	/* BOOT_DEVICE_SPI - boot from spi flash */
+	/* TODO: user can decide the boot media according their own configuration */
+	return BOOT_DEVICE_MMC1;
+}
+
 void board_boot_order(u32 *spl_boot_list)
 {
 #define SOC_OM_ADDRBASE        0xffef018010
+#if CONFIG_IS_ENABLED(LIGHT_BOOT_FORCE_SEQ)
 	switch (readl((void *)SOC_OM_ADDRBASE) & 0x7) {
 	case 0:
 	case 1:
@@ -428,6 +443,8 @@ void board_boot_order(u32 *spl_boot_list)
 	default:
 		spl_boot_list[0] = BOOT_DEVICE_NONE;
 	}
-
+#else
+	spl_boot_list[0] = get_custom_boot_seq();
+#endif
 	cpu_performance_enable();
 }

board/thead/light-c910/sys_clk.c

@@ -18,6 +18,8 @@
 #define LIGHT_DSP_SUBSYS_ADDRBASE	0xffff041000
 #define LIGHT_AUDIO_SUBSYS_ADDRBASE	0xffcb000000
 #define LIGHT_APSYS_RSTGEN_ADDRBASE	0xffff015000
+#define LIGHT_DPU_CLOCK_GATING_CTRL0	0xffef601A28
+#define LIGHT_DPU_CLOCK_GATING_CTRL1    0xffef601A2C
 
 void show_sys_clk(void)
 {
@@ -41,9 +43,9 @@ void cpu_clk_config(uint32_t cpu_freq)
 	udelay(11);
 
 	/* config bus: cpu clk ratio to 1:1 */
-	writel((readl(LIGHT_APCLK_ADDRBASE + 0x100) & (~(0x7<<8))) | (0x0<<8), (void *)(LIGHT_APCLK_ADDRBASE + 0x100)); // ratio=0
-	writel(readl(LIGHT_APCLK_ADDRBASE + 0x100) & (~(0x1<<11)), (void *)(LIGHT_APCLK_ADDRBASE + 0x100)); // sync=0
-	writel(readl(LIGHT_APCLK_ADDRBASE + 0x100) | (0x1<<11), (void *)(LIGHT_APCLK_ADDRBASE + 0x100)); // sync=1
+	writel((readl((const volatile void __iomem *)(LIGHT_APCLK_ADDRBASE + 0x100)) & (~(0x7<<8))) | (0x0<<8), (void *)(LIGHT_APCLK_ADDRBASE + 0x100)); // ratio=0
+	writel(readl((const volatile void __iomem *)(LIGHT_APCLK_ADDRBASE + 0x100)) & (~(0x1<<11)), (void *)(LIGHT_APCLK_ADDRBASE + 0x100)); // sync=0
+	writel(readl((const volatile void __iomem *)(LIGHT_APCLK_ADDRBASE + 0x100)) | (0x1<<11), (void *)(LIGHT_APCLK_ADDRBASE + 0x100)); // sync=1
 
 	/* switch c910_cclk to cpu_pll1_foutpostdiv */
 	tmp = readl((void *)LIGHT_APCLK_ADDRBASE + 0x100);
@@ -285,6 +287,52 @@ void sys_clk_config(void)
 	tmp = readl((void *)LIGHT_APCLK_ADDRBASE + 0x1c8);
 	tmp |= 0x30;
 	writel(tmp, (void *)LIGHT_APCLK_ADDRBASE + 0x1c8);
+
+	/* The boards other than the LightA board perform the bus down-speed operation */
+
+#if defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_DISCRETE) || defined (CONFIG_TARGET_LIGHT_FM_C910_B_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_B_POWER) || defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_B)
+	/* axi_sram_clk: 812.8512MHz -> 688.128MHz */
+	tmp = readl((void *)LIGHT_AONCLK_ADDRBASE + 0x104);
+	tmp |= 0x2000;
+	writel(tmp, (void *)LIGHT_AONCLK_ADDRBASE + 0x104);
+
+	/* visys_aclk_m decrease frequency 792MHZ->594MHZ */
+	tmp = readl((void *)LIGHT_APCLK_ADDRBASE + 0x1d0);
+	tmp &= ~0x00100000;
+	writel(tmp, (void *)LIGHT_APCLK_ADDRBASE + 0x1d0);
+
+	tmp &= ~0x000f0000;
+	tmp |= 0x00140000;
+	writel(tmp, (void *)LIGHT_APCLK_ADDRBASE + 0x1d0);
+	/* vosys_aclk_m：792MHz->594MHz */
+	tmp = readl((void *)LIGHT_APCLK_ADDRBASE + 0x1dc);
+	tmp &= ~0x00000020;
+	writel(tmp, (void *)LIGHT_APCLK_ADDRBASE + 0x1dc);
+
+	tmp &= ~0x0000000f;
+	tmp |= 0x00000024;
+	writel(tmp, (void *)LIGHT_APCLK_ADDRBASE + 0x1dc);
+
+	/* vpsys_axi_aclk：792MHz->594MHz */
+	tmp = readl((void *)LIGHT_APCLK_ADDRBASE + 0x1e0);
+	tmp &= ~0x00001000;
+	writel(tmp, (void *)LIGHT_APCLK_ADDRBASE + 0x1e0);
+
+	tmp &= ~0x00000f00;
+	tmp |= 0x00001400;
+	writel(tmp, (void *)LIGHT_APCLK_ADDRBASE + 0x1e0);
+
+	/* npu_cclk：1000MHz->792MHz */
+	tmp = readl((void *)LIGHT_APCLK_ADDRBASE + 0x1c8);
+	tmp |= 0x00000040;
+	writel(tmp, (void *)LIGHT_APCLK_ADDRBASE + 0x1c8);
+
+
+	/* Enable dpu auto clock gating */
+	writel(0, (void __iomem *)LIGHT_DPU_CLOCK_GATING_CTRL0);
+	writel(0, (void __iomem *)LIGHT_DPU_CLOCK_GATING_CTRL1);
+#endif
+
 #endif
 }
 

board/thead/light-c910/timer.c

@@ -0,0 +1,224 @@
+/*
+ * Copyright (C) 2017-2020 Alibaba Group Holding Limited
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/types.h>
+#include <thead/clock_config.h>
+#include <linux/bitops.h>
+#include <asm/arch-thead/light-iopmp.h>
+#include <asm/arch-thead/light-plic.h>
+
+#define DW_TIMER0_BASE		0xffefc32000
+#define DW_TIMER0_TLC_REG	(DW_TIMER0_BASE + 0x00)		/* Offset: 0x000 (R/W) TimerLoadCount */
+#define DW_TIMER0_TCV_REG	(DW_TIMER0_BASE + 0X04)		/* Offset: 0x004 (R/ ) TimerCurrentValue */
+#define DW_TIMER0_TCR_REG       (DW_TIMER0_BASE + 0X08)         /* Offset: 0x008 (R/W) TimerControlReg */
+#define DW_TIMER0_TEOI_REG      (DW_TIMER0_BASE + 0X0C)         /* Offset: 0x00c (R/ ) TimerEOI */
+#define DW_TIMER0_TIS_REG       (DW_TIMER0_BASE + 0X10)         /* Offset: 0x010 (R/ ) TimerIntStatus */
+
+/*! Timer Int Status,     offset: 0x10 */
+#define DW_TIMER_INT_STATUS_Pos                                        (0U)
+#define DW_TIMER_INT_STATUS_Msk                                        (0x1U << DW_TIMER_INT_STATUS_Pos)
+#define DW_TIMER_INT_STATUS_EN                                         DW_TIMER_INT_STATUS_Msk
+
+/*! Timer1 Control Reg,	       offset: 0x08 */
+#define DW_TIMER_CTL_ENABLE_SEL_Pos                                    (0U)
+#define DW_TIMER_CTL_ENABLE_SEL_Msk                                    (0x1U << DW_TIMER_CTL_ENABLE_SEL_Pos)
+#define DW_TIMER_CTL_ENABLE_SEL_EN                                     DW_TIMER_CTL_ENABLE_SEL_Msk
+
+#define DW_TIMER_CTL_MODE_SEL_Pos                                      (1U)
+#define DW_TIMER_CTL_MODE_SEL_Msk                                      (0x1U << DW_TIMER_CTL_MODE_SEL_Pos)
+#define DW_TIMER_CTL_MODE_SEL_EN                                       DW_TIMER_CTL_MODE_SEL_Msk
+
+#define DW_TIMER_CTL_INT_MASK_Pos                                      (2U)
+#define DW_TIMER_CTL_INT_MASK_Msk                                      (0x1U << DW_TIMER_CTL_INT_MASK_Pos)
+#define DW_TIMER_CTL_INT_MAKS_EN                                       DW_TIMER_CTL_INT_MASK_Msk
+
+#define DW_TIMER_CTL_HARD_TRIG_Pos                                     (4U)
+#define DW_TIMER_CTL_HARD_TRIG_Msk                                     (0x1U << DW_TIMER_CTL_HARD_TRIG_Pos)
+#define DW_TIMER_CTL_HARD_TRIG_EN                                      DW_TIMER_CTL_HARD_TRIG_Msk
+
+/*! Timer EOI,            offset: 0x0c */
+#define DW_TIMER_EOI_REG_Pos                                           (0U)
+#define DW_TIMER_EOI_REG_Msk                                           (0x1U << DW_TIMER_EOI_REG_Pos)
+#define DW_TIMER_EOI_REG_EN                                            DW_TIMER_EOI_REG_Msk
+
+#define TIMER0_IRQ_NUM	16
+#define TIMER0_FREQ_HZ	125000000U
+#define DW_TIMER_GET_RELOAD_VAL(_tim_, _frq_)      ((_tim_ < 25000U) ? ((_frq_ * _tim_) / 1000U) : (_frq_ * (_tim_ / 1000U)))
+
+static int time_user_defined_flag = 0;
+
+static void csi_timer_stop(void);
+
+static inline u32 dw_timer_get_int_status(void)
+{
+	return (readl((void __iomem *)DW_TIMER0_TIS_REG) & DW_TIMER_INT_STATUS_EN) ?  1 : 0;
+}
+
+static inline void dw_timer_clear_irq(void)
+{
+	readl((void __iomem *)DW_TIMER0_TEOI_REG);
+}
+
+static inline void dw_timer_write_load(uint32_t value)
+{
+	writel(value, (void __iomem *)DW_TIMER0_TLC_REG);
+}
+
+static inline void dw_timer_set_mode_load(void)
+{
+	writel((readl((void __iomem *)DW_TIMER0_TCR_REG) | DW_TIMER_CTL_MODE_SEL_EN), (void __iomem *)DW_TIMER0_TCR_REG);
+}
+
+static inline void dw_timer_set_disable(void)
+{
+	u32 data = readl((void __iomem *)DW_TIMER0_TCR_REG);
+
+	data &= ~DW_TIMER_CTL_ENABLE_SEL_EN;
+	writel(data, (void __iomem *)DW_TIMER0_TCR_REG);
+}
+
+static inline void dw_timer_set_enable(void)
+{
+	u32 data = readl((void __iomem *)DW_TIMER0_TCR_REG);
+
+	data |= DW_TIMER_CTL_ENABLE_SEL_EN;
+	writel(data, (void __iomem *)DW_TIMER0_TCR_REG);
+}
+
+static inline void dw_timer_set_unmask(void)
+{
+	u32 data = readl((void __iomem *)DW_TIMER0_TCR_REG);
+
+	data &= ~DW_TIMER_CTL_INT_MAKS_EN;
+	writel(data, (void __iomem *)DW_TIMER0_TCR_REG);
+}
+
+static inline void dw_timer_set_mask(void)
+{
+	u32 data = readl((void __iomem *)DW_TIMER0_TCR_REG);
+
+	data |= DW_TIMER_CTL_INT_MAKS_EN;
+	writel(data, (void __iomem *)DW_TIMER0_TCR_REG);
+}
+
+static void dw_timer_irq_handler(void)
+{
+	debug("[%s,%d]\n", __func__, __LINE__);
+	if (dw_timer_get_int_status()) {
+		dw_timer_clear_irq();
+		csi_timer_stop();
+		debug("[%s,%d]\n", __func__, __LINE__);
+		time_user_defined_flag = 1;
+	}
+}
+
+static inline void dw_timer_reset_register(void)
+{
+	writel(0, (void __iomem *)DW_TIMER0_TLC_REG);
+	writel(0, (void __iomem *)DW_TIMER0_TCV_REG);
+}
+
+static int csi_timer_start(u32 timeout_us)
+{
+	u32 timer_freq = TIMER0_FREQ_HZ;
+	u32 tmp_load = DW_TIMER_GET_RELOAD_VAL(timeout_us, timer_freq);
+
+	dw_timer_set_mode_load();
+
+	//FIXME: no less than 10
+	if (tmp_load < 10)
+		tmp_load = 10;
+
+	dw_timer_write_load(tmp_load);
+
+	dw_timer_set_disable();
+	dw_timer_set_enable();
+	dw_timer_set_unmask();
+
+	return 0;
+}
+
+static void csi_timer_stop(void)
+{
+	dw_timer_set_mask();
+	dw_timer_set_disable();
+}
+
+static void timer_interrupt_init(void)
+{
+	irq_handler_register(TIMER0_IRQ_NUM, dw_timer_irq_handler);
+	irq_priority_set(TIMER0_IRQ_NUM);
+	irq_enable(TIMER0_IRQ_NUM);
+	arch_local_irq_enable();
+}
+
+static void timer_interrupt_uninit(void)
+{
+	arch_local_irq_disable();
+	irq_disable(TIMER0_IRQ_NUM);
+}
+
+static int csi_timer_init(void)
+{
+	dw_timer_reset_register();
+	timer_interrupt_init();
+	return 0;
+}
+
+static void csi_timer_uinit(void)
+{
+	timer_interrupt_uninit();
+	dw_timer_reset_register();
+}
+
+int timer_alarm_set(cmd_tbl_t *cmdtp, int flag, int argc,
+		char * const argv[])
+{
+	unsigned long time_us;
+	int ret, state;
+	u32 timeout = 0;
+
+	if (argc != 2) {
+		printf("invalid input parameters\n");
+		return -EINVAL;
+	}
+
+	if (strict_strtoul(argv[1], 10, &time_us) < 0)
+		return CMD_RET_USAGE;
+
+	time_us = time_us * 1000000;
+	ret = csi_timer_init();
+	if(ret) {
+		printf("failed to initialize the timer\n");
+		return -EINVAL;
+	}
+
+	time_user_defined_flag = 0;
+	state = csi_timer_start(time_us);
+	if (state) {
+		printf("failed to start the timer0\n");
+		return ret;
+	}
+
+	do {
+
+		timeout++;
+		//if (!timeout)
+		//	break;
+		mdelay(1000);
+		printf("[%s,%d]wait for timer interrupt, %d seconds elapsed\n",
+				__func__, __LINE__, timeout);
+
+	} while (!time_user_defined_flag);
+
+	csi_timer_uinit();
+
+	return 0;
+}
+
+U_BOOT_CMD(timer_alarm, 2, 0, timer_alarm_set, "timer_alarm 10", "timer interrupt test");

board/thead/light-c910/version_rollback.c

@@ -0,0 +1,100 @@
+/*
+ * Copyright (C) 2017-2020 Alibaba Group Holding Limited
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <env.h>
+
+
+static int rollback_part(const char *partition, const char *partition_alt)
+{
+	char *p;
+	int ret;
+	int tmp;
+
+	p = env_get(partition_alt);
+	if (p == NULL) {
+		return 0;
+	}
+	tmp = 1;
+	printf("Rollback partition %s to %s\n", partition, p);
+	ret = env_set(partition, p);
+	if (ret) {
+		printf("Failed to set env %s %s: ret = %d\n", partition, p, ret);
+		tmp = -1;
+	}
+	ret = env_set(partition_alt, NULL);
+	if (ret) {
+		printf("Failed to del env %s: ret = %d\n", partition_alt, ret);
+		tmp = -1;
+	}
+	return tmp;
+}
+
+static int upgrade_rollback_check(void)
+{
+	unsigned long bootlimit;
+	unsigned long bootcount;
+	char *p;
+	char buf[20];
+	int ret;
+	int save;
+
+	p = env_get("bootlimit");
+	if (p == NULL) {
+		return -1;
+	}
+	if (!strcmp(p, "0")) {
+		return 0;
+	} else {
+		if (strict_strtoul(p, 16, &bootlimit) < 0) {
+			printf("Failed to strict_strtoul bootlimit\n");
+			return -1;
+		}
+	}
+	p = env_get("bootcount");
+	if (p == NULL) {
+		bootcount = 0;
+	} else if (strict_strtoul(p, 16, &bootcount) < 0) {
+		bootcount = 0;
+	}
+	save = 0;
+	bootcount++;
+	if (bootcount == bootlimit + 1) {
+		save = 1;
+		printf("Failed to start for %lu times, will rollback!\n", bootlimit);
+		rollback_part("boot_partition", "boot_partition_alt");
+		rollback_part("root_partition", "root_partition_alt");
+	} else if (bootcount < bootlimit + 1) {
+		save = 1;
+	}
+	if (save) {
+		snprintf(buf, sizeof(buf), "%lu", bootcount);
+		ret = env_set("bootcount", buf);
+		if (ret) {
+			printf("Failed to set env bootcount %s: ret = %d\n", buf, ret);
+		}
+		ret = env_save();
+		if (ret) {
+			printf("Failed to env_save: ret = %d\n", ret);
+		}
+	}
+	
+	return 0;
+}
+
+static int do_rollback(cmd_tbl_t *cmdtp, int flag, int argc,
+			char * const argv[])
+{
+    upgrade_rollback_check();
+	return CMD_RET_SUCCESS;
+}
+
+U_BOOT_CMD(
+	rollback, 1, 1,	do_rollback,
+	"Automatic rollback if upgrade fails",
+	NULL
+);

cmd/Kconfig

@@ -263,6 +263,12 @@ config CMD_BOOTI
 	help
 	  Boot an AArch64 Linux Kernel image from memory.
 
+config CMD_BOOTANDROID
+	bool "bootandroid"
+	default n
+	help
+	Boot an android image from mmc.
+
 config BOOTM_LINUX
 	bool "Support booting Linux OS images"
 	depends on CMD_BOOTM || CMD_BOOTZ || CMD_BOOTI
@@ -369,6 +375,18 @@ config CMD_FDT
 	help
 	  Do FDT related setup before booting into the Operating System.
 
+config SUPPORT_EXTENSION_SCAN
+	bool
+
+config CMD_EXTENSION
+	bool "Extension board management command"
+	select CMD_FDT
+	depends on SUPPORT_EXTENSION_SCAN
+	help
+	  Enables the "extension" command, which allows to detect
+	  extension boards connected to the system, and apply
+	  corresponding Device Tree overlays.
+
 config CMD_GO
 	bool "go"
 	default y

cmd/Makefile

@@ -48,6 +48,7 @@ ifdef CONFIG_POST
 obj-$(CONFIG_CMD_DIAG) += diag.o
 endif
 obj-$(CONFIG_CMD_DTIMG) += dtimg.o
+obj-$(CONFIG_CMD_EXTENSION) += extension_board.o
 obj-$(CONFIG_CMD_ECHO) += echo.o
 obj-$(CONFIG_ENV_IS_IN_EEPROM) += eeprom.o
 obj-$(CONFIG_CMD_EEPROM) += eeprom.o
@@ -175,6 +176,7 @@ obj-$(CONFIG_CMD_REGULATOR) += regulator.o
 obj-$(CONFIG_CMD_BLOB) += blob.o
 
 # Android Verified Boot 2.0
+obj-$(CONFIG_CMD_BOOTANDROID) += bootandroid.o
 obj-$(CONFIG_CMD_AVB) += avb.o
 
 obj-$(CONFIG_DDR_SCAN) += ddrscan.o

cmd/avb.c

@@ -312,6 +312,10 @@ int do_avb_verify_part(cmd_tbl_t *cmdtp, int flag,
 		printf("Unknown error occurred\n");
 	}
 
+#ifdef CONFIG_ANDROID_BOOT_IMAGE
+	if (out_data)
+		avb_slot_verify_data_free(out_data);
+#endif
 	return res;
 }
 

cmd/bootandroid.c

@@ -0,0 +1,566 @@
+/*
+ * (C) Copyright 2018, Linaro Limited
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <avb_verify.h>
+#include <command.h>
+#include <env.h>
+#include <image.h>
+#include <malloc.h>
+#include <mmc.h>
+#include <android_image.h>
+#include <android_bootloader_message.h>
+#include <xbc.h>
+
+#define ENV_KERNEL_ADDR  "kernel_addr"
+#define ENV_RAMDISK_ADDR "ramdisk_addr"
+#define ENV_DTB_ADDR     "dtb_addr"
+#define DEFAULT_KERNEL_ADDR  0x00200800
+#define DEFAULT_RAMDISK_ADDR LIGHT_ROOTFS_ADDR
+#define DEFAULT_DTB_ADDR     LIGHT_DTB_ADDR
+#define ENV_RAMDISK_SIZE "ramdisk_size"
+#define MISC_PARTITION "misc"
+#define RECOVERY_PARTITION "recovery"
+#define BOOT_PARTITION "boot"
+#define VENDOR_BOOT_PARTITION "vendor_boot"
+
+#define BOOTDEV_DEFAULT		0
+#define BCB_BOOTONCE	"bootonce-bootloader"
+#define BCB_BOOTRECOVERY	"boot-recovery"
+
+
+/*
+ * Knowing secure boot is enable or disable dependents on
+ * special data field in efuse and efuse control register.
+ */
+extern bool get_system_boot_type(void);
+/*
+ * The suffix for partition name is from the value of ENV_BOOTAB
+ */
+static const char *slot_name_suffix = NULL;
+
+/*
+ * BOOT IMAGE HEADER V3/V4 PAGESIZE
+ * Source code:system/tools/mkbootimg/unpack_bootimg.py
+ */
+#define BOOT_IMAGE_HEADER_V3_PAGESIZE 4096
+
+static struct AvbOps *avb_ops = NULL;
+static struct bootloader_message_ab *s_bcb = NULL;
+static struct bootloader_control *boot_ctl = NULL;
+
+static char *get_boot_partition_name_suffix(void)
+{
+#ifdef CONFIG_ANDROID_AB
+    if (boot_ctl != NULL) {
+		/* index 0 is _a, index 1 is _b*/
+		if(boot_ctl->slot_info[0].priority < boot_ctl->slot_info[1].priority) {
+			strcpy(boot_ctl->slot_suffix, "_b");
+		} else {
+			strcpy(boot_ctl->slot_suffix, "_a");
+		}
+	} else {
+		printf("get_slot_suffix boot_ctl is null return _a");
+		return "_a";
+	}
+	printf("get_slot_suffix boot_ctl->slot_suffix %s\r\n", boot_ctl->slot_suffix);
+	return boot_ctl->slot_suffix;
+#else
+	return "";
+#endif
+}
+
+static void get_partition_name(const char *partion, char *partion_name)
+{
+	strcpy(partion_name, partion);
+	strcat(partion_name, get_boot_partition_name_suffix());
+}
+
+/*
+ *format 4 chars/bytes to a int number
+ */
+static int byteToInt(uint8_t* data,int offset)
+{
+	return data[offset+0] + (data[offset+1] << 8) + (data[offset+2] << 16) + (data[offset+3] << 24);
+}
+
+static int get_number_of_pages(int image_size, int page_size)
+{
+    return (image_size + page_size - 1) / page_size;
+}
+
+/**
+ * header_version >=3,get dtb data from vendor_boot.img ,else boot.img.
+ *
+ * header_version = 4,get bootconfig data from vendor_boot.img ,
+ * and append bootconfig to the end of ramdisk(initrd)
+ * doc:https://www.kernel.org/doc/html/next/translations/zh_CN/admin-guide/bootconfig.html#initrd
+ */
+static int prepare_data_from_vendor_boot(struct andr_img_hdr *hdr, int dtb_start, uint8_t** buf_bootconfig, int* vendor_bootconfig_size, bool isRecovery)
+{
+	int ret;
+	disk_partition_t part_info;
+	uint8_t* vendor_boot_data = NULL;
+	struct blk_desc *dev_desc  = blk_get_dev("mmc", CONFIG_FASTBOOT_FLASH_MMC_DEV);
+	char vb_part_name[32] = {0};
+
+	if (hdr == NULL) {
+		printf("invalid hdr\n");
+		return -1;
+	}
+
+	/* if the vendor boot partition name is beyond 32B, arise error */
+	if ((32 - strlen(VENDOR_BOOT_PARTITION)) < 2)
+		return -1;
+	
+    get_partition_name(VENDOR_BOOT_PARTITION, vb_part_name);
+
+	printf("blk_get_dev %s\n", vb_part_name);
+	if (!dev_desc || dev_desc->type == DEV_TYPE_UNKNOWN) {
+		printf("MMC err: invalid mmc device\n");
+		return -1;
+	}
+	/* Get boot partition info */
+	ret = part_get_info_by_name(dev_desc, vb_part_name, &part_info);
+	if (ret < 0) {
+		printf("MMC err: cannot find %s partition\n", vb_part_name);
+		return -1;
+	}
+
+    if (part_info.size * part_info.blksz > CONFIG_FASTBOOT_BUF_SIZE) {
+        return -1;
+    }
+    //vendor_boot_data = (uint8_t*)CONFIG_FASTBOOT_BUF_ADDR;
+
+	printf("vendor_boot_data part_info.size = %ld, part_info.blksz = %lu", part_info.size, part_info.blksz);
+	// reuse kernel start address to load vendor boot data
+	// because av_malloc(32M) failed in 2G devices
+	// TODO: why av_malloc failed
+	// ATTATION: If the vendor_boot partition size > boot partition size, it is error.
+	// avb_malloc(part_info.size * part_info.blksz);
+	vendor_boot_data = (uint8_t*)env_get_hex(ENV_KERNEL_ADDR, DEFAULT_KERNEL_ADDR);
+
+	ret = blk_dread(dev_desc, part_info.start, part_info.size, vendor_boot_data);
+	// vendor_boot.img
+	//* +------------------------+
+	//* | vendor boot header     | o pages
+	//* +------------------------+
+	//* | vendor ramdisk section | p pages
+	//* +------------------------+
+	//* | dtb                    | q pages
+	//* +------------------------+
+	//* | vendor ramdisk table   | r pages
+	//* +------------------------+
+	//* | bootconfig             | s pages
+	//* +------------------------+
+	//* o = (2124 + page_size - 1) / page_size
+	//* p = (vendor_ramdisk_size + page_size - 1) / page_size
+	//* q = (dtb_size + page_size - 1) / page_size
+	//* r = (vendor_ramdisk_table_size + page_size - 1) / page_size
+	//* s = (vendor_bootconfig_size + page_size - 1) / page_size
+
+	// see system/tools/mkbootimg/unpack_bootimg.py
+	// info.boot_magic = unpack('8s', args.boot_img.read(8))[0].decode()
+	// info.header_version = unpack('I', args.boot_img.read(4))[0]
+	// info.page_size = unpack('I', args.boot_img.read(4))[0]
+	// info.kernel_load_address = unpack('I', args.boot_img.read(4))[0]
+	// info.ramdisk_load_address = unpack('I', args.boot_img.read(4))[0]
+	// info.vendor_ramdisk_size = unpack('I', args.boot_img.read(4))[0]
+	// info.cmdline = cstr(unpack('2048s', args.boot_img.read(2048))[0].decode())
+	// info.tags_load_address = unpack('I', args.boot_img.read(4))[0]
+	// info.product_name = cstr(unpack('16s', args.boot_img.read(16))[0].decode())
+	// info.header_size = unpack('I', args.boot_img.read(4))[0]
+	// info.dtb_size = unpack('I', args.boot_img.read(4))[0]
+	// info.dtb_load_address = unpack('Q', args.boot_img.read(8))[0]
+	// info.vendor_ramdisk_table_size = unpack('I', args.boot_img.read(4))[0]
+	// vendor_ramdisk_table_entry_num = unpack('I', args.boot_img.read(4))[0]
+	// vendor_ramdisk_table_entry_size = unpack('I', args.boot_img.read(4))[0]
+	// info.vendor_bootconfig_size = unpack('I', args.boot_img.read(4))[0]
+	// num_vendor_ramdisk_table_pages = get_number_of_pages(
+	// 	info.vendor_ramdisk_table_size, page_size)
+	// vendor_ramdisk_table_offset = page_size * (
+	// 	num_boot_header_pages + num_boot_ramdisk_pages + num_boot_dtb_pages)
+	// bootconfig_offset = page_size * (num_boot_header_pages
+	// 	+ num_boot_ramdisk_pages + num_boot_dtb_pages
+	// 	+ num_vendor_ramdisk_table_pages)
+
+	int vendor_boot_pagesize = byteToInt(vendor_boot_data,12);//offset 12
+	int vendor_ramdisk_size = byteToInt(vendor_boot_data,24);//offset 24
+	int dtb_size = byteToInt(vendor_boot_data,2100);//offset 2100
+	int o = (2124 + vendor_boot_pagesize - 1) / vendor_boot_pagesize;
+	int p = (vendor_ramdisk_size + vendor_boot_pagesize - 1) / vendor_boot_pagesize;
+	int dtb_offset = vendor_boot_pagesize * (o + p);
+
+	hdr->dtb_size=  dtb_size;
+	memcpy((void *)(uint64_t)dtb_start, vendor_boot_data + dtb_offset, hdr->dtb_size);
+
+	int q=(hdr->dtb_size + vendor_boot_pagesize - 1) / vendor_boot_pagesize;
+	int vendor_ramdisk_table_size=byteToInt(vendor_boot_data,2112);//offset 2112
+	
+	int r=(vendor_ramdisk_table_size + vendor_boot_pagesize - 1) / vendor_boot_pagesize;
+	*vendor_bootconfig_size=byteToInt(vendor_boot_data,2124);//offset 2124
+	
+	*buf_bootconfig = avb_malloc(*vendor_bootconfig_size);
+	if (*buf_bootconfig == NULL) {
+		printf("vendor bootconfig malloc fail\n");
+		return -1;
+	}
+	int bootconfig_offset=vendor_boot_pagesize * (o + p + q + r);
+	memcpy(*buf_bootconfig, vendor_boot_data + bootconfig_offset, *vendor_bootconfig_size);
+
+#ifdef CONFIG_ANDROID_AB
+	char *find_str = NULL;
+	char *slot_suffix = get_boot_partition_name_suffix();
+    char *slot_suffx_pre = "androidboot.slot_suffix=";
+	printf("prepare_data_from_vendor_boot slot_suffix:%s\n", slot_suffix);
+    printf("prepare_data_from_vendor_boot slot_suffx_pre:%s\n", slot_suffx_pre);
+
+	find_str = strstr((char *)*buf_bootconfig, slot_suffx_pre);
+    if (find_str != NULL) {
+		memcpy(find_str + strlen(slot_suffx_pre), slot_suffix, strlen(slot_suffix));
+	}
+#endif
+
+	if (isRecovery) {
+		int i = 0;
+		struct vendor_ramdisk_table_entry *ramdisk_entry = NULL;
+		int vendor_ramdisk_table_offset = vendor_boot_pagesize * (o + p + q);
+		int vendor_ramdisk_table_entry_num = byteToInt(vendor_boot_data,2116);//offset 2116
+		printf("vendor_boot vendor_ramdisk_table_entry_num:%d\n",vendor_ramdisk_table_entry_num);
+		int vendor_ramdisk_table_entry_size = byteToInt(vendor_boot_data,2120);//offset 2116
+		printf("vendor_boot vendor_ramdisk_table_entry_size:%d\n",vendor_ramdisk_table_entry_size);
+		for (i = 0; i < vendor_ramdisk_table_entry_num; i++) {
+			ramdisk_entry = (struct vendor_ramdisk_table_entry*)(vendor_boot_data + vendor_ramdisk_table_offset
+											 + ( i * vendor_ramdisk_table_entry_size ));
+			if (ramdisk_entry->ramdisk_type != VENDOR_RAMDISK_TYPE_RECOVERY) {
+				continue;
+			}
+			printf("find recovery from ramdisk table.");
+			int ramdisk_start = env_get_hex(ENV_RAMDISK_ADDR, DEFAULT_RAMDISK_ADDR);
+			int recovery_ramdisk_offset = vendor_boot_pagesize * o + ramdisk_entry->ramdisk_offset;
+			memcpy((void *)(uint64_t)ramdisk_start, vendor_boot_data + recovery_ramdisk_offset,
+													 ramdisk_entry->ramdisk_size);//ramdisk
+			//get bootconfig form vendor_boot.img and append bootconfig to ramdisk
+			char* bootconfig_params = (char*)*buf_bootconfig;
+			int ret = addBootConfigParameters(bootconfig_params, *vendor_bootconfig_size,
+						ramdisk_start + ramdisk_entry->ramdisk_size , 0);
+			if (ret == -1) {
+				printf("\nadd BootConfig Parameters error!!!\n");
+			} else {
+				printf("\nramdisk size is changed,new value is:%d\n",ramdisk_entry->ramdisk_size + ret);
+				//set ramdisk size for bootm
+				env_set_hex(ENV_RAMDISK_SIZE, ramdisk_entry->ramdisk_size + ret);
+			}
+			break;
+		}
+	}
+
+	return 0;
+}
+
+static void prepare_loaded_parttion_data(const uint8_t* data, bool isRecovery)
+{
+	struct andr_img_hdr *hdr = (struct andr_img_hdr *)map_sysmem((phys_addr_t)data, 0);
+
+	if (IMAGE_FORMAT_ANDROID == genimg_get_format(hdr)) {
+		int dtb_start = env_get_hex(ENV_DTB_ADDR, DEFAULT_DTB_ADDR);
+		uint8_t* buf_bootconfig = NULL;
+		int size_bootconfig=0;
+
+		printf("Boot image header_version:%d\n", hdr->header_version);
+		if (hdr->header_version >= 3) {
+			// see system/tools/mkbootimg/unpack_bootimg.py
+			hdr->kernel_size = byteToInt((uint8_t *)data, 8);
+			hdr->ramdisk_size = byteToInt((uint8_t *)data, 12);
+			hdr->page_size = BOOT_IMAGE_HEADER_V3_PAGESIZE;
+			prepare_data_from_vendor_boot(hdr,dtb_start,&buf_bootconfig,&size_bootconfig,isRecovery);
+		}
+
+		int kernel_start = env_get_hex(ENV_KERNEL_ADDR, DEFAULT_KERNEL_ADDR);
+		int ramdisk_start = env_get_hex(ENV_RAMDISK_ADDR, DEFAULT_RAMDISK_ADDR);
+		// see system/tools/mkbootimg/unpack_bootimg.py
+ 		int page_size = hdr->page_size;
+		int num_header_pages = 1;
+		int num_kernel_pages = get_number_of_pages(hdr->kernel_size, page_size);
+		int num_ramdisk_pages = get_number_of_pages(hdr->ramdisk_size, page_size);
+		int kernel_offset = page_size * num_header_pages;
+		int ramdisk_offset = page_size * (num_header_pages + num_kernel_pages);
+		int dtb_offset = page_size * (num_header_pages + num_kernel_pages + num_ramdisk_pages);
+
+		printf("Boot image kernel_start:%x, kernel_offset:%x, kernel_size:%d\n", kernel_start, kernel_offset, hdr->kernel_size);
+		printf("Boot image ramdisk_start:%x, ramdisk_offset:%x, ramdisk_size:%d\n", ramdisk_start, ramdisk_offset, hdr->ramdisk_size);
+		printf("Boot image page_size:%d\n", hdr->page_size);
+		printf("dtb_offset:%x, dtb_size:%d\n", dtb_offset, hdr->dtb_size);
+
+ 		if (kernel_start + hdr->kernel_size > ramdisk_start || kernel_start + hdr->kernel_size > dtb_start) {
+			printf("boot.img kernel space and ramdis space are overlaped !!!\n");
+		} else {
+			memcpy((void *)(uint64_t)kernel_start, data + kernel_offset, hdr->kernel_size);
+			if (!isRecovery) {
+				memcpy((void *)(uint64_t)ramdisk_start, data + ramdisk_offset, hdr->ramdisk_size);
+			}
+
+			if( hdr->header_version < 3) {
+				//set ramdisk size for bootm
+				env_set_hex(ENV_RAMDISK_SIZE, hdr->ramdisk_size);
+				memcpy((void *)(uint64_t)dtb_start, data + dtb_offset, hdr->dtb_size);
+			} else if (!isRecovery) {
+				//get bootconfig form vendor_boot.img and append bootconfig to ramdisk
+				char* bootconfig_params=(char*)buf_bootconfig;
+				int ret = addBootConfigParameters(bootconfig_params, size_bootconfig,
+                            						ramdisk_start + hdr->ramdisk_size , 0);
+				if (ret == -1) {
+					printf("Bootconfig Err: add BootConfig Parameters error!!!\n");
+				} else {
+					printf("ramdisk size is updated to new value is:%d\n",hdr->ramdisk_size + ret);
+					//set ramdisk size for bootm
+					env_set_hex(ENV_RAMDISK_SIZE, hdr->ramdisk_size + ret);
+				}
+			}
+		}
+		if (buf_bootconfig != NULL) {
+			avb_free(buf_bootconfig);
+		}
+	}
+	unmap_sysmem(hdr);
+}
+
+static int prepare_boot_data(const AvbSlotVerifyData *out_data, bool isRecovery)
+{
+	int res = CMD_RET_FAILURE;
+	int i = 0;
+	int num_loaded_partition = out_data->num_loaded_partitions;
+
+	printf("@@@@ prepare loaded partition (%d) data start\n", num_loaded_partition);
+	for (i = 0; i < num_loaded_partition; i++) {
+		const AvbPartitionData *loaded_partition = &out_data->loaded_partitions[i];
+		
+		if (loaded_partition->partition_name != NULL) {
+			printf("partition_name=%s, data_size=%ld\n", \
+					loaded_partition->partition_name, loaded_partition->data_size);
+			prepare_loaded_parttion_data(loaded_partition->data, isRecovery);
+		}
+	}
+	return res;
+}
+
+static void prepare_partition_data(const char *name, bool isRecovery)
+{
+	int ret = 0;
+	disk_partition_t part_info;
+	struct blk_desc *dev_desc  = blk_get_dev("mmc", CONFIG_FASTBOOT_FLASH_MMC_DEV);
+	uint8_t *data = NULL;
+
+	printf("prepare_partition_data %s\n", name);
+	if (!dev_desc || dev_desc->type == DEV_TYPE_UNKNOWN) {
+		printf("MMC err: invalid mmc device\n");
+		return;
+	}
+	/* Get boot partition info */
+	ret = part_get_info_by_name(dev_desc, name, &part_info);
+	if (ret < 0) {
+		printf("MMC err: cannot find %s partition\n", name);
+		return;
+	}
+
+	data = avb_malloc(part_info.size * part_info.blksz);
+	if (data == NULL) {
+		printf("avb malloc(%ldKB) fails\n", part_info.size * part_info.blksz / 1024);
+		return;
+	}
+
+	ret = blk_dread(dev_desc, part_info.start, part_info.size, data);
+	prepare_loaded_parttion_data(data, isRecovery);
+	
+	printf("prepare_partition_data %s, read=%d, start:%lx, size:%ld, blksize:%lx\n", \
+			name, ret, part_info.start, part_info.size, part_info.blksz);
+
+	avb_free(data);
+}
+
+static void clear_bcb(void)
+{
+	int ret;
+	disk_partition_t part_info;
+	struct blk_desc *dev_desc  = blk_get_dev("mmc", CONFIG_FASTBOOT_FLASH_MMC_DEV);
+
+	//bcb clear and store
+	memset(s_bcb, 0, sizeof(struct bootloader_message_ab));
+
+	if (!dev_desc || dev_desc->type == DEV_TYPE_UNKNOWN) {
+		printf("BootAndriod bcb err: invalid mmc device\n");
+		return;
+	}
+	/* Get boot partition info */
+	ret = part_get_info_by_name(dev_desc, MISC_PARTITION, &part_info);
+	if (ret < 0) {
+		printf("BootAndriod bcb err: cannot find misc partition\n");
+		return;
+	}
+
+	ret = blk_dwrite(dev_desc, part_info.start, part_info.size, s_bcb);
+	printf("BootAndriod bcb info :clear_bcb write=%d, %ld,%ld,%ld\n", ret, part_info.start, part_info.size, part_info.blksz);
+}
+
+static int do_andriod_bcb_business(int *boot_recovery)
+{
+	AvbIOResult ret = AVB_IO_RESULT_OK;
+	size_t bytes_read = 0;
+	int res = CMD_RET_FAILURE;
+
+#ifdef CONFIG_ANDROID_AB
+	char *slot_suffix = "_a";
+#else
+	char *slot_suffix = "";
+#endif
+
+    if (avb_ops != NULL) {
+        avb_ops_free(avb_ops);
+        avb_ops = NULL;
+    }
+
+    avb_ops = avb_ops_alloc(BOOTDEV_DEFAULT);
+    if (avb_ops == NULL) {
+        goto _bcb_err;
+    }
+
+    if (s_bcb != NULL) {
+        avb_free(s_bcb);
+        s_bcb = NULL;
+    }
+
+	s_bcb = avb_malloc(sizeof(struct bootloader_message_ab));
+	if (s_bcb == NULL) {
+		goto _bcb_err;
+	}
+
+    if (boot_ctl != NULL) {
+        avb_free(boot_ctl);
+        boot_ctl = NULL;
+    }
+
+    boot_ctl = malloc(sizeof(struct bootloader_control));
+	if (boot_ctl == NULL)
+	{
+        ret = -2;
+		goto _bcb_err;
+	}
+
+	ret = avb_ops->read_from_partition(avb_ops,
+										MISC_PARTITION,
+										0,
+										sizeof(struct bootloader_message_ab),
+										s_bcb,
+										&bytes_read);
+	if (ret != AVB_IO_RESULT_OK) {
+		printf("BootAndriod Err: Bcb read failed\n");
+		goto _bcb_err;
+	}
+
+	/* Enter into fastboot mode if bcb string is bootonce or bootrecovery */
+	if (0 == strncmp(s_bcb->message.command, "bootonce-bootloader", strlen("bootonce-bootloader")))
+		{
+		printf("BootAndriod Info: Bcb read %ld bytes, %s\n", bytes_read, s_bcb->message.command);
+		printf("BootAndriod Info: Enter fastboot mode\n");
+		clear_bcb();
+		run_command("fastboot usb 0", 0);
+	}
+	else if (0 == strncmp(s_bcb->message.command, "boot-recovery", strlen("boot-recovery")))
+	{
+		printf("recovery slot_suffix = %s\n", slot_suffix);
+		*boot_recovery = 1;
+	}
+
+    memset(boot_ctl, 0, sizeof(struct bootloader_control));
+    memcpy(boot_ctl, (struct bootloader_control*)s_bcb->slot_suffix, sizeof(struct bootloader_control));
+
+	res = CMD_RET_SUCCESS;
+
+_bcb_err:
+	if (res != CMD_RET_SUCCESS) {
+        if (avb_ops != NULL) {
+            avb_ops_free(avb_ops);
+            avb_ops = NULL;
+        }
+
+		if (boot_ctl != NULL) {
+            avb_free(boot_ctl);
+            boot_ctl = NULL;
+        }
+
+        if (s_bcb != NULL) {
+            avb_free(s_bcb);
+            s_bcb = NULL;
+        }
+    }
+
+	return res;
+}
+
+static int do_bootandroid(struct cmd_tbl_s *cmdtp, int flag, int argc,
+						char * const argv[]) {
+	
+	const char * const requested_partitions[] = {"vbmeta", "boot", "vbmeta_system", NULL};
+	AvbSlotVerifyResult slot_result = AVB_SLOT_VERIFY_RESULT_OK;
+	AvbSlotVerifyData *slot_data = NULL;
+	AvbIOResult ret = AVB_IO_RESULT_OK;
+	AvbSlotVerifyFlags slotflags = AVB_SLOT_VERIFY_FLAGS_NONE;
+	AvbHashtreeErrorMode htflags = AVB_HASHTREE_ERROR_MODE_RESTART_AND_INVALIDATE;
+	int res = CMD_RET_FAILURE;
+    char bp_name[32] = {0};
+	int boot_recovery = 0;
+
+    res = do_andriod_bcb_business(&boot_recovery);
+    if (res != CMD_RET_SUCCESS) {
+        goto exit;
+    }
+
+	/* Retieve boot partition 's name suffix */
+	slot_name_suffix = get_boot_partition_name_suffix();
+
+	/* Start with slot verification in secure boot */
+	if (get_system_boot_type()) {
+		/* Verify boot partition requested in vbmeta.img */
+		slot_result = avb_slot_verify(avb_ops,
+									  requested_partitions,
+									  slot_name_suffix,
+									  slotflags,
+									  htflags,
+									&slot_data);
+
+		if (slot_result == AVB_SLOT_VERIFY_RESULT_OK) {
+			printf("BootAndriod Info: Request Partition are verified successfully\n");
+			printf("BootAndriod cmdline: slot_data.cmdline:%s\n", slot_data->cmdline);
+			prepare_boot_data(slot_data, boot_recovery ? true:false);
+			if (ret == 0) {
+				if (slot_data != NULL)
+					avb_slot_verify_data_free(slot_data);
+			}
+		} else {
+			/* In case of avb slot verification failure, Force system reset */
+			run_command("reset", 0);
+		}
+	} else {
+	/* Go to load BOOT partition directly in non-secure boot */
+        get_partition_name(BOOT_PARTITION, bp_name);
+		prepare_partition_data(bp_name, boot_recovery ? true:false);
+	}
+
+exit:
+	return res;
+}
+
+const char * get_slot_name_suffix(void)
+{
+	return slot_name_suffix;
+}
+
+U_BOOT_CMD(
+	bootandroid, 2,	1, do_bootandroid,
+	"bootandroid   - boot android bootimg from device\n",
+	"mmc0 | mmc1 | mmc2 | mmcX]\n    "
+	"- boot application image stored in storage device like mmc\n"
+);
+

cmd/booti.c

@@ -67,7 +67,6 @@ static int booti_start(cmd_tbl_t *cmdtp, int flag, int argc,
 int do_booti(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
 	int ret;
-
 	/* Consume 'booti' */
 	argc--; argv++;
 
@@ -119,18 +118,22 @@ U_BOOT_CMD(
 
 #endif
 
-#if CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_VAL_A) || CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_VAL_B) || CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_ANT_EVT)
+#if CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_VAL_A) || CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_VAL_B) || CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_ANT_REF) || CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_LPI4A)
+#if CONFIG_IS_ENABLED(LIGHT_SEC_UPGRADE)
 extern int light_secboot(int argc, char * const argv[]);
+#endif
 int do_secboot(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
-	if (light_secboot(argc, argv) != 0)
-		return -1;
-
+#if CONFIG_IS_ENABLED(LIGHT_SEC_UPGRADE)
+    if (light_secboot(argc, argv) != 0) {
+        return -1;
+    }
+#endif
 	return 0;
 }
 U_BOOT_CMD(
-	secboot, CONFIG_SYS_MAXARGS, 1, do_secboot, 
-	"verify image file with known pubkey which reside in father image or itself!", 
+	secboot, CONFIG_SYS_MAXARGS, 1, do_secboot,
+	"verify image file with known pubkey which reside in father image or itself!",
 	"vimage addr imgname[[tee/tf]	- verify specifed image resides in addr\n"
 );
 

cmd/extension_board.c

@@ -0,0 +1,167 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2021
+ * Köry Maincent, Bootlin, <kory.maincent@bootlin.com>
+ */
+
+#include <common.h>
+#include <command.h>
+#include <malloc.h>
+#include <extension_board.h>
+#include <mapmem.h>
+#include <linux/libfdt.h>
+#include <fdt_support.h>
+
+static LIST_HEAD(extension_list);
+
+static int extension_apply(struct extension *extension)
+{
+	char *overlay_cmd;
+	ulong extrasize, overlay_addr;
+	struct fdt_header *blob;
+
+	if (!working_fdt) {
+		printf("No FDT memory address configured. Please configure\n"
+		       "the FDT address via \"fdt addr <address>\" command.\n");
+		return CMD_RET_FAILURE;
+	}
+
+	overlay_cmd = env_get("extension_overlay_cmd");
+	if (!overlay_cmd) {
+		printf("Environment extension_overlay_cmd is missing\n");
+		return CMD_RET_FAILURE;
+	}
+
+	overlay_addr = env_get_hex("extension_overlay_addr", 0);
+	if (!overlay_addr) {
+		printf("Environment extension_overlay_addr is missing\n");
+		return CMD_RET_FAILURE;
+	}
+
+	env_set("extension_overlay_name", extension->overlay);
+	if (run_command(overlay_cmd, 0) != 0)
+		return CMD_RET_FAILURE;
+
+	extrasize = env_get_hex("filesize", 0);
+	if (!extrasize)
+		return CMD_RET_FAILURE;
+
+	fdt_shrink_to_minimum(working_fdt, extrasize);
+
+	blob = map_sysmem(overlay_addr, 0);
+	if (!fdt_valid(&blob))
+		return CMD_RET_FAILURE;
+
+	/* apply method prints messages on error */
+	if (fdt_overlay_apply_verbose(working_fdt, blob))
+		return CMD_RET_FAILURE;
+
+	return CMD_RET_SUCCESS;
+}
+
+static int do_extension_list(struct cmd_tbl *cmdtp, int flag,
+			     int argc, char *const argv[])
+{
+	int i = 0;
+	struct extension *extension;
+
+	if (list_empty(&extension_list)) {
+		printf("No extension registered - Please run \"extension scan\"\n");
+		return CMD_RET_SUCCESS;
+	}
+
+	list_for_each_entry(extension, &extension_list, list) {
+		printf("Extension %d: %s\n", i++, extension->name);
+		printf("\tManufacturer: \t\t%s\n", extension->owner);
+		printf("\tVersion: \t\t%s\n", extension->version);
+		printf("\tDevicetree overlay: \t%s\n", extension->overlay);
+		printf("\tOther information: \t%s\n", extension->other);
+	}
+	return CMD_RET_SUCCESS;
+}
+
+static int do_extension_scan(struct cmd_tbl *cmdtp, int flag,
+			     int argc, char *const argv[])
+{
+	struct extension *extension, *next;
+	int extension_num;
+
+	list_for_each_entry_safe(extension, next, &extension_list, list) {
+		list_del(&extension->list);
+		free(extension);
+	}
+	extension_num = extension_board_scan(&extension_list);
+
+	if (extension_num < 0)
+		return CMD_RET_FAILURE;
+
+	printf("Found %d extension board(s).\n", extension_num);
+
+	return CMD_RET_SUCCESS;
+}
+
+static int do_extension_apply(struct cmd_tbl *cmdtp, int flag,
+			      int argc, char *const argv[])
+{
+	struct extension *extension = NULL;
+	struct list_head *entry;
+	int i = 0, extension_id, ret;
+
+	if (argc < 2)
+		return CMD_RET_USAGE;
+
+	if (strcmp(argv[1], "all") == 0) {
+		list_for_each_entry(extension, &extension_list, list) {
+			ret = extension_apply(extension);
+			if (ret != CMD_RET_SUCCESS)
+				break;
+		}
+	} else {
+		extension_id = simple_strtol(argv[1], NULL, 10);
+		list_for_each(entry, &extension_list) {
+			if (i == extension_id) {
+				extension = list_entry(entry, struct extension,  list);
+				break;
+			}
+			i++;
+		}
+
+		if (!extension) {
+			printf("Wrong extension number\n");
+			return CMD_RET_FAILURE;
+		}
+
+		ret = extension_apply(extension);
+	}
+
+	return ret;
+}
+
+static struct cmd_tbl cmd_extension[] = {
+	U_BOOT_CMD_MKENT(scan, 1, 1, do_extension_scan, "", ""),
+	U_BOOT_CMD_MKENT(list, 1, 0, do_extension_list, "", ""),
+	U_BOOT_CMD_MKENT(apply, 2, 0, do_extension_apply, "", ""),
+};
+
+static int do_extensionops(struct cmd_tbl *cmdtp, int flag, int argc,
+			   char *const argv[])
+{
+	struct cmd_tbl *cp;
+
+	/* Drop the extension command */
+	argc--;
+	argv++;
+
+	cp = find_cmd_tbl(argv[0], cmd_extension, ARRAY_SIZE(cmd_extension));
+	if (cp)
+		return cp->cmd(cmdtp, flag, argc, argv);
+
+	return CMD_RET_USAGE;
+}
+
+U_BOOT_CMD(extension, 3, 1, do_extensionops,
+	"Extension board management sub system",
+	"scan - scan plugged extension(s) board(s)\n"
+	"extension list - lists available extension(s) board(s)\n"
+	"extension apply <extension number|all> - applies DT overlays corresponding to extension boards\n"
+);

cmd/fdt.c

@@ -27,7 +27,6 @@
  */
 DECLARE_GLOBAL_DATA_PTR;
 
-static int fdt_valid(struct fdt_header **blobp);
 static int fdt_parse_prop(char *const*newval, int count, char *data, int *len);
 static int fdt_print(const char *pathp, char *prop, int depth);
 static int is_printable_string(const void *data, int len);
@@ -732,54 +731,6 @@ static int do_fdt(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 
 /****************************************************************************/
 
-/**
- * fdt_valid() - Check if an FDT is valid. If not, change it to NULL
- *
- * @blobp: Pointer to FDT pointer
- * @return 1 if OK, 0 if bad (in which case *blobp is set to NULL)
- */
-static int fdt_valid(struct fdt_header **blobp)
-{
-	const void *blob = *blobp;
-	int err;
-
-	if (blob == NULL) {
-		printf ("The address of the fdt is invalid (NULL).\n");
-		return 0;
-	}
-
-	err = fdt_check_header(blob);
-	if (err == 0)
-		return 1;	/* valid */
-
-	if (err < 0) {
-		printf("libfdt fdt_check_header(): %s", fdt_strerror(err));
-		/*
-		 * Be more informative on bad version.
-		 */
-		if (err == -FDT_ERR_BADVERSION) {
-			if (fdt_version(blob) <
-			    FDT_FIRST_SUPPORTED_VERSION) {
-				printf (" - too old, fdt %d < %d",
-					fdt_version(blob),
-					FDT_FIRST_SUPPORTED_VERSION);
-			}
-			if (fdt_last_comp_version(blob) >
-			    FDT_LAST_SUPPORTED_VERSION) {
-				printf (" - too new, fdt %d > %d",
-					fdt_version(blob),
-					FDT_LAST_SUPPORTED_VERSION);
-			}
-		}
-		printf("\n");
-		*blobp = NULL;
-		return 0;
-	}
-	return 1;
-}
-
-/****************************************************************************/
-
 /*
  * Parse the user's input, partially heuristic.  Valid formats:
  * <0x00112233 4 05>	- an array of cells.  Numbers follow standard

cmd/mmc.c

@@ -574,6 +574,7 @@ static int do_mmc_rescan(cmd_tbl_t *cmdtp, int flag,
 }
 
 extern volatile uint32_t DELAY_LANE;
+extern volatile int manual_set_delay ;
 static int do_mmc_set_delay_lane(cmd_tbl_t *cmdtp, int flag,
 	       int argc, char * const argv[])
 {
@@ -587,17 +588,22 @@ static int do_mmc_set_delay_lane(cmd_tbl_t *cmdtp, int flag,
 	mmc = find_mmc_device(curr_device);
 	if (!mmc) {
 		printf("no mmc device at slot %x\n", curr_device);
-		return CMD_RET_FAILURE;
+		goto RET_FAILURE;
 	}
-
+	manual_set_delay = 1;
 	if (0 != snps_mmc_init(mmc))
-		return CMD_RET_FAILURE;
+		goto RET_FAILURE;
 
 	mmc = init_mmc_device(curr_device, true);
 	if (!mmc)
-		return CMD_RET_FAILURE;
-
+		goto RET_FAILURE;
+	
+	manual_set_delay = 0;
 	return CMD_RET_SUCCESS;
+
+RET_FAILURE:
+	manual_set_delay = 0;
+	return CMD_RET_FAILURE;
 }
 
 static int do_mmc_turning(cmd_tbl_t *cmdtp, int flag,
@@ -605,6 +611,10 @@ static int do_mmc_turning(cmd_tbl_t *cmdtp, int flag,
 {
 	struct mmc *mmc;
 	int i = 0, n;
+	int stop_on_ok = 1;
+	if(argc > 1 && (!strncmp(argv[1],"cont",4))){
+		stop_on_ok = 0;
+	}
 	for(i = 0; i <= 128; i++) {
 		DELAY_LANE = i;
 		printf("set DELAY_LANE = %d\n", DELAY_LANE);
@@ -616,8 +626,10 @@ static int do_mmc_turning(cmd_tbl_t *cmdtp, int flag,
 			return CMD_RET_FAILURE;
 		}
 
+		manual_set_delay = 1;
 		if (0 != snps_mmc_init(mmc)) {
 			printf("Error: mmc init error!\n");
+			manual_set_delay = 0;
 			return CMD_RET_FAILURE;
 		}
 
@@ -628,18 +640,21 @@ static int do_mmc_turning(cmd_tbl_t *cmdtp, int flag,
 
 		if (mmc_getwp(mmc) == 1) {
 			printf("Error: card is write protected!\n");
+			manual_set_delay = 0;
 			return CMD_RET_FAILURE;
 		}
 
 		n = blk_dwrite(mmc_get_blk_desc(mmc), 0, 1, 0);
 		if (n == 1) {
 			printf("blocks written: %s\n", "OK" );
-			return CMD_RET_SUCCESS;
+			manual_set_delay = 0;
+			if(stop_on_ok)
+				return CMD_RET_SUCCESS;
 		} else {
 			printf("written: %s\n", "error");
 		}
 	}
-
+	manual_set_delay = 0;
 	if (i > 128) {
 		return CMD_RET_FAILURE;
 	}
@@ -1239,9 +1254,10 @@ U_BOOT_CMD(
 #endif
 	"mmc erase blk# cnt\n"
 	"mmc rescan\n"
-	"mmc set_delay # val\n"
-	"mmc turning\n"
-	"mmc memset addr # lenght\n"
+	"mmc set_delay # val - set clk out delay mannaul,reinit host and rescan dev\n"
+	"mmc turning [continue] - loop test for clk delay form 0 to 128, reinit host and rescan dev\n"
+	"             - without arg [continue] exit once init and write ok\n"
+	"mmc memset addr # length - set mem addr 0xff with length  '# length' \n"
 	"mmc part - lists available partition on current mmc device\n"
 	"mmc dev [dev] [part] - show or set current mmc device [partition]\n"
 	"mmc list - lists available devices\n"

cmd/pxe_utils.c

@@ -9,6 +9,8 @@
 #include <malloc.h>
 #include <mapmem.h>
 #include <lcd.h>
+#include <fdt_support.h>
+#include <linux/libfdt.h>
 #include <linux/string.h>
 #include <linux/ctype.h>
 #include <errno.h>
@@ -279,6 +281,9 @@ static void label_destroy(struct pxe_label *label)
 	if (label->fdtdir)
 		free(label->fdtdir);
 
+	if (label->fdtoverlays)
+		free(label->fdtoverlays);
+
 	free(label);
 }
 
@@ -326,6 +331,92 @@ static int label_localboot(struct pxe_label *label)
 	return run_command_list(localcmd, strlen(localcmd), 0);
 }
 
+/*
+ * Loads fdt overlays specified in 'fdtoverlays'.
+ */
+#ifdef CONFIG_OF_LIBFDT_OVERLAY
+static void label_boot_fdtoverlay(struct cmd_tbl *cmdtp, struct pxe_label *label)
+{
+	char *fdtoverlay = label->fdtoverlays;
+	struct fdt_header *working_fdt;
+	char *fdtoverlay_addr_env;
+	ulong fdtoverlay_addr;
+	ulong fdt_addr;
+	int err;
+
+	/* Get the main fdt and map it */
+	fdt_addr = simple_strtoul(env_get("fdt_addr_r"), NULL, 16);
+	working_fdt = map_sysmem(fdt_addr, 0);
+	err = fdt_check_header(working_fdt);
+	if (err)
+		return;
+
+	/* Get the specific overlay loading address */
+	fdtoverlay_addr_env = env_get("fdtoverlay_addr_r");
+	if (!fdtoverlay_addr_env) {
+		printf("Invalid fdtoverlay_addr_r for loading overlays\n");
+		return;
+	}
+
+	fdtoverlay_addr = simple_strtoul(fdtoverlay_addr_env, NULL, 16);
+
+	/* Cycle over the overlay files and apply them in order */
+	do {
+		struct fdt_header *blob;
+		char *overlayfile;
+		char *end;
+		int len;
+
+		/* Drop leading spaces */
+		while (*fdtoverlay == ' ')
+			++fdtoverlay;
+
+		/* Copy a single filename if multiple provided */
+		end = strstr(fdtoverlay, " ");
+		if (end) {
+			len = (int)(end - fdtoverlay);
+			overlayfile = malloc(len + 1);
+			strncpy(overlayfile, fdtoverlay, len);
+			overlayfile[len] = '\0';
+		} else
+			overlayfile = fdtoverlay;
+
+		if (!strlen(overlayfile))
+			goto skip_overlay;
+
+		/* Load overlay file */
+		err = get_relfile_envaddr(cmdtp, overlayfile,
+					  "fdtoverlay_addr_r");
+		if (err < 0) {
+			printf("Failed loading overlay %s\n", overlayfile);
+			goto skip_overlay;
+		}
+
+		/* Resize main fdt */
+		fdt_shrink_to_minimum(working_fdt, 8192);
+
+		blob = map_sysmem(fdtoverlay_addr, 0);
+		err = fdt_check_header(blob);
+		if (err) {
+			printf("Invalid overlay %s, skipping\n",
+			       overlayfile);
+			goto skip_overlay;
+		}
+
+		err = fdt_overlay_apply_verbose(working_fdt, blob);
+		if (err) {
+			printf("Failed to apply overlay %s, skipping\n",
+			       overlayfile);
+			goto skip_overlay;
+		}
+
+skip_overlay:
+		if (end)
+			free(overlayfile);
+	} while ((fdtoverlay = strstr(fdtoverlay, " ")));
+}
+#endif
+
 /*
  * Boot according to the contents of a pxe_label.
  *
@@ -520,6 +611,11 @@ static int label_boot(cmd_tbl_t *cmdtp, struct pxe_label *label)
 				       label->name);
 				goto cleanup;
 			}
+
+#ifdef CONFIG_OF_LIBFDT_OVERLAY
+			if (label->fdtoverlays)
+				label_boot_fdtoverlay(cmdtp, label);
+#endif
 		} else {
 			bootm_argv[3] = NULL;
 		}
@@ -577,6 +673,7 @@ enum token_type {
 	T_INCLUDE,
 	T_FDT,
 	T_FDTDIR,
+	T_FDTOVERLAYS,
 	T_ONTIMEOUT,
 	T_IPAPPEND,
 	T_BACKGROUND,
@@ -611,6 +708,7 @@ static const struct token keywords[] = {
 	{"fdt", T_FDT},
 	{"devicetreedir", T_FDTDIR},
 	{"fdtdir", T_FDTDIR},
+	{"fdtoverlays", T_FDTOVERLAYS},
 	{"ontimeout", T_ONTIMEOUT,},
 	{"ipappend", T_IPAPPEND,},
 	{"background", T_BACKGROUND,},
@@ -1043,6 +1141,11 @@ static int parse_label(char **c, struct pxe_menu *cfg)
 				err = parse_sliteral(c, &label->fdtdir);
 			break;
 
+		case T_FDTOVERLAYS:
+			if (!label->fdtoverlays)
+				err = parse_sliteral(c, &label->fdtoverlays);
+			break;
+
 		case T_LOCALBOOT:
 			label->localboot = 1;
 			err = parse_integer(c, &label->localboot_val);

cmd/pxe_utils.h

@@ -43,6 +43,7 @@ struct pxe_label {
 	char *initrd;
 	char *fdt;
 	char *fdtdir;
+	char *fdtoverlays;
 	int ipappend;
 	int attempted;
 	int localboot;

common/Kconfig

@@ -962,6 +962,20 @@ config TPL_HASH
 	  and the algorithms it supports are defined in common/hash.c. See
 	  also CMD_HASH for command-line access.
 
+config BOARD_RNG_SEED
+        bool "Provide /chosen/rng-seed property to the linux kernel"
+        help
+          Selecting this option requires the board to define a
+          board_rng_seed() function, which should return a buffer
+          which will be used to populate the /chosen/rng-seed property
+          in the device tree for the OS being booted.
+
+          It is up to the board code (and more generally the whole
+          BSP) where and how to store (or generate) such a seed, how
+          to ensure a given seed is only used once, how to create a
+          new seed for use on subsequent boots, and whether or not the
+          kernel should account any entropy from the given seed.
+
 endmenu
 
 menu "Update support"

common/avb_verify.c

@@ -14,6 +14,48 @@
 #include <tee.h>
 #include <tee/optee_ta_avb.h>
 
+#ifdef CONFIG_AVB_ROLLBACK_ENABLE
+extern int sec_write_rollback_index(size_t rollback_index_slot, uint64_t rollback_index);
+extern int sec_read_rollback_index(size_t rollback_index_slot, uint64_t *out_rollback_index);
+#endif
+
+#if defined (CONFIG_AVB_USE_OEM_KEY)
+static const unsigned char avb_root_oem_pub[520] = {
+	0x00,0x00,0x08,0x00,0x11,0x70,0xEA,0xC9,0xC2,0xAD,0x66,0x2A,0x57,0x2A,0x89,0x68,
+	0x8B,0x40,0x33,0xF2,0xEA,0x22,0xD7,0x3E,0x31,0x5F,0x9D,0xB8,0xD1,0x16,0x5C,0x22,
+	0xC3,0xFE,0xE6,0x35,0x3F,0x96,0x6D,0xD8,0x1A,0x11,0xE9,0x53,0x90,0x88,0xA9,0xCE,
+	0xA7,0x33,0xB2,0x16,0x60,0x18,0xBE,0x23,0xCC,0x5C,0xAB,0x29,0x0E,0x7B,0x35,0x16,
+	0xB0,0x59,0x3A,0x2F,0x62,0xF1,0x9B,0x39,0x0A,0x21,0x00,0xFE,0x75,0xEB,0x00,0xDF,
+	0x17,0xAF,0x44,0x11,0x42,0x4E,0x4C,0x7C,0xA6,0xDC,0xC5,0xAD,0xB3,0x7C,0xC3,0xB1,
+	0x52,0xAD,0x0C,0xEF,0x73,0x69,0x7E,0xFC,0xF9,0x12,0xA7,0x5C,0x60,0x47,0xEF,0x8F,
+	0xC7,0x9D,0xD9,0x62,0xF5,0x0E,0x62,0xBB,0x3E,0x80,0x23,0xFA,0x19,0x4C,0x0A,0xD6,
+	0xE0,0xA7,0x0E,0x65,0xEA,0xD5,0xB8,0xA9,0xF2,0xA3,0xDA,0x18,0xBE,0x5D,0x4B,0x37,
+	0x91,0xBA,0xDB,0x0D,0x50,0x7E,0xEE,0x52,0xDF,0x90,0xE6,0xFC,0x8F,0xB8,0x24,0x2A,
+	0x2B,0xBE,0xA6,0xC9,0x5B,0x89,0x3E,0xE8,0x24,0xBD,0x6A,0x03,0x31,0x6C,0xFC,0x4A,
+	0xBA,0x6B,0xEE,0x08,0xAE,0x33,0x6E,0xC0,0x64,0x87,0xC1,0x35,0x65,0x42,0x34,0xE5,
+	0xF8,0x3B,0x82,0x36,0xE9,0xFA,0x23,0xD7,0x12,0xC5,0x7B,0x27,0x16,0xB0,0xC7,0x40,
+	0x5A,0xA4,0x8A,0x56,0xA4,0x54,0x0F,0xD9,0xA7,0x25,0x25,0xE3,0x7F,0x72,0x6E,0x4B,
+	0x63,0x1B,0x05,0xFE,0x4E,0x1F,0x1D,0x05,0xDD,0x91,0xA7,0xBF,0xA4,0x90,0xDA,0x7D,
+	0x0F,0xB6,0xFC,0x5D,0x8E,0xFB,0xE2,0xF7,0x5F,0x76,0xFA,0xD5,0x12,0xEC,0x87,0xD6,
+	0x07,0xA0,0xAC,0xB6,0xE6,0xBA,0xB0,0x87,0xBA,0x51,0xD7,0x6C,0x19,0xC0,0x2C,0xA5,
+	0x2C,0x08,0x52,0x2A,0x63,0x18,0x10,0x94,0xEA,0x5C,0x13,0xBF,0x42,0x8E,0x12,0xB6,
+	0x7D,0x34,0xD9,0x1C,0x42,0xBC,0xCE,0x44,0x8A,0x13,0x5B,0x93,0x6F,0x34,0x41,0xA1,
+	0xA3,0xD3,0x2E,0xF4,0xD3,0x28,0xAD,0x8F,0x8B,0x89,0x9D,0x42,0x43,0xD6,0xBF,0xDE,
+	0x9F,0xBD,0x32,0x06,0xE3,0x67,0xD3,0x14,0x2F,0x4C,0xE7,0x6B,0x9A,0xD9,0x04,0xFA,
+	0x4B,0x46,0x88,0xE7,0x04,0xAA,0x56,0xFF,0xBF,0x89,0x1D,0xFD,0x32,0xDF,0x47,0xC0,
+	0x34,0x0D,0x25,0x8C,0xF6,0xE1,0x5E,0xA9,0x3C,0x30,0x3A,0x53,0x0C,0xDB,0xAD,0x8E,
+	0x01,0xCB,0x46,0xE0,0xF5,0x97,0x2D,0xB8,0xF8,0x29,0xC3,0x19,0x4C,0x05,0x8B,0x74,
+	0xE0,0xA6,0x3B,0x3C,0x96,0x4F,0x91,0x74,0x62,0xAA,0x50,0x0F,0x11,0x30,0x59,0xAE,
+	0x7A,0x80,0xD3,0xAC,0xB3,0xDB,0x24,0x3A,0x79,0xD4,0xDB,0x79,0x10,0x63,0x27,0xD0,
+	0x6B,0xF9,0xA3,0xF4,0x27,0x24,0x89,0x0C,0xAC,0x31,0x15,0x08,0x10,0x59,0x08,0x2D,
+	0x00,0x3D,0xD8,0xD6,0x3B,0x91,0xC8,0x55,0xCF,0x28,0x3A,0xFB,0xD7,0xF7,0xF7,0x9D,
+	0x41,0xBD,0x3E,0xD1,0x77,0xA3,0xF6,0xFA,0x33,0x05,0x5A,0x36,0xCE,0xB9,0x02,0x12,
+	0x10,0xEB,0xCA,0xA7,0x3C,0xC8,0x5D,0xCD,0x33,0xD9,0xFA,0x16,0xD4,0x52,0x12,0xB6,
+	0x35,0xD5,0x84,0x53,0xC4,0x21,0xDC,0x72,0x2F,0xF9,0x1E,0x59,0x0A,0xCD,0x7D,0x89,
+	0xD4,0xCF,0x8E,0x2E,0x09,0x36,0xF5,0x12,0x35,0x43,0x64,0x6C,0xD1,0x70,0xBF,0x67,
+	0x3A,0x54,0x72,0x84,0xF3,0xF1,0x4A,0x6A
+};
+#else
 static const unsigned char avb_root_pub[1032] = {
 	0x0, 0x0, 0x10, 0x0, 0x55, 0xd9, 0x4, 0xad, 0xd8, 0x4,
 	0xaf, 0xe3, 0xd3, 0x84, 0x6c, 0x7e, 0xd, 0x89, 0x3d, 0xc2,
@@ -120,7 +162,7 @@ static const unsigned char avb_root_pub[1032] = {
 	0xe1, 0x74, 0xa1, 0xa3, 0x99, 0xa0, 0x85, 0x9e, 0xf1, 0xac,
 	0xd8, 0x7e,
 };
-
+#endif
 /**
  * ============================================================================
  * Boot states support (GREEN, YELLOW, ORANGE, RED) and dm_verity
@@ -590,6 +632,19 @@ static AvbIOResult validate_vbmeta_public_key(AvbOps *ops,
 					      public_key_metadata_length,
 					      bool *out_key_is_trusted)
 {
+#if defined (CONFIG_AVB_USE_OEM_KEY)
+	if (!public_key_length || !public_key_data || !out_key_is_trusted)
+		return AVB_IO_RESULT_ERROR_IO;
+
+	*out_key_is_trusted = false;
+	if (public_key_length != sizeof(avb_root_oem_pub))
+		return AVB_IO_RESULT_ERROR_IO;
+
+	if (memcmp(avb_root_oem_pub, public_key_data, public_key_length) == 0)
+		*out_key_is_trusted = true;
+	
+	return AVB_IO_RESULT_OK;
+#else
 	if (!public_key_length || !public_key_data || !out_key_is_trusted)
 		return AVB_IO_RESULT_ERROR_IO;
 
@@ -601,6 +656,7 @@ static AvbIOResult validate_vbmeta_public_key(AvbOps *ops,
 		*out_key_is_trusted = true;
 
 	return AVB_IO_RESULT_OK;
+#endif
 }
 
 #ifdef CONFIG_OPTEE_TA_AVB
@@ -681,8 +737,15 @@ static AvbIOResult read_rollback_index(AvbOps *ops,
 				       size_t rollback_index_slot,
 				       u64 *out_rollback_index)
 {
+#ifdef CONFIG_AVB_ROLLBACK_ENABLE
+    if (sec_read_rollback_index(rollback_index_slot, out_rollback_index) != 0) {
+        return AVB_IO_RESULT_ERROR_IO;
+    }
+
+	return AVB_IO_RESULT_OK;
+#else
 #ifndef CONFIG_OPTEE_TA_AVB
-	/* For now we always return 0 as the stored rollback index. */
+    /* For now we always return 0 as the stored rollback index. */
 	printf("%s not supported yet\n", __func__);
 
 	if (out_rollback_index)
@@ -708,8 +771,10 @@ static AvbIOResult read_rollback_index(AvbOps *ops,
 
 	*out_rollback_index = (u64)param[1].u.value.a << 32 |
 			      (u32)param[1].u.value.b;
+
 	return AVB_IO_RESULT_OK;
 #endif
+#endif
 }
 
 /**
@@ -727,6 +792,13 @@ static AvbIOResult write_rollback_index(AvbOps *ops,
 					size_t rollback_index_slot,
 					u64 rollback_index)
 {
+#ifdef CONFIG_AVB_ROLLBACK_ENABLE
+    if (sec_write_rollback_index(rollback_index_slot, rollback_index) != 0) {
+        return AVB_IO_RESULT_ERROR_IO;
+    }
+    
+	return AVB_IO_RESULT_OK;
+#else
 #ifndef CONFIG_OPTEE_TA_AVB
 	/* For now this is a no-op. */
 	printf("%s not supported yet\n", __func__);
@@ -748,6 +820,7 @@ static AvbIOResult write_rollback_index(AvbOps *ops,
 	return invoke_func(ops->user_data, TA_AVB_CMD_WRITE_ROLLBACK_INDEX,
 			   ARRAY_SIZE(param), param);
 #endif
+#endif
 }
 
 /**

common/fdt_support.c

@@ -7,6 +7,7 @@
  */
 
 #include <common.h>
+#include <abuf.h>
 #include <env.h>
 #include <mapmem.h>
 #include <stdio_dev.h>
@@ -274,6 +275,7 @@ int fdt_initrd(void *fdt, ulong initrd_start, ulong initrd_end)
 
 int fdt_chosen(void *fdt)
 {
+        struct abuf buf = {};
 	int   nodeoffset;
 	int   err;
 	char  *str;		/* used to set string properties */
@@ -289,6 +291,17 @@ int fdt_chosen(void *fdt)
 	if (nodeoffset < 0)
 		return nodeoffset;
 
+        if (IS_ENABLED(CONFIG_BOARD_RNG_SEED) && !board_rng_seed(&buf)) {
+                err = fdt_setprop(fdt, nodeoffset, "rng-seed",
+                                  abuf_data(&buf), abuf_size(&buf));
+                abuf_uninit(&buf);
+                if (err < 0) {
+                        printf("WARNING: could not set rng-seed %s.\n",
+                               fdt_strerror(err));
+                        return err;
+                }
+        }
+
 	str = env_get("bootargs");
 	if (str) {
 		err = fdt_setprop(fdt, nodeoffset, "bootargs", str,
@@ -1809,3 +1822,49 @@ int fdt_overlay_apply_verbose(void *fdt, void *fdto)
 	return err;
 }
 #endif
+
+/**
+ * fdt_valid() - Check if an FDT is valid. If not, change it to NULL
+ *
+ * @blobp: Pointer to FDT pointer
+ * @return 1 if OK, 0 if bad (in which case *blobp is set to NULL)
+ */
+int fdt_valid(struct fdt_header **blobp)
+{
+	const void *blob = *blobp;
+	int err;
+
+	if (!blob) {
+		printf("The address of the fdt is invalid (NULL).\n");
+		return 0;
+	}
+
+	err = fdt_check_header(blob);
+	if (err == 0)
+		return 1;	/* valid */
+
+	if (err < 0) {
+		printf("libfdt fdt_check_header(): %s", fdt_strerror(err));
+		/*
+		 * Be more informative on bad version.
+		 */
+		if (err == -FDT_ERR_BADVERSION) {
+			if (fdt_version(blob) <
+			    FDT_FIRST_SUPPORTED_VERSION) {
+				printf(" - too old, fdt %d < %d",
+				       fdt_version(blob),
+				       FDT_FIRST_SUPPORTED_VERSION);
+			}
+			if (fdt_last_comp_version(blob) >
+			    FDT_LAST_SUPPORTED_VERSION) {
+				printf(" - too new, fdt %d > %d",
+				       fdt_version(blob),
+				       FDT_LAST_SUPPORTED_VERSION);
+			}
+		}
+		printf("\n");
+		*blobp = NULL;
+		return 0;
+	}
+	return 1;
+}

common/spl/spl.c

@@ -735,6 +735,30 @@ void board_init_r(gd_t *dummy1, ulong dummy2)
 	jump_to_image_no_args(&spl_image);
 }
 
+static void print_ruyisdk_logo(void)
+{
+	//  _____             _  _____ _____  _  __
+	// |  __ \           (_)/ ____|  __ \| |/ /
+	// | |__) |   _ _   _ _| (___ | |  | | ' / 
+	// |  _  / | | | | | | |\___ \| |  | |  <  
+	// | | \ \ |_| | |_| | |____) | |__| | . \ 
+	// |_|  \_\__,_|\__, |_|_____/|_____/|_|\_\
+	//               __/ |                     
+	//              |___/                      
+
+	printf("-----------------------------------------\n");
+	printf("  _____             _  _____ _____  _  __\n");
+	printf(" |  __ \\           (_)/ ____|  __ \\| |/ /\n");
+	printf(" | |__) |   _ _   _ _| (___ | |  | | ' / \n");
+	printf(" |  _  / | | | | | | |\\___ \\| |  | |  <  \n");
+	printf(" | | \\ \\ |_| | |_| | |____) | |__| | . \\ \n");
+	printf(" |_|  \\_\\__,_|\\__, |_|_____/|_____/|_|\\_\\\n");
+	printf("               __/ |                     \n");
+	printf("              |___/                      \n");
+	printf("                    -- Presented by ISCAS\n");
+	printf("-----------------------------------------\n");
+}
+
 #ifdef CONFIG_SPL_SERIAL_SUPPORT
 /*
  * This requires UART clocks to be enabled.  In order for this to work the
@@ -748,6 +772,8 @@ void preloader_console_init(void)
 
 	gd->have_console = 1;
 
+	print_ruyisdk_logo();
+
 #if CONFIG_IS_ENABLED(BANNER_PRINT)
 	puts("\nU-Boot " SPL_TPL_NAME " " PLAIN_VERSION " (" U_BOOT_DATE " - "
 	     U_BOOT_TIME " " U_BOOT_TZ ")\n");

common/splash.c

@@ -71,7 +71,7 @@ static int splash_video_logo_load(void)
 		return -EFAULT;
 	}
 
-	memcpy((void *)bmp_load_addr, bmp_logo_bitmap,
+	memcpy((void *)(u64)bmp_load_addr, bmp_logo_bitmap,
 	       ARRAY_SIZE(bmp_logo_bitmap));
 
 	return 0;

config.mk

@@ -63,6 +63,11 @@ ifdef FTRACE
 PLATFORM_CPPFLAGS += -finstrument-functions -DFTRACE
 endif
 
+ifeq ($(BUILD_TYPE),RELEASE)
+PLATFORM_CPPFLAGS += -DU_BUILD_RELEASE
+else # default build debug 
+PLATFORM_CPPFLAGS += -DU_BUILD_DEBUG
+endif
 #########################################################################
 
 RELFLAGS := $(PLATFORM_RELFLAGS)

configs/light_a_ref_defconfig

@@ -0,0 +1,103 @@
+CONFIG_RISCV=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_ENV_SIZE=0x20000
+CONFIG_ENV_OFFSET=0xe0000
+CONFIG_NR_DRAM_BANKS=8
+CONFIG_SPL=y
+CONFIG_SMP=y
+CONFIG_TARGET_LIGHT_C910=y
+CONFIG_TARGET_LIGHT_FM_C910_A_REF=y
+CONFIG_ARCH_RV64I=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_BUILD_TARGET="u-boot-with-spl.bin"
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_DISPLAY_BOARDINFO=y
+# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
+CONFIG_SPL_RAM_SUPPORT=y
+CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SYS_PROMPT="C910 Light# "
+CONFIG_DDR_LP4X_3733_SINGLERANK=y
+# CONFIG_DDR_LP4_3733_DUALRANK is not set
+CONFIG_DDR_BOARD_CONFIG=y
+CONFIG_CMD_BOOT_SLAVE=y
+CONFIG_CMD_ERASEENV=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_DDR_SCAN=y
+CONFIG_DDR_PRBS_TEST=n
+# CONFIG_DOS_PARTITION is not set
+# CONFIG_ISO_PARTITION is not set
+CONFIG_PARTITION_TYPE_GUID=y
+CONFIG_OF_EMBED=y
+CONFIG_DEFAULT_DEVICE_TREE="light-a-ref"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SPL_CLK=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_UDP_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x10000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_DW=y
+CONFIG_DWAPB_GPIO=y
+# CONFIG_MMC_SPI is not set
+CONFIG_MMC_VERBOSE=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_SNPS=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SNPS=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MMC_RPMB=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_SPI_NAND=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_PHY_REALTEK=y
+CONFIG_RTL8211E_PINE64_GIGABIT_FIX=y
+CONFIG_RTL8211X_PHY_FORCE_MASTER=y
+CONFIG_RTL8211F_PHY_FORCE_EEE_RXC_ON=y
+CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_DESIGNWARE_SPI=y
+CONFIG_DESIGNWARE_QSPI=y
+CONFIG_USB=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="U-Boot-THEAD"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1234
+CONFIG_USB_GADGET_PRODUCT_NUM=0x8888
+# CONFIG_SPL_USE_TINY_PRINTF is not set
+# CONFIG_EFI_LOADER is not set
+# CONFIG_LIGHT_SEC_BOOT is not set
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_DM_VIDEO=y
+CONFIG_PHY=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_CMD_BMP=y
+CONFIG_VIDEO_BRIDGE=y
+CONFIG_DM_PCA953X=y
+CONFIG_VIDEO_VS_DPU=y
+CONFIG_VIDEO_LCD_ILITEK_ILI9881C=y
+CONFIG_VIDEO_DW_DSI_LIGHT=y
+CONFIG_VIDEO_DW_DPHY=y
+CONFIG_VIDEO_DW_DSI_HOST=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_PMIC_VOL_INIT=y
+CONFIG_DDR_REGU_0V6=600000
+CONFIG_DDR_REGU_0V8=800000
+CONFIG_DDR_REGU_1V1=1100000

configs/light_a_val_android_defconfig

@@ -0,0 +1,117 @@
+CONFIG_RISCV=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_ENV_SIZE=0x20000
+CONFIG_ENV_OFFSET=0xe0000
+CONFIG_NR_DRAM_BANKS=8
+CONFIG_SPL=y
+CONFIG_SMP=y
+CONFIG_TARGET_LIGHT_C910=y
+CONFIG_ARCH_RV64I=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_BUILD_TARGET="u-boot-with-spl.bin"
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_DISPLAY_BOARDINFO=y
+# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
+CONFIG_SPL_RAM_SUPPORT=y
+CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SYS_PROMPT="C910 Light# "
+CONFIG_DDR_LP4X_3733_SINGLERANK=y
+# CONFIG_DDR_LP4_3733_DUALRANK is not set
+CONFIG_DDR_BOARD_CONFIG=y
+CONFIG_CMD_BOOT_SLAVE=y
+CONFIG_CMD_ERASEENV=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_DDR_SCAN=y
+CONFIG_DDR_PRBS_TEST=n
+# CONFIG_DOS_PARTITION is not set
+# CONFIG_ISO_PARTITION is not set
+CONFIG_PARTITION_TYPE_GUID=y
+CONFIG_OF_EMBED=y
+CONFIG_DEFAULT_DEVICE_TREE="light-a-val"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SPL_CLK=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_UDP_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x10000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_DW=y
+CONFIG_DWAPB_GPIO=y
+# CONFIG_MMC_SPI is not set
+CONFIG_MMC_VERBOSE=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_SNPS=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SNPS=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MMC_RPMB=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_SPI_NAND=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_PHY_REALTEK=y
+CONFIG_RTL8211E_PINE64_GIGABIT_FIX=y
+CONFIG_RTL8211X_PHY_FORCE_MASTER=y
+CONFIG_RTL8211F_PHY_FORCE_EEE_RXC_ON=y
+CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_DESIGNWARE_SPI=y
+CONFIG_DESIGNWARE_QSPI=y
+CONFIG_USB=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="U-Boot-THEAD"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1234
+CONFIG_USB_GADGET_PRODUCT_NUM=0x8888
+# CONFIG_SPL_USE_TINY_PRINTF is not set
+# CONFIG_EFI_LOADER is not set
+# CONFIG_LIGHT_SEC_BOOT_WITH_VERIFY_VAL_A=y
+# CONFIG_LIGHT_SEC_UPGRADE=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_DM_VIDEO=y
+CONFIG_PHY=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_CMD_BMP=y
+CONFIG_VIDEO_BRIDGE=y
+CONFIG_DM_PCA953X=y
+CONFIG_VIDEO_VS_DPU=y
+CONFIG_VIDEO_LCD_ILITEK_ILI9881C=y
+CONFIG_VIDEO_DW_DSI_LIGHT=y
+CONFIG_VIDEO_DW_DPHY=y
+CONFIG_VIDEO_DW_DSI_HOST=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_PMIC_VOL_INIT=y
+CONFIG_DDR_REGU_0V6=600000
+CONFIG_DDR_REGU_0V8=800000
+CONFIG_DDR_REGU_1V1=1100000
+CONFIG_SPL_TEXT_BASE=0xffe0000800
+CONFIG_LIGHT_ANDROID_BOOT_IMAGE_VAL_A=y
+CONFIG_AVB_USE_OEM_KEY=y
+# CONFIG_AVB_ROLLBACK_ENABLE is not set
+CONFIG_AVB_HW_ENGINE_ENABLE=y
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_LIBAVB=y
+CONFIG_AVB_VERIFY=y
+CONFIG_CMD_AVB=y
+CONFIG_CMD_BOOTANDROID=y
+CONFIG_ANDROID_AB=y
+CONFIG_CMD_AB_SELECT=y
+CONFIG_XBC=y
+CONFIG_BOARD_RNG_SEED=y

configs/light_a_val_defconfig

@@ -6,6 +6,10 @@ CONFIG_NR_DRAM_BANKS=8
 CONFIG_SPL=y
 CONFIG_SMP=y
 CONFIG_TARGET_LIGHT_C910=y
+CONFIG_TARGET_LIGHT_FM_C910_VAL_A=y
+# CONFIG_THEAD_PLIC is not set
+# CONFIG_THEAD_LIGHT_TIMER is not set
+# CONFIG_THEAD_LIGHT_DIGITAL_SENSOR is not set
 CONFIG_ARCH_RV64I=y
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_BUILD_TARGET="u-boot-with-spl.bin"
@@ -14,7 +18,7 @@ CONFIG_DISPLAY_BOARDINFO=y
 # CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
 CONFIG_SPL_RAM_SUPPORT=y
 CONFIG_SPL_RAM_DEVICE=y
-CONFIG_SYS_PROMPT="C910 Light# "
+CONFIG_SYS_PROMPT="Light VAL-A# "
 CONFIG_DDR_LP4X_3733_SINGLERANK=y
 # CONFIG_DDR_LP4_3733_DUALRANK is not set
 CONFIG_DDR_BOARD_CONFIG=y
@@ -59,6 +63,7 @@ CONFIG_MMC_SDHCI_SNPS=y
 CONFIG_MMC_SDHCI_SDMA=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_MMC_RPMB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
 CONFIG_SUPPORT_EMMC_RPMB=y
 CONFIG_DM_MTD=y
 CONFIG_MTD_SPI_NAND=y
@@ -78,9 +83,11 @@ CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_MANUFACTURER="U-Boot-THEAD"
 CONFIG_USB_GADGET_VENDOR_NUM=0x1234
 CONFIG_USB_GADGET_PRODUCT_NUM=0x8888
+CONFIG_USB_FUNCTION_MASS_STORAGE=y
 # CONFIG_SPL_USE_TINY_PRINTF is not set
 # CONFIG_EFI_LOADER is not set
 # CONFIG_LIGHT_SEC_BOOT is not set
+CONFIG_DEFAULT_FDT_FILE="light-a-val.dtb"
 CONFIG_BOARD_LATE_INIT=y
 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
 CONFIG_DM_VIDEO=y
@@ -100,3 +107,4 @@ CONFIG_PMIC_VOL_INIT=y
 CONFIG_DDR_REGU_0V6=600000
 CONFIG_DDR_REGU_0V8=800000
 CONFIG_DDR_REGU_1V1=1100000
+CONFIG_BOARD_RNG_SEED=y

configs/light_a_val_sec_defconfig

@@ -18,6 +18,12 @@ CONFIG_SYS_PROMPT="C910 Light# "
 CONFIG_DDR_LP4X_3733_SINGLERANK=y
 # CONFIG_DDR_LP4_3733_DUALRANK is not set
 CONFIG_DDR_BOARD_CONFIG=y
+# CONFIG_TPM is not set
+# CONFIG_TPM_Z32H330TC_SPI is not set
+# CONFIG_TPM_V2 is not set
+# CONFIG_CMD_TPM_V2 is not set
+# CONFIG_CMD_TPM is not set
+# CONFIG_CMD_TPM_TEST is not set
 CONFIG_CMD_BOOT_SLAVE=y
 CONFIG_CMD_ERASEENV=y
 CONFIG_CMD_GPT=y
@@ -82,6 +88,7 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0x8888
 # CONFIG_EFI_LOADER is not set
 CONFIG_LIGHT_SEC_BOOT_WITH_VERIFY_VAL_A=y
 CONFIG_LIGHT_SEC_UPGRADE=y
+# CONFIG_LIGHT_BOOT_FORCE_SEQ is not set
 CONFIG_BOARD_LATE_INIT=y
 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
 CONFIG_DM_VIDEO=y

configs/light_ant_discrete_defconfig

@@ -34,7 +34,7 @@ CONFIG_DDR_PRBS_TEST=n
 # CONFIG_ISO_PARTITION is not set
 CONFIG_PARTITION_TYPE_GUID=y
 CONFIG_OF_EMBED=y
-CONFIG_DEFAULT_DEVICE_TREE="light-ant-evt"
+CONFIG_DEFAULT_DEVICE_TREE="light-ant-ref"
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_SPL_CLK=y

configs/light_ant_ref_android_defconfig

@@ -0,0 +1,119 @@
+CONFIG_RISCV=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_ENV_SIZE=0x20000
+CONFIG_ENV_OFFSET=0xe0000
+CONFIG_NR_DRAM_BANKS=8
+CONFIG_SPL=y
+CONFIG_SMP=y
+CONFIG_TARGET_LIGHT_C910=y
+CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_REF=y
+CONFIG_ARCH_RV64I=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_BUILD_TARGET="u-boot-with-spl.bin"
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_DISPLAY_BOARDINFO=y
+# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
+CONFIG_SPL_RAM_SUPPORT=y
+CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SYS_PROMPT="C910 Light# "
+CONFIG_DDR_LP4X_3200_SINGLERANK=y
+CONFIG_DDR_H32_MODE=y
+# CONFIG_DDR_LP4_3733_DUALRANK is not set
+CONFIG_DDR_BOARD_CONFIG=y
+CONFIG_CMD_BOOT_SLAVE=y
+CONFIG_CMD_ERASEENV=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_DDR_SCAN=y
+CONFIG_DDR_PRBS_TEST=n
+# CONFIG_DOS_PARTITION is not set
+# CONFIG_ISO_PARTITION is not set
+CONFIG_PARTITION_TYPE_GUID=y
+CONFIG_OF_EMBED=y
+CONFIG_DEFAULT_DEVICE_TREE="light-ant-ref"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SPL_CLK=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_UDP_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x10000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_DW=y
+CONFIG_DWAPB_GPIO=y
+# CONFIG_MMC_SPI is not set
+CONFIG_MMC_VERBOSE=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_SNPS=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SNPS=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MMC_RPMB=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_SPI_NAND=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_PHY_REALTEK=y
+CONFIG_RTL8211E_PINE64_GIGABIT_FIX=y
+CONFIG_RTL8211X_PHY_FORCE_MASTER=y
+CONFIG_RTL8211F_PHY_FORCE_EEE_RXC_ON=y
+CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_DESIGNWARE_SPI=y
+CONFIG_DESIGNWARE_QSPI=y
+CONFIG_USB=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="U-Boot-THEAD"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1234
+CONFIG_USB_GADGET_PRODUCT_NUM=0x8888
+# CONFIG_SPL_USE_TINY_PRINTF is not set
+# CONFIG_EFI_LOADER is not set
+# CONFIG_LIGHT_SEC_UPGRADE is not set
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_DM_VIDEO=y
+CONFIG_PHY=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_CMD_BMP=y
+CONFIG_VIDEO_BRIDGE=y
+CONFIG_DM_PCA953X=y
+CONFIG_VIDEO_VS_DPU=y
+CONFIG_VIDEO_LCD_ILITEK_ILI9881C=y
+CONFIG_VIDEO_DW_DSI_LIGHT=y
+CONFIG_VIDEO_DW_DPHY=y
+CONFIG_VIDEO_DW_DSI_HOST=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_SYS_TEXT_BASE=0x7b000000
+CONFIG_PMIC_VOL_INIT=y
+CONFIG_DDR_REGU_0V6=600000
+CONFIG_DDR_REGU_0V8=800000
+CONFIG_DDR_REGU_1V1=1100000
+CONFIG_SPL_TEXT_BASE=0xffe0000800
+CONFIG_LIGHT_ANDROID_BOOT_IMAGE_ANT_REF=y
+CONFIG_AVB_USE_OEM_KEY=y
+# CONFIG_AVB_ROLLBACK_ENABLE is not set
+CONFIG_AVB_HW_ENGINE_ENABLE=y
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_LIBAVB=y
+CONFIG_AVB_VERIFY=y
+CONFIG_CMD_AVB=y
+CONFIG_CMD_BOOTANDROID=y
+CONFIG_ANDROID_AB=y
+CONFIG_CMD_AB_SELECT=y
+CONFIG_XBC=y
+CONFIG_BOARD_RNG_SEED=y

configs/light_ant_ref_defconfig

@@ -6,7 +6,7 @@ CONFIG_NR_DRAM_BANKS=8
 CONFIG_SPL=y
 CONFIG_SMP=y
 CONFIG_TARGET_LIGHT_C910=y
-CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_EVT=y
+CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_REF=y
 CONFIG_ARCH_RV64I=y
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_BUILD_TARGET="u-boot-with-spl.bin"
@@ -34,7 +34,7 @@ CONFIG_DDR_PRBS_TEST=n
 # CONFIG_ISO_PARTITION is not set
 CONFIG_PARTITION_TYPE_GUID=y
 CONFIG_OF_EMBED=y
-CONFIG_DEFAULT_DEVICE_TREE="light-ant-evt"
+CONFIG_DEFAULT_DEVICE_TREE="light-ant-ref"
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_SPL_CLK=y
@@ -82,7 +82,7 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x1234
 CONFIG_USB_GADGET_PRODUCT_NUM=0x8888
 # CONFIG_SPL_USE_TINY_PRINTF is not set
 # CONFIG_EFI_LOADER is not set
-CONFIG_LIGHT_SEC_BOOT_WITH_VERIFY_ANT_EVT=y
+CONFIG_LIGHT_SEC_BOOT_WITH_VERIFY_ANT_REF=y
 CONFIG_LIGHT_SEC_UPGRADE=y
 CONFIG_BOARD_LATE_INIT=y
 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y

configs/light_ant_ref_sec_defconfig

@@ -0,0 +1,106 @@
+CONFIG_RISCV=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_ENV_SIZE=0x20000
+CONFIG_ENV_OFFSET=0xe0000
+CONFIG_NR_DRAM_BANKS=8
+CONFIG_SPL=y
+CONFIG_SMP=y
+CONFIG_TARGET_LIGHT_C910=y
+CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_REF=y
+CONFIG_ARCH_RV64I=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_BUILD_TARGET="u-boot-with-spl.bin"
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_DISPLAY_BOARDINFO=y
+# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
+CONFIG_SPL_RAM_SUPPORT=y
+CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SYS_PROMPT="C910 Light# "
+CONFIG_DDR_LP4X_3200_SINGLERANK=y
+CONFIG_DDR_H32_MODE=y
+# CONFIG_DDR_LP4_3733_DUALRANK is not set
+CONFIG_DDR_BOARD_CONFIG=y
+CONFIG_CMD_BOOT_SLAVE=y
+CONFIG_CMD_ERASEENV=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_DDR_SCAN=y
+CONFIG_DDR_PRBS_TEST=n
+# CONFIG_DOS_PARTITION is not set
+# CONFIG_ISO_PARTITION is not set
+CONFIG_PARTITION_TYPE_GUID=y
+CONFIG_OF_EMBED=y
+CONFIG_DEFAULT_DEVICE_TREE="light-ant-ref"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SPL_CLK=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_UDP_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x10000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_DW=y
+CONFIG_DWAPB_GPIO=y
+# CONFIG_MMC_SPI is not set
+CONFIG_MMC_VERBOSE=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_SNPS=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SNPS=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MMC_RPMB=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_SPI_NAND=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_PHY_REALTEK=y
+CONFIG_RTL8211E_PINE64_GIGABIT_FIX=y
+CONFIG_RTL8211X_PHY_FORCE_MASTER=y
+CONFIG_RTL8211F_PHY_FORCE_EEE_RXC_ON=y
+CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_DESIGNWARE_SPI=y
+CONFIG_DESIGNWARE_QSPI=y
+CONFIG_USB=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="U-Boot-THEAD"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1234
+CONFIG_USB_GADGET_PRODUCT_NUM=0x8888
+# CONFIG_SPL_USE_TINY_PRINTF is not set
+# CONFIG_EFI_LOADER is not set
+CONFIG_LIGHT_SEC_BOOT_WITH_VERIFY_ANT_REF=y
+CONFIG_LIGHT_SEC_UPGRADE=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_DM_VIDEO=y
+CONFIG_PHY=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_CMD_BMP=y
+CONFIG_VIDEO_BRIDGE=y
+CONFIG_DM_PCA953X=y
+CONFIG_VIDEO_VS_DPU=y
+CONFIG_VIDEO_LCD_ILITEK_ILI9881C=y
+CONFIG_VIDEO_DW_DSI_LIGHT=y
+CONFIG_VIDEO_DW_DPHY=y
+CONFIG_VIDEO_DW_DSI_HOST=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_SYS_TEXT_BASE=0x7b000000
+CONFIG_PMIC_VOL_INIT=y
+CONFIG_DDR_REGU_0V6=600000
+CONFIG_DDR_REGU_0V8=800000
+CONFIG_DDR_REGU_1V1=1100000

configs/light_b_power_defconfig

@@ -0,0 +1,106 @@
+CONFIG_RISCV=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_ENV_SIZE=0x20000
+CONFIG_ENV_OFFSET=0xe0000
+CONFIG_NR_DRAM_BANKS=8
+CONFIG_SPL=y
+CONFIG_SMP=y
+CONFIG_TARGET_LIGHT_C910=y
+CONFIG_TARGET_LIGHT_FM_C910_B_POWER=y
+CONFIG_ARCH_RV64I=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_BUILD_TARGET="u-boot-with-spl.bin"
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_DISPLAY_BOARDINFO=y
+# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
+CONFIG_SPL_RAM_SUPPORT=y
+CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SYS_PROMPT="C910 Light# "
+CONFIG_DDR_LP4X_3200_SINGLERANK=y
+CONFIG_DDR_H32_MODE=y
+# CONFIG_DDR_LP4_3733_DUALRANK is not set
+CONFIG_DDR_BOARD_CONFIG=y
+CONFIG_CMD_BOOT_SLAVE=y
+CONFIG_CMD_ERASEENV=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_TIME=y
+CONFIG_DDR_SCAN=y
+CONFIG_DDR_PRBS_TEST=n
+# CONFIG_DOS_PARTITION is not set
+# CONFIG_ISO_PARTITION is not set
+CONFIG_PARTITION_TYPE_GUID=y
+CONFIG_OF_EMBED=y
+CONFIG_DEFAULT_DEVICE_TREE="light-b-power"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SPL_CLK=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_UDP_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x10000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_DW=y
+CONFIG_DWAPB_GPIO=y
+# CONFIG_MMC_SPI is not set
+CONFIG_MMC_VERBOSE=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_SNPS=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SNPS=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MMC_RPMB=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_SPI_NAND=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_PHY_REALTEK=y
+CONFIG_RTL8211E_PINE64_GIGABIT_FIX=y
+CONFIG_RTL8211X_PHY_FORCE_MASTER=y
+CONFIG_RTL8211F_PHY_FORCE_EEE_RXC_ON=y
+CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_DESIGNWARE_SPI=y
+CONFIG_DESIGNWARE_QSPI=y
+CONFIG_USB=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="U-Boot-THEAD"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1234
+CONFIG_USB_GADGET_PRODUCT_NUM=0x8888
+# CONFIG_SPL_USE_TINY_PRINTF is not set
+# CONFIG_EFI_LOADER is not set
+# CONFIG_LIGHT_SEC_BOOT is not set
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_DM_VIDEO=y
+CONFIG_PHY=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_CMD_BMP=y
+CONFIG_VIDEO_BRIDGE=y
+CONFIG_DM_PCA953X=y
+CONFIG_VIDEO_VS_DPU=y
+CONFIG_VIDEO_LCD_ILITEK_ILI9881C=y
+CONFIG_VIDEO_DW_DSI_LIGHT=y
+CONFIG_VIDEO_DW_DPHY=y
+CONFIG_VIDEO_DW_DSI_HOST=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_SYS_TEXT_BASE=0x7b000000
+CONFIG_PMIC_VOL_INIT=y
+CONFIG_DDR_REGU_0V6=600000
+CONFIG_DDR_REGU_0V8=800000
+CONFIG_DDR_REGU_1V1=1100000

configs/light_b_product_android_defconfig

@@ -0,0 +1,121 @@
+CONFIG_RISCV=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_ENV_SIZE=0x20000
+CONFIG_ENV_OFFSET=0xe0000
+CONFIG_NR_DRAM_BANKS=8
+CONFIG_SPL=y
+CONFIG_SMP=y
+CONFIG_TARGET_LIGHT_C910=y
+CONFIG_TARGET_LIGHT_FM_C910_VAL_B=y
+CONFIG_ARCH_RV64I=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_BUILD_TARGET="u-boot-with-spl.bin"
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_DISPLAY_BOARDINFO=y
+# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
+CONFIG_SPL_RAM_SUPPORT=y
+CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SYS_PROMPT="C910 Light# "
+CONFIG_DDR_LP4X_3200_SINGLERANK=y
+CONFIG_DDR_H32_MODE=y
+# CONFIG_DDR_LP4_3733_DUALRANK is not set
+CONFIG_DDR_BOARD_CONFIG=y
+CONFIG_CMD_BOOT_SLAVE=y
+CONFIG_CMD_ERASEENV=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_TIME=y
+CONFIG_DDR_SCAN=y
+CONFIG_DDR_PRBS_TEST=n
+# CONFIG_DOS_PARTITION is not set
+# CONFIG_ISO_PARTITION is not set
+CONFIG_PARTITION_TYPE_GUID=y
+CONFIG_OF_EMBED=y
+CONFIG_DEFAULT_DEVICE_TREE="light-b-product"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SPL_CLK=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_UDP_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x10000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_DW=y
+CONFIG_DWAPB_GPIO=y
+# CONFIG_MMC_SPI is not set
+CONFIG_MMC_VERBOSE=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_SNPS=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SNPS=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MMC_RPMB=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_SPI_NAND=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_PHY_REALTEK=y
+CONFIG_RTL8211E_PINE64_GIGABIT_FIX=y
+CONFIG_RTL8211X_PHY_FORCE_MASTER=y
+CONFIG_RTL8211F_PHY_FORCE_EEE_RXC_ON=y
+CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_DESIGNWARE_SPI=y
+CONFIG_DESIGNWARE_QSPI=y
+CONFIG_USB=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="U-Boot-THEAD"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1234
+CONFIG_USB_GADGET_PRODUCT_NUM=0x8888
+# CONFIG_SPL_USE_TINY_PRINTF is not set
+# CONFIG_EFI_LOADER is not set
+# CONFIG_LIGHT_SEC_BOOT_WITH_VERIFY_VAL_A=y
+# CONFIG_LIGHT_SEC_UPGRADE=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_DM_VIDEO=y
+CONFIG_PHY=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_CMD_BMP=y
+CONFIG_VIDEO_BRIDGE=y
+CONFIG_DM_PCA953X=y
+CONFIG_VIDEO_VS_DPU=y
+CONFIG_VIDEO_LCD_ILITEK_ILI9881C=y
+CONFIG_VIDEO_DW_DSI_LIGHT=y
+CONFIG_VIDEO_DW_DPHY=y
+CONFIG_VIDEO_DW_DSI_HOST=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_SYS_TEXT_BASE=0x7b000000
+CONFIG_PMIC_VOL_INIT=y
+CONFIG_DDR_REGU_0V6=600000
+CONFIG_DDR_REGU_0V8=800000
+CONFIG_DDR_REGU_1V1=1100000
+CONFIG_SPL_TEXT_BASE=0xffe0000800
+CONFIG_LIGHT_ANDROID_BOOT_IMAGE_VAL_B=y
+CONFIG_AVB_USE_OEM_KEY=y
+# CONFIG_AVB_ROLLBACK_ENABLE is not set
+CONFIG_AVB_HW_ENGINE_ENABLE=y
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_LIBAVB=y
+CONFIG_AVB_VERIFY=y
+CONFIG_CMD_AVB=y
+CONFIG_CMD_BOOTANDROID=y
+CONFIG_ANDROID_AB=y
+CONFIG_CMD_AB_SELECT=y
+CONFIG_XBC=y
+CONFIG_BOARD_RNG_SEED=y

configs/light_b_ref_defconfig

@@ -6,7 +6,7 @@ CONFIG_NR_DRAM_BANKS=8
 CONFIG_SPL=y
 CONFIG_SMP=y
 CONFIG_TARGET_LIGHT_C910=y
-CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_EVT=y
+CONFIG_TARGET_LIGHT_FM_C910_B_REF=y
 CONFIG_ARCH_RV64I=y
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_BUILD_TARGET="u-boot-with-spl.bin"
@@ -28,13 +28,14 @@ CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_TIME=y
 CONFIG_DDR_SCAN=y
 CONFIG_DDR_PRBS_TEST=n
 # CONFIG_DOS_PARTITION is not set
 # CONFIG_ISO_PARTITION is not set
 CONFIG_PARTITION_TYPE_GUID=y
 CONFIG_OF_EMBED=y
-CONFIG_DEFAULT_DEVICE_TREE="light-ant-evt"
+CONFIG_DEFAULT_DEVICE_TREE="light-b-ref"
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_SPL_CLK=y

configs/light_beagle_android_defconfig

@@ -0,0 +1,117 @@
+CONFIG_RISCV=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_ENV_SIZE=0x20000
+CONFIG_ENV_OFFSET=0xe0000
+CONFIG_NR_DRAM_BANKS=8
+CONFIG_SPL=y
+CONFIG_SMP=y
+CONFIG_TARGET_LIGHT_C910=y
+CONFIG_TARGET_LIGHT_FM_C910_BEAGLE=y
+CONFIG_ARCH_RV64I=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_BUILD_TARGET="u-boot-with-spl.bin"
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_DISPLAY_BOARDINFO=y
+# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
+CONFIG_SPL_RAM_SUPPORT=y
+CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SYS_PROMPT="C910 Light# "
+CONFIG_DDR_LP4X_3733_SINGLERANK=y
+# CONFIG_DDR_LP4_3733_DUALRANK is not set
+CONFIG_DDR_BOARD_CONFIG=y
+CONFIG_CMD_BOOT_SLAVE=y
+CONFIG_CMD_ERASEENV=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_DDR_SCAN=y
+CONFIG_DDR_PRBS_TEST=n
+# CONFIG_DOS_PARTITION is not set
+# CONFIG_ISO_PARTITION is not set
+CONFIG_PARTITION_TYPE_GUID=y
+CONFIG_OF_EMBED=y
+CONFIG_DEFAULT_DEVICE_TREE="light-a-val"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SPL_CLK=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_UDP_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x10000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_DW=y
+CONFIG_DWAPB_GPIO=y
+# CONFIG_MMC_SPI is not set
+CONFIG_MMC_VERBOSE=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_SNPS=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SNPS=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MMC_RPMB=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_SPI_NAND=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_PHY_REALTEK=y
+CONFIG_RTL8211E_PINE64_GIGABIT_FIX=y
+CONFIG_RTL8211X_PHY_FORCE_MASTER=y
+CONFIG_RTL8211F_PHY_FORCE_EEE_RXC_ON=y
+CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_DESIGNWARE_SPI=y
+CONFIG_DESIGNWARE_QSPI=y
+CONFIG_USB=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="U-Boot-THEAD"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1234
+CONFIG_USB_GADGET_PRODUCT_NUM=0x8888
+# CONFIG_SPL_USE_TINY_PRINTF is not set
+# CONFIG_EFI_LOADER is not set
+# CONFIG_LIGHT_SEC_BOOT is not set
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_DM_VIDEO=y
+CONFIG_PHY=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_CMD_BMP=y
+CONFIG_VIDEO_BRIDGE=y
+CONFIG_DM_PCA953X=y
+CONFIG_VIDEO_VS_DPU=y
+CONFIG_VIDEO_LCD_ILITEK_ILI9881C=y
+CONFIG_VIDEO_DW_DSI_LIGHT=y
+CONFIG_VIDEO_DW_DPHY=y
+CONFIG_VIDEO_DW_DSI_HOST=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_PMIC_VOL_INIT=y
+CONFIG_DDR_REGU_0V6=600000
+CONFIG_DDR_REGU_0V8=800000
+CONFIG_DDR_REGU_1V1=1100000
+CONFIG_LIGHT_ANDROID_BOOT_IMAGE_VAL_BEAGLE=y
+CONFIG_AVB_USE_OEM_KEY=y
+# CONFIG_AVB_ROLLBACK_ENABLE is not set
+CONFIG_AVB_HW_ENGINE_ENABLE=y
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_LIBAVB=y
+CONFIG_AVB_VERIFY=y
+CONFIG_CMD_AVB=y
+CONFIG_CMD_BOOTANDROID=y
+CONFIG_ANDROID_AB=y
+CONFIG_CMD_AB_SELECT=y
+CONFIG_XBC=y
+CONFIG_BOARD_RNG_SEED=y
+CONFIG_SPL_TEXT_BASE=0xffe0000800

configs/light_beagle_defconfig

@@ -0,0 +1,101 @@
+CONFIG_RISCV=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_ENV_SIZE=0x20000
+CONFIG_ENV_OFFSET=0xe0000
+CONFIG_NR_DRAM_BANKS=8
+CONFIG_SPL=y
+CONFIG_SMP=y
+CONFIG_TARGET_LIGHT_C910=y
+CONFIG_PMIC_VOL_INIT=y
+CONFIG_TARGET_LIGHT_FM_C910_BEAGLE=y
+CONFIG_DDR_LP4X_3733_SINGLERANK=y
+CONFIG_DDR_BOARD_CONFIG=y
+CONFIG_ARCH_RV64I=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_BUILD_TARGET="u-boot-with-spl.bin"
+CONFIG_DEFAULT_FDT_FILE="thead/light-beagle.dtb"
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_DISPLAY_BOARDINFO=y
+# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
+CONFIG_SPL_RAM_SUPPORT=y
+CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SYS_PROMPT="Light AHead# "
+CONFIG_CMD_BOOT_SLAVE=y
+CONFIG_CMD_ERASEENV=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_DDR_SCAN=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_EXT4_WRITE=y
+# CONFIG_DOS_PARTITION is not set
+# CONFIG_ISO_PARTITION is not set
+CONFIG_PARTITION_TYPE_GUID=y
+CONFIG_OF_EMBED=y
+CONFIG_DEFAULT_DEVICE_TREE="light-beagle"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_SPL_CLK=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_UDP_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x10000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_DM_GPIO=y
+CONFIG_DWAPB_GPIO=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_DW=y
+# CONFIG_MMC_SPI is not set
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_SNPS=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_MMC_SDHCI_SNPS=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MMC_RPMB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_SPI_NAND=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_PHY_REALTEK=y
+CONFIG_RTL8211E_PINE64_GIGABIT_FIX=y
+CONFIG_RTL8211X_PHY_FORCE_MASTER=y
+CONFIG_RTL8211F_PHY_FORCE_EEE_RXC_ON=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_PHY=y
+CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_DESIGNWARE_SPI=y
+CONFIG_DESIGNWARE_QSPI=y
+CONFIG_USB=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="U-Boot-THEAD"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1234
+CONFIG_USB_GADGET_PRODUCT_NUM=0x8888
+CONFIG_USB_FUNCTION_MASS_STORAGE=y
+CONFIG_DM_VIDEO=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_VIDEO_LCD_ILITEK_ILI9881C=y
+CONFIG_VIDEO_BRIDGE=y
+CONFIG_VIDEO_VS_DPU=y
+CONFIG_VIDEO_DW_DSI_LIGHT=y
+CONFIG_VIDEO_DW_DPHY=y
+# CONFIG_SPL_USE_TINY_PRINTF is not set
+CONFIG_OF_LIBFDT_OVERLAY=y
+# CONFIG_EFI_LOADER is not set
+CONFIG_BOARD_RNG_SEED=y

configs/light_lpi4a_16g_defconfig

@@ -0,0 +1,111 @@
+CONFIG_RISCV=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_ENV_SIZE=0x20000
+CONFIG_ENV_OFFSET=0xe0000
+CONFIG_NR_DRAM_BANKS=8
+CONFIG_SPL=y
+CONFIG_SMP=y
+CONFIG_TARGET_LIGHT_C910=y
+CONFIG_TARGET_LIGHT_FM_C910_LPI4A=y
+# CONFIG_THEAD_PLIC is not set
+# CONFIG_THEAD_LIGHT_TIMER is not set
+# CONFIG_THEAD_LIGHT_DIGITAL_SENSOR is not set
+CONFIG_ARCH_RV64I=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_BUILD_TARGET="u-boot-with-spl.bin"
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_DISPLAY_BOARDINFO=y
+# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
+CONFIG_SPL_RAM_SUPPORT=y
+CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SYS_PROMPT="Light LPI4A 16G# "
+CONFIG_DDR_LP4X_3733_DUALRANK=y
+CONFIG_DDR_DDP=y
+# CONFIG_DDR_LP4_3733_DUALRANK is not set
+CONFIG_DDR_BOARD_CONFIG=y
+CONFIG_CMD_BOOT_SLAVE=y
+CONFIG_CMD_ERASEENV=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_DDR_SCAN=y
+CONFIG_DDR_PRBS_TEST=n
+# CONFIG_DOS_PARTITION is not set
+# CONFIG_ISO_PARTITION is not set
+CONFIG_PARTITION_TYPE_GUID=y
+CONFIG_OF_EMBED=y
+CONFIG_DEFAULT_DEVICE_TREE="light-lpi4a"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SPL_CLK=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_UDP_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x10000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_DW=y
+CONFIG_DWAPB_GPIO=y
+# CONFIG_MMC_SPI is not set
+CONFIG_MMC_VERBOSE=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_SNPS=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SNPS=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MMC_RPMB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_SPI_NAND=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_PHY_REALTEK=y
+CONFIG_RTL8211E_PINE64_GIGABIT_FIX=y
+CONFIG_RTL8211X_PHY_FORCE_MASTER=y
+CONFIG_RTL8211F_PHY_FORCE_EEE_RXC_ON=y
+CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_DESIGNWARE_SPI=y
+CONFIG_DESIGNWARE_QSPI=y
+CONFIG_USB=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="U-Boot-THEAD"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1234
+CONFIG_USB_GADGET_PRODUCT_NUM=0x8888
+CONFIG_USB_FUNCTION_MASS_STORAGE=y
+# CONFIG_SPL_USE_TINY_PRINTF is not set
+# CONFIG_EFI_LOADER is not set
+# CONFIG_LIGHT_SEC_BOOT is not set
+CONFIG_DEFAULT_FDT_FILE="thead/light-lpi4a-16gb.dtb"
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_DM_VIDEO=y
+CONFIG_PHY=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_CMD_BMP=y
+CONFIG_VIDEO_BRIDGE=y
+CONFIG_DM_PCA953X=y
+CONFIG_VIDEO_VS_DPU=y
+CONFIG_VIDEO_LCD_ILITEK_ILI9881C=y
+CONFIG_VIDEO_DW_DSI_LIGHT=y
+CONFIG_VIDEO_DW_DPHY=y
+CONFIG_VIDEO_DW_DSI_HOST=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_PMIC_VOL_INIT=y
+CONFIG_DDR_REGU_0V6=600000
+CONFIG_DDR_REGU_0V8=800000
+CONFIG_DDR_REGU_1V1=1100000
+CONFIG_BOARD_RNG_SEED=y

configs/light_lpi4a_android_defconfig

@@ -0,0 +1,117 @@
+CONFIG_RISCV=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_ENV_SIZE=0x20000
+CONFIG_ENV_OFFSET=0xe0000
+CONFIG_NR_DRAM_BANKS=8
+CONFIG_SPL=y
+CONFIG_SMP=y
+CONFIG_TARGET_LIGHT_C910=y
+CONFIG_TARGET_LIGHT_FM_C910_LPI4A=y
+CONFIG_ARCH_RV64I=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_BUILD_TARGET="u-boot-with-spl.bin"
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_DISPLAY_BOARDINFO=y
+# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
+CONFIG_SPL_RAM_SUPPORT=y
+CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SYS_PROMPT="C910 Light# "
+CONFIG_DDR_LP4X_3733_DUALRANK=y
+# CONFIG_DDR_LP4_3733_DUALRANK is not set
+CONFIG_DDR_BOARD_CONFIG=y
+CONFIG_CMD_BOOT_SLAVE=y
+CONFIG_CMD_ERASEENV=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_DDR_SCAN=y
+CONFIG_DDR_PRBS_TEST=n
+# CONFIG_DOS_PARTITION is not set
+# CONFIG_ISO_PARTITION is not set
+CONFIG_PARTITION_TYPE_GUID=y
+CONFIG_OF_EMBED=y
+CONFIG_DEFAULT_DEVICE_TREE="light-lpi4a"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SPL_CLK=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_UDP_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x10000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_DW=y
+CONFIG_DWAPB_GPIO=y
+# CONFIG_MMC_SPI is not set
+CONFIG_MMC_VERBOSE=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_SNPS=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SNPS=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MMC_RPMB=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_SPI_NAND=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_PHY_REALTEK=y
+CONFIG_RTL8211E_PINE64_GIGABIT_FIX=y
+CONFIG_RTL8211X_PHY_FORCE_MASTER=y
+CONFIG_RTL8211F_PHY_FORCE_EEE_RXC_ON=y
+CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_DESIGNWARE_SPI=y
+CONFIG_DESIGNWARE_QSPI=y
+CONFIG_USB=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="U-Boot-THEAD"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1234
+CONFIG_USB_GADGET_PRODUCT_NUM=0x8888
+# CONFIG_SPL_USE_TINY_PRINTF is not set
+# CONFIG_EFI_LOADER is not set
+# CONFIG_LIGHT_SEC_BOOT is not set
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_DM_VIDEO=y
+CONFIG_PHY=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_CMD_BMP=y
+CONFIG_VIDEO_BRIDGE=y
+CONFIG_DM_PCA953X=y
+CONFIG_VIDEO_VS_DPU=y
+CONFIG_VIDEO_LCD_ILITEK_ILI9881C=y
+CONFIG_VIDEO_DW_DSI_LIGHT=y
+CONFIG_VIDEO_DW_DPHY=y
+CONFIG_VIDEO_DW_DSI_HOST=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_PMIC_VOL_INIT=y
+CONFIG_DDR_REGU_0V6=600000
+CONFIG_DDR_REGU_0V8=800000
+CONFIG_DDR_REGU_1V1=1100000
+CONFIG_SPL_TEXT_BASE=0xffe0000800
+CONFIG_LIGHT_ANDROID_BOOT_IMAGE_VAL_LPI4A=y
+CONFIG_AVB_USE_OEM_KEY=y
+# CONFIG_AVB_ROLLBACK_ENABLE is not set
+CONFIG_AVB_HW_ENGINE_ENABLE=y
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_LIBAVB=y
+CONFIG_AVB_VERIFY=y
+CONFIG_CMD_AVB=y
+CONFIG_CMD_BOOTANDROID=y
+CONFIG_ANDROID_AB=y
+CONFIG_CMD_AB_SELECT=y
+CONFIG_XBC=y
+CONFIG_BOARD_RNG_SEED=y

configs/light_lpi4a_cluster_16g_defconfig

@@ -0,0 +1,111 @@
+CONFIG_RISCV=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_ENV_SIZE=0x20000
+CONFIG_ENV_OFFSET=0xe0000
+CONFIG_NR_DRAM_BANKS=8
+CONFIG_SPL=y
+CONFIG_SMP=y
+CONFIG_TARGET_LIGHT_C910=y
+CONFIG_TARGET_LIGHT_FM_C910_LPI4A=y
+# CONFIG_THEAD_PLIC is not set
+# CONFIG_THEAD_LIGHT_TIMER is not set
+# CONFIG_THEAD_LIGHT_DIGITAL_SENSOR is not set
+CONFIG_ARCH_RV64I=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_BUILD_TARGET="u-boot-with-spl.bin"
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_DISPLAY_BOARDINFO=y
+# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
+CONFIG_SPL_RAM_SUPPORT=y
+CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SYS_PROMPT="LicheeCluster4A 16G # "
+CONFIG_DDR_LP4X_3733_DUALRANK=y
+CONFIG_DDR_DDP=y
+# CONFIG_DDR_LP4_3733_DUALRANK is not set
+CONFIG_DDR_BOARD_CONFIG=y
+CONFIG_CMD_BOOT_SLAVE=y
+CONFIG_CMD_ERASEENV=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_DDR_SCAN=y
+CONFIG_DDR_PRBS_TEST=n
+# CONFIG_DOS_PARTITION is not set
+# CONFIG_ISO_PARTITION is not set
+CONFIG_PARTITION_TYPE_GUID=y
+CONFIG_OF_EMBED=y
+CONFIG_DEFAULT_DEVICE_TREE="light-lpi4a"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SPL_CLK=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_UDP_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x10000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_DW=y
+CONFIG_DWAPB_GPIO=y
+# CONFIG_MMC_SPI is not set
+CONFIG_MMC_VERBOSE=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_SNPS=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SNPS=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MMC_RPMB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_SPI_NAND=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_PHY_REALTEK=y
+CONFIG_RTL8211E_PINE64_GIGABIT_FIX=y
+CONFIG_RTL8211X_PHY_FORCE_MASTER=y
+CONFIG_RTL8211F_PHY_FORCE_EEE_RXC_ON=y
+CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_DESIGNWARE_SPI=y
+CONFIG_DESIGNWARE_QSPI=y
+CONFIG_USB=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="U-Boot-THEAD"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1234
+CONFIG_USB_GADGET_PRODUCT_NUM=0x8888
+CONFIG_USB_FUNCTION_MASS_STORAGE=y
+# CONFIG_SPL_USE_TINY_PRINTF is not set
+# CONFIG_EFI_LOADER is not set
+# CONFIG_LIGHT_SEC_BOOT is not set
+CONFIG_DEFAULT_FDT_FILE="thead/light-lpi4a-cluster-16gb.dtb"
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_DM_VIDEO=y
+CONFIG_PHY=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_CMD_BMP=y
+CONFIG_VIDEO_BRIDGE=y
+CONFIG_DM_PCA953X=y
+CONFIG_VIDEO_VS_DPU=y
+CONFIG_VIDEO_LCD_ILITEK_ILI9881C=y
+CONFIG_VIDEO_DW_DSI_LIGHT=y
+CONFIG_VIDEO_DW_DPHY=y
+CONFIG_VIDEO_DW_DSI_HOST=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_PMIC_VOL_INIT=y
+CONFIG_DDR_REGU_0V6=600000
+CONFIG_DDR_REGU_0V8=800000
+CONFIG_DDR_REGU_1V1=1100000
+CONFIG_BOARD_RNG_SEED=y

configs/light_lpi4a_cluster_defconfig

@@ -0,0 +1,110 @@
+CONFIG_RISCV=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_ENV_SIZE=0x20000
+CONFIG_ENV_OFFSET=0xe0000
+CONFIG_NR_DRAM_BANKS=8
+CONFIG_SPL=y
+CONFIG_SMP=y
+CONFIG_TARGET_LIGHT_C910=y
+CONFIG_TARGET_LIGHT_FM_C910_LPI4A=y
+# CONFIG_THEAD_PLIC is not set
+# CONFIG_THEAD_LIGHT_TIMER is not set
+# CONFIG_THEAD_LIGHT_DIGITAL_SENSOR is not set
+CONFIG_ARCH_RV64I=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_BUILD_TARGET="u-boot-with-spl.bin"
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_DISPLAY_BOARDINFO=y
+# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
+CONFIG_SPL_RAM_SUPPORT=y
+CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SYS_PROMPT="LicheeCluster4A # "
+CONFIG_DDR_LP4X_3733_DUALRANK=y
+# CONFIG_DDR_LP4_3733_DUALRANK is not set
+CONFIG_DDR_BOARD_CONFIG=y
+CONFIG_CMD_BOOT_SLAVE=y
+CONFIG_CMD_ERASEENV=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_DDR_SCAN=y
+CONFIG_DDR_PRBS_TEST=n
+# CONFIG_DOS_PARTITION is not set
+# CONFIG_ISO_PARTITION is not set
+CONFIG_PARTITION_TYPE_GUID=y
+CONFIG_OF_EMBED=y
+CONFIG_DEFAULT_DEVICE_TREE="light-lpi4a"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SPL_CLK=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_UDP_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x10000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_DW=y
+CONFIG_DWAPB_GPIO=y
+# CONFIG_MMC_SPI is not set
+CONFIG_MMC_VERBOSE=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_SNPS=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SNPS=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MMC_RPMB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_SPI_NAND=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_PHY_REALTEK=y
+CONFIG_RTL8211E_PINE64_GIGABIT_FIX=y
+CONFIG_RTL8211X_PHY_FORCE_MASTER=y
+CONFIG_RTL8211F_PHY_FORCE_EEE_RXC_ON=y
+CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_DESIGNWARE_SPI=y
+CONFIG_DESIGNWARE_QSPI=y
+CONFIG_USB=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="U-Boot-THEAD"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1234
+CONFIG_USB_GADGET_PRODUCT_NUM=0x8888
+CONFIG_USB_FUNCTION_MASS_STORAGE=y
+# CONFIG_SPL_USE_TINY_PRINTF is not set
+# CONFIG_EFI_LOADER is not set
+# CONFIG_LIGHT_SEC_BOOT is not set
+CONFIG_DEFAULT_FDT_FILE="thead/light-lpi4a-cluster.dtb"
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_DM_VIDEO=y
+CONFIG_PHY=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_CMD_BMP=y
+CONFIG_VIDEO_BRIDGE=y
+CONFIG_DM_PCA953X=y
+CONFIG_VIDEO_VS_DPU=y
+CONFIG_VIDEO_LCD_ILITEK_ILI9881C=y
+CONFIG_VIDEO_DW_DSI_LIGHT=y
+CONFIG_VIDEO_DW_DPHY=y
+CONFIG_VIDEO_DW_DSI_HOST=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_PMIC_VOL_INIT=y
+CONFIG_DDR_REGU_0V6=600000
+CONFIG_DDR_REGU_0V8=800000
+CONFIG_DDR_REGU_1V1=1100000
+CONFIG_BOARD_RNG_SEED=y

configs/light_lpi4a_console_16g_defconfig

@@ -0,0 +1,111 @@
+CONFIG_RISCV=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_ENV_SIZE=0x20000
+CONFIG_ENV_OFFSET=0xe0000
+CONFIG_NR_DRAM_BANKS=8
+CONFIG_SPL=y
+CONFIG_SMP=y
+CONFIG_TARGET_LIGHT_C910=y
+CONFIG_TARGET_LIGHT_FM_C910_LPI4A=y
+# CONFIG_THEAD_PLIC is not set
+# CONFIG_THEAD_LIGHT_TIMER is not set
+# CONFIG_THEAD_LIGHT_DIGITAL_SENSOR is not set
+CONFIG_ARCH_RV64I=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_BUILD_TARGET="u-boot-with-spl.bin"
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_DISPLAY_BOARDINFO=y
+# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
+CONFIG_SPL_RAM_SUPPORT=y
+CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SYS_PROMPT="LicheeConsole4A 16G # "
+CONFIG_DDR_LP4X_3733_DUALRANK=y
+CONFIG_DDR_DDP=y
+# CONFIG_DDR_LP4_3733_DUALRANK is not set
+CONFIG_DDR_BOARD_CONFIG=y
+CONFIG_CMD_BOOT_SLAVE=y
+CONFIG_CMD_ERASEENV=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_DDR_SCAN=y
+CONFIG_DDR_PRBS_TEST=n
+# CONFIG_DOS_PARTITION is not set
+# CONFIG_ISO_PARTITION is not set
+CONFIG_PARTITION_TYPE_GUID=y
+CONFIG_OF_EMBED=y
+CONFIG_DEFAULT_DEVICE_TREE="light-lpi4a-laptop"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SPL_CLK=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_UDP_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x10000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_DW=y
+CONFIG_DWAPB_GPIO=y
+# CONFIG_MMC_SPI is not set
+CONFIG_MMC_VERBOSE=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_SNPS=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SNPS=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MMC_RPMB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_SPI_NAND=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_PHY_REALTEK=y
+CONFIG_RTL8211E_PINE64_GIGABIT_FIX=y
+CONFIG_RTL8211X_PHY_FORCE_MASTER=y
+CONFIG_RTL8211F_PHY_FORCE_EEE_RXC_ON=y
+CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_DESIGNWARE_SPI=y
+CONFIG_DESIGNWARE_QSPI=y
+CONFIG_USB=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="U-Boot-THEAD"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1234
+CONFIG_USB_GADGET_PRODUCT_NUM=0x8888
+CONFIG_USB_FUNCTION_MASS_STORAGE=y
+# CONFIG_SPL_USE_TINY_PRINTF is not set
+# CONFIG_EFI_LOADER is not set
+# CONFIG_LIGHT_SEC_BOOT is not set
+CONFIG_DEFAULT_FDT_FILE="thead/light-lpi4a-console-16g.dtb"
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_DM_VIDEO=y
+CONFIG_PHY=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_CMD_BMP=y
+CONFIG_VIDEO_BRIDGE=y
+CONFIG_DM_PCA953X=y
+CONFIG_VIDEO_VS_DPU=y
+CONFIG_VIDEO_LCD_ILITEK_ILI9881C=y
+CONFIG_VIDEO_DW_DSI_LIGHT=y
+CONFIG_VIDEO_DW_DPHY=y
+CONFIG_VIDEO_DW_DSI_HOST=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_PMIC_VOL_INIT=y
+CONFIG_DDR_REGU_0V6=600000
+CONFIG_DDR_REGU_0V8=800000
+CONFIG_DDR_REGU_1V1=1100000
+CONFIG_BOARD_RNG_SEED=y

configs/light_lpi4a_console_defconfig

@@ -0,0 +1,110 @@
+CONFIG_RISCV=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_ENV_SIZE=0x20000
+CONFIG_ENV_OFFSET=0xe0000
+CONFIG_NR_DRAM_BANKS=8
+CONFIG_SPL=y
+CONFIG_SMP=y
+CONFIG_TARGET_LIGHT_C910=y
+CONFIG_TARGET_LIGHT_FM_C910_LPI4A=y
+# CONFIG_THEAD_PLIC is not set
+# CONFIG_THEAD_LIGHT_TIMER is not set
+# CONFIG_THEAD_LIGHT_DIGITAL_SENSOR is not set
+CONFIG_ARCH_RV64I=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_BUILD_TARGET="u-boot-with-spl.bin"
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_DISPLAY_BOARDINFO=y
+# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
+CONFIG_SPL_RAM_SUPPORT=y
+CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SYS_PROMPT="LicheeConsole4A # "
+CONFIG_DDR_LP4X_3733_DUALRANK=y
+# CONFIG_DDR_LP4_3733_DUALRANK is not set
+CONFIG_DDR_BOARD_CONFIG=y
+CONFIG_CMD_BOOT_SLAVE=y
+CONFIG_CMD_ERASEENV=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_DDR_SCAN=y
+CONFIG_DDR_PRBS_TEST=n
+# CONFIG_DOS_PARTITION is not set
+# CONFIG_ISO_PARTITION is not set
+CONFIG_PARTITION_TYPE_GUID=y
+CONFIG_OF_EMBED=y
+CONFIG_DEFAULT_DEVICE_TREE="light-lpi4a-laptop"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SPL_CLK=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_UDP_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x10000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_DW=y
+CONFIG_DWAPB_GPIO=y
+# CONFIG_MMC_SPI is not set
+CONFIG_MMC_VERBOSE=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_SNPS=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SNPS=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MMC_RPMB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_SPI_NAND=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_PHY_REALTEK=y
+CONFIG_RTL8211E_PINE64_GIGABIT_FIX=y
+CONFIG_RTL8211X_PHY_FORCE_MASTER=y
+CONFIG_RTL8211F_PHY_FORCE_EEE_RXC_ON=y
+CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_DESIGNWARE_SPI=y
+CONFIG_DESIGNWARE_QSPI=y
+CONFIG_USB=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="U-Boot-THEAD"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1234
+CONFIG_USB_GADGET_PRODUCT_NUM=0x8888
+CONFIG_USB_FUNCTION_MASS_STORAGE=y
+# CONFIG_SPL_USE_TINY_PRINTF is not set
+# CONFIG_EFI_LOADER is not set
+# CONFIG_LIGHT_SEC_BOOT is not set
+CONFIG_DEFAULT_FDT_FILE="thead/light-lpi4a-console.dtb"
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_DM_VIDEO=y
+CONFIG_PHY=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_CMD_BMP=y
+CONFIG_VIDEO_BRIDGE=y
+CONFIG_DM_PCA953X=y
+CONFIG_VIDEO_VS_DPU=y
+CONFIG_VIDEO_LCD_ILITEK_ILI9881C=y
+CONFIG_VIDEO_DW_DSI_LIGHT=y
+CONFIG_VIDEO_DW_DPHY=y
+CONFIG_VIDEO_DW_DSI_HOST=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_PMIC_VOL_INIT=y
+CONFIG_DDR_REGU_0V6=600000
+CONFIG_DDR_REGU_0V8=800000
+CONFIG_DDR_REGU_1V1=1100000
+CONFIG_BOARD_RNG_SEED=y

configs/light_lpi4a_defconfig

@@ -0,0 +1,110 @@
+CONFIG_RISCV=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_ENV_SIZE=0x20000
+CONFIG_ENV_OFFSET=0xe0000
+CONFIG_NR_DRAM_BANKS=8
+CONFIG_SPL=y
+CONFIG_SMP=y
+CONFIG_TARGET_LIGHT_C910=y
+CONFIG_TARGET_LIGHT_FM_C910_LPI4A=y
+# CONFIG_THEAD_PLIC is not set
+# CONFIG_THEAD_LIGHT_TIMER is not set
+# CONFIG_THEAD_LIGHT_DIGITAL_SENSOR is not set
+CONFIG_ARCH_RV64I=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_BUILD_TARGET="u-boot-with-spl.bin"
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_DISPLAY_BOARDINFO=y
+# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
+CONFIG_SPL_RAM_SUPPORT=y
+CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SYS_PROMPT="Light LPI4A# "
+CONFIG_DDR_LP4X_3733_DUALRANK=y
+# CONFIG_DDR_LP4_3733_DUALRANK is not set
+CONFIG_DDR_BOARD_CONFIG=y
+CONFIG_CMD_BOOT_SLAVE=y
+CONFIG_CMD_ERASEENV=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_DDR_SCAN=y
+CONFIG_DDR_PRBS_TEST=n
+# CONFIG_DOS_PARTITION is not set
+# CONFIG_ISO_PARTITION is not set
+CONFIG_PARTITION_TYPE_GUID=y
+CONFIG_OF_EMBED=y
+CONFIG_DEFAULT_DEVICE_TREE="light-lpi4a"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SPL_CLK=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_UDP_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x10000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_DW=y
+CONFIG_DWAPB_GPIO=y
+# CONFIG_MMC_SPI is not set
+CONFIG_MMC_VERBOSE=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_SNPS=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SNPS=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MMC_RPMB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_SPI_NAND=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_PHY_REALTEK=y
+CONFIG_RTL8211E_PINE64_GIGABIT_FIX=y
+CONFIG_RTL8211X_PHY_FORCE_MASTER=y
+CONFIG_RTL8211F_PHY_FORCE_EEE_RXC_ON=y
+CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_DESIGNWARE_SPI=y
+CONFIG_DESIGNWARE_QSPI=y
+CONFIG_USB=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="U-Boot-THEAD"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1234
+CONFIG_USB_GADGET_PRODUCT_NUM=0x8888
+CONFIG_USB_FUNCTION_MASS_STORAGE=y
+# CONFIG_SPL_USE_TINY_PRINTF is not set
+# CONFIG_EFI_LOADER is not set
+# CONFIG_LIGHT_SEC_BOOT is not set
+CONFIG_DEFAULT_FDT_FILE="thead/light-lpi4a.dtb"
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_DM_VIDEO=y
+CONFIG_PHY=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_CMD_BMP=y
+CONFIG_VIDEO_BRIDGE=y
+CONFIG_DM_PCA953X=y
+CONFIG_VIDEO_VS_DPU=y
+CONFIG_VIDEO_LCD_ILITEK_ILI9881C=y
+CONFIG_VIDEO_DW_DSI_LIGHT=y
+CONFIG_VIDEO_DW_DPHY=y
+CONFIG_VIDEO_DW_DSI_HOST=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_PMIC_VOL_INIT=y
+CONFIG_DDR_REGU_0V6=600000
+CONFIG_DDR_REGU_0V8=800000
+CONFIG_DDR_REGU_1V1=1100000
+CONFIG_BOARD_RNG_SEED=y

configs/light_lpi4a_sec_defconfig

@@ -0,0 +1,107 @@
+CONFIG_RISCV=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_ENV_SIZE=0x20000
+CONFIG_ENV_OFFSET=0xe0000
+CONFIG_NR_DRAM_BANKS=8
+CONFIG_SPL=y
+CONFIG_SMP=y
+CONFIG_TARGET_LIGHT_C910=y
+CONFIG_TARGET_LIGHT_FM_C910_LPI4A=y
+# CONFIG_THEAD_PLIC is not set
+# CONFIG_THEAD_LIGHT_TIMER is not set
+# CONFIG_THEAD_LIGHT_DIGITAL_SENSOR is not set
+CONFIG_ARCH_RV64I=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_BUILD_TARGET="u-boot-with-spl.bin"
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_DISPLAY_BOARDINFO=y
+# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
+CONFIG_SPL_RAM_SUPPORT=y
+CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SYS_PROMPT="C910 Light# "
+CONFIG_DDR_LP4X_3733_DUALRANK=y
+# CONFIG_DDR_LP4_3733_DUALRANK is not set
+CONFIG_DDR_BOARD_CONFIG=y
+CONFIG_CMD_BOOT_SLAVE=y
+CONFIG_CMD_ERASEENV=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_DDR_SCAN=y
+CONFIG_DDR_PRBS_TEST=n
+# CONFIG_DOS_PARTITION is not set
+# CONFIG_ISO_PARTITION is not set
+CONFIG_PARTITION_TYPE_GUID=y
+CONFIG_OF_EMBED=y
+CONFIG_DEFAULT_DEVICE_TREE="light-lpi4a"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SPL_CLK=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_UDP_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x10000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_DW=y
+CONFIG_DWAPB_GPIO=y
+# CONFIG_MMC_SPI is not set
+CONFIG_MMC_VERBOSE=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_SNPS=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SNPS=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MMC_RPMB=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_SPI_NAND=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_PHY_REALTEK=y
+CONFIG_RTL8211E_PINE64_GIGABIT_FIX=y
+CONFIG_RTL8211X_PHY_FORCE_MASTER=y
+CONFIG_RTL8211F_PHY_FORCE_EEE_RXC_ON=y
+CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_DESIGNWARE_SPI=y
+CONFIG_DESIGNWARE_QSPI=y
+CONFIG_USB=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="U-Boot-THEAD"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1234
+CONFIG_USB_GADGET_PRODUCT_NUM=0x8888
+# CONFIG_SPL_USE_TINY_PRINTF is not set
+# CONFIG_EFI_LOADER is not set
+CONFIG_LIGHT_SEC_BOOT_WITH_VERIFY_LPI4A=y
+CONFIG_LIGHT_SEC_UPGRADE=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_DM_VIDEO=y
+CONFIG_PHY=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_CMD_BMP=y
+CONFIG_VIDEO_BRIDGE=y
+CONFIG_DM_PCA953X=y
+CONFIG_VIDEO_VS_DPU=y
+CONFIG_VIDEO_LCD_ILITEK_ILI9881C=y
+CONFIG_VIDEO_DW_DSI_LIGHT=y
+CONFIG_VIDEO_DW_DPHY=y
+CONFIG_VIDEO_DW_DSI_HOST=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_PMIC_VOL_INIT=y
+CONFIG_DDR_REGU_0V6=600000
+CONFIG_DDR_REGU_0V8=800000
+CONFIG_DDR_REGU_1V1=1100000

configs/light_lpi4a_singlerank_defconfig

@@ -0,0 +1,106 @@
+CONFIG_RISCV=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_ENV_SIZE=0x20000
+CONFIG_ENV_OFFSET=0xe0000
+CONFIG_NR_DRAM_BANKS=8
+CONFIG_SPL=y
+CONFIG_SMP=y
+CONFIG_TARGET_LIGHT_C910=y
+CONFIG_TARGET_LIGHT_FM_C910_LPI4A=y
+# CONFIG_THEAD_PLIC is not set
+# CONFIG_THEAD_LIGHT_TIMER is not set
+# CONFIG_THEAD_LIGHT_DIGITAL_SENSOR is not set
+CONFIG_ARCH_RV64I=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_BUILD_TARGET="u-boot-with-spl.bin"
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_DISPLAY_BOARDINFO=y
+# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
+CONFIG_SPL_RAM_SUPPORT=y
+CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SYS_PROMPT="C910 Light# "
+CONFIG_DDR_LP4X_3733_SINGLERANK=y
+# CONFIG_DDR_LP4_3733_DUALRANK is not set
+CONFIG_DDR_BOARD_CONFIG=y
+CONFIG_CMD_BOOT_SLAVE=y
+CONFIG_CMD_ERASEENV=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_DDR_SCAN=y
+CONFIG_DDR_PRBS_TEST=n
+# CONFIG_DOS_PARTITION is not set
+# CONFIG_ISO_PARTITION is not set
+CONFIG_PARTITION_TYPE_GUID=y
+CONFIG_OF_EMBED=y
+CONFIG_DEFAULT_DEVICE_TREE="light-lpi4a"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SPL_CLK=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_UDP_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x10000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_DW=y
+CONFIG_DWAPB_GPIO=y
+# CONFIG_MMC_SPI is not set
+CONFIG_MMC_VERBOSE=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_SNPS=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SNPS=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MMC_RPMB=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_SPI_NAND=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_PHY_REALTEK=y
+CONFIG_RTL8211E_PINE64_GIGABIT_FIX=y
+CONFIG_RTL8211X_PHY_FORCE_MASTER=y
+CONFIG_RTL8211F_PHY_FORCE_EEE_RXC_ON=y
+CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_DESIGNWARE_SPI=y
+CONFIG_DESIGNWARE_QSPI=y
+CONFIG_USB=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="U-Boot-THEAD"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1234
+CONFIG_USB_GADGET_PRODUCT_NUM=0x8888
+# CONFIG_SPL_USE_TINY_PRINTF is not set
+# CONFIG_EFI_LOADER is not set
+# CONFIG_LIGHT_SEC_BOOT is not set
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_DM_VIDEO=y
+CONFIG_PHY=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_CMD_BMP=y
+CONFIG_VIDEO_BRIDGE=y
+CONFIG_DM_PCA953X=y
+CONFIG_VIDEO_VS_DPU=y
+CONFIG_VIDEO_LCD_ILITEK_ILI9881C=y
+CONFIG_VIDEO_DW_DSI_LIGHT=y
+CONFIG_VIDEO_DW_DPHY=y
+CONFIG_VIDEO_DW_DSI_HOST=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_PMIC_VOL_INIT=y
+CONFIG_DDR_REGU_0V6=600000
+CONFIG_DDR_REGU_0V8=800000
+CONFIG_DDR_REGU_1V1=1100000

configs/light_milkv_meles_defconfig

@@ -0,0 +1,89 @@
+CONFIG_RISCV=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_ENV_SIZE=0x20000
+CONFIG_ENV_OFFSET=0xe0000
+CONFIG_NR_DRAM_BANKS=8
+CONFIG_SPL=y
+CONFIG_SMP=y
+CONFIG_TARGET_LIGHT_C910=y
+CONFIG_PMIC_VOL_INIT=y
+CONFIG_TARGET_LIGHT_FM_C910_MILKV_MELES=y
+CONFIG_DDR_LP4X_3733_SINGLERANK=y
+CONFIG_DDR_BOARD_CONFIG=y
+CONFIG_ARCH_RV64I=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_BUILD_TARGET="u-boot-with-spl.bin"
+CONFIG_DEFAULT_FDT_FILE="thead/th1520-milkv-meles.dtb"
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_DISPLAY_BOARDINFO=y
+# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
+CONFIG_SPL_RAM_SUPPORT=y
+CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SYS_PROMPT="Milk-V Meles# "
+CONFIG_CMD_BOOT_SLAVE=y
+CONFIG_CMD_ERASEENV=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_DDR_SCAN=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_EXT4_WRITE=y
+# CONFIG_DOS_PARTITION is not set
+# CONFIG_ISO_PARTITION is not set
+CONFIG_PARTITION_TYPE_GUID=y
+CONFIG_OF_EMBED=y
+CONFIG_DEFAULT_DEVICE_TREE="light-milkv-meles"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_SPL_CLK=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_UDP_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x10000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_DM_GPIO=y
+CONFIG_DWAPB_GPIO=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_DW=y
+# CONFIG_MMC_SPI is not set
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_SNPS=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_MMC_SDHCI_SNPS=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_SPI_NAND=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_PHY_REALTEK=y
+CONFIG_RTL8211E_PINE64_GIGABIT_FIX=y
+CONFIG_RTL8211X_PHY_FORCE_MASTER=y
+CONFIG_RTL8211F_PHY_FORCE_EEE_RXC_ON=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_PHY=y
+CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_DESIGNWARE_SPI=y
+CONFIG_DESIGNWARE_QSPI=y
+CONFIG_USB=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="U-Boot-THEAD"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1234
+CONFIG_USB_GADGET_PRODUCT_NUM=0x8888
+CONFIG_SYS_WHITE_ON_BLACK=y
+# CONFIG_SPL_USE_TINY_PRINTF is not set
+CONFIG_OF_LIBFDT_OVERLAY=y
+# CONFIG_EFI_LOADER is not set

configs/light_milkv_meles_dualrank_defconfig

@@ -0,0 +1,90 @@
+CONFIG_RISCV=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_ENV_SIZE=0x20000
+CONFIG_ENV_OFFSET=0xe0000
+CONFIG_NR_DRAM_BANKS=8
+CONFIG_SPL=y
+CONFIG_SMP=y
+CONFIG_TARGET_LIGHT_C910=y
+CONFIG_PMIC_VOL_INIT=y
+CONFIG_TARGET_LIGHT_FM_C910_MILKV_MELES=y
+CONFIG_DDR_LP4X_3733_DUALRANK=y
+CONFIG_DDR_BOARD_CONFIG=y
+CONFIG_ARCH_RV64I=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_BUILD_TARGET="u-boot-with-spl.bin"
+CONFIG_DEFAULT_FDT_FILE="thead/th1520-milkv-meles.dtb"
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_DISPLAY_BOARDINFO=y
+# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
+CONFIG_SPL_RAM_SUPPORT=y
+CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SYS_PROMPT="Milk-V Meles# "
+CONFIG_CMD_BOOT_SLAVE=y
+CONFIG_CMD_ERASEENV=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_DDR_SCAN=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_EXT4_WRITE=y
+# CONFIG_DOS_PARTITION is not set
+# CONFIG_ISO_PARTITION is not set
+CONFIG_PARTITION_TYPE_GUID=y
+CONFIG_OF_EMBED=y
+CONFIG_DEFAULT_DEVICE_TREE="light-milkv-meles"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_SPL_CLK=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_UDP_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x10000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_DM_GPIO=y
+CONFIG_DWAPB_GPIO=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_DW=y
+# CONFIG_MMC_SPI is not set
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_SNPS=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_MMC_SDHCI_SNPS=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_SPI_NAND=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_PHY_REALTEK=y
+CONFIG_RTL8211E_PINE64_GIGABIT_FIX=y
+CONFIG_RTL8211X_PHY_FORCE_MASTER=y
+CONFIG_RTL8211F_PHY_FORCE_EEE_RXC_ON=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_PHY=y
+CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_DESIGNWARE_SPI=y
+CONFIG_DESIGNWARE_QSPI=y
+CONFIG_USB=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="U-Boot-THEAD"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1234
+CONFIG_USB_GADGET_PRODUCT_NUM=0x8888
+CONFIG_SYS_WHITE_ON_BLACK=y
+# CONFIG_SPL_USE_TINY_PRINTF is not set
+CONFIG_OF_LIBFDT_OVERLAY=y
+# CONFIG_EFI_LOADER is not set
+CONFIG_BOARD_RNG_SEED=y

configs/light_milkv_meles_singlerank_defconfig

@@ -0,0 +1,90 @@
+CONFIG_RISCV=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_ENV_SIZE=0x20000
+CONFIG_ENV_OFFSET=0xe0000
+CONFIG_NR_DRAM_BANKS=8
+CONFIG_SPL=y
+CONFIG_SMP=y
+CONFIG_TARGET_LIGHT_C910=y
+CONFIG_PMIC_VOL_INIT=y
+CONFIG_TARGET_LIGHT_FM_C910_MILKV_MELES=y
+CONFIG_DDR_LP4X_3733_SINGLERANK=y
+CONFIG_DDR_BOARD_CONFIG=y
+CONFIG_ARCH_RV64I=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_BUILD_TARGET="u-boot-with-spl.bin"
+CONFIG_DEFAULT_FDT_FILE="thead/th1520-milkv-meles-4g.dtb"
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_DISPLAY_BOARDINFO=y
+# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
+CONFIG_SPL_RAM_SUPPORT=y
+CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SYS_PROMPT="Milk-V Meles 4G# "
+CONFIG_CMD_BOOT_SLAVE=y
+CONFIG_CMD_ERASEENV=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_DDR_SCAN=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_EXT4_WRITE=y
+# CONFIG_DOS_PARTITION is not set
+# CONFIG_ISO_PARTITION is not set
+CONFIG_PARTITION_TYPE_GUID=y
+CONFIG_OF_EMBED=y
+CONFIG_DEFAULT_DEVICE_TREE="light-milkv-meles"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_SPL_CLK=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_UDP_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x10000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_DM_GPIO=y
+CONFIG_DWAPB_GPIO=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_DW=y
+# CONFIG_MMC_SPI is not set
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_SNPS=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_MMC_SDHCI_SNPS=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_SPI_NAND=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_PHY_REALTEK=y
+CONFIG_RTL8211E_PINE64_GIGABIT_FIX=y
+CONFIG_RTL8211X_PHY_FORCE_MASTER=y
+CONFIG_RTL8211F_PHY_FORCE_EEE_RXC_ON=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_PHY=y
+CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_DESIGNWARE_SPI=y
+CONFIG_DESIGNWARE_QSPI=y
+CONFIG_USB=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="U-Boot-THEAD"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1234
+CONFIG_USB_GADGET_PRODUCT_NUM=0x8888
+CONFIG_SYS_WHITE_ON_BLACK=y
+# CONFIG_SPL_USE_TINY_PRINTF is not set
+CONFIG_OF_LIBFDT_OVERLAY=y
+# CONFIG_EFI_LOADER is not set
+CONFIG_BOARD_RNG_SEED=y

configs/tools-only_defconfig

@@ -6,6 +6,7 @@ CONFIG_FIT_SIGNATURE=y
 # CONFIG_CMD_BOOTD is not set
 # CONFIG_CMD_BOOTM is not set
 # CONFIG_CMD_ELF is not set
+# CONFIG_CMD_EXTENSION is not set
 # CONFIG_CMD_DATE is not set
 CONFIG_OF_CONTROL=y
 CONFIG_OF_HOSTFILE=y