riscv: dts: thead: downclock SD card for LPi4A

It's reported that @198MHz some R/W error will happen.

215f2c97bd.patch

Signed-off-by: Han Gao <gaohan@iscas.ac.cn>

.github/workflows/build.yml

@@ -0,0 +1,137 @@
+name: thead-u-boot-build
+
+on:
+  push:
+    tags:
+      - '*'
+    branches:
+      - '*'
+  pull_request:
+  workflow_dispatch:
+  schedule:
+    - cron: "0 2 * * *"
+
+env:
+  xuantie_toolchain: https://occ-oss-prod.oss-cn-hangzhou.aliyuncs.com/resource//1698113812618
+  toolchain_file_name: Xuantie-900-gcc-linux-5.10.4-glibc-x86_64-V2.8.0-20231018.tar.gz
+  mainline_toolchain: https://github.com/riscv-collab/riscv-gnu-toolchain/releases/download/2023.10.18
+  mainline_toolchain_file_name: riscv64-glibc-ubuntu-22.04-gcc-nightly-2023.10.18-nightly.tar.gz
+  wget_alias: 'wget --retry-connrefused --waitretry=1 --read-timeout=20 --timeout=15 -t 0'
+  ARCH: riscv
+  CROSS_COMPILE: riscv64-unknown-linux-gnu-
+
+jobs:
+  build:
+    strategy:
+      fail-fast: false
+      matrix:
+        name: [thead-gcc, gcc-13]
+
+    runs-on: ubuntu-22.04
+
+    steps:
+      - name: Install software
+        run: |
+              sudo apt update && \
+              sudo apt install -y gdisk dosfstools g++-12-riscv64-linux-gnu build-essential \
+                                  libncurses-dev gawk flex bison openssl libssl-dev tree \
+                                  dkms libelf-dev libudev-dev libpci-dev libiberty-dev autoconf device-tree-compiler
+
+      - name: Checkout uboot
+        uses: actions/checkout@v4
+
+      - name: uboot compile
+        run: |
+              mkdir output
+              if [[ ${{ matrix.name }} = "thead-gcc" ]]; then
+                ${wget_alias} ${xuantie_toolchain}/${toolchain_file_name}
+                tar -xvf ${toolchain_file_name} -C /opt
+                export PATH="/opt/Xuantie-900-gcc-linux-5.10.4-glibc-x86_64-V2.8.0/bin:$PATH"
+              else
+                ${wget_alias} ${mainline_toolchain}/${mainline_toolchain_file_name}
+                tar -xvf ${mainline_toolchain_file_name} -C /opt
+                export PATH="/opt/riscv/bin:$PATH"
+              fi
+              ${CROSS_COMPILE}gcc -v
+
+              pushd $PWD
+                make light_lpi4a_16g_defconfig
+                make -j$(nproc)
+                find . -name "u-boot-with-spl.bin" | xargs -I{} cp -av {} ${GITHUB_WORKSPACE}/output/u-boot-with-spl-lpi4a-16g.bin
+                make clean
+                make light_lpi4a_defconfig
+                make -j$(nproc)
+                find . -name "u-boot-with-spl.bin" | xargs -I{} cp -av {} ${GITHUB_WORKSPACE}/output/u-boot-with-spl-lpi4a.bin
+                make clean
+                make light_lpi4a_console_defconfig
+                make -j$(nproc)
+                find . -name "u-boot-with-spl.bin" | xargs -I{} cp -av {} ${GITHUB_WORKSPACE}/output/u-boot-with-spl-lcon4a.bin
+                make clean
+                make light_lpi4a_console_16g_defconfig
+                make -j$(nproc)
+                find . -name "u-boot-with-spl.bin" | xargs -I{} cp -av {} ${GITHUB_WORKSPACE}/output/u-boot-with-spl-lcon4a-16g.bin
+                make clean
+                make light_lpi4a_cluster_defconfig
+                make -j$(nproc)
+                find . -name "u-boot-with-spl.bin" | xargs -I{} cp -av {} ${GITHUB_WORKSPACE}/output/u-boot-with-spl-lc4a.bin
+                make clean
+                make light_lpi4a_cluster_16g_defconfig
+                make -j$(nproc)
+                find . -name "u-boot-with-spl.bin" | xargs -I{} cp -av {} ${GITHUB_WORKSPACE}/output/u-boot-with-spl-lc4a-16g.bin
+                make clean
+                make light_beagle_defconfig
+                make -j$(nproc)
+                find . -name "u-boot-with-spl.bin" | xargs -I{} cp -av {} ${GITHUB_WORKSPACE}/output/u-boot-with-spl-beagle.bin
+                make clean
+                make light_a_val_defconfig
+                make -j$(nproc)
+                find . -name "u-boot-with-spl.bin" | xargs -I{} cp -av {} ${GITHUB_WORKSPACE}/output/u-boot-with-spl-vala.bin
+                make clean
+                make light_milkv_meles_dualrank_defconfig
+                make -j$(nproc)
+                find . -name "u-boot-with-spl.bin" | xargs -I{} cp -av {} ${GITHUB_WORKSPACE}/output/u-boot-with-spl-meles.bin
+                make clean
+                make light_milkv_meles_singlerank_defconfig
+                make -j$(nproc)
+                find . -name "u-boot-with-spl.bin" | xargs -I{} cp -av {} ${GITHUB_WORKSPACE}/output/u-boot-with-spl-meles-4g.bin
+
+                # mainline support
+                make clean
+                make light_lpi4a_defconfig
+                sed -i 's#thead/light-lpi4a.dtb#thead/th1520-lichee-pi-4a.dtb#' .config
+                make -j$(nproc)
+                find . -name "u-boot-with-spl.bin" | xargs -I{} cp -av {} ${GITHUB_WORKSPACE}/output/u-boot-with-spl-lpi4a-main.bin
+
+                make clean
+                make light_lpi4a_16g_defconfig
+                sed -i 's#thead/light-lpi4a-16gb.dtb#thead/th1520-lichee-pi-4a-16g.dtb#' .config
+                make -j$(nproc)
+                find . -name "u-boot-with-spl.bin" | xargs -I{} cp -av {} ${GITHUB_WORKSPACE}/output/u-boot-with-spl-lpi4a-16g-main.bin
+
+                make clean
+                make light_lpi4a_cluster_defconfig
+                sed -i 's#thead/light-lpi4a-cluster.dtb#thead/th1520-lichee-cluster-4a.dtb#' .config
+                make -j$(nproc)
+                find . -name "u-boot-with-spl.bin" | xargs -I{} cp -av {} ${GITHUB_WORKSPACE}/output/u-boot-with-spl-lc4a-main.bin
+
+                make clean
+                make light_lpi4a_cluster_16g_defconfig
+                sed -i 's#thead/light-lpi4a-cluster-16gb.dtb#thead/th1520-lichee-cluster-4a-16g.dtb#' .config
+                make -j$(nproc)
+                find . -name "u-boot-with-spl.bin" | xargs -I{} cp -av {} ${GITHUB_WORKSPACE}/output/u-boot-with-spl-lc4a-16g-main.bin
+              popd
+              tree ${GITHUB_WORKSPACE}/output
+
+      - name: 'Upload Artifact'
+        uses: actions/upload-artifact@v3
+        with:
+          name: thead-u-uboot-${{ matrix.name }}
+          path: output/*.bin
+          retention-days: 30
+
+      - name: 'Create release by tag'
+        uses: softprops/action-gh-release@v1
+        if: ${{ startsWith(github.ref, 'refs/tags/') && matrix.name == 'thead-gcc' }}
+        with:
+          files: output/*.bin
+          token: ${{ secrets.GITHUB_TOKEN }}

arch/Kconfig

@@ -119,6 +119,7 @@ config SANDBOX
 	select SPI
 	select SUPPORT_OF_CONTROL
 	select SYSRESET_CMD_POWEROFF if CMD_POWEROFF
+	select SUPPORT_EXTENSION_SCAN
 	imply BITREVERSE
 	select BLOBLIST
 	imply CMD_DM
@@ -152,6 +153,7 @@ config SANDBOX
 	imply PHYLIB
 	imply DM_MDIO
 	imply DM_MDIO_MUX
+	imply CMD_EXTENSION
 
 config SH
 	bool "SuperH architecture"

arch/riscv/Makefile

@@ -24,7 +24,16 @@ ifeq ($(CONFIG_CMODEL_MEDANY),y)
 	CMODEL = medany
 endif
 
-ARCH_FLAGS = -march=$(ARCH_BASE)$(ARCH_A)$(ARCH_C) -mabi=$(ABI) \
+RISCV_MARCH = $(ARCH_BASE)$(ARCH_A)$(ARCH_C)
+
+# Newer binutils versions default to ISA spec version 20191213 which moves some
+# instructions from the I extension to the Zicsr and Zifencei extensions.
+toolchain-need-zicsr-zifencei := $(call cc-option-yn, -mabi=$(ABI) -march=$(RISCV_MARCH)_zicsr_zifencei)
+ifeq ($(toolchain-need-zicsr-zifencei),y)
+	RISCV_MARCH := $(RISCV_MARCH)_zicsr_zifencei
+endif
+
+ARCH_FLAGS = -march=$(RISCV_MARCH) -mabi=$(ABI) \
 	     -mcmodel=$(CMODEL)
 
 PLATFORM_CPPFLAGS	+= $(ARCH_FLAGS)

arch/riscv/cpu/c9xx/cpu.c

@@ -125,10 +125,11 @@ void icache_enable(void)
 #ifdef CONFIG_SPL_BUILD
 #ifdef CONFIG_SPL_RISCV_MMODE
 #ifdef CONFIG_TARGET_LIGHT_C910
+// mhcr is 0x7c1
 	asm volatile (
-        "csrr x29, mhcr\n\t"
+        "csrr x29, 0x7c1\n\t"
         "ori x28, x29, 0x1\n\t"
-        "csrw mhcr, x28\n\t"
+        "csrw 0x7c1, x28\n\t"
     );
 #endif
 #endif
@@ -141,9 +142,9 @@ void dcache_enable(void)
 #ifdef CONFIG_SPL_RISCV_MMODE
 #ifdef CONFIG_TARGET_LIGHT_C910
 	asm volatile (
-		"csrr x29, mhcr\n\t"
-        "ori x28, x29, 0x2\n\t"
-        "csrw mhcr, x28\n\t"
+	"csrr x29, 0x7c1\n\t"
+	"ori x28, x29, 0x2\n\t"
+	"csrw 0x7c1, x28\n\t"
     );
 #endif
 #endif

arch/riscv/cpu/c9xx/dram.c

@@ -14,9 +14,9 @@ DECLARE_GLOBAL_DATA_PTR;
 int dram_init(void)
 {
 #ifdef CONFIG_DDR_BOARD_CONFIG
-	// already setup during ddr initial flow
-	gd->bd->bi_memsize = gd->ram_size;
-	gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
+extern unsigned long get_ddr_density(void);
+	// update ram_size from board config info
+	gd->ram_size = get_ddr_density();
 	return 0;
 #else
 	return fdtdec_setup_mem_size_base();

arch/riscv/cpu/cpu.c

@@ -27,15 +27,6 @@ u32 hart_lottery __attribute__((section(".data"))) = 0;
 u32 available_harts_lock = 1;
 #endif
 
-void arch_setup_gd(struct global_data *gd_ptr)
-{
-	// sync specific info from spl
-	gd_ptr->ram_size = gd->ram_size;
-
-	// setup gd ptr
-	gd = gd_ptr;
-}
-
 static inline bool supports_extension(char ext)
 {
 #ifdef CONFIG_CPU

arch/riscv/cpu/start.S

@@ -104,6 +104,12 @@ call_board_init_f_0:
 	mv	a0, sp
 	jal	board_init_f_alloc_reserve
 
+	/*
+	 * Set global data pointer here for all harts, uninitialized at this
+	 * point.
+	 */
+	mv	gp, a0
+
 	/* setup stack */
 #ifdef CONFIG_SMP
 	/* tp: hart id */
@@ -121,34 +127,16 @@ call_board_init_f_0:
 	la	t0, hart_lottery
 	li	s2, 1
 	amoswap.w s2, t1, 0(t0)
-	beqz	s2, call_board_init_f_1
-
-	/*
-	 * Set global data pointer here for secondary harts, uninitialized at this
-	 * point.
-	 */
-	mv	gp, a0
-
-	jal wait_for_gd_init
+	bnez	s2, wait_for_gd_init
 #else
-	beqz	tp, call_board_init_f_1
-
-	/*
-	 * Set global data pointer here for secondary harts, uninitialized at this
-	 * point.
-	 */
-	mv	gp, a0
-
-	jal secondary_hart_loop
+	bnez	tp, secondary_hart_loop
 #endif
 
-call_board_init_f_1:
 #ifdef CONFIG_OF_PRIOR_STAGE
 	la	t0, prior_stage_fdt_address
 	SREG	s1, 0(t0)
 #endif
 
-	 /* Set global data pointer here for main hart */
 	jal	board_init_f_init_reserve
 
 	/* save the boot hart id to global_data */

arch/riscv/dts/Makefile

@@ -5,7 +5,8 @@ dtb-$(CONFIG_TARGET_SIFIVE_FU540) += hifive-unleashed-a00.dtb
 dtb-$(CONFIG_TARGET_ICE_C910) += ice-c910.dtb
 dtb-$(CONFIG_TARGET_LIGHT_EVB_MPW_C910) += light-evb-mpw-c910.dtb
 dtb-$(CONFIG_TARGET_LIGHT_FPGA_FM_C910) += light-fpga-fm-c910.dtb
-dtb-$(CONFIG_TARGET_LIGHT_C910) += light-a-ref.dtb light-b-ref.dtb light-a-val.dtb light-b-product.dtb light-a-product.dtb light-ant-ref.dtb light-beagle.dtb light-b-power.dtb light-lpi4a.dtb
+dtb-$(CONFIG_TARGET_LIGHT_C910) += light-a-ref.dtb light-b-ref.dtb light-a-val.dtb light-b-product.dtb light-a-product.dtb light-ant-ref.dtb light-beagle.dtb light-b-power.dtb light-lpi4a.dtb light-milkv-meles.dtb
+dtb-$(CONFIG_TARGET_LIGHT_C910) += light-lpi4a-laptop.dtb
 
 targets += $(dtb-y)
 

arch/riscv/dts/light-a-val.dts

@@ -1,7 +1,4 @@
 /dts-v1/;
-
-#include <dt-bindings/pmic/light_pmic.h>
-
 / {
 	model = "T-HEAD c910 light";
 	compatible = "thead,c910_light";
@@ -362,20 +359,6 @@
 			};
 		};
 
-		usb: usb@ffe7040000 {
-			compatible = "snps,dwc3";
-			reg = <0xff 0xe7040000 0x0 0x10000>;
-			interrupts = <68>;
-			reg-shift = <2>;
-			reg-io-width = <4>;
-			maximum-speed = "super-speed";
-			dr_mode = "host";
-			dma-mask = <0xf 0xffffffff>;
-			snps,usb3_lpm_capable;
-			snps,usb_sofitpsync;
-			status = "okay";
-		};
-
 		pwm: pwm@ffec01c000 {
 			compatible = "thead,pwm-light";
 			reg = <0xff 0xec01c000 0x0 0x4000>;
@@ -496,430 +479,6 @@
 			lcd-en-gpios    = <&pcal6408ahk_a 2 0>; /* active high */
 			lcd-bias-en-gpios = <&pcal6408ahk_a 4 0>;/* active high */
 		};
-
-		aon {
-		compatible = "thead,light-aon";
-		status = "okay";
-
-		wakeup-by-gpio-on;
-		wakeup-by-rtc-on;
-
-		pd: light-aon-pd {
-			compatible = "thead,light-aon-pd";
-			#power-domain-cells = <1>;
-		};
-
-		light-regu-reg {
-			compatible = "thead,light-dialog-pmic";
-			status = "okay";
-
-
-
-			soc_dvdd18_aon_reg: soc_dvdd18_aon {
-				regulator-name = "soc_dvdd18_aon";
-				regulator-boot-on;
-				regulator-always-on;
-			};
-
-			soc_avdd33_usb3_reg: soc_avdd33_usb3 {
-				regulator-name = "soc_avdd33_usb3";
-				regulator-boot-on;
-				regulator-always-on;
-			};
-
-			soc_dvdd08_aon_reg: soc_dvdd08_aon {
-				regulator-name = "soc_dvdd08_aon";
-				regulator-boot-on;
-				regulator-always-on;
-			};
-
-			soc_apcpu_dvdd_dvddm_reg: soc_apcpu_dvdd_dvddm {
-				regulator-name = "soc_apcpu_dvdd_dvddm";
-				regulator-min-microvolt = <300000>;
-				regulator-max-microvolt = <1570000>;
-				regulator-boot-on;
-				regulator-always-on;
-			};
-
-			soc_dvdd08_ddr_reg: soc_dvdd08_ddr {
-				regulator-name = "soc_dvdd08_ddr";
-				regulator-boot-on;
-				regulator-always-on;
-			};
-
-			soc_vdd_ddr_1v8_reg: soc_vdd_ddr_1v8 {
-				regulator-name = "soc_vdd_ddr_1v8";
-				regulator-boot-on;
-				regulator-always-on;
-			};
-
-			soc_vdd_ddr_1v1_reg: soc_vdd_ddr_1v1 {
-				regulator-name = "soc_vdd_ddr_1v1";
-				regulator-boot-on;
-				regulator-always-on;
-			};
-
-			soc_vdd_ddr_0v6_reg: soc_vdd_ddr_0v6 {
-				regulator-name = "soc_vdd_ddr_0v6";
-				regulator-boot-on;
-				regulator-always-on;
-			};
-
-			soc_dvdd18_ap_reg: soc_dvdd18_ap {
-				regulator-name = "soc_dvdd18_ap";
-				regulator-boot-on;
-				regulator-always-on;
-			};
-
-			soc_dvdd08_ap_reg: soc_dvdd08_ap {
-				regulator-name = "soc_dvdd08_ap";
-				regulator-boot-on;
-				regulator-always-on;
-			};
-
-			soc_avdd08_mipi_hdmi_reg: soc_avdd08_mipi_hdmi {
-				regulator-name = "soc_avdd08_mipi_hdmi";
-				regulator-boot-on;
-				regulator-always-on;
-			};
-
-			soc_avdd18_mipi_hdmi_reg: soc_avdd18_mipi_hdmi {
-				regulator-name = "soc_avdd18_mipi_hdmi";
-				regulator-boot-on;
-				regulator-always-on;
-			};
-
-			soc_dvdd33_emmc_reg: soc_dvdd33_emmc {
-				regulator-name = "soc_dvdd33_emmc";
-				regulator-boot-on;
-				regulator-always-on;
-			};
-
-			soc_dvdd18_emmc_reg: soc_dvdd18_emmc {
-				regulator-name = "soc_vdd18_emmc";
-				regulator-boot-on;
-				regulator-always-on;
-			};
-			soc_dovdd18_scan_reg: soc_dovdd18_scan {
-				regulator-name = "soc_dovdd18_scan";
-				regulator-min-microvolt = <900000>;
-				regulator-max-microvolt = <3600000>;
-			};
-			soc_vext_2v8_reg: soc_vext_2v8 {
-				regulator-name = "soc_vext_2v8";
-				regulator-boot-on;
-				regulator-always-on;
-			};
-			soc_dvdd12_scan_reg: soc_dvdd12_scan {
-				regulator-name = "soc_dvdd12_scan";
-				regulator-min-microvolt = <900000>;
-				regulator-max-microvolt = <3600000>;
-			};
-			soc_avdd28_scan_en_reg: soc_avdd28_scan_en {
-				regulator-name = "soc_avdd28_scan_en";
-				regulator-min-microvolt = <2800000>;
-				regulator-max-microvolt = <2800000>;
-			};
-			soc_avdd28_rgb_reg: soc_avdd28_rgb {
-				regulator-name = "soc_avdd28_rgb";
-				regulator-min-microvolt = <2200000>;
-				regulator-max-microvolt = <3475000>;
-				regulator-boot-on;
-				regulator-always-on;
-			};
-			soc_dovdd18_rgb_reg: soc_dovdd18_rgb {
-				regulator-name = "soc_dovdd18_rgb";
-				regulator-min-microvolt = <1200000>;
-				regulator-max-microvolt = <3600000>;
-				regulator-boot-on;
-				regulator-always-on;
-			};
-			soc_dvdd12_rgb_reg: soc_dvdd12_rgb {
-				regulator-name = "soc_dvdd12_rgb";
-				regulator-min-microvolt = <400000>;
-				regulator-max-microvolt = <1675000>;
-				regulator-boot-on;
-				regulator-always-on;
-			};
-			soc_avdd25_ir_reg: soc_avdd25_ir {
-				regulator-name = "soc_avdd25_ir";
-				regulator-min-microvolt = <2200000>;
-				regulator-max-microvolt = <3475000>;
-				regulator-boot-on;
-				regulator-always-on;
-			};
-			soc_dovdd18_ir_reg: soc_dovdd18_ir {
-				regulator-name = "soc_dovdd18_ir";
-				regulator-min-microvolt = <1200000>;
-				regulator-max-microvolt = <3600000>;
-				regulator-boot-on;
-				regulator-always-on;
-			};
-			soc_dvdd12_ir_reg: soc_dvdd12_ir {
-				regulator-name = "soc_dvdd12_ir";
-				regulator-min-microvolt = <400000>;
-				regulator-max-microvolt = <1675000>;
-				regulator-boot-on;
-				regulator-always-on;
-			};
-	   };
-
-	    aon_pmic_config {
-			compatible = "thead,light-pmic-conf";
-			status = "okay";
-			#address-cells = <1>;
-			#size-cells = <0>;
-			pmic_dev_0: pmic-dev@0 {
-			  pmic-name = "dialog,da9063,v1";
-			  pmic-addr = <0x5a 0x5b>;
-			  pmic_wdt_on;
-			  errio_gpio = <0 14 3>;
-			  status = "okay";
-			};
-
-			pmic_dev_1: pmic-dev@1 {
-			  pmic-name = "dialog,da9121,v1";
-			  pmic-addr = <0x68>;
-			  status = "okay";
-			};
-
-			pmic_dev_2: pmic-dev@2 {
-			  pmic-name = "dialog,slg51000,v1";
-			  pmic-addr = <0x75>;
-			  status = "okay";
-			};
-
-			regu_config_0 {
-                reg_info = <&soc_dvdd18_aon_reg>;
-				status = "okay";
-				regu_id@0 {
-                    pmic_dev = <&pmic_dev_0 DA9063_ID_LDO3>;
-				};
-			};
-
-			regu_config_1 {
-                reg_info = <&soc_avdd33_usb3_reg>;
-				status = "okay";
-				regu_id@0 {
-                    pmic_dev = <&pmic_dev_0 DA9063_ID_LDO9>;
-				};
-			};
-
-			regu_config_2 {
-                reg_info = <&soc_dvdd08_aon_reg>;
-				status = "okay";
-				regu_id@0 {
-                    pmic_dev = <&pmic_dev_0 DA9063_ID_LDO2>;
-				};
-			};
-
-			regu_config_3 {
-                reg_info = <&soc_apcpu_dvdd_dvddm_reg>;
-				status = "okay";
-				regu_id@0 {
-                    pmic_dev = <&pmic_dev_0 DA9063_ID_BCORE1>;
-					auto_on_info = <0 0 800000>;
-				};
-
-				regu_id@1 {
-                    pmic_dev = <&pmic_dev_0 DA9063_ID_BCORE2>;
-					auto_on_info = <1 0 800000>;
-				};
-
-				coupling_info@0 {
-					negative-min;
-                    info = <0 1 5 30>;
-				};
-			};
-
-			regu_config_4 {
-                reg_info = <&soc_dvdd08_ddr_reg>;
-				status = "okay";
-				regu_id@0 {
-                    pmic_dev = <&pmic_dev_0 DA9063_ID_BUCKPERI>;
-				};
-			};
-
-			regu_config_5 {
-                reg_info = <&soc_vdd_ddr_1v8_reg>;
-				status = "okay";
-				regu_id@0 {
-                    pmic_dev = <&pmic_dev_0 DA9063_ID_LDO4>;
-				};
-			};
-
-		    regu_config_6 {
-                reg_info = <&soc_vdd_ddr_1v1_reg>;
-				status = "okay";
-				regu_id@0 {
-                    pmic_dev = <&pmic_dev_0 DA9063_ID_BUCKMEM>;
-				};
-				regu_id@1 {
-                    pmic_dev = <&pmic_dev_0 DA9063_ID_BUCKIO>;
-				};
-
-			};
-
-			regu_config_7 {
-                reg_info = <&soc_vdd_ddr_0v6_reg>;
-				status = "okay";
-				regu_id@0 {
-                    pmic_dev = <&pmic_dev_0 DA9063_ID_BUCKPRO>;
-				};
-			};
-
-			regu_config_8 {
-                reg_info = <&soc_dvdd18_ap_reg>;
-				status = "okay";
-				regu_id@0 {
-                    pmic_dev = <&pmic_dev_0 DA9063_ID_LDO11>;
-				};
-			};
-
-            regu_config_9 {
-                reg_info = <&soc_avdd08_mipi_hdmi_reg>;
-				status = "okay";
-				regu_id@0 {
-					pmic_dev = <&pmic_dev_0 DA9063_ID_LDO1>;
-				};
-			};
-
-			regu_config_10 {
-                reg_info = <&soc_avdd18_mipi_hdmi_reg>;
-				status = "okay";
-				regu_id@0 {
-                    pmic_dev = <&pmic_dev_0 DA9063_ID_LDO5>;
-				};
-			};
-
-			regu_config_11 {
-                reg_info = <&soc_dvdd33_emmc_reg>;
-				status = "okay";
-				regu_id@0 {
-                    pmic_dev = <&pmic_dev_0 DA9063_ID_LDO10>;
-				};
-			};
-
-			regu_config_12 {
-                reg_info = <&soc_dovdd18_scan_reg>;
-				status = "okay";
-				regu_id@0 {
-                    pmic_dev = <&pmic_dev_0 DA9063_ID_LDO6>;
-					auto_on_info = <2 1 1800000>;
-					auto_off_info = <7 1>;
-				};
-			};
-
-			regu_config_13 {
-                reg_info = <&soc_vext_2v8_reg>;
-				status = "okay";
-				regu_id@0 {
-                    pmic_dev = <&pmic_dev_0 DA9063_ID_LDO7>;
-					auto_on_info = <3 1 2800000>;
-					auto_off_info = <8 1>;
-				};
-			};
-
-			regu_config_14 {
-                reg_info = <&soc_dvdd12_scan_reg>;
-				status = "okay";
-				regu_id@0 {
-                    pmic_dev = <&pmic_dev_0 DA9063_ID_LDO8>;
-					auto_on_info = <4 1 1200000>;
-					auto_off_info = <9 1>;
-				};
-			};
-
-			regu_config_15 {
-                reg_info = <&soc_avdd28_scan_en_reg>;
-				status = "okay";
-				regu_id@0 {
-                    pmic_dev = <&pmic_dev_0 DA9063_ID_GPIO4>;
-					auto_on_info = <5 1 2800000>;
-					auto_off_info = <6 1>;
-				};
-			};
-
-			regu_config_16 {
-                reg_info = <&soc_dvdd08_ap_reg>;
-				status = "okay";
-				regu_id@0 {
-                    pmic_dev = <&pmic_dev_1 DA9121_ID_BUCK1>;
-                    parent_pmic_dev = <&pmic_dev_0 2 0>;
-				};
-			};
-
-			regu_config_17 {
-                reg_info = <&soc_avdd28_rgb_reg>;
-				status = "okay";
-				regu_id@0 {
-                    pmic_dev = <&pmic_dev_2 SLG51000_ID_LDO1>;
-                    auto_on_info = <6 0 2800000>;
-					auto_off_info = <0 1>;
-				};
-			};
-
-			regu_config_18 {
-                reg_info = <&soc_avdd25_ir_reg>;
-				status = "okay";
-				regu_id@0 {
-                    pmic_dev = <&pmic_dev_2 SLG51000_ID_LDO2>;
-                    auto_on_info = <7 0 2500000>;
-					auto_off_info = <1 1>;
-				};
-			};
-
-			regu_config_19 {
-                reg_info = <&soc_dvdd18_emmc_reg>;
-				status = "okay";
-				regu_id@0 {
-                    pmic_dev = <&pmic_dev_2 SLG51000_ID_LDO3>;
-					parent_pmic_dev = <&pmic_dev_0 7 0>;
-				};
-			};
-
-			regu_config_20 {
-                reg_info = <&soc_dovdd18_rgb_reg>;
-				status = "okay";
-				regu_id@0 {
-                    pmic_dev = <&pmic_dev_2 SLG51000_ID_LDO4>;
-				    auto_on_info = <8 0 1800000>;
-					auto_off_info = <2 1>;
-				};
-			};
-
-			regu_config_21 {
-                reg_info = <&soc_dvdd12_rgb_reg>;
-				status = "okay";
-				regu_id@0 {
-                    pmic_dev = <&pmic_dev_2 SLG51000_ID_LDO5>;
-				    auto_on_info = <9 0 1200000>;
-					auto_off_info = <3 1>;
-				};
-			};
-
-			regu_config_22 {
-                reg_info = <&soc_dvdd12_ir_reg>;
-				status = "okay";
-				regu_id@0 {
-                    pmic_dev = <&pmic_dev_2 SLG51000_ID_LDO6>;
-				    auto_on_info = <10 0 1200000>;
-					auto_off_info = <4 1>;
-				};
-			};
-
-			 regu_config_23 {
-                reg_info = <&soc_dovdd18_ir_reg>;
-				status = "okay";
-				regu_id@0 {
-                    pmic_dev = <&pmic_dev_2 SLG51000_ID_LDO7>;
-				    auto_on_info = <11 0 1800000>;
-					auto_off_info = <5 1>;
-				};
-			};
-		};
-	};
-
 	};
 
 	chosen {

arch/riscv/dts/light-b-product.dts

@@ -1,7 +1,4 @@
 /dts-v1/;
-
-#include <dt-bindings/pmic/light_pmic.h>
-
 / {
 	model = "T-HEAD c910 light";
 	compatible = "thead,c910_light";
@@ -472,362 +469,6 @@
 			lcd-en-gpios    = <&gpio1_porta 9 0>; /* active high */
 			lcd-bias-en-gpios = <&gpio1_porta 10 0>;/* active high */
 		};
-
-		aon {
-		compatible = "thead,light-aon";
-		status = "okay";
-
-		wakeup-by-gpio-on;
-		wakeup-by-rtc-on;
-
-		pd: light-aon-pd {
-			compatible = "thead,light-aon-pd";
-			#power-domain-cells = <1>;
-		};
-
-		light-regu-reg {
-			compatible = "thead,light-dialog-pmic";
-			status = "okay";
-
-
-
-			soc_dvdd18_aon_reg: soc_dvdd18_aon {
-				regulator-name = "soc_dvdd18_aon";
-				regulator-boot-on;
-				regulator-always-on;
-			};
-
-			soc_avdd33_usb3_reg: soc_avdd33_usb3 {
-				regulator-name = "soc_avdd33_usb3";
-				regulator-boot-on;
-				regulator-always-on;
-			};
-
-			soc_dvdd08_aon_reg: soc_dvdd08_aon {
-				regulator-name = "soc_dvdd08_aon";
-				regulator-boot-on;
-				regulator-always-on;
-			};
-
-			soc_apcpu_dvdd_dvddm_reg: soc_apcpu_dvdd_dvddm {
-				regulator-name = "soc_apcpu_dvdd_dvddm";
-				regulator-min-microvolt = <300000>;
-				regulator-max-microvolt = <1570000>;
-				regulator-boot-on;
-				regulator-always-on;
-			};
-
-			soc_dvdd08_ddr_reg: soc_dvdd08_ddr {
-				regulator-name = "soc_dvdd08_ddr";
-				regulator-boot-on;
-				regulator-always-on;
-			};
-
-			soc_vdd_ddr_1v8_reg: soc_vdd_ddr_1v8 {
-				regulator-name = "soc_vdd_ddr_1v8";
-				regulator-boot-on;
-				regulator-always-on;
-			};
-
-			soc_vdd_ddr_1v1_reg: soc_vdd_ddr_1v1 {
-				regulator-name = "soc_vdd_ddr_1v1";
-				regulator-boot-on;
-				regulator-always-on;
-			};
-
-			soc_vdd_ddr_0v6_reg: soc_vdd_ddr_0v6 {
-				regulator-name = "soc_vdd_ddr_0v6";
-				regulator-boot-on;
-				regulator-always-on;
-			};
-
-			soc_dvdd18_ap_reg: soc_dvdd18_ap {
-				regulator-name = "soc_dvdd18_ap";
-				regulator-boot-on;
-				regulator-always-on;
-			};
-
-			soc_dvdd08_ap_reg: soc_dvdd08_ap {
-				regulator-name = "soc_dvdd08_ap";
-				regulator-boot-on;
-				regulator-always-on;
-			};
-
-			soc_avdd08_mipi_hdmi_reg: soc_avdd08_mipi_hdmi {
-				regulator-name = "soc_avdd08_mipi_hdmi";
-				regulator-boot-on;
-				regulator-always-on;
-			};
-
-			soc_avdd18_mipi_hdmi_reg: soc_avdd18_mipi_hdmi {
-				regulator-name = "soc_avdd18_mipi_hdmi";
-				regulator-boot-on;
-				regulator-always-on;
-			};
-
-			soc_dvdd33_emmc_reg: soc_dvdd33_emmc {
-				regulator-name = "soc_dvdd33_emmc";
-				regulator-boot-on;
-				regulator-always-on;
-			};
-
-			soc_dvdd18_emmc_reg: soc_dvdd18_emmc {
-				regulator-name = "soc_vdd18_emmc";
-				regulator-boot-on;
-				regulator-always-on;
-			};
-			soc_dovdd18_scan_reg: soc_dovdd18_scan {
-				regulator-name = "soc_dovdd18_scan";
-				regulator-min-microvolt = <900000>;
-				regulator-max-microvolt = <3600000>;
-				status = "disabled";
-			};
-			soc_vext_2v8_reg: soc_vext_2v8 {
-				regulator-name = "soc_vext_2v8";
-				regulator-boot-on;
-				regulator-always-on;
-				status = "disabled";
-			};
-			soc_dvdd12_scan_reg: soc_dvdd12_scan {
-				regulator-name = "soc_dvdd12_scan";
-				regulator-min-microvolt = <900000>;
-				regulator-max-microvolt = <3600000>;
-				status = "disabled";
-			};
-			soc_avdd28_scan_en_reg: soc_avdd28_scan_en {
-				regulator-name = "soc_avdd28_scan_en";
-				regulator-min-microvolt = <2800000>;
-				regulator-max-microvolt = <2800000>;
-				status = "disabled";
-			};
-			soc_avdd28_rgb_reg: soc_avdd28_rgb {
-				regulator-name = "soc_avdd28_rgb";
-				regulator-min-microvolt = <2200000>;
-				regulator-max-microvolt = <3475000>;
-				regulator-boot-on;
-				regulator-always-on;
-				status = "disabled";
-			};
-			soc_dovdd18_rgb_reg: soc_dovdd18_rgb {
-				regulator-name = "soc_dovdd18_rgb";
-				regulator-min-microvolt = <1200000>;
-				regulator-max-microvolt = <3600000>;
-				regulator-boot-on;
-				regulator-always-on;
-				status = "disabled";
-			};
-			soc_dvdd12_rgb_reg: soc_dvdd12_rgb {
-				regulator-name = "soc_dvdd12_rgb";
-				regulator-min-microvolt = <400000>;
-				regulator-max-microvolt = <1675000>;
-				regulator-boot-on;
-				regulator-always-on;
-				status = "disabled";
-			};
-			soc_avdd25_ir_reg: soc_avdd25_ir {
-				regulator-name = "soc_avdd25_ir";
-				regulator-min-microvolt = <2200000>;
-				regulator-max-microvolt = <3475000>;
-				regulator-boot-on;
-				regulator-always-on;
-				status = "disabled";
-			};
-			soc_dovdd18_ir_reg: soc_dovdd18_ir {
-				regulator-name = "soc_dovdd18_ir";
-				regulator-min-microvolt = <1200000>;
-				regulator-max-microvolt = <3600000>;
-				regulator-boot-on;
-				regulator-always-on;
-				status = "disabled";
-			};
-			soc_dvdd12_ir_reg: soc_dvdd12_ir {
-				regulator-name = "soc_dvdd12_ir";
-				regulator-min-microvolt = <400000>;
-				regulator-max-microvolt = <1675000>;
-				regulator-boot-on;
-				regulator-always-on;
-				status = "disabled";
-			};
-			soc_adc_vref_reg: soc_adc_vref {
-				regulator-name = "soc_adc_vref";
-			};
-			soc_lcd0_en_reg: soc_lcd0_en {
-				regulator-name = "soc_lcd0_en";
-			};
-			soc_vext_1v8_reg: soc_vext_1v8 {
-				regulator-name = "soc_vext_1v8";
-			};
-	   };
-
-	    aon_pmic_config {
-			compatible = "thead,light-pmic-conf";
-			status = "okay";
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			pmic_dev_0: pmic-dev@0 {
-			  pmic-name = "ricoh,rn5t567,v0";
-			  pmic-addr = <0x31>;
-			  pmic_wdt_on;
-			  status = "okay";
-			};
-
-			pmic_dev_1: pmic-dev@1 {
-			  pmic-name = "ricoh,rn5t567,v1";
-			  pmic-addr = <0x32>;
-			  status = "okay";
-			};
-
-			regu_config_0 {
-                reg_info = <&soc_dvdd18_aon_reg>;
-				status = "okay";
-				regu_id@0 {
-                    pmic_dev = <&pmic_dev_0 RICOH567_ID_LDO4>;
-				};
-			};
-
-			regu_config_1 {
-                reg_info = <&soc_avdd33_usb3_reg>;
-				status = "okay";
-				regu_id@0 {
-                    pmic_dev = <&pmic_dev_0 RICOH567_ID_LDO1>;
-				};
-			};
-
-			regu_config_2 {
-                reg_info = <&soc_dvdd08_aon_reg>;
-				status = "okay";
-				regu_id@0 {
-                    pmic_dev = <&pmic_dev_0 RICOH567_ID_LDO3>;
-				};
-			};
-
-			regu_config_3 {
-                reg_info = <&soc_apcpu_dvdd_dvddm_reg>;
-				status = "okay";
-				regu_id@0 {
-                    pmic_dev = <&pmic_dev_0 RICOH567_ID_DC3>;
-					auto_on_info = <2 0 800000>;
-				};
-
-				regu_id@1 {
-                    pmic_dev = <&pmic_dev_0 RICOH567_ID_DC4>;
-					auto_on_info = <3 0 800000>;
-				};
-
-				coupling_info@0 {
-					negative-min;
-                    info = <0 1 5 30>;
-				};
-			};
-
-			regu_config_4 {
-                reg_info = <&soc_dvdd08_ddr_reg>;
-				status = "okay";
-				regu_id@0 {
-                    pmic_dev = <&pmic_dev_0 RICOH567_ID_DC1>;
-				};
-			};
-
-			regu_config_5 {
-                reg_info = <&soc_vdd_ddr_1v8_reg>;
-				status = "okay";
-				regu_id@0 {
-                    pmic_dev = <&pmic_dev_0 RICOH567_ID_LDO2>;
-				};
-			};
-
-		    regu_config_6 {
-                reg_info = <&soc_vdd_ddr_1v1_reg>;
-				status = "okay";
-				regu_id@0 {
-                    pmic_dev = <&pmic_dev_1 RICOH567_ID_DC2>;
-				};
-			};
-
-			regu_config_7 {
-                reg_info = <&soc_vdd_ddr_0v6_reg>;
-				status = "okay";
-				regu_id@0 {
-                    pmic_dev = <&pmic_dev_1 RICOH567_ID_DC1>;
-				};
-			};
-
-			regu_config_8 {
-                reg_info = <&soc_dvdd18_ap_reg>;
-				status = "okay";
-				regu_id@0 {
-                    pmic_dev = <&pmic_dev_1 RICOH567_ID_LDO2>;
-				};
-			};
-
-            regu_config_9 {
-                reg_info = <&soc_avdd08_mipi_hdmi_reg>;
-				status = "okay";
-				regu_id@0 {
-					pmic_dev = <&pmic_dev_1 RICOH567_ID_LDO3>;
-				};
-			};
-
-			regu_config_10 {
-                reg_info = <&soc_avdd18_mipi_hdmi_reg>;
-				status = "okay";
-				regu_id@0 {
-                    pmic_dev = <&pmic_dev_1 RICOH567_ID_LDO4>;
-				};
-			};
-
-			regu_config_11 {
-                reg_info = <&soc_dvdd33_emmc_reg>;
-				status = "okay";
-				regu_id@0 {
-                    pmic_dev = <&pmic_dev_1 RICOH567_ID_LDO1>;
-				};
-			};
-
-			regu_config_12 {
-                reg_info = <&soc_dvdd08_ap_reg>;
-				status = "okay";
-				regu_id@0 {
-                    pmic_dev = <&pmic_dev_1 RICOH567_ID_GPIO3>;
-				};
-			};
-
-			regu_config_13 {
-                reg_info = <&soc_dvdd18_emmc_reg>;
-				status = "okay";
-				regu_id@0 {
-                    pmic_dev = <&pmic_dev_1 RICOH567_ID_DC3>;
-				};
-			};
-
-			regu_config_14 {
-                reg_info = <&soc_adc_vref_reg>;
-				status = "okay";
-				regu_id@0 {
-                    pmic_dev = <&pmic_dev_1 RICOH567_ID_LDO5>;
-				};
-			};
-
-			regu_config_15 {
-                reg_info = <&soc_lcd0_en_reg>;
-				status = "okay";
-				regu_id@0 {
-                    pmic_dev = <&pmic_dev_0 RICOH567_ID_LDO5>;
-					auto_on_info = <0 0 1800000>;
-				};
-			};
-
-			regu_config_16 {
-                reg_info = <&soc_vext_1v8_reg>;
-				status = "okay";
-				regu_id@0 {
-                    pmic_dev = <&pmic_dev_1 RICOH567_ID_DC4>;
-					auto_on_info = <1 0 1800000>;
-				};
-			};
-		};
-	};
 	};
 
 	chosen {

arch/riscv/dts/light-lpi4a-laptop.dts

@@ -0,0 +1,50 @@
+#include "light-lpi4a.dts"
+
+/ {
+};
+
+&i2c1 {
+	clock-frequency = <400000>;
+        status = "okay";
+
+        pcal6408ahk_c: gpio@20 {
+                compatible = "nxp,pca9557";
+                reg = <0x18>;
+                gpio-controller;
+                #gpio-cells = <2>;
+        };
+};
+
+&i2c3 {
+	clock-frequency = <400000>;
+	status = "okay";
+	pcal6408ahk_d: gpio@20 {
+		compatible = "nxp,pca9557";
+		reg = <0x18>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+};
+
+&lcd_backlight {
+	pwms = <&pwm 0 50000>;
+	brightness-levels = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35
+	36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75
+	76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100>;
+	default-brightness-level = <2>;
+};
+
+&panel0 {
+	status = "okay";
+	backlight = <&lcd_backlight>;
+	// 5v power cycle
+	// TODO: move into regulator
+	reset-gpios     = <&pcal6408ahk_c 0 0>; /* active low  */
+	/delete-property/ lcd-en-gpios;
+	/delete-property/ lcd-bias-en-gpios;
+};
+
+&sdhci0 {
+	max-frequency = <35000000>;
+	status = "okay";
+};

arch/riscv/dts/light-lpi4a.dts

@@ -1,7 +1,4 @@
 /dts-v1/;
-
-#include <dt-bindings/pmic/light_pmic.h>
-
 / {
 	model = "T-HEAD c910 light";
 	compatible = "thead,c910_light";
@@ -150,13 +147,6 @@
 
 			#address-cells = <1>;
 			#size-cells = <0>;
-
-			pcal6408ahk_d: gpio@20 {
-				compatible = "nxp,pca9557";
-				reg = <0x18>;
-				gpio-controller;
-				#gpio-cells = <2>;
-			};
 		};
 
 		i2c4: i2c@ffe7f28000{
@@ -167,6 +157,13 @@
 
 			#address-cells = <1>;
 			#size-cells = <0>;
+
+			pcal6408ahk_a: gpio@20 {
+				compatible = "nxp,pca9554";
+				reg = <0x20>;
+				gpio-controller;
+				#gpio-cells = <2>;
+			};
 		};
 
 		i2c5: i2c@fff7f2c000{
@@ -385,20 +382,6 @@
 			reg = <0xff 0xef600000 0x0 0x100>;
 		};
 
-		usb: usb@ffe7040000 {
-			compatible = "snps,dwc3";
-			reg = <0xff 0xe7040000 0x0 0x10000>;
-			interrupts = <68>;
-			reg-shift = <2>;
-			reg-io-width = <4>;
-			maximum-speed = "super-speed";
-			dr_mode = "host";
-			dma-mask = <0xf 0xffffffff>;
-			snps,usb3_lpm_capable;
-			snps,usb_sofitpsync;
-			status = "okay";
-		};
-
 		axiscr {
 			compatible = "thead,axiscr";
 			reg = <0xff 0xff004000 0x0 0x1000>;
@@ -489,376 +472,13 @@
 			default-brightness-level = <7>;
 		};
 
-		jadard_jd9365da {
-			compatible      = "jadard,jd9365da-h3";
+		panel0: dsi_panel0 {
+			compatible      = "ilitek,ili9881c";
 			backlight       = <&lcd_backlight>;
-			reset-gpio     = <&pcal6408ahk_d 7 0>;
-			hsvcc-gpio   = <&pcal6408ahk_d 6 1>;
-			vspn3v3-gpio = <&pcal6408ahk_d 5 1>;
+			reset-gpios     = <&gpio1_porta 5 1>;   /* active low  */
+			lcd-en-gpios    = <&pcal6408ahk_a 2 0>; /* active high */
+			lcd-bias-en-gpios = <&pcal6408ahk_a 4 0>;/* active high */
 		};
-
-		aon {
-		compatible = "thead,light-aon";
-		status = "okay";
-
-		wakeup-by-gpio-on;
-		wakeup-by-rtc-on;
-
-		pd: light-aon-pd {
-			compatible = "thead,light-aon-pd";
-			#power-domain-cells = <1>;
-		};
-
-		light-regu-reg {
-			compatible = "thead,light-dialog-pmic";
-			status = "okay";
-
-
-
-			soc_dvdd18_aon_reg: soc_dvdd18_aon {
-				regulator-name = "soc_dvdd18_aon";
-				regulator-boot-on;
-				regulator-always-on;
-			};
-
-			soc_avdd33_usb3_reg: soc_avdd33_usb3 {
-				regulator-name = "soc_avdd33_usb3";
-				regulator-boot-on;
-				regulator-always-on;
-			};
-
-			soc_dvdd08_aon_reg: soc_dvdd08_aon {
-				regulator-name = "soc_dvdd08_aon";
-				regulator-boot-on;
-				regulator-always-on;
-			};
-
-			soc_apcpu_dvdd_dvddm_reg: soc_apcpu_dvdd_dvddm {
-				regulator-name = "soc_apcpu_dvdd_dvddm";
-				regulator-min-microvolt = <300000>;
-				regulator-max-microvolt = <1570000>;
-				regulator-boot-on;
-				regulator-always-on;
-			};
-
-			soc_dvdd08_ddr_reg: soc_dvdd08_ddr {
-				regulator-name = "soc_dvdd08_ddr";
-				regulator-boot-on;
-				regulator-always-on;
-			};
-
-			soc_vdd_ddr_1v8_reg: soc_vdd_ddr_1v8 {
-				regulator-name = "soc_vdd_ddr_1v8";
-				regulator-boot-on;
-				regulator-always-on;
-			};
-
-			soc_vdd_ddr_1v1_reg: soc_vdd_ddr_1v1 {
-				regulator-name = "soc_vdd_ddr_1v1";
-				regulator-boot-on;
-				regulator-always-on;
-			};
-
-			soc_vdd_ddr_0v6_reg: soc_vdd_ddr_0v6 {
-				regulator-name = "soc_vdd_ddr_0v6";
-				regulator-boot-on;
-				regulator-always-on;
-			};
-
-			soc_dvdd18_ap_reg: soc_dvdd18_ap {
-				regulator-name = "soc_dvdd18_ap";
-				regulator-boot-on;
-				regulator-always-on;
-			};
-
-			soc_dvdd08_ap_reg: soc_dvdd08_ap {
-				regulator-name = "soc_dvdd08_ap";
-				regulator-boot-on;
-				regulator-always-on;
-			};
-
-			soc_avdd08_mipi_hdmi_reg: soc_avdd08_mipi_hdmi {
-				regulator-name = "soc_avdd08_mipi_hdmi";
-				regulator-boot-on;
-				regulator-always-on;
-			};
-
-			soc_avdd18_mipi_hdmi_reg: soc_avdd18_mipi_hdmi {
-				regulator-name = "soc_avdd18_mipi_hdmi";
-				regulator-boot-on;
-				regulator-always-on;
-			};
-
-			soc_dvdd33_emmc_reg: soc_dvdd33_emmc {
-				regulator-name = "soc_dvdd33_emmc";
-				regulator-boot-on;
-				regulator-always-on;
-			};
-
-			soc_dvdd18_emmc_reg: soc_dvdd18_emmc {
-				regulator-name = "soc_vdd18_emmc";
-				regulator-boot-on;
-				regulator-always-on;
-			};
-			soc_dovdd18_scan_reg: soc_dovdd18_scan {
-				regulator-name = "soc_dovdd18_scan";
-				regulator-min-microvolt = <900000>;
-				regulator-max-microvolt = <3600000>;
-			};
-			soc_vext_2v8_reg: soc_vext_2v8 {
-				regulator-name = "soc_vext_2v8";
-				regulator-boot-on;
-				regulator-always-on;
-				status = "disabled";
-			};
-			soc_dvdd12_scan_reg: soc_dvdd12_scan {
-				regulator-name = "soc_dvdd12_scan";
-				regulator-min-microvolt = <900000>;
-				regulator-max-microvolt = <3600000>;
-			};
-			soc_avdd28_scan_en_reg: soc_avdd28_scan_en {
-				regulator-name = "soc_avdd28_scan_en";
-				regulator-min-microvolt = <2800000>;
-				regulator-max-microvolt = <2800000>;
-			};
-			soc_avdd28_rgb_reg: soc_avdd28_rgb {
-				regulator-name = "soc_avdd28_rgb";
-				regulator-min-microvolt = <2200000>;
-				regulator-max-microvolt = <3475000>;
-				regulator-boot-on;
-				regulator-always-on;
-				status = "disabled";
-			};
-			soc_dovdd18_rgb_reg: soc_dovdd18_rgb {
-				regulator-name = "soc_dovdd18_rgb";
-				regulator-min-microvolt = <1200000>;
-				regulator-max-microvolt = <3600000>;
-				regulator-boot-on;
-				regulator-always-on;
-				status = "disabled";
-			};
-			soc_dvdd12_rgb_reg: soc_dvdd12_rgb {
-				regulator-name = "soc_dvdd12_rgb";
-				regulator-min-microvolt = <400000>;
-				regulator-max-microvolt = <1675000>;
-				regulator-boot-on;
-				regulator-always-on;
-				status = "disabled";
-			};
-			soc_avdd25_ir_reg: soc_avdd25_ir {
-				regulator-name = "soc_avdd25_ir";
-				regulator-min-microvolt = <2200000>;
-				regulator-max-microvolt = <3475000>;
-				regulator-boot-on;
-				regulator-always-on;
-				status = "disabled";
-			};
-			soc_dovdd18_ir_reg: soc_dovdd18_ir {
-				regulator-name = "soc_dovdd18_ir";
-				regulator-min-microvolt = <1200000>;
-				regulator-max-microvolt = <3600000>;
-				regulator-boot-on;
-				regulator-always-on;
-				status = "disabled";
-			};
-			soc_dvdd12_ir_reg: soc_dvdd12_ir {
-				regulator-name = "soc_dvdd12_ir";
-				regulator-min-microvolt = <400000>;
-				regulator-max-microvolt = <1675000>;
-				regulator-boot-on;
-				regulator-always-on;
-				status = "disabled";
-			};
-	   };
-
-	    aon_pmic_config {
-			compatible = "thead,light-pmic-conf";
-			status = "okay";
-
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			pmic_dev_0: pmic-dev@0 {
-			  pmic-name = "dialog,da9063,v1";
-			  pmic-addr = <0x5a 0x5b>;
-			  pmic_wdt_on;
-			  status = "okay";
-			};
-
-			pmic_dev_1: pmic-dev@1 {
-			  pmic-name = "dialog,da9121,v1";
-			  pmic-addr = <0x68>;
-			  status = "okay";
-			};
-
-			regu_config_0 {
-                reg_info = <&soc_dvdd18_aon_reg>;
-				status = "okay";
-				regu_id@0 {
-                    pmic_dev = <&pmic_dev_0 DA9063_ID_LDO3>;
-				};
-			};
-
-			regu_config_1 {
-                reg_info = <&soc_avdd33_usb3_reg>;
-				status = "okay";
-				regu_id@0 {
-                    pmic_dev = <&pmic_dev_0 DA9063_ID_LDO9>;
-				};
-			};
-
-			regu_config_2 {
-                reg_info = <&soc_dvdd08_aon_reg>;
-				status = "okay";
-				regu_id@0 {
-                    pmic_dev = <&pmic_dev_0 DA9063_ID_LDO2>;
-				};
-			};
-
-			regu_config_3 {
-                reg_info = <&soc_apcpu_dvdd_dvddm_reg>;
-				status = "okay";
-				regu_id@0 {
-                    pmic_dev = <&pmic_dev_0 DA9063_ID_BCORE1>;
-					auto_on_info = <0 0 800000>;
-				};
-
-				regu_id@1 {
-                    pmic_dev = <&pmic_dev_0 DA9063_ID_BCORE2>;
-					auto_on_info = <1 0 800000>;
-				};
-
-				regu_id@2 {
-                    pmic_dev = <&pmic_dev_0 DA9063_ID_BUCKIO>;
-					auto_on_info = <2 0 800000>;
-				};
-
-				coupling_info@0 {
-					negative-min;
-                    info = <0 2 5 30>;
-				};
-
-				coupling_info@1 {
-					negative-min;
-                    info = <1 2 5 30>;
-				};
-			};
-
-			regu_config_4 {
-                reg_info = <&soc_dvdd08_ddr_reg>;
-				status = "okay";
-				regu_id@0 {
-                    pmic_dev = <&pmic_dev_0 DA9063_ID_BUCKPERI>;
-				};
-			};
-
-			regu_config_5 {
-                reg_info = <&soc_vdd_ddr_1v8_reg>;
-				status = "okay";
-				regu_id@0 {
-                    pmic_dev = <&pmic_dev_0 DA9063_ID_LDO4>;
-				};
-			};
-
-		    regu_config_6 {
-                reg_info = <&soc_vdd_ddr_1v1_reg>;
-				status = "okay";
-				regu_id@0 {
-                    pmic_dev = <&pmic_dev_0 DA9063_ID_BUCKMEM>;
-				};
-			};
-
-			regu_config_7 {
-                reg_info = <&soc_vdd_ddr_0v6_reg>;
-				status = "okay";
-				regu_id@0 {
-                    pmic_dev = <&pmic_dev_0 DA9063_ID_BUCKPRO>;
-				};
-			};
-
-			regu_config_8 {
-                reg_info = <&soc_dvdd18_ap_reg>;
-				status = "okay";
-				regu_id@0 {
-                    pmic_dev = <&pmic_dev_0 DA9063_ID_LDO11>;
-				};
-			};
-
-            regu_config_9 {
-                reg_info = <&soc_avdd08_mipi_hdmi_reg>;
-				status = "okay";
-				regu_id@0 {
-					pmic_dev = <&pmic_dev_0 DA9063_ID_LDO1>;
-				};
-			};
-
-			regu_config_10 {
-                reg_info = <&soc_avdd18_mipi_hdmi_reg>;
-				status = "okay";
-				regu_id@0 {
-                    pmic_dev = <&pmic_dev_0 DA9063_ID_LDO5>;
-				};
-			};
-
-			regu_config_11 {
-                reg_info = <&soc_dvdd33_emmc_reg>;
-				status = "okay";
-				regu_id@0 {
-                    pmic_dev = <&pmic_dev_0 DA9063_ID_LDO10>;
-				};
-			};
-
-			regu_config_12 {
-                reg_info = <&soc_dovdd18_scan_reg>;
-				status = "okay";
-				regu_id@0 {
-                    pmic_dev = <&pmic_dev_0 DA9063_ID_LDO6>;
-					auto_on_info = <3 1 1800000>;
-					auto_off_info = <1 1>;
-				};
-			};
-
-
-			regu_config_13 {
-                reg_info = <&soc_dvdd12_scan_reg>;
-				status = "okay";
-				regu_id@0 {
-                    pmic_dev = <&pmic_dev_0 DA9063_ID_LDO8>;
-					auto_on_info = <4 1 1200000>;
-					auto_off_info = <2 1>;
-				};
-			};
-
-			regu_config_14 {
-                reg_info = <&soc_avdd28_scan_en_reg>;
-				status = "okay";
-				regu_id@0 {
-                    pmic_dev = <&pmic_dev_0 DA9063_ID_LDO7>;
-					auto_on_info = <5 1 2800000>;
-					auto_off_info = <0 1>;
-				};
-			};
-
-			regu_config_15 {
-                reg_info = <&soc_dvdd08_ap_reg>;
-				status = "okay";
-				regu_id@0 {
-                    pmic_dev = <&pmic_dev_1 DA9121_ID_BUCK1>;
-                    parent_pmic_dev = <&pmic_dev_0 2 0>;
-				};
-			};
-
-			regu_config_16 {
-                reg_info = <&soc_dvdd18_emmc_reg>;
-				status = "okay";
-				regu_id@0 {
-                    pmic_dev = <&pmic_dev_0 DA9063_ID_GPIO7>;
-					parent_pmic_dev = <&pmic_dev_0 7 0>;
-				};
-			};
-		};
-	};
-
 	};
 
 	chosen {

arch/riscv/dts/light-milkv-meles.dts

@@ -0,0 +1,288 @@
+/dts-v1/;
+/ {
+	model = "Milk-V Meles";
+	compatible = "milkv,meles", "thead,c910_light";
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	config {
+		select-gpio = <&gpio1_porta 16 0>;
+	};
+
+	memory@0 {
+		device_type = "memory";
+		reg = <0x0 0xc0000000 0x0 0x40000000>;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		timebase-frequency = <3000000>;
+		u-boot,dm-pre-reloc;
+		cpu@0 {
+			device_type = "cpu";
+			reg = <0>;
+			status = "okay";
+			compatible = "riscv";
+			riscv,isa = "rv64imafdcvsu";
+			mmu-type = "riscv,sv39";
+			u-boot,dm-pre-reloc;
+		};
+	};
+
+	soc {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		compatible = "simple-bus";
+		ranges;
+		u-boot,dm-pre-reloc;
+
+		intc: interrupt-controller@ffd8000000 {
+			compatible = "riscv,plic0";
+			reg = <0xff 0xd8000000 0x0 0x04000000>;
+			status = "disabled";
+		};
+
+		dummy_apb: apb-clock {
+			compatible = "fixed-clock";
+			clock-frequency = <62500000>;
+			clock-output-names = "dummy_apb";
+			#clock-cells = <0>;
+			u-boot,dm-pre-reloc;
+		};
+
+		dummy_ahb: ahb-clock {
+			compatible = "fixed-clock";
+			clock-frequency = <250000000>;
+			clock-output-names = "core";
+			#clock-cells = <0>;
+			u-boot,dm-pre-reloc;
+		};
+
+		dummy_spi: spi-clock {
+			compatible = "fixed-clock";
+			clock-frequency = <396000000>;
+			clock-output-names = "dummy_spi";
+			#clock-cells = <0>;
+			u-boot,dm-pre-reloc;
+		};
+
+		dummy_qspi0: qspi0-clock {
+			compatible = "fixed-clock";
+			clock-frequency = <792000000>;
+			clock-output-names = "dummy_qspi0";
+			#clock-cells = <0>;
+			u-boot,dm-pre-reloc;
+		};
+
+		dummy_uart_sclk: uart-sclk-clock {
+			compatible = "fixed-clock";
+			clock-frequency = <100000000>;
+			clock-output-names = "dummy_uart_sclk";
+			#clock-cells = <0>;
+			u-boot,dm-pre-reloc;
+		};
+
+		dummy_i2c_icclk: i2c-icclk-clock {
+			compatible = "fixed-clock";
+			clock-frequency = <50000000>;
+			clock-output-names = "dummy_i2c_icclk";
+			#clock-cells = <0>;
+			u-boot,dm-pre-reloc;
+		};
+
+		dummy_dpu_pixclk: dpu-pix-clock {
+			compatible = "fixed-clock";
+			clock-frequency = <74250000>;
+			clock-output-names = "dummy_dpu_pixclk";
+			#clock-cells = <0>;
+			u-boot,dm-pre-reloc;
+		};
+
+		dummy_dphy_refclk: dphy-ref-clock {
+			compatible = "fixed-clock";
+			clock-frequency = <24000000>;
+			clock-output-names = "dummy_dpu_refclk";
+			#clock-cells = <0>;
+			u-boot,dm-pre-reloc;
+		};
+
+		serial@ffe7014000 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0xff 0xe7014000 0x0 0x400>;
+			clocks = <&dummy_uart_sclk>;
+			clock-frequency = <100000000>;
+			clock-names = "baudclk";
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			u-boot,dm-pre-reloc;
+		};
+
+		gmac0: ethernet@ffe7070000 {
+			compatible = "snps,dwmac";
+			reg = <0xff 0xe7070000 0x0 0x2000>;
+			clocks = <&dummy_apb>;
+			clock-names = "stmmaceth";
+			snps,pbl = <32>;
+			snps,fixed-burst;
+
+			phy-mode = "rgmii-id";
+			phy-handle = <&phy_88E1111_a>;
+			status = "okay";
+			mdio0 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "snps,dwmac-mdio";
+
+				phy_88E1111_a: ethernet-phy@1 {
+					reg = <0x1>;
+				};
+			};
+		};
+
+		emmc: sdhci@ffe7080000 {
+			compatible = "snps,dwcmshc-sdhci";
+			reg = <0xff 0xe7080000 0x0 0x10000>;
+			index = <0x0>;
+			clocks = <&dummy_ahb>;
+			clock-frequency = <198000000>;
+			clock-names = "core";
+			max-frequency = <198000000>;
+			sdhci-caps-mask = <0x0 0x1000000>;
+			mmc-hs400-1_8v;
+			non-removable;
+			no-sdio;
+			no-sd;
+			bus-width = <8>;
+			voltage= "1.8v";
+			pull_up;
+			io_fixed_1v8;
+			fifo-mode;
+			u-boot,dm-pre-reloc;
+		};
+
+		sdhci0: sd@ffe7090000 {
+			compatible = "snps,dwcmshc-sdhci";
+			reg = <0xff 0xe7090000 0x0 0x10000>;
+			index = <0x1>;
+			clocks = <&dummy_ahb>;
+			clock-frequency = <198000000>;
+			max-frequency = <198000000>;
+			sd-uhs-sdr104;
+			pull_up;
+			clock-names = "core";
+			bus-width = <4>;
+			voltage= "3.3v";
+		};
+
+		gpio2: gpio@ffe7f34000 {
+			compatible = "snps,dw-apb-gpio";
+			reg = <0xff 0xe7f34000 0x0 0x1000>;
+			clocks = <&dummy_apb>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			gpio2_porta: gpio-controller@0 {
+				compatible = "snps,dw-apb-gpio-port";
+				gpio-controller;
+				#gpio-cells = <2>;
+				snps,nr-gpios = <32>;
+				reg = <0>;
+			};
+		};
+
+		gpio0: gpio@ffec005000 {
+			compatible = "snps,dw-apb-gpio";
+			reg = <0xff 0xec005000 0x0 0x1000>;
+			clocks = <&dummy_apb>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			gpio0_porta: gpio-controller@0 {
+				compatible = "snps,dw-apb-gpio-port";
+				gpio-controller;
+				#gpio-cells = <2>;
+				snps,nr-gpios = <32>;
+				reg = <0>;
+			};
+		};
+
+		gpio1: gpio@ffec006000 {
+			compatible = "snps,dw-apb-gpio";
+			reg = <0xff 0xec006000 0x0 0x1000>;
+			clocks = <&dummy_apb>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			gpio1_porta: gpio-controller@0 {
+				compatible = "snps,dw-apb-gpio-port";
+				gpio-controller;
+				#gpio-cells = <2>;
+				snps,nr-gpios = <32>;
+				reg = <0>;
+			};
+		};
+
+		axiscr {
+			compatible = "thead,axiscr";
+			reg = <0xff 0xff004000 0x0 0x1000>;
+			lock-read = "okay";
+			lock-write = "okay";
+			#address-cells = <2>;
+			#size-cells = <2>;
+			u-boot,dm-pre-reloc;
+			axiscr0: axisrc@0 {
+				device_type = "axiscr";
+				region = <0x00 0x00000000 0x00 0x80000000>; // 4KB align
+				status = "disabled";
+				#address-cells = <2>;
+				#size-cells = <2>;
+				u-boot,dm-pre-reloc;
+			};
+			axiscr1: axisrc@1 {
+				device_type = "axiscr";
+				region = <0x00 0x80000000 0x00 0x80000000>; // 4KB align
+				status = "disabled";
+				#address-cells = <2>;
+				#size-cells = <2>;
+				u-boot,dm-pre-reloc;
+			};
+			axiscr2: axisrc@2 {
+				device_type = "axiscr";
+				region = <0x01 0x00000000 0x00 0x80000000>; // 4KB align
+				status = "disabled";
+				#address-cells = <2>;
+				#size-cells = <2>;
+				u-boot,dm-pre-reloc;
+			};
+		};
+
+		axiparity {
+			compatible = "thead,axiparity";
+			reg = <0xff 0xff00c000 0x0 0x1000>;
+			lock = "okay";
+			#address-cells = <2>;
+			#size-cells = <2>;
+			u-boot,dm-pre-reloc;
+			axiparity0: axiparity@0 {
+				device_type = "axiparity";
+				region = <0x00 0x00000000 0x01 0x0000000>; // 4KB align
+				status = "disabled";
+				#address-cells = <2>;
+				#size-cells = <2>;
+				u-boot,dm-pre-reloc;
+			};
+			axiparity1: axiparity@1 {
+				device_type = "axiparity";
+				region = <0x01 0x00000000 0x01 0x00000000>; // 4KB align
+				status = "disabled";
+				#address-cells = <2>;
+				#size-cells = <2>;
+				u-boot,dm-pre-reloc;
+			};
+		};
+	};
+
+	chosen {
+		bootargs = "console=ttyS0,115200";
+		stdout-path = "/soc/serial@ffe7014000:115200";
+	};
+};

arch/riscv/include/asm/bitops.h

@@ -90,6 +90,16 @@ static inline int __test_and_clear_bit(int nr, void *addr)
 	return retval;
 }
 
+static inline int test_and_clear_bit(int nr, volatile void * addr)
+{
+	unsigned long flags = 0;
+	int out;
+
+	out = __test_and_clear_bit(nr, addr);
+
+	return out;
+}
+
 static inline int __test_and_change_bit(int nr, void *addr)
 {
 	int mask, retval;

arch/sandbox/dts/Makefile

@@ -6,6 +6,7 @@ else
 dtb-$(CONFIG_SANDBOX) += sandbox.dtb
 endif
 dtb-$(CONFIG_UT_DM) += test.dtb
+dtb-$(CONFIG_CMD_EXTENSION) += overlay0.dtbo overlay1.dtbo
 
 targets += $(dtb-y)
 

arch/sandbox/dts/overlay0.dts

@@ -0,0 +1,9 @@
+/dts-v1/;
+/plugin/;
+
+&{/buttons} {
+	btn3 {
+		gpios = <&gpio_a 5 0>;
+		label = "button3";
+	};
+};

arch/sandbox/dts/overlay1.dts

@@ -0,0 +1,9 @@
+/dts-v1/;
+/plugin/;
+
+&{/buttons} {
+	btn4 {
+		gpios = <&gpio_a 5 0>;
+		label = "button4";
+	};
+};

board/sandbox/sandbox.c

@@ -12,6 +12,9 @@
 #include <os.h>
 #include <asm/test.h>
 #include <asm/u-boot-sandbox.h>
+#include <malloc.h>
+
+#include <extension_board.h>
 
 /*
  * Pointer to initial global data area
@@ -58,6 +61,26 @@ int board_init(void)
 	return 0;
 }
 
+#ifdef CONFIG_CMD_EXTENSION
+int extension_board_scan(struct list_head *extension_list)
+{
+	struct extension *extension;
+	int i;
+
+	for (i = 0; i < 2; i++) {
+		extension = calloc(1, sizeof(struct extension));
+		snprintf(extension->overlay, sizeof(extension->overlay), "overlay%d.dtbo", i);
+		snprintf(extension->name, sizeof(extension->name), "extension board %d", i);
+		snprintf(extension->owner, sizeof(extension->owner), "sandbox");
+		snprintf(extension->version, sizeof(extension->version), "1.1");
+		snprintf(extension->other, sizeof(extension->other), "Fictionnal extension board");
+		list_add_tail(&extension->list, extension_list);
+	}
+
+	return i;
+}
+#endif
+
 #ifdef CONFIG_BOARD_LATE_INIT
 int board_late_init(void)
 {

board/thead/light-c910/Kconfig

@@ -130,13 +130,18 @@ config TARGET_LIGHT_FM_C910_B_POWER
     bool "light fullmask for light-b-power board "
     default n
 
+config TARGET_LIGHT_FM_C910_MILKV_MELES
+    bool "light fullmask for Milk-V Meles board "
+    default n
+
 config SYS_TEXT_BASE
     default 0xc0000000 if RISCV_MMODE
     default 0x00200000 if RISCV_SMODE
 
 config SPL_TEXT_BASE
     hex
-    default 0xffe0000800
+    default 0xffe0000800 if LIGHT_SEC_BOOT_WITH_VERIFY_VAL_A || LIGHT_SEC_BOOT_WITH_VERIFY_VAL_B || LIGHT_SEC_BOOT_WITH_VERIFY_ANT_REF || LIGHT_SEC_BOOT_WITH_VERIFY_LPI4A
+    default 0xffe0000000 if !(LIGHT_SEC_BOOT_WITH_VERIFY_VAL_A || LIGHT_SEC_BOOT_WITH_VERIFY_VAL_B || LIGHT_SEC_BOOT_WITH_VERIFY_ANT_REF || LIGHT_SEC_BOOT_WITH_VERIFY_LPI4A)
 
 config SPL_MAX_SIZE
     hex
@@ -253,11 +258,6 @@ config DDR_DDP
 	  Enabling this will support ddr Dual Die Package configuration.
 	  e.g. to support 8GB ddr device with 17-bit row address (16:0)
 
-config FIXUP_MEMORY_REGION
-	bool "self-adapt to query and fixup memory region"
-	help
-	  Enabling this will support self-adapt to query and fixup memory region
-
 config DDR_H32_MODE
         bool "LPDDR4/4X 32bit mode configuration"
         help

board/thead/light-c910/Makefile

@@ -23,7 +23,6 @@ obj-$(CONFIG_LPDDR) += $(DDR_SRC_PATH)/init_ddr.o
 obj-$(CONFIG_LPDDR) += $(DDR_SRC_PATH)/pinmux.o
 obj-$(CONFIG_LPDDR) += $(DDR_SRC_PATH)/waitfwdone.o
 obj-$(CONFIG_LPDDR) += $(DDR_SRC_PATH)/ddr_common_func.o
-obj-$(CONFIG_LPDDR) += $(DDR_SRC_PATH)/ddr_retention.o
 obj-$(CONFIG_LPDDR) += $(DDR_SRC_PATH)/common_lib.o
 obj-$(CONFIG_LPDDR) += $(DDR_SRC_PATH)/lpddr4_init.o
 ifdef CONFIG_DDR_DBI_OFF
@@ -64,7 +63,6 @@ obj-y += boot.o
 obj-y += sbmeta/sbmeta.o
 ifndef CONFIG_TARGET_LIGHT_FPGA_FM_C910
 obj-$(CONFIG_LPDDR) += $(DDR_SRC_PATH)/ddr_common_func.o
-obj-$(CONFIG_LPDDR) += $(DDR_SRC_PATH)/ddr_retention.o
 obj-$(CONFIG_LPDDR) += $(DDR_SRC_PATH)/common_lib.o
 endif
 

board/thead/light-c910/board.c

@@ -8,16 +8,11 @@
 #include <asm/io.h>
 #include <dwc3-uboot.h>
 #include <usb.h>
-#include <usb/xhci.h>
 #include <cpu_func.h>
+#include <asm/gpio.h>
 #include <abuf.h>
 #include "sec_library.h"
 
-#ifdef CONFIG_LIGHT_AON_CONF
-#include "../../../drivers/misc/light_regu.h"
-#include "dm/device.h"
-#endif
-
 #ifdef CONFIG_USB_DWC3
 static struct dwc3_device dwc3_device_data = {
 	.maximum_speed = USB_SPEED_SUPER,
@@ -34,13 +29,6 @@ int usb_gadget_handle_interrupts(int index)
 int board_usb_init(int index, enum usb_init_type init)
 {
 	dwc3_device_data.base = 0xFFE7040000UL;
-
-	if (init == USB_INIT_DEVICE) {
-		dwc3_device_data.dr_mode = USB_DR_MODE_PERIPHERAL;
-	} else {
-		dwc3_device_data.dr_mode = USB_DR_MODE_HOST;
-	}
-
 	return dwc3_uboot_init(&dwc3_device_data);
 }
 
@@ -50,28 +38,6 @@ int board_usb_cleanup(int index, enum usb_init_type init)
 	return 0;
 }
 
-int xhci_hcd_init(int index, struct xhci_hccr **hccr, struct xhci_hcor **hcor)
-{
-
-
-	int ret = board_usb_init(index, USB_INIT_HOST);
-	if (ret != 0) {
-		puts("Failed to initialize board for USB\n");
-		return ret;
-	}
-
-	*hccr = (struct xhci_hccr *)dwc3_device_data.base;
-	*hcor = (struct xhci_hcor *)(dwc3_device_data.base +
-			HC_LENGTH(xhci_readl(&(*hccr)->cr_capbase)));;
-
-	return ret;
-}
-
-void xhci_hcd_stop(int index)
-{
-	board_usb_cleanup(index, USB_INIT_HOST);
-}
-
 int g_dnl_board_usb_cable_connected(void)
 {
 	return 1;
@@ -79,14 +45,9 @@ int g_dnl_board_usb_cable_connected(void)
 #endif
 
 #ifdef CONFIG_CMD_BOOT_SLAVE
-#ifdef CONFIG_LIGHT_AON_CONF
-#define E902_AON_CONFIG_SIZE 0xC00
-#else
-#define E902_AON_CONFIG_SIZE 0x000
-#endif
 #define E902_SYSREG_START	0xfffff48044
 #define E902_SYSREG_RESET	0xfffff44024
-#define E902_START_ADDRESS	(0xFFEF8000 + E902_AON_CONFIG_SIZE)
+#define E902_START_ADDRESS	0xFFEF8000
 #define C910_E902_START_ADDRESS 0xFFFFEF8000
 #define E902_IOPMP_BASE		0xFFFFC21000
 
@@ -126,120 +87,65 @@ void set_c906_cpu_entry(phys_addr_t entry_h, phys_addr_t entry_l)
 
 void boot_audio(void)
 {
-	writel(0x37, (volatile void *)C906_RESET_REG);
+        writel(0x37, (volatile void *)C906_RESET_REG);
 
-	set_c906_cpu_entry(C906_START_ADDRESS_H, C906_START_ADDRESS_L);
-	flush_cache((uintptr_t)C910_C906_START_ADDRESS, 0x20000);
+        set_c906_cpu_entry(C906_START_ADDRESS_H, C906_START_ADDRESS_L);
+        flush_cache((uintptr_t)C910_C906_START_ADDRESS, 0x20000);
 
-	writel(0x7ffff1f, (volatile void *)C906_CPR_IPCG_ADDRESS);
-	writel((1<<23) | (1<<24), (volatile void *)C906_IOCTL_GPIO_SEL_ADDRESS);
-	writel(0, (volatile void *)C906_IOCTL_AF_SELH_ADDRESS);
+        writel(0x7ffff1f, (volatile void *)C906_CPR_IPCG_ADDRESS);
+        writel((1<<23) | (1<<24), (volatile void *)C906_IOCTL_GPIO_SEL_ADDRESS);
+        writel(0, (volatile void *)C906_IOCTL_AF_SELH_ADDRESS);
 
-	writel(0x3f, (volatile void *)C906_RESET_REG);
+        writel(0x3f, (volatile void *)C906_RESET_REG);
 }
 
-#ifdef CONFIG_LIGHT_AON_CONF
-
-int get_and_set_aon_config_data()
+void boot_aon(void)
 {
-	int ret =0;
-    struct udevice *dev;
-	struct mic_regu_platdata *config_data =NULL;
-
-	ret = uclass_first_device_err(UCLASS_MISC, &dev);
-	if(ret){
-        printf("get light aon config faild %d\n", ret);
-		return ret;
-	}
-
-	config_data = (struct mic_regu_platdata *)(dev->platdata);
-
-    volatile aon_config_t* read_config = (aon_config_t* )C910_E902_START_ADDRESS;
-	if(strncmp(read_config->magic , AON_CONFIG_MAGIC, strlen(AON_CONFIG_MAGIC))) {
-        printf("No aon config magic found in aon bin, please check the aon bin\n");
-		return -1;
-	}
-
-	if(strncmp(read_config->version, AON_CONFIG_VERSION, strlen(AON_CONFIG_VERSION))) {
-       printf("Err aon config version, aon bin is:%s, u-boot is:%s\n", read_config->version, AON_CONFIG_VERSION);
-	   return -1;
-	}
-
-	if(PMIC_MAX_HW_ID_NUM >  read_config->max_hw_id_num) {
-        printf("Invald max hw id num, aon bin support %d , u-boot is %d\n",read_config->max_hw_id_num, PMIC_MAX_HW_ID_NUM);
-		return -1;
-	}
-
-	/*set pmic dev info */
-	int pmic_dev_num =  config_data->pmic_list.pmic_num;
-    int pmic_dev_list_offset   = sizeof(aon_config_t);
-	uintptr_t pmic_dev_start_addr  =  C910_E902_START_ADDRESS + pmic_dev_list_offset;
-
-	int  regu_num            = config_data->regu_id_list.regu_id_num;
-	int  regu_id_list_offset = pmic_dev_list_offset + pmic_dev_num * sizeof(pmic_dev_info_t);
-	uintptr_t regu_start_addr  = C910_E902_START_ADDRESS + regu_id_list_offset;
-    int aon_bin_size  =  regu_id_list_offset + regu_num* sizeof(csi_regu_id_t);
-    if( aon_bin_size > read_config->aon_config_partition_size) {
-         printf("Invalid aon partition size, aon bin support:%d, u-boot is %d\n", read_config->aon_config_partition_size, aon_bin_size);
-		 return -1;
-	}
-
-	printf("pmic_dev_num:%d offset:%d addr:0x%10x\n",pmic_dev_num, pmic_dev_list_offset, pmic_dev_start_addr);
-
-	memcpy(pmic_dev_start_addr, config_data->pmic_list.pmic_list, pmic_dev_num * sizeof(pmic_dev_info_t));
-    printf("regu_num:%d offset:%d addr:0x%10x\n",regu_num,regu_id_list_offset, regu_start_addr);
-
-	memcpy(regu_start_addr, config_data->regu_id_list.regu_id_list, regu_num * sizeof(csi_regu_id_t));
-    
-	read_config->wakeup_flag = config_data->wakeup_flag;
-	read_config->aon_pmic.pmic_dev_num =  pmic_dev_num;
-    read_config->aon_pmic.pmic_dev_list_offset   = pmic_dev_list_offset;
-
-	/*set regu list info*/
-	read_config->aon_pmic.regu_num =  regu_num;
-	read_config->aon_pmic.regu_id_list_offset = regu_id_list_offset;
-
-    flush_cache((uintptr_t)C910_E902_START_ADDRESS, aon_bin_size);
-
-	printf("-->pmic_dev_num:%d offset:%d\n",read_config->aon_pmic.pmic_dev_num, read_config->aon_pmic.pmic_dev_list_offset);
-	printf("-->regu_num:%d offset:%d\n",read_config->aon_pmic.regu_num,read_config->aon_pmic.regu_id_list_offset);
-
-	return 0;
-}
-#endif
-
-int do_boot_aon(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
-{
-#ifdef CONFIG_LIGHT_AON_CONF
-    int ret = 0;
-	ret = get_and_set_aon_config_data();
-	if(ret) {
-        printf("aon config and set faild %d", ret);
-		hang();
-		return ret;
-	}
-#endif
 	writel(0xffffffff, (void *)(E902_IOPMP_BASE + 0xc0));
 	disable_slave_cpu();
 	set_slave_cpu_entry(E902_START_ADDRESS);
 	flush_cache((uintptr_t)C910_E902_START_ADDRESS, 0x10000);
 	enable_slave_cpu();
-	return 0;
 }
 
-U_BOOT_CMD(
-	bootaon, CONFIG_SYS_MAXARGS, 0, do_boot_aon,
-	"Boot aon from memory  ",
-	" "
-);
-
 int do_bootslave(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
 {
+	boot_aon();
+	mdelay(100);
 	boot_audio();
 	return 0;
 }
 #endif
 
+static void light_c910_set_gpio_output_high(void)
+{
+	ofnode node;
+	struct gpio_desc select_gpio;
+
+	printf("%s: trying to set gpio output high\n", __func__);
+
+	node = ofnode_path("/config");
+	if (!ofnode_valid(node)) {
+		printf("%s: no /config node?\n", __func__);
+		return;
+	}
+
+	if (gpio_request_by_name_nodev(node, "select-gpio", 0,
+				       &select_gpio, GPIOD_IS_OUT)) {
+		printf("%s: could not find a /config/select-gpio\n", __func__);
+		return;
+	}
+
+	dm_gpio_set_value(&select_gpio, 1);
+}
+
+int misc_init_r(void)
+{
+	light_c910_set_gpio_output_high();
+
+	return 0;
+}
+
 #ifdef CONFIG_BOARD_RNG_SEED
 const char pre_gen_seed[128] = {211, 134, 226, 116, 1, 13, 224, 196, 88, 213, 188, 219, 128, 41, 231, 228, 129, 123, 173, 234, 219, 79, 152, 154, 169, 27, 183, 166, 52, 21, 118, 7, 155, 89, 124, 156, 102, 92, 96, 190, 49, 28, 154, 177, 69, 129, 149, 199, 253, 66, 177, 216, 146, 73, 114, 59, 100, 41, 225, 152, 62, 88, 160, 217, 177, 28, 117, 23, 120, 213, 213, 169, 242, 111, 90, 55, 241, 239, 254, 238, 50, 175, 198, 196, 248, 56, 255, 92, 97, 224, 245, 160, 56, 149, 121, 233, 177, 239, 0, 41, 196, 214, 210, 182, 69, 44, 238, 54, 27, 236, 36, 77, 156, 234, 17, 148, 34, 16, 241, 132, 241, 230, 36, 41, 123, 157, 19, 44};
 /* Use hardware rng to seed Linux random. */

board/thead/light-c910/clock_config.c

@@ -1146,7 +1146,7 @@ void ap_mipi_dsi1_clk_endisable(bool en)
 	writel(cfg1, (void __iomem *)AP_DPU1_PLL_CFG1);
 }
 
-#if defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_DISCRETE) || defined (CONFIG_TARGET_LIGHT_FM_C910_BEAGLE) || defined (CONFIG_TARGET_LIGHT_FM_C910_B_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_B_POWER) || defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_B) || defined (CONFIG_TARGET_LIGHT_FM_C910_LPI4A)
+#if defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_DISCRETE) || defined (CONFIG_TARGET_LIGHT_FM_C910_BEAGLE) || defined (CONFIG_TARGET_LIGHT_FM_C910_B_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_B_POWER) || defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_B) || defined (CONFIG_TARGET_LIGHT_FM_C910_LPI4A) || defined (CONFIG_TARGET_LIGHT_FM_C910_MILKV_MELES)
 static void ap_multimedia_div_num_set(enum multimedia_div_type type, unsigned int div_num)
 {
 	unsigned long div_reg;
@@ -1220,7 +1220,7 @@ int clk_config(void)
 		return -EINVAL;
 
 	printf("C910 CPU FREQ: %ldMHz\n", rate / 1000000);
-#ifdef PERI_BUS_PLL_FREQ_PRINT
+
 	rate = clk_light_get_rate("ahb2_cpusys_hclk", CLK_DEV_MUX);
 	if (!rate)
 		return -EINVAL;
@@ -1262,7 +1262,6 @@ int clk_config(void)
 		return -EINVAL;
 
 	printf("DPU1 PLL POSTDIV FREQ: %ldMHZ\n", rate / 1000000);
-#endif
 
 #ifdef AUDIO_PLL_FREQ_PRINT
 	rate = clk_light_get_rate("audio_pll_foutpostdiv", CLK_DEV_PLL);
@@ -1305,7 +1304,7 @@ int clk_config(void)
 
 	/* The boards other than the LightA board perform the bus down-speed operation */
 
-#if defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_DISCRETE) || defined (CONFIG_TARGET_LIGHT_FM_C910_BEAGLE) || defined (CONFIG_TARGET_LIGHT_FM_C910_B_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_B_POWER) || defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_B) || defined (CONFIG_TARGET_LIGHT_FM_C910_LPI4A)
+#if defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_DISCRETE) || defined (CONFIG_TARGET_LIGHT_FM_C910_BEAGLE) || defined (CONFIG_TARGET_LIGHT_FM_C910_B_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_B_POWER) || defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_B) || defined (CONFIG_TARGET_LIGHT_FM_C910_LPI4A) || defined (CONFIG_TARGET_LIGHT_FM_C910_MILKV_MELES)
 	ap_multimedia_div_num_set(VI_MIPI_CSI0_DIV, 12); /* Input frquency: 2376MHZ */
 	ap_multimedia_div_num_set(VI_ISP0_CORE_DIV, 12); /* Input frquency: 2376MHZ */
 	ap_multimedia_div_num_set(VI_ISP1_CORE_DIV, 12); /* Input frquency: 2376MHZ */

board/thead/light-c910/ddr.c

@@ -12,17 +12,3 @@ void init_ddr(void)
 {
 	writel(0x1ff << 4, (void *)0xffff005000);
 }
-
-int fixup_ddr_addrmap(unsigned long size)
-{
-	return 0;
-}
-
-int query_ddr_boundary(unsigned long size)
-{
-	return 0;
-}
-unsigned long get_ddr_density(void)
-{
-	return 0x100000000;
-}

board/thead/light-c910/light.c

@@ -11,10 +11,6 @@
 #include <thead/clock_config.h>
 #include <linux/bitops.h>
 #include <asm/arch-thead/light-iopmp.h>
-#include <memalign.h>
-#include <fdt_support.h>
-#include <fs.h>
-#include <asm/global_data.h>
 
 #define SOC_PIN_AP_RIGHT_TOP          (0x0)
 #define SOC_PIN_AP_LEFT_TOP           (0x1)
@@ -34,6 +30,7 @@
 
 #define GMAC0_APB3S_BADDR	0xffec003000
 #define GMAC1_APB3S_BADDR	0xffec004000
+
 static uint64_t apb3s_baddr;
 extern int check_image_board_id(uint8_t *image_data);
 
@@ -634,6 +631,7 @@ static void light_iopin_init(void)
 {
 	return;
 }
+
 #elif defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_A)
 static void light_iopin_init(void)
 {
@@ -813,6 +811,7 @@ static void light_iopin_init(void)
 	light_pin_cfg(GMAC0_RXD3, PIN_SPEED_NORMAL, PIN_PN, 0xF);
 
 }
+
 #elif defined ( CONFIG_TARGET_LIGHT_FM_C910_VAL_B) || defined ( CONFIG_TARGET_LIGHT_FM_C910_B_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_B_POWER)
 static void light_iopin_init(void)
 {
@@ -1218,7 +1217,8 @@ static void light_iopin_init(void)
 	light_pin_cfg(GMAC0_RXD2, PIN_SPEED_NORMAL, PIN_PN, 0xF);
 	light_pin_cfg(GMAC0_RXD3, PIN_SPEED_NORMAL, PIN_PN, 0xF);
 }
-#elif defined   (CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_BEAGLE)
+
+#elif defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_REF)
 static void light_iopin_init(void)
 {
 	/* aon-padmux config */
@@ -1371,7 +1371,7 @@ static void light_iopin_init(void)
 	light_pin_cfg(GPIO2_22,PIN_SPEED_NORMAL,PIN_PN,2);                        ///<WIFI_BT_GPIO2
 	light_pin_cfg(GPIO2_23,PIN_SPEED_NORMAL,PIN_PN,2);                        ///<WIFI_BT_GPIO3
 	light_pin_cfg(GPIO2_24,PIN_SPEED_NORMAL,PIN_PN,2);                        ///<WIFI_BT_RST_N
-	light_pin_cfg(GPIO2_25,PIN_SPEED_NORMAL,PIN_PU,2);                        ///KEY1
+	light_pin_cfg(GPIO2_25,PIN_SPEED_NORMAL,PIN_PN,2);                        ///KEY1
 
 
 	light_pin_mux(SDIO0_WPRTN,3);
@@ -1388,7 +1388,7 @@ static void light_iopin_init(void)
 	light_pin_mux(GPIO3_2,1);
 	light_pin_mux(GPIO3_3,0);
 	light_pin_cfg(GPIO2_30, PIN_SPEED_NORMAL, PIN_PN, 0x2);                 ///NC
-	light_pin_cfg(GPIO2_31, PIN_SPEED_NORMAL, PIN_PN, 0x2);                 ///NC
+	light_pin_cfg(GPIO2_31, PIN_SPEED_NORMAL, PIN_PU, 0x2);                 ///NC
 	light_pin_cfg(GPIO3_0, PIN_SPEED_NORMAL, PIN_PN, 0x2);                  ///NC
 	light_pin_cfg(GPIO3_1, PIN_SPEED_NORMAL, PIN_PN, 0x2);
 	light_pin_cfg(GPIO3_2, PIN_SPEED_NORMAL, PIN_PN, 0xF);
@@ -1438,7 +1438,7 @@ static void light_iopin_init(void)
 	// light_pin_mux(AOGPIO_15,0);
 	light_pin_cfg(AOGPIO_7, PIN_SPEED_NORMAL, PIN_PN, 2);     ///NC
 	light_pin_cfg(AOGPIO_8, PIN_SPEED_NORMAL, PIN_PN, 2);     ///NC
-	light_pin_cfg(AOGPIO_9,PIN_SPEED_NORMAL,PIN_PN,2);
+	// light_pin_cfg(AOGPIO_9,PIN_SPEED_NORMAL,PIN_PN,2);
 	light_pin_cfg(AOGPIO_10, PIN_SPEED_NORMAL, PIN_PN, 2);
 	light_pin_cfg(AOGPIO_11, PIN_SPEED_NORMAL, PIN_PN, 2);
 	light_pin_cfg(AOGPIO_12, PIN_SPEED_NORMAL, PIN_PN, 2);
@@ -1472,8 +1472,6 @@ static void light_iopin_init(void)
 	light_pin_cfg(AUDIO_PA29, PIN_SPEED_NORMAL, PIN_PN, 2);
 	light_pin_mux(AUDIO_PA30, 0);
 	light_pin_cfg(AUDIO_PA30, PIN_SPEED_NORMAL, PIN_PN, 2);
-	#warning "aon set to 3"
-	light_pin_mux(AUDIO_PA30, 3);
 
 	// light_pin_mux(AUDIO_PA9,3);                         ///AUDIO-PA-RESET
 	// light_pin_cfg(AUDIO_PA9,PIN_SPEED_NORMAL,PIN_PN,2);
@@ -1689,20 +1687,576 @@ static void light_iopin_init(void)
 	light_pin_cfg(GMAC0_COL, PIN_SPEED_NORMAL, PIN_PU, 2);
 	light_pin_cfg(GMAC0_CRS, PIN_SPEED_NORMAL, PIN_PU, 2);
 }
-#else
 
+#elif defined (CONFIG_TARGET_LIGHT_FM_C910_BEAGLE)
+static void light_iopin_init(void)
+{	
+	/* P8_03 (Ball:J34) GPIO1_21_MUX*/
+	light_pin_mux(GPIO1_21,3);
+	light_pin_cfg(GPIO1_21, PIN_SPEED_NORMAL, PIN_PN, 2);
+	/* P8_04 (Ball:J35) GPIO1_22_MUX*/
+	light_pin_mux(GPIO1_22,3);
+	light_pin_cfg(GPIO1_22, PIN_SPEED_NORMAL, PIN_PN, 2);
+	/* P8_05 (Ball:K32) GPIO1_23_MUX*/
+	light_pin_mux(GPIO1_23,3);
+	light_pin_cfg(GPIO1_23, PIN_SPEED_NORMAL, PIN_PN, 2);
+	/* P8_06 (Ball:K33) GPIO1_24_MUX*/
+	light_pin_mux(GPIO1_24,3);
+	light_pin_cfg(GPIO1_24, PIN_SPEED_NORMAL, PIN_PN, 2);
+	/* P8_07 (Ball:K34) GPIO1_25_MUX*/
+	light_pin_mux(GPIO1_25,3);
+	light_pin_cfg(GPIO1_25, PIN_SPEED_NORMAL, PIN_PN, 2);
+	/* P8_08 (Ball:K35) GPIO1_26_MUX*/
+	light_pin_mux(GPIO1_26,0);
+	light_pin_cfg(GPIO1_26, PIN_SPEED_NORMAL, PIN_PN, 2);
+	/* P8_09 (Ball:K36) GPIO1_27_MUX*/
+	light_pin_mux(GPIO1_27,0);
+	light_pin_cfg(GPIO1_27, PIN_SPEED_NORMAL, PIN_PN, 2);
+	/* P8_10 (Ball:K37) GPIO1_28_MUX*/
+	light_pin_mux(GPIO1_28,0);
+	light_pin_cfg(GPIO1_28, PIN_SPEED_NORMAL, PIN_PN, 2);
+	/* P8_11 (Ball:L32) GPIO1_29_MUX*/
+	light_pin_mux(GPIO1_29,0);
+	light_pin_cfg(GPIO1_29, PIN_SPEED_NORMAL, PIN_PN, 2);
+	/* P8_12 (Ball:L33) GPIO1_30_MUX*/
+	light_pin_mux(GPIO1_30,0);
+	light_pin_cfg(GPIO1_30, PIN_SPEED_NORMAL, PIN_PN, 2);
+	/* P8_13 (Ball:C6) GPIO3_2_MUX*/
+	light_pin_mux(GPIO3_2,0);
+	light_pin_cfg(GPIO3_2, PIN_SPEED_NORMAL, PIN_PN, 2);
+	/* P8_14 (Ball:E29) CLK_OUT_3_MUX*/
+	light_pin_mux(CLK_OUT_3,3);
+	light_pin_cfg(CLK_OUT_3, PIN_SPEED_NORMAL, PIN_PN, 2);
+	/* P8_15 (Ball:A6) GPIO3_0_MUX*/
+	light_pin_mux(GPIO3_0,0);
+	light_pin_cfg(GPIO3_0, PIN_SPEED_NORMAL, PIN_PN, 2);
+	/* P8_16 (Ball:F34) GPIO0_20_MUX*/
+	light_pin_mux(GPIO0_20,0);
+	light_pin_cfg(GPIO0_20, PIN_SPEED_NORMAL, PIN_PN, 2);
+	/* P8_17 (Ball:B6) GPIO3_1_MUX*/
+	light_pin_mux(GPIO3_1,0);
+	light_pin_cfg(GPIO3_1, PIN_SPEED_NORMAL, PIN_PN, 2);
+	/* P8_18 (Ball:B34) GPIO1_5_MUX*/
+	light_pin_mux(GPIO1_5,0);
+	light_pin_cfg(GPIO1_5, PIN_SPEED_NORMAL, PIN_PN, 2);
+	/* P8_19 (Ball:D6) GPIO3_3_MUX*/
+	light_pin_mux(GPIO3_3,0);
+	light_pin_cfg(GPIO3_3, PIN_SPEED_NORMAL, PIN_PN, 2);
+	/* P8_20 (Ball:C34) GPIO1_6_MUX*/
+	light_pin_mux(GPIO1_6,0);
+	light_pin_cfg(GPIO1_6, PIN_SPEED_NORMAL, PIN_PN, 2);
+	/* P8_21 (Ball:D34) GPIO1_7_MUX*/
+	light_pin_mux(GPIO1_7,0);
+	light_pin_cfg(GPIO1_7, PIN_SPEED_NORMAL, PIN_PN, 2);
+	/* P8_22 (Ball:B35) GPIO1_8_MUX*/
+	light_pin_mux(GPIO1_8,0);
+	light_pin_cfg(GPIO1_8, PIN_SPEED_NORMAL, PIN_PN, 2);
+	/* P8_23 (Ball:A36) GPIO1_9_MUX*/
+	light_pin_mux(GPIO1_9,0);
+	light_pin_cfg(GPIO1_9, PIN_SPEED_NORMAL, PIN_PN, 2);
+	/* P8_24 (Ball:B36) GPIO1_10_MUX*/
+	light_pin_mux(GPIO1_10,0);
+	light_pin_cfg(GPIO1_10, PIN_SPEED_NORMAL, PIN_PN, 2);
+	/* P8_25 (Ball:B37) GPIO1_11_MUX*/
+	light_pin_mux(GPIO1_11,0);
+	light_pin_cfg(GPIO1_11, PIN_SPEED_NORMAL, PIN_PN, 2);
+	/* P8_26 (Ball:C36) GPIO1_12_MUX*/
+	light_pin_mux(GPIO1_12,0);
+	light_pin_cfg(GPIO1_12, PIN_SPEED_NORMAL, PIN_PN, 2);
+	/* P8_27 (Ball:D37) GPIO1_15_MUX*/
+	light_pin_mux(GPIO1_15,0);
+	light_pin_cfg(GPIO1_15, PIN_SPEED_NORMAL, PIN_PN, 2);
+	/* P8_28 (Ball:E34) GPIO1_16_MUX*/
+	light_pin_mux(GPIO1_16,0);
+	light_pin_cfg(GPIO1_16, PIN_SPEED_NORMAL, PIN_PN, 2);
+	/* P8_29 (Ball:D36) GPIO1_14_MUX*/
+	light_pin_mux(GPIO1_14,0);
+	light_pin_cfg(GPIO1_14, PIN_SPEED_NORMAL, PIN_PN, 2);
+	/* P8_30 (Ball:D35) GPIO1_13_MUX*/
+	light_pin_mux(GPIO1_13,0);
+	light_pin_cfg(GPIO1_13, PIN_SPEED_NORMAL, PIN_PN, 2);
+	/* P8_31 (Ball:D33) GPIO1_3_MUX*/
+	light_pin_mux(GPIO1_3,0);
+	light_pin_cfg(GPIO1_3, PIN_SPEED_NORMAL, PIN_PN, 2);
+	/* P8_32 (Ball:A34) GPIO1_4_MUX*/
+	light_pin_mux(GPIO1_4,0);
+	light_pin_cfg(GPIO1_4, PIN_SPEED_NORMAL, PIN_PN, 2);
+	/* P8_33 (Ball:C33) GPIO1_2_MUX*/
+	light_pin_mux(GPIO1_2,0);
+	light_pin_cfg(GPIO1_2, PIN_SPEED_NORMAL, PIN_PN, 2);
+	/* P8_34 (Ball:E32) GPIO1_0_MUX*/
+	light_pin_mux(GPIO1_0,0);
+	light_pin_cfg(GPIO1_0, PIN_SPEED_NORMAL, PIN_PN, 2);
+	/* P8_35 (Ball:A32) GPIO1_1_MUX*/
+	light_pin_mux(GPIO1_1,0);
+	light_pin_cfg(GPIO1_1, PIN_SPEED_NORMAL, PIN_PN, 2);
+	/* P8_36 (Ball:D32) GPIO0_31_MUX*/
+	light_pin_mux(GPIO0_31,0);
+	light_pin_cfg(GPIO0_31, PIN_SPEED_NORMAL, PIN_PN, 2);
+	/* P8_37 (Ball:B32) GPIO0_29_MUX*/
+	light_pin_mux(GPIO0_29,0);
+	light_pin_cfg(GPIO0_29, PIN_SPEED_NORMAL, PIN_PN, 2);
+	/* P8_38 (Ball:C32) GPIO0_30_MUX*/
+	light_pin_mux(GPIO0_30,0);
+	light_pin_cfg(GPIO0_30, PIN_SPEED_NORMAL, PIN_PN, 2);
+	/* P8_39 (Ball:D31) GPIO0_27_MUX*/
+	light_pin_mux(GPIO0_27,0);
+	light_pin_cfg(GPIO0_27, PIN_SPEED_NORMAL, PIN_PN, 2);
+	/* P8_40 (Ball:E31) GPIO0_28_MUX*/
+	light_pin_mux(GPIO0_28,0);
+	light_pin_cfg(GPIO0_28, PIN_SPEED_NORMAL, PIN_PN, 2);
+	/* P8_41 (Ball:F30) GPIO0_25_MUX*/
+	light_pin_mux(GPIO0_25,0);
+	light_pin_cfg(GPIO0_25, PIN_SPEED_NORMAL, PIN_PN, 2);
+	/* P8_42 (Ball:C31) GPIO0_26_MUX*/
+	light_pin_mux(GPIO0_26,0);
+	light_pin_cfg(GPIO0_26, PIN_SPEED_NORMAL, PIN_PN, 2);
+	/* P8_43 (Ball:C30) GPIO0_23_MUX*/
+	light_pin_mux(GPIO0_23,0);
+	light_pin_cfg(GPIO0_23, PIN_SPEED_NORMAL, PIN_PN, 2);
+	/* P8_44 (Ball:D30) GPIO0_24_MUX*/
+	light_pin_mux(GPIO0_24,0);
+	light_pin_cfg(GPIO0_24, PIN_SPEED_NORMAL, PIN_PN, 2);
+	/* P8_45 (Ball:F36) GPIO0_21_MUX*/
+	light_pin_mux(GPIO0_21,0);
+	light_pin_cfg(GPIO0_21, PIN_SPEED_NORMAL, PIN_PN, 2);
+	/* P8_46 (Ball:D29) GPIO0_22_MUX*/
+	light_pin_mux(GPIO0_22,0);
+	light_pin_cfg(GPIO0_22, PIN_SPEED_NORMAL, PIN_PN, 2);
+	/* P9_01 - GND */
+	/* P9_02 - GND */
+	/* P9_03 - VOUT_3V3 */
+	/* P9_04 - VOUT_3V3 */
+	/* P9_05 - VIN */
+	/* P9_06 - VIN */
+	/* P9_07 - VOUT_SYS */
+	/* P9_08 - VOUT_SYS */
+	/* P9_09 - ONKEY# */
+	/* P9_10 - RESET# */
+	/* P9_11 (Ball:M32) UART1_TXD_MUX*/
+	light_pin_mux(UART1_TXD,3);
+	light_pin_cfg(UART1_TXD, PIN_SPEED_NORMAL, PIN_PN, 2);
+	/* P9_12 (Ball:H1) QSPI0_CSN0_MUX*/
+	light_pin_mux(QSPI0_CSN0,3);
+	light_pin_cfg(QSPI0_CSN0, PIN_SPEED_NORMAL, PIN_PN, 2);
+	/* P9_13 (Ball:M33) UART1_RXD_MUX*/
+	light_pin_mux(UART1_RXD,3);
+	light_pin_cfg(UART1_RXD, PIN_SPEED_NORMAL, PIN_PN, 2);
+	/* P9_14 (Ball:K3) QSPI0_D1_MISO_MUX*/
+	light_pin_mux(QSPI0_D1_MISO,3);
+	light_pin_cfg(QSPI0_D1_MISO, PIN_SPEED_NORMAL, PIN_PN, 2);
+	/* P9_15 (Ball:K2) QSPI0_D2_WP_MUX*/
+	light_pin_mux(QSPI0_D2_WP,3);
+	light_pin_cfg(QSPI0_D2_WP, PIN_SPEED_NORMAL, PIN_PN, 2);
+	/* P9_16 (Ball:J3) QSPI0_D0_MOSI_MUX*/
+	light_pin_mux(QSPI0_D0_MOSI,3);
+	light_pin_cfg(QSPI0_D0_MOSI, PIN_SPEED_NORMAL, PIN_PN, 2);
+	/* P9_17 (Ball:H32) QSPI1_CSN0_MUX*/
+	light_pin_mux(QSPI1_CSN0,3);
+	light_pin_cfg(QSPI1_CSN0, PIN_SPEED_NORMAL, PIN_PN, 2);
+	/* P9_18 (Ball:G35) QSPI1_D0_MOSI_MUX*/
+	light_pin_mux(QSPI1_D0_MOSI,3);
+	light_pin_cfg(QSPI1_D0_MOSI, PIN_SPEED_NORMAL, PIN_PN, 2);
+	/* P9_19 (Ball:G4) I2C2_SCL_MUX*/
+	light_pin_mux(I2C2_SCL,3);
+	light_pin_cfg(I2C2_SCL, PIN_SPEED_NORMAL, PIN_PN, 2);
+	/* P9_20 (Ball:G3) I2C2_SDA_MUX*/
+	light_pin_mux(I2C2_SDA,3);
+	light_pin_cfg(I2C2_SDA, PIN_SPEED_NORMAL, PIN_PN, 2);
+	/* P9_21 (Ball:G34) QSPI1_D1_MISO_MUX*/
+	light_pin_mux(QSPI1_D1_MISO,3);
+	light_pin_cfg(QSPI1_D1_MISO, PIN_SPEED_NORMAL, PIN_PN, 2);
+	/* P9_22 (Ball:H34) QSPI1_SCLK_MUX*/
+	light_pin_mux(QSPI1_SCLK,3);
+	light_pin_cfg(QSPI1_SCLK, PIN_SPEED_NORMAL, PIN_PN, 2);
+	/* P9_23 (Ball:K1) QSPI0_D3_HOLD_MUX*/
+	light_pin_mux(QSPI0_D3_HOLD,3);
+	light_pin_cfg(QSPI0_D3_HOLD, PIN_SPEED_NORMAL, PIN_PN, 2);
+	/* P9_24 (Ball:G33) QSPI1_D2_WP_MUX*/
+	light_pin_mux(QSPI1_D2_WP,3);
+	light_pin_cfg(QSPI1_D2_WP, PIN_SPEED_NORMAL, PIN_PN, 2);
+	/* P9_25 (Ball:F5) GPIO2_18_MUX*/
+	light_pin_mux(GPIO2_18,0);
+	light_pin_cfg(GPIO2_18, PIN_SPEED_NORMAL, PIN_PN, 2);
+	/* P9_26 (Ball:F37) QSPI1_D3_HOLD_MUX*/
+	light_pin_mux(QSPI1_D3_HOLD,3);
+	light_pin_cfg(QSPI1_D3_HOLD, PIN_SPEED_NORMAL, PIN_PN, 2);
+	/* P9_27 (Ball:E4) GPIO2_19_MUX*/
+	light_pin_mux(GPIO2_19,0);
+	light_pin_cfg(GPIO2_19, PIN_SPEED_NORMAL, PIN_PN, 2);
+	/* P9_28 (Ball:E3) SPI_CSN_MUX*/
+	light_pin_mux(SPI_CSN,3);
+	light_pin_cfg(SPI_CSN, PIN_SPEED_NORMAL, PIN_PN, 2);
+	/* P9_29 (Ball:F1) SPI_MISO_MUX*/
+	light_pin_mux(SPI_MISO,3);
+	light_pin_cfg(SPI_MISO, PIN_SPEED_NORMAL, PIN_PN, 2);
+	/* P9_30 (Ball:F2) SPI_MOSI_MUX*/
+	light_pin_mux(SPI_MOSI,3);
+	light_pin_cfg(SPI_MOSI, PIN_SPEED_NORMAL, PIN_PN, 2);
+	/* P9_31 (Ball:D3) SPI_SCLK_MUX*/
+	light_pin_mux(SPI_SCLK,3);
+	light_pin_cfg(SPI_SCLK, PIN_SPEED_NORMAL, PIN_PN, 2);
+	/* P9_32 - GND */
+	/* P9_33 - ADC_VIN_CH4 */
+	/* P9_34 - GND */
+	/* P9_35 - ADC_VIN_CH6 */
+	/* P9_36 - ADC_VIN_CH5 */
+	/* P9_37 - ADC_VIN_CH2 */
+	/* P9_38 - ADC_VIN_CH3 */
+	/* P9_39 - ADC_VIN_CH0 */
+	/* P9_39 - ADC_VIN_CH1 */
+	/* P9_41 (Ball:D2) GPIO2_13_MUX*/
+	light_pin_mux(GPIO2_13,0);
+	light_pin_cfg(GPIO2_13, PIN_SPEED_NORMAL, PIN_PN, 2);
+	/* P9_42 (Ball:H3) QSPI0_SCLK_MUX*/
+	light_pin_mux(QSPI0_SCLK,3);
+	light_pin_cfg(QSPI0_SCLK, PIN_SPEED_NORMAL, PIN_PN, 2);
+	/* P9_43 - GND */
+	/* P9_44 - GND */
+	/* P9_45 - GND */
+	/* P9_46 - GND */
+
+	/* RTL8211F-VD-CG */
+
+	light_pin_mux(GMAC0_COL,3);
+	light_pin_mux(GMAC0_CRS,3);
+	light_pin_cfg(GMAC0_COL,PIN_SPEED_NORMAL,PIN_PU,2);
+	light_pin_cfg(GMAC0_CRS,PIN_SPEED_NORMAL,PIN_PU,2);
+
+	light_pin_cfg(GMAC0_TX_CLK, PIN_SPEED_NORMAL, PIN_PN, 0xF);
+	light_pin_cfg(GMAC0_RX_CLK, PIN_SPEED_NORMAL, PIN_PN, 0xF);
+	light_pin_cfg(GMAC0_TXEN, PIN_SPEED_NORMAL, PIN_PN, 0xF);
+	light_pin_cfg(GMAC0_TXD0, PIN_SPEED_NORMAL, PIN_PN, 0xF);
+	light_pin_cfg(GMAC0_TXD1, PIN_SPEED_NORMAL, PIN_PN, 0xF);
+	light_pin_cfg(GMAC0_TXD2, PIN_SPEED_NORMAL, PIN_PN, 0xF);
+	light_pin_cfg(GMAC0_TXD3, PIN_SPEED_NORMAL, PIN_PN, 0xF);
+	light_pin_cfg(GMAC0_RXDV, PIN_SPEED_NORMAL, PIN_PN, 0xF);
+	light_pin_cfg(GMAC0_RXD0, PIN_SPEED_NORMAL, PIN_PN, 0xF);
+	light_pin_cfg(GMAC0_RXD1, PIN_SPEED_NORMAL, PIN_PN, 0xF);
+	light_pin_cfg(GMAC0_RXD2, PIN_SPEED_NORMAL, PIN_PN, 0xF);
+	light_pin_cfg(GMAC0_RXD3, PIN_SPEED_NORMAL, PIN_PN, 0xF);
+
+	/* PMIC */
+	light_pin_cfg(I2C_AON_SCL,PIN_SPEED_NORMAL,PIN_PN,8);
+	light_pin_cfg(I2C_AON_SDA,PIN_SPEED_NORMAL,PIN_PN,8);
+	
+	light_pin_cfg(AOGPIO_14,PIN_SPEED_NORMAL,PIN_PN,2);
+	light_pin_cfg(AOGPIO_15,PIN_SPEED_NORMAL,PIN_PN,2);
+	light_pin_mux(AOGPIO_14,0);
+	light_pin_mux(AOGPIO_15,0);
+	
+	/* Debug port */
+    light_pin_mux(AOGPIO_12,0xF); // TXD
+	light_pin_mux(AOGPIO_13,0xF); // RXD
+
+	/* LEDs */
+	light_pin_mux(AUDIO_PA8,3);
+	light_pin_cfg(AUDIO_PA8,PIN_SPEED_NORMAL,PIN_PN,2);
+	light_pin_mux(AUDIO_PA9,3);
+	light_pin_cfg(AUDIO_PA9,PIN_SPEED_NORMAL,PIN_PN,2);
+	light_pin_mux(AUDIO_PA10,3);
+	light_pin_cfg(AUDIO_PA10,PIN_SPEED_NORMAL,PIN_PU,2);
+	light_pin_mux(AUDIO_PA11,3);
+	light_pin_cfg(AUDIO_PA11,PIN_SPEED_NORMAL,PIN_PU,2);
+	light_pin_mux(AUDIO_PA12,3);
+	light_pin_cfg(AUDIO_PA12,PIN_SPEED_NORMAL,PIN_PU,2);
+	
+	/* Boot select*/
+
+	/* SD boot button*/
+	light_pin_mux(CLK_OUT_0,3);
+	light_pin_cfg(CLK_OUT_0,PIN_SPEED_NORMAL,PIN_PD,2);
+
+	/* NC */
+	light_pin_mux(CLK_OUT_1,3);
+	light_pin_cfg(CLK_OUT_1,PIN_SPEED_NORMAL,PIN_PD,2);
+
+	/* USB boot button*/
+	light_pin_mux(CLK_OUT_2,3);
+	light_pin_cfg(CLK_OUT_2,PIN_SPEED_NORMAL,PIN_PU,2);
+
+
+	/*mikroBUS pinmuxing*/
+
+	/*mikroBUS PWM*/
+	light_pin_mux(QSPI0_CSN1,3); // MB_PWM
+	light_pin_cfg(QSPI0_CSN1,PIN_SPEED_NORMAL,PIN_PN,2);
+	
+	/*mikroBUS GPIO*/
+	light_pin_mux(AUDIO_PA3,3); // MB_RST
+	light_pin_mux(GPIO2_21,0); // MB_INT
+	light_pin_cfg(AUDIO_PA3,PIN_SPEED_NORMAL,PIN_PN,2);
+	light_pin_cfg(GPIO2_21,PIN_SPEED_NORMAL,PIN_PN,2);
+
+	/*mikroBUS UART*/
+	light_pin_mux(UART3_RXD,3); // MB_RXD
+	light_pin_mux(UART3_TXD,3); // MB_TXD
+	light_pin_cfg(UART3_RXD,PIN_SPEED_NORMAL,PIN_PN,2);
+	light_pin_cfg(UART3_TXD,PIN_SPEED_NORMAL,PIN_PN,2);
+	
+	/*mikroBUS SPI*/
+	light_pin_mux(GPIO2_20,3); // MB_CS
+	light_pin_mux(SPI_SCLK,3); // MB_SCK
+	light_pin_mux(SPI_MISO,3); // MB_MOSI
+	light_pin_mux(SPI_MOSI,3); // MB_MISO
+	light_pin_cfg(GPIO2_20,PIN_SPEED_NORMAL,PIN_PN,2);
+	light_pin_cfg(SPI_SCLK,PIN_SPEED_NORMAL,PIN_PN,2);
+	light_pin_cfg(SPI_MISO,PIN_SPEED_NORMAL,PIN_PN,2);
+	light_pin_cfg(SPI_MOSI,PIN_SPEED_NORMAL,PIN_PN,2);
+
+	/*mikroBUS I2C*/
+	light_pin_mux(GPIO0_18,0); // MB_SCL
+	light_pin_mux(GPIO0_19,0); // MB_SDA
+	light_pin_cfg(GPIO0_18,PIN_SPEED_NORMAL,PIN_PN,4);
+	light_pin_cfg(GPIO0_19,PIN_SPEED_NORMAL,PIN_PN,4);
+	
+	/* CSI0 */
+    light_pin_mux(GPIO2_23,0); // CSI0
+	light_pin_cfg(GPIO2_23,PIN_SPEED_NORMAL,PIN_PN,2);
+    light_pin_cfg(I2C1_SCL,PIN_SPEED_NORMAL,PIN_PN,4);
+	light_pin_cfg(I2C1_SDA,PIN_SPEED_NORMAL,PIN_PN,4);
+	
+	/* CSI1 */
+    light_pin_mux(GPIO2_24,0); // CSI1
+	light_pin_cfg(GPIO2_24,PIN_SPEED_NORMAL,PIN_PN,2);
+    light_pin_cfg(I2C3_SCL,PIN_SPEED_NORMAL,PIN_PN,4);
+	light_pin_cfg(I2C3_SDA,PIN_SPEED_NORMAL,PIN_PN,4);
+	 
+    /* EEPROM */
+    light_pin_mux(GPIO2_22,0); // EEPROM
+    light_pin_cfg(GPIO2_22,PIN_SPEED_NORMAL,PIN_PN,2);
+    light_pin_cfg(I2C0_SCL,PIN_SPEED_NORMAL,PIN_PN,4);
+	light_pin_cfg(I2C0_SDA,PIN_SPEED_NORMAL,PIN_PN,4);
+	
+	/* AM6203BM */
+	light_pin_mux(SDIO1_WPRTN,3);
+    light_pin_mux(SDIO1_DETN,3);
+    light_pin_mux(GPIO2_25,0);
+    light_pin_mux(GPIO2_30,0);
+	light_pin_mux(GPIO2_31,0);
+	light_pin_cfg(SDIO1_WPRTN,PIN_SPEED_NORMAL,PIN_PU,2);                   
+	light_pin_cfg(SDIO1_DETN,PIN_SPEED_NORMAL,PIN_PN,2);                    
+    light_pin_cfg(GPIO2_25,PIN_SPEED_NORMAL,PIN_PN,2);
+	light_pin_cfg(GPIO2_30,PIN_SPEED_NORMAL,PIN_PN,2);                 
+	light_pin_cfg(GPIO2_31,PIN_SPEED_NORMAL,PIN_PU,2);
+
+	//BT hardware flow control uart
+    light_pin_cfg(UART4_TXD, PIN_SPEED_NORMAL, PIN_PN, 2);
+	light_pin_cfg(UART4_RXD, PIN_SPEED_NORMAL, PIN_PN, 2);
+	light_pin_cfg(UART4_CTSN, PIN_SPEED_NORMAL, PIN_PN, 2);
+	light_pin_cfg(UART4_RTSN, PIN_SPEED_NORMAL, PIN_PN, 2);
+
+
+}
+
+#elif defined (CONFIG_TARGET_LIGHT_FM_C910_MILKV_MELES)
+static void light_iopin_init(void)
+{
+	/* aon-padmux config */
+	light_pin_cfg(I2C_AON_SCL,PIN_SPEED_NORMAL,PIN_PN,8);
+	light_pin_cfg(I2C_AON_SDA,PIN_SPEED_NORMAL,PIN_PN,8);
+
+	light_pin_mux(AOGPIO_7,3);
+	light_pin_mux(AOGPIO_8,3);
+	light_pin_mux(AOGPIO_9,3);
+	light_pin_mux(AOGPIO_10,3);
+	light_pin_mux(AOGPIO_11,0);
+	light_pin_mux(AOGPIO_12,1);
+	light_pin_mux(AOGPIO_13,1);
+	light_pin_mux(AOGPIO_14,0);
+	light_pin_mux(AOGPIO_15,0);
+	light_pin_cfg(AOGPIO_7,PIN_SPEED_NORMAL,PIN_PN,2);
+	light_pin_cfg(AOGPIO_8,PIN_SPEED_NORMAL,PIN_PN,2);
+	light_pin_cfg(AOGPIO_9,PIN_SPEED_NORMAL,PIN_PN,2);
+	light_pin_cfg(AOGPIO_10,PIN_SPEED_NORMAL,PIN_PN,2);
+	light_pin_cfg(AOGPIO_11,PIN_SPEED_NORMAL,PIN_PN,2);
+	light_pin_cfg(AOGPIO_14,PIN_SPEED_NORMAL,PIN_PN,2);
+	light_pin_cfg(AOGPIO_15,PIN_SPEED_NORMAL,PIN_PN,2);
+
+	light_pin_mux(AUDIO_PA9,3);
+	light_pin_cfg(AUDIO_PA9,PIN_SPEED_NORMAL,PIN_PN,2);
+	light_pin_mux(AUDIO_PA10,3);
+	light_pin_cfg(AUDIO_PA10,PIN_SPEED_NORMAL,PIN_PU,2);
+	light_pin_mux(AUDIO_PA12,3);
+	light_pin_cfg(AUDIO_PA12,PIN_SPEED_NORMAL,PIN_PU,2);
+	light_pin_mux(AUDIO_PA13,0);
+
+	/*ap-padmux on left/top */
+	light_pin_mux(QSPI1_CSN0,3);
+	light_pin_mux(QSPI1_D2_WP,1);
+	light_pin_cfg(QSPI1_CSN0,PIN_SPEED_NORMAL,PIN_PN,8);
+	light_pin_cfg(QSPI1_SCLK,PIN_SPEED_NORMAL,PIN_PN,8);
+	light_pin_cfg(QSPI1_D0_MOSI,PIN_SPEED_NORMAL,PIN_PU,8);
+	light_pin_cfg(QSPI1_D1_MISO,PIN_SPEED_NORMAL,PIN_PU,8);
+	light_pin_cfg(QSPI1_D2_WP,PIN_SPEED_NORMAL,PIN_PN,0xF);
+	light_pin_cfg(QSPI1_D3_HOLD,PIN_SPEED_NORMAL,PIN_PN,8);
+
+	light_pin_mux(I2C0_SCL,0);
+	light_pin_mux(I2C0_SDA,0);
+	light_pin_cfg(I2C0_SCL,PIN_SPEED_NORMAL,PIN_PN,4);
+	light_pin_cfg(I2C0_SDA,PIN_SPEED_NORMAL,PIN_PN,4);
+
+	light_pin_mux(UART3_TXD,1);
+	light_pin_mux(UART3_RXD,1);
+	light_pin_cfg(UART3_TXD,PIN_SPEED_NORMAL,PIN_PN,2);
+	light_pin_cfg(UART3_RXD,PIN_SPEED_NORMAL,PIN_PN,2);
+
+	light_pin_mux(GPIO0_18,1);
+	light_pin_mux(GPIO0_19,1);
+	light_pin_cfg(GPIO0_18,PIN_SPEED_NORMAL,PIN_PN,4);
+	light_pin_cfg(GPIO0_19,PIN_SPEED_NORMAL,PIN_PN,4);
+
+	light_pin_mux(GPIO0_20,0);
+	light_pin_mux(GPIO0_21,0);
+	light_pin_mux(GPIO0_22,1);
+	light_pin_mux(GPIO0_23,1);
+	light_pin_mux(GPIO0_24,1);
+	light_pin_mux(GPIO0_25,1);
+	light_pin_mux(GPIO0_26,1);
+	light_pin_mux(GPIO0_27,0);
+	light_pin_mux(GPIO0_28,0);
+	light_pin_mux(GPIO0_29,0);
+	light_pin_mux(GPIO0_30,0);
+	light_pin_cfg(GPIO0_20,PIN_SPEED_NORMAL,PIN_PN,2);
+	light_pin_cfg(GPIO0_21,PIN_SPEED_NORMAL,PIN_PN,2);
+	light_pin_cfg(GPIO0_27,PIN_SPEED_NORMAL,PIN_PN,2);
+	light_pin_cfg(GPIO0_28,PIN_SPEED_NORMAL,PIN_PN,2);
+	light_pin_cfg(GPIO0_29,PIN_SPEED_NORMAL,PIN_PN,2);
+	light_pin_cfg(GPIO0_30,PIN_SPEED_NORMAL,PIN_PU,2);
+
+	light_pin_mux(GPIO1_0,1);
+	light_pin_mux(GPIO1_1,1);
+	light_pin_mux(GPIO1_2,1);
+	light_pin_mux(GPIO1_3,1);
+	light_pin_mux(GPIO1_4,1);
+	light_pin_mux(GPIO1_9,0);
+	light_pin_mux(GPIO1_10,0);
+	light_pin_mux(GPIO1_11,0);
+	light_pin_mux(GPIO1_12,0);
+	light_pin_mux(GPIO1_13,0);
+	light_pin_mux(GPIO1_14,0);
+	light_pin_mux(GPIO1_15,0);
+	light_pin_mux(GPIO1_16,0);
+	light_pin_mux(GPIO1_21,3);
+	light_pin_mux(GPIO1_22,3);
+	light_pin_mux(GPIO1_23,3);
+	light_pin_mux(GPIO1_24,3);
+	light_pin_mux(GPIO1_25,3);
+	light_pin_cfg(GPIO1_0,PIN_SPEED_NORMAL,PIN_PN,2);
+	light_pin_cfg(GPIO1_1,PIN_SPEED_NORMAL,PIN_PN,2);
+	light_pin_cfg(GPIO1_2,PIN_SPEED_NORMAL,PIN_PN,2);
+	light_pin_cfg(GPIO1_3,PIN_SPEED_NORMAL,PIN_PN,2);
+	light_pin_cfg(GPIO1_4,PIN_SPEED_NORMAL,PIN_PN,2);
+	light_pin_cfg(GPIO1_9,PIN_SPEED_NORMAL,PIN_PN,2);
+	light_pin_cfg(GPIO1_10,PIN_SPEED_NORMAL,PIN_PN,2);
+	light_pin_cfg(GPIO1_11,PIN_SPEED_NORMAL,PIN_PN,2);
+	light_pin_cfg(GPIO1_12,PIN_SPEED_NORMAL,PIN_PN,2);
+	light_pin_cfg(GPIO1_13,PIN_SPEED_NORMAL,PIN_PN,2);
+	light_pin_cfg(GPIO1_14,PIN_SPEED_NORMAL,PIN_PN,2);
+	light_pin_cfg(GPIO1_15,PIN_SPEED_NORMAL,PIN_PN,2);
+	light_pin_cfg(GPIO1_16,PIN_SPEED_NORMAL,PIN_PN,2);
+	light_pin_cfg(GPIO1_21,PIN_SPEED_NORMAL,PIN_PN,2);
+	light_pin_cfg(GPIO1_22,PIN_SPEED_NORMAL,PIN_PN,2);
+	light_pin_cfg(GPIO1_23,PIN_SPEED_NORMAL,PIN_PN,2);
+	light_pin_cfg(GPIO1_24,PIN_SPEED_NORMAL,PIN_PN,2);
+	light_pin_cfg(GPIO1_25,PIN_SPEED_NORMAL,PIN_PN,2);
+	light_pin_cfg(GPIO1_26,PIN_SPEED_NORMAL,PIN_PN,2);
+
+	light_pin_mux(CLK_OUT_0,1);
+	light_pin_mux(CLK_OUT_1,1);
+	light_pin_mux(CLK_OUT_3,1);
+	light_pin_mux(CLK_OUT_2,3);
+	light_pin_cfg(CLK_OUT_2,PIN_SPEED_NORMAL,PIN_PU,2);
+
+	/*ap-pdmux on righ/top*/
+	light_pin_mux(QSPI0_SCLK,3);
+	light_pin_mux(QSPI0_CSN0,3);
+	light_pin_mux(QSPI0_CSN1,3);
+	light_pin_mux(QSPI0_D0_MOSI,3);
+	light_pin_mux(QSPI0_D1_MISO,3);
+	light_pin_mux(QSPI0_D2_WP,3);
+	light_pin_mux(QSPI0_D3_HOLD,3);
+
+	light_pin_cfg(I2C2_SCL,PIN_SPEED_NORMAL,PIN_PN,4);
+	light_pin_cfg(I2C2_SDA,PIN_SPEED_NORMAL,PIN_PN,4);
+
+	light_pin_mux(I2C3_SCL,0);
+	light_pin_mux(I2C3_SDA,0);
+	light_pin_cfg(I2C3_SCL,PIN_SPEED_NORMAL,PIN_PU,4);
+	light_pin_cfg(I2C3_SDA,PIN_SPEED_NORMAL,PIN_PU,4);
+
+	light_pin_mux(SPI_CSN,1);
+	light_pin_cfg(SPI_CSN,PIN_SPEED_NORMAL,PIN_PU,2);
+
+	light_pin_mux(GPIO2_18,0);
+	light_pin_mux(GPIO2_19,0);
+	light_pin_mux(GPIO2_20,0);
+	light_pin_mux(GPIO2_21,0);
+	light_pin_mux(GPIO2_22,0);
+	light_pin_mux(GPIO2_23,0);
+	light_pin_mux(GPIO2_24,0);
+	light_pin_mux(GPIO2_25,0);
+
+	light_pin_cfg(GPIO2_18,PIN_SPEED_NORMAL,PIN_PN,2);
+	light_pin_cfg(GPIO2_19,PIN_SPEED_NORMAL,PIN_PN,2);
+	light_pin_cfg(GPIO2_20,PIN_SPEED_NORMAL,PIN_PN,2);
+	light_pin_cfg(GPIO2_21,PIN_SPEED_NORMAL,PIN_PN,2);
+	light_pin_cfg(GPIO2_22,PIN_SPEED_NORMAL,PIN_PN,2);
+	light_pin_cfg(GPIO2_23,PIN_SPEED_NORMAL,PIN_PN,2);
+	light_pin_cfg(GPIO2_24,PIN_SPEED_NORMAL,PIN_PN,2);
+	light_pin_cfg(GPIO2_25,PIN_SPEED_NORMAL,PIN_PU,2);
+
+	light_pin_mux(SDIO0_WPRTN,3);
+	light_pin_cfg(SDIO0_WPRTN,PIN_SPEED_NORMAL,PIN_PN,2);
+	light_pin_mux(SDIO1_WPRTN,3);
+	light_pin_cfg(SDIO1_WPRTN,PIN_SPEED_NORMAL,PIN_PU,2);
+	light_pin_mux(SDIO1_DETN,3);
+	light_pin_cfg(SDIO1_DETN,PIN_SPEED_NORMAL,PIN_PN,2);
+
+	light_pin_mux(GPIO2_30,0);
+	light_pin_mux(GPIO2_31,0);
+	light_pin_mux(GPIO3_0,0);
+	light_pin_mux(GPIO3_1,0);
+	light_pin_mux(GPIO3_2,1);
+	light_pin_mux(GPIO3_3,1);
+	light_pin_cfg(GPIO2_30, PIN_SPEED_NORMAL, PIN_PN, 0x2);
+	light_pin_cfg(GPIO2_31, PIN_SPEED_NORMAL, PIN_PN, 0x2);
+	light_pin_cfg(GPIO3_0, PIN_SPEED_NORMAL, PIN_PN, 0x2);
+	light_pin_cfg(GPIO3_1, PIN_SPEED_NORMAL, PIN_PN, 0x2);
+	light_pin_cfg(GPIO3_2, PIN_SPEED_NORMAL, PIN_PN, 0xF);
+	light_pin_cfg(GPIO3_3, PIN_SPEED_NORMAL, PIN_PN, 0xF);
+
+	light_pin_mux(GMAC0_COL,3);
+	light_pin_mux(GMAC0_CRS,3);
+	light_pin_cfg(GMAC0_COL,PIN_SPEED_NORMAL,PIN_PU,2);
+	light_pin_cfg(GMAC0_CRS,PIN_SPEED_NORMAL,PIN_PU,2);
+
+	/* GMAC0 pad drive strength configurate to 0xF */
+	light_pin_cfg(GMAC0_TX_CLK, PIN_SPEED_NORMAL, PIN_PN, 0xF);
+	light_pin_cfg(GMAC0_RX_CLK, PIN_SPEED_NORMAL, PIN_PN, 0xF);
+	light_pin_cfg(GMAC0_TXEN, PIN_SPEED_NORMAL, PIN_PN, 0xF);
+	light_pin_cfg(GMAC0_TXD0, PIN_SPEED_NORMAL, PIN_PN, 0xF);
+	light_pin_cfg(GMAC0_TXD1, PIN_SPEED_NORMAL, PIN_PN, 0xF);
+	light_pin_cfg(GMAC0_TXD2, PIN_SPEED_NORMAL, PIN_PN, 0xF);
+	light_pin_cfg(GMAC0_TXD3, PIN_SPEED_NORMAL, PIN_PN, 0xF);
+	light_pin_cfg(GMAC0_RXDV, PIN_SPEED_NORMAL, PIN_PN, 0xF);
+	light_pin_cfg(GMAC0_RXD0, PIN_SPEED_NORMAL, PIN_PN, 0xF);
+	light_pin_cfg(GMAC0_RXD1, PIN_SPEED_NORMAL, PIN_PN, 0xF);
+	light_pin_cfg(GMAC0_RXD2, PIN_SPEED_NORMAL, PIN_PN, 0xF);
+	light_pin_cfg(GMAC0_RXD3, PIN_SPEED_NORMAL, PIN_PN, 0xF);
+}
+
+#else
 static void light_iopin_init(void)
 {
 	light_pin_cfg(I2C_AON_SCL,PIN_SPEED_NORMAL,PIN_PN,4);
 	light_pin_cfg(I2C_AON_SDA,PIN_SPEED_NORMAL,PIN_PN,4);
 	light_pin_cfg(AOGPIO_8,PIN_SPEED_NORMAL,PIN_PN,2);
 	light_pin_cfg(AOGPIO_9,PIN_SPEED_NORMAL,PIN_PN,2);
-	light_pin_cfg(AOGPIO_14, PIN_SPEED_NORMAL, PIN_PN, 2);
 	light_pin_mux(AOGPIO_10,1);
 	light_pin_mux(AOGPIO_11,1);
 	light_pin_mux(AOGPIO_12,1);
 	light_pin_mux(AOGPIO_13,1);
-	light_pin_mux(AOGPIO_14, 0);
 	light_pin_mux(AUDIO_PA30,3);
 
 	/*qspi1 cs0 gpio0-1 pad strength and pin-pull mode*/
@@ -1868,10 +2422,10 @@ int board_init(void)
 
 static void light_usb_boot_check(void)
 {
-	int boot_mode;
-	uchar env_enetaddr[6]={0};
-	uchar env_enet1addr[6]={0};
+	uchar env_enetaddr[6];
+	uchar env_enet1addr[6];
 	int env_ethaddr_flag,env_eth1addr_flag;
+	int boot_mode;
 	int ret = 0;
 
 	boot_mode = readl((void *)SOC_OM_ADDRBASE) & 0x7;
@@ -1887,31 +2441,48 @@ static void light_usb_boot_check(void)
 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
 	env_set("usb_fastboot", "yes");
 #endif
-	/*Get this version ethaddr(mac addr) env,which follows one board, trans to next version env*/
+
+	/* ensure flashing img not to lose mac address on ramfs mode */
 	env_ethaddr_flag  = eth_env_get_enetaddr_by_index("eth", 0, env_enetaddr);
 	env_eth1addr_flag = eth_env_get_enetaddr_by_index("eth", 1, env_enet1addr);
 
 	run_command("env default -a -f", 0);
-	/*If mac addr in last version env  is valid, before save,inherit env mac addr */
-	if(env_ethaddr_flag){
+	if (env_ethaddr_flag)
 		eth_env_set_enetaddr_by_index("eth", 0, env_enetaddr);
-		run_command("printenv ethaddr",0);
-	}else{
-		printf("env ethaddr not exist or invalid\n");
-	}
-
-	if(env_eth1addr_flag){
+	if (env_eth1addr_flag)
 		eth_env_set_enetaddr_by_index("eth", 1, env_enet1addr);
-		run_command("printenv eth1addr",0);
-	}else{
-		printf("env eth1addr not exist or invalid\n");
-	}
-
-	run_command("env save", 0);
+	env_save();
 	run_command("run gpt_partition", 0);
 	run_command("fastboot usb 0", 0);
 }
 
+static void light_mac_vaild_check(void)
+{
+	uchar env_enetaddr[6];
+	uchar env_enet1addr[6];
+	int env_ethaddr_flag,env_eth1addr_flag;
+
+	/*Get this version ethaddr(mac addr) env,which follows one board, trans to next version env*/
+	env_ethaddr_flag  = eth_env_get_enetaddr_by_index("eth", 0, env_enetaddr);
+	env_eth1addr_flag = eth_env_get_enetaddr_by_index("eth", 1, env_enet1addr);
+
+	if (!env_ethaddr_flag || !env_eth1addr_flag) {
+		net_random_ethaddr(env_enetaddr);
+		if (env_enetaddr[5] == (uchar)(0xff)) {
+			env_enetaddr[5] = 0xfe;
+		}
+		eth_env_set_enetaddr_by_index("eth", 0, env_enetaddr);
+		env_enetaddr[5] += 0x01;
+		eth_env_set_enetaddr_by_index("eth", 1, env_enetaddr);
+		printf("Use random addr as fixed mac addr\n");
+		env_save();
+	}
+
+	printf("ethaddr: %s\n", env_get("ethaddr"));
+	printf("eth1addr: %s\n", env_get("eth1addr"));
+
+	return;
+}
 
 int board_late_init(void)
 {
@@ -1922,8 +2493,8 @@ int board_late_init(void)
 	sec_upgrade_thread();
 	sec_firmware_version_dump();
 #endif
-
 	light_usb_boot_check();
+	light_mac_vaild_check();
 	ap_peri_clk_disable();
 	return 0;
 }
@@ -1954,208 +2525,3 @@ U_BOOT_CMD(
 	"check ethaddrs in environment variables is valid",
 	""
 );
-
-
-#define PAGE_SIZE 4096
-#define HIBERNATE_SIG	"S1SUSPEND"
-#define HIBERNATE_SIG2	"S1SUSPEN2" //sign for 2nd time load image
-
-static inline int fdt_disabled_node(void *blob,const char *path)
-{
-	int offset;
-	offset = fdt_path_offset(blob,path);
-	if (offset < 0) {
-		printf("ERROR:failed to find %s node in dtb (ret %d)\n",path,offset);
-		return offset;
-	}
-	return fdt_status_disabled(blob,offset);
-}
-
-static int do_board_check_hibernate(cmd_tbl_t *cmdtp, int flag, int argc,
-		       char * const argv[])
-{
-	int ret;
-	char runcmd[128];
-	ulong addr;
-	void *blob = NULL;
-	ulong mask = 0;
-	int mmc_parts;
-	int resume_part;
-	bool fastresume = 0;
-	#define ON_RET_ERROR(str) if(ret < 0) printf("set node %s status failed %d\n",str,ret)
-	ALLOC_CACHE_ALIGN_BUFFER(u8,swsusp_header_buf,PAGE_SIZE);
-	u8 *header = &swsusp_header_buf[0];
-
-	mmc_parts = env_get_hex("mmcpart",3);
-	resume_part = mmc_parts - 2;
-
-	if(argc >= 4) { // is user pass in ,use that
-		sprintf(runcmd, "read %s %s %s 0 8",
-			argv[1],argv[2],argv[3]);
-		header = (u8 *)simple_strtoul(argv[3],NULL,16);
-		if(argc >= 5)
-			mask = simple_strtoul(argv[4],NULL,16);
-		printf("read swsusp_header to %p,dtb disbale mask 0x%lx\n",header,mask);
-	} else {
-		sprintf(runcmd, "read mmc 0:%d 0x%lx 0 8",
-			resume_part,(unsigned long)&header[0]);
-	}
-
-	ret = run_command(runcmd, 0);
-	if(ret != CMD_RET_SUCCESS)
-		goto failed;
-	if(!memcmp(HIBERNATE_SIG, &header[PAGE_SIZE-10], 10) ||
-		!memcmp(HIBERNATE_SIG2, &header[PAGE_SIZE-10], 10) ) {
-		printf("found sign\n");
-	}
-	else {
-		sprintf(runcmd, "0:%s",env_get("mmcbootpart"));
-		if(file_exists("mmc",runcmd,"no_fastresume",FS_TYPE_EXT)) {
-			printf("do not fastresume\n");
-			goto default_set;
-		}
-
-		sprintf(runcmd, "read mmc 0:%d 0x%lx 0 8",
-			resume_part+1,(unsigned long)&header[0]);
-		ret = run_command(runcmd, 0);
-		if(ret != CMD_RET_SUCCESS)
-			goto failed;
-		if(!memcmp(HIBERNATE_SIG, &header[PAGE_SIZE-10], 10) ||
-			!memcmp(HIBERNATE_SIG2, &header[PAGE_SIZE-10], 10) ) {
-			printf("found fastresume sign\n");
-			resume_part = resume_part+1;
-			fastresume = true;
-		}
-		else {
-			printf(" not find hibernate sign\n");
-			goto default_set;
-		}
-	}
-
-	/*get dtb address*/
-	if(env_get("dtb_addr") == NULL)
-	{
-		printf("Cannot get dtb_addr,check flow !\n");
-		goto failed;
-	}
-	addr = env_get_hex("dtb_addr",0);
-	sprintf(runcmd, "fdt addr 0x%lx", env_get_hex("dtb_addr",0));
-	ret = run_command(runcmd, 0);
-	if(ret != CMD_RET_SUCCESS)
-		goto failed;
-	sprintf(runcmd, "fdt resize");
-	ret = run_command(runcmd, 0);
-	if(ret != CMD_RET_SUCCESS)
-		goto failed;
-
-	/*set unneed devices node disabled for hibernate resume in kernel dtb*/
-	blob = (void *)addr;
-	ret = fdt_status_disabled_by_alias(blob,"i2c0");
-	ON_RET_ERROR("i2c0");
-	ret = fdt_status_disabled_by_alias(blob,"i2c1");
-	ON_RET_ERROR("i2c1");
-	ret = fdt_status_disabled_by_alias(blob,"i2c2");
-	ON_RET_ERROR("i2c2");
-
-	ret = fdt_status_disabled_by_alias(blob,"audio_i2c0");
-	ON_RET_ERROR("audio_i2c0");
-	ret = fdt_status_disabled_by_alias(blob,"audio_i2c1");
-	ON_RET_ERROR("audio_i2c1");
-	ret = fdt_status_disabled_by_alias(blob,"ethernet0");
-	ON_RET_ERROR("ethernet0");
-	ret = fdt_status_disabled_by_alias(blob,"ethernet1");
-	ON_RET_ERROR("ethernet1");
-	ret = fdt_status_disabled_by_alias(blob,"spi0");
-	ON_RET_ERROR("spi0");
-	ret = fdt_status_disabled_by_alias(blob,"spi1");
-	ON_RET_ERROR("spi1");
-	ret = fdt_status_disabled_by_alias(blob,"spi2");
-	ON_RET_ERROR("spi2");
-
-	ret = fdt_disabled_node(blob,"/soc/adc");
-	ON_RET_ERROR("/soc/adc");
-
-	//default mask is 0, need set this node disbaled
-	if(0 == (mask & 0x01)) {
-		ret = fdt_disabled_node(blob,"/soc/light_i2s");
-		ON_RET_ERROR("/soc/light_i2s");
-		ret = fdt_disabled_node(blob,"/soc/audio_i2s0");
-		ON_RET_ERROR("/soc/audio_i2s0");
-		ret = fdt_disabled_node(blob,"/soc/audio_i2s1");
-		ON_RET_ERROR("/soc/audio_i2s1");
-		ret = fdt_disabled_node(blob,"/soc/audio_i2s2");
-		ON_RET_ERROR("/soc/audio_i2s2");
-	}
-	if(0 == (mask & 0x02)) {
-		ret = fdt_disabled_node(blob,"/soc/audio_i2s_8ch_sd0");
-		ON_RET_ERROR("/soc/audio_i2s_8ch_sd0");
-		ret = fdt_disabled_node(blob,"/soc/audio_i2s_8ch_sd1");
-		ON_RET_ERROR("/soc/audio_i2s_8ch_sd1");
-		ret = fdt_disabled_node(blob,"/soc/audio_i2s_8ch_sd2");
-		ON_RET_ERROR("/soc/audio_i2s_8ch_sd2");
-		ret = fdt_disabled_node(blob,"/soc/audio_i2s_8ch_sd3");
-		ON_RET_ERROR("/soc/audio_i2s_8ch_sd3");
-	}
-	/*set resume_bootargs for kernel do fast bootup */
-	sprintf(runcmd,"resume=/dev/mmcblk0p%d notrace noftrace nopty noclkdebug ",resume_part);
-	env_set("resume_bootargs",runcmd);
-
-	return CMD_RET_SUCCESS;
-
-default_set:
-	sprintf(runcmd,"resume=/dev/mmcblk0p%d",resume_part);
-	env_set("resume_bootargs",runcmd);
-	return CMD_RET_SUCCESS;
-
-failed:
-	printf("ERROR:runcmd %s failed!\n",runcmd);
-	sprintf(runcmd,"resume=/dev/mmcblk0p%d",resume_part);
-	env_set("resume_bootargs",runcmd);
-	return CMD_RET_FAILURE;
-}
-
-U_BOOT_CMD(
-	chk_hibernate, 6, 0,	do_board_check_hibernate,
-	"check hibernate image sign,if valid set dtb nodes and bootargs for fast boot resume",
-	" [<interface> <dev[:part]>] [mask]"
-);
-
-#ifdef CONFIG_FIXUP_MEMORY_REGION
-static int do_fixup_memory_region(cmd_tbl_t *cmdtp, int flag, int argc,
-		       char * const argv[])
-{
-	ulong addr;
-	void *blob = NULL;
-	DECLARE_GLOBAL_DATA_PTR;
-	u64 base, size;
-
-	base = gd->ram_base;
-	size = gd->ram_size;
-
-	/*get dtb address*/
-	if(env_get("dtb_addr") == NULL)
-	{
-		printf("Cannot get dtb_addr,check flow !\n");
-		return CMD_RET_FAILURE;
-	}
-	addr = env_get_hex("dtb_addr",0);
-
-	/*set unneed devices node disabled for hibernate resume in kernel dtb*/
-	blob = (void *)addr;
-	fdtdec_setup_mem_size_base_fdt(blob);
-	size -= gd->ram_base;
-
-	if (size != gd->ram_size) {
-		printf("fixup memory region from [0x%09lx ~ 0x%09lx] to [0x%09lx ~ 0x%09lx]\n",
-				gd->ram_base, gd->ram_base+gd->ram_size, gd->ram_base, gd->ram_base+size);
-		gd->ram_size = size;
-		fdt_fixup_memory(blob, gd->ram_base, gd->ram_size);
-	}
-	return CMD_RET_SUCCESS;
-}
-U_BOOT_CMD(
-	fixup_memory_region, 2, 0,	do_fixup_memory_region,
-	"modify linux memory region via gd->ram_size",
-	""
-);
-#endif

board/thead/light-c910/lpddr-regu/ddr_regu.c

@@ -136,7 +136,7 @@ static const struct regulator_t g_apcpu_regu_id_list[] = {
 		REGU_ID_DEF(IIC_IDX_AONIIC,APCPU_REGU_VDDM,0x31,0x39,0,1,800000,600000,3500000,12500,1),
 	},
 };
-#elif defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_A_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_B_REF) || (CONFIG_TARGET_LIGHT_FM_C910_BEAGLE) || defined (CONFIG_TARGET_LIGHT_FM_C910_LPI4A)
+#elif defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_A_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_B_REF) || (CONFIG_TARGET_LIGHT_FM_C910_BEAGLE) || defined (CONFIG_TARGET_LIGHT_FM_C910_LPI4A) || defined (CONFIG_TARGET_LIGHT_FM_C910_MILKV_MELES)
 /**
  * board for ant-ref
  *
@@ -794,7 +794,7 @@ static void light_iopmp_config(void)
 	}
 }
 
-int aon_local_init(void)
+int pmic_ddr_regu_init(void)
 {
 #define AON_PADMUX_BASE (0xfffff4a000)
 	int ret;
@@ -955,7 +955,7 @@ int pmic_reset_apcpu_voltage(void)
 		return ret;
 	return 0;
 }
-#elif defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_A_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_B_REF)|| (CONFIG_TARGET_LIGHT_FM_C910_BEAGLE) || defined (CONFIG_TARGET_LIGHT_FM_C910_LPI4A)
+#elif defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_A_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_B_REF)|| (CONFIG_TARGET_LIGHT_FM_C910_BEAGLE) || defined (CONFIG_TARGET_LIGHT_FM_C910_LPI4A) || defined (CONFIG_TARGET_LIGHT_FM_C910_MILKV_MELES)
 int pmic_reset_apcpu_voltage(void)
 {
 	int                ret = -1;

board/thead/light-c910/lpddr-regu/ddr_regu.h

@@ -9,5 +9,5 @@
 #define __DDR_REGU_H__
 
 int pmic_ddr_set_voltage(void);
-int aon_local_init(void);
+int pmic_ddr_regu_init(void);
 #endif

board/thead/light-c910/lpddr4/include/aonsys_reg_define.h

@@ -1,218 +0,0 @@
-//------------------------------------------------------------
-// DONOT MODIFY THIS FILE
-// generated by JISHENGJU automatically
-//------------------------------------------------------------
-
-#ifndef AONSYS_SYSREG_REG_OFFSET_DEFINE_H
-#define AONSYS_SYSREG_REG_OFFSET_DEFINE_H
-
-#define AONSYS_REG_BASE			0xFFFFF48000
-
-#define REG_AON_CPU_LP_MODE         (AONSYS_REG_BASE + 0x0  )
-#define REG_AON_CHIP_LP_MODE        (AONSYS_REG_BASE + 0x4  )
-#define REG_AON_AO_SERAM_TRN        (AONSYS_REG_BASE + 0x10 )
-#define REG_AON_AO_SERAM_INT        (AONSYS_REG_BASE + 0x14 )
-#define REG_AON_STR_SERAM_TRN       (AONSYS_REG_BASE + 0x18 )
-#define REG_AON_STR_SERAM_INT       (AONSYS_REG_BASE + 0x1c )
-#define REG_AON_STR_INDICATOR_0     (AONSYS_REG_BASE + 0x20 )
-#define REG_AON_STR_INDICATOR_1     (AONSYS_REG_BASE + 0x24 )
-#define REG_AON_STR_INDICATOR_2     (AONSYS_REG_BASE + 0x28 )
-#define REG_AON_STR_INDICATOR_3     (AONSYS_REG_BASE + 0x2c )
-#define REG_AON_PVTC_WR_LOCK        (AONSYS_REG_BASE + 0x30 )
-#define REG_AON_PVTC_TS_ALARM       (AONSYS_REG_BASE + 0x34 )
-#define REG_AON_PVTC_VM_ALARM       (AONSYS_REG_BASE + 0x38 )
-#define REG_AON_PVTC_PD_ALARM       (AONSYS_REG_BASE + 0x3c )
-#define REG_AON_E902_CNT_CLR        (AONSYS_REG_BASE + 0x40 )
-#define REG_AON_E902_RST_ADDR       (AONSYS_REG_BASE + 0x44 )
-#define REG_AON_C906_RST_ADDR_L     (AONSYS_REG_BASE + 0x48 )
-#define REG_AON_C906_RST_ADDR_H     (AONSYS_REG_BASE + 0x4c )
-#define REG_AON_RESERVED_REG_0      (AONSYS_REG_BASE + 0x50 )
-#define REG_AON_RESERVED_REG_1      (AONSYS_REG_BASE + 0x54 )
-#define REG_AON_RESERVED_REG_2      (AONSYS_REG_BASE + 0x58 )
-#define REG_AON_RESERVED_REG_3      (AONSYS_REG_BASE + 0x5c )
-#define REG_AON_AON_AHB_ADEXT       (AONSYS_REG_BASE + 0x60 )
-#define REG_AON_RC_EN               (AONSYS_REG_BASE + 0x70 )
-#define REG_AON_RC_FCAL             (AONSYS_REG_BASE + 0x74 )
-#define REG_AON_RC_MODE             (AONSYS_REG_BASE + 0x78 )
-#define REG_AON_RC_READY            (AONSYS_REG_BASE + 0x7c )
-#define REG_AON_ISO_CFG             (AONSYS_REG_BASE + 0x80 )
-#define REG_AON_OCRAM_ERR           (AONSYS_REG_BASE + 0x90 )
-#define REG_AON_TIMER_LINK          (AONSYS_REG_BASE + 0x100)
-#define REG_AON_PD_REQ              (AONSYS_REG_BASE + 0x110)
-#define REG_AON_PD_ISO_EN_SET       (AONSYS_REG_BASE + 0x114)
-#define REG_AON_PD_ISO_EN_CLR       (AONSYS_REG_BASE + 0x118)
-#define REG_AON_PD_SW_EN_SET        (AONSYS_REG_BASE + 0x11c)
-#define REG_AON_PD_SW_EN_CLR        (AONSYS_REG_BASE + 0x120)
-#define REG_AON_PD_SW_ACK           (AONSYS_REG_BASE + 0x124)
-#define REG_AON_PD_SW_CNT_EN        (AONSYS_REG_BASE + 0x128)
-#define REG_AON_PD_FSM_RST          (AONSYS_REG_BASE + 0x12c)
-#define REG_AON_PD_INT_MASK         (AONSYS_REG_BASE + 0x130)
-#define REG_AON_PD_FSM_STS_L        (AONSYS_REG_BASE + 0x134)
-#define REG_AON_PD_FSM_STS_H        (AONSYS_REG_BASE + 0x138)
-#define REG_AON_PD_INT_STS          (AONSYS_REG_BASE + 0x13c)
-#define REG_AON_PD_INT_CLR          (AONSYS_REG_BASE + 0x140)
-#define REG_AON_PD_BLK0_SW_CNT      (AONSYS_REG_BASE + 0x144)
-#define REG_AON_PD_BLK1_SW_CNT      (AONSYS_REG_BASE + 0x148)
-#define REG_AON_PD_BLK2_SW_CNT      (AONSYS_REG_BASE + 0x14c)
-#define REG_AON_PD_BLK3_SW_CNT      (AONSYS_REG_BASE + 0x150)
-#define REG_AON_PD_BLK4_SW_CNT      (AONSYS_REG_BASE + 0x154)
-#define REG_AON_PD_BLK5_SW_CNT      (AONSYS_REG_BASE + 0x158)
-#define REG_AON_PD_BLK6_SW_CNT      (AONSYS_REG_BASE + 0x15c)
-#define REG_AON_PD_BLK7_SW_CNT      (AONSYS_REG_BASE + 0x160)
-#define REG_AON_PD_BLK8_SW_CNT      (AONSYS_REG_BASE + 0x164)
-#define REG_AON_PD_BLK9_SW_CNT      (AONSYS_REG_BASE + 0x168)
-#define REG_AON_PD_BLK10_SW_CNT     (AONSYS_REG_BASE + 0x16c)
-#define REG_AON_PD_BLK0_INTV_CNT    (AONSYS_REG_BASE + 0x180)
-#define REG_AON_PD_BLK1_INTV_CNT    (AONSYS_REG_BASE + 0x184)
-#define REG_AON_PD_BLK2_INTV_CNT    (AONSYS_REG_BASE + 0x188)
-#define REG_AON_PD_BLK3_INTV_CNT    (AONSYS_REG_BASE + 0x18c)
-#define REG_AON_PD_BLK4_INTV_CNT    (AONSYS_REG_BASE + 0x190)
-#define REG_AON_PD_BLK5_INTV_CNT    (AONSYS_REG_BASE + 0x194)
-#define REG_AON_PD_BLK6_INTV_CNT    (AONSYS_REG_BASE + 0x198)
-#define REG_AON_PD_BLK7_INTV_CNT    (AONSYS_REG_BASE + 0x19c)
-#define REG_AON_PD_BLK8_INTV_CNT    (AONSYS_REG_BASE + 0x1a0)
-#define REG_AON_PD_BLK9_INTV_CNT    (AONSYS_REG_BASE + 0x1a4)
-#define REG_AON_PD_BLK10_INTV_CNT   (AONSYS_REG_BASE + 0x1a8)
-#define REG_AON_AUDIO_PMU_REQ       (AONSYS_REG_BASE + 0x1f8)
-#define REG_AON_AUDIO_PMU_STS       (AONSYS_REG_BASE + 0x1fc)
-#define REG_AON_AUDIO_PMU_INTR      (AONSYS_REG_BASE + 0x204)
-#define REG_AON_PMU_AUDIO_REQ       (AONSYS_REG_BASE + 0x208)
-#define REG_AON_PMU_AUDIO_STS       (AONSYS_REG_BASE + 0x20c)
-#define REG_AON_MEM_LP_MODE         (AONSYS_REG_BASE + 0x210)
-#define REG_AON_C910_DBG_MASK       (AONSYS_REG_BASE + 0x214)
-#define REG_AON_C910_L2CACHE        (AONSYS_REG_BASE + 0x218)
-#define REG_AON_BISR_CTRL           (AONSYS_REG_BASE + 0x220)
-#define REG_AON_EFUSE_PRELOAD_DONE  (AONSYS_REG_BASE + 0x224)
-#define REG_AON_GPIO_RTE            (AONSYS_REG_BASE + 0x228)
-#define REG_AON_PLL_DSKEW_LOCK      (AONSYS_REG_BASE + 0x22c)
-#define REG_AON_SRAM_AXI_CFG        (AONSYS_REG_BASE + 0x230)
-#define REG_AON_SRAM_AXI_ST         (AONSYS_REG_BASE + 0x234)
-#define REG_AON_SRAM_AXI_ERR_STS_0  (AONSYS_REG_BASE + 0x238)
-#define REG_AON_SRAM_AXI_ERR_STS_1  (AONSYS_REG_BASE + 0x23c)
-#define REG_AON_SRAM_AXI_ERR_STS_2  (AONSYS_REG_BASE + 0x240)
-#define REG_AON_SRAM_AXI_ERR_STS_3  (AONSYS_REG_BASE + 0x244)
-#define REG_AON_SRAM_AXI_ERR_STS_4  (AONSYS_REG_BASE + 0x248)
-#define REG_AON_SE_MUX_LOCK         (AONSYS_REG_BASE + 0x24c)
-#define REG_AON_CPU_DBG_DIS_LOCK    (AONSYS_REG_BASE + 0x270)
-#define REG_AON_RESERVED_REG_4      (AONSYS_REG_BASE + 0x300)
-#define REG_AON_RESERVED_REG_5      (AONSYS_REG_BASE + 0x304)
-#define REG_AON_RESERVED_REG_6      (AONSYS_REG_BASE + 0x308)
-#define REG_AON_RESERVED_REG_7      (AONSYS_REG_BASE + 0x30c)
-#define REG_AON_RESERVED_REG_8      (AONSYS_REG_BASE + 0x400)
-#define REG_AON_RESERVED_REG_9      (AONSYS_REG_BASE + 0x404)
-#define REG_AON_RESERVED_REG_10     (AONSYS_REG_BASE + 0x408)
-#define REG_AON_RESERVED_REG_11     (AONSYS_REG_BASE + 0x40c)
-#define REG_AON_RESERVED_REG_12     (AONSYS_REG_BASE + 0x500)
-#define REG_AON_RESERVED_REG_13     (AONSYS_REG_BASE + 0x504)
-#define REG_AON_RESERVED_REG_14     (AONSYS_REG_BASE + 0x508)
-#define REG_AON_RESERVED_REG_15     (AONSYS_REG_BASE + 0x50c)
-#define REG_AON_RESERVED_REG_16     (AONSYS_REG_BASE + 0x600)
-#define REG_AON_RESERVED_REG_17     (AONSYS_REG_BASE + 0x604)
-#define REG_AON_RESERVED_REG_18     (AONSYS_REG_BASE + 0x608)
-#define REG_AON_RESERVED_REG_19     (AONSYS_REG_BASE + 0x60c)
-
-#define CPU_LP_MODE_DFLT_VAL          0x3ff
-#define CHIP_LP_MODE_DFLT_VAL         0x0
-#define AO_SERAM_TRN_DFLT_VAL         0x0
-#define AO_SERAM_INT_DFLT_VAL         0x0
-#define STR_SERAM_TRN_DFLT_VAL        0x0
-#define STR_SERAM_INT_DFLT_VAL        0x0
-#define STR_INDICATOR_0_DFLT_VAL      0x0
-#define STR_INDICATOR_1_DFLT_VAL      0x0
-#define STR_INDICATOR_2_DFLT_VAL      0x0
-#define STR_INDICATOR_3_DFLT_VAL      0x0
-#define PVTC_WR_LOCK_DFLT_VAL         0x0
-#define PVTC_TS_ALARM_DFLT_VAL        0x0
-#define PVTC_VM_ALARM_DFLT_VAL        0x0
-#define PVTC_PD_ALARM_DFLT_VAL        0x0
-#define E902_CNT_CLR_DFLT_VAL         0x0
-#define E902_RST_ADDR_DFLT_VAL        0xffef8000
-#define C906_RST_ADDR_L_DFLT_VAL      0xc0000000
-#define C906_RST_ADDR_H_DFLT_VAL      0xff
-#define RESERVED_REG_0_DFLT_VAL       0x0
-#define RESERVED_REG_1_DFLT_VAL       0x0
-#define RESERVED_REG_2_DFLT_VAL       0x0
-#define RESERVED_REG_3_DFLT_VAL       0x0
-#define AON_AHB_ADEXT_DFLT_VAL        0x0
-#define RC_EN_DFLT_VAL                0x1
-#define RC_FCAL_DFLT_VAL              0x77f
-#define RC_MODE_DFLT_VAL              0x1
-#define RC_READY_DFLT_VAL             0x0
-#define ISO_CFG_DFLT_VAL              0x0
-#define OCRAM_ERR_DFLT_VAL            0x0
-#define TIMER_LINK_DFLT_VAL           0x0
-#define PD_REQ_DFLT_VAL               0x0
-#define PD_ISO_EN_SET_DFLT_VAL        0x0
-#define PD_ISO_EN_CLR_DFLT_VAL        0x0
-#define PD_SW_EN_SET_DFLT_VAL         0x0
-#define PD_SW_EN_CLR_DFLT_VAL         0x0
-#define PD_SW_ACK_DFLT_VAL            0x3fffff
-#define PD_SW_CNT_EN_DFLT_VAL         0x0
-#define PD_FSM_RST_DFLT_VAL           0x0
-#define PD_INT_MASK_DFLT_VAL          0x3fffff
-#define PD_FSM_STS_L_DFLT_VAL         0x0
-#define PD_FSM_STS_H_DFLT_VAL         0x0
-#define PD_INT_STS_DFLT_VAL           0x0
-#define PD_INT_CLR_DFLT_VAL           0x0
-#define PD_BLK0_SW_CNT_DFLT_VAL       0xff00ff
-#define PD_BLK1_SW_CNT_DFLT_VAL       0xff00ff
-#define PD_BLK2_SW_CNT_DFLT_VAL       0xff00ff
-#define PD_BLK3_SW_CNT_DFLT_VAL       0xff00ff
-#define PD_BLK4_SW_CNT_DFLT_VAL       0xff00ff
-#define PD_BLK5_SW_CNT_DFLT_VAL       0xff00ff
-#define PD_BLK6_SW_CNT_DFLT_VAL       0xff00ff
-#define PD_BLK7_SW_CNT_DFLT_VAL       0xff00ff
-#define PD_BLK8_SW_CNT_DFLT_VAL       0xff00ff
-#define PD_BLK9_SW_CNT_DFLT_VAL       0xff00ff
-#define PD_BLK10_SW_CNT_DFLT_VAL      0xff00ff
-#define PD_BLK0_INTV_CNT_DFLT_VAL     0xff0ffff
-#define PD_BLK1_INTV_CNT_DFLT_VAL     0xff0ffff
-#define PD_BLK2_INTV_CNT_DFLT_VAL     0xff0ffff
-#define PD_BLK3_INTV_CNT_DFLT_VAL     0xff0ffff
-#define PD_BLK4_INTV_CNT_DFLT_VAL     0xff0ffff
-#define PD_BLK5_INTV_CNT_DFLT_VAL     0xff0ffff
-#define PD_BLK6_INTV_CNT_DFLT_VAL     0xff0ffff
-#define PD_BLK7_INTV_CNT_DFLT_VAL     0xff0ffff
-#define PD_BLK8_INTV_CNT_DFLT_VAL     0xff0ffff
-#define PD_BLK9_INTV_CNT_DFLT_VAL     0xff0ffff
-#define PD_BLK10_INTV_CNT_DFLT_VAL    0xff0ffff
-#define AUDIO_PMU_REQ_DFLT_VAL        0x0
-#define AUDIO_PMU_STS_DFLT_VAL        0x0
-#define AUDIO_PMU_INTR_DFLT_VAL       0x0
-#define PMU_AUDIO_REQ_DFLT_VAL        0x0
-#define PMU_AUDIO_STS_DFLT_VAL        0x0
-#define MEM_LP_MODE_DFLT_VAL          0x0
-#define C910_DBG_MASK_DFLT_VAL        0x0
-#define C910_L2CACHE_DFLT_VAL         0x0
-#define BISR_CTRL_DFLT_VAL            0x0
-#define EFUSE_PRELOAD_DONE_DFLT_VAL   0x0
-#define GPIO_RTE_DFLT_VAL             0x0
-#define PLL_DSKEW_LOCK_DFLT_VAL       0x0
-#define SRAM_AXI_CFG_DFLT_VAL         0x0
-#define SRAM_AXI_ST_DFLT_VAL          0x0
-#define SRAM_AXI_ERR_STS_0_DFLT_VAL   0x0
-#define SRAM_AXI_ERR_STS_1_DFLT_VAL   0x0
-#define SRAM_AXI_ERR_STS_2_DFLT_VAL   0x0
-#define SRAM_AXI_ERR_STS_3_DFLT_VAL   0x0
-#define SRAM_AXI_ERR_STS_4_DFLT_VAL   0x0
-#define SE_MUX_LOCK_DFLT_VAL          0x0
-#define CPU_DBG_DIS_LOCK_DFLT_VAL     0x0
-#define RESERVED_REG_4_DFLT_VAL       0x0
-#define RESERVED_REG_5_DFLT_VAL       0x0
-#define RESERVED_REG_6_DFLT_VAL       0x0
-#define RESERVED_REG_7_DFLT_VAL       0x0
-#define RESERVED_REG_8_DFLT_VAL       0x0
-#define RESERVED_REG_9_DFLT_VAL       0x0
-#define RESERVED_REG_10_DFLT_VAL      0x0
-#define RESERVED_REG_11_DFLT_VAL      0x0
-#define RESERVED_REG_12_DFLT_VAL      0x0
-#define RESERVED_REG_13_DFLT_VAL      0x0
-#define RESERVED_REG_14_DFLT_VAL      0x0
-#define RESERVED_REG_15_DFLT_VAL      0x0
-#define RESERVED_REG_16_DFLT_VAL      0x0
-#define RESERVED_REG_17_DFLT_VAL      0x0
-#define RESERVED_REG_18_DFLT_VAL      0x0
-#define RESERVED_REG_19_DFLT_VAL      0x0
-
-
-#endif

board/thead/light-c910/lpddr4/include/aonsys_rstget_reg_define.h

@@ -1,90 +0,0 @@
-//------------------------------------------------------------
-// DONOT MODIFY THIS FILE
-// generated by JISHENGJU automatically
-//------------------------------------------------------------
-
-#ifndef AONSYS_RSTGEN_REG_OFFSET_DEFINE_H
-#define AONSYS_RSTGEN_REG_OFFSET_DEFINE_H
-
-#define AONSYS_RSTGEN_REG_BASE	0xFFFFF44000
-
-#define REG_AON_RST_CNT             (AONSYS_RSTGEN_REG_BASE + 0x0   )
-#define REG_AON_SYS_RST_CFG         (AONSYS_RSTGEN_REG_BASE + 0x10  )
-#define REG_AON_RTC_RST_CFG         (AONSYS_RSTGEN_REG_BASE + 0x14  )
-#define REG_AON_AOGPIO_RST_CFG      (AONSYS_RSTGEN_REG_BASE + 0x18  )
-#define REG_AON_AOI2C_RST_CFG       (AONSYS_RSTGEN_REG_BASE + 0x1c  )
-#define REG_AON_PVTC_RST_CFG        (AONSYS_RSTGEN_REG_BASE + 0x20  )
-#define REG_AON_E902_RST_CFG        (AONSYS_RSTGEN_REG_BASE + 0x24  )
-#define REG_AON_AOTIMER_RST_CFG     (AONSYS_RSTGEN_REG_BASE + 0x28  )
-#define REG_AON_AOWDT_RST_CFG       (AONSYS_RSTGEN_REG_BASE + 0x2c  )
-#define REG_AON_APSYS_RST_CFG       (AONSYS_RSTGEN_REG_BASE + 0x30  )
-#define REG_AON_NPUSYS_RST_CFG      (AONSYS_RSTGEN_REG_BASE + 0x34  )
-#define REG_AON_DDRSYS_RST_CFG      (AONSYS_RSTGEN_REG_BASE + 0x38  )
-#define REG_AON_AUDIO_RST_CFG       (AONSYS_RSTGEN_REG_BASE + 0x3c  )
-#define REG_AON_BISR_RST_CFG        (AONSYS_RSTGEN_REG_BASE + 0x50  )
-#define REG_AON_DSP0_RST_CFG        (AONSYS_RSTGEN_REG_BASE + 0x54  )
-#define REG_AON_DSP1_RST_CFG        (AONSYS_RSTGEN_REG_BASE + 0x58  )
-#define REG_AON_GPU_RST_CFG         (AONSYS_RSTGEN_REG_BASE + 0x5c  )
-#define REG_AON_VDEC_RST_CFG        (AONSYS_RSTGEN_REG_BASE + 0x60  )
-#define REG_AON_VENC_RST_CFG        (AONSYS_RSTGEN_REG_BASE + 0x64  )
-#define REG_AON_ADC_RST_CFG         (AONSYS_RSTGEN_REG_BASE + 0x70  )
-#define REG_AON_AUDGPIO_RST_CFG     (AONSYS_RSTGEN_REG_BASE + 0x74  )
-#define REG_AON_AOUART_RST_CFG      (AONSYS_RSTGEN_REG_BASE + 0x78  )
-#define REG_AON_RST_CLR_0           (AONSYS_RSTGEN_REG_BASE + 0x100 )
-#define REG_AON_RST_CLR_1           (AONSYS_RSTGEN_REG_BASE + 0x104 )
-#define REG_AON_RST_CLR_2           (AONSYS_RSTGEN_REG_BASE + 0x108 )
-#define REG_AON_RST_CLR_3           (AONSYS_RSTGEN_REG_BASE + 0x10c )
-#define REG_AON_RST_CLR_4           (AONSYS_RSTGEN_REG_BASE + 0x110 )
-#define REG_AON_RST_STS_0           (AONSYS_RSTGEN_REG_BASE + 0x120 )
-#define REG_AON_RST_STS_1           (AONSYS_RSTGEN_REG_BASE + 0x124 )
-#define REG_AON_RST_STS_2           (AONSYS_RSTGEN_REG_BASE + 0x128 )
-#define REG_AON_RST_STS_3           (AONSYS_RSTGEN_REG_BASE + 0x12c )
-#define REG_AON_RST_STS_4           (AONSYS_RSTGEN_REG_BASE + 0x130 )
-#define REG_AON_RST_REQ_EN_0        (AONSYS_RSTGEN_REG_BASE + 0x140 )
-#define REG_AON_RST_REQ_EN_1        (AONSYS_RSTGEN_REG_BASE + 0x144 )
-#define REG_AON_RST_REQ_EN_2        (AONSYS_RSTGEN_REG_BASE + 0x148 )
-#define REG_AON_RST_REQ_EN_3        (AONSYS_RSTGEN_REG_BASE + 0x14c )
-#define REG_AON_SRAM_AXI_RST_CFG    (AONSYS_RSTGEN_REG_BASE + 0x11f4)
-#define REG_AON_SE_RST_CFG          (AONSYS_RSTGEN_REG_BASE + 0x160 )
-
-#define RST_CNT_DFLT_VAL              0xf0f
-#define SYS_RST_CFG_DFLT_VAL          0x0
-#define RTC_RST_CFG_DFLT_VAL          0x3
-#define AOGPIO_RST_CFG_DFLT_VAL       0x3
-#define AOI2C_RST_CFG_DFLT_VAL        0x1
-#define PVTC_RST_CFG_DFLT_VAL         0x1
-#define E902_RST_CFG_DFLT_VAL         0x2
-#define AOTIMER_RST_CFG_DFLT_VAL      0x3
-#define AOWDT_RST_CFG_DFLT_VAL        0x1
-#define APSYS_RST_CFG_DFLT_VAL        0x1
-#define NPUSYS_RST_CFG_DFLT_VAL       0x1
-#define DDRSYS_RST_CFG_DFLT_VAL       0x1
-#define AUDIO_RST_CFG_DFLT_VAL        0x0
-#define BISR_RST_CFG_DFLT_VAL         0x3
-#define DSP0_RST_CFG_DFLT_VAL         0x1
-#define DSP1_RST_CFG_DFLT_VAL         0x1
-#define GPU_RST_CFG_DFLT_VAL          0x1
-#define VDEC_RST_GEN_RST_CFG_DFLT_VAL         0x1
-#define VENC_RST_CFG_DFLT_VAL         0x1
-#define ADC_RST_CFG_DFLT_VAL          0x1
-#define AUDGPIO_RST_CFG_DFLT_VAL      0x3
-#define AOUART_RST_CFG_DFLT_VAL       0x3
-#define RST_CLR_0_DFLT_VAL            0x0
-#define RST_CLR_1_DFLT_VAL            0x0
-#define RST_CLR_2_DFLT_VAL            0x0
-#define RST_CLR_3_DFLT_VAL            0x0
-#define RST_CLR_4_DFLT_VAL            0x0
-#define RST_STS_0_DFLT_VAL            0x0
-#define RST_STS_1_DFLT_VAL            0x0
-#define RST_STS_2_DFLT_VAL            0x0
-#define RST_STS_3_DFLT_VAL            0x0
-#define RST_STS_4_DFLT_VAL            0x0
-#define RST_REQ_EN_0_DFLT_VAL         0x11100
-#define RST_REQ_EN_1_DFLT_VAL         0xbb000000
-#define RST_REQ_EN_2_DFLT_VAL         0x0
-#define RST_REQ_EN_3_DFLT_VAL         0x0
-#define SRAM_AXI_RST_CFG_DFLT_VAL     0x5f
-#define SE_RST_CFG_DFLT_VAL           0x1
-
-
-#endif

board/thead/light-c910/lpddr4/include/common_lib.h

@@ -7,8 +7,6 @@
 #include "ddr_reg_define.h"
 #include "ddr_sysreg_registers_struct.h"
 #include "ddr_sysreg_registers.h"
-#include "aonsys_reg_define.h"
-#include "aonsys_rstget_reg_define.h"
 #include "define_ddr.h"
 #include "DWC_ddr_umctl2_c_struct.h"
 #include "DWC_ddr_umctl2_header.h"

board/thead/light-c910/lpddr4/include/ddr_common_func.h

@@ -15,9 +15,6 @@ enum DDR_BITWIDTH {
 
 unsigned long get_ddr_density(void);
 enum DDR_TYPE get_ddr_type(void);
-int get_ddr_rank_number(void);
-int get_ddr_freq(void);
-enum DDR_BITWIDTH get_ddr_bitwidth(void);
 void ddr_sysreg_wr(unsigned long int addr,unsigned int wr_data);
 unsigned int ddr_sysreg_rd(unsigned long int addr);
 
@@ -52,8 +49,4 @@ void addrmap(int rank_num, enum DDR_BITWIDTH bits);
 void ctrl_en(enum DDR_BITWIDTH bits);
 void enable_auto_refresh(void);
 void lpddr4_auto_selref(void);
-int lpddr4_query_boundary(enum DDR_TYPE type, int rank_num, int speed,
-                    enum DDR_BITWIDTH bits, unsigned long size);
-int lpddr4_reinit_ctrl(enum DDR_TYPE type, int rank_num, int speed,
-                    enum DDR_BITWIDTH bits, unsigned long size);
 #endif // DDR_COMMON_FUNCE_H

board/thead/light-c910/lpddr4/include/ddr_retention.h

@@ -1,35 +0,0 @@
-#ifndef DDR_RETENTION_H
-#define DDR_RETENTION_H
-
-///data structure to store ddr misc register address, value
-typedef struct Reg_Misc_Addr_Val {
-  uint32_t Address; ///< register address
-  uint32_t Value;   ///< register value
-} Reg_Misc_Addr_Val_t;
-
-///data structure to store register address, value pairs
-typedef struct Reg_Phy_Addr_Val {
-  uint32_t Address; ///< register address
-  uint16_t Value0;   ///< register value phy0
-  uint16_t Value1;   ///< register value phy1
-} Reg_Phy_Addr_Val_t;
-
-/// enumeration of instructions for PhyInit Register Interface
-typedef enum {
-  saveRegs,         ///< save(read) tracked register values
-  restoreRegs,      ///< restore (write) saved register values
-} regInstr;
-
-// typedef struct Reg_Addr_Value {
-//   uint32_t reg_num;
-//   Reg_Addr_Val_t reg[0];
-// } Reg_Addr_Value_t;
-
-typedef struct Ddr_Reg_Config {
-    uint32_t misc_reg_num;
-    uint32_t phy_reg_num;
-} Ddr_Reg_Config_t;
-
-int dwc_ddrphy_phyinit_regInterface(regInstr myRegInstr);
-
-#endif

board/thead/light-c910/lpddr4/src/ddr_common_func.c

@@ -2,14 +2,9 @@
 #include <linux/sizes.h>
 #include "../include/common_lib.h"
 #include "../include/ddr_common_func.h"
-#include "../include/ddr_retention.h"
 
 DDR_SYSREG_REG_SW_REG_S ddr_sysreg;
 
-#ifdef CONFIG_DDR_MSG
-#define DDR_DEBUG(x) printf(x)
-#endif
-
 #ifndef CONFIG_DDR_RANK_SIZE
 #define CONFIG_DDR_RANK_SIZE SZ_4G
 #endif
@@ -39,44 +34,6 @@ enum DDR_TYPE get_ddr_type() {
 #endif // #ifdef CONFIG_LPDDR4X
 }
 
-int get_ddr_rank_number() {
-#ifdef CONFIG_DDR_SINGLE_RANK
-	return 1;
-#elif defined CONFIG_DDR_DUAL_RANK
-	return 2;
-#else
-#ifdef CONFIG_DDR_MSG
-	DDR_DEBUG("unsupported ddr rank type!!!\n");
-#endif
-    return NULL;
-#endif
-}
-
-int get_ddr_freq() {
-#ifdef CONFIG_DDR_4266
-    return 4266;
-#elif CONFIG_DDR_3733
-    return 3733;
-#elif CONFIG_DDR_3200
-    return 3200;
-#elif CONFIG_DDR_2133
-	return 2133;
-#else
-    printf("unsupport lpddr4 freq!!!\n");
-    return -1;
-#endif
-}
-
-enum DDR_BITWIDTH get_ddr_bitwidth() {
-#ifdef CONFIG_DDR_H32_MODE
-    return DDR_BITWIDTH_32;
-#elif CONFIG_DDR_H16_MODE
-    return DDR_BITWIDTH_16;
-#else
-    return DDR_BITWIDTH_64;
-#endif
-}
-
 void ddr_sysreg_wr(unsigned long int addr,unsigned int wr_data) {
   wr(addr+DDR_SYSREG_BADDR,wr_data);
 }
@@ -147,114 +104,75 @@ unsigned int ddr_phy_reg_rd(unsigned long int addr) {
 
   void lp4_mrw(int addr, int wdata,int dch,int rank) {
   DWC_DDR_UMCTL2_C_STRUCT_REG_S umctl2_reg;
-  uint32_t val_t0,val_t1;
   if(dch==0) {
-        while ((rd(MRSTAT) & 0x1) == 0x1);
-        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32 = rd(MRCTRL0);
-        //umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_addr = addr; //do not care for lp4
-        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_rank = rank;//rank0 only
-        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_type = 0;//write
-        wr(MRCTRL0, umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32);
+  umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32 = rd(MRCTRL0);
+  //umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_addr = addr; //do not care for lp4
+  umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_rank = rank;//rank0 only
+  umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_type = 0;//write
+  wr(MRCTRL0,umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32);
 
-        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32 = rd(MRCTRL1);
-        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.mr_data = (addr << 8) | (wdata & 0xFF);
-        wr(MRCTRL1, umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32);
-
-        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32 = rd(MRCTRL1);
-        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.mr_data = (addr << 8) | (wdata & 0xFF);
-        wr(MRCTRL1, umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32);
-
-        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32 = rd(MRCTRL0);
-        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_wr = 1;//trigger wr/rd
-        wr(MRCTRL0, umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32);
-
-        //udelay(10);
-        //delay 5us
-        val_t0=rd(0xFFF4D004);
-        val_t1=rd(0xFFF4D004);
-        while((val_t0-val_t1)<200){val_t1=rd(0xFFF4D004);};
-
-        while ((rd(MRSTAT) & 0x1) == 0x1);
+  umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32 = rd(MRCTRL1);
+  umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.mr_data = (addr<<8) | (wdata&0xFF);
+  wr(MRCTRL1,umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32);
+  
+  umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32 = rd(MRCTRL0);
+  umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_wr = 1;//trigger wr/rd
+  wr(MRCTRL0,umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32);
   }
   else {
-        while ((rd(MRSTAT_DCH1) & 0x1) == 0x1);
-        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32 = rd(MRCTRL0_DCH1);
-        //umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_addr = addr; //do not care for lp4
-        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_rank = rank;//rank0 only
-        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_type = 0;//write
-        wr(MRCTRL0_DCH1, umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32);
+  umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32 = rd(MRCTRL0_DCH1);
+  //umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_addr = addr; //do not care for lp4
+  umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_rank = rank;//rank0 only
+  umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_type = 0;//write
+  wr(MRCTRL0_DCH1,umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32);
 
-        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32 = rd(MRCTRL1_DCH1);
-        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.mr_data = (addr << 8) | (wdata & 0xFF);
-        wr(MRCTRL1_DCH1, umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32);
-
-
-        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32 = rd(MRCTRL1_DCH1);
-        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.mr_data = (addr << 8) | (wdata & 0xFF);
-        wr(MRCTRL1_DCH1, umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32);
-
-        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32 = rd(MRCTRL0_DCH1);
-        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_wr = 1;//trigger wr/rd
-        wr(MRCTRL0_DCH1, umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32);
-
-        //udelay(10);
-        //delay 5us
-        val_t0=rd(0xFFF4D004);
-        val_t1=rd(0xFFF4D004);
-        while((val_t0-val_t1)<200){val_t1=rd(0xFFF4D004);};
-        while ((rd(MRSTAT_DCH1) & 0x1) == 0x1);
+  umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32 = rd(MRCTRL1_DCH1);
+  umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.mr_data = (addr<<8) | (wdata&0xFF);
+  wr(MRCTRL1_DCH1,umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32);
+  
+  umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32 = rd(MRCTRL0_DCH1);
+  umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_wr = 1;//trigger wr/rd
+  wr(MRCTRL0_DCH1,umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32);
+  }
   }
-}
 
   int lp4_mrr(int addr,int dch,int rank) {
   DWC_DDR_UMCTL2_C_STRUCT_REG_S umctl2_reg;
   if(dch==0) {
-        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32 = rd(MRCTRL0);
-        //umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_addr = addr; //do not care for lp4
-        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_rank = rank;//rank0 only
-        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_type = 1;//read
-        wr(MRCTRL0, umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32);
+  umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32 = rd(MRCTRL0);
+  //umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_addr = addr; //do not care for lp4
+  umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_rank = rank;//rank0 only
+  umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_type = 1;//read
+  wr(MRCTRL0,umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32);
 
-        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32 = rd(MRCTRL1);
-        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.mr_data = addr << 8;
-        wr(MRCTRL1, umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32);
+  umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32 = rd(MRCTRL1);
+  umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.mr_data = addr<<8;
+  wr(MRCTRL1,umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32);
+  
+  umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32 = rd(MRCTRL0);
+  umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_wr = 1;//trigger wr/rd
+  wr(MRCTRL0,umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32);
 
-        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32 = rd(MRCTRL1);
-        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.mr_data = addr << 8;
-        wr(MRCTRL1, umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32);
-
-
-        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32 = rd(MRCTRL0);
-        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_wr = 1;//trigger wr/rd
-        wr(MRCTRL0, umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32);
-
-        udelay(20);
-        while ((rd(MRSTAT) & 0x1) == 0x1);
-        return ddr_sysreg_rd(MRR_STS_CH0);
+  umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32 = rd(MRCTRL1);
+  return (umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.mr_data & 0xFF);
   }
   else {
-        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32 = rd(MRCTRL0_DCH1);
-        //umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_addr = addr; //do not care for lp4
-        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_rank = rank;//rank0 only
-        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_type = 1;//read
-        wr(MRCTRL0_DCH1, umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32);
+  umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32 = rd(MRCTRL0_DCH1);
+  //umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_addr = addr; //do not care for lp4
+  umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_rank = rank;//rank0 only
+  umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_type = 1;//read
+  wr(MRCTRL0_DCH1,umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32);
 
-        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32 = rd(MRCTRL1_DCH1);
-        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.mr_data = addr << 8;
-        wr(MRCTRL1_DCH1, umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32);
+  umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32 = rd(MRCTRL1_DCH1);
+  umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.mr_data = addr<<8;
+  wr(MRCTRL1_DCH1,umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32);
+  
+  umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32 = rd(MRCTRL0_DCH1);
+  umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_wr = 1;//trigger wr/rd
+  wr(MRCTRL0_DCH1,umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32);
 
-
-        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32 = rd(MRCTRL1_DCH1);
-        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.mr_data = addr << 8;
-        wr(MRCTRL1_DCH1, umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32);
-
-        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32 = rd(MRCTRL0_DCH1);
-        umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.mr_wr = 1;//trigger wr/rd
-        wr(MRCTRL0_DCH1, umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl0.u32);
-
-        udelay(20);
-        while ((rd(MRSTAT_DCH1) & 0x1) == 0x1);
-        return ddr_sysreg_rd(MRR_STS_CH1);
+  umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.u32 = rd(MRCTRL1_DCH1);
+  return (umctl2_reg.dwc_ddr_umctl2_c_struct_mrctrl1.mr_data & 0xFF);
   }
   }
 
@@ -318,15 +236,15 @@ unsigned int ddr_phy_reg_rd(unsigned long int addr) {
     if(port & 0x4) wr(PCTRL_2,0);
     if(port & 0x8) wr(PCTRL_3,0);
     if(port & 0x10) wr(PCTRL_4,0);
-    while (rd(PSTAT) != 0x0);
-    if ((port & 0x1F) == 0x1F) { //all ports are disabled
-        wr(DBG1, 2);
-        wr(DBG1_DCH1, 2);
+    if(port & 0x1F) { //at least one port is not disabled
+        wr(DBG1,0);
+        wr(DBG1_DCH1,0);
     }
-    else { //at least one port is not disabled
-        wr(DBG1, 0);
-        wr(DBG1_DCH1, 0);
+    else { //all ports are disabled
+        wr(DBG1,3);
+        wr(DBG1_DCH1,3);
     }
+
   }
 
   void enable_axi_port(int port) {
@@ -539,7 +457,7 @@ if(bits==64) {
   wr(DFITMG0,0x05a3820e);//[28:24] dft_t_ctrl_delay [22:16] dfi_t_rddate_en=RL-5
 #endif
   wr(DFITMG1,0x000c0303);
-  wr(DFILPCFG0,0x0351a101); //[8]=1: enable dfi lp mode during selfref
+  wr(DFILPCFG0,0x0351a001);
   //wr(DFIUPD0,0x00400018); //[31:30]=0 use ctrlupd enable
   //wr(DFIUPD1,0x00b700c4);
   //wr(DFIUPD2,0x00000000);//[31]=0 disable phy ctrlupdate
@@ -639,7 +557,7 @@ if(bits==64) {
   wr(DFITMG0,0x059f820c);//[28:24] dfi_t_ctrl_delay
 #endif
   wr(DFITMG1,0x000c0303);//dfi_t_wrdata_delay=tctrl+6+BL/2+trainedTdqsdly=24, may need take care cmd pipe
-  wr(DFILPCFG0,0x0351a101); //[8]=1: enable dfi lp mode during selfref
+  wr(DFILPCFG0,0x0351a001);
   //wr(DFIUPD0,0xc0400018);
   //wr(DFIUPD1,0x00b700c4);
   //wr(DFIUPD2,0x80000000);
@@ -727,7 +645,7 @@ if(bits==64) {
   wr(DFITMG0,0x059b820a); //[22:16] dfi_t_rddate_en=RL-5
 #endif
   wr(DFITMG1,0x000b0303);
-  wr(DFILPCFG0,0x0351a101); //[8]=1: enable dfi lp mode during selfref
+  wr(DFILPCFG0,0x0351a001);
   //wr(DFIUPD0,0xc0400018);
   //wr(DFIUPD1,0x00b700c4);
   //wr(DFIUPD2,0x80000000);
@@ -812,7 +730,7 @@ if(bits==64) {
   wr(ZQCTL2,0x00000000);
   wr(DFITMG0,0x048f8206);
   wr(DFITMG1,0x000b0303);
-  wr(DFILPCFG0,0x0351a101); //[8]=1: enable dfi lp mode during selfref
+  wr(DFILPCFG0,0x0351a001);
   //wr(DFIUPD0,0xc0400018);
   //wr(DFIUPD1,0x00b700c4);
   //wr(DFIUPD2,0x80000000);
@@ -938,28 +856,17 @@ if(bits==64) {
 #ifdef CONFIG_DDR_MSG
  printf("DDR 32bit mode\n");
 #endif
+  wr(ADDRMAP0,0x001f001f);  //
   if(rank_num==2) {
-#ifdef CONFIG_DDR_DDP
-    wr(ADDRMAP0,0x001f0018);//max 8GB
-#else
-    wr(ADDRMAP0,0x001f0017); //4GB
-#endif
-  }
-  else {
-    wr(ADDRMAP0,0x001f001f); //cs_bit0: NULL
+  wr(ADDRMAP0,0x001f0017);//4GB
   }
   wr(ADDRMAP1,0x00080808); //bank +2
   wr(ADDRMAP2,0x00000000); //col b5+5 ~ col b2  +2
   wr(ADDRMAP3,0x00000000); //col b9 ~ col b6
   wr(ADDRMAP4,0x00001f1f); //col b11~ col b10
   wr(ADDRMAP5,0x070f0707); //row_b11 row b2_10 row b1 row b0  +6
-  wr(ADDRMAP6,0x07070707); //row 15
-  wr(ADDRMAP7,0x00000f0f); //row16: NULL
-#ifdef CONFIG_DDR_DDP
-  if(rank_num==2) {
-    wr(ADDRMAP7,0x00000f07); //max row16
-  }
-#endif
+  wr(ADDRMAP6,0x07070707); //max row 15
+  wr(ADDRMAP7,0x00000f0f);
   wr(ADDRMAP9,0x07070707);
   wr(ADDRMAP10,0x07070707);
   wr(ADDRMAP11,0x00000007);
@@ -967,12 +874,12 @@ if(bits==64) {
 #ifdef CONFIG_DDR_MSG
  printf("DDR 64bit mode, 256B interleaving\n");
 #endif
-  wr(ADDRMAP0,0x0004001f); //cs_bit0: NULL
+  wr(ADDRMAP0,0x0004001f);  // +2
   if(rank_num==2) {
 #ifdef CONFIG_DDR_DDP
-    wr(ADDRMAP0,0x00040019);//max 16GB
+  wr(ADDRMAP0,0x00040019);//16GB
 #else
-    wr(ADDRMAP0,0x00040018);//8GB
+  wr(ADDRMAP0,0x00040018);//8GB
 #endif
   }
   wr(ADDRMAP1,0x00090909); //bank +2
@@ -980,11 +887,11 @@ if(bits==64) {
   wr(ADDRMAP3,0x01010101); //col b9 ~ col b6
   wr(ADDRMAP4,0x00001f1f); //col b11~ col b10
   wr(ADDRMAP5,0x080f0808); //row_b11 row b2_10 row b1 row b0  +6
-  wr(ADDRMAP6,0x08080808); //row15
+  wr(ADDRMAP6,0x08080808);
 #ifdef CONFIG_DDR_DDP
-  wr(ADDRMAP7,0x00000f08); //row16
+  wr(ADDRMAP7,0x00000f08);
 #else
-  wr(ADDRMAP7,0x00000f0f); //row16: NULL
+  wr(ADDRMAP7,0x00000f0f);
 #endif
   wr(ADDRMAP9,0x08080808);
   wr(ADDRMAP10,0x08080808);
@@ -994,130 +901,6 @@ if(bits==64) {
  }
 }
 
-#define MEMSIZE_MIN_MB (2*1024)
-#define MEMSIZE_MAX_MB (16*1024)
-#define UNIT_MB (1024*1024)
-int lpddr4_query_boundary(enum DDR_TYPE type, int rank_num, int speed,
-					enum DDR_BITWIDTH bits, unsigned long size)
-{
-  if ((size < (unsigned long)MEMSIZE_MIN_MB*UNIT_MB) ||
-    (size > (unsigned long)MEMSIZE_MAX_MB*UNIT_MB))
-    goto err_ret;
-
-  if (bits == DDR_BITWIDTH_32) {// only phy0
-    if (rank_num == 2) {
-      if (size == 0x80000000) //2GB
-        goto err_ret;
-      else if (size == 0x100000000) //4GB
-        goto ret_ok;
-      else if (size == 0x200000000) //8GB
-        goto ret_ok;
-      else if (size == 0x400000000) //16GB
-        goto err_ret;
-      else
-        goto err_ret;
-    }
-    else { // single rank
-      if (size == 0x80000000) //2GB
-        goto ret_ok;
-      else if (size == 0x100000000) //4GB
-        goto err_ret;
-      else if (size == 0x200000000) //8GB
-        goto err_ret;
-      else if (size == 0x400000000) //16GB
-        goto err_ret;
-      else
-        goto err_ret;
-    }
-  }
-  else if (bits == DDR_BITWIDTH_64) { // phy0+phy1
-    if (rank_num == 2) {
-      if (size == 0x80000000) //2GB
-        goto err_ret;
-      else if (size == 0x100000000) //4GB
-        goto err_ret;
-      else if (size == 0x200000000) //8GB
-        goto ret_ok;
-      else if (size == 0x400000000) //16GB
-        goto ret_ok;
-      else
-        goto err_ret;
-    }
-    else { // single rank
-      if (size == 0x80000000) //2GB
-        goto err_ret;
-      else if (size == 0x100000000) //4GB
-        goto ret_ok;
-      else if (size == 0x200000000) //8GB
-        goto err_ret;
-      else if (size == 0x400000000) //16GB
-        goto err_ret;
-      else
-        goto err_ret;
-    }
-  }
-  else {
-    goto err_ret;
-  }
-
-ret_ok:
-  return 0;
-
-err_ret:
-  return -1;
-}
-
-int adjust_ddr_addrmap(enum DDR_TYPE type, int rank_num, int speed,
-					enum DDR_BITWIDTH bits, unsigned long size)
-{
-  if (lpddr4_query_boundary(type, rank_num, speed, bits, size) < 0)
-    goto err_ret;
-
-  if (bits == DDR_BITWIDTH_32) {// only phy0
-    if (rank_num == 2) {
-      if (size == 0x100000000) {//4GB
-        wr(ADDRMAP0,0x001f0017); // cs_bit0: HIF[29]
-        wr(ADDRMAP7,0x00000f0f); // row16: NULL
-      }
-      else if (size == 0x200000000) {//8GB
-        wr(ADDRMAP0,0x001f0018); // cs_bit0: HIF[30]
-        wr(ADDRMAP7,0x00000f07); // row16: HIF[29]
-      }
-    }
-	else { // single rank
-      if (size == 0x80000000) //2GB
-        wr(ADDRMAP0,0x001f001f); // cs_bit0: NULL
-    }
-  }
-  else if (bits == DDR_BITWIDTH_64) { // phy0+phy1
-    if (rank_num == 2) {
-      if (size == 0x200000000) {//8GB
-        wr(ADDRMAP0,0x00040018); // cs_bit0: HIF[30]
-        wr(ADDRMAP7,0x00000f0f); // row16: NULL
-      }
-      else if (size == 0x400000000) {//16GB
-        wr(ADDRMAP0,0x00040019); // cs_bit0: HIF[31]
-        wr(ADDRMAP7,0x00000f08); // row16: HIF[30]
-      }
-    }
-    else { // single rank
-      if (size == 0x100000000) {//4GB
-        wr(ADDRMAP0,0x0004001f); // cs_bit0: NULL
-        wr(ADDRMAP7,0x00000f0f); // row16: NULL
-      }
-    }
-  }
-  else {
-    // nothing
-  }
-
-  return 0;
-
-err_ret:
-  printf("unsupport memsize %ld\n", size);
-  return -1;
-}
-
   void quasi_reg_write(unsigned long int reg,int wdata) {
     DWC_DDR_UMCTL2_C_STRUCT_REG_S umctl2_reg;
 
@@ -1232,11 +1015,11 @@ void lpddr4_enter_selfrefresh(int pwdn_en,int dis_dram_clk,int mode) {
     umctl2_reg.dwc_ddr_umctl2_c_struct_stat.u32 = rd(STAT_DCH1);
     if(pwdn_en) {
     while( umctl2_reg.dwc_ddr_umctl2_c_struct_stat.selfref_state != 2) //wait sdram enter selfrefresh-powerdown state
-        umctl2_reg.dwc_ddr_umctl2_c_struct_stat.u32 = rd(STAT_DCH1);
+        umctl2_reg.dwc_ddr_umctl2_c_struct_stat.u32 = rd(STAT);
     }
     else {
     while( umctl2_reg.dwc_ddr_umctl2_c_struct_stat.selfref_state != 1) //wait sdram enter selfrefresh state
-        umctl2_reg.dwc_ddr_umctl2_c_struct_stat.u32 = rd(STAT_DCH1);
+        umctl2_reg.dwc_ddr_umctl2_c_struct_stat.u32 = rd(STAT);
     }
 #ifdef CONFIG_DDR_MSG
     printf("[lpddr4_enter_selfrefresh]: CH1 STAT is :%x after enter selfrefresh state\n",umctl2_reg.dwc_ddr_umctl2_c_struct_stat.u32);
@@ -1272,8 +1055,7 @@ void lpddr4_auto_ps_en(int pwdn_en,int selfref_en,int clock_auto_disable ) {
     //ddr_sysreg_wr(DDR_CFG0,0x1ff0);
     //ddr_sysreg_wr(DDR_CFG0,0x1ff0);
     ddr_sysreg.ddr_sysreg_registers_struct_ddr_cfg0.u32 = ddr_sysreg_rd(DDR_CFG0);
-    //ddr_sysreg.ddr_sysreg_registers_struct_ddr_cfg0.rg_ctl_ddr_usw_rst_reg |= 0x1F2;
-    ddr_sysreg.ddr_sysreg_registers_struct_ddr_cfg0.rg_ctl_ddr_usw_rst_reg |= 0x1FA;
+    ddr_sysreg.ddr_sysreg_registers_struct_ddr_cfg0.rg_ctl_ddr_usw_rst_reg |= 0x1F2;
     ddr_sysreg_wr(DDR_CFG0,ddr_sysreg.ddr_sysreg_registers_struct_ddr_cfg0.u32);
   }
 
@@ -1293,7 +1075,7 @@ void dfi_freq_change(int dfi_freq,int skip_dram_init) {
 #ifdef CONFIG_DDR_MSG
   printf("[dfi_freq_change]: start dfi_freq_change, target dfi_freq is %x \n",dfi_freq);
 #endif
-  //wr(DBG1,3);
+  wr(DBG1,3);
   umctl2_reg.dwc_ddr_umctl2_c_struct_swctl.u32 = rd(SWCTL);
   umctl2_reg.dwc_ddr_umctl2_c_struct_swctl.sw_done = 0;
   wr(SWCTL,umctl2_reg.dwc_ddr_umctl2_c_struct_swctl.u32);
@@ -1304,6 +1086,7 @@ void dfi_freq_change(int dfi_freq,int skip_dram_init) {
 
   umctl2_reg.dwc_ddr_umctl2_c_struct_dfimisc.u32 = rd(DFIMISC);
   umctl2_reg.dwc_ddr_umctl2_c_struct_dfimisc.dfi_frequency = dfi_freq;
+  umctl2_reg.dwc_ddr_umctl2_c_struct_dfimisc.dfi_init_start = 0x1;
   umctl2_reg.dwc_ddr_umctl2_c_struct_dfimisc.dfi_init_complete_en = 0;
   wr(DFIMISC,umctl2_reg.dwc_ddr_umctl2_c_struct_dfimisc.u32);
 
@@ -1314,28 +1097,15 @@ void dfi_freq_change(int dfi_freq,int skip_dram_init) {
   while( umctl2_reg.dwc_ddr_umctl2_c_struct_swstat.sw_done_ack == 0)
     umctl2_reg.dwc_ddr_umctl2_c_struct_swctl.u32 = rd(SWSTAT);
 
-  wr(SWCTL,0x0);
-  umctl2_reg.dwc_ddr_umctl2_c_struct_dfimisc.u32 = rd(DFIMISC);
-  umctl2_reg.dwc_ddr_umctl2_c_struct_dfimisc.dfi_init_start = 0x1;
-  wr(DFIMISC,umctl2_reg.dwc_ddr_umctl2_c_struct_dfimisc.u32);
-  wr(SWCTL,0x1);
-  while(rd(SWSTAT)!=0x00000001);
   rdata = rd(DFISTAT);
-  while ((rdata & 0x1) != 0) //wait dfi_init_complete = 0
-    rdata = rd(DFISTAT);
-
-#ifndef CONFIG_DDR_H32_MODE
-  rdata = rd(DCH1_DFISTAT);
   while((rdata & 0x1) != 0) //wait dfi_init_complete = 0
-    rdata = rd(DCH1_DFISTAT);
-#endif
-
+  rdata = rd(DFISTAT);
   //change dfi clk freq here
   //pull down dfi_init_start
   umctl2_reg.dwc_ddr_umctl2_c_struct_swctl.u32 = rd(SWCTL);
   umctl2_reg.dwc_ddr_umctl2_c_struct_swctl.sw_done = 0;
-  wr(SWCTL, umctl2_reg.dwc_ddr_umctl2_c_struct_swctl.u32);
- 
+  wr(SWCTL,umctl2_reg.dwc_ddr_umctl2_c_struct_swctl.u32);
+
   umctl2_reg.dwc_ddr_umctl2_c_struct_dfimisc.u32 = rd(DFIMISC);
   umctl2_reg.dwc_ddr_umctl2_c_struct_dfimisc.dfi_init_start = 0;
   wr(DFIMISC,umctl2_reg.dwc_ddr_umctl2_c_struct_dfimisc.u32);
@@ -1349,17 +1119,9 @@ void dfi_freq_change(int dfi_freq,int skip_dram_init) {
   umctl2_reg.dwc_ddr_umctl2_c_struct_dfistat.u32 = rd(DFISTAT);
   while(umctl2_reg.dwc_ddr_umctl2_c_struct_dfistat.dfi_init_complete == 0)
     umctl2_reg.dwc_ddr_umctl2_c_struct_dfistat.u32 = rd(DFISTAT);
-
-  //wait dfi_init_complete = 1
-#ifndef CONFIG_DDR_H32_MODE
-  umctl2_reg.dwc_ddr_umctl2_c_struct_dfistat.u32 = rd(DCH1_DFISTAT);
-  while(umctl2_reg.dwc_ddr_umctl2_c_struct_dfistat.dfi_init_complete == 0)
-    umctl2_reg.dwc_ddr_umctl2_c_struct_dfistat.u32 = rd(DCH1_DFISTAT);
-#endif
-
-  //wr(DBG1,0);
+  wr(DBG1,0);
 #ifdef CONFIG_DDR_MSG
-  printf("[dfi_freq_change]: dfi_freq_change, end \n");
+  printf("[dfi_freq_change]: dfi_freq_change, end \n",dfi_freq);
 #endif
 }
 
@@ -1384,168 +1146,3 @@ void lpddr4_auto_selref(void)
   wr(PWRCTL,0x0000000b); //[3] dfi_dram_clk_disable [1] powerdown_en [0]serref_en
   wr(DCH1_PWRCTL,0x0000000b);
 }
-
-void ctrl_en_lp3_exit(enum DDR_BITWIDTH bits) {
-  //skip DRAM init, because this has done 
-  wr(SWCTL,0x00000000);
-  wr(INIT0,0xc0020002);
-  wr(SWCTL,0x00000001);
-  while(rd(SWSTAT)!=0x00000001);
-
-  //dfi frequency change proto ,to PS0
-  wr(SWCTL,0x00000000);
-  wr(DFIMISC,0x00000000);// [5]dfi_freq=0x0
-  wr(SWCTL,0x00000001);
-  while(rd(SWSTAT)!=0x00000001);
-
-  wr(SWCTL,0x00000000);
-  wr(DFIMISC,0x00000020);// [5]dfi_init_start=0x1
-  wr(SWCTL,0x00000001);
-  while(rd(SWSTAT)!=0x00000001);
-
-
-  while(rd(DFISTAT)!=0x00000001); //polling dfi_init_complete
-if(bits==64) {
-  while(rd(DCH1_DFISTAT)!=0x00000001);
- }
-  wr(SWCTL,0x00000000);
-  wr(DFIMISC,0x00000000);
-  wr(SWCTL,0x00000001);
-  while(rd(SWSTAT)!=0x00000001);
-
-
-  wr(SWCTL,0x00000000);
-  wr(DFIMISC,0x00000001);
-  wr(SWCTL,0x00000001);
-  while(rd(SWSTAT)!=0x00000001);
-
-  //for low power,
-  wr(SWCTL,0x00000000);
-  wr(PWRCTL,0x0000000a); //[3] dfi_dram_clk_disable [1] powerdown_en
-  wr(DCH1_PWRCTL,0x0000000a);
-  wr(SWCTL,0x00000001);
-  while (rd(SWSTAT) != 0x00000001);
-  //detect until umctrl into normal state
-  while (rd(STAT) != 0x00000001);
-  if(bits==64) {
-    while(rd(DCH1_STAT) != 0x00000001);
-  }
-
-  //en phy master proto
-  wr(DFIPHYMSTR,0x14000001);
-
-#ifdef CONFIG_DDR_MSG
-    DDR_DEBUG("DFIPHYMSTR is %0x \n", rd(DFIPHYMSTR));
-    DDR_DEBUG("DFIUPD0    is %0x \n", rd(DFIUPD0));
-    DDR_DEBUG("DFIUPD1    is %0x \n", rd(DFIUPD1));
-    DDR_DEBUG("ZQCTL0     is %0x \n", rd(ZQCTL0));
-    DDR_DEBUG("ADDRMAP0     is %0x \n", rd(ADDRMAP0));
-    DDR_DEBUG("ADDRMAP1     is %0x \n", rd(ADDRMAP1));
-#endif
-}
-
-int lpddr4_reinit_ctrl(enum DDR_TYPE type, int rank_num, int speed,
-					enum DDR_BITWIDTH bits, unsigned long size)
-{
-    int ret;
-    unsigned int rdata;
-
-    //a.
-    ddr_sysreg_wr(DDR_CFG1, 0xa000011f);   //remove core clock after xx
-    wr(PWRCTL, 0x00000000); //[3] dfi_dram_clk_disable [1] powerdown_en [0]serref_en
-    wr(DCH1_PWRCTL, 0x00000000);
-
-    // use phy value stored in spl
-    //dwc_ddrphy_phyinit_regInterface(saveRegs);
-
-    //b.dis axi port
-    disable_axi_port(0x1f);
-    while (rd(PSTAT) != 0x0);
-
-#ifdef CONFIG_DDR_MSG
-    DDR_DEBUG("Axi prot idle\n");
-#endif
-    wr(DFIPHYMSTR, 0x14000000);
-    //check status.
-    while ((rd(STAT) & 0x3) == 0x03);
-
-#ifndef CONFIG_DDR_H32_MODE
-    while ((rd(STAT_DCH1) & 0x3) == 0x03);
-#endif
-    //c.poll cam empty flag
-    while ((rd(DBGCAM) & 0x36000000) != 0x36000000);
-    //d.save phy regs
-    //e.SRE
-    lpddr4_enter_selfrefresh(1, 0, 0);
-    //f.LP3 enter
-    dfi_freq_change(0x1f, 0x3);
-    //g.PwrOk disassert
-    rdata = ddr_sysreg_rd(DDR_CFG0);
-    rdata &= ~(0x1 << 6);
-    ddr_sysreg_wr(DDR_CFG0, rdata);   //Pwrokin dessert
-
-    //p.phy reset
-    rdata = ddr_sysreg_rd(DDR_CFG0);
-    rdata &= ~(0x1 << 7);
-    rdata &= 0x0;
-    ddr_sysreg_wr(DDR_CFG0, rdata);   //Phy reset .DDR_CFG0 ALL reset
-
-    //r.ddr core reset
-    rdata = ddr_sysreg_rd(DDR_CFG0);
-    rdata &= ~(0x1 << 5);
-    ddr_sysreg_wr(DDR_CFG0, rdata);   //ctrl sw reset
-
-    //s.pwr ok assert
-    rdata = ddr_sysreg_rd(DDR_CFG0);
-    rdata |= (0x1 << 6);
-    ddr_sysreg_wr(DDR_CFG0, rdata);   //Pwrokin dessert
-
-    //t.ctrl init
-    //dwc_umctl_init_skip_traing(type, rank_num, speed, bits);
-    ddr_sysreg_wr(DDR_CFG0, 0x50);  // release apb presetn
-    ddr_sysreg_wr(DDR_CFG0, 0x50);
-    ddr_sysreg_wr(DDR_CFG0, 0x50);
-    if (bits == 32) {
-        ddr_sysreg_wr(DDR_CFG0, 0x52);
-    }
-    ctrl_init(rank_num, speed);
-    addrmap(rank_num, bits);
-    ret = adjust_ddr_addrmap(type, rank_num, speed, bits, size);
-
-    // msic regu restore for str
-    dwc_ddr_misc_regu_save();
-
-    de_assert_other_reset_ddr(); //after this step, only PwrOk is staill low
-
-    dq_pinmux(bits);
-
-    //u.phy restor
-	  dwc_ddrphy_phyinit_regInterface(restoreRegs);
-
-    //v.ctrl en ,hs
-    ctrl_en_lp3_exit(bits);
-
-    //w.SRE
-    lpddr4_selfrefresh_exit(0);
-
-    //y.en auto refresh
-    enable_auto_refresh();
- 
-    //x.en axi port
-    enable_axi_port(0x1f);
-    wr(DFIPHYMSTR, 0x14000001);
-    lpddr4_auto_selref();
-
-    if(rd(PSTAT))
-    {
-#ifdef CONFIG_DDR_MSG
-	    DDR_DEBUG("***** DDR busy in LP3 Mode *****\n");
-#endif
-    }else{
-#ifdef CONFIG_DDR_MSG
-	    DDR_DEBUG("***** AXI port idle *****\n");
-#endif
-    }
-    return ret;
- }
-

board/thead/light-c910/spl.c

@@ -26,11 +26,6 @@
 DECLARE_GLOBAL_DATA_PTR;
 
 extern void init_ddr(void);
-#ifdef CONFIG_FIXUP_MEMORY_REGION
-extern int fixup_ddr_addrmap(unsigned long size);
-extern int query_ddr_boundary(unsigned long size);
-#endif
-extern unsigned long get_ddr_density(void);
 extern void cpu_clk_config(int cpu_freq);
 extern void sys_clk_config(void);
 extern void ddr_clk_config(int ddr_freq);
@@ -98,25 +93,6 @@ void setup_ddr_pmp(void)
 	sync_is();
 }
 
-void clear_ddr_pmp(void)
-{
-	/* restore pmp entry0,entry1 setting in bootrom */
-	writel(0x0400000000 >> 12, (void *)(PMP_BASE_ADDR + 0x104));
-	writel(0x0 >> 12, (void *)(PMP_BASE_ADDR + 0x100));
-	writel(0xffe1000000 >> 12, (void *)(PMP_BASE_ADDR + 0x10c));
-	writel(0xffe0180000 >> 12, (void *)(PMP_BASE_ADDR + 0x108));
-
-	writel(0x4040, (void *)(PMP_BASE_ADDR + 0x000));
-
-	sync_is();
-}
-
-static inline void _l2cache_ciall(void)
-{
-	asm volatile (".long 0x0170000b");
-}
-
-
 int get_rng(unsigned int *rng, int cnt)
 {
 	int i;
@@ -321,101 +297,6 @@ void setup_ddr_parity(void)
 	}
 }
 
-#ifdef CONFIG_FIXUP_MEMORY_REGION
-
-#define MAGIC_DATA (0xF4240)
-#define MAGIC_DATA2 (0x5AA5)
-#define MAGIC_DATA3 (0x3C3C)
-#define MAGIC_DATA4 (0xF0F0)
-
-/*
-return: 0: found boundary;
-*/
-int boundary_verify(unsigned long boundary) {
-	phys_addr_t verify_addr = (phys_addr_t)CONFIG_SYS_SDRAM_BASE;
-	phys_addr_t verify_addr2 = ((phys_addr_t)boundary + CONFIG_SYS_SDRAM_BASE)/4;
-	phys_addr_t verify_addr3 = ((phys_addr_t)boundary + CONFIG_SYS_SDRAM_BASE)/2;
-	phys_addr_t verify_addr4 = (phys_addr_t)boundary + CONFIG_SYS_SDRAM_BASE;
-
-	// verify data accessing result firstly
-	writel(MAGIC_DATA2, verify_addr);
-	invalidate_dcache_range(verify_addr, verify_addr + CONFIG_SYS_CACHELINE_SIZE);
-	if (readl(verify_addr) != MAGIC_DATA2) {
-		printf("ddr rw test failed\n");
-		return -1;
-	}
-	writel(MAGIC_DATA, verify_addr);  // writing at beginning
-	invalidate_dcache_range(verify_addr, verify_addr + CONFIG_SYS_CACHELINE_SIZE);
-	if (readl(verify_addr) != MAGIC_DATA) {
-		printf("ddr rw test failed\n");
-		return -1;
-	}
-	writel(MAGIC_DATA2, verify_addr2); // writing at one-quarter addr
-	writel(MAGIC_DATA3, verify_addr3); // writing at half addr
-	invalidate_dcache_range(verify_addr, verify_addr + CONFIG_SYS_CACHELINE_SIZE);
-	invalidate_dcache_range(verify_addr2, verify_addr2 + CONFIG_SYS_CACHELINE_SIZE);
-	invalidate_dcache_range(verify_addr3, verify_addr3 + CONFIG_SYS_CACHELINE_SIZE);
-
-	if (boundary == (unsigned long)MAXIMAL_DDR_DENSITY_MB * UNIT_MB) { // boundary by design
-		if ((readl(verify_addr) == MAGIC_DATA) &&
-			(readl(verify_addr2) == MAGIC_DATA2) &&
-			(readl(verify_addr3) == MAGIC_DATA3))
-			return 0;
-	}
-	else {
-		writel(MAGIC_DATA4, verify_addr4); // writing out of boundary
-		invalidate_dcache_range(verify_addr4, verify_addr4 + CONFIG_SYS_CACHELINE_SIZE);
-		if ((readl(verify_addr) == MAGIC_DATA4) && // overwrite by verify_addr4
-			(readl(verify_addr2) == MAGIC_DATA2) &&
-			(readl(verify_addr3) == MAGIC_DATA3) &&
-			(readl(verify_addr4) == MAGIC_DATA4))
-			return 0;
-	}
-
-	return -1;
-}
-
-int setup_ddr_addrmap(void)
-{
-	int ret;
-	unsigned long boundary = (unsigned long)MAXIMAL_DDR_DENSITY_MB * UNIT_MB;
-
-	// verify data accessing result firstly
-	writel(MAGIC_DATA, (phys_addr_t)CONFIG_SYS_SDRAM_BASE);
-	invalidate_dcache_range(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_CACHELINE_SIZE);
-	if (readl((phys_addr_t)CONFIG_SYS_SDRAM_BASE) != MAGIC_DATA) {
-		printf("ddr rw test failed\n");
-		goto addrmap_err;
-	}
-	writel(MAGIC_DATA2, (phys_addr_t)CONFIG_SYS_SDRAM_BASE);
-	invalidate_dcache_range(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_CACHELINE_SIZE);
-	if (readl((phys_addr_t)CONFIG_SYS_SDRAM_BASE) != MAGIC_DATA2) {
-		printf("ddr rw test failed\n");
-		goto addrmap_err;
-	}
-
-	// try to find memory boundary
-	while (boundary >= (unsigned long)MINIMAL_DDR_DENSITY_MB * UNIT_MB) {
-		if (query_ddr_boundary(boundary) == 0) {
-			clear_ddr_pmp();
-			fixup_ddr_addrmap(boundary);
-			setup_ddr_pmp();
-			if (boundary_verify(boundary) == 0) {
-				gd->ram_size = boundary;
-				printf("found ddr boundary <0x%lx>\n", boundary);
-				return 0;
-			}
-		}
-		boundary = boundary >> 1;
-	}
-
-	gd->ram_size = get_ddr_density();
-addrmap_err:
-	printf("failed to setup ddr addrmap\n");
-	return -1;
-}
-#endif
-
 void cpu_performance_enable(void)
 {
 #define CSR_MHINT2_E	0x7cc
@@ -427,7 +308,9 @@ void cpu_performance_enable(void)
 	csr_write(CSR_MCCR2, 0xe2490009);
 	// FIXME: Clear bit[12] to disable L0BTB.
 	csr_write(CSR_MHCR, 0x17f); // clear bit7 to disable indirect brantch prediction
+	csr_write(CSR_MXSTATUS, 0x638000);
 	csr_write(CSR_MHINT, 0x6e30c | (1<<21) | (1<<22)); // set bit21 & bit 22 to close tlb & fence broadcast
+	mdelay(50); // workaround
 }
 
 static int bl1_img_have_head(unsigned long img_src_addr)
@@ -489,9 +372,9 @@ void board_init_f(ulong dummy)
 	preloader_console_init();
 
 #ifdef CONFIG_PMIC_VOL_INIT
-	ret = aon_local_init();
+	ret = pmic_ddr_regu_init();
 	if (ret) {
-		printf("%s aon local init failed %d \n",__func__,ret);
+		printf("%s pmic init failed %d \n",__func__,ret);
 		hang();
 	}
 
@@ -506,6 +389,7 @@ void board_init_f(ulong dummy)
 		printf("%s set apcpu voltage failed \n",__func__);
 		hang();
 	}
+
 #endif
 	ddr_clk_config(0);
 	cpu_clk_config(0);
@@ -514,12 +398,6 @@ void board_init_f(ulong dummy)
 	setup_ddr_scramble();
 	setup_ddr_parity();
 	setup_ddr_pmp();
-#ifdef CONFIG_FIXUP_MEMORY_REGION
-	setup_ddr_addrmap();
-#else
-	// update ram_size from board config
-	gd->ram_size = get_ddr_density();
-#endif
 
 	printf("ddr initialized, jump to uboot\n");
 	light_board_init_r(NULL, 0);

cmd/Kconfig

@@ -375,6 +375,18 @@ config CMD_FDT
 	help
 	  Do FDT related setup before booting into the Operating System.
 
+config SUPPORT_EXTENSION_SCAN
+	bool
+
+config CMD_EXTENSION
+	bool "Extension board management command"
+	select CMD_FDT
+	depends on SUPPORT_EXTENSION_SCAN
+	help
+	  Enables the "extension" command, which allows to detect
+	  extension boards connected to the system, and apply
+	  corresponding Device Tree overlays.
+
 config CMD_GO
 	bool "go"
 	default y

cmd/Makefile

@@ -48,6 +48,7 @@ ifdef CONFIG_POST
 obj-$(CONFIG_CMD_DIAG) += diag.o
 endif
 obj-$(CONFIG_CMD_DTIMG) += dtimg.o
+obj-$(CONFIG_CMD_EXTENSION) += extension_board.o
 obj-$(CONFIG_CMD_ECHO) += echo.o
 obj-$(CONFIG_ENV_IS_IN_EEPROM) += eeprom.o
 obj-$(CONFIG_CMD_EEPROM) += eeprom.o

cmd/extension_board.c

@@ -0,0 +1,167 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2021
+ * Köry Maincent, Bootlin, <kory.maincent@bootlin.com>
+ */
+
+#include <common.h>
+#include <command.h>
+#include <malloc.h>
+#include <extension_board.h>
+#include <mapmem.h>
+#include <linux/libfdt.h>
+#include <fdt_support.h>
+
+static LIST_HEAD(extension_list);
+
+static int extension_apply(struct extension *extension)
+{
+	char *overlay_cmd;
+	ulong extrasize, overlay_addr;
+	struct fdt_header *blob;
+
+	if (!working_fdt) {
+		printf("No FDT memory address configured. Please configure\n"
+		       "the FDT address via \"fdt addr <address>\" command.\n");
+		return CMD_RET_FAILURE;
+	}
+
+	overlay_cmd = env_get("extension_overlay_cmd");
+	if (!overlay_cmd) {
+		printf("Environment extension_overlay_cmd is missing\n");
+		return CMD_RET_FAILURE;
+	}
+
+	overlay_addr = env_get_hex("extension_overlay_addr", 0);
+	if (!overlay_addr) {
+		printf("Environment extension_overlay_addr is missing\n");
+		return CMD_RET_FAILURE;
+	}
+
+	env_set("extension_overlay_name", extension->overlay);
+	if (run_command(overlay_cmd, 0) != 0)
+		return CMD_RET_FAILURE;
+
+	extrasize = env_get_hex("filesize", 0);
+	if (!extrasize)
+		return CMD_RET_FAILURE;
+
+	fdt_shrink_to_minimum(working_fdt, extrasize);
+
+	blob = map_sysmem(overlay_addr, 0);
+	if (!fdt_valid(&blob))
+		return CMD_RET_FAILURE;
+
+	/* apply method prints messages on error */
+	if (fdt_overlay_apply_verbose(working_fdt, blob))
+		return CMD_RET_FAILURE;
+
+	return CMD_RET_SUCCESS;
+}
+
+static int do_extension_list(struct cmd_tbl *cmdtp, int flag,
+			     int argc, char *const argv[])
+{
+	int i = 0;
+	struct extension *extension;
+
+	if (list_empty(&extension_list)) {
+		printf("No extension registered - Please run \"extension scan\"\n");
+		return CMD_RET_SUCCESS;
+	}
+
+	list_for_each_entry(extension, &extension_list, list) {
+		printf("Extension %d: %s\n", i++, extension->name);
+		printf("\tManufacturer: \t\t%s\n", extension->owner);
+		printf("\tVersion: \t\t%s\n", extension->version);
+		printf("\tDevicetree overlay: \t%s\n", extension->overlay);
+		printf("\tOther information: \t%s\n", extension->other);
+	}
+	return CMD_RET_SUCCESS;
+}
+
+static int do_extension_scan(struct cmd_tbl *cmdtp, int flag,
+			     int argc, char *const argv[])
+{
+	struct extension *extension, *next;
+	int extension_num;
+
+	list_for_each_entry_safe(extension, next, &extension_list, list) {
+		list_del(&extension->list);
+		free(extension);
+	}
+	extension_num = extension_board_scan(&extension_list);
+
+	if (extension_num < 0)
+		return CMD_RET_FAILURE;
+
+	printf("Found %d extension board(s).\n", extension_num);
+
+	return CMD_RET_SUCCESS;
+}
+
+static int do_extension_apply(struct cmd_tbl *cmdtp, int flag,
+			      int argc, char *const argv[])
+{
+	struct extension *extension = NULL;
+	struct list_head *entry;
+	int i = 0, extension_id, ret;
+
+	if (argc < 2)
+		return CMD_RET_USAGE;
+
+	if (strcmp(argv[1], "all") == 0) {
+		list_for_each_entry(extension, &extension_list, list) {
+			ret = extension_apply(extension);
+			if (ret != CMD_RET_SUCCESS)
+				break;
+		}
+	} else {
+		extension_id = simple_strtol(argv[1], NULL, 10);
+		list_for_each(entry, &extension_list) {
+			if (i == extension_id) {
+				extension = list_entry(entry, struct extension,  list);
+				break;
+			}
+			i++;
+		}
+
+		if (!extension) {
+			printf("Wrong extension number\n");
+			return CMD_RET_FAILURE;
+		}
+
+		ret = extension_apply(extension);
+	}
+
+	return ret;
+}
+
+static struct cmd_tbl cmd_extension[] = {
+	U_BOOT_CMD_MKENT(scan, 1, 1, do_extension_scan, "", ""),
+	U_BOOT_CMD_MKENT(list, 1, 0, do_extension_list, "", ""),
+	U_BOOT_CMD_MKENT(apply, 2, 0, do_extension_apply, "", ""),
+};
+
+static int do_extensionops(struct cmd_tbl *cmdtp, int flag, int argc,
+			   char *const argv[])
+{
+	struct cmd_tbl *cp;
+
+	/* Drop the extension command */
+	argc--;
+	argv++;
+
+	cp = find_cmd_tbl(argv[0], cmd_extension, ARRAY_SIZE(cmd_extension));
+	if (cp)
+		return cp->cmd(cmdtp, flag, argc, argv);
+
+	return CMD_RET_USAGE;
+}
+
+U_BOOT_CMD(extension, 3, 1, do_extensionops,
+	"Extension board management sub system",
+	"scan - scan plugged extension(s) board(s)\n"
+	"extension list - lists available extension(s) board(s)\n"
+	"extension apply <extension number|all> - applies DT overlays corresponding to extension boards\n"
+);

cmd/fdt.c

@@ -27,7 +27,6 @@
  */
 DECLARE_GLOBAL_DATA_PTR;
 
-static int fdt_valid(struct fdt_header **blobp);
 static int fdt_parse_prop(char *const*newval, int count, char *data, int *len);
 static int fdt_print(const char *pathp, char *prop, int depth);
 static int is_printable_string(const void *data, int len);
@@ -732,54 +731,6 @@ static int do_fdt(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 
 /****************************************************************************/
 
-/**
- * fdt_valid() - Check if an FDT is valid. If not, change it to NULL
- *
- * @blobp: Pointer to FDT pointer
- * @return 1 if OK, 0 if bad (in which case *blobp is set to NULL)
- */
-static int fdt_valid(struct fdt_header **blobp)
-{
-	const void *blob = *blobp;
-	int err;
-
-	if (blob == NULL) {
-		printf ("The address of the fdt is invalid (NULL).\n");
-		return 0;
-	}
-
-	err = fdt_check_header(blob);
-	if (err == 0)
-		return 1;	/* valid */
-
-	if (err < 0) {
-		printf("libfdt fdt_check_header(): %s", fdt_strerror(err));
-		/*
-		 * Be more informative on bad version.
-		 */
-		if (err == -FDT_ERR_BADVERSION) {
-			if (fdt_version(blob) <
-			    FDT_FIRST_SUPPORTED_VERSION) {
-				printf (" - too old, fdt %d < %d",
-					fdt_version(blob),
-					FDT_FIRST_SUPPORTED_VERSION);
-			}
-			if (fdt_last_comp_version(blob) >
-			    FDT_LAST_SUPPORTED_VERSION) {
-				printf (" - too new, fdt %d > %d",
-					fdt_version(blob),
-					FDT_LAST_SUPPORTED_VERSION);
-			}
-		}
-		printf("\n");
-		*blobp = NULL;
-		return 0;
-	}
-	return 1;
-}
-
-/****************************************************************************/
-
 /*
  * Parse the user's input, partially heuristic.  Valid formats:
  * <0x00112233 4 05>	- an array of cells.  Numbers follow standard

cmd/net.c

@@ -458,22 +458,3 @@ U_BOOT_CMD(
 );
 
 #endif  /* CONFIG_CMD_LINK_LOCAL */
-
-/* moved from board_init_r sequence here to save normal boot time */
-static int do_eth_init(cmd_tbl_t *cmdtp, int flag, int argc,
-			char * const argv[])
-{
-	puts("Net:   ");
-	eth_initialize();
-#if defined(CONFIG_RESET_PHY_R)
-	debug("Reset Ethernet PHY\n");
-	reset_phy();
-#endif
-	return 0;
-}
-
-U_BOOT_CMD(
-	eth,	6,	1,	do_eth_init,
-	"eth initialize",
-	""
-);

cmd/pxe_utils.c

@@ -9,6 +9,8 @@
 #include <malloc.h>
 #include <mapmem.h>
 #include <lcd.h>
+#include <fdt_support.h>
+#include <linux/libfdt.h>
 #include <linux/string.h>
 #include <linux/ctype.h>
 #include <errno.h>
@@ -279,6 +281,9 @@ static void label_destroy(struct pxe_label *label)
 	if (label->fdtdir)
 		free(label->fdtdir);
 
+	if (label->fdtoverlays)
+		free(label->fdtoverlays);
+
 	free(label);
 }
 
@@ -326,6 +331,92 @@ static int label_localboot(struct pxe_label *label)
 	return run_command_list(localcmd, strlen(localcmd), 0);
 }
 
+/*
+ * Loads fdt overlays specified in 'fdtoverlays'.
+ */
+#ifdef CONFIG_OF_LIBFDT_OVERLAY
+static void label_boot_fdtoverlay(struct cmd_tbl *cmdtp, struct pxe_label *label)
+{
+	char *fdtoverlay = label->fdtoverlays;
+	struct fdt_header *working_fdt;
+	char *fdtoverlay_addr_env;
+	ulong fdtoverlay_addr;
+	ulong fdt_addr;
+	int err;
+
+	/* Get the main fdt and map it */
+	fdt_addr = simple_strtoul(env_get("fdt_addr_r"), NULL, 16);
+	working_fdt = map_sysmem(fdt_addr, 0);
+	err = fdt_check_header(working_fdt);
+	if (err)
+		return;
+
+	/* Get the specific overlay loading address */
+	fdtoverlay_addr_env = env_get("fdtoverlay_addr_r");
+	if (!fdtoverlay_addr_env) {
+		printf("Invalid fdtoverlay_addr_r for loading overlays\n");
+		return;
+	}
+
+	fdtoverlay_addr = simple_strtoul(fdtoverlay_addr_env, NULL, 16);
+
+	/* Cycle over the overlay files and apply them in order */
+	do {
+		struct fdt_header *blob;
+		char *overlayfile;
+		char *end;
+		int len;
+
+		/* Drop leading spaces */
+		while (*fdtoverlay == ' ')
+			++fdtoverlay;
+
+		/* Copy a single filename if multiple provided */
+		end = strstr(fdtoverlay, " ");
+		if (end) {
+			len = (int)(end - fdtoverlay);
+			overlayfile = malloc(len + 1);
+			strncpy(overlayfile, fdtoverlay, len);
+			overlayfile[len] = '\0';
+		} else
+			overlayfile = fdtoverlay;
+
+		if (!strlen(overlayfile))
+			goto skip_overlay;
+
+		/* Load overlay file */
+		err = get_relfile_envaddr(cmdtp, overlayfile,
+					  "fdtoverlay_addr_r");
+		if (err < 0) {
+			printf("Failed loading overlay %s\n", overlayfile);
+			goto skip_overlay;
+		}
+
+		/* Resize main fdt */
+		fdt_shrink_to_minimum(working_fdt, 8192);
+
+		blob = map_sysmem(fdtoverlay_addr, 0);
+		err = fdt_check_header(blob);
+		if (err) {
+			printf("Invalid overlay %s, skipping\n",
+			       overlayfile);
+			goto skip_overlay;
+		}
+
+		err = fdt_overlay_apply_verbose(working_fdt, blob);
+		if (err) {
+			printf("Failed to apply overlay %s, skipping\n",
+			       overlayfile);
+			goto skip_overlay;
+		}
+
+skip_overlay:
+		if (end)
+			free(overlayfile);
+	} while ((fdtoverlay = strstr(fdtoverlay, " ")));
+}
+#endif
+
 /*
  * Boot according to the contents of a pxe_label.
  *
@@ -520,6 +611,11 @@ static int label_boot(cmd_tbl_t *cmdtp, struct pxe_label *label)
 				       label->name);
 				goto cleanup;
 			}
+
+#ifdef CONFIG_OF_LIBFDT_OVERLAY
+			if (label->fdtoverlays)
+				label_boot_fdtoverlay(cmdtp, label);
+#endif
 		} else {
 			bootm_argv[3] = NULL;
 		}
@@ -577,6 +673,7 @@ enum token_type {
 	T_INCLUDE,
 	T_FDT,
 	T_FDTDIR,
+	T_FDTOVERLAYS,
 	T_ONTIMEOUT,
 	T_IPAPPEND,
 	T_BACKGROUND,
@@ -611,6 +708,7 @@ static const struct token keywords[] = {
 	{"fdt", T_FDT},
 	{"devicetreedir", T_FDTDIR},
 	{"fdtdir", T_FDTDIR},
+	{"fdtoverlays", T_FDTOVERLAYS},
 	{"ontimeout", T_ONTIMEOUT,},
 	{"ipappend", T_IPAPPEND,},
 	{"background", T_BACKGROUND,},
@@ -1043,6 +1141,11 @@ static int parse_label(char **c, struct pxe_menu *cfg)
 				err = parse_sliteral(c, &label->fdtdir);
 			break;
 
+		case T_FDTOVERLAYS:
+			if (!label->fdtoverlays)
+				err = parse_sliteral(c, &label->fdtoverlays);
+			break;
+
 		case T_LOCALBOOT:
 			label->localboot = 1;
 			err = parse_integer(c, &label->localboot_val);

cmd/pxe_utils.h

@@ -43,6 +43,7 @@ struct pxe_label {
 	char *initrd;
 	char *fdt;
 	char *fdtdir;
+	char *fdtoverlays;
 	int ipappend;
 	int attempted;
 	int localboot;

common/fdt_support.c

@@ -1822,3 +1822,49 @@ int fdt_overlay_apply_verbose(void *fdt, void *fdto)
 	return err;
 }
 #endif
+
+/**
+ * fdt_valid() - Check if an FDT is valid. If not, change it to NULL
+ *
+ * @blobp: Pointer to FDT pointer
+ * @return 1 if OK, 0 if bad (in which case *blobp is set to NULL)
+ */
+int fdt_valid(struct fdt_header **blobp)
+{
+	const void *blob = *blobp;
+	int err;
+
+	if (!blob) {
+		printf("The address of the fdt is invalid (NULL).\n");
+		return 0;
+	}
+
+	err = fdt_check_header(blob);
+	if (err == 0)
+		return 1;	/* valid */
+
+	if (err < 0) {
+		printf("libfdt fdt_check_header(): %s", fdt_strerror(err));
+		/*
+		 * Be more informative on bad version.
+		 */
+		if (err == -FDT_ERR_BADVERSION) {
+			if (fdt_version(blob) <
+			    FDT_FIRST_SUPPORTED_VERSION) {
+				printf(" - too old, fdt %d < %d",
+				       fdt_version(blob),
+				       FDT_FIRST_SUPPORTED_VERSION);
+			}
+			if (fdt_last_comp_version(blob) >
+			    FDT_LAST_SUPPORTED_VERSION) {
+				printf(" - too new, fdt %d > %d",
+				       fdt_version(blob),
+				       FDT_LAST_SUPPORTED_VERSION);
+			}
+		}
+		printf("\n");
+		*blobp = NULL;
+		return 0;
+	}
+	return 1;
+}

common/image-fdt.c

@@ -416,7 +416,7 @@ int boot_get_fdt(int flag, int argc, char * const argv[], uint8_t arch,
 				 * FDT blob
 				 */
 				debug("*  fdt: raw FDT blob\n");
-				debug("## Flattened Device Tree blob at %08lx\n",
+				printf("## Flattened Device Tree blob at %08lx\n",
 				       (long)fdt_addr);
 			}
 			break;
@@ -425,7 +425,7 @@ int boot_get_fdt(int flag, int argc, char * const argv[], uint8_t arch,
 			goto no_fdt;
 		}
 
-		debug("   Booting using the fdt blob at %#08lx\n", fdt_addr);
+		printf("   Booting using the fdt blob at %#08lx\n", fdt_addr);
 		fdt_blob = map_sysmem(fdt_addr, 0);
 	} else if (images->legacy_hdr_valid &&
 			image_check_type(&images->legacy_hdr_os_copy,

common/spl/spl.c

@@ -735,6 +735,30 @@ void board_init_r(gd_t *dummy1, ulong dummy2)
 	jump_to_image_no_args(&spl_image);
 }
 
+static void print_ruyisdk_logo(void)
+{
+	//  _____             _  _____ _____  _  __
+	// |  __ \           (_)/ ____|  __ \| |/ /
+	// | |__) |   _ _   _ _| (___ | |  | | ' / 
+	// |  _  / | | | | | | |\___ \| |  | |  <  
+	// | | \ \ |_| | |_| | |____) | |__| | . \ 
+	// |_|  \_\__,_|\__, |_|_____/|_____/|_|\_\
+	//               __/ |                     
+	//              |___/                      
+
+	printf("-----------------------------------------\n");
+	printf("  _____             _  _____ _____  _  __\n");
+	printf(" |  __ \\           (_)/ ____|  __ \\| |/ /\n");
+	printf(" | |__) |   _ _   _ _| (___ | |  | | ' / \n");
+	printf(" |  _  / | | | | | | |\\___ \\| |  | |  <  \n");
+	printf(" | | \\ \\ |_| | |_| | |____) | |__| | . \\ \n");
+	printf(" |_|  \\_\\__,_|\\__, |_|_____/|_____/|_|\\_\\\n");
+	printf("               __/ |                     \n");
+	printf("              |___/                      \n");
+	printf("                    -- Presented by ISCAS\n");
+	printf("-----------------------------------------\n");
+}
+
 #ifdef CONFIG_SPL_SERIAL_SUPPORT
 /*
  * This requires UART clocks to be enabled.  In order for this to work the
@@ -748,6 +772,8 @@ void preloader_console_init(void)
 
 	gd->have_console = 1;
 
+	print_ruyisdk_logo();
+
 #if CONFIG_IS_ENABLED(BANNER_PRINT)
 	puts("\nU-Boot " SPL_TPL_NAME " " PLAIN_VERSION " (" U_BOOT_DATE " - "
 	     U_BOOT_TIME " " U_BOOT_TZ ")\n");

configs/light_a_val_android_defconfig

@@ -18,7 +18,6 @@ CONFIG_SYS_PROMPT="C910 Light# "
 CONFIG_DDR_LP4X_3733_SINGLERANK=y
 # CONFIG_DDR_LP4_3733_DUALRANK is not set
 CONFIG_DDR_BOARD_CONFIG=y
-CONFIG_FIXUP_MEMORY_REGION=n
 CONFIG_CMD_BOOT_SLAVE=y
 CONFIG_CMD_ERASEENV=y
 CONFIG_CMD_GPT=y

configs/light_a_val_defconfig

@@ -6,6 +6,7 @@ CONFIG_NR_DRAM_BANKS=8
 CONFIG_SPL=y
 CONFIG_SMP=y
 CONFIG_TARGET_LIGHT_C910=y
+CONFIG_TARGET_LIGHT_FM_C910_VAL_A=y
 # CONFIG_THEAD_PLIC is not set
 # CONFIG_THEAD_LIGHT_TIMER is not set
 # CONFIG_THEAD_LIGHT_DIGITAL_SENSOR is not set
@@ -17,22 +18,21 @@ CONFIG_DISPLAY_BOARDINFO=y
 # CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
 CONFIG_SPL_RAM_SUPPORT=y
 CONFIG_SPL_RAM_DEVICE=y
-CONFIG_SYS_PROMPT="C910 Light# "
+CONFIG_SYS_PROMPT="Light VAL-A# "
 CONFIG_DDR_LP4X_3733_SINGLERANK=y
 # CONFIG_DDR_LP4_3733_DUALRANK is not set
 CONFIG_DDR_BOARD_CONFIG=y
-CONFIG_FIXUP_MEMORY_REGION=y
 CONFIG_CMD_BOOT_SLAVE=y
 CONFIG_CMD_ERASEENV=y
 CONFIG_CMD_GPT=y
 CONFIG_CMD_MTD=y
-CONFIG_CMD_USB=y
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MEMTEST=y
 CONFIG_DDR_SCAN=y
 CONFIG_DDR_PRBS_TEST=n
+# CONFIG_DOS_PARTITION is not set
 # CONFIG_ISO_PARTITION is not set
 CONFIG_PARTITION_TYPE_GUID=y
 CONFIG_OF_EMBED=y
@@ -63,6 +63,7 @@ CONFIG_MMC_SDHCI_SNPS=y
 CONFIG_MMC_SDHCI_SDMA=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_MMC_RPMB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
 CONFIG_SUPPORT_EMMC_RPMB=y
 CONFIG_DM_MTD=y
 CONFIG_MTD_SPI_NAND=y
@@ -77,17 +78,16 @@ CONFIG_SPI=y
 CONFIG_DESIGNWARE_SPI=y
 CONFIG_DESIGNWARE_QSPI=y
 CONFIG_USB=y
-CONFIG_DM_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_DWC3=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_MANUFACTURER="U-Boot-THEAD"
 CONFIG_USB_GADGET_VENDOR_NUM=0x1234
 CONFIG_USB_GADGET_PRODUCT_NUM=0x8888
+CONFIG_USB_FUNCTION_MASS_STORAGE=y
 # CONFIG_SPL_USE_TINY_PRINTF is not set
 # CONFIG_EFI_LOADER is not set
-# CONFIG_LIGHT_BOOT_FORCE_SEQ is not set
+# CONFIG_LIGHT_SEC_BOOT is not set
+CONFIG_DEFAULT_FDT_FILE="light-a-val.dtb"
 CONFIG_BOARD_LATE_INIT=y
 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
 CONFIG_DM_VIDEO=y
@@ -107,5 +107,4 @@ CONFIG_PMIC_VOL_INIT=y
 CONFIG_DDR_REGU_0V6=600000
 CONFIG_DDR_REGU_0V8=800000
 CONFIG_DDR_REGU_1V1=1100000
-CONFIG_MISC=y
-CONFIG_LIGHT_AON_CONF=y
+CONFIG_BOARD_RNG_SEED=y

configs/light_a_val_sec_defconfig

@@ -18,7 +18,6 @@ CONFIG_SYS_PROMPT="C910 Light# "
 CONFIG_DDR_LP4X_3733_SINGLERANK=y
 # CONFIG_DDR_LP4_3733_DUALRANK is not set
 CONFIG_DDR_BOARD_CONFIG=y
-CONFIG_FIXUP_MEMORY_REGION=y
 # CONFIG_TPM is not set
 # CONFIG_TPM_Z32H330TC_SPI is not set
 # CONFIG_TPM_V2 is not set
@@ -35,6 +34,7 @@ CONFIG_CMD_I2C=y
 CONFIG_CMD_MEMTEST=y
 CONFIG_DDR_SCAN=y
 CONFIG_DDR_PRBS_TEST=n
+# CONFIG_DOS_PARTITION is not set
 # CONFIG_ISO_PARTITION is not set
 CONFIG_PARTITION_TYPE_GUID=y
 CONFIG_OF_EMBED=y
@@ -79,9 +79,6 @@ CONFIG_SPI=y
 CONFIG_DESIGNWARE_SPI=y
 CONFIG_DESIGNWARE_QSPI=y
 CONFIG_USB=y
-CONFIG_DM_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_DWC3=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_MANUFACTURER="U-Boot-THEAD"
@@ -99,7 +96,6 @@ CONFIG_PHY=y
 CONFIG_REGMAP=y
 CONFIG_SYSCON=y
 CONFIG_CMD_BMP=y
-CONFIG_CMD_USB=y
 CONFIG_VIDEO_BRIDGE=y
 CONFIG_DM_PCA953X=y
 CONFIG_VIDEO_VS_DPU=y
@@ -112,5 +108,3 @@ CONFIG_PMIC_VOL_INIT=y
 CONFIG_DDR_REGU_0V6=600000
 CONFIG_DDR_REGU_0V8=800000
 CONFIG_DDR_REGU_1V1=1100000
-CONFIG_MISC=y
-CONFIG_LIGHT_AON_CONF=y

configs/light_ant_ref_android_defconfig

@@ -20,7 +20,6 @@ CONFIG_DDR_LP4X_3200_SINGLERANK=y
 CONFIG_DDR_H32_MODE=y
 # CONFIG_DDR_LP4_3733_DUALRANK is not set
 CONFIG_DDR_BOARD_CONFIG=y
-CONFIG_FIXUP_MEMORY_REGION=n
 CONFIG_CMD_BOOT_SLAVE=y
 CONFIG_CMD_ERASEENV=y
 CONFIG_CMD_GPT=y

configs/light_ant_ref_defconfig

@@ -20,7 +20,6 @@ CONFIG_DDR_LP4X_3200_SINGLERANK=y
 CONFIG_DDR_H32_MODE=y
 # CONFIG_DDR_LP4_3733_DUALRANK is not set
 CONFIG_DDR_BOARD_CONFIG=y
-CONFIG_FIXUP_MEMORY_REGION=y
 CONFIG_CMD_BOOT_SLAVE=y
 CONFIG_CMD_ERASEENV=y
 CONFIG_CMD_GPT=y

configs/light_ant_ref_sec_defconfig

@@ -20,7 +20,6 @@ CONFIG_DDR_LP4X_3200_SINGLERANK=y
 CONFIG_DDR_H32_MODE=y
 # CONFIG_DDR_LP4_3733_DUALRANK is not set
 CONFIG_DDR_BOARD_CONFIG=y
-CONFIG_FIXUP_MEMORY_REGION=y
 CONFIG_CMD_BOOT_SLAVE=y
 CONFIG_CMD_ERASEENV=y
 CONFIG_CMD_GPT=y

configs/light_b_product_android_defconfig

@@ -20,7 +20,6 @@ CONFIG_DDR_LP4X_3200_SINGLERANK=y
 CONFIG_DDR_H32_MODE=y
 # CONFIG_DDR_LP4_3733_DUALRANK is not set
 CONFIG_DDR_BOARD_CONFIG=y
-CONFIG_FIXUP_MEMORY_REGION=n
 CONFIG_CMD_BOOT_SLAVE=y
 CONFIG_CMD_ERASEENV=y
 CONFIG_CMD_GPT=y

configs/light_b_product_defconfig

@@ -20,7 +20,6 @@ CONFIG_DDR_LP4X_3200_SINGLERANK=y
 CONFIG_DDR_H32_MODE=y
 # CONFIG_DDR_LP4_3733_DUALRANK is not set
 CONFIG_DDR_BOARD_CONFIG=y
-CONFIG_FIXUP_MEMORY_REGION=y
 CONFIG_CMD_BOOT_SLAVE=y
 CONFIG_CMD_ERASEENV=y
 CONFIG_CMD_GPT=y
@@ -105,5 +104,3 @@ CONFIG_PMIC_VOL_INIT=y
 CONFIG_DDR_REGU_0V6=600000
 CONFIG_DDR_REGU_0V8=800000
 CONFIG_DDR_REGU_1V1=1100000
-CONFIG_MISC=y
-CONFIG_LIGHT_AON_CONF=y

configs/light_b_product_sec_defconfig

@@ -20,7 +20,6 @@ CONFIG_DDR_LP4X_3200_SINGLERANK=y
 CONFIG_DDR_H32_MODE=y
 # CONFIG_DDR_LP4_3733_DUALRANK is not set
 CONFIG_DDR_BOARD_CONFIG=y
-CONFIG_FIXUP_MEMORY_REGION=y
 CONFIG_CMD_BOOT_SLAVE=y
 CONFIG_CMD_ERASEENV=y
 CONFIG_CMD_GPT=y
@@ -105,5 +104,3 @@ CONFIG_PMIC_VOL_INIT=y
 CONFIG_DDR_REGU_0V6=600000
 CONFIG_DDR_REGU_0V8=800000
 CONFIG_DDR_REGU_1V1=1100000
-CONFIG_MISC=y
-CONFIG_LIGHT_AON_CONF=y

configs/light_beagle_android_defconfig

@@ -19,7 +19,6 @@ CONFIG_SYS_PROMPT="C910 Light# "
 CONFIG_DDR_LP4X_3733_SINGLERANK=y
 # CONFIG_DDR_LP4_3733_DUALRANK is not set
 CONFIG_DDR_BOARD_CONFIG=y
-CONFIG_FIXUP_MEMORY_REGION=n
 CONFIG_CMD_BOOT_SLAVE=y
 CONFIG_CMD_ERASEENV=y
 CONFIG_CMD_GPT=y
@@ -115,4 +114,4 @@ CONFIG_ANDROID_AB=y
 CONFIG_CMD_AB_SELECT=y
 CONFIG_XBC=y
 CONFIG_BOARD_RNG_SEED=y
-CONFIG_SPL_TEXT_BASE=0xffe0000800
+CONFIG_SPL_TEXT_BASE=0xffe0000800

configs/light_beagle_defconfig

@@ -6,39 +6,41 @@ CONFIG_NR_DRAM_BANKS=8
 CONFIG_SPL=y
 CONFIG_SMP=y
 CONFIG_TARGET_LIGHT_C910=y
+CONFIG_PMIC_VOL_INIT=y
 CONFIG_TARGET_LIGHT_FM_C910_BEAGLE=y
-# CONFIG_THEAD_PLIC is not set
-# CONFIG_THEAD_LIGHT_TIMER is not set
-# CONFIG_THEAD_LIGHT_DIGITAL_SENSOR is not set
+CONFIG_DDR_LP4X_3733_SINGLERANK=y
+CONFIG_DDR_BOARD_CONFIG=y
 CONFIG_ARCH_RV64I=y
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_BUILD_TARGET="u-boot-with-spl.bin"
+CONFIG_DEFAULT_FDT_FILE="thead/light-beagle.dtb"
+CONFIG_BOARD_LATE_INIT=y
 CONFIG_DISPLAY_CPUINFO=y
 CONFIG_DISPLAY_BOARDINFO=y
 # CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
 CONFIG_SPL_RAM_SUPPORT=y
 CONFIG_SPL_RAM_DEVICE=y
-CONFIG_SYS_PROMPT="C910 Light# "
-CONFIG_DDR_LP4X_3733_SINGLERANK=y
-# CONFIG_DDR_LP4_3733_DUALRANK is not set
-CONFIG_DDR_BOARD_CONFIG=y
+CONFIG_SYS_PROMPT="Light AHead# "
 CONFIG_CMD_BOOT_SLAVE=y
 CONFIG_CMD_ERASEENV=y
-CONFIG_CMD_GPT=y
-CONFIG_CMD_MTD=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_SPI=y
-CONFIG_CMD_I2C=y
 CONFIG_CMD_MEMTEST=y
 CONFIG_DDR_SCAN=y
-CONFIG_DDR_PRBS_TEST=n
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_EXT4_WRITE=y
 # CONFIG_DOS_PARTITION is not set
 # CONFIG_ISO_PARTITION is not set
 CONFIG_PARTITION_TYPE_GUID=y
 CONFIG_OF_EMBED=y
-CONFIG_DEFAULT_DEVICE_TREE="light-a-val"
+CONFIG_DEFAULT_DEVICE_TREE="light-beagle"
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
 CONFIG_SPL_CLK=y
 CONFIG_USB_FUNCTION_FASTBOOT=y
 CONFIG_UDP_FUNCTION_FASTBOOT=y
@@ -47,11 +49,12 @@ CONFIG_FASTBOOT_FLASH=y
 CONFIG_FASTBOOT_FLASH_MMC_DEV=0
 CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
 CONFIG_DM_GPIO=y
+CONFIG_DWAPB_GPIO=y
+CONFIG_DM_PCA953X=y
 CONFIG_DM_I2C=y
 CONFIG_SYS_I2C_DW=y
-CONFIG_DWAPB_GPIO=y
 # CONFIG_MMC_SPI is not set
-CONFIG_MMC_VERBOSE=y
+CONFIG_SUPPORT_EMMC_RPMB=y
 CONFIG_SUPPORT_EMMC_BOOT=y
 CONFIG_MMC_IO_VOLTAGE=y
 CONFIG_MMC_UHS_SUPPORT=y
@@ -59,19 +62,21 @@ CONFIG_MMC_HS400_SUPPORT=y
 CONFIG_MMC_DW=y
 CONFIG_MMC_DW_SNPS=y
 CONFIG_MMC_SDHCI=y
-CONFIG_MMC_SDHCI_SNPS=y
 CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_MMC_SDHCI_SNPS=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_MMC_RPMB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
 CONFIG_SUPPORT_EMMC_RPMB=y
 CONFIG_DM_MTD=y
 CONFIG_MTD_SPI_NAND=y
 CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_ETH_DESIGNWARE=y
 CONFIG_PHY_REALTEK=y
 CONFIG_RTL8211E_PINE64_GIGABIT_FIX=y
 CONFIG_RTL8211X_PHY_FORCE_MASTER=y
 CONFIG_RTL8211F_PHY_FORCE_EEE_RXC_ON=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_PHY=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_DESIGNWARE_SPI=y
@@ -82,25 +87,15 @@ CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_MANUFACTURER="U-Boot-THEAD"
 CONFIG_USB_GADGET_VENDOR_NUM=0x1234
 CONFIG_USB_GADGET_PRODUCT_NUM=0x8888
-# CONFIG_SPL_USE_TINY_PRINTF is not set
-# CONFIG_EFI_LOADER is not set
-# CONFIG_LIGHT_SEC_BOOT is not set
-CONFIG_BOARD_LATE_INIT=y
-CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_USB_FUNCTION_MASS_STORAGE=y
 CONFIG_DM_VIDEO=y
-CONFIG_PHY=y
-CONFIG_REGMAP=y
-CONFIG_SYSCON=y
-CONFIG_CMD_BMP=y
-CONFIG_VIDEO_BRIDGE=y
-CONFIG_DM_PCA953X=y
-CONFIG_VIDEO_VS_DPU=y
+CONFIG_SYS_WHITE_ON_BLACK=y
 CONFIG_VIDEO_LCD_ILITEK_ILI9881C=y
+CONFIG_VIDEO_BRIDGE=y
+CONFIG_VIDEO_VS_DPU=y
 CONFIG_VIDEO_DW_DSI_LIGHT=y
 CONFIG_VIDEO_DW_DPHY=y
-CONFIG_VIDEO_DW_DSI_HOST=y
-CONFIG_SYS_WHITE_ON_BLACK=y
-CONFIG_PMIC_VOL_INIT=y
-CONFIG_DDR_REGU_0V6=600000
-CONFIG_DDR_REGU_0V8=800000
-CONFIG_DDR_REGU_1V1=1100000
+# CONFIG_SPL_USE_TINY_PRINTF is not set
+CONFIG_OF_LIBFDT_OVERLAY=y
+# CONFIG_EFI_LOADER is not set
+CONFIG_BOARD_RNG_SEED=y

configs/light_lpi4a_16g_defconfig

@@ -0,0 +1,111 @@
+CONFIG_RISCV=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_ENV_SIZE=0x20000
+CONFIG_ENV_OFFSET=0xe0000
+CONFIG_NR_DRAM_BANKS=8
+CONFIG_SPL=y
+CONFIG_SMP=y
+CONFIG_TARGET_LIGHT_C910=y
+CONFIG_TARGET_LIGHT_FM_C910_LPI4A=y
+# CONFIG_THEAD_PLIC is not set
+# CONFIG_THEAD_LIGHT_TIMER is not set
+# CONFIG_THEAD_LIGHT_DIGITAL_SENSOR is not set
+CONFIG_ARCH_RV64I=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_BUILD_TARGET="u-boot-with-spl.bin"
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_DISPLAY_BOARDINFO=y
+# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
+CONFIG_SPL_RAM_SUPPORT=y
+CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SYS_PROMPT="Light LPI4A 16G# "
+CONFIG_DDR_LP4X_3733_DUALRANK=y
+CONFIG_DDR_DDP=y
+# CONFIG_DDR_LP4_3733_DUALRANK is not set
+CONFIG_DDR_BOARD_CONFIG=y
+CONFIG_CMD_BOOT_SLAVE=y
+CONFIG_CMD_ERASEENV=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_DDR_SCAN=y
+CONFIG_DDR_PRBS_TEST=n
+# CONFIG_DOS_PARTITION is not set
+# CONFIG_ISO_PARTITION is not set
+CONFIG_PARTITION_TYPE_GUID=y
+CONFIG_OF_EMBED=y
+CONFIG_DEFAULT_DEVICE_TREE="light-lpi4a"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SPL_CLK=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_UDP_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x10000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_DW=y
+CONFIG_DWAPB_GPIO=y
+# CONFIG_MMC_SPI is not set
+CONFIG_MMC_VERBOSE=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_SNPS=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SNPS=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MMC_RPMB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_SPI_NAND=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_PHY_REALTEK=y
+CONFIG_RTL8211E_PINE64_GIGABIT_FIX=y
+CONFIG_RTL8211X_PHY_FORCE_MASTER=y
+CONFIG_RTL8211F_PHY_FORCE_EEE_RXC_ON=y
+CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_DESIGNWARE_SPI=y
+CONFIG_DESIGNWARE_QSPI=y
+CONFIG_USB=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="U-Boot-THEAD"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1234
+CONFIG_USB_GADGET_PRODUCT_NUM=0x8888
+CONFIG_USB_FUNCTION_MASS_STORAGE=y
+# CONFIG_SPL_USE_TINY_PRINTF is not set
+# CONFIG_EFI_LOADER is not set
+# CONFIG_LIGHT_SEC_BOOT is not set
+CONFIG_DEFAULT_FDT_FILE="thead/light-lpi4a-16gb.dtb"
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_DM_VIDEO=y
+CONFIG_PHY=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_CMD_BMP=y
+CONFIG_VIDEO_BRIDGE=y
+CONFIG_DM_PCA953X=y
+CONFIG_VIDEO_VS_DPU=y
+CONFIG_VIDEO_LCD_ILITEK_ILI9881C=y
+CONFIG_VIDEO_DW_DSI_LIGHT=y
+CONFIG_VIDEO_DW_DPHY=y
+CONFIG_VIDEO_DW_DSI_HOST=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_PMIC_VOL_INIT=y
+CONFIG_DDR_REGU_0V6=600000
+CONFIG_DDR_REGU_0V8=800000
+CONFIG_DDR_REGU_1V1=1100000
+CONFIG_BOARD_RNG_SEED=y

configs/light_lpi4a_android_defconfig

@@ -19,7 +19,6 @@ CONFIG_SYS_PROMPT="C910 Light# "
 CONFIG_DDR_LP4X_3733_DUALRANK=y
 # CONFIG_DDR_LP4_3733_DUALRANK is not set
 CONFIG_DDR_BOARD_CONFIG=y
-CONFIG_FIXUP_MEMORY_REGION=n
 CONFIG_CMD_BOOT_SLAVE=y
 CONFIG_CMD_ERASEENV=y
 CONFIG_CMD_GPT=y

configs/light_lpi4a_cluster_16g_defconfig

@@ -0,0 +1,111 @@
+CONFIG_RISCV=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_ENV_SIZE=0x20000
+CONFIG_ENV_OFFSET=0xe0000
+CONFIG_NR_DRAM_BANKS=8
+CONFIG_SPL=y
+CONFIG_SMP=y
+CONFIG_TARGET_LIGHT_C910=y
+CONFIG_TARGET_LIGHT_FM_C910_LPI4A=y
+# CONFIG_THEAD_PLIC is not set
+# CONFIG_THEAD_LIGHT_TIMER is not set
+# CONFIG_THEAD_LIGHT_DIGITAL_SENSOR is not set
+CONFIG_ARCH_RV64I=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_BUILD_TARGET="u-boot-with-spl.bin"
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_DISPLAY_BOARDINFO=y
+# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
+CONFIG_SPL_RAM_SUPPORT=y
+CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SYS_PROMPT="LicheeCluster4A 16G # "
+CONFIG_DDR_LP4X_3733_DUALRANK=y
+CONFIG_DDR_DDP=y
+# CONFIG_DDR_LP4_3733_DUALRANK is not set
+CONFIG_DDR_BOARD_CONFIG=y
+CONFIG_CMD_BOOT_SLAVE=y
+CONFIG_CMD_ERASEENV=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_DDR_SCAN=y
+CONFIG_DDR_PRBS_TEST=n
+# CONFIG_DOS_PARTITION is not set
+# CONFIG_ISO_PARTITION is not set
+CONFIG_PARTITION_TYPE_GUID=y
+CONFIG_OF_EMBED=y
+CONFIG_DEFAULT_DEVICE_TREE="light-lpi4a"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SPL_CLK=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_UDP_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x10000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_DW=y
+CONFIG_DWAPB_GPIO=y
+# CONFIG_MMC_SPI is not set
+CONFIG_MMC_VERBOSE=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_SNPS=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SNPS=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MMC_RPMB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_SPI_NAND=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_PHY_REALTEK=y
+CONFIG_RTL8211E_PINE64_GIGABIT_FIX=y
+CONFIG_RTL8211X_PHY_FORCE_MASTER=y
+CONFIG_RTL8211F_PHY_FORCE_EEE_RXC_ON=y
+CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_DESIGNWARE_SPI=y
+CONFIG_DESIGNWARE_QSPI=y
+CONFIG_USB=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="U-Boot-THEAD"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1234
+CONFIG_USB_GADGET_PRODUCT_NUM=0x8888
+CONFIG_USB_FUNCTION_MASS_STORAGE=y
+# CONFIG_SPL_USE_TINY_PRINTF is not set
+# CONFIG_EFI_LOADER is not set
+# CONFIG_LIGHT_SEC_BOOT is not set
+CONFIG_DEFAULT_FDT_FILE="thead/light-lpi4a-cluster-16gb.dtb"
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_DM_VIDEO=y
+CONFIG_PHY=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_CMD_BMP=y
+CONFIG_VIDEO_BRIDGE=y
+CONFIG_DM_PCA953X=y
+CONFIG_VIDEO_VS_DPU=y
+CONFIG_VIDEO_LCD_ILITEK_ILI9881C=y
+CONFIG_VIDEO_DW_DSI_LIGHT=y
+CONFIG_VIDEO_DW_DPHY=y
+CONFIG_VIDEO_DW_DSI_HOST=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_PMIC_VOL_INIT=y
+CONFIG_DDR_REGU_0V6=600000
+CONFIG_DDR_REGU_0V8=800000
+CONFIG_DDR_REGU_1V1=1100000
+CONFIG_BOARD_RNG_SEED=y

configs/light_lpi4a_cluster_defconfig

@@ -0,0 +1,110 @@
+CONFIG_RISCV=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_ENV_SIZE=0x20000
+CONFIG_ENV_OFFSET=0xe0000
+CONFIG_NR_DRAM_BANKS=8
+CONFIG_SPL=y
+CONFIG_SMP=y
+CONFIG_TARGET_LIGHT_C910=y
+CONFIG_TARGET_LIGHT_FM_C910_LPI4A=y
+# CONFIG_THEAD_PLIC is not set
+# CONFIG_THEAD_LIGHT_TIMER is not set
+# CONFIG_THEAD_LIGHT_DIGITAL_SENSOR is not set
+CONFIG_ARCH_RV64I=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_BUILD_TARGET="u-boot-with-spl.bin"
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_DISPLAY_BOARDINFO=y
+# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
+CONFIG_SPL_RAM_SUPPORT=y
+CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SYS_PROMPT="LicheeCluster4A # "
+CONFIG_DDR_LP4X_3733_DUALRANK=y
+# CONFIG_DDR_LP4_3733_DUALRANK is not set
+CONFIG_DDR_BOARD_CONFIG=y
+CONFIG_CMD_BOOT_SLAVE=y
+CONFIG_CMD_ERASEENV=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_DDR_SCAN=y
+CONFIG_DDR_PRBS_TEST=n
+# CONFIG_DOS_PARTITION is not set
+# CONFIG_ISO_PARTITION is not set
+CONFIG_PARTITION_TYPE_GUID=y
+CONFIG_OF_EMBED=y
+CONFIG_DEFAULT_DEVICE_TREE="light-lpi4a"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SPL_CLK=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_UDP_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x10000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_DW=y
+CONFIG_DWAPB_GPIO=y
+# CONFIG_MMC_SPI is not set
+CONFIG_MMC_VERBOSE=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_SNPS=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SNPS=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MMC_RPMB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_SPI_NAND=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_PHY_REALTEK=y
+CONFIG_RTL8211E_PINE64_GIGABIT_FIX=y
+CONFIG_RTL8211X_PHY_FORCE_MASTER=y
+CONFIG_RTL8211F_PHY_FORCE_EEE_RXC_ON=y
+CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_DESIGNWARE_SPI=y
+CONFIG_DESIGNWARE_QSPI=y
+CONFIG_USB=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="U-Boot-THEAD"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1234
+CONFIG_USB_GADGET_PRODUCT_NUM=0x8888
+CONFIG_USB_FUNCTION_MASS_STORAGE=y
+# CONFIG_SPL_USE_TINY_PRINTF is not set
+# CONFIG_EFI_LOADER is not set
+# CONFIG_LIGHT_SEC_BOOT is not set
+CONFIG_DEFAULT_FDT_FILE="thead/light-lpi4a-cluster.dtb"
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_DM_VIDEO=y
+CONFIG_PHY=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_CMD_BMP=y
+CONFIG_VIDEO_BRIDGE=y
+CONFIG_DM_PCA953X=y
+CONFIG_VIDEO_VS_DPU=y
+CONFIG_VIDEO_LCD_ILITEK_ILI9881C=y
+CONFIG_VIDEO_DW_DSI_LIGHT=y
+CONFIG_VIDEO_DW_DPHY=y
+CONFIG_VIDEO_DW_DSI_HOST=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_PMIC_VOL_INIT=y
+CONFIG_DDR_REGU_0V6=600000
+CONFIG_DDR_REGU_0V8=800000
+CONFIG_DDR_REGU_1V1=1100000
+CONFIG_BOARD_RNG_SEED=y

configs/light_lpi4a_console_16g_defconfig

@@ -0,0 +1,111 @@
+CONFIG_RISCV=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_ENV_SIZE=0x20000
+CONFIG_ENV_OFFSET=0xe0000
+CONFIG_NR_DRAM_BANKS=8
+CONFIG_SPL=y
+CONFIG_SMP=y
+CONFIG_TARGET_LIGHT_C910=y
+CONFIG_TARGET_LIGHT_FM_C910_LPI4A=y
+# CONFIG_THEAD_PLIC is not set
+# CONFIG_THEAD_LIGHT_TIMER is not set
+# CONFIG_THEAD_LIGHT_DIGITAL_SENSOR is not set
+CONFIG_ARCH_RV64I=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_BUILD_TARGET="u-boot-with-spl.bin"
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_DISPLAY_BOARDINFO=y
+# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
+CONFIG_SPL_RAM_SUPPORT=y
+CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SYS_PROMPT="LicheeConsole4A 16G # "
+CONFIG_DDR_LP4X_3733_DUALRANK=y
+CONFIG_DDR_DDP=y
+# CONFIG_DDR_LP4_3733_DUALRANK is not set
+CONFIG_DDR_BOARD_CONFIG=y
+CONFIG_CMD_BOOT_SLAVE=y
+CONFIG_CMD_ERASEENV=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_DDR_SCAN=y
+CONFIG_DDR_PRBS_TEST=n
+# CONFIG_DOS_PARTITION is not set
+# CONFIG_ISO_PARTITION is not set
+CONFIG_PARTITION_TYPE_GUID=y
+CONFIG_OF_EMBED=y
+CONFIG_DEFAULT_DEVICE_TREE="light-lpi4a-laptop"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SPL_CLK=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_UDP_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x10000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_DW=y
+CONFIG_DWAPB_GPIO=y
+# CONFIG_MMC_SPI is not set
+CONFIG_MMC_VERBOSE=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_SNPS=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SNPS=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MMC_RPMB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_SPI_NAND=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_PHY_REALTEK=y
+CONFIG_RTL8211E_PINE64_GIGABIT_FIX=y
+CONFIG_RTL8211X_PHY_FORCE_MASTER=y
+CONFIG_RTL8211F_PHY_FORCE_EEE_RXC_ON=y
+CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_DESIGNWARE_SPI=y
+CONFIG_DESIGNWARE_QSPI=y
+CONFIG_USB=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="U-Boot-THEAD"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1234
+CONFIG_USB_GADGET_PRODUCT_NUM=0x8888
+CONFIG_USB_FUNCTION_MASS_STORAGE=y
+# CONFIG_SPL_USE_TINY_PRINTF is not set
+# CONFIG_EFI_LOADER is not set
+# CONFIG_LIGHT_SEC_BOOT is not set
+CONFIG_DEFAULT_FDT_FILE="thead/light-lpi4a-console-16g.dtb"
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_DM_VIDEO=y
+CONFIG_PHY=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_CMD_BMP=y
+CONFIG_VIDEO_BRIDGE=y
+CONFIG_DM_PCA953X=y
+CONFIG_VIDEO_VS_DPU=y
+CONFIG_VIDEO_LCD_ILITEK_ILI9881C=y
+CONFIG_VIDEO_DW_DSI_LIGHT=y
+CONFIG_VIDEO_DW_DPHY=y
+CONFIG_VIDEO_DW_DSI_HOST=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_PMIC_VOL_INIT=y
+CONFIG_DDR_REGU_0V6=600000
+CONFIG_DDR_REGU_0V8=800000
+CONFIG_DDR_REGU_1V1=1100000
+CONFIG_BOARD_RNG_SEED=y

configs/light_lpi4a_console_defconfig

@@ -0,0 +1,110 @@
+CONFIG_RISCV=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_ENV_SIZE=0x20000
+CONFIG_ENV_OFFSET=0xe0000
+CONFIG_NR_DRAM_BANKS=8
+CONFIG_SPL=y
+CONFIG_SMP=y
+CONFIG_TARGET_LIGHT_C910=y
+CONFIG_TARGET_LIGHT_FM_C910_LPI4A=y
+# CONFIG_THEAD_PLIC is not set
+# CONFIG_THEAD_LIGHT_TIMER is not set
+# CONFIG_THEAD_LIGHT_DIGITAL_SENSOR is not set
+CONFIG_ARCH_RV64I=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_BUILD_TARGET="u-boot-with-spl.bin"
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_DISPLAY_BOARDINFO=y
+# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
+CONFIG_SPL_RAM_SUPPORT=y
+CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SYS_PROMPT="LicheeConsole4A # "
+CONFIG_DDR_LP4X_3733_DUALRANK=y
+# CONFIG_DDR_LP4_3733_DUALRANK is not set
+CONFIG_DDR_BOARD_CONFIG=y
+CONFIG_CMD_BOOT_SLAVE=y
+CONFIG_CMD_ERASEENV=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_DDR_SCAN=y
+CONFIG_DDR_PRBS_TEST=n
+# CONFIG_DOS_PARTITION is not set
+# CONFIG_ISO_PARTITION is not set
+CONFIG_PARTITION_TYPE_GUID=y
+CONFIG_OF_EMBED=y
+CONFIG_DEFAULT_DEVICE_TREE="light-lpi4a-laptop"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SPL_CLK=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_UDP_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x10000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_DW=y
+CONFIG_DWAPB_GPIO=y
+# CONFIG_MMC_SPI is not set
+CONFIG_MMC_VERBOSE=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_SNPS=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SNPS=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MMC_RPMB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_SPI_NAND=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_PHY_REALTEK=y
+CONFIG_RTL8211E_PINE64_GIGABIT_FIX=y
+CONFIG_RTL8211X_PHY_FORCE_MASTER=y
+CONFIG_RTL8211F_PHY_FORCE_EEE_RXC_ON=y
+CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_DESIGNWARE_SPI=y
+CONFIG_DESIGNWARE_QSPI=y
+CONFIG_USB=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="U-Boot-THEAD"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1234
+CONFIG_USB_GADGET_PRODUCT_NUM=0x8888
+CONFIG_USB_FUNCTION_MASS_STORAGE=y
+# CONFIG_SPL_USE_TINY_PRINTF is not set
+# CONFIG_EFI_LOADER is not set
+# CONFIG_LIGHT_SEC_BOOT is not set
+CONFIG_DEFAULT_FDT_FILE="thead/light-lpi4a-console.dtb"
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_DM_VIDEO=y
+CONFIG_PHY=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_CMD_BMP=y
+CONFIG_VIDEO_BRIDGE=y
+CONFIG_DM_PCA953X=y
+CONFIG_VIDEO_VS_DPU=y
+CONFIG_VIDEO_LCD_ILITEK_ILI9881C=y
+CONFIG_VIDEO_DW_DSI_LIGHT=y
+CONFIG_VIDEO_DW_DPHY=y
+CONFIG_VIDEO_DW_DSI_HOST=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_PMIC_VOL_INIT=y
+CONFIG_DDR_REGU_0V6=600000
+CONFIG_DDR_REGU_0V8=800000
+CONFIG_DDR_REGU_1V1=1100000
+CONFIG_BOARD_RNG_SEED=y

configs/light_lpi4a_defconfig

@@ -18,11 +18,10 @@ CONFIG_DISPLAY_BOARDINFO=y
 # CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
 CONFIG_SPL_RAM_SUPPORT=y
 CONFIG_SPL_RAM_DEVICE=y
-CONFIG_SYS_PROMPT="C910 Light# "
+CONFIG_SYS_PROMPT="Light LPI4A# "
 CONFIG_DDR_LP4X_3733_DUALRANK=y
 # CONFIG_DDR_LP4_3733_DUALRANK is not set
 CONFIG_DDR_BOARD_CONFIG=y
-CONFIG_FIXUP_MEMORY_REGION=y
 CONFIG_CMD_BOOT_SLAVE=y
 CONFIG_CMD_ERASEENV=y
 CONFIG_CMD_GPT=y
@@ -33,6 +32,7 @@ CONFIG_CMD_I2C=y
 CONFIG_CMD_MEMTEST=y
 CONFIG_DDR_SCAN=y
 CONFIG_DDR_PRBS_TEST=n
+# CONFIG_DOS_PARTITION is not set
 # CONFIG_ISO_PARTITION is not set
 CONFIG_PARTITION_TYPE_GUID=y
 CONFIG_OF_EMBED=y
@@ -63,6 +63,7 @@ CONFIG_MMC_SDHCI_SNPS=y
 CONFIG_MMC_SDHCI_SDMA=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_MMC_RPMB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
 CONFIG_SUPPORT_EMMC_RPMB=y
 CONFIG_DM_MTD=y
 CONFIG_MTD_SPI_NAND=y
@@ -77,17 +78,16 @@ CONFIG_SPI=y
 CONFIG_DESIGNWARE_SPI=y
 CONFIG_DESIGNWARE_QSPI=y
 CONFIG_USB=y
-CONFIG_DM_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_DWC3=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_MANUFACTURER="U-Boot-THEAD"
 CONFIG_USB_GADGET_VENDOR_NUM=0x1234
 CONFIG_USB_GADGET_PRODUCT_NUM=0x8888
+CONFIG_USB_FUNCTION_MASS_STORAGE=y
 # CONFIG_SPL_USE_TINY_PRINTF is not set
 # CONFIG_EFI_LOADER is not set
 # CONFIG_LIGHT_SEC_BOOT is not set
+CONFIG_DEFAULT_FDT_FILE="thead/light-lpi4a.dtb"
 CONFIG_BOARD_LATE_INIT=y
 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
 CONFIG_DM_VIDEO=y
@@ -95,13 +95,10 @@ CONFIG_PHY=y
 CONFIG_REGMAP=y
 CONFIG_SYSCON=y
 CONFIG_CMD_BMP=y
-CONFIG_CMD_USB=y
 CONFIG_VIDEO_BRIDGE=y
 CONFIG_DM_PCA953X=y
 CONFIG_VIDEO_VS_DPU=y
-CONFIG_VIDEO_LCD_ILITEK_ILI9881C=n
-CONFIG_VIDEO_LCD_JD9365DA=y
-CONFIG_VIDEO_LCD_CUSTOM_LOGO=y
+CONFIG_VIDEO_LCD_ILITEK_ILI9881C=y
 CONFIG_VIDEO_DW_DSI_LIGHT=y
 CONFIG_VIDEO_DW_DPHY=y
 CONFIG_VIDEO_DW_DSI_HOST=y
@@ -110,6 +107,4 @@ CONFIG_PMIC_VOL_INIT=y
 CONFIG_DDR_REGU_0V6=600000
 CONFIG_DDR_REGU_0V8=800000
 CONFIG_DDR_REGU_1V1=1100000
-CONFIG_MISC=y
-CONFIG_LIGHT_AON_CONF=y
-
+CONFIG_BOARD_RNG_SEED=y

configs/light_lpi4a_sec_defconfig

@@ -22,7 +22,6 @@ CONFIG_SYS_PROMPT="C910 Light# "
 CONFIG_DDR_LP4X_3733_DUALRANK=y
 # CONFIG_DDR_LP4_3733_DUALRANK is not set
 CONFIG_DDR_BOARD_CONFIG=y
-CONFIG_FIXUP_MEMORY_REGION=y
 CONFIG_CMD_BOOT_SLAVE=y
 CONFIG_CMD_ERASEENV=y
 CONFIG_CMD_GPT=y
@@ -33,6 +32,7 @@ CONFIG_CMD_I2C=y
 CONFIG_CMD_MEMTEST=y
 CONFIG_DDR_SCAN=y
 CONFIG_DDR_PRBS_TEST=n
+# CONFIG_DOS_PARTITION is not set
 # CONFIG_ISO_PARTITION is not set
 CONFIG_PARTITION_TYPE_GUID=y
 CONFIG_OF_EMBED=y
@@ -77,9 +77,6 @@ CONFIG_SPI=y
 CONFIG_DESIGNWARE_SPI=y
 CONFIG_DESIGNWARE_QSPI=y
 CONFIG_USB=y
-CONFIG_DM_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_DWC3=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_MANUFACTURER="U-Boot-THEAD"
@@ -96,13 +93,10 @@ CONFIG_PHY=y
 CONFIG_REGMAP=y
 CONFIG_SYSCON=y
 CONFIG_CMD_BMP=y
-CONFIG_CMD_USB=y
 CONFIG_VIDEO_BRIDGE=y
 CONFIG_DM_PCA953X=y
 CONFIG_VIDEO_VS_DPU=y
-CONFIG_VIDEO_LCD_ILITEK_ILI9881C=n
-CONFIG_VIDEO_LCD_JD9365DA=y
-CONFIG_VIDEO_LCD_CUSTOM_LOGO=y
+CONFIG_VIDEO_LCD_ILITEK_ILI9881C=y
 CONFIG_VIDEO_DW_DSI_LIGHT=y
 CONFIG_VIDEO_DW_DPHY=y
 CONFIG_VIDEO_DW_DSI_HOST=y
@@ -111,5 +105,3 @@ CONFIG_PMIC_VOL_INIT=y
 CONFIG_DDR_REGU_0V6=600000
 CONFIG_DDR_REGU_0V8=800000
 CONFIG_DDR_REGU_1V1=1100000
-CONFIG_MISC=y
-CONFIG_LIGHT_AON_CONF=y

configs/light_milkv_meles_defconfig

@@ -0,0 +1,89 @@
+CONFIG_RISCV=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_ENV_SIZE=0x20000
+CONFIG_ENV_OFFSET=0xe0000
+CONFIG_NR_DRAM_BANKS=8
+CONFIG_SPL=y
+CONFIG_SMP=y
+CONFIG_TARGET_LIGHT_C910=y
+CONFIG_PMIC_VOL_INIT=y
+CONFIG_TARGET_LIGHT_FM_C910_MILKV_MELES=y
+CONFIG_DDR_LP4X_3733_SINGLERANK=y
+CONFIG_DDR_BOARD_CONFIG=y
+CONFIG_ARCH_RV64I=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_BUILD_TARGET="u-boot-with-spl.bin"
+CONFIG_DEFAULT_FDT_FILE="thead/th1520-milkv-meles.dtb"
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_DISPLAY_BOARDINFO=y
+# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
+CONFIG_SPL_RAM_SUPPORT=y
+CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SYS_PROMPT="Milk-V Meles# "
+CONFIG_CMD_BOOT_SLAVE=y
+CONFIG_CMD_ERASEENV=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_DDR_SCAN=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_EXT4_WRITE=y
+# CONFIG_DOS_PARTITION is not set
+# CONFIG_ISO_PARTITION is not set
+CONFIG_PARTITION_TYPE_GUID=y
+CONFIG_OF_EMBED=y
+CONFIG_DEFAULT_DEVICE_TREE="light-milkv-meles"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_SPL_CLK=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_UDP_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x10000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_DM_GPIO=y
+CONFIG_DWAPB_GPIO=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_DW=y
+# CONFIG_MMC_SPI is not set
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_SNPS=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_MMC_SDHCI_SNPS=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_SPI_NAND=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_PHY_REALTEK=y
+CONFIG_RTL8211E_PINE64_GIGABIT_FIX=y
+CONFIG_RTL8211X_PHY_FORCE_MASTER=y
+CONFIG_RTL8211F_PHY_FORCE_EEE_RXC_ON=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_PHY=y
+CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_DESIGNWARE_SPI=y
+CONFIG_DESIGNWARE_QSPI=y
+CONFIG_USB=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="U-Boot-THEAD"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1234
+CONFIG_USB_GADGET_PRODUCT_NUM=0x8888
+CONFIG_SYS_WHITE_ON_BLACK=y
+# CONFIG_SPL_USE_TINY_PRINTF is not set
+CONFIG_OF_LIBFDT_OVERLAY=y
+# CONFIG_EFI_LOADER is not set

configs/light_milkv_meles_dualrank_defconfig

@@ -0,0 +1,90 @@
+CONFIG_RISCV=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_ENV_SIZE=0x20000
+CONFIG_ENV_OFFSET=0xe0000
+CONFIG_NR_DRAM_BANKS=8
+CONFIG_SPL=y
+CONFIG_SMP=y
+CONFIG_TARGET_LIGHT_C910=y
+CONFIG_PMIC_VOL_INIT=y
+CONFIG_TARGET_LIGHT_FM_C910_MILKV_MELES=y
+CONFIG_DDR_LP4X_3733_DUALRANK=y
+CONFIG_DDR_BOARD_CONFIG=y
+CONFIG_ARCH_RV64I=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_BUILD_TARGET="u-boot-with-spl.bin"
+CONFIG_DEFAULT_FDT_FILE="thead/th1520-milkv-meles.dtb"
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_DISPLAY_BOARDINFO=y
+# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
+CONFIG_SPL_RAM_SUPPORT=y
+CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SYS_PROMPT="Milk-V Meles# "
+CONFIG_CMD_BOOT_SLAVE=y
+CONFIG_CMD_ERASEENV=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_DDR_SCAN=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_EXT4_WRITE=y
+# CONFIG_DOS_PARTITION is not set
+# CONFIG_ISO_PARTITION is not set
+CONFIG_PARTITION_TYPE_GUID=y
+CONFIG_OF_EMBED=y
+CONFIG_DEFAULT_DEVICE_TREE="light-milkv-meles"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_SPL_CLK=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_UDP_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x10000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_DM_GPIO=y
+CONFIG_DWAPB_GPIO=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_DW=y
+# CONFIG_MMC_SPI is not set
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_SNPS=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_MMC_SDHCI_SNPS=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_SPI_NAND=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_PHY_REALTEK=y
+CONFIG_RTL8211E_PINE64_GIGABIT_FIX=y
+CONFIG_RTL8211X_PHY_FORCE_MASTER=y
+CONFIG_RTL8211F_PHY_FORCE_EEE_RXC_ON=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_PHY=y
+CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_DESIGNWARE_SPI=y
+CONFIG_DESIGNWARE_QSPI=y
+CONFIG_USB=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="U-Boot-THEAD"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1234
+CONFIG_USB_GADGET_PRODUCT_NUM=0x8888
+CONFIG_SYS_WHITE_ON_BLACK=y
+# CONFIG_SPL_USE_TINY_PRINTF is not set
+CONFIG_OF_LIBFDT_OVERLAY=y
+# CONFIG_EFI_LOADER is not set
+CONFIG_BOARD_RNG_SEED=y

configs/light_milkv_meles_singlerank_defconfig

@@ -0,0 +1,90 @@
+CONFIG_RISCV=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_ENV_SIZE=0x20000
+CONFIG_ENV_OFFSET=0xe0000
+CONFIG_NR_DRAM_BANKS=8
+CONFIG_SPL=y
+CONFIG_SMP=y
+CONFIG_TARGET_LIGHT_C910=y
+CONFIG_PMIC_VOL_INIT=y
+CONFIG_TARGET_LIGHT_FM_C910_MILKV_MELES=y
+CONFIG_DDR_LP4X_3733_SINGLERANK=y
+CONFIG_DDR_BOARD_CONFIG=y
+CONFIG_ARCH_RV64I=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_BUILD_TARGET="u-boot-with-spl.bin"
+CONFIG_DEFAULT_FDT_FILE="thead/th1520-milkv-meles-4g.dtb"
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_DISPLAY_BOARDINFO=y
+# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
+CONFIG_SPL_RAM_SUPPORT=y
+CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SYS_PROMPT="Milk-V Meles 4G# "
+CONFIG_CMD_BOOT_SLAVE=y
+CONFIG_CMD_ERASEENV=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_DDR_SCAN=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_EXT4_WRITE=y
+# CONFIG_DOS_PARTITION is not set
+# CONFIG_ISO_PARTITION is not set
+CONFIG_PARTITION_TYPE_GUID=y
+CONFIG_OF_EMBED=y
+CONFIG_DEFAULT_DEVICE_TREE="light-milkv-meles"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_SPL_CLK=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_UDP_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x10000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_DM_GPIO=y
+CONFIG_DWAPB_GPIO=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_DW=y
+# CONFIG_MMC_SPI is not set
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_SNPS=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_MMC_SDHCI_SNPS=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_SPI_NAND=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_PHY_REALTEK=y
+CONFIG_RTL8211E_PINE64_GIGABIT_FIX=y
+CONFIG_RTL8211X_PHY_FORCE_MASTER=y
+CONFIG_RTL8211F_PHY_FORCE_EEE_RXC_ON=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_PHY=y
+CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_DESIGNWARE_SPI=y
+CONFIG_DESIGNWARE_QSPI=y
+CONFIG_USB=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="U-Boot-THEAD"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1234
+CONFIG_USB_GADGET_PRODUCT_NUM=0x8888
+CONFIG_SYS_WHITE_ON_BLACK=y
+# CONFIG_SPL_USE_TINY_PRINTF is not set
+CONFIG_OF_LIBFDT_OVERLAY=y
+# CONFIG_EFI_LOADER is not set
+CONFIG_BOARD_RNG_SEED=y

configs/tools-only_defconfig

@@ -6,6 +6,7 @@ CONFIG_FIT_SIGNATURE=y
 # CONFIG_CMD_BOOTD is not set
 # CONFIG_CMD_BOOTM is not set
 # CONFIG_CMD_ELF is not set
+# CONFIG_CMD_EXTENSION is not set
 # CONFIG_CMD_DATE is not set
 CONFIG_OF_CONTROL=y
 CONFIG_OF_HOSTFILE=y

doc/README.pxe

@@ -89,6 +89,9 @@ pxe boot
      fdt_addr - the location of a fdt blob. 'fdt_addr' will be passed to bootm
      command if it is set and 'fdt_addr_r' is not passed to bootm command.
 
+     fdtoverlay_addr_r - location in RAM at which 'pxe boot' will temporarily store
+     fdt overlay(s) before applying them to the fdt blob stored at 'fdt_addr_r'.
+
 pxe file format
 ===============
 The pxe file format is nearly a subset of the PXELINUX file format; see
@@ -148,6 +151,12 @@ kernel <path>	    - if this label is chosen, use tftp to retrieve the kernel
 		      It useful for overlay selection in pxe file
 		      (see: doc/uImage.FIT/overlay-fdt-boot.txt)
 
+fdtoverlays <path> [...] - if this label is chosen, use tftp to retrieve the DT
+                      overlay(s) at <path>. it will be temporarily stored at the
+                      address indicated in the fdtoverlay_addr_r environment variable,
+                      and then applied in the load order to the fdt blob stored at the
+                      address indicated in the fdt_addr_r environment variable.
+
 append <string>	    - use <string> as the kernel command line when booting this
 		      label.
 

doc/usage/extension.rst

@@ -0,0 +1,111 @@
+.. SPDX-License-Identifier: GPL-2.0+
+.. Copyright 2021, Kory Maincent <kory.maincent@bootlin.com>
+
+U-Boot extension board usage (CONFIG_EXTENSION)
+===============================================
+
+Synopsis
+--------
+
+::
+
+    extension scan
+    extension list
+    extension apply <extension number|all>
+
+Description
+-----------
+
+The "extension" command proposes a generic U-Boot mechanism to detect
+extension boards connected to the HW platform, and apply the appropriate
+Device Tree overlays depending on the detected extension boards.
+
+The "extension" command comes with three sub-commands:
+
+ - "extension scan" makes the generic code call the board-specific
+   extension_board_scan() function to retrieve the list of detected
+   extension boards.
+
+ - "extension list" allows to list the detected extension boards.
+
+ - "extension apply <number>|all" allows to apply the Device Tree
+   overlay(s) corresponding to one, or all, extension boards
+
+The latter requires two environment variables to exist:
+
+ - extension_overlay_addr: the RAM address where to load the Device
+   Tree overlays
+
+ - extension_overlay_cmd: the U-Boot command to load one overlay.
+   Indeed, the location and mechanism to load DT overlays is very setup
+   specific.
+
+In order to enable this mechanism, board-specific code must implement
+the extension_board_scan() function that fills in a linked list of
+"struct extension", each describing one extension board. In addition,
+the board-specific code must select the SUPPORT_EXTENSION_SCAN Kconfig
+boolean.
+
+Usage example
+-------------
+
+1. Make sure your devicetree is loaded and set as the working fdt tree.
+
+::
+
+    => run loadfdt
+    => fdt addr $fdtaddr
+
+2. Prepare the environment variables
+
+::
+
+    => setenv extension_overlay_addr 0x88080000
+    => setenv extension_overlay_cmd 'load mmc 0:1 ${extension_overlay_addr} /boot/${extension_overlay_name}'
+
+3. Detect the plugged extension board
+
+::
+
+    => extension scan
+
+4. List the plugged extension board information and the devicetree
+   overlay name
+
+::
+
+    => extension list
+
+5. Apply the appropriate devicetree overlay
+
+For apply the selected overlay:
+
+::
+
+    => extension apply 0
+
+For apply all the overlays:
+
+::
+
+    => extension apply all
+
+Simple extension_board_scan function example
+--------------------------------------------
+
+.. code-block:: c
+
+    int extension_board_scan(struct list_head *extension_list)
+    {
+        struct extension *extension;
+
+        extension = calloc(1, sizeof(struct extension));
+        snprintf(extension->overlay, sizeof(extension->overlay), "overlay.dtbo");
+        snprintf(extension->name, sizeof(extension->name), "extension board");
+        snprintf(extension->owner, sizeof(extension->owner), "sandbox");
+        snprintf(extension->version, sizeof(extension->version), "1.1");
+        snprintf(extension->other, sizeof(extension->other), "Extension board information");
+        list_add_tail(&extension->list, extension_list);
+
+        return 1;
+    }

drivers/fastboot/fb_command.c

@@ -310,7 +310,6 @@ static void flash(char *cmd_parameter, char *response)
 	char cmdbuf[32];
 	u32 block_cnt;
 	struct blk_desc *dev_desc;
-	disk_partition_t info;
 	int ret = 0;
 
 	if (strcmp(cmd_parameter, "uboot") == 0) {
@@ -352,25 +351,8 @@ static void flash(char *cmd_parameter, char *response)
 		memcpy((void *)LIGHT_TF_FW_ADDR, fastboot_buf_addr, image_size);
 	} else if ((strcmp(cmd_parameter, TEE_PART_NAME) == 0)) {
 		memcpy((void *)LIGHT_TEE_FW_ADDR, fastboot_buf_addr, image_size);
-	} else if ((strcmp(cmd_parameter, "boot") == 0)) {
-		dev_desc = blk_get_dev("mmc", CONFIG_FASTBOOT_FLASH_MMC_DEV);
-		if (!dev_desc || dev_desc->type == DEV_TYPE_UNKNOWN) {
-			fastboot_fail("invalid mmc device", response);
-			return;
-        }
-		/* if fastresume partition exists, earse the old image header */
-		if(part_get_info_by_name(dev_desc, "fastresume", &info)) {
-			printf(" find fastresume partition , erase the header:\n");
-			char * buf = memalign(CONFIG_SYS_CACHELINE_SIZE,4096);
-			if(!buf) {
-				printf(" fastresume partition header mem alloc failed\n");
-				return;
-			}
-			memset(buf,0xff,4096);
-			blk_dwrite(dev_desc, info.start, 4096/info.blksz, buf);
-			free(buf);
-		}
 	}
+
 	if(strcmp(cmd_parameter, "uboot") == 0 || (strcmp(cmd_parameter, "fw") == 0) ||
 	   (strcmp(cmd_parameter, "uImage") == 0) || (strcmp(cmd_parameter, "dtb") == 0) ||
 	   (strcmp(cmd_parameter, "rootfs") == 0) || (strcmp(cmd_parameter, "aon") == 0)) {

drivers/misc/Kconfig

@@ -439,10 +439,4 @@ config K3_AVS0
 	  optimized voltage from the efuse, so that it can be programmed
 	  to the PMIC on board.
 
-config LIGHT_AON_CONF
-	bool "Light aon config support"
-	depends on MISC
-	help
-	  Select this to enable aon config by dts.
-
 endmenu

drivers/misc/Makefile

@@ -68,4 +68,3 @@ obj-$(CONFIG_WINBOND_W83627) += winbond_w83627.o
 obj-$(CONFIG_JZ4780_EFUSE) += jz4780_efuse.o
 obj-$(CONFIG_MICROCHIP_FLEXCOM) += microchip_flexcom.o
 obj-$(CONFIG_K3_AVS0) += k3_avs.o
-obj-$(CONFIG_LIGHT_AON_CONF) += light_regu.o

drivers/misc/light_regu.c

@@ -1,975 +0,0 @@
-#include <common.h>
-#include <asm/gpio.h>
-#include <misc.h>
-#include <dm.h>
-#include <linux/bitops.h>
-#include <linux/delay.h>
-#include <command.h>
-#include "light_regu.h"
-
-#define FDT32_TO_CPU(x) (fdt32_to_cpu(x))
-
-#ifndef ARRAY_SIZE
-#define ARRAY_SIZE(x) (szieof(x) / sizeof(x[0]))
-#endif
-
-#ifndef MIN
-#define MIN(x, y) ((x) < (y) ? (x) : (y))
-#endif
-
-#ifdef AON_CONF_DEBUG
-#define AON_CONF_D(fmt, args...)  printf(fmt,##args)
-#else
-#define AON_CONF_D(fmt, args...)
-#endif
-
-#define SOC_VIRTUAL_ID(virtual_id)      \
-	{                                   \
-		.id = virtual_id,               \
-		.virtual_id_name = #virtual_id, \
-	}
-
-soc_virtual_id_t soc_base_virtual_id_list[] = {
-	SOC_VIRTUAL_ID(SOC_DVDD18_AON),		  /*da9063:  ldo-3 */
-	SOC_VIRTUAL_ID(SOC_AVDD33_USB3),	  /*da9063:  ldo-9 */
-	SOC_VIRTUAL_ID(SOC_DVDD08_AON),		  /*da9063:  ldo-2 */
-	SOC_VIRTUAL_ID(SOC_APCPU_DVDD_DVDDM), /*da9063:  vbcore1 & vbcore2*/
-	SOC_VIRTUAL_ID(SOC_DVDD08_DDR),		  /*da9063:  buckperi */
-	SOC_VIRTUAL_ID(SOC_VDD_DDR_1V8),	  /*da9063:  ldo-4  */
-	SOC_VIRTUAL_ID(SOC_VDD_DDR_1V1),	  /*da9063:  buckmem & buckio  */
-	SOC_VIRTUAL_ID(SOC_VDD_DDR_0V6),	  /*da9063:  buckpro */
-	SOC_VIRTUAL_ID(SOC_DVDD18_AP),		  /*da9063:  ldo-11 */
-	SOC_VIRTUAL_ID(SOC_DVDD08_AP),		  /*da9121:  da9121_ex */
-	SOC_VIRTUAL_ID(SOC_AVDD08_MIPI_HDMI), /*da9063:  ldo-1  */
-	SOC_VIRTUAL_ID(SOC_AVDD18_MIPI_HDMI), /*da9063:  ldo-5  */
-	SOC_VIRTUAL_ID(SOC_DVDD33_EMMC),	  /*da9063:  ldo-10 */
-	SOC_VIRTUAL_ID(SOC_DVDD18_EMMC),	  /*slg51000:ldo-3 */
-	SOC_VIRTUAL_ID(SOC_DOVDD18_SCAN),	  /*da9063:  ldo-6 */
-	SOC_VIRTUAL_ID(SOC_VEXT_2V8),		  /*da9063:  ldo-7 */
-	SOC_VIRTUAL_ID(SOC_DVDD12_SCAN),	  /*da9063:  ldo-8 */
-	SOC_VIRTUAL_ID(SOC_AVDD28_SCAN_EN),	  /*da9063:  gpio-4),SGM2019-ADJ */
-	SOC_VIRTUAL_ID(SOC_AVDD28_RGB),		  /*slg51000:ldo-1 */
-	SOC_VIRTUAL_ID(SOC_DOVDD18_RGB),	  /*slg51000:ldo-4 */
-	SOC_VIRTUAL_ID(SOC_DVDD12_RGB),		  /*slg51000:ldo-5 */
-	SOC_VIRTUAL_ID(SOC_AVDD25_IR),		  /*slg51000:ldo-2 */
-	SOC_VIRTUAL_ID(SOC_DOVDD18_IR),		  /*slg51000:ldo-7 */
-	SOC_VIRTUAL_ID(SOC_DVDD12_IR),		  /*slg51000:ldo-6 */
-	SOC_VIRTUAL_ID(SOC_ADC_VREF),
-	SOC_VIRTUAL_ID(SOC_LCD0_EN),
-	SOC_VIRTUAL_ID(SOC_VEXT_1V8),
-};
-
-static int misc_regu_probe(struct udevice *dev)
-{
-	return 0;
-}
-
-static int misc_regu_remove(struct udevice *dev)
-{
-	return 0;
-}
-
-static soc_virtual_id_t *found_base_virtual_id(char *name)
-{
-	for (int i = 0; i < ARRAY_SIZE(soc_base_virtual_id_list); i++)
-	{
-		if (!strcasecmp(soc_base_virtual_id_list[i].virtual_id_name, name))
-		{
-			return &soc_base_virtual_id_list[i];
-		}
-	}
-	return NULL;
-}
-
-static inline char toupper(char str1)
-{
-	if (str1 >= 'a' && str1 <= 'z')
-	{
-		return str1 - 'a' + 'A';
-	}
-	return str1;
-}
-
-void string_to_upper(char *str)
-{
-	if (str == NULL)
-		return;
-
-	while (*str)
-	{
-		*str = toupper((unsigned char)*str);
-		str++;
-	}
-}
-
-static int misc_regu_get_virtual_regu_config(struct udevice *dev, ofnode parent_node, virtual_regu_list_t *regu_list)
-{
-	int regu_num = 0;
-	int ret;
-	ofnode child_node;
-	soc_virtual_id_t *id_list;
-	soc_virtual_id_t *soc_base_id;
-	ofnode_for_each_subnode(child_node, parent_node)
-	{
-		//printf("sub node name: %s\n", ofnode_get_name(child_node));
-		regu_num++;
-	}
-
-	if (!regu_num)
-	{
-		printf("regu list not found in dts\n");
-		return -1;
-	}
-
-	id_list = devm_kcalloc(dev, 1, regu_num * sizeof(soc_virtual_id_t), GFP_KERNEL);
-	if (!id_list)
-	{
-		printf("regu id malloc faild\n");
-		return -ENOMEM;
-	}
-
-	int index = 0;
-	int new_regu_index = ARRAY_SIZE(soc_base_virtual_id_list);
-
-	ofnode_for_each_subnode(child_node, parent_node)
-	{
-		const char *virtual_id_name = ofnode_get_name(child_node);
-		int min_uv;
-		int max_uv;
-		soc_base_id = found_base_virtual_id(virtual_id_name);
-		if (soc_base_id)
-		{
-			id_list[index].id = soc_base_id->id;
-		}
-		else
-		{
-			id_list[index].id = new_regu_index++;
-		}
-
-		int copy_size = MIN(sizeof(id_list[index].virtual_id_name) - 1, strlen(virtual_id_name));
-		memcpy(id_list[index].virtual_id_name, virtual_id_name, copy_size);
-		id_list[index].virtual_id_name[copy_size] = '\0';
-
-		string_to_upper(id_list[index].virtual_id_name);
-
-		ret = ofnode_read_u32(child_node, "regulator-min-microvolt", &min_uv);
-		if (ret)
-		{
-			// printf("%s :regulator-min-microvolt not set, min_uv set to -1", virtual_id_name);
-			id_list[index].min_uv = -1;
-		}
-		else
-		{
-			id_list[index].min_uv = min_uv;
-		}
-
-		ret = ofnode_read_u32(child_node, "regulator-max-microvolt", &max_uv);
-		if (ret)
-		{
-			// printf("%s :regulator-max-microvolt not set, max_uv set to -1", virtual_id_name);
-			id_list[index].max_uv = -1;
-		}
-		else
-		{
-			id_list[index].max_uv = max_uv;
-		}
-#warning "check double"
-		// printf("Get virtual regu_id:[%d]:%s min_uv:%dmv max_uv:%dmv\n", id_list[index].id, id_list[index].virtual_id_name,
-		// 	   id_list[index].min_uv, id_list[index].max_uv);
-		index++;
-	}
-
-	(*regu_list).regu_num = regu_num;
-	(*regu_list).regu_list = id_list;
-
-	return 0;
-}
-
-static int misc_grep_pmic_dev_name_info(char *dev_name, pmic_dev_info_t *dev)
-{
-	int flag_num = 0;
-	int version_flag = 0;
-	int index = 0;
-	char *dev_name_orig = dev_name;
-	while (*dev_name)
-	{
-		if (*dev_name == ',')
-		{
-			flag_num++;
-			if (flag_num == 2)
-			{
-				version_flag = index;
-			}
-		}
-		index++;
-		dev_name++;
-	}
-
-	if (flag_num != 2 || *(dev_name - 1) == ',')
-	{
-		printf("pmic-name should set as pmic-name = \"vendor,type,version");
-		return -1;
-	}
-
-	int len = MIN((version_flag), sizeof(dev->device_name) - 1);
-	memcpy(dev->device_name, dev_name_orig, len);
-	dev->device_name[len] = '\0';
-	len = MIN((index - version_flag - 1), sizeof(dev->device_name) - 1);
-	memcpy(dev->version_name, dev_name_orig + version_flag + 1, len);
-	dev->version_name[len] = '\0';
-	return 0;
-}
-
-static int get_node_index(const char *name)
-{
-	while (*name && *name != '@')
-	{
-		name++;
-	}
-
-	if (strlen(name) == 0)
-	{
-		return -1;
-	}
-	name++;
-	return strtoul(name, NULL, 10);
-}
-
-static int misc_regu_get_pmic_dev_config(ofnode parent_node, pmic_dev_info_t *pmic_dev_info_list)
-{
-	int ret = 0;
-	ofnode child_node, errio_node;
-	fdt_addr_t index;
-	char *pmic_name;
-	int pmic_wdt_flag = 0;
-	int pmic_index = 0;
-	int pmic_addr_len = 0, pmic_addr_size;
-	int gpio_addr_len = 0, gpio_addr_size;
-	char err_io_str[40] = "NOT_SUPPORT";
-	char lpm_io_str[40] = "NOT_SUPPORT";
-	uint32_t port, pin, trigger_mode;
-	uint32_t phandle;
-	const uint32_t *prop_val;
-
-	ofnode_for_each_subnode(child_node, parent_node)
-	{
-		pmic_dev_info_t *dev = &(pmic_dev_info_list[pmic_index]);
-		const char *node_name = ofnode_get_name(child_node);
-		if (!strncmp(node_name, PMIC_DEV_DTS_NAME, strlen(PMIC_DEV_DTS_NAME)))
-		{
-			index = get_node_index(node_name);
-			if (index < 0)
-			{
-				printf("get pmic_dev id faild");
-				return -1;
-			}
-			pmic_name = ofnode_read_string(child_node, "pmic-name");
-			if (!pmic_name)
-			{
-				printf("pmic_name property not set for %s%d", PMIC_DEV_DTS_NAME, index);
-				return -1;
-			}
-
-			if (ofnode_read_bool(child_node, "pmic_wdt_on"))
-			{
-				if (pmic_wdt_flag)
-				{
-					printf("only one pmic dev support wdt\n");
-					return -1;
-				}
-				dev->flag |= PMIC_DEV_ENABLE_WDT;
-				pmic_wdt_flag = 1;
-			}
-
-			prop_val = ofnode_get_property(child_node, "pmic-addr", &pmic_addr_len);
-			if (!prop_val)
-			{
-				printf("pmic-addr property not found\n");
-				return -1;
-			}
-			pmic_addr_size = pmic_addr_len / sizeof(uint32_t);
-
-			if (pmic_addr_size != 2 &&  pmic_addr_size!= 1)
-			{
-				printf("invalid pmic-addr cell size %d\n", pmic_addr_size);
-				return -1;
-			}
-
-			dev->addr1 = FDT32_TO_CPU(prop_val[0]);
-			dev->addr2 = pmic_addr_size == 2 ? FDT32_TO_CPU(prop_val[1]) : dev->addr1;
-
-			prop_val = ofnode_get_property(child_node, "errio_gpio", &gpio_addr_len);
-			if (prop_val)
-			{
-				gpio_addr_size = gpio_addr_len / sizeof(uint32_t);
-				if (gpio_addr_size != 3)
-				{
-					printf("invalid errio_gpio cell size %d\n", gpio_addr_size);
-					return -1;
-				}
-				else
-				{
-					port = FDT32_TO_CPU(prop_val[0]);
-					pin = 1 << FDT32_TO_CPU(prop_val[1]);
-					trigger_mode = FDT32_TO_CPU(prop_val[2]);
-					dev->flag |= PMIC_DEV_ENABLE_ERR_IO;
-					dev->err_io_info.gpio_port = port;
-					dev->err_io_info.pin = pin;
-					dev->err_io_info.trigger_mode = trigger_mode;
-					sprintf(err_io_str, "port:%d pin:%d trigger:%d", port, pin, trigger_mode);
-				}
-			} else {
-                    sprintf(err_io_str, "NOT_SUPPORT");
-			}
-
-			prop_val = ofnode_get_property(child_node, "lpm_gpio", &gpio_addr_len);
-			if (prop_val)
-			{
-				gpio_addr_size = gpio_addr_len / sizeof(uint32_t);
-				if (gpio_addr_size != 3)
-				{
-					printf("invalid lpm_gpio cell size %d\n", gpio_addr_size);
-					return -1;
-				}
-				else
-				{
-					port = FDT32_TO_CPU(prop_val[0]);
-					pin = 1 << FDT32_TO_CPU(prop_val[1]);
-					trigger_mode = FDT32_TO_CPU(prop_val[2]);
-					dev->flag |= PMIC_DEV_ENABLE_LPM_IO;
-					dev->lpm_io_info.gpio_port = port;
-					dev->lpm_io_info.pin = pin;
-					dev->lpm_io_info.trigger_mode = trigger_mode;
-					sprintf(lpm_io_str, "port:%d pin:%d trigger:%d", port, pin, trigger_mode);
-				}
-			} else {
-				sprintf(lpm_io_str,"NOT_SUPPORT");
-			}
-
-			dev->pmic_id = index;
-			ret = misc_grep_pmic_dev_name_info(pmic_name, dev);
-			pmic_index++;
-			AON_CONF_D("Get pmic dev:[%d]:%s|%s addr1:0x%02x addr2:0x%02x wdt:{%s} errio:{%s} lpm_io:{%s}\n", index, dev->device_name, dev->version_name, dev->addr1, dev->addr2, (dev->flag & PMIC_DEV_ENABLE_WDT ? "SUPPORT" : "NOT_SUPPORT"), err_io_str, lpm_io_str);
-		}
-	}
-	return 0;
-}
-
-static int misc_regu_get_pmic_dev_by_name(const char *name, int pmic_dev_num, pmic_dev_info_t *pmic_dev_info_list)
-{
-	int pmic_id = get_node_index(name);
-	if (pmic_id < 0)
-	{
-		return -1;
-	}
-
-	int pmic_index = 0;
-	for (; pmic_index < pmic_dev_num; pmic_index++)
-	{
-		if (pmic_dev_info_list[pmic_index].pmic_id == pmic_id)
-		{
-			break;
-		}
-	}
-
-	if (pmic_index == pmic_dev_num)
-	{
-		printf("%s not found in pmic list\n", name);
-		return -1;
-	}
-
-	return pmic_index;
-}
-
-static int misc_regu_get_each_regu_hw_id_config(ofnode regu_id_node, int pmic_dev_num, pmic_dev_info_t *pmic_dev_info_list, soc_virtual_id_t *virtual_id_info, pmic_hw_info_t *id)
-{
-	uint32_t phandle;
-	ofnode pmic_node, pmic_parent_node;
-
-	char *pmic_name;
-
-	int prop_len, prop_size;
-	int on_order, on_delay_ms;
-	int off_order, off_delay_ms;
-	int pmic_index, parent_pmic_index;
-	const uint32_t *prop_val;
-
-	/*get pmic_dev = <&pmic_dev_0 DA9063_ID_BCORE1>*/
-	prop_val = ofnode_get_property(regu_id_node, "pmic_dev", &prop_len);
-	if (!prop_val)
-	{
-		printf("pmic-addr property not found\n");
-		return -1;
-	}
-
-	prop_size = prop_len / sizeof(uint32_t);
-	if (prop_size != 2)
-	{
-		printf("pmic_dev property should set in format as  pmic_dev = <&pmic_dev_num HW_ID>;\n");
-		return -1;
-	}
-
-	pmic_node = ofnode_get_by_phandle(FDT32_TO_CPU(prop_val[0]));
-	if (!ofnode_valid(pmic_node))
-	{
-		printf("pmic node not found\n");
-		return -1;
-	}
-
-	pmic_index = misc_regu_get_pmic_dev_by_name(ofnode_get_name(pmic_node), pmic_dev_num, pmic_dev_info_list);
-	if (pmic_index < 0)
-	{
-		return -1;
-	}
-
-	(*id).pmic_id = pmic_dev_info_list[pmic_index].pmic_id;
-	(*id).hw_id = FDT32_TO_CPU(prop_val[1]);
-
-	/*get auto_on_info = <0 1 800000>*/
-	prop_val = ofnode_get_property(regu_id_node, "auto_on_info", &prop_len);
-	if (!prop_val)
-	{
-		(*id).soft_power_ctrl_info.on_info.on_order = HW_ID_NO_SOFT_AUTO_ON;
-	}
-	else
-	{
-		prop_size = prop_len / sizeof(uint32_t);
-		if (prop_size != 3 && prop_size != 2)
-		{
-			printf("auto_on_info property should set in format as auto_on_info = <on_order on_delay_ms [on_uv_mv]>\n");
-			return -1;
-		}
-		if (virtual_id_info->min_uv != -1 && FDT32_TO_CPU(prop_val[2]) < virtual_id_info->min_uv)
-		{
-			printf("virtual regu %s voltage shoud larger than %dmv, it is %dmv\n", virtual_id_info->virtual_id_name, virtual_id_info->min_uv, FDT32_TO_CPU(prop_val[2]));
-			return -1;
-		}
-		if (virtual_id_info->max_uv != -1 && FDT32_TO_CPU(prop_val[2]) > virtual_id_info->max_uv)
-		{
-			printf("virtual regu %s voltage shoud less than %dmv, it is %dmv\n", virtual_id_info->virtual_id_name, virtual_id_info->max_uv, FDT32_TO_CPU(prop_val[2]));
-			return -1;
-		}
-		(*id).soft_power_ctrl_info.on_info.on_order = FDT32_TO_CPU(prop_val[0]);
-		(*id).soft_power_ctrl_info.on_info.on_delay_ms = FDT32_TO_CPU(prop_val[1]);
-		if(prop_size == 3) {
-            (*id).soft_power_ctrl_info.on_info.init_target_uv = FDT32_TO_CPU(prop_val[2]);
-		} else {
-			(*id).soft_power_ctrl_info.on_info.init_target_uv = 0;
-		}
-		
-	}
-
-	/*get auto_off_info = <1 1>*/
-	prop_val = ofnode_get_property(regu_id_node, "auto_off_info", &prop_len);
-	if (!prop_val)
-	{
-		(*id).soft_power_ctrl_info.off_info.off_order = HW_ID_NO_SOFT_AUTO_OFF;
-	}
-	else
-	{
-		prop_size = prop_len / sizeof(uint32_t);
-		if (prop_size != 2)
-		{
-			printf("auto_off_info property should set in format as auto_off_info = <off_order off_delay_ms>\n");
-			return -1;
-		}
-		(*id).soft_power_ctrl_info.off_info.off_order = FDT32_TO_CPU(prop_val[0]);
-		(*id).soft_power_ctrl_info.off_info.off_delay_ms = FDT32_TO_CPU(prop_val[1]);
-	}
-
-	/*get parent_pmic_dev = <&pmic_dev_0 2 1>*/
-	prop_val = ofnode_get_property(regu_id_node, "parent_pmic_dev", &prop_len);
-	if (!prop_val)
-	{
-		(*id).parent_hw_info.pmic_id = PMIC_ID_INVALID;
-	}
-	else
-	{
-		prop_size = prop_len / sizeof(uint32_t);
-		if (prop_size != 3)
-		{
-			printf("parent_pmic_dev property should set in format as  parent_pmic_dev = <&pmic_dev_num IO_ID ACTIVATE_STATUS>;\n");
-			return -1;
-		}
-
-		pmic_parent_node = ofnode_get_by_phandle(FDT32_TO_CPU(prop_val[0]));
-		if (!ofnode_valid(pmic_parent_node))
-		{
-			printf("pmic_parent node not found\n");
-			return -1;
-		}
-
-		pmic_index = misc_regu_get_pmic_dev_by_name(ofnode_get_name(pmic_parent_node), pmic_dev_num, pmic_dev_info_list);
-		if (pmic_index < 0)
-		{
-			return -1;
-		}
-
-		(*id).parent_hw_info.pmic_id = pmic_dev_info_list[pmic_index].pmic_id;
-		(*id).parent_hw_info.io_hw_id = FDT32_TO_CPU(prop_val[1]);
-#warning "check status"
-		(*id).parent_hw_info.activate_status = FDT32_TO_CPU(prop_val[2]);
-	}
-
-	return 0;
-}
-
-static int misc_regu_get_each_regu_config(ofnode regu_config_node, int pmic_dev_num, pmic_dev_info_t *pmic_dev_info_list, soc_virtual_id_t *regu_info, csi_regu_id_t *pmic_regu_id_info)
-{
-	int ret = 0;
-	ofnode hw_id_node;
-	ofnode coupling_node;
-	uint32_t phandle = 0;
-	int index = 0;
-	char *regu_id_name;
-	const uint32_t *prop_val;
-	int prop_len = 0;
-	int prop_size = 0;
-    int coupling_num = 0;
-	uint16_t hw_id_used_flag = 0x0;
-
-	ofnode_for_each_subnode(hw_id_node, regu_config_node)
-	{
-		const char *node_name = ofnode_get_name(hw_id_node);
-		if (!strncmp(node_name, REGU_ID_NAME, strlen(REGU_ID_NAME)))
-		{
-			index = get_node_index(node_name);
-			if (index < 0)
-			{
-				printf("get hw_id faild");
-				return -1;
-			}
-
-			if (index >= PMIC_MAX_HW_ID_NUM || index >= 8 * sizeof(uint16_t))
-			{
-				printf("regu_id index should less than %d\n", MIN(PMIC_MAX_HW_ID_NUM, 8 * sizeof(uint16_t)));
-				return -1;
-			}
-
-			if ((hw_id_used_flag >> index) & 0x01)
-			{
-				printf("%s@%d already exist\n", REGU_ID_NAME, index);
-				return -1;
-			}
-			else
-			{
-				hw_id_used_flag |= 0x01 << index;
-			}
-
-			ret = misc_regu_get_each_regu_hw_id_config(hw_id_node, pmic_dev_num, pmic_dev_info_list, regu_info, &pmic_regu_id_info->sub.id[index]);
-			if (ret)
-			{
-				printf("get hw_id@%d config faild %d\n", ret);
-				return -1;
-			}
-		}
-
-	}
-
-	for (int i = PMIC_MAX_HW_ID_NUM - 1; i >= 0; i--)
-	{
-		if ((hw_id_used_flag & (0x01 << i)) == 0x0)
-		{
-			(*pmic_regu_id_info).sub.id[i].pmic_id = PMIC_ID_INVALID;
-		}
-	}
-    
-	ofnode_for_each_subnode(coupling_node, regu_config_node)
-	{
-		const char *node_name = ofnode_get_name(coupling_node);
-
-		if (!strncmp(node_name, COUPLING_ID_INFO_NAME, strlen(COUPLING_ID_INFO_NAME)))
-		{
-		/*get info = <0 1 -5 30>;*/
-	     prop_val = ofnode_get_property(coupling_node, "info", &prop_len);
-	    if (!prop_val)
-	    {
-		   printf("no info property set for %s", node_name);
-		   return -1;
-	    } else
-	    {
-			prop_size = prop_len / sizeof(uint32_t);
-			if (prop_size != 4)
-			{
-				printf("coupling info property should set in format as info = <id0 id1 max_spread min_spread)>\n");
-				return -1;
-			}
-
-            int id0 = FDT32_TO_CPU(prop_val[0]);
-		    int id1 = FDT32_TO_CPU(prop_val[1]);
-			int8_t max_spread = FDT32_TO_CPU(prop_val[2]);
-			int8_t min_spread = FDT32_TO_CPU(prop_val[3]);
-
-			if(ofnode_read_bool(coupling_node, "negative-min")) {
-                 min_spread = -min_spread; 
-			}
-			if(ofnode_read_bool(coupling_node, "negative-max")) {
-                 max_spread = -max_spread; 
-			}
-			if(id0 == id1) {
-                printf("coupling info: id0 id1 should not be equal");
-				return -1;
-			}
-			if(min_spread > max_spread) {
-                printf("coupling info: min_spread:%d is higher than max_spread:%d", min_spread, max_spread);
-				return -1;
-			}
-			if(id0 >= PMIC_MAX_HW_ID_NUM || id1 >= PMIC_MAX_HW_ID_NUM) {
-                printf("coupling info: id0:%d id1:%d is higher than max_id:%d", id0, id1, PMIC_MAX_HW_ID_NUM -1);
-				return -1;
-			}
-
-			if((*pmic_regu_id_info).sub.id[id0].pmic_id == PMIC_ID_INVALID || (*pmic_regu_id_info).sub.id[id1].pmic_id == PMIC_ID_INVALID) {
-                printf("coupling info:id0:%d id1:%d is invalid", id0, id1);
-				return -1;
-			}
-			(*pmic_regu_id_info).sub.coupling_list[coupling_num].id0 = id0;
-			(*pmic_regu_id_info).sub.coupling_list[coupling_num].id1 = id1;
-			(*pmic_regu_id_info).sub.coupling_list[coupling_num].max_spread = max_spread;
-			(*pmic_regu_id_info).sub.coupling_list[coupling_num].min_spread = min_spread;
-			coupling_num++;
-			if(coupling_num > PMIC_MAX_COUPLING_NUM) {
-                printf("coupling info should no more than %d\n", coupling_num);
-				return -1;
-			}
-	   }
-		}
-
-	}
-
-	for(int i = PMIC_MAX_COUPLING_NUM - 1; i >= coupling_num; i--)
-	{
-       (*pmic_regu_id_info).sub.coupling_list[i].id0 =  REGU_SUB_ID_INVALID;
-	   (*pmic_regu_id_info).sub.coupling_list[i].id1 =  REGU_SUB_ID_INVALID;
-	}
-
-	return 0;
-}
-
-static int misc_regu_get_regu_config(ofnode parent_node, int pmic_dev_num, pmic_dev_info_t *pmic_dev_info_list, int virtual_id_num, soc_virtual_id_t *regu_list, csi_regu_id_t *pmic_regu_id_list)
-{
-	ofnode child_node;
-	int index = 0;
-	uint32_t phandle = 0;
-	int ret = 0;
-	ofnode regu_virtual_node;
-	char *regu_id_name;
-	int virtual_id_index = 0;
-	uint16_t virtual_id_config_flag = 0;
-	int regu_config_index = 0;
-
-	ofnode_for_each_subnode(child_node, parent_node)
-	{
-		virtual_id_index = 0;
-		char *node_name = ofnode_get_name(child_node);
-		if (!strncmp(node_name, REGU_ID_CONF_NAME, strlen(REGU_ID_CONF_NAME)))
-		{
-
-			if (ofnode_read_u32(child_node, "reg_info", &phandle))
-			{
-				printf("reg_info property not found\n");
-				return -1;
-			}
-
-			regu_virtual_node = ofnode_get_by_phandle(phandle);
-			if (!ofnode_valid(regu_virtual_node))
-			{
-				printf("virtual_regu_node  not found\n");
-				return -1;
-			}
-
-			regu_id_name = ofnode_get_name(regu_virtual_node);
-
-			for (; virtual_id_index < virtual_id_num; virtual_id_index++)
-			{
-				if (!strcasecmp(regu_list[virtual_id_index].virtual_id_name, regu_id_name))
-				{
-					break;
-				}
-			}
-
-			if (virtual_id_index == virtual_id_num)
-			{
-				printf("virtual regu id %s not found\n", regu_id_name);
-				return -1;
-			}
-
-			int virtual_id = regu_list[virtual_id_index].id;
-
-			if ((virtual_id_config_flag >> virtual_id) & 0x01)
-			{
-				printf("%s config for %s already exist\n!", REGU_ID_CONF_NAME, regu_list[virtual_id_index].virtual_id_name);
-				return -1;
-			}
-			else
-			{
-				virtual_id_config_flag |= 0x01 << virtual_id;
-			}
-
-			csi_regu_id_t *regu_conf = &pmic_regu_id_list[regu_config_index];
-
-			regu_conf->regu_ext_id = virtual_id;
-			int copy_size = MIN(sizeof(regu_conf->regu_ext_id_name) - 1, strlen(regu_list[virtual_id_index].virtual_id_name));
-			memcpy(regu_conf->regu_ext_id_name, regu_list[virtual_id_index].virtual_id_name, copy_size);
-
-			ret = misc_regu_get_each_regu_config(child_node, pmic_dev_num, pmic_dev_info_list, &regu_list[virtual_id_index], regu_conf);
-			if (ret)
-			{
-				return -1;
-			}
-
-			AON_CONF_D("Get regu config, virtual_regu_id:[%d]:%s min_uv:%dmv max_uv:%dmv\n", virtual_id, regu_list[virtual_id_index].virtual_id_name, regu_list[virtual_id_index].min_uv,regu_list[virtual_id_index].max_uv);
-			for (int i = 0; i < ARRAY_SIZE(regu_conf->sub.id); i++)
-			{
-				pmic_hw_info_t *sub = &regu_conf->sub.id[i];
-				if (sub->pmic_id != PMIC_ID_INVALID)
-				{
-					char parent_info[50];
-					char auto_on_info[50];
-					char auto_off_info[50];
-
-					if (sub->parent_hw_info.pmic_id == PMIC_ID_INVALID)
-					{
-						sprintf(parent_info, "{NO_PARENT_PMIC}");
-					}
-					else
-					{
-						sprintf(parent_info, "{parent_pmic_dev:%d io_hw_id:%d activate_status:%d}", sub->parent_hw_info.pmic_id, sub->parent_hw_info.io_hw_id, sub->parent_hw_info.activate_status);
-					}
-
-					if (sub->soft_power_ctrl_info.on_info.on_order == HW_ID_NO_SOFT_AUTO_ON)
-					{
-						sprintf(auto_on_info, "{NOT_SUPPORT}");
-					}
-					else
-					{
-						sprintf(auto_on_info, "{on_order:%d on_delay:%d on_uv:%dmv}", sub->soft_power_ctrl_info.on_info.on_order, sub->soft_power_ctrl_info.on_info.on_delay_ms, sub->soft_power_ctrl_info.on_info.init_target_uv);
-					}
-					if (sub->soft_power_ctrl_info.off_info.off_order == HW_ID_NO_SOFT_AUTO_OFF)
-					{
-						sprintf(auto_off_info, "{NOT_SUPPORT}");
-					}
-					else
-					{
-						sprintf(auto_off_info, "{off_order:%d off_delay:%d}", sub->soft_power_ctrl_info.off_info.off_order, sub->soft_power_ctrl_info.off_info.off_delay_ms);
-					}
-
-					AON_CONF_D(">>>>>>%s@%d:{pmic_dev:%d hw_id:%d} parent_info:%s auto_on_info:%s auto_off_info:%s\n", REGU_ID_NAME, i, sub->pmic_id, sub->hw_id, parent_info, auto_on_info, auto_off_info);
-				}
-			}
-			int temp_flag = 0;
-			for(int i = 0; i < ARRAY_SIZE(regu_conf->sub.coupling_list); i++) {
-                coupling_desc_t* coupling_info = &regu_conf->sub.coupling_list[i];
-				if(coupling_info->id0 != REGU_SUB_ID_INVALID) {
-					if(!temp_flag) {
-                        AON_CONF_D(">>>>>>");
-						temp_flag = 1;
-					}
-                    AON_CONF_D("%s@%d:{id0:%d id1:%d max_spreed:%dmv min_spreed:%dmv}   ", COUPLING_ID_INFO_NAME, i,coupling_info->id0, coupling_info->id1, coupling_info->max_spread *10 , coupling_info->min_spread * 10);
-				}
-			}
-			if(temp_flag) {
-				AON_CONF_D("\n");
-			}
-			regu_config_index++;
-		}
-	}
-
-#warning "add no config check"
-	return 0;
-}
-
-static int misc_regu_get_aon_pmic_config(struct udevice *dev, ofnode parent_node, int virtual_id_num, soc_virtual_id_t *regu_list, pmic_dev_list_t *pmic_list, regu_id_list_t *regu_id_list)
-{
-	ofnode child_node;
-	int pmic_dev_num = 0;
-	int regu_id_conf_num = 0;
-	pmic_dev_info_t *pmic_dev_info_list;
-	csi_regu_id_t *pmic_regu_id_list;
-
-	const char *node_name;
-	int ret = 0;
-
-	ofnode_for_each_subnode(child_node, parent_node)
-	{
-		node_name = ofnode_get_name(child_node);
-		if (!strncmp(node_name, PMIC_DEV_DTS_NAME, strlen(PMIC_DEV_DTS_NAME)))
-		{
-			pmic_dev_num++;
-		}
-	}
-
-	if (!pmic_dev_num)
-	{
-		printf("No %s node in dts\n", PMIC_DEV_DTS_NAME);
-		return -1;
-	}
-
-	pmic_dev_info_list = devm_kcalloc(dev, 1, pmic_dev_num * sizeof(pmic_dev_info_t), GFP_KERNEL);
-	if (!pmic_dev_info_list)
-	{
-		printf("pmic dev list malloc faild\n");
-		return -ENOMEM;
-	}
-
-	ret = misc_regu_get_pmic_dev_config(parent_node, pmic_dev_info_list);
-	if (ret)
-	{
-		printf("pmic dev config get faild %d", ret);
-#warning "free"
-		return -1;
-	}
-
-	ofnode_for_each_subnode(child_node, parent_node)
-	{
-		node_name = ofnode_get_name(child_node);
-		if (!strncmp(node_name, REGU_ID_CONF_NAME, strlen(REGU_ID_CONF_NAME)))
-		{
-			regu_id_conf_num++;
-		}
-	}
-
-	if (!regu_id_conf_num)
-	{
-		printf("No %s node in dts\n", REGU_ID_CONF_NAME);
-		return -1;
-	}
-
-	pmic_regu_id_list = devm_kcalloc(dev, 1, regu_id_conf_num * sizeof(csi_regu_id_t), GFP_KERNEL);
-	if (!pmic_regu_id_list)
-	{
-		printf("pmic regu list malloc faild\n");
-		return -ENOMEM;
-	}
-
-	ret = misc_regu_get_regu_config(parent_node, pmic_dev_num, pmic_dev_info_list, virtual_id_num, regu_list, pmic_regu_id_list);
-	if (ret)
-	{
-		printf("get regu config faild %d\n", ret);
-#warning "free"
-		return -1;
-	}
-
-	(*pmic_list).pmic_num = pmic_dev_num;
-	(*pmic_list).pmic_list = pmic_dev_info_list;
-
-	(*regu_id_list).regu_id_num = regu_id_conf_num;
-	(*regu_id_list).regu_id_list = pmic_regu_id_list;
-
-	return 0;
-}
-
-static int misc_regu_bind(struct udevice *dev)
-{
-	struct mic_regu_platdata *plat = dev_get_platdata(dev);
-	ofnode parent_node = dev->node;
-
-	int ret;
-	ofnode child_node, node, regu_node, aon_conf_node;
-	const void *blob = gd->fdt_blob;
-	int subnode;
-	struct udevice *dev_1;
-
-	/* If this is a child device, there is nothing to do here */
-	if (plat)
-	{
-		return 0;
-	}
-
-	if (!ofnode_valid(parent_node))
-	{
-		printf("aon node not ok\n");
-		return -1;
-	}
-
-	int get_regu_dts_flag = 0;
-	int get_aon_conf_dst_flag = 0;
-
-	ofnode_for_each_subnode(child_node, parent_node)
-	{
-		/* Increment base_id for all subnodes, also the disabled ones */
-		//printf("sub node name: %s\n", ofnode_get_name(child_node));
-		if (!strncmp(ofnode_get_name(child_node), REGU_DTS_NAME, strlen(REGU_DTS_NAME)))
-		{
-			regu_node = child_node;
-			get_regu_dts_flag = 1;
-		}
-		if (!strncmp(ofnode_get_name(child_node), AON_CONF_NAME, strlen(AON_CONF_NAME)))
-		{
-			aon_conf_node = child_node;
-			get_aon_conf_dst_flag = 1;
-		}
-	}
-
-
-
-	if (!get_regu_dts_flag)
-	{
-		printf("No %s node in dts\n", REGU_DTS_NAME);
-		return -1;
-	}
-
-	if (!get_aon_conf_dst_flag)
-	{
-		printf("No %s node in dts\n", AON_CONF_NAME);
-		return -1;
-	}
-
-	plat = devm_kcalloc(dev, 1, sizeof(struct mic_regu_platdata), GFP_KERNEL);
-	if (!plat)
-	{
-		return -ENOMEM;
-	}
-
-	plat->wakeup_flag  = 0;
-
-	if (ofnode_read_bool(parent_node, "wakeup-by-gpio-on")) {
-		plat->wakeup_flag |= AON_WAKEUP_BY_GPIO;
-		printf("aon wakeup by gpio enabled\n");
-	}
-
-	if (ofnode_read_bool(parent_node, "wakeup-by-rtc-on")) {
-		plat->wakeup_flag |= AON_WAKEUP_BY_RTC;
-		printf("aon wakeup by rtc enabled\n");
-	}
-
-	ret = misc_regu_get_virtual_regu_config(dev, regu_node, &plat->regu_list);
-	if (ret)
-	{
-		printf("get virtual regu config failed %d\n", ret);
-		return -1;
-	}
-
-	ret = misc_regu_get_aon_pmic_config(dev, aon_conf_node, plat->regu_list.regu_num, plat->regu_list.regu_list, &plat->pmic_list, &plat->regu_id_list);
-	if (ret)
-	{
-		printf("get aon config failed %d\n", ret);
-		return -1;
-	}
-
-	plat->name = ofnode_get_name(parent_node);
-
-	ret = device_bind_ofnode(dev, dev->driver, plat->name, plat, parent_node, &dev_1);
-	if (ret)
-	{
-		printf("bind device faild %d", ret);
-		return ret;
-	}
-	/*fix me err usage*/
-	dev->platdata = plat;
-
-	return 0;
-}
-
-static const struct udevice_id misc_regu_ids[] = {
-	{.compatible = "thead,light-aon"},
-	{}};
-
-U_BOOT_DRIVER(light_regu) = {
-	.name = "light_regu,misc",
-	.id = UCLASS_MISC,
-	.of_match = misc_regu_ids,
-	.probe = misc_regu_probe,
-	.bind = misc_regu_bind,
-	.remove = misc_regu_remove,
-};

drivers/misc/light_regu.h

@@ -1,229 +0,0 @@
-#ifndef __LIGHT_REGU_H__
-#define __LIGHT_REGU_H__
-
-
-typedef enum
-{
-	SOC_DVDD18_AON,		  /*da9063:  ldo-3 */
-	SOC_AVDD33_USB3,	  /*da9063:  ldo-9 */
-	SOC_DVDD08_AON,		  /*da9063:  ldo-2 */
-	SOC_APCPU_DVDD_DVDDM, /*da9063:  vbcore1 & vbcore2*/
-	SOC_DVDD08_DDR,		  /*da9063:  buckperi */
-	SOC_VDD_DDR_1V8,	  /*da9063:  ldo-4  */
-	SOC_VDD_DDR_1V1,	  /*da9063:  buckmem & buckio  */
-	SOC_VDD_DDR_0V6,	  /*da9063:  buckpro */
-	SOC_DVDD18_AP,		  /*da9063:  ldo-11 */
-	SOC_DVDD08_AP,		  /*da9121:  da9121_ex */
-	SOC_AVDD08_MIPI_HDMI, /*da9063:  ldo-1  */
-	SOC_AVDD18_MIPI_HDMI, /*da9063:  ldo-5  */
-	SOC_DVDD33_EMMC,	  /*da9063:  ldo-10 */
-	SOC_DVDD18_EMMC,	  /*slg51000:ldo-3 */
-	SOC_DOVDD18_SCAN,	  /*da9063:  ldo-6 */
-	SOC_VEXT_2V8,		  /*da9063:  ldo-7 */
-	SOC_DVDD12_SCAN,	  /*da9063:  ldo-8 */
-	SOC_AVDD28_SCAN_EN,	  /*da9063:  gpio-4,SGM2019-ADJ */
-	SOC_AVDD28_RGB,		  /*slg51000:ldo-1 */
-	SOC_DOVDD18_RGB,	  /*slg51000:ldo-4 */
-	SOC_DVDD12_RGB,		  /*slg51000:ldo-5 */
-	SOC_AVDD25_IR,		  /*slg51000:ldo-2 */
-	SOC_DOVDD18_IR,		  /*slg51000:ldo-7 */
-	SOC_DVDD12_IR,		  /*slg51000:ldo-6 */
-	SOC_ADC_VREF,
-	SOC_LCD0_EN,
-	SOC_VEXT_1V8,
-
-	SOC_REGU_INVALID = 0xFF
-} soc_virtual_id_en;
-
-
-#define REGU_DTS_NAME "light-regu-reg"
-#define AON_CONF_NAME "aon_pmic_config"
-#define PMIC_DEV_DTS_NAME "pmic-dev"
-#define REGU_ID_CONF_NAME "regu_config"
-#define REGU_ID_NAME      "regu_id"
-#define COUPLING_ID_INFO_NAME  "coupling_info"
-
-
-
-#define PMIC_DEV_ENABLE_WDT                (1U << 0)
-#define PMIC_DEV_ENABLE_ERR_IO             (1U << 1)
-#define PMIC_DEV_ENABLE_LPM_IO             (1U << 2)
-
-#define HW_ID_NO_SOFT_AUTO_ON   (0xff)
-#define HW_ID_NO_SOFT_AUTO_OFF  (0xff)
-#define HW_ID_INVALID           (0xff)
-#define PMIC_ID_INVALID         (0xff)
-#define REGU_SUB_ID_INVALID     (0xff)
-
-#define REGU_EXT_ID_NAME_LEN 30
-#define PMIC_DEV_NAME_LEN 20
-#define PMIC_DEV_VERSION_LEN 20
-
-#define PMIC_MAX_HW_ID_NUM 3
-#define PMIC_MAX_COUPLING_NUM 3
-
-#define AON_WAKEUP_BY_GPIO (1 << 0)
-#define AON_WAKEUP_BY_RTC  (1 << 1)
-
-typedef enum {
-   HW_ID_ACTIVATE_HIGH  = 0U,
-   HW_ID_ACTIVATE_LOW =   1U,
-} hw_activate_status_en;
-
-typedef struct __packed {
-	uint8_t pmic_id;
-    uint8_t io_hw_id;
-    uint8_t activate_status;
-} pmic_parent_hw_io_ctrl_info_t;
-
-typedef struct __packed  {
-    uint8_t   on_order;
-	uint8_t   on_delay_ms;
-    uint32_t  init_target_uv;
-} regu_soft_power_ctrl_on_t;
-
-typedef struct __packed {
-    uint8_t off_order;
-	uint8_t off_delay_ms;
-} regu_soft_power_ctrl_off_t;
-
-typedef struct __packed {
-   regu_soft_power_ctrl_on_t  on_info;
-   regu_soft_power_ctrl_off_t off_info;
-} regu_soft_power_ctrl_t;
-
-
-typedef struct __packed {
-	uint8_t id0;
-	uint8_t id1;
-	int8_t max_spread; // mv/10
-	int8_t min_spread; // mv/10
-}coupling_desc_t;
-
-
-typedef struct __packed {
-   uint8_t pmic_id;
-   uint8_t hw_id;
-   uint8_t benable;
-   pmic_parent_hw_io_ctrl_info_t parent_hw_info;
-   regu_soft_power_ctrl_t soft_power_ctrl_info;
-} pmic_hw_info_t;
-
-
-typedef	struct __packed{
-	coupling_desc_t coupling_list[PMIC_MAX_COUPLING_NUM];
-	pmic_hw_info_t  id[PMIC_MAX_HW_ID_NUM];                             ///<  sub id1 for single-rail or first src of dual-rail
-}pmic_hw_id_t;
-
-typedef struct __packed {
-	uint8_t     regu_ext_id;                   ///< virtual global regulator id
-	char        regu_ext_id_name[REGU_EXT_ID_NAME_LEN];             ///< vitual regu-id name
-	pmic_hw_id_t sub;                           ///<  sub id set for dual-rail/single-rail regulator
-}csi_regu_id_t;
-
-typedef enum {
-   PMIC_CTRL_BY_AON_GPIO =  0U,
-   PMIC_CTRL_BY_PMIC_GPIO = 1U,
-   PMIC_CTRL_BY_NOTHINTG  = 0xFF,
-} pmic_ctrl_info_en;
-
-typedef struct __packed {
-    uint8_t port;
-	uint8_t pin;
-    uint8_t activate_status;
-} pmic_ctrl_by_aon_info_t;
-
-typedef struct __packed {
-	uint8_t pmic_id;
-    uint8_t io_hw_id;
-    uint8_t activate_status;
-} pmic_ctrl_by_pmic_info_t;
-
-typedef struct __packed {
-    uint8_t pmic_ctrl_type;
-	union {
-       pmic_ctrl_by_aon_info_t  aon_io_info;
-	   pmic_ctrl_by_pmic_info_t pmic_io_info;
-	};
-} pmic_parent_ctrl_info_t;
-
-typedef struct  __packed{
-	 uint16_t gpio_port;
-     uint16_t pin;
-	 uint8_t  trigger_mode;
-} pmic_interrupt_io_info_t;
-
-typedef struct __packed  {
-    char device_name[PMIC_DEV_NAME_LEN];
-    char version_name[PMIC_DEV_VERSION_LEN];
-    uint8_t pmic_id;
-    uint8_t addr1;
-    uint8_t addr2;
-	uint8_t flag;          /*support wdt|errio| lpm io*/
-	uint8_t slew_rate;
-	uint32_t    wdt_len;
-	pmic_interrupt_io_info_t err_io_info;
-	pmic_interrupt_io_info_t lpm_io_info;
-    pmic_parent_ctrl_info_t ctrl_info;
-} pmic_dev_info_t;
-
-typedef struct
-{
-	soc_virtual_id_en id;
-	char virtual_id_name[REGU_EXT_ID_NAME_LEN];
-	int min_uv;
-	int max_uv;
-} soc_virtual_id_t;
-
-typedef struct
-{
-	int regu_num;
-	soc_virtual_id_t *regu_list;
-} virtual_regu_list_t;
-
-typedef struct
-{
-	int pmic_num;
-	pmic_dev_info_t *pmic_list;
-} pmic_dev_list_t;
-
-typedef struct
-{
-	int regu_id_num;
-	csi_regu_id_t *regu_id_list;
-} regu_id_list_t;
-
-struct mic_regu_platdata
-{
-	const char *name;
-	uint32_t  wakeup_flag;
-	virtual_regu_list_t regu_list;
-	pmic_dev_list_t pmic_list;
-	regu_id_list_t regu_id_list;
-};
-
-
-#define   AON_CONFIG_MAGIC   "AON_CONFIG"
-#define   AON_CONFIG_VERSION "1.0.0"
-
-typedef  struct __packed{
-	uint8_t iic_id;
-    uint8_t pmic_dev_num;
-    uint8_t regu_num;
-	int pmic_dev_list_offset;
-	int regu_id_list_offset;
-}aon_pmic_config_t;
-
-typedef  struct  __packed{
-   const char  magic[11];
-   const char  version[11];
-   uint8_t   max_hw_id_num;
-   uint64_t  aon_config_partition_size;
-   uint32_t  wakeup_flag;
-   aon_pmic_config_t aon_pmic;
-} aon_config_t;
-
-
-
-
-#endif

drivers/misc/misc-uclass.c

@@ -13,6 +13,7 @@
  * general classes. A set of generic read, write and ioctl methods may
  * be used to access the device.
  */
+
 int misc_read(struct udevice *dev, int offset, void *buf, int size)
 {
 	const struct misc_ops *ops = device_get_ops(dev);

drivers/mmc/sdhci.c

@@ -38,7 +38,9 @@ static void sdhci_reset(struct sdhci_host *host, u8 mask)
 		timeout--;
 		udelay(1000);
 	}
-
+#ifdef CONFIG_TARGET_LIGHT_C910
+	mdelay(50);
+#endif
 }
 
 static void sdhci_cmd_done(struct sdhci_host *host, struct mmc_cmd *cmd)

drivers/video/Kconfig

@@ -351,16 +351,17 @@ config VIDEO_LCD_ILITEK_ILI9881C
 	Say Y here if you want to enable support for ILITEK ILI9881C
 	800x1280 DSI video mode panel.
 
-config VIDEO_LCD_JD9365DA
-	bool "JD9365DA DSI LCD panel support"
+config VIDEO_LCD_MINGJUN_070BI30IA2
+	bool "MingJun 070BI30IA2 DSI LCD panel support"
 	depends on DM_VIDEO
 	select VIDEO_MIPI_DSI
 	help
-	Say Y here if you want to enable support for JD9365DA
+	Say Y here if you want to enable support for Mingjun 070BI30IA2
 	800x1280 DSI video mode panel.
 
 config VIDEO_LCD_CUSTOM_LOGO
 	bool "LCD CUSTOM logo support"
+	default n
 	help
 	Say Y here if you want to enable support for custom logo.
 

drivers/video/Makefile

@@ -55,6 +55,7 @@ obj-$(CONFIG_VIDEO_LCD_HITACHI_TX18D42VM) += hitachi_tx18d42vm_lcd.o
 obj-$(CONFIG_VIDEO_LCD_ORISETECH_OTM8009A) += orisetech_otm8009a.o
 obj-$(CONFIG_VIDEO_LCD_RAYDIUM_RM68200) += raydium-rm68200.o
 obj-$(CONFIG_VIDEO_LCD_ILITEK_ILI9881C) += ilitek-ili9881c.o
+obj-$(CONFIG_VIDEO_LCD_MINGJUN_070BI30IA2) += mingjun-070bi30ia2.o
 obj-$(CONFIG_VIDEO_LCD_SSD2828) += ssd2828.o
 obj-$(CONFIG_VIDEO_MB862xx) += mb862xx.o videomodes.o
 obj-${CONFIG_VIDEO_MESON} += meson/
@@ -69,7 +70,6 @@ obj-$(CONFIG_VIDEO_SIMPLE) += simplefb.o
 obj-$(CONFIG_VIDEO_TEGRA20) += tegra.o
 obj-$(CONFIG_VIDEO_VCXK) += bus_vcxk.o
 obj-$(CONFIG_VIDEO_VESA) += vesa.o
-obj-$(CONFIG_VIDEO_LCD_JD9365DA) += jadard-jd9365da-h3.o
 
 obj-y += bridge/
 obj-y += sunxi/

drivers/video/ilitek-ili9881c.c

@@ -368,12 +368,12 @@ static int ili9881c_panel_prepare(struct udevice *panel)
 	ret = dm_gpio_set_value(&priv->reset, true);
 	if (ret)
 		return ret;
-	mdelay(1);
+	mdelay(500);
 
 	ret = dm_gpio_set_value(&priv->reset, false);
 	if (ret)
 		return ret;
-	mdelay(10);
+	mdelay(100);
 
 	return 0;
 }
@@ -464,6 +464,20 @@ static int ili9881c_panel_ofdata_to_platdata(struct udevice *dev)
 		dev_err(dev, "Warning: cannot get reset GPIO\n");
 		if (ret != -ENOENT)
 			return ret;
+	} else {
+		/* not a bug, but uboot's regulator is buggy,
+		I haven't more time to fix it, so put it here
+		*/
+		/* reset panel */
+		ret = dm_gpio_set_value(&priv->reset, false);
+		if (ret)
+			return ret;
+		mdelay(100);
+
+		ret = dm_gpio_set_value(&priv->reset, true);
+		if (ret)
+			return ret;
+		mdelay(100);
 	}
 
 	/* power gpios */

drivers/video/jadard-jd9365da-h3.c

@@ -1,238 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (c) 2019 Radxa Limited
- * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd.
- *
- * Author:
- * - Jagan Teki <jagan@amarulasolutions.com>
- * - Stephen Chen <stephen@radxa.com>
- */
-
-#include <common.h>
-#include <backlight.h>
-#include <dm.h>
-#include <mipi_dsi.h>
-#include <panel.h>
-#include <asm/gpio.h>
-
-struct jadard_panel_desc {
-	const struct display_timing *timing;
-	unsigned long mode_flags;
-	enum mipi_dsi_pixel_format format;
-	unsigned int lanes;
-};
-
-struct panel_info {
-	const struct jadard_panel_desc *desc;
-	struct gpio_desc	reset;
-	struct gpio_desc	hsvcc;
-	struct gpio_desc	vspn3v3;
-	bool   prepared;
-	bool   enabled;
-};
-
-static int jd9365_get_display_timing(struct udevice *dev,
-		struct display_timing *timings)
-{
-	struct mipi_dsi_panel_plat *plat = dev_get_platdata(dev);
-	struct mipi_dsi_device *device = plat->device;
-	struct panel_info *pinfo = dev_get_priv(dev);
-
-	memcpy(timings, pinfo->desc->timing, sizeof(*timings));
-
-	device->lanes	   = pinfo->desc->lanes;
-	device->format	   = pinfo->desc->format;
-	device->mode_flags = pinfo->desc->mode_flags;
-
-	return 0;
-}
-
-static int jadard_prepare(struct udevice *panel)
-{
-	struct panel_info *pinfo = dev_get_priv(panel);
-	int ret;
-
-	if (pinfo->prepared)
-		return 0;
-	dm_gpio_set_value(&pinfo->reset, false);
-
-	/* Power the panel */
-	ret = dm_gpio_set_value(&pinfo->hsvcc, true);
-	if (ret) {
-		return ret;
-	}
-
-	mdelay(1);
-	ret = dm_gpio_set_value(&pinfo->vspn3v3, true);
-	if (ret) {
-		return ret;
-	}
-	mdelay(1);
-
-	dm_gpio_set_value(&pinfo->reset, true);
-	mdelay(10);
-
-	pinfo->prepared = true;
-
-	return 0;
-}
-
-static int jadard_enable(struct udevice *panel)
-{
-	struct mipi_dsi_panel_plat *plat = dev_get_platdata(panel);
-	struct mipi_dsi_device *dsi = plat->device;
-	struct panel_info *pinfo = dev_get_priv(panel);
-	u8 power_mode;
-	int ret;
-
-	if (pinfo->enabled)
-		return 0;
-
-	dsi->mode_flags |= MIPI_DSI_MODE_LPM;
-
-	/* sanity test for connection */
-	ret = mipi_dsi_dcs_get_power_mode(dsi, &power_mode);
-	if (ret) {
-		dev_warn(dsi->dev, "%s: failed to get power mode: %d\n", __func__, ret);
-		return ret;
-	}
-
-	ret = mipi_dsi_dcs_set_tear_on(dsi, MIPI_DSI_DCS_TEAR_MODE_VBLANK);
-	if (ret)
-		return ret;
-
-	ret = mipi_dsi_dcs_exit_sleep_mode(dsi);
-	if (ret)
-	{
-		return ret;
-	}
-
-	mdelay(10);
-
-	ret = mipi_dsi_dcs_set_display_on(dsi);
-	if (ret){
-		return ret;
-	}
-
-	pinfo->enabled = true;
-
-	return 0;
-}
-
-static int jd9365_panel_enable(struct udevice *dev)
-{
-	struct mipi_dsi_panel_plat *plat   = dev_get_platdata(dev);
-	struct mipi_dsi_device     *device = plat->device;
-	int ret;
-
-	ret = mipi_dsi_attach(device);
-	if (ret < 0)
-		return ret;
-
-	ret = jadard_enable(dev);
-	if (ret)
-		return ret;
-
-	return 0;
-}
-
-static const struct display_timing txd_jd9365_timing = {
-	.pixelclock.typ		= 74250000,
-	.hactive.typ		= 800,
-	.hfront_porch.typ	= 60,
-	.hback_porch.typ	= 60,
-	.hsync_len.typ		= 40,
-	.vactive.typ		= 1280,
-	.vfront_porch.typ	= 16,
-	.vback_porch.typ	= 16,
-	.vsync_len.typ		= 8,
-	.flags			=  DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
-};
-
-static const struct jadard_panel_desc jd9365_panel_desc = {
-	.timing = &txd_jd9365_timing,
-	.mode_flags = MIPI_DSI_MODE_VIDEO |  MIPI_DSI_MODE_VIDEO_BURST,
-	.format = MIPI_DSI_FMT_RGB888,
-	.lanes = 4,
-};
-
-static int jd9365_panel_ofdata_to_platdata(struct udevice *dev)
-{
-	struct panel_info *pinfo = dev_get_priv(dev);
-	int ret;
-
-	ret = gpio_request_by_name(dev, "reset-gpio", 0,
-			&pinfo->reset, GPIOD_IS_OUT);
-	if (ret) {
-		dev_err(dev, "Warning: cannot get reset GPIO\n");
-		if (ret != -ENOENT)
-			return ret;
-	}
-
-	ret = gpio_request_by_name(dev, "hsvcc-gpio", 0,
-			&pinfo->hsvcc, GPIOD_IS_OUT);
-	if (ret) {
-		dev_err(dev, "Warning: cannot get hsvcc GPIO\n");
-		if (ret != -ENOENT)
-			return ret;
-	}
-
-	ret = gpio_request_by_name(dev, "vspn3v3-gpio", 0,
-			&pinfo->vspn3v3, GPIOD_IS_OUT);
-	if (ret) {
-		dev_err(dev, "Warning: cannot get vspn3v3 GPIO\n");
-		if (ret != -ENOENT)
-			return ret;
-	}
-
-	return 0;
-}
-
-static int jadard_dsi_probe(struct udevice *panel)
-{
-	int ret;
-	struct panel_info *pinfo = dev_get_priv(panel);
-
-	pinfo->desc = (const struct jadard_panel_desc*)dev_get_driver_data(panel);
-
-	ret = jadard_prepare(panel);
-	if (ret) {
-		dev_err(panel, "failed to prepare panel : %d\n", ret);
-		return ret;
-	}
-
-	return 0;
-}
-
-static int jadard_dsi_remove(struct udevice *panel)
-{
-	return 0;
-}
-
-static const struct panel_ops jd9365_panel_ops = {
-	.enable_backlight	= jd9365_panel_enable,
-	.get_display_timing	= jd9365_get_display_timing,
-};
-
-static const struct udevice_id panel_of_match[] = {
-	{
-		.compatible = "jadard,jd9365da-h3",
-		.data = (ulong)&jd9365_panel_desc,
-	},
-	{
-		/* sentinel */
-	}
-};
-
-U_BOOT_DRIVER(jadard_jd9365da) = {
-	.name 			  = "jadard_jd9365da",
-	.id			      = UCLASS_PANEL,
-	.of_match		  = panel_of_match,
-	.ops			  = &jd9365_panel_ops,
-	.ofdata_to_platdata	  = jd9365_panel_ofdata_to_platdata,
-	.probe			  = jadard_dsi_probe,
-	.remove			  = jadard_dsi_remove,
-	.platdata_auto_alloc_size = sizeof(struct mipi_dsi_panel_plat),
-	.priv_auto_alloc_size	  = sizeof(struct panel_info),
-};
-

drivers/video/mingjun-070bi30ia2.c

@@ -0,0 +1,490 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include <common.h>
+#include <backlight.h>
+#include <dm.h>
+#include <mipi_dsi.h>
+#include <panel.h>
+#include <asm/gpio.h>
+
+struct mingjun_panel_cmd {
+	char cmdlen;
+	char cmddata[0x40];
+};
+
+static const struct mingjun_panel_cmd mingjun_on_cmds[] = {
+	// { .cmdlen = 4,	.cmddata = {0xB9, 0xFF, 0x83, 0x94} },
+	// { .cmdlen = 11,	.cmddata = {0xB1, 0x48, 0x0A, 0x6A, 0x09, 0x33, 0x54,
+	// 			0x71, 0x71, 0x2E, 0x45} },
+	// { .cmdlen = 7,	.cmddata = {0xBA, 0x63, 0x03, 0x68, 0x6B, 0xB2, 0xC0} },
+	// { .cmdlen = 7,	.cmddata = {0xB2, 0x00, 0x80, 0x64, 0x0C, 0x06, 0x2F} },
+	// { .cmdlen = 22, .cmddata = {0xB4, 0x1C, 0x78, 0x1C, 0x78, 0x1C, 0x78, 0x01,
+	// 			0x0C, 0x86, 0x75, 0x00, 0x3F, 0x1C, 0x78, 0x1C,
+	// 			0x78, 0x1C, 0x78, 0x01, 0x0C, 0x86} },
+	// { .cmdlen = 34, .cmddata = {0xD3, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08,
+	// 			0x08, 0x32, 0x10, 0x05, 0x00, 0x05, 0x32, 0x13,
+	// 			0xC1, 0x00, 0x01, 0x32, 0x10, 0x08, 0x00, 0x00,
+	// 			0x37, 0x03, 0x07, 0x07, 0x37, 0x05, 0x05, 0x37,
+	// 			0x0C, 0x40} },
+	// { .cmdlen = 45, .cmddata = {0xD5, 0x18, 0x18, 0x18, 0x18, 0x22, 0x23, 0x20,
+	// 			0x21, 0x04, 0x05, 0x06, 0x07, 0x00, 0x01, 0x02,
+	// 			0x03, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
+	// 			0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
+	// 			0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
+	// 			0x18, 0x19, 0x19, 0x19, 0x19} },
+	// { .cmdlen = 45, .cmddata = {0xD6, 0x18, 0x18, 0x19, 0x19, 0x21, 0x20, 0x23,
+	// 			0x22, 0x03, 0x02, 0x01, 0x00, 0x07, 0x06, 0x05,
+	// 			0x04, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
+	// 			0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
+	// 			0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
+	// 			0x18, 0x19, 0x19, 0x18, 0x18} },
+	// { .cmdlen = 59, .cmddata = {0xE0, 0x07, 0x08, 0x09, 0x0D, 0x10, 0x14, 0x16,
+	// 			0x13, 0x24, 0x36, 0x48, 0x4A, 0x58, 0x6F, 0x76,
+	// 			0x80, 0x97, 0xA5, 0xA8, 0xB5, 0xC6, 0x62, 0x63,
+	// 			0x68, 0x6F, 0x72, 0x78, 0x7F, 0x7F, 0x00, 0x02,
+	// 			0x08, 0x0D, 0x0C, 0x0E, 0x0F, 0x10, 0x24, 0x36,
+	// 			0x48, 0x4A, 0x58, 0x6F, 0x78, 0x82, 0x99, 0xA4,
+	// 			0xA0, 0xB1, 0xC0, 0x5E, 0x5E, 0x64, 0x6B, 0x6C,
+	// 			0x73, 0x7F, 0x7F} },
+	// { .cmdlen = 2, .cmddata = {0xCC, 0x03} },
+	// { .cmdlen = 3, .cmddata = {0xC0, 0x1F, 0x73} },
+	// { .cmdlen = 3, .cmddata = {0xB6, 0x90, 0x90} },
+	// { .cmdlen = 2, .cmddata = {0xD4, 0x02} },
+	// { .cmdlen = 2, .cmddata = {0xBD, 0x01} },
+	// { .cmdlen = 2, .cmddata = {0xB1, 0x00} },
+	// { .cmdlen = 2, .cmddata = {0xBD, 0x00} },
+	// { .cmdlen = 8, .cmddn bata = {0xBF, 0x40, 0x81, 0x50, 0x00, 0x1A, 0xFC, 0x01} },
+
+	// { .cmdlen = 2, .cmddata = {0x36, 0x02} },
+{ .cmdlen =4, .cmddata = {0xFF,0x98,0x81,0x03} },
+{ .cmdlen = 2, .cmddata = {0x01,0x00} },
+{ .cmdlen = 2, .cmddata = {0x02,0x00} },
+{ .cmdlen = 2, .cmddata = {0x03,0x73} },
+{ .cmdlen = 2, .cmddata = {0x04,0x13} },
+{ .cmdlen = 2, .cmddata = {0x05,0x00} },
+{ .cmdlen = 2, .cmddata = {0x06,0x0A} },
+{ .cmdlen = 2, .cmddata = {0x07,0x05} },
+{ .cmdlen = 2, .cmddata = {0x11,0x00} },
+{ .cmdlen = 2, .cmddata = {0x09,0x28} },
+{ .cmdlen = 2, .cmddata = {0x0A,0x00} },
+{ .cmdlen = 2, .cmddata = {0x0B,0x00} },
+{ .cmdlen = 2, .cmddata = {0x0C,0x00} },
+{ .cmdlen = 2, .cmddata = {0x0D,0x28} },
+{ .cmdlen = 2, .cmddata = {0x0E,0x00} },
+{ .cmdlen = 2, .cmddata = {0x0F,0x28} },
+{ .cmdlen = 2, .cmddata = {0x10,0x28} },
+{ .cmdlen = 2, .cmddata = {0x11,0x00} },
+{ .cmdlen = 2, .cmddata = {0x12,0x00} },
+{ .cmdlen = 2, .cmddata = {0x13,0x00} },
+{ .cmdlen = 2, .cmddata = {0x14,0x00} },
+{ .cmdlen = 2, .cmddata = {0x15,0x00} },
+{ .cmdlen = 2, .cmddata = {0x16,0x00} },
+{ .cmdlen = 2, .cmddata = {0x17,0x00} },
+{ .cmdlen = 2, .cmddata = {0x18,0x00} },
+{ .cmdlen = 2, .cmddata = {0x19,0x00} },
+{ .cmdlen = 2, .cmddata = {0x1A,0x00} },
+{ .cmdlen = 2, .cmddata = {0x1B,0x00} },
+{ .cmdlen = 2, .cmddata = {0x1C,0x00} },
+{ .cmdlen = 2, .cmddata = {0x1D,0x00} },
+{ .cmdlen = 2, .cmddata = {0x1E,0x40} },
+{ .cmdlen = 2, .cmddata = {0x1F,0x80} },
+{ .cmdlen = 2, .cmddata = {0x20,0x06} },
+{ .cmdlen = 2, .cmddata = {0x21,0x01} },
+{ .cmdlen = 2, .cmddata = {0x22,0x00} },
+{ .cmdlen = 2, .cmddata = {0x23,0x00} },
+{ .cmdlen = 2, .cmddata = {0x24,0x00} },
+{ .cmdlen = 2, .cmddata = {0x25,0x00} },
+{ .cmdlen = 2, .cmddata = {0x26,0x00} },
+{ .cmdlen = 2, .cmddata = {0x27,0x00} },
+{ .cmdlen = 2, .cmddata = {0x28,0x33} },
+{ .cmdlen = 2, .cmddata = {0x29,0x33} },
+{ .cmdlen = 2, .cmddata = {0x2A,0x00} },
+{ .cmdlen = 2, .cmddata = {0x2B,0x00} },
+{ .cmdlen = 2, .cmddata = {0x2C,0x04} },
+{ .cmdlen = 2, .cmddata = {0x2D,0x0C} },
+{ .cmdlen = 2, .cmddata = {0x2E,0x05} },
+{ .cmdlen = 2, .cmddata = {0x2F,0x05} },
+{ .cmdlen = 2, .cmddata = {0x30,0x00} },
+{ .cmdlen = 2, .cmddata = {0x31,0x00} },
+{ .cmdlen = 2, .cmddata = {0x32,0x31} },
+{ .cmdlen = 2, .cmddata = {0x33,0x00} },
+{ .cmdlen = 2, .cmddata = {0x34,0x00} },
+{ .cmdlen = 2, .cmddata = {0x35,0x0A} },
+{ .cmdlen = 2, .cmddata = {0x36,0x00} },
+{ .cmdlen = 2, .cmddata = {0x37,0x08} },
+{ .cmdlen = 2, .cmddata = {0x70,0x00} },
+{ .cmdlen = 2, .cmddata = {0x39,0x00} },
+{ .cmdlen = 2, .cmddata = {0x3A,0x00} },
+{ .cmdlen = 2, .cmddata = {0x3B,0x00} },
+{ .cmdlen = 2, .cmddata = {0x3C,0x00} },
+{ .cmdlen = 2, .cmddata = {0x3D,0x00} },
+{ .cmdlen = 2, .cmddata = {0x3E,0x00} },
+{ .cmdlen = 2, .cmddata = {0x3F,0x00} },
+{ .cmdlen = 2, .cmddata = {0x40,0x00} },
+{ .cmdlen = 2, .cmddata = {0x41,0x00} },
+{ .cmdlen = 2, .cmddata = {0x42,0x00} },
+{ .cmdlen = 2, .cmddata = {0x43,0x08} },
+{ .cmdlen = 2, .cmddata = {0x44,0x00} },
+{ .cmdlen = 2, .cmddata = {0xA0,0x02} },
+{ .cmdlen = 2, .cmddata = {0x51,0x23} },
+{ .cmdlen = 2, .cmddata = {0x52,0x44} },
+{ .cmdlen = 2, .cmddata = {0x53,0x67} },
+{ .cmdlen = 2, .cmddata = {0x54,0x89} },
+{ .cmdlen = 2, .cmddata = {0x55,0xAB} },
+{ .cmdlen = 2, .cmddata = {0x56,0x01} },
+{ .cmdlen = 2, .cmddata = {0x57,0x23} },
+{ .cmdlen = 2, .cmddata = {0x58,0x45} },
+{ .cmdlen = 2, .cmddata = {0x59,0x67} },
+{ .cmdlen = 2, .cmddata = {0x5A,0x89} },
+{ .cmdlen = 2, .cmddata = {0x5B,0xAB} },
+{ .cmdlen = 2, .cmddata = {0x5C,0xCD} },
+{ .cmdlen = 2, .cmddata = {0x5D,0xEF} },
+{ .cmdlen = 2, .cmddata = {0x5E,0x11} },
+{ .cmdlen = 2, .cmddata = {0x5F,0x02} },
+{ .cmdlen = 2, .cmddata = {0x60,0x08} },
+{ .cmdlen = 2, .cmddata = {0x61,0x0E} },
+{ .cmdlen = 2, .cmddata = {0x62,0x0F} },
+{ .cmdlen = 2, .cmddata = {0x63,0x0C} },
+{ .cmdlen = 2, .cmddata = {0x64,0x0D} },
+{ .cmdlen = 2, .cmddata = {0x65,0x17} },
+{ .cmdlen = 2, .cmddata = {0x66,0x01} },
+{ .cmdlen = 2, .cmddata = {0x67,0x01} },
+{ .cmdlen = 2, .cmddata = {0x68,0x02} },
+{ .cmdlen = 2, .cmddata = {0x69,0x02} },
+{ .cmdlen = 2, .cmddata = {0x6A,0x00} },
+{ .cmdlen = 2, .cmddata = {0x6B,0x00} },
+{ .cmdlen = 2, .cmddata = {0x6C,0x02} },
+{ .cmdlen = 2, .cmddata = {0x6D,0x02} },
+{ .cmdlen = 2, .cmddata = {0x6E,0x16} },
+{ .cmdlen = 2, .cmddata = {0x6F,0x16} },
+{ .cmdlen = 2, .cmddata = {0x70,0x06} },
+{ .cmdlen = 2, .cmddata = {0x71,0x06} },
+{ .cmdlen = 2, .cmddata = {0x72,0x07} },
+{ .cmdlen = 2, .cmddata = {0x73,0x07} },
+{ .cmdlen = 2, .cmddata = {0x74,0x02} },
+{ .cmdlen = 2, .cmddata = {0x75,0x02} },
+{ .cmdlen = 2, .cmddata = {0x76,0x08} },
+{ .cmdlen = 2, .cmddata = {0x77,0x0E} },
+{ .cmdlen = 2, .cmddata = {0x78,0x0F} },
+{ .cmdlen = 2, .cmddata = {0x79,0x0C} },
+{ .cmdlen = 2, .cmddata = {0x7A,0x0D} },
+{ .cmdlen = 2, .cmddata = {0x7B,0x17} },
+{ .cmdlen = 2, .cmddata = {0x7C,0x01} },
+{ .cmdlen = 2, .cmddata = {0x7D,0x01} },
+{ .cmdlen = 2, .cmddata = {0x7E,0x02} },
+{ .cmdlen = 2, .cmddata = {0x7F,0x02} },
+{ .cmdlen = 2, .cmddata = {0x80,0x00} },
+{ .cmdlen = 2, .cmddata = {0x81,0x00} },
+{ .cmdlen = 2, .cmddata = {0x82,0x02} },
+{ .cmdlen = 2, .cmddata = {0x83,0x02} },
+{ .cmdlen = 2, .cmddata = {0x84,0x16} },
+{ .cmdlen = 2, .cmddata = {0x85,0x16} },
+{ .cmdlen = 2, .cmddata = {0x86,0x06} },
+{ .cmdlen = 2, .cmddata = {0x87,0x06} },
+{ .cmdlen = 2, .cmddata = {0x88,0x07} },
+{ .cmdlen = 2, .cmddata = {0x89,0x07} },
+{ .cmdlen = 2, .cmddata = {0x8A,0x02} },
+{ .cmdlen = 4, .cmddata = {0xFF,0x98,0x81,0x04} },
+{ .cmdlen = 2, .cmddata = {0x6E,0x1A} },
+{ .cmdlen = 2, .cmddata = {0x6F,0x37} },
+{ .cmdlen = 2, .cmddata = {0x3A,0xA4} },
+{ .cmdlen = 2, .cmddata = {0x8D,0x1F} },
+{ .cmdlen = 2, .cmddata = {0x87,0xBA} },
+{ .cmdlen = 2, .cmddata = {0xB2,0xD1} },
+{ .cmdlen = 2, .cmddata = {0x88,0x0B} },
+{ .cmdlen = 2, .cmddata = {0x38,0x01} },
+{ .cmdlen = 2, .cmddata = {0x39,0x00} },
+{ .cmdlen = 2, .cmddata = {0xB5,0x02} },
+{ .cmdlen = 2, .cmddata = {0x31,0x25} },
+{ .cmdlen = 2, .cmddata = {0x3B,0x98} },
+{ .cmdlen = 4, .cmddata = {0xFF,0x98,0x81,0x01} },
+{ .cmdlen = 2, .cmddata = {0x22,0x0A} },
+{ .cmdlen = 2, .cmddata = {0x31,0x00} },
+{ .cmdlen = 2, .cmddata = {0xA6,0xA6} },
+{ .cmdlen = 2, .cmddata = {0x55,0x3D} },
+{ .cmdlen = 2, .cmddata = {0x50,0x9E} },
+{ .cmdlen = 2, .cmddata = {0x51,0x99} },
+{ .cmdlen = 2, .cmddata = {0x60,0x06} },
+{ .cmdlen = 2, .cmddata = {0x62,0x20} },
+{ .cmdlen = 2, .cmddata = {0xA0,0x00} },
+{ .cmdlen = 2, .cmddata = {0xA1,0x17} },
+{ .cmdlen = 2, .cmddata = {0xA2,0x26} },
+{ .cmdlen = 2, .cmddata = {0xA3,0x13} },
+{ .cmdlen = 2, .cmddata = {0xA4,0x16} },
+{ .cmdlen = 2, .cmddata = {0xA5,0x29} },
+{ .cmdlen = 2, .cmddata = {0xA6,0x1E} },
+{ .cmdlen = 2, .cmddata = {0xA7,0x1F} },
+{ .cmdlen = 2, .cmddata = {0xA8,0x8B} },
+{ .cmdlen = 2, .cmddata = {0xA9,0x1D} },
+{ .cmdlen = 2, .cmddata = {0xAA,0x2A} },
+{ .cmdlen = 2, .cmddata = {0xAB,0x7B} },
+{ .cmdlen = 2, .cmddata = {0xAC,0x1A} },
+{ .cmdlen = 2, .cmddata = {0xAD,0x19} },
+{ .cmdlen = 2, .cmddata = {0xAE,0x4E} },
+{ .cmdlen = 2, .cmddata = {0xAF,0x24} },
+{ .cmdlen = 2, .cmddata = {0xB0,0x29} },
+{ .cmdlen = 2, .cmddata = {0xB1,0x4F} },
+{ .cmdlen = 2, .cmddata = {0xB2,0x5C} },
+{ .cmdlen = 2, .cmddata = {0xB3,0x3E} },
+{ .cmdlen = 2, .cmddata = {0xC0,0x00} },
+{ .cmdlen = 2, .cmddata = {0xC1,0x17} },
+{ .cmdlen = 2, .cmddata = {0xC2,0x26} },
+{ .cmdlen = 2, .cmddata = {0xC3,0x13} },
+{ .cmdlen = 2, .cmddata = {0xC4,0x16} },
+{ .cmdlen = 2, .cmddata = {0xC5,0x29} },
+{ .cmdlen = 2, .cmddata = {0xC6,0x1E} },
+{ .cmdlen = 2, .cmddata = {0xC7,0x1F} },
+{ .cmdlen = 2, .cmddata = {0xC8,0x8B} },
+{ .cmdlen = 2, .cmddata = {0xC9,0x1D} },
+{ .cmdlen = 2, .cmddata = {0xCA,0x2A} },
+{ .cmdlen = 2, .cmddata = {0xCB,0x7B} },
+{ .cmdlen = 2, .cmddata = {0xCC,0x1A} },
+{ .cmdlen = 2, .cmddata = {0xCD,0x19} },
+{ .cmdlen = 2, .cmddata = {0xCE,0x4E} },
+{ .cmdlen = 2, .cmddata = {0xCF,0x24} },
+{ .cmdlen = 2, .cmddata = {0xD0,0x29} },
+{ .cmdlen = 2, .cmddata = {0xD1,0x4D} },
+{ .cmdlen = 2, .cmddata = {0xD2,0x5C} },
+{ .cmdlen = 2, .cmddata = {0xD3,0x3E} },
+{ .cmdlen = 4, .cmddata = {0xFF,0x98,0x81,0x00} },
+{ .cmdlen = 2, .cmddata = {0x11,0x00} },
+{ .cmdlen = 2, .cmddata = {0x29,0x00} },
+{ .cmdlen = 2, .cmddata = {0x35,0x00} },
+{ .cmdlen = 2, .cmddata = {0x00,0x00} },
+};
+
+
+struct mj070bi30ia2_desc {
+	const struct mingjun_panel_cmd *on_cmds;
+	unsigned int on_cmds_num;
+	const struct display_timing *timing;
+};
+
+struct mj070bi30ia2_panel_priv {
+	struct udevice *backlight;
+	struct gpio_desc reset;
+	const struct mj070bi30ia2_desc *desc;
+};
+
+static const struct display_timing mj070bi30ia2_timing = {
+	.pixelclock.typ		= 75750000,
+	.hactive.typ		= 800,
+	.hfront_porch.typ	= 48,
+	.hback_porch.typ	= 80,
+	.hsync_len.typ		= 32,
+	.vactive.typ		= 1280,
+	.vfront_porch.typ	= 3,
+	.vback_porch.typ	= 24,
+	.vsync_len.typ		= 10,
+	.flags			= DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
+};
+
+static int mingjun_send_mipi_cmds(struct udevice *panel,
+					struct mingjun_panel_cmd *cmds)
+{
+	struct mipi_dsi_panel_plat *plat = dev_get_platdata(panel);
+	struct mipi_dsi_device *dsi = plat->device;
+	struct mj070bi30ia2_panel_priv *priv = dev_get_priv(panel);
+	int ret;
+	int i;
+
+	for (i = 0; i < priv->desc->on_cmds_num; i++) {
+		ret = mipi_dsi_dcs_write_buffer(dsi,
+				&(cmds[i].cmddata[0]), cmds[i].cmdlen);
+		if (ret < 0)
+			return ret;
+	}
+	dev_info(dsi->dev, "%s: send initial instruction\n", __func__);
+
+	return 0;
+}
+
+static int mj070bi30ia2_panel_setup(struct udevice *panel)
+{
+	int ret;
+	u8 power_mode;
+	const struct mj070bi30ia2_instr *instr;
+	struct mj070bi30ia2_panel_priv *priv = dev_get_priv(panel);
+	struct mipi_dsi_panel_plat *plat = dev_get_platdata(panel);
+	struct mipi_dsi_device *dsi = plat->device;
+
+	dsi->mode_flags |= MIPI_DSI_MODE_LPM;
+
+	/* sanity test for connection */
+	ret = mipi_dsi_dcs_get_power_mode(dsi, &power_mode);
+	if (ret) {
+		dev_warn(dsi->dev, "%s: failed to get power mode: %d\n", __func__, ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+static int mj070bi30ia2_panel_prepare(struct udevice *panel)
+{
+	struct mj070bi30ia2_panel_priv *priv = dev_get_priv(panel);
+	int ret;
+
+	/* reset panel */
+	ret = dm_gpio_set_value(&priv->reset, true);
+	if (ret)
+		return ret;
+	mdelay(1);
+
+	ret = dm_gpio_set_value(&priv->reset, false);
+	if (ret)
+		return ret;
+	mdelay(10);
+
+	return 0;
+}
+
+static int mj070bi30ia2_panel_enable(struct udevice *panel)
+{
+	int ret;
+	struct mj070bi30ia2_panel_priv *priv = dev_get_priv(panel);
+	struct mipi_dsi_panel_plat *plat = dev_get_platdata(panel);
+	struct mipi_dsi_device *dsi = plat->device;
+
+	dsi->mode_flags |= MIPI_DSI_MODE_LPM;
+
+	ret = mingjun_send_mipi_cmds(panel, priv->desc->on_cmds);
+	if (ret < 0) {
+		dev_err(panel->dev, "failed to send DCS Init Code: %d\n", ret);
+		return ret;
+	}
+
+	ret = mipi_dsi_dcs_set_tear_on(dsi, MIPI_DSI_DCS_TEAR_MODE_VBLANK);
+	if (ret)
+		return ret;
+
+	ret = mipi_dsi_dcs_exit_sleep_mode(dsi);
+	if (ret)
+		return ret;
+
+	mdelay(10);
+
+	ret = mipi_dsi_dcs_set_display_on(dsi);
+	if (ret)
+		return ret;
+
+#if 0
+	ret = backlight_enable(priv->backlight);
+	if (ret)
+		return ret;
+#endif
+
+	return 0;
+}
+
+static int mj070bi30ia2_panel_enable_backlight(struct udevice *dev)
+{
+	int ret;
+	struct mipi_dsi_panel_plat *plat = dev_get_platdata(dev);
+	struct mipi_dsi_device *device = plat->device;
+
+	ret = mipi_dsi_attach(device);
+	if (ret < 0)
+		return ret;
+
+	ret = mj070bi30ia2_panel_setup(dev);
+	if (ret)
+		return ret;
+
+	ret = mj070bi30ia2_panel_enable(dev);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
+static int mj070bi30ia2_panel_get_display_timing(struct udevice *dev,
+					     struct display_timing *timings)
+{
+	struct mipi_dsi_panel_plat *plat = dev_get_platdata(dev);
+	struct mipi_dsi_device *device = plat->device;
+	struct mj070bi30ia2_panel_priv *priv = dev_get_priv(dev);
+
+	memcpy(timings, priv->desc->timing, sizeof(*timings));
+
+	device->lanes	= 4;
+	device->format	= MIPI_DSI_FMT_RGB888;
+	device->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST;
+
+	return 0;
+}
+
+static int mj070bi30ia2_panel_ofdata_to_platdata(struct udevice *dev)
+{
+	struct mj070bi30ia2_panel_priv *priv = dev_get_priv(dev);
+	int ret;
+
+	ret = gpio_request_by_name(dev, "reset-gpios", 0,
+			&priv->reset, GPIOD_IS_OUT);
+	if (ret) {
+		dev_err(dev, "Warning: cannot get reset GPIO\n");
+		return ret;
+	}
+
+	ret = uclass_get_device_by_phandle(UCLASS_PANEL_BACKLIGHT, dev,
+					   "backlight", &priv->backlight);
+	if (ret) {
+		dev_err(dev, "Cannot get backlight: ret=%d\n", ret);
+	}
+
+	/* TODO: get lanes, format and mode from dtb */
+
+	return 0;
+}
+
+static int mj070bi30ia2_panel_probe(struct udevice *panel)
+{
+	int ret;
+	struct mj070bi30ia2_panel_priv *priv = dev_get_priv(panel);
+
+	priv->desc = (const struct mj070bi30ia2_desc *)dev_get_driver_data(panel);
+
+	/* prepare_panel */
+	ret = mj070bi30ia2_panel_prepare(panel);
+	if (ret) {
+		dev_err(panel, "failed to prepare panel : %d\n", ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+static int mj070bi30ia2_panel_remove(struct udevice *panel)
+{
+	struct mj070bi30ia2_panel_priv *priv = dev_get_priv(panel);
+
+	return dm_gpio_set_value(&priv->reset, true);
+}
+
+static const struct mj070bi30ia2_desc mj070bi30ia2_desc = {
+	.on_cmds = mingjun_on_cmds,
+	.on_cmds_num = ARRAY_SIZE(mingjun_on_cmds),
+        .timing = &mj070bi30ia2_timing,
+};
+
+static const struct panel_ops mj070bi30ia2_panel_ops = {
+	.enable_backlight	= mj070bi30ia2_panel_enable_backlight,
+	.get_display_timing	= mj070bi30ia2_panel_get_display_timing,
+};
+
+static const struct udevice_id mj070bi30ia2_panel_ids[] = {
+	{ .compatible = "mingjun,mj070bi30ia2", .data = (ulong)&mj070bi30ia2_desc },
+	{ /* sentinel */ }
+};
+
+U_BOOT_DRIVER(mj070bi30ia2_panel) = {
+	.name 			  = "mj070bi30ia2_panel",
+	.id			  = UCLASS_PANEL,
+	.of_match		  = mj070bi30ia2_panel_ids,
+	.ops			  = &mj070bi30ia2_panel_ops,
+	.ofdata_to_platdata	  = mj070bi30ia2_panel_ofdata_to_platdata,
+	.probe			  = mj070bi30ia2_panel_probe,
+	.remove			  = mj070bi30ia2_panel_remove,
+	.platdata_auto_alloc_size = sizeof(struct mipi_dsi_panel_plat),
+	.priv_auto_alloc_size	  = sizeof(struct mj070bi30ia2_panel_priv),
+};

include/configs/light-c910.h

@@ -30,15 +30,10 @@
 #define CONFIG_SYS_BOOTM_LEN        SZ_64M
 #define CONFIG_SYS_CACHELINE_SIZE   64
 
-#define CONFIG_CMD_READ 1
-
 #define SRAM_BASE_ADDR	 0xffe0000000
 #define PLIC_BASE_ADDR   0xffd8000000
 #define PMP_BASE_ADDR    0xffdc020000
 
-#define MINIMAL_DDR_DENSITY_MB (1*1024)
-#define MAXIMAL_DDR_DENSITY_MB (16*1024)
-#define UNIT_MB (1024*1024)
 
 /* Network Configuration */
 #define CONFIG_DW_ALTDESCRIPTOR
@@ -132,542 +127,45 @@
 #define ENV_STR_SERIAL 		"serial#=\0"
 #define ENV_KERNEL_KDUMP	"kdump_buf=0M\0"
 #endif
-/*public bootargs in mostly boards, make env 'set_booargs' shorter and clean */
-#define ENV_PUBLIC_BOOTARGS "pub_bootargs=rootfstype=ext4 rdinit=/sbin/init rootwait rw earlycon clk_ignore_unused\0"
 
-/* Define board ID in ENV for firmware download protection */
-#if defined(CONFIG_LIGHT_ANDROID_BOOT_IMAGE_VAL_A) || \
-    defined(CONFIG_LIGHT_SEC_BOOT_WITH_VERIFY_VAL_A) || \
-    defined(CONFIG_TARGET_LIGHT_FM_C910_VAL_A)
-#define ENV_STR_BOARD "board#=LA\0"
-#elif defined(CONFIG_LIGHT_ANDROID_BOOT_IMAGE_VAL_B) || \
-      defined(CONFIG_LIGHT_SEC_BOOT_WITH_VERIFY_VAL_B) || \
-      defined(CONFIG_TARGET_LIGHT_FM_C910_VAL_B)
-#define ENV_STR_BOARD "board#=LB\0"
-#elif defined(CONFIG_LIGHT_ANDROID_BOOT_IMAGE_VAL_LPI4A) || \
-      defined(CONFIG_LIGHT_SEC_BOOT_WITH_VERIFY_LPI4A) || \
-      defined(CONFIG_TARGET_LIGHT_FM_C910_LPI4A)
+#define CONFIG_MISC_INIT_R
+
 #define ENV_STR_BOARD "board#=LP\0"
-#elif defined(CONFIG_LIGHT_ANDROID_BOOT_IMAGE_VAL_BEAGLE) || \
-      defined(CONFIG_TARGET_LIGHT_FM_C910_BEAGLE)
-#define ENV_STR_BOARD "board#=LG\0"
-#elif defined(CONFIG_LIGHT_ANDROID_BOOT_IMAGE_ANT_REF) || \
-      defined(CONFIG_LIGHT_SEC_BOOT_WITH_VERIFY_ANT_REF) || \
-      defined(CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_REF)
-#define ENV_STR_BOARD "board#=LD\0"
-#endif
 
-
-#if defined (CONFIG_LIGHT_SEC_BOOT_WITH_VERIFY_VAL_A)
 #define CONFIG_EXTRA_ENV_SETTINGS \
-	"splashimage=0x30000000\0" \
-	"splashpos=m,m\0" \
-	"fdt_high=0xffffffffffffffff\0" \
-    ENV_STR_BOARD \
-	"tf_addr=0x100000\0" \
+	"scriptaddr=0x00500000\0" \
+	"pxefile_addr_r=0x00600000\0" \
 	"dtb_addr=0x03800000\0" \
-	"kernel_addr=0x00200000\0" \
+	"fdt_addr_r=0x03800000\0" \
+	"kernel_addr_r=0x00200000\0" \
+	"ramdisk_addr_r=0x06000000\0" \
+	"boot_conf_addr_r=0xc0000000\0" \
 	"aon_ram_addr=0xffffef8000\0" \
 	"audio_ram_addr=0x32000000\0" \
 	"str_ram_addr=0xffe0000000\0" \
-	"fwaddr=0x10000000\0"\
-	"tee_addr=0x1c000000\0" \
-	"sec_upgrade_mode=0\0"\
-	"mmcdev=0\0" \
-	"mmcpart=8\0" \
-	"mmcbootpart=2\0" \
-	ENV_KERNEL_LOGLEVEL \
-	"kdump_buf=180M\0" \
-	ENV_STR_BOOT_DELAY \
-	"sbmeta_security_level=1\0" \
-	"uboot_version=0x0000000000000000\0"\
-	"tee_version=0x00000000\0"\
-	"tf_version=0x00000000\0"\
-	"sbmeta_version=0x00000000\0"\
-	"fdt_file=th1520-a-val-sec.dtb\0" \
-	"uuid_rootfs=80a5a8e9-c744-491a-93c1-4f4194fd690b\0" \
-	"partitions=name=table,size=2031KB;name=boot,size=200MiB,type=boot;name=tee,size=50MiB,type=boot;name=stash,size=50MiB,type=boot;name=sbmeta,size=8MiB,type=boot;name=swap,size=1536MiB,type=boot;name=fastresume,size=512MiB,type=boot;name=root,size=-,type=linux,uuid=${uuid_rootfs}\0" \
-	"finduuid=part uuid mmc ${mmcdev}:${mmcpart} uuid\0" \
-	"gpt_partition=gpt write mmc ${mmcdev} $partitions\0" \
-	ENV_PUBLIC_BOOTARGS \
-	"set_bootargs=setenv bootargs console=ttyS0,115200 root=PARTUUID=${uuid} ${pub_bootargs} loglevel=${kernel_loglevel} eth=$ethaddr crashkernel=${kdump_buf} ${resume_bootargs}\0" \
-	"load_aon=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_aon_fpga.bin;cp.b $fwaddr $aon_ram_addr $filesize;bootaon\0"\
-	"load_c906_audio=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_c906_audio.bin;cp.b $fwaddr $audio_ram_addr $filesize\0"\
-	"load_str=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr str.bin;cp.b $fwaddr $str_ram_addr $filesize\0"\
-	"bootcmd_load=run load_aon;run load_c906_audio;ext4load mmc 0:3 $tf_addr trust_firmware.bin; ext4load mmc 0:3 $tee_addr tee.bin;ext4load mmc ${mmcdev}:${mmcbootpart} $dtb_addr ${fdt_file}; ext4load mmc ${mmcdev}:${mmcbootpart} $kernel_addr Image\0" \
-	"bootcmd=run bootcmd_load; chk_hibernate; fixup_memory_region; bootslave; run finduuid; run set_bootargs; sbmetaboot;run load_str;booti $kernel_addr - $dtb_addr;\0" \
-        "\0"
-
-#elif defined (CONFIG_LIGHT_SEC_BOOT_WITH_VERIFY_VAL_B)
-#define CONFIG_EXTRA_ENV_SETTINGS \
+	"opensbi_addr=0x0\0" \
+	"fwaddr=0x10000000\0" \
 	"splashimage=0x30000000\0" \
 	"splashpos=m,m\0" \
 	"fdt_high=0xffffffffffffffff\0" \
-    ENV_STR_BOARD \
-	"tf_addr=0x100000\0" \
-	"dtb_addr=0x03800000\0" \
-	"kernel_addr=0x00200000\0" \
-	"aon_ram_addr=0xffffef8000\0" \
-	"audio_ram_addr=0x32000000\0" \
-	"str_ram_addr=0xffe0000000\0" \
-	"fwaddr=0x10000000\0"\
-	"tee_addr=0x1c000000\0" \
-	"sec_upgrade_mode=0\0"\
-	"mmcdev=0\0" \
-	"mmcpart=6\0" \
-	"mmcbootpart=2\0" \
-	ENV_KERNEL_LOGLEVEL \
-	"kdump_buf=180M\0" \
-	ENV_STR_BOOT_DELAY \
-	"sbmeta_security_level=1\0" \
-	"uboot_version=0x0000000000000000\0"\
-	"tee_version=0x00000000\0"\
-	"tf_version=0x00000000\0"\
-	"sbmeta_version=0x00000000\0"\
-	"fdt_file=th1520-b-product-sec.dtb\0" \
-	"uuid_rootfs=80a5a8e9-c744-491a-93c1-4f4194fd690b\0" \
-	"partitions=name=table,size=2031KB;name=boot,size=200MiB,type=boot;name=tee,size=50MiB,type=boot;name=stash,size=50MiB,type=boot;name=sbmeta,size=8MiB,type=boot;name=root,size=-,type=linux,uuid=${uuid_rootfs}\0" \
-	"finduuid=part uuid mmc ${mmcdev}:${mmcpart} uuid\0" \
-	"gpt_partition=gpt write mmc ${mmcdev} $partitions\0" \
-	ENV_PUBLIC_BOOTARGS \
-	"set_bootargs=setenv bootargs console=ttyS0,115200 root=PARTUUID=${uuid} ${pub_bootargs} loglevel=${kernel_loglevel} eth=$ethaddr crashkernel=${kdump_buf}\0" \
-	"load_aon=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_aon_fpga.bin;cp.b $fwaddr $aon_ram_addr $filesize;bootaon\0"\
-	"load_c906_audio=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_c906_audio.bin;cp.b $fwaddr $audio_ram_addr $filesize\0"\
-	"load_str=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr str.bin;cp.b $fwaddr $str_ram_addr $filesize\0"\
-	"bootcmd_load=run load_aon;run load_c906_audio; ext4load mmc 0:3 $tf_addr trust_firmware.bin; ext4load mmc 0:3 $tee_addr tee.bin;ext4load mmc ${mmcdev}:${mmcbootpart} $dtb_addr ${fdt_file}; ext4load mmc ${mmcdev}:${mmcbootpart} $kernel_addr Image\0" \
-	"bootcmd=run bootcmd_load; fixup_memory_region; bootslave; run finduuid; run set_bootargs; sbmetaboot; run load_str;booti $kernel_addr - $dtb_addr;\0" \
-        "\0"
-
-#elif defined (CONFIG_LIGHT_SEC_BOOT_WITH_VERIFY_ANT_REF)
-#define CONFIG_EXTRA_ENV_SETTINGS \
-	"splashimage=0x30000000\0" \
-	"splashpos=m,m\0" \
-	"fdt_high=0xffffffffffffffff\0" \
-    ENV_STR_BOARD \
-	"tf_addr=0x100000\0" \
-	"dtb_addr=0x03800000\0" \
-	"kernel_addr=0x00200000\0" \
-	"aon_ram_addr=0xffffef8000\0" \
-	"audio_ram_addr=0x32000000\0" \
-	"str_ram_addr=0xffe0000000\0" \
-	"fwaddr=0x10000000\0"\
-	"tee_addr=0x1c000000\0" \
-	"sec_upgrade_mode=0\0"\
-	"mmcdev=0\0" \
-	"mmcpart=6\0" \
-	"mmcbootpart=2\0" \
-	ENV_KERNEL_LOGLEVEL \
-	"kdump_buf=180M\0" \
-	ENV_STR_BOOT_DELAY \
-	"uboot_version=0x0000000000000000\0"\
-	"tee_version=0x00000000\0"\
-	"tf_version=0x00000000\0"\
-	"fdt_file=th1520-ant-ref-sec.dtb\0" \
-	"uuid_rootfs=80a5a8e9-c744-491a-93c1-4f4194fd690b\0" \
-	"partitions=name=table,size=2031KB;name=boot,size=200MiB,type=boot;name=tf,size=50MiB,type=boot;name=tee,size=50MiB,type=boot;name=stash,size=50MiB,type=boot;name=root,size=-,type=linux,uuid=${uuid_rootfs}\0" \
-	"finduuid=part uuid mmc ${mmcdev}:${mmcpart} uuid\0" \
-	"gpt_partition=gpt write mmc ${mmcdev} $partitions\0" \
-	ENV_PUBLIC_BOOTARGS \
-	"set_bootargs=setenv bootargs console=ttyS0,115200 root=PARTUUID=${uuid} ${pub_bootargs} loglevel=${kernel_loglevel} eth=$ethaddr crashkernel=${kdump_buf}\0" \
-	"load_aon=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_aon_fpga.bin;cp.b $fwaddr $aon_ram_addr $filesize;bootaon\0"\
-	"load_c906_audio=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_c906_audio.bin;cp.b $fwaddr $audio_ram_addr $filesize\0"\
-	"load_str=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr str.bin;cp.b $fwaddr $str_ram_addr $filesize\0"\
-	"bootcmd_load=run load_aon;run load_c906_audio;run load_str; ext4load mmc 0:3 $tf_addr trust_firmware.bin; ext4load mmc 0:4 $tee_addr tee.bin;ext4load mmc ${mmcdev}:${mmcbootpart} $dtb_addr ${fdt_file}; ext4load mmc ${mmcdev}:${mmcbootpart} $kernel_addr Image\0" \
-	"bootcmd=run bootcmd_load; fixup_memory_region; bootslave; run finduuid; run set_bootargs; secboot; booti $kernel_addr - $dtb_addr;\0" \
-        "\0"
-
-#elif defined (CONFIG_LIGHT_SEC_BOOT_WITH_VERIFY_LPI4A)
-#define CONFIG_EXTRA_ENV_SETTINGS \
-	"splashimage=0x30000000\0" \
-	"splashpos=m,m\0" \
-	"fdt_high=0xffffffffffffffff\0" \
-    ENV_STR_BOARD \
-	"tf_addr=0x100000\0" \
-	"dtb_addr=0x03800000\0" \
-	"kernel_addr=0x00200000\0" \
-	"aon_ram_addr=0xffffef8000\0" \
-	"audio_ram_addr=0x32000000\0" \
-	"str_ram_addr=0xffe0000000\0" \
-	"fwaddr=0x10000000\0"\
-	"tee_addr=0x1c000000\0" \
-	"sec_upgrade_mode=0\0"\
-	"mmcdev=0\0" \
-	"mmcpart=8\0" \
-	"mmcbootpart=2\0" \
-	ENV_KERNEL_LOGLEVEL \
-	"sbmeta_security_level=1\0" \
-	"kdump_buf=180M\0" \
-	ENV_STR_BOOT_DELAY \
-	"uboot_version=0x0000000000000000\0"\
-	"tee_version=0x00000000\0"\
-	"tf_version=0x00000000\0"\
-	"sbmeta_version=0x00000000\0"\
-	"fdt_file=th1520-lpi4a-product-sec.dtb\0" \
-	"uuid_rootfs=80a5a8e9-c744-491a-93c1-4f4194fd690b\0" \
-	"partitions=name=table,size=2031KB;name=boot,size=200MiB,type=boot;name=tee,size=50MiB,type=boot;name=stash,size=50MiB,type=boot;name=sbmeta,size=8MiB,type=boot;name=swap,size=1536MiB,type=boot;name=fastresume,size=512MiB,type=boot;name=root,size=-,type=linux,uuid=${uuid_rootfs}\0" \
-	"finduuid=part uuid mmc ${mmcdev}:${mmcpart} uuid\0" \
-	"gpt_partition=gpt write mmc ${mmcdev} $partitions\0" \
-	ENV_PUBLIC_BOOTARGS \
-	"set_bootargs=setenv bootargs console=ttyS0,115200 root=PARTUUID=${uuid} ${pub_bootargs} loglevel=${kernel_loglevel} eth=$ethaddr crashkernel=${kdump_buf} ${resume_bootargs}\0" \
-	"load_aon=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_aon_fpga.bin;cp.b $fwaddr $aon_ram_addr $filesize;bootaon\0"\
-	"load_c906_audio=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_c906_audio.bin;cp.b $fwaddr $audio_ram_addr $filesize\0"\
-	"load_str=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr str.bin;cp.b $fwaddr $str_ram_addr $filesize\0"\
-	"bootcmd_load=run load_aon;run load_c906_audio;ext4load mmc 0:3 $tf_addr trust_firmware.bin; ext4load mmc 0:3 $tee_addr tee.bin;ext4load mmc ${mmcdev}:${mmcbootpart} $dtb_addr ${fdt_file}; ext4load mmc ${mmcdev}:${mmcbootpart} $kernel_addr Image\0" \
-	"bootcmd=run bootcmd_load; chk_hibernate; fixup_memory_region; bootslave; run finduuid; run set_bootargs; sbmetaboot; run load_str;booti $kernel_addr - $dtb_addr;\0" \
-        "\0"
-
-#elif defined(CONFIG_LIGHT_ANDROID_BOOT_IMAGE_VAL_A) || defined(CONFIG_LIGHT_ANDROID_BOOT_IMAGE_VAL_B) || \
-      defined(CONFIG_LIGHT_ANDROID_BOOT_IMAGE_VAL_LPI4A) || defined(CONFIG_LIGHT_ANDROID_BOOT_IMAGE_VAL_BEAGLE) || \
-      defined(CONFIG_LIGHT_ANDROID_BOOT_IMAGE_ANT_REF)
-#define CONFIG_EXTRA_ENV_SETTINGS \
-	"splashimage=0x30000000\0" \
-	"splashpos=m,m\0" \
-	"fdt_high=0xffffffffffffffff\0" \
-	ENV_STR_SERIAL \
 	ENV_STR_BOARD \
-	"tf_addr=0x0\0" \
-	"tee_addr=0x1c000000\0" \
-	"opensbi_addr=0x0\0" \
-	"dtb_addr=0x03800000\0" \
-	"kernel_addr=0x00200000\0" \
-	"ramdisk_addr=0x02000000\0" \
-	"aon_ram_addr=0xffffef8000\0" \
-	"audio_ram_addr=0x32000000\0" \
-	"fwaddr=0x10000000\0"\
-	"boot_ab=_a\0"\
-	"sb_emulater=1\0"\
-	"mmcdev=0\0" \
-	"mmcpart=3\0" \
+	"kernel_addr_r=0x00200000\0" \
+	"kdump_buf=180M\0" \
 	"mmcbootpart=2\0" \
-	"mmcteepart=8\0" \
-	ENV_KERNEL_LOGLEVEL \
-	ENV_KERNEL_KDUMP \
-	ENV_STR_BOOT_DELAY \
-	"fdt_file=light-val.dtb\0" \
-	"uuid_rootfs=80a5a8e9-c744-491a-93c1-4f4194fd690b\0" \
-	"partitions=name=sparse,size=2031kb;name=bootpart_a,size=16MiB;name=bootpart_b,size=16MiB;name=boot_a,size=32MiB;name=boot_b,size=32MiB;name=vendor_boot_a,size=32MiB;name=vendor_boot_b,size=32MiB;name=tee_a,size=32MiB;name=tee_b,size=32MiB;name=dtbo_a,size=8MiB;name=dtbo_b,size=8MiB;name=super,size=4096MiB;name=vbmeta_a,size=1MiB;name=vbmeta_b,size=1MiB;name=vbmeta_system_a,size=1MiB;name=vbmeta_system_b,size=1MiB;name=misc,size=2MiB;name=metadata,size=16MiB;name=userdata,size=-\0" \
-	"finduuid=part uuid mmc ${mmcdev}:${mmcpart} uuid\0" \
+	"default_mmcdev=1\0" \
+	"mmc_select=if test -e mmc ${default_mmcdev}:${mmcbootpart} ${boot_conf_file}; then mmcdev=1; else mmcdev=0; fi;\0" \
+	"boot_conf_file=/extlinux/extlinux.conf\0" \
+	"uuid_rootfsA=80a5a8e9-c744-491a-93c1-4f4194fd690a\0" \
+	"uuid_swap=5ebcaaf0-e098-43b9-beef-1f8deedd135e\0" \
+	"partitions=name=table,size=2031KB;name=boot,size=500MiB,type=boot;name=swap,size=4096MiB,type=swap,uuid=${uuid_swap};name=root,size=-,type=linux,uuid=${uuid_rootfsA}\0" \
 	"gpt_partition=gpt write mmc ${mmcdev} $partitions\0" \
-	"set_bootargs=setenv bootargs console=ttyS0,115200 earlycon clk_ignore_unused loop.max_part=7 loglevel=${kernel_loglevel} crashkernel=${kdump_buf} init=/init bootconfig video=HDMI-A-1:800x600-32@60 firmware_class.path=/vendor/firmware androidboot.serialno=${serial#}\0" \
-	"load_aon=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_aon_fpga.bin;cp.b $fwaddr $aon_ram_addr $filesize;bootaon\0"\
-	"load_c906_audio=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_c906_audio.bin;cp.b $fwaddr $audio_ram_addr $filesize\0"\
-	"sec_m_load=ext4load mmc ${mmcdev}:${mmcbootpart} $opensbi_addr fw_dynamic.bin\0"\
-	"bootcmd_load=bootandroid;secimg_load;run sec_m_load;run load_aon;run load_c906_audio;fdt addr ${dtb_addr};fdt resize 100;fdt chosen;\0" \
-	"bootcmd=run bootcmd_load; fixup_memory_region; bootslave; run finduuid; run set_bootargs; bootm $kernel_addr $ramdisk_addr:$ramdisk_size $dtb_addr;\0" \
-         "\0"
+	"load_aon=load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_aon_fpga.bin;cp.b $fwaddr $aon_ram_addr $filesize\0" \
+	"load_c906_audio=load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_c906_audio.bin;cp.b $fwaddr $audio_ram_addr $filesize\0" \
+	"load_str=load mmc ${mmcdev}:${mmcbootpart} $fwaddr str.bin;cp.b $fwaddr $str_ram_addr $filesize\0" \
+	"load_opensbi=load mmc ${mmcdev}:${mmcbootpart} $opensbi_addr fw_dynamic.bin\0" \
+	"bootcmd_load=run mmc_select; run load_aon; run load_c906_audio; run load_str; run load_opensbi\0" \
+	"bootcmd=run bootcmd_load; bootslave; sysboot mmc ${mmcdev}:${mmcbootpart} any $boot_conf_addr_r $boot_conf_file;\0" \
+	"fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
+	"\0"
 
-#else
-#if defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_A)
-#define CONFIG_EXTRA_ENV_SETTINGS \
-	"splashimage=0x30000000\0" \
-	"splashpos=m,m\0" \
-	"fdt_high=0xffffffffffffffff\0" \
-	"opensbi_addr=0x0\0" \
-	"dtb_addr=0x03800000\0" \
-	"kernel_addr=0x00200000\0" \
-	"aon_ram_addr=0xffffef8000\0" \
-	"audio_ram_addr=0x32000000\0" \
-	"str_ram_addr=0xffe0000000\0" \
-	"fwaddr=0x10000000\0"\
-    ENV_STR_BOARD \
-	"mmcdev=0\0" \
-	"mmcpart=5\0" \
-	"mmcbootpart=2\0" \
-	ENV_KERNEL_LOGLEVEL \
-	"kdump_buf=180M\0" \
-	ENV_STR_BOOT_DELAY \
-	"fdt_file=th1520-a-product.dtb\0" \
-	"uuid_rootfs=80a5a8e9-c744-491a-93c1-4f4194fd690b\0" \
-	"partitions=name=table,size=2031KB;name=boot,size=200MiB,type=boot;name=swap,size=1536MiB,type=boot;name=fastresume,size=512MiB,type=boot;name=root,size=-,type=linux,uuid=${uuid_rootfs}\0" \
-	"finduuid=part uuid mmc ${mmcdev}:${mmcpart} uuid\0" \
-	"gpt_partition=gpt write mmc ${mmcdev} $partitions\0" \
-	ENV_PUBLIC_BOOTARGS \
-	"set_bootargs=setenv bootargs console=ttyS0,115200 root=PARTUUID=${uuid} ${pub_bootargs} loglevel=${kernel_loglevel} eth=$ethaddr crashkernel=${kdump_buf} ${resume_bootargs}\0" \
-	"load_aon=ext4load mmc 0:2 $fwaddr light_aon_fpga.bin;cp.b $fwaddr $aon_ram_addr $filesize;bootaon\0"\
-	"load_c906_audio=ext4load mmc 0:2 $fwaddr light_c906_audio.bin;cp.b $fwaddr $audio_ram_addr $filesize\0"\
-	"load_str=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr str.bin;cp.b $fwaddr $str_ram_addr $filesize\0"\
-	"bootcmd_load=run load_aon;run load_c906_audio; run load_str; ext4load mmc 0:2 $opensbi_addr fw_dynamic.bin; ext4load mmc 0:2 $dtb_addr ${fdt_file}; ext4load mmc 0:2 $kernel_addr Image\0" \
-	"bootcmd=run bootcmd_load; bootslave; run finduuid; run set_bootargs; booti $kernel_addr - $dtb_addr;\0" \
-        "\0"
-#elif defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_B)
-#define CONFIG_EXTRA_ENV_SETTINGS \
-	"splashimage=0x30000000\0" \
-	"splashpos=m,m\0" \
-	"fdt_high=0xffffffffffffffff\0" \
-	"opensbi_addr=0x0\0" \
-	"dtb_addr=0x03800000\0" \
-	"kernel_addr=0x00200000\0" \
-	"aon_ram_addr=0xffffef8000\0" \
-	"audio_ram_addr=0x32000000\0" \
-	"str_ram_addr=0xffe0000000\0" \
-	"fwaddr=0x10000000\0"\
-	"mmcdev=0\0" \
-	"mmcpart=3\0" \
-	"mmcbootpart=2\0" \
-	ENV_KERNEL_LOGLEVEL \
-	"kdump_buf=180M\0" \
-	ENV_STR_BOOT_DELAY \
-	"fdt_file=th1520-b-product.dtb\0" \
-	"uuid_rootfs=80a5a8e9-c744-491a-93c1-4f4194fd690b\0" \
-	"partitions=name=table,size=2031KB;name=boot,size=200MiB,type=boot;name=root,size=-,type=linux,uuid=${uuid_rootfs}\0" \
-	"finduuid=part uuid mmc ${mmcdev}:${mmcpart} uuid\0" \
-	"gpt_partition=gpt write mmc ${mmcdev} $partitions\0" \
-	ENV_PUBLIC_BOOTARGS \
-	"set_bootargs=setenv bootargs console=ttyS0,115200 root=PARTUUID=${uuid} ${pub_bootargs} loglevel=${kernel_loglevel} eth=$ethaddr crashkernel=${kdump_buf}\0" \
-	"load_aon=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_aon_fpga.bin;cp.b $fwaddr $aon_ram_addr $filesize;bootaon\0"\
-	"load_c906_audio=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_c906_audio.bin;cp.b $fwaddr $audio_ram_addr $filesize\0"\
-	"load_str=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr str.bin;cp.b $fwaddr $str_ram_addr $filesize\0"\
-	"bootcmd_load=run load_aon;run load_c906_audio; run load_str; ext4load mmc ${mmcdev}:${mmcbootpart} $opensbi_addr fw_dynamic.bin; ext4load mmc ${mmcdev}:${mmcbootpart} $dtb_addr ${fdt_file};ext4load mmc ${mmcdev}:${mmcbootpart} $kernel_addr Image;\0" \
-	"bootcmd=run bootcmd_load; fixup_memory_region; bootslave ; run finduuid; run set_bootargs; booti $kernel_addr - $dtb_addr;\0" \
-        "\0"
-#elif defined (CONFIG_TARGET_LIGHT_FM_C910_B_REF)
-#define CONFIG_EXTRA_ENV_SETTINGS \
-	"splashimage=0x30000000\0" \
-	"splashpos=m,m\0" \
-	"fdt_high=0xffffffffffffffff\0" \
-	"opensbi_addr=0x0\0" \
-	"dtb_addr=0x03800000\0" \
-	"kernel_addr=0x00200000\0" \
-	"aon_ram_addr=0xffffef8000\0" \
-	"audio_ram_addr=0x32000000\0" \
-	"str_ram_addr=0xffe0000000\0" \
-	"fwaddr=0x10000000\0"\
-	"mmcdev=0\0" \
-	"mmcpart=3\0" \
-	"mmcbootpart=2\0" \
-	ENV_KERNEL_LOGLEVEL \
-	"kdump_buf=180M\0" \
-	ENV_STR_BOOT_DELAY \
-	"fdt_file=th1520-b-ref.dtb\0" \
-	"uuid_rootfs=80a5a8e9-c744-491a-93c1-4f4194fd690b\0" \
-	"partitions=name=table,size=2031KB;name=boot,size=200MiB,type=boot;name=root,size=-,type=linux,uuid=${uuid_rootfs}\0" \
-	"finduuid=part uuid mmc ${mmcdev}:${mmcpart} uuid\0" \
-	"gpt_partition=gpt write mmc ${mmcdev} $partitions\0" \
-	ENV_PUBLIC_BOOTARGS \
-	"set_bootargs=setenv bootargs console=ttyS0,115200 root=PARTUUID=${uuid} ${pub_bootargs} loglevel=${kernel_loglevel} eth=$ethaddr crashkernel=${kdump_buf}\0" \
-	"load_aon=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_aon_fpga.bin;cp.b $fwaddr $aon_ram_addr $filesize;bootaon\0"\
-	"load_c906_audio=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_c906_audio.bin;cp.b $fwaddr $audio_ram_addr $filesize\0"\
-	"load_str=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr str.bin;cp.b $fwaddr $str_ram_addr $filesize\0"\
-	"bootcmd_load=run load_aon;run load_c906_audio; run load_str; ext4load mmc ${mmcdev}:${mmcbootpart} $opensbi_addr fw_dynamic.bin; ext4load mmc ${mmcdev}:${mmcbootpart} $dtb_addr ${fdt_file};ext4load mmc ${mmcdev}:${mmcbootpart} $kernel_addr Image;\0" \
-	"bootcmd=run bootcmd_load; bootslave ; run finduuid; run set_bootargs; booti $kernel_addr - $dtb_addr;\0" \
-        "\0"
-#elif defined (CONFIG_TARGET_LIGHT_FM_C910_B_POWER)
-#define CONFIG_EXTRA_ENV_SETTINGS \
-	"splashimage=0x30000000\0" \
-	"splashpos=m,m\0" \
-	"fdt_high=0xffffffffffffffff\0" \
-	"opensbi_addr=0x0\0" \
-	"dtb_addr=0x03800000\0" \
-	"kernel_addr=0x00200000\0" \
-	"aon_ram_addr=0xffffef8000\0" \
-	"audio_ram_addr=0x32000000\0" \
-	"str_ram_addr=0xffe0000000\0" \
-	"fwaddr=0x10000000\0"\
-	"mmcdev=0\0" \
-	"mmcpart=3\0" \
-	"mmcbootpart=2\0" \
-	ENV_KERNEL_LOGLEVEL \
-	"kdump_buf=180M\0" \
-	ENV_STR_BOOT_DELAY \
-	"fdt_file=th1520-b-power.dtb\0" \
-	"uuid_rootfs=80a5a8e9-c744-491a-93c1-4f4194fd690b\0" \
-	"partitions=name=table,size=2031KB;name=boot,size=200MiB,type=boot;name=root,size=-,type=linux,uuid=${uuid_rootfs}\0" \
-	"finduuid=part uuid mmc ${mmcdev}:${mmcpart} uuid\0" \
-	"gpt_partition=gpt write mmc ${mmcdev} $partitions\0" \
-	ENV_PUBLIC_BOOTARGS \
-	"set_bootargs=setenv bootargs console=ttyS0,115200 root=PARTUUID=${uuid} ${pub_bootargs} loglevel=${kernel_loglevel} eth=$ethaddr crashkernel=${kdump_buf}\0" \
-	"load_aon=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_aon_fpga.bin;cp.b $fwaddr $aon_ram_addr $filesize;bootaon\0"\
-	"load_c906_audio=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_c906_audio.bin;cp.b $fwaddr $audio_ram_addr $filesize\0"\
-	"load_str=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr str.bin;cp.b $fwaddr $str_ram_addr $filesize\0"\
-	"bootcmd_load=run load_aon;run load_c906_audio; run load_str; ext4load mmc ${mmcdev}:${mmcbootpart} $opensbi_addr fw_dynamic.bin; ext4load mmc ${mmcdev}:${mmcbootpart} $dtb_addr ${fdt_file}; ext4load mmc ${mmcdev}:${mmcbootpart} $kernel_addr Image\0" \
-	"bootcmd=run bootcmd_load; bootslave; run finduuid; run set_bootargs; booti $kernel_addr - $dtb_addr;\0" \
-        "\0"
-#elif defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_REF)
-#define CONFIG_EXTRA_ENV_SETTINGS \
-	"splashimage=0x30000000\0" \
-	"splashpos=m,m\0" \
-	"fdt_high=0xffffffffffffffff\0" \
-	"opensbi_addr=0x0\0" \
-	"dtb_addr=0x03800000\0" \
-	"kernel_addr=0x00200000\0" \
-	"aon_ram_addr=0xffffef8000\0" \
-	"audio_ram_addr=0x32000000\0" \
-	"str_ram_addr=0xffe0000000\0" \
-	"fwaddr=0x10000000\0"\
-	"mmcdev=0\0" \
-	"mmcpart=3\0" \
-	"mmcbootpart=2\0" \
-	ENV_KERNEL_LOGLEVEL \
-	"kdump_buf=180M\0" \
-	ENV_STR_BOOT_DELAY \
-	"fdt_file=th1520-ant-ref.dtb\0" \
-	"uuid_rootfs=80a5a8e9-c744-491a-93c1-4f4194fd690b\0" \
-	"partitions=name=table,size=2031KB;name=boot,size=200MiB,type=boot;name=root,size=-,type=linux,uuid=${uuid_rootfs}\0" \
-	"finduuid=part uuid mmc ${mmcdev}:${mmcpart} uuid\0" \
-	"gpt_partition=gpt write mmc ${mmcdev} $partitions\0" \
-	ENV_PUBLIC_BOOTARGS \
-	"set_bootargs=setenv bootargs console=ttyS0,115200 root=PARTUUID=${uuid} ${pub_bootargs} loglevel=${kernel_loglevel} eth=$ethaddr crashkernel=${kdump_buf}\0" \
-	"load_aon=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_aon_fpga.bin;cp.b $fwaddr $aon_ram_addr $filesize;bootaon\0"\
-	"load_c906_audio=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_c906_audio.bin;cp.b $fwaddr $audio_ram_addr $filesize\0"\
-	"load_str=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr str.bin;cp.b $fwaddr $str_ram_addr $filesize\0"\
-	"bootcmd_load=run load_aon;run load_c906_audio; run load_str; ext4load mmc ${mmcdev}:${mmcbootpart} $opensbi_addr fw_dynamic.bin; ext4load mmc ${mmcdev}:${mmcbootpart} $dtb_addr ${fdt_file}; ext4load mmc ${mmcdev}:${mmcbootpart} $kernel_addr Image\0" \
-	"bootcmd=run bootcmd_load; fixup_memory_region; bootslave; run finduuid; run set_bootargs; booti $kernel_addr - $dtb_addr;\0" \
-        "\0"
-#elif defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_DISCRETE)
-#define CONFIG_EXTRA_ENV_SETTINGS \
-	"splashimage=0x30000000\0" \
-	"splashpos=m,m\0" \
-	"fdt_high=0xffffffffffffffff\0" \
-	"opensbi_addr=0x0\0" \
-	"dtb_addr=0x03800000\0" \
-	"kernel_addr=0x00200000\0" \
-	"aon_ram_addr=0xffffef8000\0" \
-	"audio_ram_addr=0x32000000\0" \
-	"str_ram_addr=0xffe0000000\0" \
-	"fwaddr=0x10000000\0"\
-	"mmcdev=0\0" \
-	"mmcpart=3\0" \
-	"mmcbootpart=2\0" \
-	ENV_KERNEL_LOGLEVEL \
-	"kdump_buf=180M\0" \
-	ENV_STR_BOOT_DELAY \
-	"fdt_file=th1520-ant-discrete.dtb\0" \
-	"uuid_rootfs=80a5a8e9-c744-491a-93c1-4f4194fd690b\0" \
-	"partitions=name=table,size=2031KB;name=boot,size=200MiB,type=boot;name=root,size=-,type=linux,uuid=${uuid_rootfs}\0" \
-	"finduuid=part uuid mmc ${mmcdev}:${mmcpart} uuid\0" \
-	"gpt_partition=gpt write mmc ${mmcdev} $partitions\0" \
-	ENV_PUBLIC_BOOTARGS \
-	"set_bootargs=setenv bootargs console=ttyS0,115200 root=PARTUUID=${uuid} ${pub_bootargs} loglevel=${kernel_loglevel} eth=$ethaddr crashkernel=${kdump_buf}\0" \
-	"load_aon=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_aon_fpga.bin;cp.b $fwaddr $aon_ram_addr $filesize;bootaon\0"\
-	"load_c906_audio=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_c906_audio.bin;cp.b $fwaddr $audio_ram_addr $filesize\0"\
-	"load_str=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr str.bin;cp.b $fwaddr $str_ram_addr $filesize\0"\
-	"bootcmd_load=run load_aon;run load_c906_audio; run load_str; ext4load mmc ${mmcdev}:${mmcbootpart} $opensbi_addr fw_dynamic.bin; ext4load mmc ${mmcdev}:${mmcbootpart} $dtb_addr ${fdt_file}; ext4load mmc ${mmcdev}:${mmcbootpart} $kernel_addr Image\0" \
-	"bootcmd=run bootcmd_load; bootslave; run finduuid; run set_bootargs; booti $kernel_addr - $dtb_addr;\0" \
-        "\0"
-#elif defined (CONFIG_TARGET_LIGHT_FM_C910_BEAGLE)
-#define CONFIG_EXTRA_ENV_SETTINGS \
-	"splashimage=0x30000000\0" \
-	"splashpos=m,m\0" \
-	"fdt_high=0xffffffffffffffff\0" \
-	"opensbi_addr=0x0\0" \
-	"dtb_addr=0x03800000\0" \
-	"kernel_addr=0x00200000\0" \
-	"aon_ram_addr=0xffffef8000\0" \
-	"audio_ram_addr=0x32000000\0" \
-	"str_ram_addr=0xffe0000000\0" \
-	"fwaddr=0x10000000\0"\
-	"mmcdev=0\0" \
-	"mmcpart=3\0" \
-	"mmcbootpart=2\0" \
-	ENV_KERNEL_LOGLEVEL \
-	"kdump_buf=180M\0" \
-	ENV_STR_BOOT_DELAY \
-	"fdt_file=th1520-beagle.dtb\0" \
-	"uuid_rootfs=80a5a8e9-c744-491a-93c1-4f4194fd690b\0" \
-	"partitions=name=table,size=2031KB;name=boot,size=200MiB,type=boot;name=root,size=-,type=linux,uuid=${uuid_rootfs}\0" \
-	"finduuid=part uuid mmc ${mmcdev}:${mmcpart} uuid\0" \
-	"gpt_partition=gpt write mmc ${mmcdev} $partitions\0" \
-	ENV_PUBLIC_BOOTARGS \
-	"set_bootargs=setenv bootargs console=ttyS0,115200 root=PARTUUID=${uuid} ${pub_bootargs} loglevel=${kernel_loglevel} eth=$ethaddr crashkernel=${kdump_buf}\0" \
-	"load_aon=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_aon_fpga.bin;cp.b $fwaddr $aon_ram_addr $filesize;bootaon\0"\
-	"load_c906_audio=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_c906_audio.bin;cp.b $fwaddr $audio_ram_addr $filesize\0"\
-	"load_str=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr str.bin;cp.b $fwaddr $str_ram_addr $filesize\0"\
-	"bootcmd_load=run load_aon;run load_c906_audio; run load_str; ext4load mmc ${mmcdev}:${mmcbootpart} $opensbi_addr fw_dynamic.bin; ext4load mmc ${mmcdev}:${mmcbootpart} $dtb_addr ${fdt_file}; ext4load mmc ${mmcdev}:${mmcbootpart} $kernel_addr Image\0" \
-	"bootcmd=run bootcmd_load; fixup_memory_region; bootslave; run finduuid; run set_bootargs; booti $kernel_addr - $dtb_addr;\0" \
-        "\0"
-#elif defined (CONFIG_TARGET_LIGHT_FM_C910_LPI4A)
-#define CONFIG_EXTRA_ENV_SETTINGS \
-	"splashimage=0x30000000\0" \
-	"splashpos=m,m\0" \
-	"fdt_high=0xffffffffffffffff\0" \
-	"opensbi_addr=0x0\0" \
-	"dtb_addr=0x03800000\0" \
-	"kernel_addr=0x00200000\0" \
-	"aon_ram_addr=0xffffef8000\0" \
-	"audio_ram_addr=0x32000000\0" \
-	"str_ram_addr=0xffe0000000\0" \
-	"fwaddr=0x10000000\0"\
-	"mmcdev=0\0" \
-	"mmcpart=5\0" \
-	"mmcbootpart=2\0" \
-	ENV_KERNEL_LOGLEVEL \
-	"kdump_buf=180M\0" \
-	ENV_STR_BOOT_DELAY \
-	"fdt_file=th1520-lpi4a-product.dtb\0" \
-	"uuid_rootfs=80a5a8e9-c744-491a-93c1-4f4194fd690b\0" \
-	"partitions=name=table,size=2031KB;name=boot,size=200MiB,type=boot;name=swap,size=1536MiB,type=boot;name=fastresume,size=512MiB,type=boot;name=root,size=-,type=linux,uuid=${uuid_rootfs}\0" \
-	"finduuid=part uuid mmc ${mmcdev}:${mmcpart} uuid\0" \
-	"gpt_partition=gpt write mmc ${mmcdev} $partitions\0" \
-	ENV_PUBLIC_BOOTARGS \
-	"set_bootargs=setenv bootargs console=ttyS0,115200 root=PARTUUID=${uuid} ${pub_bootargs} loglevel=${kernel_loglevel} eth=$ethaddr crashkernel=${kdump_buf} ${resume_bootargs}\0" \
-	"load_aon=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_aon_fpga.bin;cp.b $fwaddr $aon_ram_addr $filesize;bootaon\0"\
-	"load_c906_audio=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_c906_audio.bin;cp.b $fwaddr $audio_ram_addr $filesize\0"\
-	"load_str=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr str.bin;cp.b $fwaddr $str_ram_addr $filesize\0"\
-	"bootcmd_load=run load_aon;run load_c906_audio; run load_str; ext4load mmc ${mmcdev}:${mmcbootpart} $opensbi_addr fw_dynamic.bin; ext4load mmc ${mmcdev}:${mmcbootpart} $dtb_addr ${fdt_file}; ext4load mmc ${mmcdev}:${mmcbootpart} $kernel_addr Image\0" \
-	"bootcmd=run bootcmd_load; chk_hibernate; fixup_memory_region; bootslave; run finduuid; run set_bootargs; booti $kernel_addr - $dtb_addr;\0" \
-        "\0"
-#elif defined (CONFIG_TARGET_LIGHT_FM_C910_A_REF)
-#define CONFIG_EXTRA_ENV_SETTINGS \
-	"splashimage=0x30000000\0" \
-	"splashpos=m,m\0" \
-	"fdt_high=0xffffffffffffffff\0" \
-	"opensbi_addr=0x0\0" \
-	"dtb_addr=0x03800000\0" \
-	"kernel_addr=0x00200000\0" \
-	"aon_ram_addr=0xffffef8000\0" \
-	"audio_ram_addr=0x32000000\0" \
-	"str_ram_addr=0xffe0000000\0" \
-	"fwaddr=0x10000000\0"\
-	"mmcdev=0\0" \
-	"mmcpart=3\0" \
-	"mmcbootpart=2\0" \
-	ENV_KERNEL_LOGLEVEL \
-	"kdump_buf=180M\0" \
-	ENV_STR_BOOT_DELAY \
-	"fdt_file=th1520-a-ref.dtb\0" \
-	"uuid_rootfs=80a5a8e9-c744-491a-93c1-4f4194fd690b\0" \
-	"partitions=name=table,size=2031KB;name=boot,size=200MiB,type=boot;name=root,size=-,type=linux,uuid=${uuid_rootfs}\0" \
-	"finduuid=part uuid mmc ${mmcdev}:${mmcpart} uuid\0" \
-	"gpt_partition=gpt write mmc ${mmcdev} $partitions\0" \
-	ENV_PUBLIC_BOOTARGS \
-	"set_bootargs=setenv bootargs console=ttyS0,115200 root=PARTUUID=${uuid} ${pub_bootargs} loglevel=${kernel_loglevel} eth=$ethaddr crashkernel=${kdump_buf}\0" \
-	"load_aon=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_aon_fpga.bin;cp.b $fwaddr $aon_ram_addr $filesize;bootaon\0"\
-	"load_c906_audio=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_c906_audio.bin;cp.b $fwaddr $audio_ram_addr $filesize\0"\
-	"load_str=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr str.bin;cp.b $fwaddr $str_ram_addr $filesize\0"\
-	"bootcmd_load=run load_aon;run load_c906_audio; run load_str; ext4load mmc ${mmcdev}:${mmcbootpart} $opensbi_addr fw_dynamic.bin; ext4load mmc ${mmcdev}:${mmcbootpart} $dtb_addr ${fdt_file}; ext4load mmc ${mmcdev}:${mmcbootpart} $kernel_addr Image\0" \
-	"bootcmd=run bootcmd_load; bootslave; run finduuid; run set_bootargs; booti $kernel_addr - $dtb_addr;\0" \
-        "\0"
-#else
-#define CONFIG_EXTRA_ENV_SETTINGS \
-	"splashimage=0x30000000\0" \
-	"splashpos=m,m\0" \
-	"fdt_high=0xffffffffffffffff\0" \
-	"opensbi_addr=0x0\0" \
-	"dtb_addr=0x03800000\0" \
-	"kernel_addr=0x00200000\0" \
-	"aon_ram_addr=0xffffef8000\0" \
-	"audio_ram_addr=0x32000000\0" \
-	"str_ram_addr=0xffe0000000\0" \
-	"fwaddr=0x10000000\0"\
-	"mmcdev=0\0" \
-	"mmcpart=5\0" \
-	"mmcbootpart=2\0" \
-	ENV_KERNEL_LOGLEVEL \
-	"kdump_buf=180M\0" \
-	ENV_STR_BOOT_DELAY \
-	"fdt_file=th1520-a-val.dtb\0" \
-	"uuid_rootfs=80a5a8e9-c744-491a-93c1-4f4194fd690b\0" \
-	"partitions=name=table,size=2031KB;name=boot,size=200MiB,type=boot;name=swap,size=1536MiB,type=boot;name=fastresume,size=512MiB,type=boot;name=root,size=-,type=linux,uuid=${uuid_rootfs}\0" \
-	"finduuid=part uuid mmc ${mmcdev}:${mmcpart} uuid\0" \
-	"gpt_partition=gpt write mmc ${mmcdev} $partitions\0" \
-	ENV_PUBLIC_BOOTARGS \
-	"set_bootargs=setenv bootargs console=ttyS0,115200 root=PARTUUID=${uuid} ${pub_bootargs} loglevel=${kernel_loglevel} eth=$ethaddr crashkernel=${kdump_buf} ${resume_bootargs}\0" \
-	"load_aon=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_aon_fpga.bin;cp.b $fwaddr $aon_ram_addr $filesize;bootaon\0"\
-	"load_c906_audio=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_c906_audio.bin;cp.b $fwaddr $audio_ram_addr $filesize\0"\
-	"load_str=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr str.bin;cp.b $fwaddr $str_ram_addr $filesize\0"\
-	"bootcmd_load=run load_aon;run load_c906_audio; run load_str; ext4load mmc ${mmcdev}:${mmcbootpart} $opensbi_addr fw_dynamic.bin; ext4load mmc ${mmcdev}:${mmcbootpart} $dtb_addr ${fdt_file}; ext4load mmc ${mmcdev}:${mmcbootpart} $kernel_addr Image\0" \
-	"bootcmd=run bootcmd_load; chk_hibernate; fixup_memory_region; bootslave; run finduuid; run set_bootargs; booti $kernel_addr - $dtb_addr;\0" \
-        "\0"
-#endif
-#endif
 #endif /* __CONFIG_H */

include/dt-bindings/pmic/light_pmic.h

@@ -1,55 +0,0 @@
-#ifndef __LIGHT_PMIC_H_
-#define __LIGHT_PMIC_H_
-
-/*for da9063*/
-#define DA9063_ID_BCORE1   0
-#define DA9063_ID_BCORE2   1
-#define DA9063_ID_BUCKPRO  2
-#define DA9063_ID_BUCKMEM  3
-#define DA9063_ID_BUCKIO   4
-#define DA9063_ID_BUCKPERI 5
-#define DA9063_ID_LDO1     6
-#define DA9063_ID_LDO2     7
-#define DA9063_ID_LDO3     8
-#define DA9063_ID_LDO4     9
-#define DA9063_ID_LDO5     10
-#define DA9063_ID_LDO9     11
-#define DA9063_ID_LDO10    12
-#define DA9063_ID_LDO11    13
-#define DA9063_ID_LDO6     14
-#define DA9063_ID_LDO7     15
-#define DA9063_ID_LDO8     16
-#define DA9063_ID_GPIO4    17
-#define DA9063_ID_GPIO7    18
-
-/*for da9121*/
-#define DA9121_ID_BUCK1  0
-
-
-/* for slg51000*/
-
-#define SLG51000_ID_LDO1   0
-#define SLG51000_ID_LDO2   1
-#define SLG51000_ID_LDO3   2
-#define SLG51000_ID_LDO4   3
-#define SLG51000_ID_LDO5   4
-#define SLG51000_ID_LDO6   5
-#define SLG51000_ID_LDO7   6
-
-
-/* for ricoh567*/
-#define RICOH567_ID_DC1     0
-#define RICOH567_ID_DC2     1
-#define RICOH567_ID_DC3     2
-#define RICOH567_ID_DC4     3
-#define RICOH567_ID_LDO1    4
-#define RICOH567_ID_LDO2    5
-#define RICOH567_ID_LDO3    6
-#define RICOH567_ID_LDO4    7
-#define RICOH567_ID_LDO5    8
-#define RICOH567_ID_LDORTC1 9
-#define RICOH567_ID_LDORTC2 10
-#define RICOH567_ID_GPIO3   11
-
-
-#endif

include/extension_board.h

@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2021
+ * Köry Maincent, Bootlin, <kory.maincent@bootlin.com>
+ */
+
+#ifndef __EXTENSION_SUPPORT_H
+#define __EXTENSION_SUPPORT_H
+
+struct extension {
+	struct list_head list;
+	char name[32];
+	char owner[32];
+	char version[32];
+	char overlay[32];
+	char other[32];
+};
+
+/**
+ * extension_board_scan - Add system-specific function to scan extension board.
+ * @param extension_list	List of extension board information to update.
+ * @return the number of extension.
+ *
+ * This function is called if CONFIG_CMD_EXTENSION is defined.
+ * Needs to fill the list extension_list with elements.
+ * Each element need to be allocated to an extension structure.
+ *
+ */
+int extension_board_scan(struct list_head *extension_list);
+
+#endif /* __EXTENSION_SUPPORT_H */

include/fdt_support.h

@@ -326,6 +326,8 @@ int fdt_setup_simplefb_node(void *fdt, int node, u64 base_address, u32 width,
 
 int fdt_overlay_apply_verbose(void *fdt, void *fdto);
 
+int fdt_valid(struct fdt_header **blobp);
+
 /**
  * fdt_get_cells_len() - Get the length of a type of cell in top-level nodes
  *

test/py/tests/test_extension.py

@@ -0,0 +1,53 @@
+# SPDX-License-Identifier:  GPL-2.0+
+# Copyright (c) 2020
+# Author: Kory Maincent <kory.maincent@bootlin.com>
+
+# Test U-Boot's "extension" commands.
+
+import os
+import pytest
+import u_boot_utils
+
+overlay_addr = 0x1000
+
+SANDBOX_DTB='arch/sandbox/dts/sandbox.dtb'
+OVERLAY_DIR='arch/sandbox/dts/'
+
+def load_dtb(u_boot_console):
+    u_boot_console.log.action('Loading devicetree to RAM...')
+    u_boot_console.run_command('host load hostfs - $fdt_addr_r %s' % (os.path.join(u_boot_console.config.build_dir, SANDBOX_DTB)))
+    u_boot_console.run_command('fdt addr $fdt_addr_r')
+
+@pytest.mark.buildconfigspec('cmd_fdt')
+@pytest.mark.boardspec('sandbox')
+def test_extension(u_boot_console):
+    """Test the 'extension' command."""
+
+    load_dtb(u_boot_console)
+
+    output = u_boot_console.run_command('extension list')
+    assert('No extension' in output)
+
+    output = u_boot_console.run_command('extension scan')
+    assert output == 'Found 2 extension board(s).'
+
+    output = u_boot_console.run_command('extension list')
+    assert('overlay0.dtbo' in output)
+    assert('overlay1.dtbo' in output)
+
+    u_boot_console.run_command_list([
+        'setenv extension_overlay_addr %s' % (overlay_addr),
+        'setenv extension_overlay_cmd \'host load hostfs - ${extension_overlay_addr} %s${extension_overlay_name}\'' % (os.path.join(u_boot_console.config.build_dir, OVERLAY_DIR))])
+
+    output = u_boot_console.run_command('extension apply 0')
+    assert('bytes read' in output)
+
+    output = u_boot_console.run_command('fdt print')
+    assert('button3' in output)
+
+    output = u_boot_console.run_command('extension apply all')
+    assert('bytes read' in output)
+
+    output = u_boot_console.run_command('fdt print')
+    assert('button4' in output)
+