Linux_SDK_V1.2.1

Signed-off-by: thead_admin <occ_thead@service.alibaba.com>

Kconfig

@@ -302,7 +302,7 @@ menu "Boot images"
 
 config ANDROID_BOOT_IMAGE
 	bool "Enable support for Android Boot Images"
-	default y if FASTBOOT
+	default n if FASTBOOT
 	help
 	  This enables support for booting images which use the Android
 	  image format header.

Makefile

@@ -219,7 +219,7 @@ endif
 
 ifeq ($(KBUILD_SRC),)
         # building in the source tree
-        srctree := .
+        srctree := $(shell pwd)
 else
         ifeq ($(KBUILD_SRC)/,$(dir $(CURDIR)))
                 # building in a subdirectory of the source tree
@@ -726,6 +726,7 @@ UBOOTINCLUDE    := \
 			$(if $(CONFIG_HAS_THUMB2),, \
 				-I$(srctree)/arch/$(ARCH)/thumb1/include),) \
 		-I$(srctree)/arch/$(ARCH)/include \
+		$(if $(CONFIG_TARGET_LIGHT_C910), -I$(srctree)/lib/sec_library/include) \
 		-include $(srctree)/include/linux/kconfig.h
 
 NOSTDINC_FLAGS += -nostdinc -isystem $(shell $(CC) -print-file-name=include)
@@ -811,7 +812,7 @@ PLATFORM_LIBGCC := -L $(shell dirname `$(CC) $(c_flags) -print-libgcc-file-name`
 endif
 PLATFORM_LIBS += $(PLATFORM_LIBGCC)
 ifeq ($(CONFIG_TARGET_LIGHT_C910),y)
-PLATFORM_LIBS += -L $(shell pwd)/lib/sec_library -lsec_library
+PLATFORM_LIBS += -L $(srctree)/lib/sec_library -lsec_library
 endif
 
 ifdef CONFIG_CC_COVERAGE

arch/riscv/cpu/c9xx/cpu.c

@@ -141,8 +141,9 @@ void dcache_enable(void)
 #ifdef CONFIG_SPL_RISCV_MMODE
 #ifdef CONFIG_TARGET_LIGHT_C910
 	asm volatile (
-        "li x29, 0x11ff\n\t"
-        "csrw mhcr, x29\n\t"
+		"csrr x29, mhcr\n\t"
+        "ori x28, x29, 0x2\n\t"
+        "csrw mhcr, x28\n\t"
     );
 #endif
 #endif

arch/riscv/cpu/start.S

@@ -41,6 +41,12 @@ secondary_harts_relocation_error:
 _start:
 
 #if (defined CONFIG_SPL_BUILD) && (defined CONFIG_TARGET_LIGHT_C910)
+	/* Disable indirect branch prediction once entering into uboot world */
+	li t0, 0x117f
+	csrw 0x7c1, t0
+	/* Disable fence broadcase and HW TLB */
+	li t0, 0x66e30c
+	csrw 0x7c5, t0
 	/* Enable cache ASAP as LIGHT's requirement */
 	jal	icache_enable
 	jal	dcache_enable

arch/riscv/dts/Makefile

@@ -5,7 +5,7 @@ dtb-$(CONFIG_TARGET_SIFIVE_FU540) += hifive-unleashed-a00.dtb
 dtb-$(CONFIG_TARGET_ICE_C910) += ice-c910.dtb
 dtb-$(CONFIG_TARGET_LIGHT_EVB_MPW_C910) += light-evb-mpw-c910.dtb
 dtb-$(CONFIG_TARGET_LIGHT_FPGA_FM_C910) += light-fpga-fm-c910.dtb
-dtb-$(CONFIG_TARGET_LIGHT_C910) += light-a-ref.dtb light-b-ref.dtb light-a-val.dtb light-b-product.dtb light-a-product.dtb light-ant-ref.dtb light-beagle.dtb light-b-power.dtb
+dtb-$(CONFIG_TARGET_LIGHT_C910) += light-a-ref.dtb light-b-ref.dtb light-a-val.dtb light-b-product.dtb light-a-product.dtb light-ant-ref.dtb light-beagle.dtb light-b-power.dtb light-lpi4a.dtb
 
 targets += $(dtb-y)
 

arch/riscv/dts/light-lpi4a.dts

@@ -0,0 +1,488 @@
+/dts-v1/;
+/ {
+	model = "T-HEAD c910 light";
+	compatible = "thead,c910_light";
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	memory@0 {
+		device_type = "memory";
+		reg = <0x0 0xc0000000 0x0 0x40000000>;
+	};
+
+	aliases {
+		spi0 = &spi0;
+		spi1 = &qspi0;
+		spi2 = &qspi1;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		timebase-frequency = <3000000>;
+		u-boot,dm-pre-reloc;
+		cpu@0 {
+			device_type = "cpu";
+			reg = <0>;
+			status = "okay";
+			compatible = "riscv";
+			riscv,isa = "rv64imafdcvsu";
+			mmu-type = "riscv,sv39";
+			u-boot,dm-pre-reloc;
+		};
+	};
+
+	soc {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		compatible = "simple-bus";
+		ranges;
+		u-boot,dm-pre-reloc;
+
+		intc: interrupt-controller@ffd8000000 {
+			compatible = "riscv,plic0";
+			reg = <0xff 0xd8000000 0x0 0x04000000>;
+			status = "disabled";
+		};
+
+		dummy_apb: apb-clock {
+			compatible = "fixed-clock";
+			clock-frequency = <62500000>;
+			clock-output-names = "dummy_apb";
+			#clock-cells = <0>;
+			u-boot,dm-pre-reloc;
+		};
+
+		dummy_ahb: ahb-clock {
+			compatible = "fixed-clock";
+			clock-frequency = <250000000>;
+			clock-output-names = "core";
+			#clock-cells = <0>;
+			u-boot,dm-pre-reloc;
+		};
+
+		dummy_spi: spi-clock {
+			compatible = "fixed-clock";
+			clock-frequency = <396000000>;
+			clock-output-names = "dummy_spi";
+			#clock-cells = <0>;
+			u-boot,dm-pre-reloc;
+		};
+
+		dummy_qspi0: qspi0-clock {
+			compatible = "fixed-clock";
+			clock-frequency = <792000000>;
+			clock-output-names = "dummy_qspi0";
+			#clock-cells = <0>;
+			u-boot,dm-pre-reloc;
+		};
+
+		dummy_uart_sclk: uart-sclk-clock {
+			compatible = "fixed-clock";
+			clock-frequency = <100000000>;
+			clock-output-names = "dummy_uart_sclk";
+			#clock-cells = <0>;
+			u-boot,dm-pre-reloc;
+		};
+
+		dummy_i2c_icclk: i2c-icclk-clock {
+			compatible = "fixed-clock";
+			clock-frequency = <50000000>;
+			clock-output-names = "dummy_i2c_icclk";
+			#clock-cells = <0>;
+			u-boot,dm-pre-reloc;
+		};
+
+		dummy_dpu_pixclk: dpu-pix-clock {
+			compatible = "fixed-clock";
+			clock-frequency = <74250000>;
+			clock-output-names = "dummy_dpu_pixclk";
+			#clock-cells = <0>;
+			u-boot,dm-pre-reloc;
+		};
+
+		dummy_dphy_refclk: dphy-ref-clock {
+			compatible = "fixed-clock";
+			clock-frequency = <24000000>;
+			clock-output-names = "dummy_dpu_refclk";
+			#clock-cells = <0>;
+			u-boot,dm-pre-reloc;
+		};
+
+		i2c0: i2c@ffe7f20000 {
+			compatible = "snps,designware-i2c";
+			reg = <0xff 0xe7f20000 0x0 0x4000>;
+			clocks = <&dummy_i2c_icclk>;
+			clock-frequency = <100000>;
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c1: i2c@ffe7f24000{
+			compatible = "snps,designware-i2c";
+			reg = <0xff 0xe7f24000 0x0 0x4000>;
+			clocks = <&dummy_i2c_icclk>;
+			clock-frequency = <100000>;
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c2: i2c@ffec00c000{
+			compatible = "snps,designware-i2c";
+			reg = <0xff 0xec00c000 0x0 0x4000>;
+			clocks = <&dummy_i2c_icclk>;
+			clock-frequency = <100000>;
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c3: i2c@ffec014000{
+			compatible = "snps,designware-i2c";
+			reg = <0xff 0xec014000 0x0 0x4000>;
+			clocks = <&dummy_i2c_icclk>;
+			clock-frequency = <100000>;
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c4: i2c@ffe7f28000{
+			compatible = "snps,designware-i2c";
+			reg = <0xff 0xe7f28000 0x0 0x4000>;
+			clocks = <&dummy_i2c_icclk>;
+			clock-frequency = <100000>;
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			pcal6408ahk_a: gpio@20 {
+				compatible = "nxp,pca9554";
+				reg = <0x20>;
+				gpio-controller;
+				#gpio-cells = <2>;
+			};
+		};
+
+		i2c5: i2c@fff7f2c000{
+			compatible = "snps,designware-i2c";
+			reg = <0xff 0xf7f2c000 0x0 0x4000>;
+			clocks = <&dummy_i2c_icclk>;
+			clock-frequency = <100000>;
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		serial@ffe7014000 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0xff 0xe7014000 0x0 0x400>;
+			clocks = <&dummy_uart_sclk>;
+			clock-frequency = <100000000>;
+			clock-names = "baudclk";
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			u-boot,dm-pre-reloc;
+		};
+
+		gmac0: ethernet@ffe7070000 {
+			compatible = "snps,dwmac";
+			reg = <0xff 0xe7070000 0x0 0x2000>;
+			clocks = <&dummy_apb>;
+			clock-names = "stmmaceth";
+			snps,pbl = <32>;
+			snps,fixed-burst;
+
+			phy-mode = "rgmii-id";
+			phy-handle = <&phy_88E1111_a>;
+			status = "okay";
+			mdio0 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "snps,dwmac-mdio";
+
+				phy_88E1111_a: ethernet-phy@1 {
+					reg = <0x1>;
+				};
+
+				phy_88E1111_b: ethernet-phy@2 {
+					reg = <0x2>;
+				};
+			};
+		};
+
+		gmac1: ethernet@ffe7060000 {
+			compatible = "snps,dwmac";
+			reg = <0xff 0xe7060000 0x0 0x2000>;
+			clocks = <&dummy_apb>;
+			clock-names = "stmmaceth";
+			snps,pbl = <32>;
+			snps,fixed-burst;
+			phy-mode = "rgmii-id";
+			phy-handle = <&phy_88E1111_b>;
+			status = "okay";
+		};
+
+		emmc: sdhci@ffe7080000 {
+			compatible = "snps,dwcmshc-sdhci";
+			reg = <0xff 0xe7080000 0x0 0x10000>;
+			index = <0x0>;
+			clocks = <&dummy_ahb>;
+			clock-frequency = <198000000>;
+			clock-names = "core";
+			max-frequency = <198000000>;
+			sdhci-caps-mask = <0x0 0x1000000>;
+			mmc-hs400-1_8v;
+			non-removable;
+			no-sdio;
+			no-sd;
+			bus-width = <8>;
+			voltage= "1.8v";
+			pull_up;
+			io_fixed_1v8;
+			fifo-mode;
+			u-boot,dm-pre-reloc;
+		};
+
+		sdhci0: sd@ffe7090000 {
+			compatible = "snps,dwcmshc-sdhci";
+			reg = <0xff 0xe7090000 0x0 0x10000>;
+			index = <0x1>;
+			clocks = <&dummy_ahb>;
+			clock-frequency = <198000000>;
+			max-frequency = <198000000>;
+			sd-uhs-sdr104;
+			pull_up;
+			clock-names = "core";
+			bus-width = <4>;
+			voltage= "3.3v";
+		};
+
+		qspi0: spi@ffea000000 {
+			compatible = "snps,dw-apb-ssi-quad";
+			reg = <0xff 0xea000000 0x0 0x1000>;
+			clocks = <&dummy_qspi0>;
+			num-cs = <1>;
+			cs-gpio = <&gpio2_porta 3 0>; // GPIO_ACTIVE_HIGH: 0
+			spi-max-frequency = <100000000>;
+			#address-cells = <1>;
+			#size-cells =<0>;
+			spi-flash@0 {
+				#address-cells = <1>;
+				#size-cells = <1>;
+				compatible = "spi-nand";
+				spi-tx-bus-width = <4>;
+				spi-rx-bus-width = <4>;
+				reg = <0>;
+			};
+		};
+
+		qspi1: spi@fff8000000 {
+			compatible = "snps,dw-apb-ssi-quad";
+			reg = <0xff 0xf8000000 0x0 0x1000>;
+			clocks = <&dummy_spi>;
+			num-cs = <1>;
+			cs-gpio = <&gpio0_porta 1 0>; // GPIO_ACTIVE_HIGH: 0
+			spi-max-frequency = <66000000>;
+			#address-cells = <1>;
+			#size-cells =<0>;
+			spi-flash@0 {
+				#address-cells = <1>;
+				#size-cells = <1>;
+				compatible = "spi-nand";
+				spi-tx-bus-width = <4>;
+				spi-rx-bus-width = <4>;
+				reg = <0>;
+			};
+		};
+
+		spi0: spi@ffe700c000 {
+			compatible = "snps,dw-apb-ssi";
+			reg = <0xff 0xe700c000 0x0 0x1000>;
+			clocks = <&dummy_spi>;
+			cs-gpio = <&gpio2_porta 15 0>;
+			spi-max-frequency = <100000000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			flash@0 {
+				compatible = "jedec,spi-nor";
+				reg = <0>;
+				spi-max-frequency = <40000000>;
+			};
+		};
+
+		gpio2: gpio@ffe7f34000 {
+			compatible = "snps,dw-apb-gpio";
+			reg = <0xff 0xe7f34000 0x0 0x1000>;
+			clocks = <&dummy_apb>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			gpio2_porta: gpio-controller@0 {
+				compatible = "snps,dw-apb-gpio-port";
+				gpio-controller;
+				#gpio-cells = <2>;
+				snps,nr-gpios = <32>;
+				reg = <0>;
+			};
+		};
+
+		gpio0: gpio@ffec005000 {
+			compatible = "snps,dw-apb-gpio";
+			reg = <0xff 0xec005000 0x0 0x1000>;
+			clocks = <&dummy_apb>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			gpio0_porta: gpio-controller@0 {
+				compatible = "snps,dw-apb-gpio-port";
+				gpio-controller;
+				#gpio-cells = <2>;
+				snps,nr-gpios = <32>;
+				reg = <0>;
+			};
+		};
+
+		gpio1: gpio@ffec006000 {
+			compatible = "snps,dw-apb-gpio";
+			reg = <0xff 0xec006000 0x0 0x1000>;
+			clocks = <&dummy_apb>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			gpio1_porta: gpio-controller@0 {
+				compatible = "snps,dw-apb-gpio-port";
+				gpio-controller;
+				#gpio-cells = <2>;
+				snps,nr-gpios = <32>;
+				reg = <0>;
+			};
+		};
+
+		pwm: pwm@ffec01c000 {
+			compatible = "thead,pwm-light";
+			reg = <0xff 0xec01c000 0x0 0x4000>;
+			#pwm-cells = <2>;
+		};
+
+		dsi_regs: dsi-controller@ffef500000 {
+			compatible = "thead,light-dsi-regs", "syscon";
+			reg = <0xff 0xef500000 0x0 0x10000>;
+			status = "okay";
+		};
+
+		vosys_regs: vosys@ffef528000 {
+			compatible = "thead,light-vo-subsys", "syscon";
+			reg = <0xff 0xef528000 0x0 0x1000>;
+			status = "okay";
+		};
+
+		dpu: dc8200@ffef600000 {
+			compatible = "verisilicon,dc8200";
+			reg = <0xff 0xef600000 0x0 0x100>;
+		};
+
+		axiscr {
+			compatible = "thead,axiscr";
+			reg = <0xff 0xff004000 0x0 0x1000>;
+			lock-read = "okay";
+			lock-write = "okay";
+			#address-cells = <2>;
+			#size-cells = <2>;
+			u-boot,dm-pre-reloc;
+			axiscr0: axisrc@0 {
+				device_type = "axiscr";
+				region = <0x00 0x00000000 0x00 0x80000000>; // 4KB align
+				status = "disabled";
+				#address-cells = <2>;
+				#size-cells = <2>;
+				u-boot,dm-pre-reloc;
+			};
+			axiscr1: axisrc@1 {
+				device_type = "axiscr";
+				region = <0x00 0x80000000 0x00 0x80000000>; // 4KB align
+				status = "disabled";
+				#address-cells = <2>;
+				#size-cells = <2>;
+				u-boot,dm-pre-reloc;
+			};
+			axiscr2: axisrc@2 {
+				device_type = "axiscr";
+				region = <0x01 0x00000000 0x00 0x80000000>; // 4KB align
+				status = "disabled";
+				#address-cells = <2>;
+				#size-cells = <2>;
+				u-boot,dm-pre-reloc;
+			};
+		};
+
+		axiparity {
+			compatible = "thead,axiparity";
+			reg = <0xff 0xff00c000 0x0 0x1000>;
+			lock = "okay";
+			#address-cells = <2>;
+			#size-cells = <2>;
+			u-boot,dm-pre-reloc;
+			axiparity0: axiparity@0 {
+				device_type = "axiparity";
+				region = <0x00 0x00000000 0x01 0x0000000>; // 4KB align
+				status = "disabled";
+				#address-cells = <2>;
+				#size-cells = <2>;
+				u-boot,dm-pre-reloc;
+			};
+			axiparity1: axiparity@1 {
+				device_type = "axiparity";
+				region = <0x01 0x00000000 0x01 0x00000000>; // 4KB align
+				status = "disabled";
+				#address-cells = <2>;
+				#size-cells = <2>;
+				u-boot,dm-pre-reloc;
+			};
+		};
+
+		dsi_bridge: dsi-bridge {
+			compatible = "thead,light-dsi-bridge";
+			clocks = <&dummy_dpu_pixclk>;
+			clock-names = "pix-clk";
+			phys = <&dsi_dphy>;
+			phy-names = "dphy";
+		};
+
+		dsi_host: dsi-host {
+			compatible = "synopsys,dw-mipi-dsi";
+			regmap = <&dsi_regs>;
+			status = "okay";
+		};
+
+		dsi_dphy: dsi-dphy {
+			compatible = "synopsys,dw-dphy";
+			regmap = <&dsi_regs>;
+			vosys-regmap = <&vosys_regs>;
+			clocks = <&dummy_dpu_pixclk>, <&dummy_dphy_refclk>;
+			clock-names = "pix-clk", "ref-clk";
+			#phy-cells = <0>;
+			status = "okay";
+		};
+
+		lcd_backlight: pwm-backlight {
+			compatible = "pwm-backlight";
+			pwms = <&pwm 0 5000000>;
+			brightness-levels = <0 4 8 16 32 64 128 255>;
+			default-brightness-level = <7>;
+		};
+
+		ili9881c_panel {
+			compatible      = "ilitek,ili9881c";
+			backlight       = <&lcd_backlight>;
+			reset-gpios     = <&gpio1_porta 5 1>;   /* active low  */
+			lcd-en-gpios    = <&pcal6408ahk_a 2 0>; /* active high */
+			lcd-bias-en-gpios = <&pcal6408ahk_a 4 0>;/* active high */
+		};
+	};
+
+	chosen {
+		bootargs = "console=ttyS0,115200";
+		stdout-path = "/soc/serial@ffe7014000:115200";
+	};
+};

arch/riscv/include/asm/dma-mapping.h

@@ -10,6 +10,7 @@
 #define __ASM_RISCV_DMA_MAPPING_H
 
 #include <linux/dma-direction.h>
+#include "common.h"
 
 #define dma_mapping_error(x, y)	0
 

arch/riscv/lib/reset.c

@@ -5,9 +5,21 @@
 
 #include <common.h>
 #include <command.h>
+#include <asm/io.h>
+
+#define AONSYS_RSTGEN_BASE			((void __iomem *)0xFFFFF44000UL)
+#define REG_RST_REQ_EN_0			(AONSYS_RSTGEN_BASE + 0x140)
+#define WDT0_SYS_RST_REQ			(1 << 8)
 
 static __attribute__((naked))void sys_wdt_reset(void)
 {
+    uint32_t data;
+
+	/* wdt0 reset enable */
+    data = readl(REG_RST_REQ_EN_0);
+	data |= WDT0_SYS_RST_REQ;
+	writel(data, REG_RST_REQ_EN_0);
+
     asm volatile (
     "1: \n\r"
         "li      a0, 0xFFEFC30000 \n\r"
@@ -21,7 +33,7 @@ static __attribute__((naked))void sys_wdt_reset(void)
 
 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
-	printf("resetting ...\n");
+    printf("resetting ...\n");
 
 	sys_wdt_reset();
 	hang();

board/thead/light-c910/Kconfig

@@ -34,19 +34,53 @@ config SYS_BOARD
 config SYS_CONFIG_NAME
     default "light-c910"
 
+config LIGHT_BOOT_FORCE_SEQ
+	bool "light boot force sequence"
+	default n
+
 config LIGHT_SEC_UPGRADE
     bool "light secure upgrade"
     default n
 
+config LIGHT_ANDROID_BOOT_IMAGE_VAL_A
+    bool "light board-a android image"
+    default n
+
+config AVB_USE_OEM_KEY
+    bool "AVB signature with OEM key"
+    default n
+
+config AVB_ROLLBACK_ENABLE
+    bool "AVB rollback index in RPMB"
+    default n
+
+config AVB_HW_ENGINE_ENABLE
+    bool "AVB Hardware cryptographic engine enable"
+    default n
+
+config LIGHT_ANDROID_BOOT_IMAGE_VAL_B
+    bool "light board-b android image"
+    default n
+
+config LIGHT_ANDROID_BOOT_IMAGE_VAL_LPI4A
+    bool "light board-lpi4a android image"
+    default n
+
 config LIGHT_SEC_BOOT_WITH_VERIFY_VAL_A
     bool "light board-a security boot with verification"
     default n
 
 config LIGHT_SEC_BOOT_WITH_VERIFY_VAL_B
-	bool "light board-b security boot with verification"
+    bool "light board-b security boot with verification"
+    default n
 
 config LIGHT_SEC_BOOT_WITH_VERIFY_ANT_REF
-	bool "light ant ref security boot with verification"
+    bool "light ant ref security boot with verification"
+    default n
+
+config LIGHT_SEC_BOOT_WITH_VERIFY_LPI4A
+    bool "light lpi4a security boot with verification"
+    default n
 
 config TARGET_LIGHT_FPGA_FM_C910
     bool "light fullmask FPGA board"
@@ -84,6 +118,10 @@ config TARGET_LIGHT_FM_C910_BEAGLE
     bool "light fullmask for beagle board "
     default n
 
+config TARGET_LIGHT_FM_C910_LPI4A
+    bool "light fullmask for Lichee Pi 4A board "
+    default n
+
 config TARGET_LIGHT_FM_C910_B_POWER
     bool "light fullmask for light-b-power board "
     default n
@@ -94,8 +132,8 @@ config SYS_TEXT_BASE
 
 config SPL_TEXT_BASE
     hex
-    default 0xffe0000800 if LIGHT_SEC_BOOT_WITH_VERIFY_VAL_A || LIGHT_SEC_BOOT_WITH_VERIFY_VAL_B || LIGHT_SEC_BOOT_WITH_VERIFY_ANT_REF
-    default 0xffe0000000 if !(LIGHT_SEC_BOOT_WITH_VERIFY_VAL_A || LIGHT_SEC_BOOT_WITH_VERIFY_VAL_B || LIGHT_SEC_BOOT_WITH_VERIFY_ANT_REF)
+    default 0xffe0000800 if LIGHT_SEC_BOOT_WITH_VERIFY_VAL_A || LIGHT_SEC_BOOT_WITH_VERIFY_VAL_B || LIGHT_SEC_BOOT_WITH_VERIFY_ANT_REF || LIGHT_SEC_BOOT_WITH_VERIFY_LPI4A
+    default 0xffe0000000 if !(LIGHT_SEC_BOOT_WITH_VERIFY_VAL_A || LIGHT_SEC_BOOT_WITH_VERIFY_VAL_B || LIGHT_SEC_BOOT_WITH_VERIFY_ANT_REF || LIGHT_SEC_BOOT_WITH_VERIFY_LPI4A)
 
 config SPL_MAX_SIZE
     hex

board/thead/light-c910/Makefile

@@ -68,4 +68,5 @@ endif
 obj-y += light-sv/pll_io_test.o
 obj-y += light-sv/adc_test.o
 obj-y += version_rollback.o
+obj-$(CONFIG_AVB_VERIFY) += secimg_load.o
 endif

board/thead/light-c910/board.c

@@ -12,7 +12,7 @@
 
 #ifdef CONFIG_USB_DWC3
 static struct dwc3_device dwc3_device_data = {
-	.maximum_speed = USB_SPEED_HIGH,
+	.maximum_speed = USB_SPEED_SUPER,
 	.dr_mode = USB_DR_MODE_PERIPHERAL,
 	.index = 0,
 };
@@ -50,9 +50,9 @@ int g_dnl_board_usb_cable_connected(void)
 
 #define C906_RST_ADDR_L		0xfffff48048
 #define C906_RST_ADDR_H		0xfffff4804C
-#define C906_START_ADDRESS_L	0xc0000000
-#define C906_START_ADDRESS_H	0xff
-#define C910_C906_START_ADDRESS	0xffc0000000
+#define C906_START_ADDRESS_L	0x32000000
+#define C906_START_ADDRESS_H	0x00
+#define C910_C906_START_ADDRESS	0x0032000000
 #define C906_CPR_IPCG_ADDRESS   0xFFCB000010
 #define C906_IOCTL_GPIO_SEL_ADDRESS     0xFFCB01D000
 #define C906_IOCTL_AF_SELH_ADDRESS      0xFFCB01D008

board/thead/light-c910/boot.c

@@ -7,24 +7,29 @@
 #include <dm.h>
 #include <fdt_support.h>
 #include <fdtdec.h>
+#include <mmc.h>
 #include <opensbi.h>
 #include <asm/csr.h>
 #include <asm/arch-thead/boot_mode.h>
 #include "../../../lib/sec_library/include/csi_efuse_api.h"
-
-
+#include "../../../lib/sec_library/include/sec_crypto_sha.h"
+#include "../../../lib/sec_library/include/kdf.h"
+#include "../../../lib/sec_library/include/sec_crypto_mac.h"
 
 #if CONFIG_IS_ENABLED(LIGHT_SEC_UPGRADE)
 
-/* The micro is used to enable NON-COT boot with non-signed image */
+/* The macro is used to enable NON-COT boot with non-signed image */
 #define LIGHT_NON_COT_BOOT	1
 
-/* The micro is used to enable uboot version in efuse */
+/* The macro is used to enable uboot version in efuse */
 #define	LIGHT_UBOOT_VERSION_IN_ENV	1
 
-/* The micro is used to enble RPMB ACCESS KEY from KDF */
+/* The macro is used to enble RPMB ACCESS KEY from KDF */
 //#define LIGHT_KDF_RPMB_KEY	1
 
+/* The macro is used to enable secure image version check in boot */
+//#define LIGHT_IMG_VERSION_CHECK_IN_BOOT	1
+
 /* the sample rpmb key is only used for testing */
 #ifndef LIGHT_KDF_RPMB_KEY 
 static const unsigned char emmc_rpmb_key_sample[32] = {0x33, 0x22, 0x11, 0x00, 0x77, 0x66, 0x55, 0x44, \
@@ -34,18 +39,88 @@ static const unsigned char emmc_rpmb_key_sample[32] = {0x33, 0x22, 0x11, 0x00, 0
 #endif
 static unsigned int upgrade_image_version = 0;
 
+#define RPMB_EMMC_CID_SIZE 16
+#define RPMB_CID_PRV_OFFSET             9
+#define RPMB_CID_CRC_OFFSET             15
+#ifdef LIGHT_KDF_RPMB_KEY
+static int tee_rpmb_key_gen(uint8_t* key, uint32_t * length)
+{
+	uint32_t data[RPMB_EMMC_CID_SIZE / 4];
+    uint8_t huk[32];
+    uint32_t huk_len;
+	struct mmc *mmc = find_mmc_device(0);
+	int i;
+	sc_mac_t mac_handle;
+	int ret = 0;
+
+	if (!mmc)
+		return -1;
+
+	if (!mmc->ext_csd)
+		return -1;
+
+	for (i = 0; i < ARRAY_SIZE(mmc->cid); i++)
+		data[i] = cpu_to_be32(mmc->cid[i]);
+	/*
+	 * PRV/CRC would be changed when doing eMMC FFU
+	 * The following fields should be masked off when deriving RPMB key
+	 *
+	 * CID [55: 48]: PRV (Product revision)
+	 * CID [07: 01]: CRC (CRC7 checksum)
+	 * CID [00]: not used
+	 */
+	memset((void *)((uint64_t)data + RPMB_CID_PRV_OFFSET), 0, 1);
+	memset((void *)((uint64_t)data + RPMB_CID_CRC_OFFSET), 0, 1);
+
+    /* Step1: Derive HUK from KDF function */
+	ret = csi_kdf_gen_hmac_key(huk, &huk_len);
+	if (ret) {
+		printf("kdf gen hmac key faild[%d]\r\n", ret);
+		return -1;
+	}
+
+    /* Step2: Using HUK and data to generate RPMB key */
+	ret = sc_mac_init(&mac_handle, 0);
+	if (ret) {
+		printf("mac init faild[%d]\r\n", ret);
+		ret = -1;
+		return -1;
+	}
+
+	/* LSB 16 bytes are used as key */
+	ret = sc_mac_set_key(&mac_handle, huk, 16);
+	if (ret) {
+		printf("mac set key faild[%d]\r\n", ret);
+		ret = -1;
+		goto func_exit;
+	}
+
+	ret = sc_mac_calc(&mac_handle, SC_SHA_MODE_256, (uint8_t *)&data, sizeof(data), key, length);
+	if (ret) {
+		printf("mac calc faild[%d]\r\n", ret);
+		ret = -1;
+		goto func_exit;
+	}
+
+func_exit:
+	sc_mac_uninit(&mac_handle);
+
+	return ret;
+
+}
+#endif
+
 int csi_rpmb_write_access_key(void) 
 {
+#ifdef LIGHT_KDF_RPMB_KEY
     unsigned long *temp_rpmb_key_addr = NULL;
     char runcmd[64] = {0};
     uint8_t blkdata[256] = {0};
-    uint8_t kdf_rpmb_key[32];
-	uint32_t kdf_rpmb_key_length = 0;
+    __attribute__((__aligned__(8))) uint8_t kdf_rpmb_key[32];
+    uint32_t kdf_rpmb_key_length = 0;
 	int ret = 0;
-
-#ifdef LIGHT_KDF_RPMB_KEY
     /* Step1: retrive RPMB key from KDF function */
-	ret = csi_kdf_gen_hmac_key(kdf_rpmb_key, &kdf_rpmb_key_length);
+	ret = tee_rpmb_key_gen(kdf_rpmb_key, &kdf_rpmb_key_length);
 	if (ret != 0) {
 		return -1;
 	}
@@ -79,13 +154,16 @@ int csi_tf_get_image_version(unsigned int *ver)
 {
 	char runcmd[64] = {0};
 	unsigned char blkdata[256];
+	int ret = 0;
 
 	/* tf version reside in RPMB block#0, offset#16*/
 	sprintf(runcmd, "mmc rpmb read 0x%lx 0 1", (unsigned long)blkdata);
-	run_command(runcmd, 0);
-	*ver = (blkdata[16] << 8) + blkdata[17];
-
-	return 0;
+	ret = run_command(runcmd, 0);
+	if (ret == 0) {
+		*ver = (blkdata[16] << 8) + blkdata[17];
+	}
+	
+	return ret;
 }
 
 int csi_tf_set_image_version(unsigned int ver)
@@ -129,13 +207,16 @@ int csi_tee_get_image_version(unsigned int *ver)
 {
 	char runcmd[64] = {0};
 	unsigned char blkdata[256];
+	int ret = 0;
 
 	/* tf version reside in RPMB block#0, offset#0*/
 	sprintf(runcmd, "mmc rpmb read 0x%lx 0 1", (unsigned long)blkdata);
-	run_command(runcmd, 0);
-	*ver = (blkdata[0] << 8) + blkdata[1];
+	ret = run_command(runcmd, 0);
+	if (ret == 0) {
+		*ver = (blkdata[0] << 8) + blkdata[1];
+	}
 
-	return 0;
+	return ret;
 }
 
 int csi_kernel_get_image_version(unsigned int *ver)
@@ -214,7 +295,7 @@ int csi_uboot_get_image_version(unsigned int *ver)
 	unsigned int ver_x = 0;
 	int ret = 0;
 
-	ret = csi_efuse_api_int();
+	ret = csi_efuse_api_init();
 	if (ret) {
 		printf("efuse api init fail \n");
 		return -1;
@@ -240,7 +321,6 @@ int csi_uboot_set_image_version(unsigned int ver)
 	//TODO
 	unsigned long long uboot_ver = 0;
 	unsigned char ver_x = (ver & 0xff00) >> 8;
-    char ver_str[32] = {0};
 
 	uboot_ver = env_get_hex("uboot_version", 0xffffffffffffffff);
 
@@ -263,7 +343,7 @@ int csi_uboot_set_image_version(unsigned int ver)
 		return 0;
 	}
 
-	ret = csi_efuse_api_int();
+	ret = csi_efuse_api_init();
 	if (ret) {
 		printf("efuse api init fail \n");
 		return -1;
@@ -320,6 +400,82 @@ int verify_image_version_rule(unsigned int new_ver, unsigned int cur_ver)
 	return 0;
 }
 
+int check_image_version_rule(unsigned int new_ver, unsigned int cur_ver)
+{
+	unsigned char new_ver_x = 0, new_ver_y = 0;
+	unsigned char cur_ver_x = 0, cur_ver_y = 0;
+
+	/* Get secure version X from image version X.Y */
+	new_ver_x = (new_ver & 0xFF00) >> 8;
+	new_ver_y = new_ver & 0xFF;
+	cur_ver_x = (cur_ver & 0xFF00) >> 8;
+	cur_ver_y = cur_ver & 0xFF;
+
+    (void)new_ver_y;
+    (void)cur_ver_y;
+
+	/* Ensure image version must be less than expected version */
+	if (new_ver_x < cur_ver_x) {
+		return -1;
+	}
+
+	return 0;
+}
+
+int check_tf_version_in_boot(unsigned long tf_addr)
+{
+	int ret = 0;
+	unsigned int img_version = 0;
+	unsigned int expected_img_version = 0;
+	
+	img_version = get_image_version(tf_addr);
+	if (img_version == 0) {
+		printf("get tf image version fail\n");
+		return -1;
+	}
+
+	ret = csi_tf_get_image_version(&expected_img_version);
+	if (ret != 0) {
+		printf("Get tf expected img version fail\n");
+		return -1;
+	}
+
+	ret = check_image_version_rule(img_version, expected_img_version);
+	if (ret != 0) {
+		printf("Image version breaks the rule\n");
+		return -1;
+	}
+
+	return 0;
+}
+
+int check_tee_version_in_boot(unsigned long tee_addr)
+{
+	int ret = 0;
+	unsigned int img_version = 0;
+	unsigned int expected_img_version = 0;
+	
+	img_version = get_image_version(tee_addr);
+	if (img_version == 0) {
+		printf("get tee image version fail\n");
+		return -1;
+	}
+
+	ret = csi_tee_get_image_version(&expected_img_version);
+	if (ret != 0) {
+		printf("Get tee expected img version fail\n");
+		return -1;
+	}
+
+	ret = check_image_version_rule(img_version, expected_img_version);
+	if (ret != 0) {
+		printf("Image version breaks the rule\n");
+		return -1;
+	}
+
+	return 0;
+}
+
 int light_vimage(int argc, char *const argv[])
 {
 	int ret = 0;
@@ -435,10 +591,8 @@ int light_secboot(int argc, char * const argv[])
 	int ret = 0;
 	unsigned long tf_addr = LIGHT_TF_FW_ADDR;
 	unsigned long tee_addr = LIGHT_TEE_FW_ADDR;
-    unsigned long kernel_addr = LIGHT_KERNEL_ADDR;
 	unsigned int tf_image_size = 0;
 	unsigned int tee_image_size = 0;
-	unsigned int kernel_image_size = 0;
 
 	printf("\n\n");
 	printf("Now, we start to verify all trust firmware before boot kernel !\n");
@@ -454,6 +608,13 @@ int light_secboot(int argc, char * const argv[])
 
 	/* Step1. Check and verify TF image */
 	if (image_have_head(LIGHT_TF_FW_TMP_ADDR) == 1) {
+#ifdef LIGHT_IMG_VERSION_CHECK_IN_BOOT
+		printf("check TF version in boot \n");
+		ret = check_tf_version_in_boot(LIGHT_TF_FW_TMP_ADDR);
+		if (ret != 0) {
+			return CMD_RET_FAILURE;
+		}
+#endif
 
 		printf("Process TF image verification ...\n");
 		ret = verify_customer_image(T_TF, LIGHT_TF_FW_TMP_ADDR);
@@ -479,6 +640,14 @@ int light_secboot(int argc, char * const argv[])
 
 	/* Step2. Check and verify TEE image */
 	if (image_have_head(tee_addr) == 1) {
+#ifdef LIGHT_IMG_VERSION_CHECK_IN_BOOT
+		printf("check TEE version in boot \n");
+		ret = check_tee_version_in_boot(tee_addr);
+		if (ret != 0) {
+			return CMD_RET_FAILURE;
+		}
+#endif
+
 		printf("Process TEE image verification ...\n");
 		ret = verify_customer_image(T_TEE, tee_addr);
 		if (ret != 0) {
@@ -529,10 +698,22 @@ void sec_firmware_version_dump(void)
 	unsigned int tf_ver = 0;
 	unsigned int tee_ver = 0;
 	unsigned int uboot_ver = 0;
+	unsigned int tf_ver_env = 0;
+	unsigned int tee_ver_env = 0;
 
 	csi_uboot_get_image_version(&uboot_ver);
 	csi_tf_get_image_version(&tf_ver);
 	csi_tee_get_image_version(&tee_ver);
+	/* Keep sync with version in RPMB, the Following version could be leveraged by OTA client */
+	tee_ver_env = env_get_hex("tee_version", 0);
+	tf_ver_env = env_get_hex("tf_version", 0);
+	if ((tee_ver_env != tee_ver) && (tee_ver != 0)) {
+		env_set_hex("tee_version", tee_ver);
+	}
+
+	if ((tf_ver_env != tf_ver) && (tf_ver != 0)) {
+		env_set_hex("tf_version", tf_ver);
+	}
 
 	printf("\n\n");
 	printf("Secure Firmware image version info: \n");
@@ -546,6 +727,8 @@ void sec_upgrade_thread(void)
 {
 	const unsigned long temp_addr=0x200000;
 	char runcmd[80];
+    uint8_t * image_buffer = NULL;
+    uint8_t * image_malloc_buffer = NULL;
 	int ret = 0;
 	unsigned int sec_upgrade_flag = 0;
 	unsigned int upgrade_file_size = 0;
@@ -570,6 +753,15 @@ void sec_upgrade_thread(void)
 		upgrade_file_size = env_get_hex("filesize", 0);
 		printf("upgrade file size: %d\n", upgrade_file_size);
 
+        /*store image to temp buffer as temp_addr may be decrypted*/
+        image_malloc_buffer = malloc(upgrade_file_size);
+        if ( image_malloc_buffer == NULL ) {
+			image_buffer = (uint8_t*)temp_addr + upgrade_file_size;
+		} else {
+            image_buffer = image_malloc_buffer;
+        }
+        memcpy(image_buffer, (void*)temp_addr, upgrade_file_size);
+
 		/* STEP 2: verify its authentiticy here */
 		sprintf(runcmd, "vimage 0x%p tf", (void *)temp_addr);
 		printf("runcmd:%s\n", runcmd);
@@ -581,7 +773,7 @@ void sec_upgrade_thread(void)
 
 		/* STEP 3: update tf partition */
 		printf("read upgrade image (trust_firmware.bin) into tf partition \n");
-		sprintf(runcmd, "ext4write mmc 0:3 0x%p /trust_firmware.bin 0x%x", (void *)temp_addr, upgrade_file_size);
+		sprintf(runcmd, "ext4write mmc 0:3 0x%p /trust_firmware.bin 0x%x", (void *)image_buffer, upgrade_file_size);
 		printf("runcmd:%s\n", runcmd);
 		ret = run_command(runcmd, 0);
 		if (ret != 0) {
@@ -603,6 +795,10 @@ _upgrade_tf_exit:
 		run_command("saveenv", 0);
 		run_command("reset", 0);
 
+        if ( image_malloc_buffer != NULL ) {
+            free(image_malloc_buffer);
+            image_malloc_buffer = NULL;
+        }
 	} else if (sec_upgrade_flag == TEE_SEC_UPGRADE_FLAG) {
 
  		/* STEP 1: read upgrade image (tee.bin) from stash partition */
@@ -617,6 +813,15 @@ _upgrade_tf_exit:
 		/* Fetch the total file size after read out operation end */
 		upgrade_file_size = env_get_hex("filesize", 0);
 		printf("TEE upgrade file size: %d\n", upgrade_file_size);
+        
+        /*store image to temp buffer as temp_addr may be decrypted*/
+        image_malloc_buffer = malloc(upgrade_file_size);
+        if ( image_malloc_buffer == NULL ) {
+			image_buffer = (uint8_t*)temp_addr + upgrade_file_size;
+		} else {
+            image_buffer = image_malloc_buffer;
+        }
+        memcpy(image_buffer, (void*)temp_addr, upgrade_file_size);
 
 		/* STEP 2: verify its authentiticy here */
 		sprintf(runcmd, "vimage 0x%p tee", (void *)temp_addr);
@@ -629,7 +834,7 @@ _upgrade_tf_exit:
 
 		/* STEP 3: update tee partition */
 		printf("read upgrade image (tee.bin) into tf partition \n");
-		sprintf(runcmd, "ext4write mmc 0:4 0x%p /tee.bin 0x%x", (void *)temp_addr, upgrade_file_size);
+		sprintf(runcmd, "ext4write mmc 0:4 0x%p /tee.bin 0x%x", (void *)image_buffer, upgrade_file_size);
 		printf("runcmd:%s\n", runcmd);
 		ret = run_command(runcmd, 0);
 		if (ret != 0) {
@@ -650,7 +855,11 @@ _upgrade_tee_exit:
 		run_command("env set sec_upgrade_mode 0", 0);
 		run_command("saveenv", 0);
 		run_command("reset", 0);
-
+        
+        if ( image_malloc_buffer != NULL ) {
+            free(image_malloc_buffer);
+            image_malloc_buffer = NULL;
+        }
 	} else if (sec_upgrade_flag == UBOOT_SEC_UPGRADE_FLAG) { 
 		unsigned int block_cnt;
 		struct blk_desc *dev_desc;

board/thead/light-c910/clock_config.c

@@ -1146,6 +1146,7 @@ void ap_mipi_dsi1_clk_endisable(bool en)
 	writel(cfg1, (void __iomem *)AP_DPU1_PLL_CFG1);
 }
 
+#if defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_DISCRETE) || defined (CONFIG_TARGET_LIGHT_FM_C910_BEAGLE) || defined (CONFIG_TARGET_LIGHT_FM_C910_B_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_B_POWER) || defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_B) || defined (CONFIG_TARGET_LIGHT_FM_C910_LPI4A)
 static void ap_multimedia_div_num_set(enum multimedia_div_type type, unsigned int div_num)
 {
 	unsigned long div_reg;
@@ -1209,6 +1210,7 @@ static void ap_multimedia_div_num_set(enum multimedia_div_type type, unsigned in
 	div_cfg |= div_en;
 	writel(div_cfg, (void __iomem *)div_reg);
 }
+#endif
 
 int clk_config(void)
 {
@@ -1302,7 +1304,7 @@ int clk_config(void)
 
 	/* The boards other than the LightA board perform the bus down-speed operation */
 
-#if defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_DISCRETE) || defined (CONFIG_TARGET_LIGHT_FM_C910_BEAGLE) || defined (CONFIG_TARGET_LIGHT_FM_C910_B_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_B_POWER) || defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_B)
+#if defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_DISCRETE) || defined (CONFIG_TARGET_LIGHT_FM_C910_BEAGLE) || defined (CONFIG_TARGET_LIGHT_FM_C910_B_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_B_POWER) || defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_B) || defined (CONFIG_TARGET_LIGHT_FM_C910_LPI4A)
 	ap_multimedia_div_num_set(VI_MIPI_CSI0_DIV, 12); /* Input frquency: 2376MHZ */
 	ap_multimedia_div_num_set(VI_ISP0_CORE_DIV, 15); /* Input frquency: 2376MHZ */
 	ap_multimedia_div_num_set(VI_ISP1_CORE_DIV, 12); /* Input frquency: 2376MHZ */

board/thead/light-c910/light.c

@@ -555,12 +555,14 @@ static void gmac_phy_rst(void)
 	       (void *)LIGHT_GPIO3_BADDR);
 	writel(readl((void *)LIGHT_GPIO1_BADDR) & ~LIGHT_GPIO1_13,
 	       (void *)LIGHT_GPIO1_BADDR);
+	wmb();
 	/* At least 10ms */
-	mdelay(12);
+	mdelay(50);
 	writel(readl((void *)LIGHT_GPIO3_BADDR) | LIGHT_GPIO3_21,
 	       (void *)LIGHT_GPIO3_BADDR);
 	writel(readl((void *)LIGHT_GPIO1_BADDR) | LIGHT_GPIO1_13,
 	       (void *)LIGHT_GPIO1_BADDR);
+	wmb();
 }
 
 static void gmac_glue_init(uint64_t apb3s_baddr)
@@ -910,14 +912,14 @@ static void light_iopin_init(void)
 	light_pin_cfg(GPIO1_2,PIN_SPEED_NORMAL,PIN_PN,2);
 	light_pin_cfg(GPIO1_3,PIN_SPEED_NORMAL,PIN_PN,2);
 	light_pin_cfg(GPIO1_4,PIN_SPEED_NORMAL,PIN_PN,2);
-#ifndef defined (CONFIG_TARGET_LIGHT_FM_C910_B_POWER)
+#if ! defined (CONFIG_TARGET_LIGHT_FM_C910_B_POWER)
 	light_pin_cfg(GPIO1_9,PIN_SPEED_NORMAL,PIN_PN,2); //soc_vdd18_lcd0_en_reg --backup regulator
 #else
 	light_pin_cfg(GPIO1_9,PIN_SPEED_NORMAL,PIN_PU,2); //soc_vdd18_lcd0_en_reg
 #endif
 	light_pin_cfg(GPIO1_10,PIN_SPEED_NORMAL,PIN_PN,2);//soc_lcd0_bias_en_reg
 	light_pin_cfg(GPIO1_11,PIN_SPEED_NORMAL,PIN_PN,2);
-#ifndef defined (CONFIG_TARGET_LIGHT_FM_C910_B_POWER)
+#if ! defined (CONFIG_TARGET_LIGHT_FM_C910_B_POWER)
 	light_pin_cfg(GPIO1_12,PIN_SPEED_NORMAL,PIN_PN,2);//reg_tp_pwr_en --touch pannel
 #else
 	light_pin_cfg(GPIO1_12,PIN_SPEED_NORMAL,PIN_PU,2);//reg_tp_pwr_en --touch pannel
@@ -1406,6 +1408,280 @@ static void light_iopin_init(void)
 	light_pin_cfg(GMAC0_RXD2, PIN_SPEED_NORMAL, PIN_PN, 0xF);
 	light_pin_cfg(GMAC0_RXD3, PIN_SPEED_NORMAL, PIN_PN, 0xF);
 }
+#elif defined (CONFIG_TARGET_LIGHT_FM_C910_LPI4A)
+static void light_iopin_init(void)
+{
+	/* aon-padmux config */
+	light_pin_cfg(I2C_AON_SCL, PIN_SPEED_NORMAL, PIN_PN, 8);
+	light_pin_cfg(I2C_AON_SDA, PIN_SPEED_NORMAL, PIN_PN, 8);
+
+	light_pin_mux(CPU_JTG_TCLK, 3);
+	light_pin_cfg(CPU_JTG_TCLK, PIN_SPEED_NORMAL, PIN_PN, 2);
+	light_pin_mux(CPU_JTG_TMS, 3);
+	light_pin_cfg(CPU_JTG_TMS, PIN_SPEED_NORMAL, PIN_PN, 2);
+	light_pin_mux(CPU_JTG_TDI, 3);
+	light_pin_cfg(CPU_JTG_TDI, PIN_SPEED_NORMAL, PIN_PN, 2);
+
+	light_pin_mux(AOGPIO_7, 1);
+	light_pin_mux(AOGPIO_8, 1);
+	// light_pin_mux(AOGPIO_9, 0);
+	light_pin_mux(AOGPIO_10, 1);
+	light_pin_mux(AOGPIO_11, 1);
+	light_pin_mux(AOGPIO_12, 1);
+	light_pin_mux(AOGPIO_13, 1);
+	light_pin_mux(AOGPIO_14, 0);
+	// light_pin_mux(AOGPIO_15,0);
+	light_pin_cfg(AOGPIO_7, PIN_SPEED_NORMAL, PIN_PN, 2);     ///NC
+	light_pin_cfg(AOGPIO_8, PIN_SPEED_NORMAL, PIN_PN, 2);     ///NC
+	// light_pin_cfg(AOGPIO_9,PIN_SPEED_NORMAL,PIN_PN,2);
+	light_pin_cfg(AOGPIO_10, PIN_SPEED_NORMAL, PIN_PN, 2);
+	light_pin_cfg(AOGPIO_11, PIN_SPEED_NORMAL, PIN_PN, 2);
+	light_pin_cfg(AOGPIO_12, PIN_SPEED_NORMAL, PIN_PN, 2);
+	light_pin_cfg(AOGPIO_13, PIN_SPEED_NORMAL, PIN_PN, 2);
+	light_pin_cfg(AOGPIO_14, PIN_SPEED_NORMAL, PIN_PN, 2);
+	// light_pin_cfg(AOGPIO_15,PIN_SPEED_NORMAL,PIN_PN,2);
+
+	light_pin_mux(AUDIO_PA0, 0);
+	light_pin_cfg(AUDIO_PA0, PIN_SPEED_NORMAL, PIN_PN, 2);
+	light_pin_mux(AUDIO_PA1, 0);
+	light_pin_cfg(AUDIO_PA1, PIN_SPEED_NORMAL, PIN_PN, 2);
+	light_pin_mux(AUDIO_PA3, 0);
+	light_pin_cfg(AUDIO_PA3, PIN_SPEED_NORMAL, PIN_PN, 2);
+	light_pin_mux(AUDIO_PA4, 0);
+	light_pin_cfg(AUDIO_PA4, PIN_SPEED_NORMAL, PIN_PN, 2);
+	light_pin_mux(AUDIO_PA5, 0);
+	light_pin_cfg(AUDIO_PA5, PIN_SPEED_NORMAL, PIN_PN, 2);
+	light_pin_mux(AUDIO_PA6, 0);
+	light_pin_cfg(AUDIO_PA6, PIN_SPEED_NORMAL, PIN_PN, 2);
+	light_pin_mux(AUDIO_PA7, 0);
+	light_pin_cfg(AUDIO_PA7, PIN_SPEED_NORMAL, PIN_PN, 2);
+	light_pin_mux(AUDIO_PA14, 0);
+	light_pin_cfg(AUDIO_PA14, PIN_SPEED_NORMAL, PIN_PN, 2);
+	light_pin_mux(AUDIO_PA15, 0);
+	light_pin_cfg(AUDIO_PA15, PIN_SPEED_NORMAL, PIN_PN, 2);
+	light_pin_mux(AUDIO_PA16, 0);
+	light_pin_cfg(AUDIO_PA16, PIN_SPEED_NORMAL, PIN_PN, 2);
+	light_pin_mux(AUDIO_PA17, 0);
+	light_pin_cfg(AUDIO_PA17, PIN_SPEED_NORMAL, PIN_PN, 2);
+	light_pin_mux(AUDIO_PA29, 0);
+	light_pin_cfg(AUDIO_PA29, PIN_SPEED_NORMAL, PIN_PN, 2);
+	light_pin_mux(AUDIO_PA30, 0);
+	light_pin_cfg(AUDIO_PA30, PIN_SPEED_NORMAL, PIN_PN, 2);
+
+	// light_pin_mux(AUDIO_PA9,3);                         ///AUDIO-PA-RESET
+	// light_pin_cfg(AUDIO_PA9,PIN_SPEED_NORMAL,PIN_PN,2);
+	// light_pin_mux(AUDIO_PA10,3);                        /// AUD-3V3-EN
+	// light_pin_cfg(AUDIO_PA10,PIN_SPEED_NORMAL,PIN_PU,2);
+	// light_pin_mux(AUDIO_PA12,3);                        /// AUD-1V8-EN
+	// light_pin_cfg(AUDIO_PA12,PIN_SPEED_NORMAL,PIN_PU,2);
+	// light_pin_mux(AUDIO_PA13,0);
+
+	/*ap-padmux on left/top */
+	light_pin_mux(QSPI1_SCLK, 4);
+	light_pin_cfg(QSPI1_SCLK, PIN_SPEED_NORMAL,PIN_PN, 8);  ///se-spi
+	light_pin_mux(QSPI1_CSN0, 4);
+	light_pin_cfg(QSPI1_CSN0, PIN_SPEED_NORMAL, PIN_PN, 8);  ///se-spi
+	light_pin_mux(QSPI1_D0_MOSI, 4);
+	light_pin_cfg(QSPI1_D0_MOSI, PIN_SPEED_NORMAL, PIN_PU, 8);  ///se-spi
+	light_pin_mux(QSPI1_D1_MISO, 4);
+	light_pin_cfg(QSPI1_D1_MISO, PIN_SPEED_NORMAL, PIN_PU, 8);  ///se-spi
+	light_pin_mux(QSPI1_D2_WP, 4);
+	light_pin_cfg(QSPI1_D2_WP, PIN_SPEED_NORMAL, PIN_PN, 8);    ///NC
+	// light_pin_mux(QSPI1_D3_HOLD, 4);
+	// light_pin_cfg(QSPI1_D3_HOLD, PIN_SPEED_NORMAL, PIN_PN, 8);  ///NC
+
+	light_pin_cfg(I2C0_SCL, PIN_SPEED_NORMAL, PIN_PN, 4);
+	light_pin_cfg(I2C0_SDA, PIN_SPEED_NORMAL, PIN_PN, 4);
+	light_pin_cfg(I2C1_SCL, PIN_SPEED_NORMAL, PIN_PN, 4);
+	light_pin_cfg(I2C1_SDA, PIN_SPEED_NORMAL, PIN_PN, 4);
+
+	light_pin_cfg(UART1_TXD, PIN_SPEED_NORMAL, PIN_PN, 2);
+	light_pin_cfg(UART1_RXD, PIN_SPEED_NORMAL, PIN_PN, 2);
+	light_pin_cfg(UART4_TXD, PIN_SPEED_NORMAL, PIN_PN, 2);
+	light_pin_cfg(UART4_RXD, PIN_SPEED_NORMAL, PIN_PN, 2);
+	light_pin_cfg(UART4_CTSN, PIN_SPEED_NORMAL, PIN_PN, 2);
+	light_pin_cfg(UART4_RTSN, PIN_SPEED_NORMAL, PIN_PN, 2);
+	light_pin_mux(UART3_TXD, 1);
+	light_pin_cfg(UART3_TXD, PIN_SPEED_NORMAL, PIN_PN, 2);
+	light_pin_mux(UART3_RXD, 1);
+	light_pin_cfg(UART3_RXD, PIN_SPEED_NORMAL, PIN_PN, 2);
+
+	// light_pin_mux(GPIO0_18,1);
+	// light_pin_mux(GPIO0_19,1);
+	// light_pin_cfg(GPIO0_18,PIN_SPEED_NORMAL,PIN_PN,4);
+	// light_pin_cfg(GPIO0_19,PIN_SPEED_NORMAL,PIN_PN,4);
+
+	// light_pin_mux(GPIO0_20,0);
+	// light_pin_mux(GPIO0_21,0);
+	// light_pin_mux(GPIO0_22,1);
+	// light_pin_mux(GPIO0_23,1);
+	// light_pin_mux(GPIO0_24,1);
+	// light_pin_mux(GPIO0_25,1);
+	// light_pin_mux(GPIO0_26,1);
+	// light_pin_mux(GPIO0_27,0);
+	// light_pin_mux(GPIO0_28,0);
+	// light_pin_mux(GPIO0_29,0);
+	// light_pin_mux(GPIO0_30,0);
+	// light_pin_cfg(GPIO0_20,PIN_SPEED_NORMAL,PIN_PN,2);
+	// light_pin_cfg(GPIO0_21,PIN_SPEED_NORMAL,PIN_PN,2);
+	light_pin_cfg(GPIO0_24, PIN_SPEED_NORMAL, PIN_PN, 2);
+	light_pin_cfg(GPIO0_25, PIN_SPEED_NORMAL, PIN_PN, 2);
+	light_pin_cfg(GPIO0_27, PIN_SPEED_NORMAL, PIN_PN, 2);                          ///< NC(not used)
+	light_pin_cfg(GPIO0_28, PIN_SPEED_NORMAL, PIN_PN, 2);                          ///< AVDD25_IR_EN
+	// light_pin_cfg(GPIO0_29,PIN_SPEED_NORMAL,PIN_PN,2);                          ///< DVDD12_IR_EN
+	light_pin_cfg(GPIO0_30, PIN_SPEED_NORMAL, PIN_PU, 2);                          ///< gmac,uart,led
+	light_pin_cfg(GPIO0_31, PIN_SPEED_NORMAL, PIN_PN, 2);
+
+	light_pin_mux(GPIO1_0, 0);
+	// light_pin_mux(GPIO1_1,1);
+	// light_pin_mux(GPIO1_2,1);
+	light_pin_mux(GPIO1_3, 0);
+	light_pin_mux(GPIO1_4, 0);
+	light_pin_mux(GPIO1_5, 0);
+	light_pin_mux(GPIO1_6, 0);
+	light_pin_mux(GPIO1_9, 0);
+	light_pin_mux(GPIO1_10, 0);
+	// light_pin_mux(GPIO1_11,0);
+	// light_pin_mux(GPIO1_12,0);
+	light_pin_mux(GPIO1_13, 0);
+	light_pin_mux(GPIO1_14, 0);
+	// light_pin_mux(GPIO1_15,0);
+	// light_pin_mux(GPIO1_16,0);
+	light_pin_cfg(GPIO1_0, PIN_SPEED_NORMAL, PIN_PN, 2);
+	// light_pin_cfg(GPIO1_1,PIN_SPEED_NORMAL,PIN_PN,2);
+	// light_pin_cfg(GPIO1_2,PIN_SPEED_NORMAL,PIN_PN,2);
+	light_pin_cfg(GPIO1_3, PIN_SPEED_NORMAL, PIN_PN, 2);
+	light_pin_cfg(GPIO1_4, PIN_SPEED_NORMAL, PIN_PN, 2);
+	light_pin_cfg(GPIO1_5, PIN_SPEED_NORMAL, PIN_PN, 2);
+	light_pin_cfg(GPIO1_6, PIN_SPEED_NORMAL, PIN_PN, 2);
+	light_pin_cfg(GPIO1_9, PIN_SPEED_NORMAL, PIN_PN, 2);                          ///<VDD18_LCD0_EN
+	light_pin_cfg(GPIO1_10, PIN_SPEED_NORMAL, PIN_PN, 2);                         ///<LCD0_BIAS_EN
+	// light_pin_cfg(GPIO1_11,PIN_SPEED_NORMAL,PIN_PN,2);
+	// light_pin_cfg(GPIO1_12,PIN_SPEED_NORMAL,PIN_PN,2);                         ///<TOUCH-PANNEL VDD28_TP0_EN
+	light_pin_cfg(GPIO1_13, PIN_SPEED_NORMAL, PIN_PN, 2);                         ///<DOVDD18_RGB_EN
+	light_pin_cfg(GPIO1_14, PIN_SPEED_NORMAL, PIN_PN, 2);                         ///<DVDD12_RGB_EN
+	// light_pin_cfg(GPIO1_15,PIN_SPEED_NORMAL,PIN_PN,2);                         ///<AVDD28_RGB_EN
+	// light_pin_cfg(GPIO1_16,PIN_SPEED_NORMAL,PIN_PN,2);
+
+	light_pin_mux(CLK_OUT_0, 1);
+	light_pin_cfg(CLK_OUT_0, PIN_SPEED_NORMAL, PIN_PU, 2);
+	light_pin_mux(CLK_OUT_1, 1);
+	light_pin_cfg(CLK_OUT_1, PIN_SPEED_NORMAL, PIN_PU, 2);
+	light_pin_mux(CLK_OUT_2, 0);
+	light_pin_cfg(CLK_OUT_2, PIN_SPEED_NORMAL, PIN_PU, 2);
+	light_pin_mux(CLK_OUT_3, 0);
+	light_pin_cfg(CLK_OUT_3, PIN_SPEED_NORMAL, PIN_PU, 2);    
+
+	// light_pin_mux(GPIO1_21,3);
+	light_pin_mux(GPIO1_22, 3);
+	// light_pin_mux(GPIO1_23,3);
+	light_pin_mux(GPIO1_24, 3);
+	// light_pin_mux(GPIO1_25,3);
+	// light_pin_mux(GPIO1_26,3);
+	// light_pin_mux(GPIO1_27,3);
+	light_pin_mux(GPIO1_28, 0);
+	// light_pin_mux(GPIO1_29,3);
+	light_pin_mux(GPIO1_30, 0);
+	// light_pin_cfg(GPIO1_21,PIN_SPEED_NORMAL,PIN_PN,2);
+	light_pin_cfg(GPIO1_22, PIN_SPEED_NORMAL, PIN_PN,2);
+	// light_pin_cfg(GPIO1_23,PIN_SPEED_NORMAL,PIN_PN,2);                         ///<LED_PDN
+	light_pin_cfg(GPIO1_24, PIN_SPEED_NORMAL, PIN_PN, 2);
+	light_pin_cfg(GPIO1_28, PIN_SPEED_NORMAL, PIN_PN, 2);
+	light_pin_cfg(GPIO1_30, PIN_SPEED_NORMAL, PIN_PN, 2);                         ///<DBB2LEDDRIVER_EN
+
+	light_pin_cfg(UART0_TXD, PIN_SPEED_NORMAL, PIN_PN, 2);
+	light_pin_cfg(UART0_RXD, PIN_SPEED_NORMAL, PIN_PN, 2);            
+
+	/*ap-pdmux on righ/top*/
+	// light_pin_mux(QSPI0_SCLK,3);            ///NC
+	// light_pin_mux(QSPI0_CSN0,3);            ///NC
+	// light_pin_mux(QSPI0_CSN1,3);            ///NC
+	// light_pin_mux(QSPI0_D0_MOSI,3);         ///NC
+	// light_pin_mux(QSPI0_D1_MISO,3);         ///NC
+	// light_pin_mux(QSPI0_D2_WP,3);           ///NC
+	// light_pin_mux(QSPI0_D3_HOLD,3);         ///NC
+
+	light_pin_cfg(I2C2_SCL, PIN_SPEED_NORMAL, PIN_PN, 4);
+	light_pin_cfg(I2C2_SDA, PIN_SPEED_NORMAL, PIN_PN, 4);
+	light_pin_cfg(I2C3_SCL, PIN_SPEED_NORMAL, PIN_PN, 4);
+	light_pin_cfg(I2C3_SDA, PIN_SPEED_NORMAL, PIN_PN, 4);
+
+	// light_pin_mux(SPI_CSN,3);                                                /// W_DISABLE_CATE1
+	// light_pin_mux(SPI_MOSI,3);                                               /// NC
+	// light_pin_mux(SPI_MISO,3);                                               /// RERST1_N_CAT1
+	// light_pin_mux(SPI_SCLK,3);
+	light_pin_cfg(SPI_CSN, PIN_SPEED_NORMAL, PIN_PN, 2);
+	light_pin_cfg(SPI_MOSI, PIN_SPEED_NORMAL, PIN_PN, 2);
+	light_pin_cfg(SPI_MISO, PIN_SPEED_NORMAL, PIN_PN, 2);
+	light_pin_cfg(SPI_SCLK, PIN_SPEED_NORMAL, PIN_PN, 2);
+
+	light_pin_mux(GPIO2_13, 0);
+	light_pin_mux(GPIO2_18, 1);
+	light_pin_mux(GPIO2_19, 1);
+	light_pin_mux(GPIO2_20, 1);
+	light_pin_mux(GPIO2_21, 1);
+	light_pin_mux(GPIO2_22, 1);
+	light_pin_mux(GPIO2_23, 1);
+	light_pin_mux(GPIO2_24, 1);
+	light_pin_mux(GPIO2_25, 1);
+
+	light_pin_cfg(GPIO2_13, PIN_SPEED_NORMAL, PIN_PN, 2);
+	light_pin_cfg(GPIO2_18, PIN_SPEED_NORMAL, PIN_PN, 0xF);
+	light_pin_cfg(GPIO2_19, PIN_SPEED_NORMAL, PIN_PN, 0xF);
+	light_pin_cfg(GPIO2_20, PIN_SPEED_NORMAL, PIN_PN, 0xF);
+	light_pin_cfg(GPIO2_21, PIN_SPEED_NORMAL, PIN_PN, 0xF);                        ///<NC
+	light_pin_cfg(GPIO2_22, PIN_SPEED_NORMAL, PIN_PN, 0xF);                        ///<WIFI_BT_GPIO2
+	light_pin_cfg(GPIO2_23, PIN_SPEED_NORMAL, PIN_PN, 0xF);                        ///<WIFI_BT_GPIO3
+	light_pin_cfg(GPIO2_24, PIN_SPEED_NORMAL, PIN_PN, 0xF);                        ///<WIFI_BT_RST_N
+	light_pin_cfg(GPIO2_25, PIN_SPEED_NORMAL, PIN_PU, 0xF);                        ///KEY1
+
+	light_pin_mux(SDIO0_DETN, 0);
+	light_pin_cfg(SDIO0_DETN, PIN_SPEED_NORMAL, PIN_PN, 2);
+	// light_pin_mux(SDIO0_WPRTN,3);
+	// light_pin_cfg(SDIO0_WPRTN,PIN_SPEED_NORMAL,PIN_PN,2);                    ///< NC
+	// light_pin_mux(SDIO1_WPRTN,3);
+	// light_pin_cfg(SDIO1_WPRTN,PIN_SPEED_NORMAL,PIN_PU,2);                   ///VBUS_EN
+	// light_pin_mux(SDIO1_DETN,3);
+	// light_pin_cfg(SDIO1_DETN,PIN_SPEED_NORMAL,PIN_PN,2);                    ///WCN_33_EN
+
+	light_pin_mux(GPIO2_30, 1);
+	light_pin_mux(GPIO2_31, 1);
+	light_pin_mux(GPIO3_0, 1);
+	light_pin_mux(GPIO3_1, 1);
+	light_pin_mux(GPIO3_2, 1);
+	light_pin_mux(GPIO3_3, 1);
+	light_pin_cfg(GPIO2_30, PIN_SPEED_NORMAL, PIN_PN, 0xF);                 ///NC
+	light_pin_cfg(GPIO2_31, PIN_SPEED_NORMAL, PIN_PN, 0xF);                 ///NC
+	light_pin_cfg(GPIO3_0, PIN_SPEED_NORMAL, PIN_PN, 0xF);                  ///NC
+	light_pin_cfg(GPIO3_1, PIN_SPEED_NORMAL, PIN_PN, 0xF);
+	light_pin_cfg(GPIO3_2, PIN_SPEED_NORMAL, PIN_PN, 0xF);
+	light_pin_cfg(GPIO3_3, PIN_SPEED_NORMAL, PIN_PN, 0xF);
+
+	light_pin_cfg(HDMI_SCL, PIN_SPEED_NORMAL, PIN_PN, 0x2);
+	light_pin_cfg(HDMI_SDA, PIN_SPEED_NORMAL, PIN_PN, 0x2);
+	light_pin_cfg(HDMI_CEC, PIN_SPEED_NORMAL, PIN_PN, 0x2);
+
+	/* GMAC0 pad drive strength configurate to 0xF */
+	light_pin_cfg(GMAC0_TX_CLK, PIN_SPEED_NORMAL, PIN_PN, 0xF);
+	light_pin_cfg(GMAC0_RX_CLK, PIN_SPEED_NORMAL, PIN_PN, 0xF);
+	light_pin_cfg(GMAC0_TXEN, PIN_SPEED_NORMAL, PIN_PN, 0xF);
+	light_pin_cfg(GMAC0_TXD0, PIN_SPEED_NORMAL, PIN_PN, 0xF);
+	light_pin_cfg(GMAC0_TXD1, PIN_SPEED_NORMAL, PIN_PN, 0xF);
+	light_pin_cfg(GMAC0_TXD2, PIN_SPEED_NORMAL, PIN_PN, 0xF);
+	light_pin_cfg(GMAC0_TXD3, PIN_SPEED_NORMAL, PIN_PN, 0xF);
+	light_pin_cfg(GMAC0_RXDV, PIN_SPEED_NORMAL, PIN_PN, 0xF);
+	light_pin_cfg(GMAC0_RXD0, PIN_SPEED_NORMAL, PIN_PN, 0xF);
+	light_pin_cfg(GMAC0_RXD1, PIN_SPEED_NORMAL, PIN_PN, 0xF);
+	light_pin_cfg(GMAC0_RXD2, PIN_SPEED_NORMAL, PIN_PN, 0xF);
+	light_pin_cfg(GMAC0_RXD3, PIN_SPEED_NORMAL, PIN_PN, 0xF);
+	// light_pin_cfg(GMAC0_MDC, PIN_SPEED_NORMAL, PIN_PN, 0xF);
+	// light_pin_cfg(GMAC0_MDIO, PIN_SPEED_NORMAL, PIN_PN, 0xF);
+
+	light_pin_mux(GMAC0_COL, 3);
+	light_pin_mux(GMAC0_CRS, 3);
+	light_pin_cfg(GMAC0_COL, PIN_SPEED_NORMAL, PIN_PU, 2);
+	light_pin_cfg(GMAC0_CRS, PIN_SPEED_NORMAL, PIN_PU, 2);
+}
 #else
 static void light_iopin_init(void)
 {

board/thead/light-c910/lpddr-regu/ddr_regu.c

@@ -136,7 +136,7 @@ static const struct regulator_t g_apcpu_regu_id_list[] = {
 		REGU_ID_DEF(IIC_IDX_AONIIC,APCPU_REGU_VDDM,0x31,0x39,0,1,800000,600000,3500000,12500,1),
 	},
 };
-#elif defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_A_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_B_REF) || (CONFIG_TARGET_LIGHT_FM_C910_BEAGLE)
+#elif defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_A_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_B_REF) || (CONFIG_TARGET_LIGHT_FM_C910_BEAGLE) || defined (CONFIG_TARGET_LIGHT_FM_C910_LPI4A)
 /**
  * board for ant-ref
  *
@@ -165,6 +165,7 @@ static const struct regulator_t g_apcpu_regu_id_list[] = {
 	}
 };
 #else
+#if defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_B)
 /**
  * board for EB064A10/EB064A11
  *
@@ -183,6 +184,7 @@ static const struct regulator_t g_regu_id_list[] = {
 		REGU_ID_DEF(IIC_IDX_AONIIC,DDR_VDD_REGU_1V1,0x5A,0xA7,0,1,CONFIG_DDR_REGU_1V1,800000,1500000,20000,0),
 	}
 };
+#endif
 
 static const struct regulator_t g_apcpu_regu_id_list[] = {
 	{
@@ -236,7 +238,7 @@ static int wait_iic_receive(dw_iic_regs_t *iic_base, uint32_t wait_data_num, uin
 }
 
 
-unsigned long soc_get_iic_freq(uint32_t idx)
+static unsigned long soc_get_iic_freq(uint32_t idx)
 {
 	if (idx == IIC_IDX_AONIIC){
 		return 49152000U;
@@ -651,6 +653,7 @@ int32_t csi_iic_mem_receive_sr(csi_iic_t *iic, uint32_t devaddr, uint16_t memadd
     return read_count;
 }
 
+#if defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_A) ||defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_B)
 static int pmic_read_reg_sr(csi_iic_t *iic_handle,uint16_t dev_addr,uint32_t offset, uint32_t *val)
 {
 	int32_t num;
@@ -662,6 +665,7 @@ static int pmic_read_reg_sr(csi_iic_t *iic_handle,uint16_t dev_addr,uint32_t off
 	*val = temp[0];
 	return 0;
 }
+#endif
 
 static int pmic_write_reg(csi_iic_t *iic_handle,uint16_t dev_addr,uint32_t offset, uint32_t val)
 {
@@ -688,6 +692,7 @@ static int pmic_write_reg(csi_iic_t *iic_handle,uint16_t dev_addr,uint32_t offse
 	return 0;
 }
 
+#if !defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_A) && !defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_B)
 static int pmic_read_reg(csi_iic_t *iic_handle,uint16_t dev_addr,uint32_t offset, uint32_t *val)
 {
 	int32_t num;
@@ -716,6 +721,7 @@ static int pmic_read_reg(csi_iic_t *iic_handle,uint16_t dev_addr,uint32_t offset
 	*val = temp[0];
 	return 0;
 }
+#endif 
 
 static int _pmic_ddr_regu_init(uint32_t idx)
 {
@@ -818,13 +824,14 @@ int pmic_ddr_regu_init(void)
 int pmic_ddr_set_voltage(void)
 {
 	int ret = 0;
+
+#if 0 //currently,no need to modify ddr regulator voltage
 	uint32_t val = 0;
 	uint32_t regu_num = ARRAY_SIZE(g_regu_id_list);
 	uint32_t i;
 	struct regulator_t *pregu;
 	csi_iic_t          *dev_handle;
 
-#if 0 //currently,no need to modify ddr regulator voltage
 	pregu = (struct regulator_t*)g_regu_id_list;
 	for (i = 0; i < regu_num; i++, pregu++) {
 		if (pregu->regu_vol_target < pregu->regu_vol_min || pregu->regu_vol_target > pregu->regu_vol_max)
@@ -838,6 +845,10 @@ int pmic_ddr_set_voltage(void)
 #endif
 
 #if defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_B)
+	uint32_t val = 0;
+	struct regulator_t *pregu;
+	csi_iic_t          *dev_handle;
+
 	/*enable lcd0_en ldo*/
 	pregu = (struct regulator_t*)&g_regu_id_list[LCD0_EN];
 	dev_handle = pmic_get_iic_handle(pregu->iic_id);
@@ -944,7 +955,7 @@ int pmic_reset_apcpu_voltage(void)
 		return ret;
 	return 0;
 }
-#elif defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_A_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_B_REF)|| (CONFIG_TARGET_LIGHT_FM_C910_BEAGLE)
+#elif defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_A_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_B_REF)|| (CONFIG_TARGET_LIGHT_FM_C910_BEAGLE) || defined (CONFIG_TARGET_LIGHT_FM_C910_LPI4A)
 int pmic_reset_apcpu_voltage(void)
 {
 	int                ret = -1;

board/thead/light-c910/lpddr4/include/ddr_common_func.h

@@ -48,5 +48,5 @@ void ctrl_init(int rank_num, int speed);
 void addrmap(int rank_num, enum DDR_BITWIDTH bits);
 void ctrl_en(enum DDR_BITWIDTH bits);
 void enable_auto_refresh(void);
-
+void lpddr4_auto_selref(void);
 #endif // DDR_COMMON_FUNCE_H

board/thead/light-c910/lpddr4/src/ddr_common_func.c

@@ -1121,7 +1121,7 @@ void ddr_soc_pll_disable () {
   printf("DDR SOC PLL PowerDown \n");
 #endif
 }
-void lpddr4_auto_selref()
+void lpddr4_auto_selref(void)
 {
   ddr_sysreg_wr(DDR_CFG1,0xa0000);   //remove core clock after xx
   wr(SWCTL,0);

board/thead/light-c910/sec_check.c

@@ -12,7 +12,7 @@
 #include <asm/arch-thead/boot_mode.h>
 #include "../../../lib/sec_library/include/csi_sec_img_verify.h"
 
-extern int csi_efuse_api_int(void);
+extern int csi_efuse_api_init(void);
 extern int csi_efuse_api_unint(void);
 extern int csi_efuse_read_raw(uint32_t addr, void *data, uint32_t cnt);
 extern int csi_efuse_write_raw(uint32_t addr, const void *data, uint32_t cnt);
@@ -35,7 +35,7 @@ int csi_sec_init(void)
 	char *version;
 
 	/* Initialize eFuse module */
-	ret = csi_efuse_api_int();
+	ret = csi_efuse_api_init();
 	if (ret) {
 		printf("efuse init faild[%d]\n", ret);
 		 goto exit;
@@ -62,7 +62,7 @@ void designware_get_mac_from_fuse(unsigned char *mac)
 	int ret;
 
 	/* Initialize eFuse module */
-	ret = csi_efuse_api_int();
+	ret = csi_efuse_api_init();
 	if (ret) {
 		printf("efuse init faild[%d]\n", ret);
 		return;
@@ -75,6 +75,87 @@ void designware_get_mac_from_fuse(unsigned char *mac)
 	}
 }
 
+#if CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_VAL_A) || CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_VAL_B) || CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_ANT_REF) || CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_LPI4A)
+/* Secure function for image verificaiton here */
+int get_image_version(unsigned long img_src_addr)
+{
+	img_header_t *img = (img_header_t *)img_src_addr;
+	uint8_t magiccode[4] = {0};
+	
+	magiccode[3] = img->magic_num & 0xff;
+	magiccode[2] = (img->magic_num & 0xff00) >> 8;
+	magiccode[1] = (img->magic_num & 0xff0000) >> 16;
+	magiccode[0] = (img->magic_num & 0xff000000) >> 24;
+	if (memcmp(header_magic, magiccode, 4) == 0) {
+		return -1;
+	}
+	
+	return img->image_version;
+}
+
+int get_image_size(unsigned long img_src_addr)
+{
+	img_header_t *img = (img_header_t *)img_src_addr;
+	uint8_t magiccode[4] = {0};
+	
+	magiccode[3] = img->magic_num & 0xff;
+	magiccode[2] = (img->magic_num & 0xff00) >> 8;
+	magiccode[1] = (img->magic_num & 0xff0000) >> 16;
+	magiccode[0] = (img->magic_num & 0xff000000) >> 24;
+	if (memcmp(header_magic, magiccode, 4) == 0) {
+		return -1;
+	}
+	
+	return img->image_size;
+}
+
+void dump_image_header_info(long addr)
+{
+	img_header_t *phead = (img_header_t *)addr;
+
+	printf("\n---------------------------------------------\n");
+	printf("entry point: 0x%x\n", phead->entry_point);
+	printf("image size: %d Bytes\n", phead->image_size);
+	printf("head version: 0x%x\n", phead->head_version);
+	printf("image version: 0x%x\n", phead->image_version);
+	printf("image checksum: 0x%x\n", phead->image_checksum);
+	printf("image run addr: 0x%llx\n", phead->image_run_addr);
+	printf("image offset: 0x%x\n", phead->image_offset);
+	printf("image digest scheme: %d\n", phead->digest_scheme);
+	printf("image sign scheme: %d\n", phead->signature_scheme);
+	printf("image encrypt type: %d\n", phead->encrypt_type);
+	printf("\n---------------------------------------------\n");
+}
+
+int verify_customer_image(img_type_t type, long addr)
+{
+	int ret;
+    
+	/* Double check image number */
+	if (image_have_head(addr) == 0)
+		return -1;
+
+	/* Dump image header information here */
+	dump_image_header_info(addr);
+
+	/* Call customer image verification function */
+	if ((type == T_TF) || (type == T_TEE) || (type == T_KRLIMG)) {
+		ret = csi_sec_custom_image_verify(addr, UBOOT_STAGE_ADDR);
+		if (ret) {
+			printf("Image(%d) is verified fail, Please go to check!\n\n", type);
+			return ret;
+		}
+	} else if (type == T_UBOOT) {
+		ret = csi_sec_uboot_image_verify(addr, addr - PUBKEY_HEADER_SIZE);
+		if (ret) {
+			printf("Image(%s) is verified fail, Please go to check!\n\n", "uboot");
+			return ret;
+		}
+	}
+
+	return 0;
+}
+#else
 static int strtou32(const char *str, unsigned int base, u32 *result)
 {
 	char *ep;
@@ -110,7 +191,7 @@ static int do_fuse(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
 	int ret, i;
 
 	/* Initialize eFuse module */
-	ret = csi_efuse_api_int();
+	ret = csi_efuse_api_init();
 	if (ret) {
 		printf("efuse init faild[%d]\n", ret);
 		goto err;
@@ -180,88 +261,6 @@ err:
 	return CMD_RET_FAILURE;
 }
 
-#if CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_VAL_A) || CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_VAL_B) || CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_ANT_REF)
-/* Secure function for image verificaiton here */
-int get_image_version(unsigned long img_src_addr)
-{
-	img_header_t *img = (img_header_t *)img_src_addr;
-	uint8_t magiccode[4] = {0};
-	
-	magiccode[3] = img->magic_num & 0xff;
-	magiccode[2] = (img->magic_num & 0xff00) >> 8;
-	magiccode[1] = (img->magic_num & 0xff0000) >> 16;
-	magiccode[0] = (img->magic_num & 0xff000000) >> 24;
-	if (memcmp(header_magic, magiccode, 4) == 0) {
-		return -1;
-	}
-	
-	return img->image_version;
-}
-
-int get_image_size(unsigned long img_src_addr)
-{
-	img_header_t *img = (img_header_t *)img_src_addr;
-	uint8_t magiccode[4] = {0};
-	
-	magiccode[3] = img->magic_num & 0xff;
-	magiccode[2] = (img->magic_num & 0xff00) >> 8;
-	magiccode[1] = (img->magic_num & 0xff0000) >> 16;
-	magiccode[0] = (img->magic_num & 0xff000000) >> 24;
-	if (memcmp(header_magic, magiccode, 4) == 0) {
-		return -1;
-	}
-	
-	return img->image_size;
-}
-
-void dump_image_header_info(long addr)
-{
-	img_header_t *phead = (img_header_t *)addr;
-
-	printf("\n---------------------------------------------\n");
-	printf("entry point: 0x%x\n", phead->entry_point);
-	printf("image size: %d Bytes\n", phead->image_size);
-	printf("head version: 0x%x\n", phead->head_version);
-	printf("image version: 0x%x\n", phead->image_version);
-	printf("image checksum: 0x%x\n", phead->image_checksum);
-	printf("image run addr: 0x%llx\n", phead->image_run_addr);
-	printf("image offset: 0x%x\n", phead->image_offset);
-	printf("image digest scheme: %d\n", phead->digest_scheme);
-	printf("image sign scheme: %d\n", phead->signature_scheme);
-	printf("image encrypt type: %d\n", phead->encrypt_type);
-	printf("\n---------------------------------------------\n");
-}
-
-int verify_customer_image(img_type_t type, long addr)
-{
-	int ret;
-    const char *image_name = "";
-    
-	/* Double check image number */
-	if (image_have_head(addr) == 0)
-		return -1;
-
-	/* Dump image header information here */
-	dump_image_header_info(addr);
-
-	/* Call customer image verification function */
-	if ((type == T_TF) || (type == T_TEE) || (type == T_KRLIMG)) {
-		ret = csi_sec_custom_image_verify(addr, UBOOT_STAGE_ADDR);
-		if (ret) {
-			printf("Image(%d) is verified fail, Please go to check!\n\n", type);
-			return ret;
-		}
-	} else if (type == T_UBOOT) {
-		ret = csi_sec_uboot_image_verify(addr, addr - PUBKEY_HEADER_SIZE);
-		if (ret) {
-			printf("Image(%s) is verified fail, Please go to check!\n\n", "uboot");
-			return ret;
-		}
-	}
-
-	return 0;
-}
-#else
 U_BOOT_CMD(
 	efuse, CONFIG_SYS_MAXARGS, 0, do_fuse,
 	"eFuse sub-system",

board/thead/light-c910/secimg_load.c

@@ -0,0 +1,212 @@
+/*
+ * (C) Copyright 2018, Linaro Limited
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#include <command.h>
+#include <env.h>
+#include <configs/light-c910.h>
+#include <asm/arch-thead/boot_mode.h>
+#include "sec_library.h"
+
+#define ENV_SECIMG_LOAD     "sec_m_load"
+#define VAL_SECIMG_LOAD     "ext4load mmc 0:7 $tf_addr trust_firmware.bin; ext4load mmc 0:7 $tee_addr tee.bin"
+
+#define RPMB_BLOCK_SIZE 256
+#define RPMB_ROLLBACK_BLOCK_START 1
+
+#ifndef LIGHT_KDF_RPMB_KEYs
+static const unsigned char emmc_rpmb_key_sample[32] = {0x33, 0x22, 0x11, 0x00, 0x77, 0x66, 0x55, 0x44, \
+												0xbb, 0xaa, 0x99, 0x88, 0xff, 0xee, 0xdd, 0xcc, \
+												0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, \
+												0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
+#endif
+
+extern int sprintf(char *buf, const char *fmt, ...);
+
+static int get_rpmb_key(uint8_t key[32])
+{
+#ifndef LIGHT_KDF_RPMB_KEY 
+    memcpy(key, emmc_rpmb_key_sample, sizeof(emmc_rpmb_key_sample));
+
+    return 0;
+#else 
+	uint32_t kdf_rpmb_key_length = 0;
+	int ret = 0;
+	ret = csi_kdf_gen_hmac_key(key, &kdf_rpmb_key_length);
+	if (ret != 0) {
+		return -1;
+	}
+
+    return 0;
+#endif
+}
+
+static int get_image_file_size(unsigned long img_src_addr)
+{
+	img_header_t *img = (img_header_t *)img_src_addr;
+	uint8_t magiccode[4] = {0};
+	
+	magiccode[3] = img->magic_num & 0xff;
+	magiccode[2] = (img->magic_num & 0xff00) >> 8;
+	magiccode[1] = (img->magic_num & 0xff0000) >> 16;
+	magiccode[0] = (img->magic_num & 0xff000000) >> 24;
+	if (memcmp(header_magic, magiccode, 4) == 0) {
+		return -1;
+	}
+	
+	return img->image_size;
+}
+
+static int verify_and_load_image(unsigned long image_addr_src, unsigned long image_addr_dst)
+{
+    int ret = 0;
+	unsigned int image_size = 0;
+
+	if (image_have_head(image_addr_src) == 1) {
+        ret = csi_sec_init();
+        if (ret != 0) {
+			return -1;
+		}
+        
+        ret = csi_sec_custom_image_verify(image_addr_src, UBOOT_STAGE_ADDR);
+        if (ret != 0) {
+            printf("image verify error\r\n");
+            return -2;
+        }
+		
+		image_size = get_image_file_size(image_addr_src);
+		if (image_size  < 0) {
+            printf("image get size error\r\n");
+			return -3;
+		}
+
+		memmove((void *)image_addr_dst, (const void *)(image_addr_src + HEADER_SIZE), image_size);
+	} else {
+        printf("in secure mode but image has no header\r\n");
+		return -4;
+	}
+
+    return 0;
+}
+
+int verify_and_load_tee_tf_image(void)
+{
+    int ret = 0;
+
+    ret = verify_and_load_image(LIGHT_TF_FW_TMP_ADDR, LIGHT_TF_FW_ADDR);
+    if (ret != 0) {
+        printf("verify tf image failed\r\n");
+        return ret;
+    }
+    printf("verify trust firmware image success\r\n");
+
+    ret = verify_and_load_image(LIGHT_TEE_FW_ADDR, LIGHT_TEE_FW_ADDR);
+    if (ret != 0) {
+        printf("verify tee image failed\r\n");
+        return ret;
+    }
+    printf("verify tee image success\r\n");
+
+    return 0;
+}
+
+/* In order to use common bootloader for both secure boot and non-secure boot,
+   we only know the boot type through reading the sec_boot field in efuse. Due to 
+   the efuse is only accessed in lifecycle(DEV/OEM/PRO/RMP), we ensure it must be 
+   non-secure boot in lifecycle(INIT) */
+bool get_system_boot_type(void)
+{
+	bool btype = false; /* false: non-secure boot | true: secure boot */
+	int lc = 0;
+	sboot_st_t sb_flag = SECURE_BOOT_DIS;
+	int ret = 0;
+
+	ret = csi_efuse_get_lc(&lc);
+	/* 0: LC_INIT, 1: LC_DEV, 2: LC_OEM, 3: LC_PRO */
+	if ((ret == 0) && (lc != 0)) {
+		csi_efuse_api_init();
+
+		/* Check platform secure boot enable ? */
+		ret = csi_efuse_get_secure_boot_st(&sb_flag);
+		if ((ret == 0) && (sb_flag == SECURE_BOOT_EN))
+			btype = true;
+
+		csi_efuse_api_uninit();
+	}
+
+	return btype;
+}
+
+int sec_read_rollback_index(size_t rollback_index_slot, uint64_t *out_rollback_index)
+{
+	char runcmd[64] = {0};
+	unsigned char blkdata[RPMB_BLOCK_SIZE];
+    size_t rpmb_block = (rollback_index_slot * sizeof(uint64_t)) / RPMB_BLOCK_SIZE + RPMB_ROLLBACK_BLOCK_START;
+    size_t rpmb_offset = (rollback_index_slot * sizeof(uint64_t)) % RPMB_BLOCK_SIZE;
+
+    sprintf(runcmd, "mmc rpmb read 0x%lx %ld 1", (unsigned long)blkdata, rpmb_block);
+	if(run_command(runcmd, 0)) {
+        printf("read_rollback_index failed, mmc read error\r\n");
+        return -1;
+    }
+
+    *out_rollback_index = *(uint64_t*)(blkdata + rpmb_offset);
+	return 0;
+}
+
+int sec_write_rollback_index(size_t rollback_index_slot, uint64_t rollback_index)
+{
+    char runcmd[64] = {0};
+	unsigned char blkdata[RPMB_BLOCK_SIZE];
+    size_t rpmb_block = (rollback_index_slot * sizeof(uint64_t)) / RPMB_BLOCK_SIZE + RPMB_ROLLBACK_BLOCK_START;
+    size_t rpmb_offset = (rollback_index_slot * sizeof(uint64_t)) % RPMB_BLOCK_SIZE;
+    uint8_t rpmb_key[32];
+
+    sprintf(runcmd, "mmc rpmb read 0x%lx %ld 1", (unsigned long)blkdata, rpmb_block);
+	if(run_command(runcmd, 0)) {
+        printf("read_rollback_index failed, mmc read error\r\n");
+        return -1;
+    }
+
+    *(uint64_t*)(blkdata + rpmb_offset) = rollback_index;
+    
+    if (get_rpmb_key(rpmb_key) != 0) {
+        return -2;
+    }
+
+	sprintf(runcmd, "mmc rpmb write 0x%lx %ld 1 0x%lx", (unsigned long)blkdata, rpmb_block, (unsigned long)rpmb_key);
+    if(run_command(runcmd, 0)) {
+        printf("read_rollback_index failed, mmc write error\r\n");
+        return -3;
+    }
+
+    return 0;
+}
+
+static int do_secimg_load(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+    bool sb_enable = false;
+    const char *secimgs_load_str = VAL_SECIMG_LOAD;
+    int ret = -1;
+    sb_enable = get_system_boot_type();
+    if (sb_enable) {
+        /* By default, the value for ENV-SEC-M-LOAD is always to load opensbi image.
+         * if secure boot is enable, we force to change the value to load tee image.
+         * but Never to save it in volatile-RAM
+         */
+        ret = env_set(ENV_SECIMG_LOAD, secimgs_load_str);
+        if (ret != 0) {
+            printf("Rewrite ENV (%s) fails\n", ENV_SECIMG_LOAD);
+            return CMD_RET_FAILURE;
+        }
+    }
+    
+	return CMD_RET_SUCCESS;
+}
+
+U_BOOT_CMD(
+	secimg_load, 1, 1,	do_secimg_load,
+	"Runtime-load secure image if secure system is enable",
+	NULL
+);

board/thead/light-c910/spl.c

@@ -48,6 +48,7 @@ static struct light_reset_list light_post_reset_lists[] = {
 	{0x00000002, 0xFFEF528000}, /* VO sys_reg: GPU rst */
 	{0x00000003, 0xFFEF528000}, /* VO sys_reg: GPU rst */
 	{0x00000007, 0xFFFF529004}, /* VO sys_reg: DPU rst */
+	{0x07FFFF18, 0xFFCB000014}, /* Audio sys_reg: DMA rst */
 };
 
 static void light_pre_reset_config(void)
@@ -306,7 +307,7 @@ void cpu_performance_enable(void)
 	csr_write(CSR_MCCR2, 0xe2490009);
 	csr_write(CSR_MHCR, 0x117f); // clear bit7 to disable indirect brantch prediction
 	csr_write(CSR_MXSTATUS, 0x638000);
-	csr_write(CSR_MHINT, 0x6e30c | (1<<22)); // set bit22 to close fence broadcast
+	csr_write(CSR_MHINT, 0x6e30c | (1<<21) | (1<<22)); // set bit21 & bit 22 to close tlb & fence broadcast
 }
 
 static int bl1_img_have_head(unsigned long img_src_addr)
@@ -399,9 +400,20 @@ void board_init_f(ulong dummy)
 	light_board_init_r(NULL, 0);
 }
 
+static uint32_t get_custom_boot_seq(void)
+{
+	/* boot media definition */
+	/* BOOT_DEVICE_MMC1 - boot from eMMC or SD card */
+	/* BOOT_DEVICE_NAND - boot from nand flash */
+	/* BOOT_DEVICE_SPI - boot from spi flash */
+	/* TODO: user can decide the boot media according their own configuration */
+	return BOOT_DEVICE_MMC1;
+}
+
 void board_boot_order(u32 *spl_boot_list)
 {
 #define SOC_OM_ADDRBASE        0xffef018010
+#if CONFIG_IS_ENABLED(LIGHT_BOOT_FORCE_SEQ)
 	switch (readl((void *)SOC_OM_ADDRBASE) & 0x7) {
 	case 0:
 	case 1:
@@ -428,6 +440,8 @@ void board_boot_order(u32 *spl_boot_list)
 	default:
 		spl_boot_list[0] = BOOT_DEVICE_NONE;
 	}
-
+#else
+	spl_boot_list[0] = get_custom_boot_seq();
+#endif
 	cpu_performance_enable();
 }

board/thead/light-c910/sys_clk.c

@@ -43,9 +43,9 @@ void cpu_clk_config(uint32_t cpu_freq)
 	udelay(11);
 
 	/* config bus: cpu clk ratio to 1:1 */
-	writel((readl(LIGHT_APCLK_ADDRBASE + 0x100) & (~(0x7<<8))) | (0x0<<8), (void *)(LIGHT_APCLK_ADDRBASE + 0x100)); // ratio=0
-	writel(readl(LIGHT_APCLK_ADDRBASE + 0x100) & (~(0x1<<11)), (void *)(LIGHT_APCLK_ADDRBASE + 0x100)); // sync=0
-	writel(readl(LIGHT_APCLK_ADDRBASE + 0x100) | (0x1<<11), (void *)(LIGHT_APCLK_ADDRBASE + 0x100)); // sync=1
+	writel((readl((const volatile void __iomem *)(LIGHT_APCLK_ADDRBASE + 0x100)) & (~(0x7<<8))) | (0x0<<8), (void *)(LIGHT_APCLK_ADDRBASE + 0x100)); // ratio=0
+	writel(readl((const volatile void __iomem *)(LIGHT_APCLK_ADDRBASE + 0x100)) & (~(0x1<<11)), (void *)(LIGHT_APCLK_ADDRBASE + 0x100)); // sync=0
+	writel(readl((const volatile void __iomem *)(LIGHT_APCLK_ADDRBASE + 0x100)) | (0x1<<11), (void *)(LIGHT_APCLK_ADDRBASE + 0x100)); // sync=1
 
 	/* switch c910_cclk to cpu_pll1_foutpostdiv */
 	tmp = readl((void *)LIGHT_APCLK_ADDRBASE + 0x100);
@@ -290,7 +290,7 @@ void sys_clk_config(void)
 
 	/* The boards other than the LightA board perform the bus down-speed operation */
 
-#if defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_DISCRETE) || defined (CONFIG_TARGET_LIGHT_FM_C910_BEAGLE) || defined (CONFIG_TARGET_LIGHT_FM_C910_B_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_B_POWER) || defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_B)
+#if defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_DISCRETE) || defined (CONFIG_TARGET_LIGHT_FM_C910_B_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_B_POWER) || defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_B)
 	/* axi_sram_clk: 812.8512MHz -> 688.128MHz */
 	tmp = readl((void *)LIGHT_AONCLK_ADDRBASE + 0x104);
 	tmp |= 0x2000;

cmd/Kconfig

@@ -263,6 +263,12 @@ config CMD_BOOTI
 	help
 	  Boot an AArch64 Linux Kernel image from memory.
 
+config CMD_BOOTANDROID
+	bool "bootandroid"
+	default n
+	help
+	Boot an android image from mmc.
+
 config BOOTM_LINUX
 	bool "Support booting Linux OS images"
 	depends on CMD_BOOTM || CMD_BOOTZ || CMD_BOOTI

cmd/Makefile

@@ -175,6 +175,7 @@ obj-$(CONFIG_CMD_REGULATOR) += regulator.o
 obj-$(CONFIG_CMD_BLOB) += blob.o
 
 # Android Verified Boot 2.0
+obj-$(CONFIG_CMD_BOOTANDROID) += bootandroid.o
 obj-$(CONFIG_CMD_AVB) += avb.o
 
 obj-$(CONFIG_DDR_SCAN) += ddrscan.o

cmd/avb.c

@@ -312,6 +312,10 @@ int do_avb_verify_part(cmd_tbl_t *cmdtp, int flag,
 		printf("Unknown error occurred\n");
 	}
 
+#ifdef CONFIG_ANDROID_BOOT_IMAGE
+	if (out_data)
+		avb_slot_verify_data_free(out_data);
+#endif
 	return res;
 }
 

cmd/bootandroid.c

@@ -0,0 +1,453 @@
+
+/*
+ * (C) Copyright 2018, Linaro Limited
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <avb_verify.h>
+#include <command.h>
+#include <env.h>
+#include <image.h>
+#include <malloc.h>
+#include <mmc.h>
+#include <android_image.h>
+#include <android_bootloader_message.h>
+#include <xbc.h>
+
+#define ENV_KERNEL_ADDR  "kernel_addr"
+#define ENV_RAMDISK_ADDR "ramdisk_addr"
+#define ENV_DTB_ADDR     "dtb_addr"
+#define DEFAULT_KERNEL_ADDR  0x00200800
+#define DEFAULT_RAMDISK_ADDR 0x02000000
+#define DEFAULT_DTB_ADDR     0x01f00000
+#define ENV_RAMDISK_SIZE "ramdisk_size"
+#define MISC_PARTITION "misc"
+#define RECOVERY_PARTITION "recovery"
+#define BOOT_PARTITION "boot"
+#define VENDOR_BOOT_PARTITION "vendor_boot"
+
+#define BOOTDEV_DEFAULT		0
+#define BCB_BOOTONCE	"bootonce-bootloader"
+#define BCB_BOOTRECOVERY	"boot-recovery"
+
+
+/*
+ * Knowing secure boot is enable or disable dependents on 
+ * special data field in efuse and efuse control register.
+ */
+extern bool get_system_boot_type(void);
+/*
+ * The suffix for partition name is from the value of ENV_BOOTAB
+ */
+static const char *slot_name_suffix = NULL;;
+
+/*
+ * BOOT IMAGE HEADER V3/V4 PAGESIZE
+ * Source code:system/tools/mkbootimg/unpack_bootimg.py
+ */
+#define BOOT_IMAGE_HEADER_V3_PAGESIZE 4096
+
+static struct AvbOps *avb_ops = NULL;
+static struct bootloader_message* s_bcb = NULL;
+
+/*
+ *format 4 chars/bytes to a int number
+ */
+static int byteToInt(uint8_t* data,int offset)
+{
+	return data[offset+0] + (data[offset+1] << 8) + (data[offset+2] << 16) + (data[offset+3] << 24);
+}
+
+static int get_number_of_pages(int image_size, int page_size)
+{
+    return (image_size + page_size - 1) / page_size;
+}
+
+/**
+ * header_version >=3,get dtb data from vendor_boot.img ,else boot.img.
+ *
+ * header_version = 4,get bootconfig data from vendor_boot.img ,
+ * and append bootconfig to the end of ramdisk(initrd)
+ * doc:https://www.kernel.org/doc/html/next/translations/zh_CN/admin-guide/bootconfig.html#initrd
+ */
+static int prepare_data_from_vendor_boot(struct andr_img_hdr *hdr, int dtb_start, uint8_t** buf_bootconfig, int* vendor_bootconfig_size)
+{
+	int ret;
+	disk_partition_t part_info;
+	uint8_t* vendor_boot_data = NULL;
+	struct blk_desc *dev_desc  = blk_get_dev("mmc", CONFIG_FASTBOOT_FLASH_MMC_DEV);
+	char vb_part_name[32] = {0};
+
+	if (hdr == NULL) {
+		printf("invalid hdr\n");
+		return -1;
+	}
+
+	/* if the vendor boot partition name is beyond 32B, arise error */
+	if ((32 - strlen(VENDOR_BOOT_PARTITION)) < 2)
+		return -1;
+	memcpy(vb_part_name, VENDOR_BOOT_PARTITION, strlen(VENDOR_BOOT_PARTITION));
+	strcat(vb_part_name, slot_name_suffix);
+
+	printf("blk_get_dev %s\n", vb_part_name);
+	if (!dev_desc || dev_desc->type == DEV_TYPE_UNKNOWN) {
+		printf("MMC err: invalid mmc device\n");
+		return -1;
+	}
+	/* Get boot partition info */
+	ret = part_get_info_by_name(dev_desc, vb_part_name, &part_info);
+	if (ret < 0) {
+		printf("MMC err: cannot find %s partition\n", vb_part_name);
+		return -1;
+	}
+
+	vendor_boot_data = avb_malloc(part_info.size * part_info.blksz);
+	if (vendor_boot_data == NULL) {
+		printf("vendor boot data malloc fail \n");
+		return -1;
+	}
+	ret = blk_dread(dev_desc, part_info.start, part_info.size, vendor_boot_data);
+	// vendor_boot.img
+	//* +------------------------+
+	//* | vendor boot header     | o pages
+	//* +------------------------+
+	//* | vendor ramdisk section | p pages
+	//* +------------------------+
+	//* | dtb                    | q pages
+	//* +------------------------+
+	//* | vendor ramdisk table   | r pages
+	//* +------------------------+
+	//* | bootconfig             | s pages
+	//* +------------------------+
+	//* o = (2124 + page_size - 1) / page_size
+	//* p = (vendor_ramdisk_size + page_size - 1) / page_size
+	//* q = (dtb_size + page_size - 1) / page_size
+	//* r = (vendor_ramdisk_table_size + page_size - 1) / page_size
+	//* s = (vendor_bootconfig_size + page_size - 1) / page_size
+
+	// see system/tools/mkbootimg/unpack_bootimg.py
+	// info.boot_magic = unpack('8s', args.boot_img.read(8))[0].decode()
+	// info.header_version = unpack('I', args.boot_img.read(4))[0]
+	// info.page_size = unpack('I', args.boot_img.read(4))[0]
+	// info.kernel_load_address = unpack('I', args.boot_img.read(4))[0]
+	// info.ramdisk_load_address = unpack('I', args.boot_img.read(4))[0]
+	// info.vendor_ramdisk_size = unpack('I', args.boot_img.read(4))[0]
+	// info.cmdline = cstr(unpack('2048s', args.boot_img.read(2048))[0].decode())
+	// info.tags_load_address = unpack('I', args.boot_img.read(4))[0]
+	// info.product_name = cstr(unpack('16s', args.boot_img.read(16))[0].decode())
+	// info.header_size = unpack('I', args.boot_img.read(4))[0]
+	// info.dtb_size = unpack('I', args.boot_img.read(4))[0]
+	// info.dtb_load_address = unpack('Q', args.boot_img.read(8))[0]
+	// info.vendor_ramdisk_table_size = unpack('I', args.boot_img.read(4))[0]
+	// vendor_ramdisk_table_entry_num = unpack('I', args.boot_img.read(4))[0]
+	// vendor_ramdisk_table_entry_size = unpack('I', args.boot_img.read(4))[0]
+	// info.vendor_bootconfig_size = unpack('I', args.boot_img.read(4))[0]
+	// num_vendor_ramdisk_table_pages = get_number_of_pages(
+	// 	info.vendor_ramdisk_table_size, page_size)
+	// vendor_ramdisk_table_offset = page_size * (
+	// 	num_boot_header_pages + num_boot_ramdisk_pages + num_boot_dtb_pages)
+	// bootconfig_offset = page_size * (num_boot_header_pages
+	// 	+ num_boot_ramdisk_pages + num_boot_dtb_pages
+	// 	+ num_vendor_ramdisk_table_pages)
+
+	int vendor_boot_pagesize = byteToInt(vendor_boot_data,12);//offset 12
+	int vendor_ramdisk_size = byteToInt(vendor_boot_data,24);//offset 24
+	int dtb_size = byteToInt(vendor_boot_data,2100);//offset 2100
+	int o = (2124 + vendor_boot_pagesize - 1) / vendor_boot_pagesize;
+	int p = (vendor_ramdisk_size + vendor_boot_pagesize - 1) / vendor_boot_pagesize;
+	int dtb_offset = vendor_boot_pagesize * (o + p);
+
+	hdr->dtb_size=  dtb_size;
+	memcpy((void *)(uint64_t)dtb_start, vendor_boot_data + dtb_offset, hdr->dtb_size);
+
+	int q=(hdr->dtb_size + vendor_boot_pagesize - 1) / vendor_boot_pagesize;
+	int vendor_ramdisk_table_size=byteToInt(vendor_boot_data,2112);//offset 2112
+	
+	int r=(vendor_ramdisk_table_size + vendor_boot_pagesize - 1) / vendor_boot_pagesize;
+	*vendor_bootconfig_size=byteToInt(vendor_boot_data,2124);//offset 2124
+	
+	*buf_bootconfig = avb_malloc(*vendor_bootconfig_size);
+	if (*buf_bootconfig == NULL) {
+		printf("vendor bootconfig malloc fail\n");
+		if (vendor_boot_data != NULL)
+			avb_free(vendor_boot_data);
+		return -1;
+	}
+	int bootconfig_offset=vendor_boot_pagesize * (o + p + q + r);
+	memcpy(*buf_bootconfig, vendor_boot_data + bootconfig_offset, *vendor_bootconfig_size);
+
+	if (vendor_boot_data != NULL)
+		avb_free(vendor_boot_data);
+
+	return 0;
+}
+
+static void prepare_loaded_parttion_data(const uint8_t* data)
+{
+	struct andr_img_hdr *hdr = (struct andr_img_hdr *)map_sysmem((phys_addr_t)data, 0);
+
+	if (IMAGE_FORMAT_ANDROID == genimg_get_format(hdr)) {
+		int dtb_start = env_get_hex(ENV_DTB_ADDR, DEFAULT_DTB_ADDR);
+		uint8_t* buf_bootconfig = NULL;
+		int size_bootconfig=0;
+
+		printf("Boot image header_version:%d\n", hdr->header_version);
+		if (hdr->header_version >= 3) {
+			// see system/tools/mkbootimg/unpack_bootimg.py
+			hdr->kernel_size = byteToInt((uint8_t *)data, 8);
+			hdr->ramdisk_size = byteToInt((uint8_t *)data, 12);
+			hdr->page_size = BOOT_IMAGE_HEADER_V3_PAGESIZE;
+			prepare_data_from_vendor_boot(hdr,dtb_start,&buf_bootconfig,&size_bootconfig);
+		}
+
+		int kernel_start = env_get_hex(ENV_KERNEL_ADDR, DEFAULT_KERNEL_ADDR);
+		int ramdisk_start = env_get_hex(ENV_RAMDISK_ADDR, DEFAULT_RAMDISK_ADDR);
+		// see system/tools/mkbootimg/unpack_bootimg.py
+ 		int page_size = hdr->page_size;
+		int num_header_pages = 1;
+		int num_kernel_pages = get_number_of_pages(hdr->kernel_size, page_size);
+		int num_ramdisk_pages = get_number_of_pages(hdr->ramdisk_size, page_size);
+		int kernel_offset = page_size * num_header_pages;
+		int ramdisk_offset = page_size * (num_header_pages + num_kernel_pages);
+		int dtb_offset = page_size * (num_header_pages + num_kernel_pages + num_ramdisk_pages);
+
+		printf("Boot image kernel_start:%x, kernel_offset:%x, kernel_size:%d\n", kernel_start, kernel_offset, hdr->kernel_size);
+		printf("Boot image ramdisk_start:%x, ramdisk_offset:%x, ramdisk_size:%d\n", ramdisk_start, ramdisk_offset, hdr->ramdisk_size);
+		printf("Boot image page_size:%d\n", hdr->page_size);
+		printf("dtb_offset:%x, dtb_size:%d\n", dtb_offset, hdr->dtb_size);
+
+ 		if (kernel_start + hdr->kernel_size > ramdisk_start || kernel_start + hdr->kernel_size > dtb_start) {
+			printf("boot.img kernel space and ramdis space are overlaped !!!\n");
+		} else {
+			memcpy((void *)(uint64_t)kernel_start, data + kernel_offset, hdr->kernel_size);
+			memcpy((void *)(uint64_t)ramdisk_start, data + ramdisk_offset, hdr->ramdisk_size);
+			if( hdr->header_version < 3) {
+				//set ramdisk size for bootm
+				env_set_hex(ENV_RAMDISK_SIZE, hdr->ramdisk_size);
+				memcpy((void *)(uint64_t)dtb_start, data + dtb_offset, hdr->dtb_size);
+			} else {
+				//get bootconfig form vendor_boot.img and append bootconfig to ramdisk
+				char* bootconfig_params=(char*)buf_bootconfig;
+				int ret = addBootConfigParameters(bootconfig_params, size_bootconfig,
+                            						ramdisk_start + hdr->ramdisk_size , 0);
+				if (ret == -1) {
+					printf("Bootconfig Err: add BootConfig Parameters error!!!\n");
+				} else {
+					printf("ramdisk size is updated to new value is:%d\n",hdr->ramdisk_size + ret);
+					//set ramdisk size for bootm
+					env_set_hex(ENV_RAMDISK_SIZE, hdr->ramdisk_size + ret);
+				}
+			}
+		}
+		if (buf_bootconfig != NULL) {
+			avb_free(buf_bootconfig);
+		}
+	}
+	unmap_sysmem(hdr);
+}
+
+static int prepare_boot_data(const AvbSlotVerifyData *out_data)
+{
+	int res = CMD_RET_FAILURE;
+	int i = 0;
+	int num_loaded_partition = out_data->num_loaded_partitions;
+
+	printf("@@@@ prepare loaded partition (%d) data start\n", num_loaded_partition);
+	for (i = 0; i < num_loaded_partition; i++) {
+		const AvbPartitionData *loaded_partition = &out_data->loaded_partitions[i];
+		
+		if (loaded_partition->partition_name != NULL) {
+			printf("partition_name=%s, data_size=%ld\n", \
+					loaded_partition->partition_name, loaded_partition->data_size);
+			prepare_loaded_parttion_data(loaded_partition->data);
+		}
+	}
+	return res;
+}
+
+static void prepare_partition_data(const char *name)
+{
+	int ret = 0;
+	disk_partition_t part_info;
+	struct blk_desc *dev_desc  = blk_get_dev("mmc", CONFIG_FASTBOOT_FLASH_MMC_DEV);
+	uint8_t *data = NULL;
+
+	printf("prepare_partition_data %s\n", name);
+	if (!dev_desc || dev_desc->type == DEV_TYPE_UNKNOWN) {
+		printf("MMC err: invalid mmc device\n");
+		return;
+	}
+	/* Get boot partition info */
+	ret = part_get_info_by_name(dev_desc, name, &part_info);
+	if (ret < 0) {
+		printf("MMC err: cannot find %s partition\n", name);
+		return;
+	}
+
+	data = avb_malloc(part_info.size * part_info.blksz);
+	if (data == NULL) {
+		printf("avb malloc(%ldKB) fails\n", part_info.size * part_info.blksz / 1024);
+		return;
+	}
+
+	ret = blk_dread(dev_desc, part_info.start, part_info.size, data);
+	prepare_loaded_parttion_data(data);
+	
+	printf("prepare_partition_data %s, read=%d, start:%lx, size:%ld, blksize:%lx\n", \
+			name, ret, part_info.start, part_info.size, part_info.blksz);
+
+	avb_free(data);
+}
+
+static void clear_bcb(void)
+{
+	int ret;
+	disk_partition_t part_info;
+	struct blk_desc *dev_desc  = blk_get_dev("mmc", CONFIG_FASTBOOT_FLASH_MMC_DEV);
+
+	//bcb clear and store
+	memset(s_bcb, 0, sizeof(struct bootloader_message));
+
+	if (!dev_desc || dev_desc->type == DEV_TYPE_UNKNOWN) {
+		printf("BootAndriod bcb err: invalid mmc device\n");
+		return;
+	}
+	/* Get boot partition info */
+	ret = part_get_info_by_name(dev_desc, MISC_PARTITION, &part_info);
+	if (ret < 0) {
+		printf("BootAndriod bcb err: cannot find misc partition\n");
+		return;
+	}
+
+	ret = blk_dwrite(dev_desc, part_info.start, part_info.size, s_bcb);
+	printf("BootAndriod bcb info :clear_bcb write=%d, %ld,%ld,%ld\n", ret, part_info.start, part_info.size, part_info.blksz);
+}
+
+static int do_andriod_bcb_business(struct AvbOps *avb_ops, struct bootloader_message* s_bcb)
+{
+	AvbIOResult ret = AVB_IO_RESULT_OK;
+	size_t bytes_read = 0;
+	int res = CMD_RET_FAILURE;
+
+	s_bcb = avb_malloc(sizeof(struct bootloader_message));
+	if (s_bcb == NULL) {
+		printf("BootAndriod Err: Failed to initialize bcb\n");
+		goto _bcb_err;
+	}
+
+	ret = avb_ops->read_from_partition(avb_ops,
+										MISC_PARTITION,
+										0,
+										sizeof(struct bootloader_message),
+										s_bcb,
+										&bytes_read);
+	if (ret != AVB_IO_RESULT_OK) {
+		printf("BootAndriod Err: Bcb read failed\n");
+		goto _bcb_err;
+	}
+
+	/* Enter into fastboot mode if bcb string is bootonce or bootrecovery */
+	if (0 == strncmp(s_bcb->command, BCB_BOOTONCE, strlen(BCB_BOOTONCE))|| \
+	    0 == strncmp(s_bcb->command, BCB_BOOTRECOVERY, strlen(BCB_BOOTRECOVERY))) {
+		printf("BootAndriod Info: Bcb read %ld bytes, %s\n", bytes_read, s_bcb->command);
+		printf("BootAndriod Info: Enter fastboot mode\n");
+		clear_bcb();
+		run_command("fastboot usb 0", 0);
+	}
+
+	res = CMD_RET_SUCCESS;
+
+_bcb_err:
+	if (s_bcb != NULL)
+		avb_free(s_bcb);
+
+	return res;
+}
+
+static const char *get_boot_partition_name_suffix(void)
+{
+#if defined (CONFIG_ANDROID_AB)
+	char *slot_suffix = "_a";
+#else
+	char *slot_suffix = "";
+#endif
+
+	char *tmp = NULL;
+	tmp = env_get("boot_ab");
+	if (tmp != NULL)
+		slot_suffix = tmp;
+
+	return slot_suffix;
+}
+
+static int do_bootandroid(struct cmd_tbl_s *cmdtp, int flag, int argc,
+						char * const argv[]) {
+	
+	const char * const requested_partitions[] = {"vbmeta", "boot", "vbmeta_system", NULL};
+	AvbSlotVerifyResult slot_result = AVB_SLOT_VERIFY_RESULT_OK;
+	AvbSlotVerifyData *slot_data = NULL;
+	AvbIOResult ret = AVB_IO_RESULT_OK;
+	AvbSlotVerifyFlags slotflags = AVB_SLOT_VERIFY_FLAGS_NONE;
+	AvbHashtreeErrorMode htflags = AVB_HASHTREE_ERROR_MODE_RESTART_AND_INVALIDATE;
+	int res = CMD_RET_FAILURE;
+
+	/* Retieve boot partition 's name suffix */
+	slot_name_suffix = get_boot_partition_name_suffix();
+
+	/* Start with slot verification in secure boot */
+	if (get_system_boot_type()) {
+
+		avb_ops = avb_ops_alloc(BOOTDEV_DEFAULT);
+		if (avb_ops == NULL) {
+			goto _ba_err;
+		}
+
+		res = do_andriod_bcb_business(avb_ops, s_bcb);
+		if (res != CMD_RET_SUCCESS) {
+			goto _ba_err;
+		}
+				
+		/* Verify boot partition requested in vbmeta.img */
+		slot_result = avb_slot_verify(avb_ops,
+									  requested_partitions,
+									  slot_name_suffix,
+									  slotflags,
+									  htflags,
+									&slot_data);
+
+		if (slot_result == AVB_SLOT_VERIFY_RESULT_OK) {
+			printf("BootAndriod Info: Request Partition are verified successfully\n");
+			printf("BootAndriod cmdline: slot_data.cmdline:%s\n", slot_data->cmdline);
+			prepare_boot_data(slot_data);
+			if (ret == 0) {
+				if (slot_data != NULL)
+					avb_slot_verify_data_free(slot_data);
+			}
+		} else {
+			/* In case of avb slot verification failure, Force system reset */
+			run_command("reset", 0);
+		}
+_ba_err:
+		if (avb_ops)
+			avb_ops_free(avb_ops);
+
+	} else {
+	/* Go to load BOOT partition directly in non-secure boot */
+		char bp_name[32] = {0};
+		
+		strcat(bp_name, BOOT_PARTITION);
+		strcat(bp_name, slot_name_suffix);
+		prepare_partition_data(bp_name);
+	}
+
+	return res;
+}
+
+U_BOOT_CMD(
+	bootandroid, 2,	1, do_bootandroid,
+	"bootandroid   - boot android bootimg from device\n",
+	"mmc0 | mmc1 | mmc2 | mmcX]\n    "
+	"- boot application image stored in storage device like mmc\n"
+);
+

cmd/booti.c

@@ -119,15 +119,18 @@ U_BOOT_CMD(
 
 #endif
 
-#if CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_VAL_A) || CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_VAL_B) || CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_ANT_REF)
+#if CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_VAL_A) || CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_VAL_B) || CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_ANT_REF) || CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_LPI4A)
+#if CONFIG_IS_ENABLED(LIGHT_SEC_UPGRADE)
 extern int light_secboot(int argc, char * const argv[]);
+#endif
 int do_secboot(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
+#if CONFIG_IS_ENABLED(LIGHT_SEC_UPGRADE)
     if (light_secboot(argc, argv) != 0) {
         run_command("reset", 0);
         return -1;
     }
-
+#endif
 	return 0;
 }
 U_BOOT_CMD(

cmd/mmc.c

@@ -574,6 +574,7 @@ static int do_mmc_rescan(cmd_tbl_t *cmdtp, int flag,
 }
 
 extern volatile uint32_t DELAY_LANE;
+extern volatile int manual_set_delay ;
 static int do_mmc_set_delay_lane(cmd_tbl_t *cmdtp, int flag,
 	       int argc, char * const argv[])
 {
@@ -587,17 +588,22 @@ static int do_mmc_set_delay_lane(cmd_tbl_t *cmdtp, int flag,
 	mmc = find_mmc_device(curr_device);
 	if (!mmc) {
 		printf("no mmc device at slot %x\n", curr_device);
-		return CMD_RET_FAILURE;
+		goto RET_FAILURE;
 	}
-
+	manual_set_delay = 1;
 	if (0 != snps_mmc_init(mmc))
-		return CMD_RET_FAILURE;
+		goto RET_FAILURE;
 
 	mmc = init_mmc_device(curr_device, true);
 	if (!mmc)
-		return CMD_RET_FAILURE;
-
+		goto RET_FAILURE;
+	
+	manual_set_delay = 0;
 	return CMD_RET_SUCCESS;
+
+RET_FAILURE:
+	manual_set_delay = 0;
+	return CMD_RET_FAILURE;
 }
 
 static int do_mmc_turning(cmd_tbl_t *cmdtp, int flag,
@@ -605,6 +611,10 @@ static int do_mmc_turning(cmd_tbl_t *cmdtp, int flag,
 {
 	struct mmc *mmc;
 	int i = 0, n;
+	int stop_on_ok = 1;
+	if(argc > 1 && (!strncmp(argv[1],"cont",4))){
+		stop_on_ok = 0;
+	}
 	for(i = 0; i <= 128; i++) {
 		DELAY_LANE = i;
 		printf("set DELAY_LANE = %d\n", DELAY_LANE);
@@ -616,8 +626,10 @@ static int do_mmc_turning(cmd_tbl_t *cmdtp, int flag,
 			return CMD_RET_FAILURE;
 		}
 
+		manual_set_delay = 1;
 		if (0 != snps_mmc_init(mmc)) {
 			printf("Error: mmc init error!\n");
+			manual_set_delay = 0;
 			return CMD_RET_FAILURE;
 		}
 
@@ -628,18 +640,21 @@ static int do_mmc_turning(cmd_tbl_t *cmdtp, int flag,
 
 		if (mmc_getwp(mmc) == 1) {
 			printf("Error: card is write protected!\n");
+			manual_set_delay = 0;
 			return CMD_RET_FAILURE;
 		}
 
 		n = blk_dwrite(mmc_get_blk_desc(mmc), 0, 1, 0);
 		if (n == 1) {
 			printf("blocks written: %s\n", "OK" );
-			return CMD_RET_SUCCESS;
+			manual_set_delay = 0;
+			if(stop_on_ok)
+				return CMD_RET_SUCCESS;
 		} else {
 			printf("written: %s\n", "error");
 		}
 	}
-
+	manual_set_delay = 0;
 	if (i > 128) {
 		return CMD_RET_FAILURE;
 	}
@@ -1239,9 +1254,10 @@ U_BOOT_CMD(
 #endif
 	"mmc erase blk# cnt\n"
 	"mmc rescan\n"
-	"mmc set_delay # val\n"
-	"mmc turning\n"
-	"mmc memset addr # lenght\n"
+	"mmc set_delay # val - set clk out delay mannaul,reinit host and rescan dev\n"
+	"mmc turning [continue] - loop test for clk delay form 0 to 128, reinit host and rescan dev\n"
+	"             - without arg [continue] exit once init and write ok\n"
+	"mmc memset addr # length - set mem addr 0xff with length  '# length' \n"
 	"mmc part - lists available partition on current mmc device\n"
 	"mmc dev [dev] [part] - show or set current mmc device [partition]\n"
 	"mmc list - lists available devices\n"

common/avb_verify.c

@@ -14,6 +14,48 @@
 #include <tee.h>
 #include <tee/optee_ta_avb.h>
 
+#ifdef CONFIG_AVB_ROLLBACK_ENABLE
+extern int sec_write_rollback_index(size_t rollback_index_slot, uint64_t rollback_index);
+extern int sec_read_rollback_index(size_t rollback_index_slot, uint64_t *out_rollback_index);
+#endif
+
+#if defined (CONFIG_AVB_USE_OEM_KEY)
+static const unsigned char avb_root_oem_pub[520] = {
+	0x00,0x00,0x08,0x00,0x11,0x70,0xEA,0xC9,0xC2,0xAD,0x66,0x2A,0x57,0x2A,0x89,0x68,
+	0x8B,0x40,0x33,0xF2,0xEA,0x22,0xD7,0x3E,0x31,0x5F,0x9D,0xB8,0xD1,0x16,0x5C,0x22,
+	0xC3,0xFE,0xE6,0x35,0x3F,0x96,0x6D,0xD8,0x1A,0x11,0xE9,0x53,0x90,0x88,0xA9,0xCE,
+	0xA7,0x33,0xB2,0x16,0x60,0x18,0xBE,0x23,0xCC,0x5C,0xAB,0x29,0x0E,0x7B,0x35,0x16,
+	0xB0,0x59,0x3A,0x2F,0x62,0xF1,0x9B,0x39,0x0A,0x21,0x00,0xFE,0x75,0xEB,0x00,0xDF,
+	0x17,0xAF,0x44,0x11,0x42,0x4E,0x4C,0x7C,0xA6,0xDC,0xC5,0xAD,0xB3,0x7C,0xC3,0xB1,
+	0x52,0xAD,0x0C,0xEF,0x73,0x69,0x7E,0xFC,0xF9,0x12,0xA7,0x5C,0x60,0x47,0xEF,0x8F,
+	0xC7,0x9D,0xD9,0x62,0xF5,0x0E,0x62,0xBB,0x3E,0x80,0x23,0xFA,0x19,0x4C,0x0A,0xD6,
+	0xE0,0xA7,0x0E,0x65,0xEA,0xD5,0xB8,0xA9,0xF2,0xA3,0xDA,0x18,0xBE,0x5D,0x4B,0x37,
+	0x91,0xBA,0xDB,0x0D,0x50,0x7E,0xEE,0x52,0xDF,0x90,0xE6,0xFC,0x8F,0xB8,0x24,0x2A,
+	0x2B,0xBE,0xA6,0xC9,0x5B,0x89,0x3E,0xE8,0x24,0xBD,0x6A,0x03,0x31,0x6C,0xFC,0x4A,
+	0xBA,0x6B,0xEE,0x08,0xAE,0x33,0x6E,0xC0,0x64,0x87,0xC1,0x35,0x65,0x42,0x34,0xE5,
+	0xF8,0x3B,0x82,0x36,0xE9,0xFA,0x23,0xD7,0x12,0xC5,0x7B,0x27,0x16,0xB0,0xC7,0x40,
+	0x5A,0xA4,0x8A,0x56,0xA4,0x54,0x0F,0xD9,0xA7,0x25,0x25,0xE3,0x7F,0x72,0x6E,0x4B,
+	0x63,0x1B,0x05,0xFE,0x4E,0x1F,0x1D,0x05,0xDD,0x91,0xA7,0xBF,0xA4,0x90,0xDA,0x7D,
+	0x0F,0xB6,0xFC,0x5D,0x8E,0xFB,0xE2,0xF7,0x5F,0x76,0xFA,0xD5,0x12,0xEC,0x87,0xD6,
+	0x07,0xA0,0xAC,0xB6,0xE6,0xBA,0xB0,0x87,0xBA,0x51,0xD7,0x6C,0x19,0xC0,0x2C,0xA5,
+	0x2C,0x08,0x52,0x2A,0x63,0x18,0x10,0x94,0xEA,0x5C,0x13,0xBF,0x42,0x8E,0x12,0xB6,
+	0x7D,0x34,0xD9,0x1C,0x42,0xBC,0xCE,0x44,0x8A,0x13,0x5B,0x93,0x6F,0x34,0x41,0xA1,
+	0xA3,0xD3,0x2E,0xF4,0xD3,0x28,0xAD,0x8F,0x8B,0x89,0x9D,0x42,0x43,0xD6,0xBF,0xDE,
+	0x9F,0xBD,0x32,0x06,0xE3,0x67,0xD3,0x14,0x2F,0x4C,0xE7,0x6B,0x9A,0xD9,0x04,0xFA,
+	0x4B,0x46,0x88,0xE7,0x04,0xAA,0x56,0xFF,0xBF,0x89,0x1D,0xFD,0x32,0xDF,0x47,0xC0,
+	0x34,0x0D,0x25,0x8C,0xF6,0xE1,0x5E,0xA9,0x3C,0x30,0x3A,0x53,0x0C,0xDB,0xAD,0x8E,
+	0x01,0xCB,0x46,0xE0,0xF5,0x97,0x2D,0xB8,0xF8,0x29,0xC3,0x19,0x4C,0x05,0x8B,0x74,
+	0xE0,0xA6,0x3B,0x3C,0x96,0x4F,0x91,0x74,0x62,0xAA,0x50,0x0F,0x11,0x30,0x59,0xAE,
+	0x7A,0x80,0xD3,0xAC,0xB3,0xDB,0x24,0x3A,0x79,0xD4,0xDB,0x79,0x10,0x63,0x27,0xD0,
+	0x6B,0xF9,0xA3,0xF4,0x27,0x24,0x89,0x0C,0xAC,0x31,0x15,0x08,0x10,0x59,0x08,0x2D,
+	0x00,0x3D,0xD8,0xD6,0x3B,0x91,0xC8,0x55,0xCF,0x28,0x3A,0xFB,0xD7,0xF7,0xF7,0x9D,
+	0x41,0xBD,0x3E,0xD1,0x77,0xA3,0xF6,0xFA,0x33,0x05,0x5A,0x36,0xCE,0xB9,0x02,0x12,
+	0x10,0xEB,0xCA,0xA7,0x3C,0xC8,0x5D,0xCD,0x33,0xD9,0xFA,0x16,0xD4,0x52,0x12,0xB6,
+	0x35,0xD5,0x84,0x53,0xC4,0x21,0xDC,0x72,0x2F,0xF9,0x1E,0x59,0x0A,0xCD,0x7D,0x89,
+	0xD4,0xCF,0x8E,0x2E,0x09,0x36,0xF5,0x12,0x35,0x43,0x64,0x6C,0xD1,0x70,0xBF,0x67,
+	0x3A,0x54,0x72,0x84,0xF3,0xF1,0x4A,0x6A
+};
+#else
 static const unsigned char avb_root_pub[1032] = {
 	0x0, 0x0, 0x10, 0x0, 0x55, 0xd9, 0x4, 0xad, 0xd8, 0x4,
 	0xaf, 0xe3, 0xd3, 0x84, 0x6c, 0x7e, 0xd, 0x89, 0x3d, 0xc2,
@@ -120,7 +162,7 @@ static const unsigned char avb_root_pub[1032] = {
 	0xe1, 0x74, 0xa1, 0xa3, 0x99, 0xa0, 0x85, 0x9e, 0xf1, 0xac,
 	0xd8, 0x7e,
 };
-
+#endif
 /**
  * ============================================================================
  * Boot states support (GREEN, YELLOW, ORANGE, RED) and dm_verity
@@ -590,6 +632,19 @@ static AvbIOResult validate_vbmeta_public_key(AvbOps *ops,
 					      public_key_metadata_length,
 					      bool *out_key_is_trusted)
 {
+#if defined (CONFIG_AVB_USE_OEM_KEY)
+	if (!public_key_length || !public_key_data || !out_key_is_trusted)
+		return AVB_IO_RESULT_ERROR_IO;
+
+	*out_key_is_trusted = false;
+	if (public_key_length != sizeof(avb_root_oem_pub))
+		return AVB_IO_RESULT_ERROR_IO;
+
+	if (memcmp(avb_root_oem_pub, public_key_data, public_key_length) == 0)
+		*out_key_is_trusted = true;
+	
+	return AVB_IO_RESULT_OK;
+#else
 	if (!public_key_length || !public_key_data || !out_key_is_trusted)
 		return AVB_IO_RESULT_ERROR_IO;
 
@@ -601,6 +656,7 @@ static AvbIOResult validate_vbmeta_public_key(AvbOps *ops,
 		*out_key_is_trusted = true;
 
 	return AVB_IO_RESULT_OK;
+#endif
 }
 
 #ifdef CONFIG_OPTEE_TA_AVB
@@ -681,8 +737,15 @@ static AvbIOResult read_rollback_index(AvbOps *ops,
 				       size_t rollback_index_slot,
 				       u64 *out_rollback_index)
 {
+#ifdef CONFIG_AVB_ROLLBACK_ENABLE
+    if (sec_read_rollback_index(rollback_index_slot, out_rollback_index) != 0) {
+        return AVB_IO_RESULT_ERROR_IO;
+    }
+
+	return AVB_IO_RESULT_OK;
+#else
 #ifndef CONFIG_OPTEE_TA_AVB
-	/* For now we always return 0 as the stored rollback index. */
+    /* For now we always return 0 as the stored rollback index. */
 	printf("%s not supported yet\n", __func__);
 
 	if (out_rollback_index)
@@ -708,8 +771,10 @@ static AvbIOResult read_rollback_index(AvbOps *ops,
 
 	*out_rollback_index = (u64)param[1].u.value.a << 32 |
 			      (u32)param[1].u.value.b;
+
 	return AVB_IO_RESULT_OK;
 #endif
+#endif
 }
 
 /**
@@ -727,6 +792,13 @@ static AvbIOResult write_rollback_index(AvbOps *ops,
 					size_t rollback_index_slot,
 					u64 rollback_index)
 {
+#ifdef CONFIG_AVB_ROLLBACK_ENABLE
+    if (sec_write_rollback_index(rollback_index_slot, rollback_index) != 0) {
+        return AVB_IO_RESULT_ERROR_IO;
+    }
+    
+	return AVB_IO_RESULT_OK;
+#else
 #ifndef CONFIG_OPTEE_TA_AVB
 	/* For now this is a no-op. */
 	printf("%s not supported yet\n", __func__);
@@ -748,6 +820,7 @@ static AvbIOResult write_rollback_index(AvbOps *ops,
 	return invoke_func(ops->user_data, TA_AVB_CMD_WRITE_ROLLBACK_INDEX,
 			   ARRAY_SIZE(param), param);
 #endif
+#endif
 }
 
 /**

common/splash.c

@@ -71,7 +71,7 @@ static int splash_video_logo_load(void)
 		return -EFAULT;
 	}
 
-	memcpy((void *)bmp_load_addr, bmp_logo_bitmap,
+	memcpy((void *)(u64)bmp_load_addr, bmp_logo_bitmap,
 	       ARRAY_SIZE(bmp_logo_bitmap));
 
 	return 0;

configs/light_a_val_android_defconfig

@@ -0,0 +1,115 @@
+CONFIG_RISCV=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_ENV_SIZE=0x20000
+CONFIG_ENV_OFFSET=0xe0000
+CONFIG_NR_DRAM_BANKS=8
+CONFIG_SPL=y
+CONFIG_SMP=y
+CONFIG_TARGET_LIGHT_C910=y
+CONFIG_ARCH_RV64I=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_BUILD_TARGET="u-boot-with-spl.bin"
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_DISPLAY_BOARDINFO=y
+# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
+CONFIG_SPL_RAM_SUPPORT=y
+CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SYS_PROMPT="C910 Light# "
+CONFIG_DDR_LP4X_3733_SINGLERANK=y
+# CONFIG_DDR_LP4_3733_DUALRANK is not set
+CONFIG_DDR_BOARD_CONFIG=y
+CONFIG_CMD_BOOT_SLAVE=y
+CONFIG_CMD_ERASEENV=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_DDR_SCAN=y
+CONFIG_DDR_PRBS_TEST=n
+# CONFIG_DOS_PARTITION is not set
+# CONFIG_ISO_PARTITION is not set
+CONFIG_PARTITION_TYPE_GUID=y
+CONFIG_OF_EMBED=y
+CONFIG_DEFAULT_DEVICE_TREE="light-a-val"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SPL_CLK=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_UDP_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x10000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_DW=y
+CONFIG_DWAPB_GPIO=y
+# CONFIG_MMC_SPI is not set
+CONFIG_MMC_VERBOSE=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_SNPS=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SNPS=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MMC_RPMB=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_SPI_NAND=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_PHY_REALTEK=y
+CONFIG_RTL8211E_PINE64_GIGABIT_FIX=y
+CONFIG_RTL8211X_PHY_FORCE_MASTER=y
+CONFIG_RTL8211F_PHY_FORCE_EEE_RXC_ON=y
+CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_DESIGNWARE_SPI=y
+CONFIG_DESIGNWARE_QSPI=y
+CONFIG_USB=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="U-Boot-THEAD"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1234
+CONFIG_USB_GADGET_PRODUCT_NUM=0x8888
+# CONFIG_SPL_USE_TINY_PRINTF is not set
+# CONFIG_EFI_LOADER is not set
+# CONFIG_LIGHT_SEC_BOOT_WITH_VERIFY_VAL_A=y
+# CONFIG_LIGHT_SEC_UPGRADE=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_DM_VIDEO=y
+CONFIG_PHY=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_CMD_BMP=y
+CONFIG_VIDEO_BRIDGE=y
+CONFIG_DM_PCA953X=y
+CONFIG_VIDEO_VS_DPU=y
+CONFIG_VIDEO_LCD_ILITEK_ILI9881C=y
+CONFIG_VIDEO_DW_DSI_LIGHT=y
+CONFIG_VIDEO_DW_DPHY=y
+CONFIG_VIDEO_DW_DSI_HOST=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_PMIC_VOL_INIT=y
+CONFIG_DDR_REGU_0V6=600000
+CONFIG_DDR_REGU_0V8=800000
+CONFIG_DDR_REGU_1V1=1100000
+CONFIG_LIGHT_ANDROID_BOOT_IMAGE_VAL_A=y
+# CONFIG_AVB_USE_OEM_KEY is not set
+# CONFIG_AVB_ROLLBACK_ENABLE is not set
+# CONFIG_AVB_HW_ENGINE_ENABLE is not set
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_LIBAVB=y
+CONFIG_AVB_VERIFY=y
+CONFIG_CMD_AVB=y
+CONFIG_CMD_BOOTANDROID=y
+CONFIG_ANDROID_AB=y
+CONFIG_CMD_AB_SELECT=y
+CONFIG_XBC=y

configs/light_a_val_defconfig

@@ -83,7 +83,7 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x1234
 CONFIG_USB_GADGET_PRODUCT_NUM=0x8888
 # CONFIG_SPL_USE_TINY_PRINTF is not set
 # CONFIG_EFI_LOADER is not set
-# CONFIG_LIGHT_SEC_BOOT is not set
+# CONFIG_LIGHT_BOOT_FORCE_SEQ is not set
 CONFIG_BOARD_LATE_INIT=y
 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
 CONFIG_DM_VIDEO=y

configs/light_a_val_sec_defconfig

@@ -82,6 +82,7 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0x8888
 # CONFIG_EFI_LOADER is not set
 CONFIG_LIGHT_SEC_BOOT_WITH_VERIFY_VAL_A=y
 CONFIG_LIGHT_SEC_UPGRADE=y
+# CONFIG_LIGHT_BOOT_FORCE_SEQ is not set
 CONFIG_BOARD_LATE_INIT=y
 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
 CONFIG_DM_VIDEO=y

configs/light_ant_ref_defconfig

@@ -82,7 +82,8 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x1234
 CONFIG_USB_GADGET_PRODUCT_NUM=0x8888
 # CONFIG_SPL_USE_TINY_PRINTF is not set
 # CONFIG_EFI_LOADER is not set
-# CONFIG_LIGHT_SEC_BOOT is not set
+CONFIG_LIGHT_SEC_BOOT_WITH_VERIFY_ANT_REF=y
+CONFIG_LIGHT_SEC_UPGRADE=y
 CONFIG_BOARD_LATE_INIT=y
 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
 CONFIG_DM_VIDEO=y

configs/light_b_product_android_defconfig

@@ -0,0 +1,117 @@
+CONFIG_RISCV=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_ENV_SIZE=0x20000
+CONFIG_ENV_OFFSET=0xe0000
+CONFIG_NR_DRAM_BANKS=8
+CONFIG_SPL=y
+CONFIG_SMP=y
+CONFIG_TARGET_LIGHT_C910=y
+CONFIG_TARGET_LIGHT_FM_C910_VAL_B=y
+CONFIG_ARCH_RV64I=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_BUILD_TARGET="u-boot-with-spl.bin"
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_DISPLAY_BOARDINFO=y
+# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
+CONFIG_SPL_RAM_SUPPORT=y
+CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SYS_PROMPT="C910 Light# "
+CONFIG_DDR_LP4X_3200_SINGLERANK=y
+CONFIG_DDR_H32_MODE=y
+# CONFIG_DDR_LP4_3733_DUALRANK is not set
+CONFIG_DDR_BOARD_CONFIG=y
+CONFIG_CMD_BOOT_SLAVE=y
+CONFIG_CMD_ERASEENV=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_TIME=y
+CONFIG_DDR_SCAN=y
+CONFIG_DDR_PRBS_TEST=n
+# CONFIG_DOS_PARTITION is not set
+# CONFIG_ISO_PARTITION is not set
+CONFIG_PARTITION_TYPE_GUID=y
+CONFIG_OF_EMBED=y
+CONFIG_DEFAULT_DEVICE_TREE="light-b-product"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SPL_CLK=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_UDP_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x10000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_DW=y
+CONFIG_DWAPB_GPIO=y
+# CONFIG_MMC_SPI is not set
+CONFIG_MMC_VERBOSE=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_SNPS=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SNPS=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MMC_RPMB=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_SPI_NAND=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_PHY_REALTEK=y
+CONFIG_RTL8211E_PINE64_GIGABIT_FIX=y
+CONFIG_RTL8211X_PHY_FORCE_MASTER=y
+CONFIG_RTL8211F_PHY_FORCE_EEE_RXC_ON=y
+CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_DESIGNWARE_SPI=y
+CONFIG_DESIGNWARE_QSPI=y
+CONFIG_USB=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="U-Boot-THEAD"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1234
+CONFIG_USB_GADGET_PRODUCT_NUM=0x8888
+# CONFIG_SPL_USE_TINY_PRINTF is not set
+# CONFIG_EFI_LOADER is not set
+# CONFIG_LIGHT_SEC_BOOT_WITH_VERIFY_VAL_A=y
+# CONFIG_LIGHT_SEC_UPGRADE=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_DM_VIDEO=y
+CONFIG_PHY=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_CMD_BMP=y
+CONFIG_VIDEO_BRIDGE=y
+CONFIG_DM_PCA953X=y
+CONFIG_VIDEO_VS_DPU=y
+CONFIG_VIDEO_LCD_ILITEK_ILI9881C=y
+CONFIG_VIDEO_DW_DSI_LIGHT=y
+CONFIG_VIDEO_DW_DPHY=y
+CONFIG_VIDEO_DW_DSI_HOST=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_SYS_TEXT_BASE=0x7b000000
+CONFIG_PMIC_VOL_INIT=y
+CONFIG_DDR_REGU_0V6=600000
+CONFIG_DDR_REGU_0V8=800000
+CONFIG_DDR_REGU_1V1=1100000
+CONFIG_LIGHT_ANDROID_BOOT_IMAGE_VAL_B=y
+CONFIG_AVB_USE_OEM_KEY=y
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_LIBAVB=y
+CONFIG_AVB_VERIFY=y
+CONFIG_CMD_AVB=y
+CONFIG_CMD_BOOTANDROID=y
+CONFIG_ANDROID_AB=y
+CONFIG_CMD_AB_SELECT=y
+CONFIG_XBC=y

configs/light_beagle_android_defconfig

@@ -0,0 +1,111 @@
+CONFIG_RISCV=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_ENV_SIZE=0x20000
+CONFIG_ENV_OFFSET=0xe0000
+CONFIG_NR_DRAM_BANKS=8
+CONFIG_SPL=y
+CONFIG_SMP=y
+CONFIG_TARGET_LIGHT_C910=y
+CONFIG_TARGET_LIGHT_FM_C910_BEAGLE=y
+CONFIG_ARCH_RV64I=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_BUILD_TARGET="u-boot-with-spl.bin"
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_DISPLAY_BOARDINFO=y
+# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
+CONFIG_SPL_RAM_SUPPORT=y
+CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SYS_PROMPT="C910 Light# "
+CONFIG_DDR_LP4X_3733_SINGLERANK=y
+# CONFIG_DDR_LP4_3733_DUALRANK is not set
+CONFIG_DDR_BOARD_CONFIG=y
+CONFIG_CMD_BOOT_SLAVE=y
+CONFIG_CMD_ERASEENV=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_DDR_SCAN=y
+CONFIG_DDR_PRBS_TEST=n
+# CONFIG_DOS_PARTITION is not set
+# CONFIG_ISO_PARTITION is not set
+CONFIG_PARTITION_TYPE_GUID=y
+CONFIG_OF_EMBED=y
+CONFIG_DEFAULT_DEVICE_TREE="light-a-val"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SPL_CLK=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_UDP_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x10000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_DW=y
+CONFIG_DWAPB_GPIO=y
+# CONFIG_MMC_SPI is not set
+CONFIG_MMC_VERBOSE=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_SNPS=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SNPS=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MMC_RPMB=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_SPI_NAND=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_PHY_REALTEK=y
+CONFIG_RTL8211E_PINE64_GIGABIT_FIX=y
+CONFIG_RTL8211X_PHY_FORCE_MASTER=y
+CONFIG_RTL8211F_PHY_FORCE_EEE_RXC_ON=y
+CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_DESIGNWARE_SPI=y
+CONFIG_DESIGNWARE_QSPI=y
+CONFIG_USB=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="U-Boot-THEAD"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1234
+CONFIG_USB_GADGET_PRODUCT_NUM=0x8888
+# CONFIG_SPL_USE_TINY_PRINTF is not set
+# CONFIG_EFI_LOADER is not set
+# CONFIG_LIGHT_SEC_BOOT is not set
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_DM_VIDEO=y
+CONFIG_PHY=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_CMD_BMP=y
+CONFIG_VIDEO_BRIDGE=y
+CONFIG_DM_PCA953X=y
+CONFIG_VIDEO_VS_DPU=y
+CONFIG_VIDEO_LCD_ILITEK_ILI9881C=y
+CONFIG_VIDEO_DW_DSI_LIGHT=y
+CONFIG_VIDEO_DW_DPHY=y
+CONFIG_VIDEO_DW_DSI_HOST=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_PMIC_VOL_INIT=y
+CONFIG_DDR_REGU_0V6=600000
+CONFIG_DDR_REGU_0V8=800000
+CONFIG_DDR_REGU_1V1=1100000
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_LIBAVB=y
+CONFIG_AVB_VERIFY=y
+CONFIG_CMD_AVB=y
+CONFIG_CMD_BOOTANDROID=y
+CONFIG_ANDROID_AB=y
+CONFIG_CMD_AB_SELECT=y
+CONFIG_XBC=y

configs/light_lpi4a_android_defconfig

@@ -0,0 +1,111 @@
+CONFIG_RISCV=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_ENV_SIZE=0x20000
+CONFIG_ENV_OFFSET=0xe0000
+CONFIG_NR_DRAM_BANKS=8
+CONFIG_SPL=y
+CONFIG_SMP=y
+CONFIG_TARGET_LIGHT_C910=y
+CONFIG_TARGET_LIGHT_FM_C910_LPI4A=y
+CONFIG_ARCH_RV64I=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_BUILD_TARGET="u-boot-with-spl.bin"
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_DISPLAY_BOARDINFO=y
+# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
+CONFIG_SPL_RAM_SUPPORT=y
+CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SYS_PROMPT="C910 Light# "
+CONFIG_DDR_LP4X_3733_DUALRANK=y
+# CONFIG_DDR_LP4_3733_DUALRANK is not set
+CONFIG_DDR_BOARD_CONFIG=y
+CONFIG_CMD_BOOT_SLAVE=y
+CONFIG_CMD_ERASEENV=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_DDR_SCAN=y
+CONFIG_DDR_PRBS_TEST=n
+# CONFIG_DOS_PARTITION is not set
+# CONFIG_ISO_PARTITION is not set
+CONFIG_PARTITION_TYPE_GUID=y
+CONFIG_OF_EMBED=y
+CONFIG_DEFAULT_DEVICE_TREE="light-lpi4a"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SPL_CLK=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_UDP_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x10000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_DW=y
+CONFIG_DWAPB_GPIO=y
+# CONFIG_MMC_SPI is not set
+CONFIG_MMC_VERBOSE=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_SNPS=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SNPS=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MMC_RPMB=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_SPI_NAND=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_PHY_REALTEK=y
+CONFIG_RTL8211E_PINE64_GIGABIT_FIX=y
+CONFIG_RTL8211X_PHY_FORCE_MASTER=y
+CONFIG_RTL8211F_PHY_FORCE_EEE_RXC_ON=y
+CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_DESIGNWARE_SPI=y
+CONFIG_DESIGNWARE_QSPI=y
+CONFIG_USB=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="U-Boot-THEAD"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1234
+CONFIG_USB_GADGET_PRODUCT_NUM=0x8888
+# CONFIG_SPL_USE_TINY_PRINTF is not set
+# CONFIG_EFI_LOADER is not set
+# CONFIG_LIGHT_SEC_BOOT is not set
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_DM_VIDEO=y
+CONFIG_PHY=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_CMD_BMP=y
+CONFIG_VIDEO_BRIDGE=y
+CONFIG_DM_PCA953X=y
+CONFIG_VIDEO_VS_DPU=y
+CONFIG_VIDEO_LCD_ILITEK_ILI9881C=y
+CONFIG_VIDEO_DW_DSI_LIGHT=y
+CONFIG_VIDEO_DW_DPHY=y
+CONFIG_VIDEO_DW_DSI_HOST=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_PMIC_VOL_INIT=y
+CONFIG_DDR_REGU_0V6=600000
+CONFIG_DDR_REGU_0V8=800000
+CONFIG_DDR_REGU_1V1=1100000
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_LIBAVB=y
+CONFIG_AVB_VERIFY=y
+CONFIG_CMD_AVB=y
+CONFIG_CMD_BOOTANDROID=y
+CONFIG_ANDROID_AB=y
+CONFIG_CMD_AB_SELECT=y
+CONFIG_XBC=y

configs/light_lpi4a_defconfig

@@ -0,0 +1,107 @@
+CONFIG_RISCV=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_ENV_SIZE=0x20000
+CONFIG_ENV_OFFSET=0xe0000
+CONFIG_NR_DRAM_BANKS=8
+CONFIG_SPL=y
+CONFIG_SMP=y
+CONFIG_TARGET_LIGHT_C910=y
+CONFIG_TARGET_LIGHT_FM_C910_LPI4A=y
+# CONFIG_THEAD_PLIC is not set
+# CONFIG_THEAD_LIGHT_TIMER is not set
+# CONFIG_THEAD_LIGHT_DIGITAL_SENSOR is not set
+CONFIG_ARCH_RV64I=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_BUILD_TARGET="u-boot-with-spl.bin"
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_DISPLAY_BOARDINFO=y
+# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
+CONFIG_SPL_RAM_SUPPORT=y
+CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SYS_PROMPT="C910 Light# "
+CONFIG_DDR_LP4X_3733_DUALRANK=y
+# CONFIG_DDR_LP4_3733_DUALRANK is not set
+CONFIG_DDR_BOARD_CONFIG=y
+CONFIG_CMD_BOOT_SLAVE=y
+CONFIG_CMD_ERASEENV=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_DDR_SCAN=y
+CONFIG_DDR_PRBS_TEST=n
+# CONFIG_DOS_PARTITION is not set
+# CONFIG_ISO_PARTITION is not set
+CONFIG_PARTITION_TYPE_GUID=y
+CONFIG_OF_EMBED=y
+CONFIG_DEFAULT_DEVICE_TREE="light-lpi4a"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SPL_CLK=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_UDP_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x10000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_DW=y
+CONFIG_DWAPB_GPIO=y
+# CONFIG_MMC_SPI is not set
+CONFIG_MMC_VERBOSE=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_SNPS=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SNPS=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MMC_RPMB=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_SPI_NAND=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_PHY_REALTEK=y
+CONFIG_RTL8211E_PINE64_GIGABIT_FIX=y
+CONFIG_RTL8211X_PHY_FORCE_MASTER=y
+CONFIG_RTL8211F_PHY_FORCE_EEE_RXC_ON=y
+CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_DESIGNWARE_SPI=y
+CONFIG_DESIGNWARE_QSPI=y
+CONFIG_USB=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="U-Boot-THEAD"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1234
+CONFIG_USB_GADGET_PRODUCT_NUM=0x8888
+# CONFIG_SPL_USE_TINY_PRINTF is not set
+# CONFIG_EFI_LOADER is not set
+# CONFIG_LIGHT_SEC_BOOT is not set
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_DM_VIDEO=y
+CONFIG_PHY=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_CMD_BMP=y
+CONFIG_VIDEO_BRIDGE=y
+CONFIG_DM_PCA953X=y
+CONFIG_VIDEO_VS_DPU=y
+CONFIG_VIDEO_LCD_ILITEK_ILI9881C=y
+CONFIG_VIDEO_LCD_CUSTOM_LOGO=y
+CONFIG_VIDEO_DW_DSI_LIGHT=y
+CONFIG_VIDEO_DW_DPHY=y
+CONFIG_VIDEO_DW_DSI_HOST=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_PMIC_VOL_INIT=y
+CONFIG_DDR_REGU_0V6=600000
+CONFIG_DDR_REGU_0V8=800000
+CONFIG_DDR_REGU_1V1=1100000

configs/light_lpi4a_sec_defconfig

@@ -0,0 +1,108 @@
+CONFIG_RISCV=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_ENV_SIZE=0x20000
+CONFIG_ENV_OFFSET=0xe0000
+CONFIG_NR_DRAM_BANKS=8
+CONFIG_SPL=y
+CONFIG_SMP=y
+CONFIG_TARGET_LIGHT_C910=y
+CONFIG_TARGET_LIGHT_FM_C910_LPI4A=y
+# CONFIG_THEAD_PLIC is not set
+# CONFIG_THEAD_LIGHT_TIMER is not set
+# CONFIG_THEAD_LIGHT_DIGITAL_SENSOR is not set
+CONFIG_ARCH_RV64I=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_BUILD_TARGET="u-boot-with-spl.bin"
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_DISPLAY_BOARDINFO=y
+# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
+CONFIG_SPL_RAM_SUPPORT=y
+CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SYS_PROMPT="C910 Light# "
+CONFIG_DDR_LP4X_3733_DUALRANK=y
+# CONFIG_DDR_LP4_3733_DUALRANK is not set
+CONFIG_DDR_BOARD_CONFIG=y
+CONFIG_CMD_BOOT_SLAVE=y
+CONFIG_CMD_ERASEENV=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_DDR_SCAN=y
+CONFIG_DDR_PRBS_TEST=n
+# CONFIG_DOS_PARTITION is not set
+# CONFIG_ISO_PARTITION is not set
+CONFIG_PARTITION_TYPE_GUID=y
+CONFIG_OF_EMBED=y
+CONFIG_DEFAULT_DEVICE_TREE="light-lpi4a"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SPL_CLK=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_UDP_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x10000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_DW=y
+CONFIG_DWAPB_GPIO=y
+# CONFIG_MMC_SPI is not set
+CONFIG_MMC_VERBOSE=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_SNPS=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SNPS=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MMC_RPMB=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_SPI_NAND=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_PHY_REALTEK=y
+CONFIG_RTL8211E_PINE64_GIGABIT_FIX=y
+CONFIG_RTL8211X_PHY_FORCE_MASTER=y
+CONFIG_RTL8211F_PHY_FORCE_EEE_RXC_ON=y
+CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_DESIGNWARE_SPI=y
+CONFIG_DESIGNWARE_QSPI=y
+CONFIG_USB=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="U-Boot-THEAD"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1234
+CONFIG_USB_GADGET_PRODUCT_NUM=0x8888
+# CONFIG_SPL_USE_TINY_PRINTF is not set
+# CONFIG_EFI_LOADER is not set
+CONFIG_LIGHT_SEC_BOOT_WITH_VERIFY_LPI4A=y
+CONFIG_LIGHT_SEC_UPGRADE=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_DM_VIDEO=y
+CONFIG_PHY=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_CMD_BMP=y
+CONFIG_VIDEO_BRIDGE=y
+CONFIG_DM_PCA953X=y
+CONFIG_VIDEO_VS_DPU=y
+CONFIG_VIDEO_LCD_ILITEK_ILI9881C=y
+CONFIG_VIDEO_LCD_CUSTOM_LOGO=y
+CONFIG_VIDEO_DW_DSI_LIGHT=y
+CONFIG_VIDEO_DW_DPHY=y
+CONFIG_VIDEO_DW_DSI_HOST=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_PMIC_VOL_INIT=y
+CONFIG_DDR_REGU_0V6=600000
+CONFIG_DDR_REGU_0V8=800000
+CONFIG_DDR_REGU_1V1=1100000

configs/light_lpi4a_singlerank_defconfig

@@ -0,0 +1,106 @@
+CONFIG_RISCV=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_ENV_SIZE=0x20000
+CONFIG_ENV_OFFSET=0xe0000
+CONFIG_NR_DRAM_BANKS=8
+CONFIG_SPL=y
+CONFIG_SMP=y
+CONFIG_TARGET_LIGHT_C910=y
+CONFIG_TARGET_LIGHT_FM_C910_LPI4A=y
+# CONFIG_THEAD_PLIC is not set
+# CONFIG_THEAD_LIGHT_TIMER is not set
+# CONFIG_THEAD_LIGHT_DIGITAL_SENSOR is not set
+CONFIG_ARCH_RV64I=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_BUILD_TARGET="u-boot-with-spl.bin"
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_DISPLAY_BOARDINFO=y
+# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
+CONFIG_SPL_RAM_SUPPORT=y
+CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SYS_PROMPT="C910 Light# "
+CONFIG_DDR_LP4X_3733_SINGLERANK=y
+# CONFIG_DDR_LP4_3733_DUALRANK is not set
+CONFIG_DDR_BOARD_CONFIG=y
+CONFIG_CMD_BOOT_SLAVE=y
+CONFIG_CMD_ERASEENV=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_DDR_SCAN=y
+CONFIG_DDR_PRBS_TEST=n
+# CONFIG_DOS_PARTITION is not set
+# CONFIG_ISO_PARTITION is not set
+CONFIG_PARTITION_TYPE_GUID=y
+CONFIG_OF_EMBED=y
+CONFIG_DEFAULT_DEVICE_TREE="light-lpi4a"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SPL_CLK=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_UDP_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x10000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_DW=y
+CONFIG_DWAPB_GPIO=y
+# CONFIG_MMC_SPI is not set
+CONFIG_MMC_VERBOSE=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_SNPS=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SNPS=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MMC_RPMB=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_SPI_NAND=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_PHY_REALTEK=y
+CONFIG_RTL8211E_PINE64_GIGABIT_FIX=y
+CONFIG_RTL8211X_PHY_FORCE_MASTER=y
+CONFIG_RTL8211F_PHY_FORCE_EEE_RXC_ON=y
+CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_DESIGNWARE_SPI=y
+CONFIG_DESIGNWARE_QSPI=y
+CONFIG_USB=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="U-Boot-THEAD"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1234
+CONFIG_USB_GADGET_PRODUCT_NUM=0x8888
+# CONFIG_SPL_USE_TINY_PRINTF is not set
+# CONFIG_EFI_LOADER is not set
+# CONFIG_LIGHT_SEC_BOOT is not set
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_DM_VIDEO=y
+CONFIG_PHY=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_CMD_BMP=y
+CONFIG_VIDEO_BRIDGE=y
+CONFIG_DM_PCA953X=y
+CONFIG_VIDEO_VS_DPU=y
+CONFIG_VIDEO_LCD_ILITEK_ILI9881C=y
+CONFIG_VIDEO_DW_DSI_LIGHT=y
+CONFIG_VIDEO_DW_DPHY=y
+CONFIG_VIDEO_DW_DSI_HOST=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_PMIC_VOL_INIT=y
+CONFIG_DDR_REGU_0V6=600000
+CONFIG_DDR_REGU_0V8=800000
+CONFIG_DDR_REGU_1V1=1100000

drivers/fastboot/Kconfig

@@ -2,7 +2,7 @@ menu "Fastboot support"
 
 config FASTBOOT
 	bool
-	imply ANDROID_BOOT_IMAGE
+	# imply ANDROID_BOOT_IMAGE
 	imply CMD_FASTBOOT
 
 config USB_FUNCTION_FASTBOOT

drivers/fastboot/fb_common.c

@@ -118,7 +118,11 @@ void fastboot_boot(void)
 #ifdef THEAD_LIGHT_FASTBOOT
 	char cmdbuf[32];
 
+#ifdef CONFIG_ANDROID_BOOT_IMAGE
+	sprintf(cmdbuf, "run bootcmd");
+#else
 	sprintf(cmdbuf, "bootslave; run set_bootargs; booti %s - %s", LIGHT_KERNEL_ADDR_CMD, LIGHT_DTB_ADDR_CMD);
+#endif
 	printf("fastboot bootcmd %s\n", cmdbuf);
 	run_command(cmdbuf, 0);
 

drivers/fastboot/fb_getvar.c

@@ -13,6 +13,7 @@
 #include <version.h>
 
 static void getvar_version(char *var_parameter, char *response);
+static void getvar_dynamic_partition(char *var_parameter, char *response);
 static void getvar_version_bootloader(char *var_parameter, char *response);
 static void getvar_downloadsize(char *var_parameter, char *response);
 static void getvar_serialno(char *var_parameter, char *response);
@@ -41,6 +42,9 @@ static const struct {
 	}, {
 		.variable = "version-bootloader",
 		.dispatch = getvar_version_bootloader
+	}, {
+		.variable = "dynamic-partition",
+		.dispatch = getvar_dynamic_partition
 	}, {
 		.variable = "downloadsize",
 		.dispatch = getvar_downloadsize
@@ -134,6 +138,17 @@ static void getvar_version_bootloader(char *var_parameter, char *response)
 	fastboot_okay(U_BOOT_VERSION, response);
 }
 
+static void getvar_dynamic_partition(char *var_parameter, char *response)
+{
+	char *part_name="super";
+
+	int r = getvar_get_part_info(part_name, response, NULL);
+	if (r >= 0)
+		fastboot_okay("true", response); /* part exists */
+	else
+		fastboot_okay("false", response);
+}
+
 static void getvar_downloadsize(char *var_parameter, char *response)
 {
 	fastboot_response("OKAY", response, "0x%08x", fastboot_buf_size);
@@ -247,7 +262,11 @@ static void getvar_partition_size(char *part_name, char *response)
 
 static void getvar_is_userspace(char *var_parameter, char *response)
 {
+#ifdef CONFIG_ANDROID_BOOT_IMAGE
+	fastboot_okay("yes", response);
+#else
 	fastboot_okay("no", response);
+#endif
 }
 
 /**

drivers/mmc/sdhci.c

@@ -136,9 +136,9 @@ static void sdhci_prepare_dma(struct sdhci_host *host, struct mmc_data *data,
 	unsigned char ctrl;
 
 	if (data->flags == MMC_DATA_READ)
-		host->start_addr = (dma_addr_t)data->dest;
+		host->start_addr = (dma_addr_t)(u64)data->dest;
 	else
-		host->start_addr = (dma_addr_t)data->src;
+		host->start_addr = (dma_addr_t)(u64)data->src;
 
 	ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
 	ctrl &= ~SDHCI_CTRL_DMA_MASK;

drivers/mmc/snps_sdhci.c

@@ -13,6 +13,7 @@
 #define HS400_DELAY_LANE	24
 
 volatile int DELAY_LANE = 50;
+volatile int manual_set_delay = 0;  //flag for cmd manual setted DELAY_LANE,non-zero is setted. auto clear in cmd
 
 static void sdhci_phy_1_8v_init_no_pull(struct sdhci_host *host)
 {
@@ -154,10 +155,14 @@ void snps_set_uhs_timing(struct sdhci_host *host)
 {
 	struct mmc *mmc = (struct mmc *)host->mmc;
 	u32 reg;
-
+	int restore_delay;
 	reg = sdhci_readw(host, SDHCI_HOST_CONTROL2);
 	reg &= ~SDHCI_CTRL_UHS_MASK;
-
+    
+	if(manual_set_delay){
+		DELAY_LANE = DELAY_LANE & 0x7f; /*limit bit[0:6]*/
+		printf("%s: manual set delay (%d) active \n",host->name,DELAY_LANE);
+	}
 	switch (mmc->selected_mode) {
 	case UHS_SDR50:
 	case MMC_HS_52:
@@ -175,9 +180,13 @@ void snps_set_uhs_timing(struct sdhci_host *host)
 		reg |= SDHCI_CTRL_UHS_SDR104;
 		break;
 	case MMC_HS_400:
-		DELAY_LANE = HS400_DELAY_LANE;
+		restore_delay = DELAY_LANE;
+		if(!manual_set_delay){  /*default not set manual in cmd,when set in cmd,use DELAY_LANE set in cmd*/
+			 DELAY_LANE = HS400_DELAY_LANE;
+		}
 		sdhci_phy_1_8v_init(host);
 		reg |= SNPS_SDHCI_CTRL_HS400;
+		DELAY_LANE = restore_delay; /*restore for other modes*/
 		break;
 	default:
 		sdhci_phy_3_3v_init(host);
@@ -345,7 +354,10 @@ static int snps_sdhci_probe(struct udevice *dev)
 		ret = max_clk;
 		goto err;
 	}
-
+	//get Maximum Base Clock frequency from dts clock-frequency
+	if(0 == dev_read_u32(dev, "clock-frequency", &max_clk)){
+		host->max_clk = max_clk;
+	}
 	host->mmc = &plat->mmc;
 	host->mmc->dev = dev;
 	host->mmc->priv = host;

drivers/net/designware.c

@@ -508,7 +508,7 @@ static int dw_phy_init(struct dw_eth_dev *priv, void *dev)
 {
 	struct phy_device *phydev;
 	int phy_addr = -1, ret;
-
+	
 #ifdef CONFIG_PHY_ADDR
 	phy_addr = CONFIG_PHY_ADDR;
 #endif
@@ -801,13 +801,16 @@ int designware_eth_probe(struct udevice *dev)
 		err = ret;
 		goto mdio_err;
 	}
-
+#ifdef GMAC_USE_FIRST_MII_BUS
 	if (!g_mii_bus) {
 		priv->bus = miiphy_get_dev_by_name(dev->name);
 		g_mii_bus = priv->bus;
 	} else {
 		priv->bus = g_mii_bus;
 	}
+#else
+	priv->bus = miiphy_get_dev_by_name(dev->name);
+#endif
 	ret = dw_phy_init(priv, dev);
 	debug("%s, ret=%d\n", __func__, ret);
 	if (!ret)
@@ -815,8 +818,18 @@ int designware_eth_probe(struct udevice *dev)
 
 	/* continue here for cleanup if no PHY found */
 	err = ret;
+#ifdef GMAC_USE_FIRST_MII_BUS
+	struct mii_dev *t_mii = NULL;
+	t_mii = miiphy_get_dev_by_name(dev->name);
+	if((g_mii_bus != t_mii) && (t_mii != NULL) ){
+		printf("free mdio bus %s\n",t_mii->name);
+		mdio_unregister(t_mii);
+		mdio_free(t_mii);
+	}
+#else
 	mdio_unregister(priv->bus);
 	mdio_free(priv->bus);
+#endif
 mdio_err:
 
 #ifdef CONFIG_CLK

drivers/usb/dwc3/ep0.c

@@ -905,7 +905,10 @@ static void dwc3_ep0_xfer_complete(struct dwc3 *dwc,
 	dep->flags &= ~DWC3_EP_BUSY;
 	dep->resource_index = 0;
 	dwc->setup_packet_pending = false;
-	invalid_dcache_range(dwc->ctrl_req, (dmaaddr_t)dwc->ctrl_req + ROUND(sizeof(*dwc->ctrl_req), CACHELINE_SIZE));
+#ifdef CONFIG_TARGET_LIGHT_C910
+	extern void invalid_dcache_range(unsigned long start, unsigned long end);
+	invalid_dcache_range((unsigned long)dwc->ctrl_req, (dmaaddr_t)dwc->ctrl_req + ROUND(sizeof(*dwc->ctrl_req), CACHELINE_SIZE));
+#endif
 
 	switch (dwc->ep0state) {
 	case EP0_SETUP_PHASE:

drivers/video/Kconfig

@@ -351,6 +351,11 @@ config VIDEO_LCD_ILITEK_ILI9881C
 	Say Y here if you want to enable support for ILITEK ILI9881C
 	800x1280 DSI video mode panel.
 
+config VIDEO_LCD_CUSTOM_LOGO
+	bool "LCD CUSTOM logo support"
+	help
+	Say Y here if you want to enable support for custom logo.
+
 config VIDEO_LCD_SSD2828
 	bool "SSD2828 bridge chip"
 	default n

include/asm/arch

@@ -0,0 +1 @@
+/home/cxx194832/ssd/u-boot/arch/riscv/include/asm/arch-c9xx

include/configs/light-c910.h

@@ -22,7 +22,11 @@
 
 #define CONFIG_SYS_INIT_SP_ADDR     (CONFIG_SYS_TEXT_BASE + SZ_1M)
 #define CONFIG_SYS_LOAD_ADDR        (CONFIG_SYS_TEXT_BASE + SZ_1M)
+#ifdef CONFIG_ANDROID_BOOT_IMAGE
+#define CONFIG_SYS_MALLOC_LEN       (128*SZ_1M)
+#else
 #define CONFIG_SYS_MALLOC_LEN       SZ_1M
+#endif
 #define CONFIG_SYS_BOOTM_LEN        SZ_64M
 #define CONFIG_SYS_CACHELINE_SIZE   64
 
@@ -35,6 +39,7 @@
 #define CONFIG_RGMII            1
 #define CONFIG_PHY_MARVELL      1
 #define CONFIG_NET_RETRY_COUNT  20
+#define GMAC_USE_FIRST_MII_BUS
 
 #define CONFIG_SYS_FLASH_BASE       0x0
 #define CONFIG_SYS_MAX_FLASH_BANKS  1
@@ -57,14 +62,14 @@
 #define THEAD_LIGHT_FASTBOOT	1
 #define LIGHT_FW_ADDR		0x0
 #define LIGHT_KERNEL_ADDR	0x200000
-#define LIGHT_DTB_ADDR		0x1f00000
+#define LIGHT_DTB_ADDR		0x2800000
 #define LIGHT_ROOTFS_ADDR	0x2000000
 #define LIGHT_AON_FW_ADDR	0xffffef8000
 #define LIGHT_TEE_FW_ADDR	0x1c000000
 #define LIGHT_TF_FW_ADDR	LIGHT_FW_ADDR
 #define LIGHT_TF_FW_TMP_ADDR	0x100000
 #define LIGHT_KERNEL_ADDR_CMD	"0x200000"
-#define LIGHT_DTB_ADDR_CMD	"0x1f00000"
+#define LIGHT_DTB_ADDR_CMD	"0x2800000"
 
 
 /* trust image name string */
@@ -91,6 +96,14 @@
 #define TEE_SEC_UPGRADE_FLAG 0x5a5aa5a5
 #define UBOOT_SEC_UPGRADE_FLAG	0xa5a5aa55
 
+/* Define secure debug log level */
+#define LOG_LEVEL	1
+#if defined (LOG_LEVEL)
+#define SECLOG_PRINT	printf
+#else
+#define SECLOG_PRINT
+#endif
+
 #define UBOOT_MAX_VER		64
 #define CONFIG_SYS_CBSIZE 	512
 #define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
@@ -100,7 +113,7 @@
 /* List of different env in debug/release version  */
 #if defined (U_BUILD_DEBUG)
 #define ENV_KERNEL_LOGLEVEL "kernel_loglevel=7\0"
-#define ENV_STR_BOOT_DELAY  
+#define ENV_STR_BOOT_DELAY
 #else
 #define ENV_KERNEL_LOGLEVEL "kernel_loglevel=4\0"
 #define ENV_STR_BOOT_DELAY	"bootdelay=0\0"
@@ -108,87 +121,170 @@
 
 #if defined (CONFIG_LIGHT_SEC_BOOT_WITH_VERIFY_VAL_A)
 #define CONFIG_EXTRA_ENV_SETTINGS \
+	"splashimage=0x30000000\0" \
+	"splashpos=m,m\0" \
 	"fdt_high=0xffffffffffffffff\0" \
 	"tf_addr=0x100000\0" \
-	"dtb_addr=0x01f00000\0" \
+	"dtb_addr=0x02800000\0" \
 	"kernel_addr=0x00200000\0" \
 	"aon_ram_addr=0xffffef8000\0" \
-	"audio_ram_addr=0xffc0000000\0" \
+	"audio_ram_addr=0x32000000\0" \
 	"fwaddr=0x10000000\0"\
 	"tee_addr=0x1c000000\0" \
 	"sec_upgrade_mode=0\0"\
 	"mmcdev=0\0" \
 	"mmcpart=6\0" \
-	"kdump_buf=1M\0" \
+	"mmcbootpart=2\0" \
+	ENV_KERNEL_LOGLEVEL \
+	"kdump_buf=180M\0" \
+	ENV_STR_BOOT_DELAY \
 	"uboot_version=0x0000000000000000\0"\
+	"tee_version=0x00000000\0"\
+	"tf_version=0x00000000\0"\
 	"fdt_file=light-a-val-sec.dtb\0" \
 	"uuid_rootfs=80a5a8e9-c744-491a-93c1-4f4194fd690b\0" \
-	"partitions=name=table,size=2031KB;name=boot,size=200MiB,type=boot;name=tf,size=50MiB,type=boot;name=tee,size=50MiB,type=boot;name=stash,size=50MiB,type=boot;name=root,size=4000MiB,type=linux,uuid=${uuid_rootfs};name=data,size=-,type=linux\0" \
+	"partitions=name=table,size=2031KB;name=boot,size=200MiB,type=boot;name=tf,size=50MiB,type=boot;name=tee,size=50MiB,type=boot;name=stash,size=50MiB,type=boot;name=root,size=-,type=linux,uuid=${uuid_rootfs}\0" \
 	"finduuid=part uuid mmc ${mmcdev}:${mmcpart} uuid\0" \
 	"gpt_partition=gpt write mmc ${mmcdev} $partitions\0" \
-	"set_bootargs=setenv bootargs console=ttyS0,115200 root=PARTUUID=${uuid} rootfstype=ext4 rdinit=/sbin/init rootwait rw earlycon clk_ignore_unused loglevel=7 eth=$ethaddr rootrwreset=${factory_reset} crashkernel=${kdump_buf}\0" \
-	"load_aon=ext4load mmc 0:2 $fwaddr light_aon_fpga.bin;cp.b $fwaddr $aon_ram_addr $filesize\0"\
-	"load_c906_audio=ext4load mmc 0:2 $fwaddr light_c906_audio.bin;cp.b $fwaddr $audio_ram_addr $filesize\0"\
-	"bootcmd_load=run load_aon;run load_c906_audio; ext4load mmc 0:3 $tf_addr trust_firmware.bin; ext4load mmc 0:4 $tee_addr tee.bin;ext4load mmc 0:2 $dtb_addr ${fdt_file}; ext4load mmc 0:2 $kernel_addr Image\0" \
+	"set_bootargs=setenv bootargs console=ttyS0,115200 root=PARTUUID=${uuid} rootfstype=ext4 rdinit=/sbin/init rootwait rw earlycon clk_ignore_unused loglevel=${kernel_loglevel} eth=$ethaddr crashkernel=${kdump_buf}\0" \
+	"load_aon=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_aon_fpga.bin;cp.b $fwaddr $aon_ram_addr $filesize\0"\
+	"load_c906_audio=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_c906_audio.bin;cp.b $fwaddr $audio_ram_addr $filesize\0"\
+	"bootcmd_load=run load_aon;run load_c906_audio; ext4load mmc 0:3 $tf_addr trust_firmware.bin; ext4load mmc 0:4 $tee_addr tee.bin;ext4load mmc ${mmcdev}:${mmcbootpart} $dtb_addr ${fdt_file}; ext4load mmc ${mmcdev}:${mmcbootpart} $kernel_addr Image\0" \
 	"bootcmd=run bootcmd_load; bootslave; run finduuid; run set_bootargs; secboot; booti $kernel_addr - $dtb_addr;\0" \
-	"factory_reset=yes\0"\
         "\0"
 
 #elif defined (CONFIG_LIGHT_SEC_BOOT_WITH_VERIFY_VAL_B)
 #define CONFIG_EXTRA_ENV_SETTINGS \
+	"splashimage=0x30000000\0" \
+	"splashpos=m,m\0" \
 	"fdt_high=0xffffffffffffffff\0" \
 	"tf_addr=0x100000\0" \
-	"dtb_addr=0x01f00000\0" \
+	"dtb_addr=0x02800000\0" \
 	"kernel_addr=0x00200000\0" \
 	"aon_ram_addr=0xffffef8000\0" \
-	"audio_ram_addr=0xffc0000000\0" \
+	"audio_ram_addr=0x32000000\0" \
 	"fwaddr=0x10000000\0"\
 	"tee_addr=0x1c000000\0" \
 	"sec_upgrade_mode=0\0"\
 	"mmcdev=0\0" \
 	"mmcpart=6\0" \
-	"kdump_buf=1M\0" \
+	"mmcbootpart=2\0" \
+	ENV_KERNEL_LOGLEVEL \
+	"kdump_buf=180M\0" \
+	ENV_STR_BOOT_DELAY \
 	"uboot_version=0x0000000000000000\0"\
+	"tee_version=0x00000000\0"\
+	"tf_version=0x00000000\0"\
 	"fdt_file=light-b-product-sec.dtb\0" \
 	"uuid_rootfs=80a5a8e9-c744-491a-93c1-4f4194fd690b\0" \
-	"partitions=name=table,size=2031KB;name=boot,size=200MiB,type=boot;name=tf,size=50MiB,type=boot;name=tee,size=50MiB,type=boot;name=stash,size=50MiB,type=boot;name=root,size=4000MiB,type=linux,uuid=${uuid_rootfs};name=data,size=-,type=linux\0" \
+	"partitions=name=table,size=2031KB;name=boot,size=200MiB,type=boot;name=tf,size=50MiB,type=boot;name=tee,size=50MiB,type=boot;name=stash,size=50MiB,type=boot;name=root,size=-,type=linux,uuid=${uuid_rootfs}\0" \
 	"finduuid=part uuid mmc ${mmcdev}:${mmcpart} uuid\0" \
 	"gpt_partition=gpt write mmc ${mmcdev} $partitions\0" \
-	"set_bootargs=setenv bootargs console=ttyS0,115200 root=PARTUUID=${uuid} rootfstype=ext4 rdinit=/sbin/init rootwait rw earlycon clk_ignore_unused loglevel=7 eth=$ethaddr rootrwreset=${factory_reset} crashkernel=${kdump_buf}\0" \
-	"load_aon=ext4load mmc 0:2 $fwaddr light_aon_fpga.bin;cp.b $fwaddr $aon_ram_addr $filesize\0"\
-	"load_c906_audio=ext4load mmc 0:2 $fwaddr light_c906_audio.bin;cp.b $fwaddr $audio_ram_addr $filesize\0"\
-	"bootcmd_load=run load_aon;run load_c906_audio; ext4load mmc 0:3 $tf_addr trust_firmware.bin; ext4load mmc 0:4 $tee_addr tee.bin;ext4load mmc 0:2 $dtb_addr ${fdt_file}; ext4load mmc 0:2 $kernel_addr Image\0" \
+	"set_bootargs=setenv bootargs console=ttyS0,115200 root=PARTUUID=${uuid} rootfstype=ext4 rdinit=/sbin/init rootwait rw earlycon clk_ignore_unused loglevel=${kernel_loglevel} eth=$ethaddr crashkernel=${kdump_buf}\0" \
+	"load_aon=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_aon_fpga.bin;cp.b $fwaddr $aon_ram_addr $filesize\0"\
+	"load_c906_audio=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_c906_audio.bin;cp.b $fwaddr $audio_ram_addr $filesize\0"\
+	"bootcmd_load=run load_aon;run load_c906_audio; ext4load mmc 0:3 $tf_addr trust_firmware.bin; ext4load mmc 0:4 $tee_addr tee.bin;ext4load mmc ${mmcdev}:${mmcbootpart} $dtb_addr ${fdt_file}; ext4load mmc ${mmcdev}:${mmcbootpart} $kernel_addr Image\0" \
 	"bootcmd=run bootcmd_load; bootslave; run finduuid; run set_bootargs; secboot; booti $kernel_addr - $dtb_addr;\0" \
-	"factory_reset=yes\0"\
         "\0"
 
 #elif defined (CONFIG_LIGHT_SEC_BOOT_WITH_VERIFY_ANT_REF)
 #define CONFIG_EXTRA_ENV_SETTINGS \
+	"splashimage=0x30000000\0" \
+	"splashpos=m,m\0" \
 	"fdt_high=0xffffffffffffffff\0" \
 	"tf_addr=0x100000\0" \
-	"dtb_addr=0x01f00000\0" \
+	"dtb_addr=0x02800000\0" \
 	"kernel_addr=0x00200000\0" \
 	"aon_ram_addr=0xffffef8000\0" \
-	"audio_ram_addr=0xffc0000000\0" \
+	"audio_ram_addr=0x32000000\0" \
 	"fwaddr=0x10000000\0"\
 	"tee_addr=0x1c000000\0" \
 	"sec_upgrade_mode=0\0"\
 	"mmcdev=0\0" \
 	"mmcpart=6\0" \
-	"kdump_buf=1M\0" \
+	"mmcbootpart=2\0" \
+	ENV_KERNEL_LOGLEVEL \
+	"kdump_buf=180M\0" \
+	ENV_STR_BOOT_DELAY \
 	"uboot_version=0x0000000000000000\0"\
+	"tee_version=0x00000000\0"\
+	"tf_version=0x00000000\0"\
 	"fdt_file=light-ant-ref-sec.dtb\0" \
 	"uuid_rootfs=80a5a8e9-c744-491a-93c1-4f4194fd690b\0" \
-	"partitions=name=table,size=2031KB;name=boot,size=200MiB,type=boot;name=tf,size=50MiB,type=boot;name=tee,size=50MiB,type=boot;name=stash,size=50MiB,type=boot;name=root,size=4000MiB,type=linux,uuid=${uuid_rootfs};name=data,size=-,type=linux\0" \
+	"partitions=name=table,size=2031KB;name=boot,size=200MiB,type=boot;name=tf,size=50MiB,type=boot;name=tee,size=50MiB,type=boot;name=stash,size=50MiB,type=boot;name=root,size=-,type=linux,uuid=${uuid_rootfs}\0" \
 	"finduuid=part uuid mmc ${mmcdev}:${mmcpart} uuid\0" \
 	"gpt_partition=gpt write mmc ${mmcdev} $partitions\0" \
-	"set_bootargs=setenv bootargs console=ttyS0,115200 root=PARTUUID=${uuid} rootfstype=ext4 rdinit=/sbin/init rootwait rw earlycon clk_ignore_unused loglevel=7 eth=$ethaddr rootrwreset=${factory_reset} crashkernel=${kdump_buf}\0" \
+	"set_bootargs=setenv bootargs console=ttyS0,115200 root=PARTUUID=${uuid} rootfstype=ext4 rdinit=/sbin/init rootwait rw earlycon clk_ignore_unused loglevel=${kernel_loglevel} eth=$ethaddr crashkernel=${kdump_buf}\0" \
+	"load_aon=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_aon_fpga.bin;cp.b $fwaddr $aon_ram_addr $filesize\0"\
+	"load_c906_audio=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_c906_audio.bin;cp.b $fwaddr $audio_ram_addr $filesize\0"\
+	"bootcmd_load=run load_aon;run load_c906_audio; ext4load mmc 0:3 $tf_addr trust_firmware.bin; ext4load mmc 0:4 $tee_addr tee.bin;ext4load mmc ${mmcdev}:${mmcbootpart} $dtb_addr ${fdt_file}; ext4load mmc ${mmcdev}:${mmcbootpart} $kernel_addr Image\0" \
+	"bootcmd=run bootcmd_load; bootslave; run finduuid; run set_bootargs; secboot; booti $kernel_addr - $dtb_addr;\0" \
+        "\0"
+
+#elif defined (CONFIG_LIGHT_SEC_BOOT_WITH_VERIFY_LPI4A)
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"splashimage=0x30000000\0" \
+	"splashpos=m,m\0" \
+	"fdt_high=0xffffffffffffffff\0" \
+	"tf_addr=0x100000\0" \
+	"dtb_addr=0x02800000\0" \
+	"kernel_addr=0x00200000\0" \
+	"aon_ram_addr=0xffffef8000\0" \
+	"audio_ram_addr=0x32000000\0" \
+	"fwaddr=0x10000000\0"\
+	"tee_addr=0x1c000000\0" \
+	"sec_upgrade_mode=0\0"\
+	"mmcdev=0\0" \
+	"mmcpart=6\0" \
+	"mmcbootpart=2\0" \
+	ENV_KERNEL_LOGLEVEL \
+	"kdump_buf=180M\0" \
+	ENV_STR_BOOT_DELAY \
+	"uboot_version=0x0000000000000000\0"\
+	"tee_version=0x00000000\0"\
+	"tf_version=0x00000000\0"\
+	"fdt_file=light-lpi4a-sec.dtb\0" \
+	"uuid_rootfs=80a5a8e9-c744-491a-93c1-4f4194fd690b\0" \
+	"partitions=name=table,size=2031KB;name=boot,size=200MiB,type=boot;name=tf,size=50MiB,type=boot;name=tee,size=50MiB,type=boot;name=stash,size=50MiB,type=boot;name=root,size=-,type=linux,uuid=${uuid_rootfs}\0" \
+	"finduuid=part uuid mmc ${mmcdev}:${mmcpart} uuid\0" \
+	"gpt_partition=gpt write mmc ${mmcdev} $partitions\0" \
+	"set_bootargs=setenv bootargs console=ttyS0,115200 root=PARTUUID=${uuid} rootfstype=ext4 rdinit=/sbin/init rootwait rw earlycon clk_ignore_unused loglevel=${kernel_loglevel} eth=$ethaddr crashkernel=${kdump_buf}\0" \
+	"load_aon=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_aon_fpga.bin;cp.b $fwaddr $aon_ram_addr $filesize\0"\
+	"load_c906_audio=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_c906_audio.bin;cp.b $fwaddr $audio_ram_addr $filesize\0"\
+	"bootcmd_load=run load_aon;run load_c906_audio; ext4load mmc 0:3 $tf_addr trust_firmware.bin; ext4load mmc 0:4 $tee_addr tee.bin;ext4load mmc ${mmcdev}:${mmcbootpart} $dtb_addr ${fdt_file}; ext4load mmc ${mmcdev}:${mmcbootpart} $kernel_addr Image\0" \
+	"bootcmd=run bootcmd_load; bootslave; run finduuid; run set_bootargs; secboot; booti $kernel_addr - $dtb_addr;\0" \
+        "\0"
+
+#elif defined(CONFIG_LIGHT_ANDROID_BOOT_IMAGE_VAL_A) || defined(CONFIG_LIGHT_ANDROID_BOOT_IMAGE_VAL_B)
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"splashimage=0x30000000\0" \
+	"splashpos=m,m\0" \
+	"fdt_high=0xffffffffffffffff\0" \
+	"serial#=1234567890\0" \
+	"tf_addr=0x100000\0" \
+	"tee_addr=0x1c000000\0" \
+	"opensbi_addr=0x0\0" \
+	"dtb_addr=0x01f00000\0" \
+	"kernel_addr=0x00200000\0" \
+	"ramdisk_addr=0x02000000\0" \
+	"aon_ram_addr=0xffffef8000\0" \
+	"audio_ram_addr=0x32000000\0" \
+	"fwaddr=0x10000000\0"\
+	"boot_ab=_a\0"\
+	"mmcdev=0\0" \
+	"mmcpart=3\0" \
+	"fdt_file=light-val.dtb\0" \
+	"uuid_rootfs=80a5a8e9-c744-491a-93c1-4f4194fd690b\0" \
+	"partitions=name=sparse,size=2031kb;name=bootpart,size=8MiB;name=boot_a,size=32MiB;name=boot_b,size=32MiB;name=vendor_boot_a,size=32MiB;name=vendor_boot_b,size=32MiB;name=tee_a,size=32MiB;name=tee_b,size=32MiB;name=dtbo_a,size=8MiB;name=dtbo_b,size=8MiB;name=super,size=4096MiB;name=vbmeta_a,size=1MiB;name=vbmeta_b,size=1MiB;name=vbmeta_system_a,size=1MiB;name=vbmeta_system_b,size=1MiB;name=recovery,size=16MiB;name=misc,size=2MiB;name=metadata,size=16MiB;name=userdata,size=-\0" \
+	"finduuid=part uuid mmc ${mmcdev}:${mmcpart} uuid\0" \
+	"gpt_partition=gpt write mmc ${mmcdev} $partitions\0" \
+	"set_bootargs=setenv bootargs console=ttyS0,115200 earlycon clk_ignore_unused loop.max_part=7 loglevel=7 init=/init bootconfig video=HDMI-A-1:800x600-32@60 firmware_class.path=/vendor/firmware\0" \
 	"load_aon=ext4load mmc 0:2 $fwaddr light_aon_fpga.bin;cp.b $fwaddr $aon_ram_addr $filesize\0"\
 	"load_c906_audio=ext4load mmc 0:2 $fwaddr light_c906_audio.bin;cp.b $fwaddr $audio_ram_addr $filesize\0"\
-	"bootcmd_load=run load_aon;run load_c906_audio; ext4load mmc 0:3 $tf_addr trust_firmware.bin; ext4load mmc 0:4 $tee_addr tee.bin;ext4load mmc 0:2 $dtb_addr ${fdt_file}; ext4load mmc 0:2 $kernel_addr Image\0" \
-	"bootcmd=run bootcmd_load; bootslave; run finduuid; run set_bootargs; secboot; booti $kernel_addr - $dtb_addr;\0" \
-	"factory_reset=yes\0"\
-        "\0"
+	"sec_m_load=ext4load mmc 0:2 $opensbi_addr fw_dynamic.bin\0"\
+	"bootcmd_load=run load_aon;run load_c906_audio;secimg_load;run sec_m_load;bootandroid\0" \
+	"bootcmd=run bootcmd_load; bootslave; run finduuid; run set_bootargs; bootm $kernel_addr $ramdisk_addr:$ramdisk_size $dtb_addr;\0" \
+         "\0"
 
 #else
 #if defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_A)
@@ -197,25 +293,27 @@
 	"splashpos=m,m\0" \
 	"fdt_high=0xffffffffffffffff\0" \
 	"opensbi_addr=0x0\0" \
-	"dtb_addr=0x01f00000\0" \
+	"dtb_addr=0x02800000\0" \
 	"kernel_addr=0x00200000\0" \
 	"aon_ram_addr=0xffffef8000\0" \
-	"audio_ram_addr=0xffc0000000\0" \
+	"audio_ram_addr=0x32000000\0" \
 	"fwaddr=0x10000000\0"\
 	"mmcdev=0\0" \
 	"mmcpart=3\0" \
-	"kdump_buf=1M\0" \
+	"mmcbootpart=2\0" \
+	ENV_KERNEL_LOGLEVEL \
+	"kdump_buf=180M\0" \
+	ENV_STR_BOOT_DELAY \
 	"fdt_file=light-a-product.dtb\0" \
 	"uuid_rootfs=80a5a8e9-c744-491a-93c1-4f4194fd690b\0" \
-	"partitions=name=table,size=2031KB;name=boot,size=200MiB,type=boot;name=root,size=4000MiB,type=linux,uuid=${uuid_rootfs};name=data,size=-,type=linux\0" \
+	"partitions=name=table,size=2031KB;name=boot,size=200MiB,type=boot;name=root,size=-,type=linux,uuid=${uuid_rootfs}\0" \
 	"finduuid=part uuid mmc ${mmcdev}:${mmcpart} uuid\0" \
 	"gpt_partition=gpt write mmc ${mmcdev} $partitions\0" \
-	"set_bootargs=setenv bootargs console=ttyS0,115200 root=PARTUUID=${uuid} rootfstype=ext4 rdinit=/sbin/init rootwait rw earlycon clk_ignore_unused loglevel=7 eth=$ethaddr rootrwreset=${factory_reset} crashkernel=${kdump_buf}\0" \
+	"set_bootargs=setenv bootargs console=ttyS0,115200 root=PARTUUID=${uuid} rootfstype=ext4 rdinit=/sbin/init rootwait rw earlycon clk_ignore_unused loglevel=${kernel_loglevel} eth=$ethaddr crashkernel=${kdump_buf}\0" \
 	"load_aon=ext4load mmc 0:2 $fwaddr light_aon_fpga.bin;cp.b $fwaddr $aon_ram_addr $filesize\0"\
 	"load_c906_audio=ext4load mmc 0:2 $fwaddr light_c906_audio.bin;cp.b $fwaddr $audio_ram_addr $filesize\0"\
 	"bootcmd_load=run load_aon;run load_c906_audio; ext4load mmc 0:2 $opensbi_addr fw_dynamic.bin; ext4load mmc 0:2 $dtb_addr ${fdt_file}; ext4load mmc 0:2 $kernel_addr Image\0" \
 	"bootcmd=run bootcmd_load; bootslave; run finduuid; run set_bootargs; booti $kernel_addr - $dtb_addr;\0" \
-	"factory_reset=yes\0"\
         "\0"
 #elif defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_B)
 #define CONFIG_EXTRA_ENV_SETTINGS \
@@ -223,30 +321,27 @@
 	"splashpos=m,m\0" \
 	"fdt_high=0xffffffffffffffff\0" \
 	"opensbi_addr=0x0\0" \
-	"dtb_addr=0x01f00000\0" \
+	"dtb_addr=0x02800000\0" \
 	"kernel_addr=0x00200000\0" \
 	"aon_ram_addr=0xffffef8000\0" \
-	"audio_ram_addr=0xffc0000000\0" \
+	"audio_ram_addr=0x32000000\0" \
 	"fwaddr=0x10000000\0"\
 	"mmcdev=0\0" \
-	"boot_partition=bootA\0" \
-	"root_partition=rootfsA\0" \
+	"mmcpart=3\0" \
+	"mmcbootpart=2\0" \
 	ENV_KERNEL_LOGLEVEL \
-	"kdump_buf=1M\0" \
+	"kdump_buf=180M\0" \
 	ENV_STR_BOOT_DELAY \
-	"findpart=rollback; if test ${boot_partition} = bootB; then mmcbootpart=4; else mmcbootpart=2; fi; if test ${root_partition} = rootfsB; then mmcpart=5; else mmcpart=3; fi;\0" \
-	"fdt_file=light-b-product.dtb\0" \
-	"uuid_rootfsA=80a5a8e9-c744-491a-93c1-4f4194fd690a\0" \
-	"uuid_rootfsB=80a5a8e9-c744-491a-93c1-4f4194fd690b\0" \
-	"partitions=name=table,size=2031KB;name=boot,size=200MiB,type=boot;name=root,size=4000MiB,type=linux,uuid=${uuid_rootfsA};name=bootB,size=200MiB,type=boot;name=rootB,size=4000MiB,type=linux,uuid=${uuid_rootfsB};name=data,size=-,type=linux\0" \
+	"fdt_file=light-b-audio-hdmi.dtb\0" \
+	"uuid_rootfs=80a5a8e9-c744-491a-93c1-4f4194fd690b\0" \
+	"partitions=name=table,size=2031KB;name=boot,size=200MiB,type=boot;name=root,size=-,type=linux,uuid=${uuid_rootfs}\0" \
 	"finduuid=part uuid mmc ${mmcdev}:${mmcpart} uuid\0" \
 	"gpt_partition=gpt write mmc ${mmcdev} $partitions\0" \
-	"set_bootargs=setenv bootargs console=ttyS0,115200 root=PARTUUID=${uuid} rootfstype=ext4 rdinit=/sbin/init rootwait rw earlycon clk_ignore_unused loglevel=${kernel_loglevel} eth=$ethaddr rootrw=PARTLABEL=data init=/init rootinit=/sbin/init rootrwoptions=rw,noatime rootrwreset=${factory_reset} crashkernel=${kdump_buf}\0" \
+	"set_bootargs=setenv bootargs console=ttyS0,115200 root=PARTUUID=${uuid} rootfstype=ext4 rdinit=/sbin/init rootwait rw earlycon clk_ignore_unused loglevel=${kernel_loglevel} eth=$ethaddr crashkernel=${kdump_buf}\0" \
 	"load_aon=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_aon_fpga.bin;cp.b $fwaddr $aon_ram_addr $filesize\0"\
 	"load_c906_audio=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_c906_audio.bin;cp.b $fwaddr $audio_ram_addr $filesize\0"\
-	"bootcmd_load=run findpart;run load_aon;run load_c906_audio; ext4load mmc ${mmcdev}:${mmcbootpart} $opensbi_addr fw_dynamic.bin; ext4load mmc ${mmcdev}:${mmcbootpart} $dtb_addr ${fdt_file};ext4load mmc ${mmcdev}:${mmcbootpart} $kernel_addr Image;\0" \
+	"bootcmd_load=run load_aon;run load_c906_audio; ext4load mmc ${mmcdev}:${mmcbootpart} $opensbi_addr fw_dynamic.bin; ext4load mmc ${mmcdev}:${mmcbootpart} $dtb_addr ${fdt_file};ext4load mmc ${mmcdev}:${mmcbootpart} $kernel_addr Image;\0" \
 	"bootcmd=run bootcmd_load; bootslave ; run finduuid; run set_bootargs; booti $kernel_addr - $dtb_addr;\0" \
-	"factory_reset=yes\0"\
         "\0"
 #elif defined (CONFIG_TARGET_LIGHT_FM_C910_B_REF)
 #define CONFIG_EXTRA_ENV_SETTINGS \
@@ -254,25 +349,26 @@
 	"splashpos=m,m\0" \
 	"fdt_high=0xffffffffffffffff\0" \
 	"opensbi_addr=0x0\0" \
-	"dtb_addr=0x01f00000\0" \
+	"dtb_addr=0x02800000\0" \
 	"kernel_addr=0x00200000\0" \
 	"aon_ram_addr=0xffffef8000\0" \
-	"audio_ram_addr=0xffc0000000\0" \
+	"audio_ram_addr=0x32000000\0" \
 	"fwaddr=0x10000000\0"\
 	"mmcdev=0\0" \
-	"boot_partition=bootA\0" \
-	"root_partition=rootfsA\0" \
-	"findpart=if test ${boot_partition} = bootB; then mmcbootpart=4; else mmcbootpart=2; fi; if test ${root_partition} = rootfsB; then mmcpart=5; else mmcpart=3; fi;\0" \
+	"mmcpart=3\0" \
+	"mmcbootpart=2\0" \
+	ENV_KERNEL_LOGLEVEL \
+	"kdump_buf=180M\0" \
+	ENV_STR_BOOT_DELAY \
 	"fdt_file=light-b-ref.dtb\0" \
-	"uuid_rootfsA=80a5a8e9-c744-491a-93c1-4f4194fd690a\0" \
-	"uuid_rootfsB=80a5a8e9-c744-491a-93c1-4f4194fd690b\0" \
-	"partitions=name=table,size=2031KB;name=boot,size=200MiB,type=boot;name=root,size=4000MiB,type=linux,uuid=${uuid_rootfsA};name=bootB,size=200MiB,type=boot;name=rootB,size=4000MiB,type=linux,uuid=${uuid_rootfsB};name=data,size=-,type=linux\0" \
+	"uuid_rootfs=80a5a8e9-c744-491a-93c1-4f4194fd690b\0" \
+	"partitions=name=table,size=2031KB;name=boot,size=200MiB,type=boot;name=root,size=-,type=linux,uuid=${uuid_rootfs}\0" \
 	"finduuid=part uuid mmc ${mmcdev}:${mmcpart} uuid\0" \
 	"gpt_partition=gpt write mmc ${mmcdev} $partitions\0" \
-	"set_bootargs=setenv bootargs console=ttyS0,115200 root=PARTUUID=${uuid} rootfstype=ext4 rdinit=/sbin/init rootwait rw earlycon clk_ignore_unused loglevel=7 eth=$ethaddr rootrw=PARTLABEL=data init=/init rootinit=/sbin/init rootrwoptions=rw,noatime\0" \
+	"set_bootargs=setenv bootargs console=ttyS0,115200 root=PARTUUID=${uuid} rootfstype=ext4 rdinit=/sbin/init rootwait rw earlycon clk_ignore_unused loglevel=${kernel_loglevel} eth=$ethaddr crashkernel=${kdump_buf}\0" \
 	"load_aon=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_aon_fpga.bin;cp.b $fwaddr $aon_ram_addr $filesize\0"\
 	"load_c906_audio=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_c906_audio.bin;cp.b $fwaddr $audio_ram_addr $filesize\0"\
-	"bootcmd_load=run findpart;run load_aon;run load_c906_audio; ext4load mmc ${mmcdev}:${mmcbootpart} $opensbi_addr fw_dynamic.bin; ext4load mmc ${mmcdev}:${mmcbootpart} $dtb_addr ${fdt_file};ext4load mmc ${mmcdev}:${mmcbootpart} $kernel_addr Image;\0" \
+	"bootcmd_load=run load_aon;run load_c906_audio; ext4load mmc ${mmcdev}:${mmcbootpart} $opensbi_addr fw_dynamic.bin; ext4load mmc ${mmcdev}:${mmcbootpart} $dtb_addr ${fdt_file};ext4load mmc ${mmcdev}:${mmcbootpart} $kernel_addr Image;\0" \
 	"bootcmd=run bootcmd_load; bootslave ; run finduuid; run set_bootargs; booti $kernel_addr - $dtb_addr;\0" \
         "\0"
 #elif defined (CONFIG_TARGET_LIGHT_FM_C910_B_POWER)
@@ -281,28 +377,27 @@
 	"splashpos=m,m\0" \
 	"fdt_high=0xffffffffffffffff\0" \
 	"opensbi_addr=0x0\0" \
-	"dtb_addr=0x01f00000\0" \
+	"dtb_addr=0x02800000\0" \
 	"kernel_addr=0x00200000\0" \
 	"aon_ram_addr=0xffffef8000\0" \
-	"audio_ram_addr=0xffc0000000\0" \
+	"audio_ram_addr=0x32000000\0" \
 	"fwaddr=0x10000000\0"\
 	"mmcdev=0\0" \
-	"boot_partition=bootA\0" \
-	"root_partition=rootfsA\0" \
-	"kdump_buf=1M\0" \
-	"findpart=rollback; if test ${boot_partition} = bootB; then mmcbootpart=4; else mmcbootpart=2; fi; if test ${root_partition} = rootfsB; then mmcpart=5; else mmcpart=3; fi;\0" \
+	"mmcpart=3\0" \
+	"mmcbootpart=2\0" \
+	ENV_KERNEL_LOGLEVEL \
+	"kdump_buf=180M\0" \
+	ENV_STR_BOOT_DELAY \
 	"fdt_file=light-b-power.dtb\0" \
-	"uuid_rootfsA=80a5a8e9-c744-491a-93c1-4f4194fd690a\0" \
-	"uuid_rootfsB=80a5a8e9-c744-491a-93c1-4f4194fd690b\0" \
-	"partitions=name=table,size=2031KB;name=boot,size=200MiB,type=boot;name=root,size=4000MiB,type=linux,uuid=${uuid_rootfsA};name=bootB,size=200MiB,type=boot;name=rootB,size=4000MiB,type=linux,uuid=${uuid_rootfsB};name=data,size=-,type=linux\0" \
+	"uuid_rootfs=80a5a8e9-c744-491a-93c1-4f4194fd690b\0" \
+	"partitions=name=table,size=2031KB;name=boot,size=200MiB,type=boot;name=root,size=-,type=linux,uuid=${uuid_rootfs}\0" \
 	"finduuid=part uuid mmc ${mmcdev}:${mmcpart} uuid\0" \
 	"gpt_partition=gpt write mmc ${mmcdev} $partitions\0" \
-	"set_bootargs=setenv bootargs console=ttyS0,115200 root=PARTUUID=${uuid} rootfstype=ext4 rdinit=/sbin/init rootwait rw earlycon clk_ignore_unused loglevel=7 eth=$ethaddr rootrw=PARTLABEL=data init=/init rootinit=/sbin/init rootrwoptions=rw,noatime rootrwreset=${factory_reset} crashkernel=${kdump_buf}\0" \
+	"set_bootargs=setenv bootargs console=ttyS0,115200 root=PARTUUID=${uuid} rootfstype=ext4 rdinit=/sbin/init rootwait rw earlycon clk_ignore_unused loglevel=${kernel_loglevel} eth=$ethaddr crashkernel=${kdump_buf}\0" \
 	"load_aon=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_aon_fpga.bin;cp.b $fwaddr $aon_ram_addr $filesize\0"\
 	"load_c906_audio=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_c906_audio.bin;cp.b $fwaddr $audio_ram_addr $filesize\0"\
-	"bootcmd_load=run findpart;run load_aon;run load_c906_audio; ext4load mmc ${mmcdev}:${mmcbootpart} $opensbi_addr fw_dynamic.bin; ext4load mmc ${mmcdev}:${mmcbootpart} $dtb_addr ${fdt_file}; ext4load mmc ${mmcdev}:${mmcbootpart} $kernel_addr Image\0" \
+	"bootcmd_load=run load_aon;run load_c906_audio; ext4load mmc ${mmcdev}:${mmcbootpart} $opensbi_addr fw_dynamic.bin; ext4load mmc ${mmcdev}:${mmcbootpart} $dtb_addr ${fdt_file}; ext4load mmc ${mmcdev}:${mmcbootpart} $kernel_addr Image\0" \
 	"bootcmd=run bootcmd_load; bootslave; run finduuid; run set_bootargs; booti $kernel_addr - $dtb_addr;\0" \
-	"factory_reset=yes\0"\
         "\0"
 #elif defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_REF)
 #define CONFIG_EXTRA_ENV_SETTINGS \
@@ -310,28 +405,27 @@
 	"splashpos=m,m\0" \
 	"fdt_high=0xffffffffffffffff\0" \
 	"opensbi_addr=0x0\0" \
-	"dtb_addr=0x01f00000\0" \
+	"dtb_addr=0x02800000\0" \
 	"kernel_addr=0x00200000\0" \
 	"aon_ram_addr=0xffffef8000\0" \
-	"audio_ram_addr=0xffc0000000\0" \
+	"audio_ram_addr=0x32000000\0" \
 	"fwaddr=0x10000000\0"\
 	"mmcdev=0\0" \
-	"boot_partition=bootA\0" \
-	"root_partition=rootfsA\0" \
-	"kdump_buf=1M\0" \
-	"findpart=rollback; if test ${boot_partition} = bootB; then mmcbootpart=4; else mmcbootpart=2; fi; if test ${root_partition} = rootfsB; then mmcpart=5; else mmcpart=3; fi;\0" \
+	"mmcpart=3\0" \
+	"mmcbootpart=2\0" \
+	ENV_KERNEL_LOGLEVEL \
+	"kdump_buf=180M\0" \
+	ENV_STR_BOOT_DELAY \
 	"fdt_file=light-ant-ref.dtb\0" \
-	"uuid_rootfsA=80a5a8e9-c744-491a-93c1-4f4194fd690a\0" \
-	"uuid_rootfsB=80a5a8e9-c744-491a-93c1-4f4194fd690b\0" \
-	"partitions=name=table,size=2031KB;name=boot,size=200MiB,type=boot;name=root,size=4000MiB,type=linux,uuid=${uuid_rootfsA};name=bootB,size=200MiB,type=boot;name=rootB,size=4000MiB,type=linux,uuid=${uuid_rootfsB};name=data,size=-,type=linux\0" \
+	"uuid_rootfs=80a5a8e9-c744-491a-93c1-4f4194fd690b\0" \
+	"partitions=name=table,size=2031KB;name=boot,size=200MiB,type=boot;name=root,size=-,type=linux,uuid=${uuid_rootfs}\0" \
 	"finduuid=part uuid mmc ${mmcdev}:${mmcpart} uuid\0" \
 	"gpt_partition=gpt write mmc ${mmcdev} $partitions\0" \
-	"set_bootargs=setenv bootargs console=ttyS0,115200 root=PARTUUID=${uuid} rootfstype=ext4 rdinit=/sbin/init rootwait rw earlycon clk_ignore_unused loglevel=7 eth=$ethaddr rootrw=PARTLABEL=data init=/init rootinit=/sbin/init rootrwoptions=rw,noatime rootrwreset=${factory_reset} crashkernel=${kdump_buf}\0" \
+	"set_bootargs=setenv bootargs console=ttyS0,115200 root=PARTUUID=${uuid} rootfstype=ext4 rdinit=/sbin/init rootwait rw earlycon clk_ignore_unused loglevel=${kernel_loglevel} eth=$ethaddr crashkernel=${kdump_buf}\0" \
 	"load_aon=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_aon_fpga.bin;cp.b $fwaddr $aon_ram_addr $filesize\0"\
 	"load_c906_audio=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_c906_audio.bin;cp.b $fwaddr $audio_ram_addr $filesize\0"\
-	"bootcmd_load=run findpart;run load_aon;run load_c906_audio; ext4load mmc ${mmcdev}:${mmcbootpart} $opensbi_addr fw_dynamic.bin; ext4load mmc ${mmcdev}:${mmcbootpart} $dtb_addr ${fdt_file}; ext4load mmc ${mmcdev}:${mmcbootpart} $kernel_addr Image\0" \
+	"bootcmd_load=run load_aon;run load_c906_audio; ext4load mmc ${mmcdev}:${mmcbootpart} $opensbi_addr fw_dynamic.bin; ext4load mmc ${mmcdev}:${mmcbootpart} $dtb_addr ${fdt_file}; ext4load mmc ${mmcdev}:${mmcbootpart} $kernel_addr Image\0" \
 	"bootcmd=run bootcmd_load; bootslave; run finduuid; run set_bootargs; booti $kernel_addr - $dtb_addr;\0" \
-	"factory_reset=yes\0"\
         "\0"
 #elif defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_DISCRETE)
 #define CONFIG_EXTRA_ENV_SETTINGS \
@@ -339,28 +433,27 @@
 	"splashpos=m,m\0" \
 	"fdt_high=0xffffffffffffffff\0" \
 	"opensbi_addr=0x0\0" \
-	"dtb_addr=0x01f00000\0" \
+	"dtb_addr=0x02800000\0" \
 	"kernel_addr=0x00200000\0" \
 	"aon_ram_addr=0xffffef8000\0" \
-	"audio_ram_addr=0xffc0000000\0" \
+	"audio_ram_addr=0x32000000\0" \
 	"fwaddr=0x10000000\0"\
 	"mmcdev=0\0" \
-	"boot_partition=bootA\0" \
-	"root_partition=rootfsA\0" \
-	"kdump_buf=1M\0" \
-	"findpart=rollback; if test ${boot_partition} = bootB; then mmcbootpart=4; else mmcbootpart=2; fi; if test ${root_partition} = rootfsB; then mmcpart=5; else mmcpart=3; fi;\0" \
+	"mmcpart=3\0" \
+	"mmcbootpart=2\0" \
+	ENV_KERNEL_LOGLEVEL \
+	"kdump_buf=180M\0" \
+	ENV_STR_BOOT_DELAY \
 	"fdt_file=light-ant-discrete.dtb\0" \
-	"uuid_rootfsA=80a5a8e9-c744-491a-93c1-4f4194fd690a\0" \
-	"uuid_rootfsB=80a5a8e9-c744-491a-93c1-4f4194fd690b\0" \
-	"partitions=name=table,size=2031KB;name=boot,size=200MiB,type=boot;name=root,size=4000MiB,type=linux,uuid=${uuid_rootfsA};name=bootB,size=200MiB,type=boot;name=rootB,size=4000MiB,type=linux,uuid=${uuid_rootfsB};name=data,size=-,type=linux\0" \
+	"uuid_rootfs=80a5a8e9-c744-491a-93c1-4f4194fd690b\0" \
+	"partitions=name=table,size=2031KB;name=boot,size=200MiB,type=boot;name=root,size=-,type=linux,uuid=${uuid_rootfs}\0" \
 	"finduuid=part uuid mmc ${mmcdev}:${mmcpart} uuid\0" \
 	"gpt_partition=gpt write mmc ${mmcdev} $partitions\0" \
-	"set_bootargs=setenv bootargs console=ttyS0,115200 root=PARTUUID=${uuid} rootfstype=ext4 rdinit=/sbin/init rootwait rw earlycon clk_ignore_unused loglevel=7 eth=$ethaddr rootrw=PARTLABEL=data init=/init rootinit=/sbin/init rootrwoptions=rw,noatime rootrwreset=${factory_reset} crashkernel=${kdump_buf}\0" \
+	"set_bootargs=setenv bootargs console=ttyS0,115200 root=PARTUUID=${uuid} rootfstype=ext4 rdinit=/sbin/init rootwait rw earlycon clk_ignore_unused loglevel=${kernel_loglevel} eth=$ethaddr crashkernel=${kdump_buf}\0" \
 	"load_aon=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_aon_fpga.bin;cp.b $fwaddr $aon_ram_addr $filesize\0"\
 	"load_c906_audio=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_c906_audio.bin;cp.b $fwaddr $audio_ram_addr $filesize\0"\
-	"bootcmd_load=run findpart;run load_aon;run load_c906_audio; ext4load mmc ${mmcdev}:${mmcbootpart} $opensbi_addr fw_dynamic.bin; ext4load mmc ${mmcdev}:${mmcbootpart} $dtb_addr ${fdt_file}; ext4load mmc ${mmcdev}:${mmcbootpart} $kernel_addr Image\0" \
+	"bootcmd_load=run load_aon;run load_c906_audio; ext4load mmc ${mmcdev}:${mmcbootpart} $opensbi_addr fw_dynamic.bin; ext4load mmc ${mmcdev}:${mmcbootpart} $dtb_addr ${fdt_file}; ext4load mmc ${mmcdev}:${mmcbootpart} $kernel_addr Image\0" \
 	"bootcmd=run bootcmd_load; bootslave; run finduuid; run set_bootargs; booti $kernel_addr - $dtb_addr;\0" \
-	"factory_reset=yes\0"\
         "\0"
 #elif defined (CONFIG_TARGET_LIGHT_FM_C910_BEAGLE)
 #define CONFIG_EXTRA_ENV_SETTINGS \
@@ -368,28 +461,55 @@
 	"splashpos=m,m\0" \
 	"fdt_high=0xffffffffffffffff\0" \
 	"opensbi_addr=0x0\0" \
-	"dtb_addr=0x01f00000\0" \
+	"dtb_addr=0x02800000\0" \
 	"kernel_addr=0x00200000\0" \
 	"aon_ram_addr=0xffffef8000\0" \
-	"audio_ram_addr=0xffc0000000\0" \
+	"audio_ram_addr=0x32000000\0" \
 	"fwaddr=0x10000000\0"\
 	"mmcdev=0\0" \
-	"boot_partition=bootA\0" \
-	"root_partition=rootfsA\0" \
-	"kdump_buf=500M\0" \
-	"findpart=rollback; if test ${boot_partition} = bootB; then mmcbootpart=4; else mmcbootpart=2; fi; if test ${root_partition} = rootfsB; then mmcpart=5; else mmcpart=3; fi;\0" \
+	"mmcpart=3\0" \
+	"mmcbootpart=2\0" \
+	ENV_KERNEL_LOGLEVEL \
+	"kdump_buf=180M\0" \
+	ENV_STR_BOOT_DELAY \
 	"fdt_file=light-beagle.dtb\0" \
-	"uuid_rootfsA=80a5a8e9-c744-491a-93c1-4f4194fd690a\0" \
-	"uuid_rootfsB=80a5a8e9-c744-491a-93c1-4f4194fd690b\0" \
-	"partitions=name=table,size=2031KB;name=boot,size=200MiB,type=boot;name=root,size=4000MiB,type=linux,uuid=${uuid_rootfsA};name=bootB,size=200MiB,type=boot;name=rootB,size=4000MiB,type=linux,uuid=${uuid_rootfsB};name=data,size=-,type=linux\0" \
+	"uuid_rootfs=80a5a8e9-c744-491a-93c1-4f4194fd690b\0" \
+	"partitions=name=table,size=2031KB;name=boot,size=200MiB,type=boot;name=root,size=-,type=linux,uuid=${uuid_rootfs}\0" \
 	"finduuid=part uuid mmc ${mmcdev}:${mmcpart} uuid\0" \
 	"gpt_partition=gpt write mmc ${mmcdev} $partitions\0" \
-	"set_bootargs=setenv bootargs console=ttyS0,115200 root=PARTUUID=${uuid} rootfstype=ext4 rdinit=/sbin/init rootwait rw earlycon clk_ignore_unused loglevel=7 eth=$ethaddr rootrw=PARTLABEL=data init=/init rootinit=/sbin/init rootrwoptions=rw,noatime rootrwreset=${factory_reset} crashkernel=${kdump_buf}\0" \
+	"set_bootargs=setenv bootargs console=ttyS0,115200 root=PARTUUID=${uuid} rootfstype=ext4 rdinit=/sbin/init rootwait rw earlycon clk_ignore_unused loglevel=${kernel_loglevel} eth=$ethaddr crashkernel=${kdump_buf}\0" \
 	"load_aon=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_aon_fpga.bin;cp.b $fwaddr $aon_ram_addr $filesize\0"\
 	"load_c906_audio=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_c906_audio.bin;cp.b $fwaddr $audio_ram_addr $filesize\0"\
-	"bootcmd_load=run findpart;run load_aon;run load_c906_audio; ext4load mmc ${mmcdev}:${mmcbootpart} $opensbi_addr fw_dynamic.bin; ext4load mmc ${mmcdev}:${mmcbootpart} $dtb_addr ${fdt_file}; ext4load mmc ${mmcdev}:${mmcbootpart} $kernel_addr Image\0" \
+	"bootcmd_load=run load_aon;run load_c906_audio; ext4load mmc ${mmcdev}:${mmcbootpart} $opensbi_addr fw_dynamic.bin; ext4load mmc ${mmcdev}:${mmcbootpart} $dtb_addr ${fdt_file}; ext4load mmc ${mmcdev}:${mmcbootpart} $kernel_addr Image\0" \
+	"bootcmd=run bootcmd_load; bootslave; run finduuid; run set_bootargs; booti $kernel_addr - $dtb_addr;\0" \
+        "\0"
+#elif defined (CONFIG_TARGET_LIGHT_FM_C910_LPI4A)
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"splashimage=0x30000000\0" \
+	"splashpos=m,m\0" \
+	"fdt_high=0xffffffffffffffff\0" \
+	"opensbi_addr=0x0\0" \
+	"dtb_addr=0x02800000\0" \
+	"kernel_addr=0x00200000\0" \
+	"aon_ram_addr=0xffffef8000\0" \
+	"audio_ram_addr=0x32000000\0" \
+	"fwaddr=0x10000000\0"\
+	"mmcdev=0\0" \
+	"mmcpart=3\0" \
+	"mmcbootpart=2\0" \
+	ENV_KERNEL_LOGLEVEL \
+	"kdump_buf=180M\0" \
+	ENV_STR_BOOT_DELAY \
+	"fdt_file=light-lpi4a.dtb\0" \
+	"uuid_rootfs=80a5a8e9-c744-491a-93c1-4f4194fd690b\0" \
+	"partitions=name=table,size=2031KB;name=boot,size=200MiB,type=boot;name=root,size=-,type=linux,uuid=${uuid_rootfs}\0" \
+	"finduuid=part uuid mmc ${mmcdev}:${mmcpart} uuid\0" \
+	"gpt_partition=gpt write mmc ${mmcdev} $partitions\0" \
+	"set_bootargs=setenv bootargs console=ttyS0,115200 root=PARTUUID=${uuid} rootfstype=ext4 rdinit=/sbin/init rootwait rw earlycon clk_ignore_unused loglevel=${kernel_loglevel} eth=$ethaddr crashkernel=${kdump_buf}\0" \
+	"load_aon=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_aon_fpga.bin;cp.b $fwaddr $aon_ram_addr $filesize\0"\
+	"load_c906_audio=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_c906_audio.bin;cp.b $fwaddr $audio_ram_addr $filesize\0"\
+	"bootcmd_load=run load_aon;run load_c906_audio; ext4load mmc ${mmcdev}:${mmcbootpart} $opensbi_addr fw_dynamic.bin; ext4load mmc ${mmcdev}:${mmcbootpart} $dtb_addr ${fdt_file}; ext4load mmc ${mmcdev}:${mmcbootpart} $kernel_addr Image\0" \
 	"bootcmd=run bootcmd_load; bootslave; run finduuid; run set_bootargs; booti $kernel_addr - $dtb_addr;\0" \
-	"factory_reset=yes\0"\
         "\0"
 #elif defined (CONFIG_TARGET_LIGHT_FM_C910_A_REF)
 #define CONFIG_EXTRA_ENV_SETTINGS \
@@ -397,25 +517,26 @@
 	"splashpos=m,m\0" \
 	"fdt_high=0xffffffffffffffff\0" \
 	"opensbi_addr=0x0\0" \
-	"dtb_addr=0x01f00000\0" \
+	"dtb_addr=0x02800000\0" \
 	"kernel_addr=0x00200000\0" \
 	"aon_ram_addr=0xffffef8000\0" \
-	"audio_ram_addr=0xffc0000000\0" \
+	"audio_ram_addr=0x32000000\0" \
 	"fwaddr=0x10000000\0"\
 	"mmcdev=0\0" \
-	"boot_partition=bootA\0" \
-	"root_partition=rootfsA\0" \
-	"findpart=if test ${boot_partition} = bootB; then mmcbootpart=4; else mmcbootpart=2; fi; if test ${root_partition} = rootfsB; then mmcpart=5; else mmcpart=3; fi;\0" \
+	"mmcpart=3\0" \
+	"mmcbootpart=2\0" \
+	ENV_KERNEL_LOGLEVEL \
+	"kdump_buf=180M\0" \
+	ENV_STR_BOOT_DELAY \
 	"fdt_file=light-a-ref.dtb\0" \
-	"uuid_rootfsA=80a5a8e9-c744-491a-93c1-4f4194fd690a\0" \
-	"uuid_rootfsB=80a5a8e9-c744-491a-93c1-4f4194fd690b\0" \
-	"partitions=name=table,size=2031KB;name=boot,size=200MiB,type=boot;name=root,size=4000MiB,type=linux,uuid=${uuid_rootfsA};name=bootB,size=200MiB,type=boot;name=rootB,size=4000MiB,type=linux,uuid=${uuid_rootfsB};name=data,size=-,type=linux\0" \
+	"uuid_rootfs=80a5a8e9-c744-491a-93c1-4f4194fd690b\0" \
+	"partitions=name=table,size=2031KB;name=boot,size=200MiB,type=boot;name=root,size=-,type=linux,uuid=${uuid_rootfs}\0" \
 	"finduuid=part uuid mmc ${mmcdev}:${mmcpart} uuid\0" \
 	"gpt_partition=gpt write mmc ${mmcdev} $partitions\0" \
-	"set_bootargs=setenv bootargs console=ttyS0,115200 root=PARTUUID=${uuid} rootfstype=ext4 rdinit=/sbin/init rootwait rw earlycon clk_ignore_unused loglevel=7 eth=$ethaddr rootrw=PARTLABEL=data init=/init rootinit=/sbin/init rootrwoptions=rw,noatime\0" \
+	"set_bootargs=setenv bootargs console=ttyS0,115200 root=PARTUUID=${uuid} rootfstype=ext4 rdinit=/sbin/init rootwait rw earlycon clk_ignore_unused loglevel=${kernel_loglevel} eth=$ethaddr crashkernel=${kdump_buf}\0" \
 	"load_aon=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_aon_fpga.bin;cp.b $fwaddr $aon_ram_addr $filesize\0"\
 	"load_c906_audio=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_c906_audio.bin;cp.b $fwaddr $audio_ram_addr $filesize\0"\
-	"bootcmd_load=run findpart;run load_aon;run load_c906_audio; ext4load mmc ${mmcdev}:${mmcbootpart} $opensbi_addr fw_dynamic.bin; ext4load mmc ${mmcdev}:${mmcbootpart} $dtb_addr ${fdt_file}; ext4load mmc ${mmcdev}:${mmcbootpart} $kernel_addr Image\0" \
+	"bootcmd_load=run load_aon;run load_c906_audio; ext4load mmc ${mmcdev}:${mmcbootpart} $opensbi_addr fw_dynamic.bin; ext4load mmc ${mmcdev}:${mmcbootpart} $dtb_addr ${fdt_file}; ext4load mmc ${mmcdev}:${mmcbootpart} $kernel_addr Image\0" \
 	"bootcmd=run bootcmd_load; bootslave; run finduuid; run set_bootargs; booti $kernel_addr - $dtb_addr;\0" \
         "\0"
 #else
@@ -424,28 +545,27 @@
 	"splashpos=m,m\0" \
 	"fdt_high=0xffffffffffffffff\0" \
 	"opensbi_addr=0x0\0" \
-	"dtb_addr=0x01f00000\0" \
+	"dtb_addr=0x02800000\0" \
 	"kernel_addr=0x00200000\0" \
 	"aon_ram_addr=0xffffef8000\0" \
-	"audio_ram_addr=0xffc0000000\0" \
+	"audio_ram_addr=0x32000000\0" \
 	"fwaddr=0x10000000\0"\
 	"mmcdev=0\0" \
-	"boot_partition=bootA\0" \
-	"root_partition=rootfsA\0" \
-	"kdump_buf=500M\0" \
-	"findpart=rollback; if test ${boot_partition} = bootB; then mmcbootpart=4; else mmcbootpart=2; fi; if test ${root_partition} = rootfsB; then mmcpart=5; else mmcpart=3; fi;\0" \
-	"fdt_file=light-a-val.dtb\0" \
-	"uuid_rootfsA=80a5a8e9-c744-491a-93c1-4f4194fd690a\0" \
-	"uuid_rootfsB=80a5a8e9-c744-491a-93c1-4f4194fd690b\0" \
-	"partitions=name=table,size=2031KB;name=boot,size=200MiB,type=boot;name=root,size=4000MiB,type=linux,uuid=${uuid_rootfsA};name=bootB,size=200MiB,type=boot;name=rootB,size=4000MiB,type=linux,uuid=${uuid_rootfsB};name=data,size=-,type=linux\0" \
+	"mmcpart=3\0" \
+	"mmcbootpart=2\0" \
+	ENV_KERNEL_LOGLEVEL \
+	"kdump_buf=180M\0" \
+	ENV_STR_BOOT_DELAY \
+	"fdt_file=light-a-val-audio-hdmi.dtb\0" \
+	"uuid_rootfs=80a5a8e9-c744-491a-93c1-4f4194fd690b\0" \
+	"partitions=name=table,size=2031KB;name=boot,size=200MiB,type=boot;name=root,size=-,type=linux,uuid=${uuid_rootfs}\0" \
 	"finduuid=part uuid mmc ${mmcdev}:${mmcpart} uuid\0" \
 	"gpt_partition=gpt write mmc ${mmcdev} $partitions\0" \
-	"set_bootargs=setenv bootargs console=ttyS0,115200 root=PARTUUID=${uuid} rootfstype=ext4 rdinit=/sbin/init rootwait rw earlycon clk_ignore_unused loglevel=7 eth=$ethaddr rootrw=PARTLABEL=data init=/init rootinit=/sbin/init rootrwoptions=rw,noatime rootrwreset=${factory_reset} crashkernel=${kdump_buf}\0" \
+	"set_bootargs=setenv bootargs console=ttyS0,115200 root=PARTUUID=${uuid} rootfstype=ext4 rdinit=/sbin/init rootwait rw earlycon clk_ignore_unused loglevel=${kernel_loglevel} eth=$ethaddr crashkernel=${kdump_buf}\0" \
 	"load_aon=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_aon_fpga.bin;cp.b $fwaddr $aon_ram_addr $filesize\0"\
 	"load_c906_audio=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_c906_audio.bin;cp.b $fwaddr $audio_ram_addr $filesize\0"\
-	"bootcmd_load=run findpart;run load_aon;run load_c906_audio; ext4load mmc ${mmcdev}:${mmcbootpart} $opensbi_addr fw_dynamic.bin; ext4load mmc ${mmcdev}:${mmcbootpart} $dtb_addr ${fdt_file}; ext4load mmc ${mmcdev}:${mmcbootpart} $kernel_addr Image\0" \
+	"bootcmd_load=run load_aon;run load_c906_audio; ext4load mmc ${mmcdev}:${mmcbootpart} $opensbi_addr fw_dynamic.bin; ext4load mmc ${mmcdev}:${mmcbootpart} $dtb_addr ${fdt_file}; ext4load mmc ${mmcdev}:${mmcbootpart} $kernel_addr Image\0" \
 	"bootcmd=run bootcmd_load; bootslave; run finduuid; run set_bootargs; booti $kernel_addr - $dtb_addr;\0" \
-	"factory_reset=yes\0"\
         "\0"
 #endif
 #endif

include/xbc.h

@@ -0,0 +1 @@
+#include <../lib/libxbc/libxbc.h>

lib/Kconfig

@@ -316,6 +316,20 @@ config LIBAVB
 
 endmenu
 
+menu "Boot Configuration"
+
+config XBC
+	bool "Boot Configuration support"
+	depends on ANDROID_BOOT_IMAGE
+	default n
+	help
+	  This enables support of Boot Configuration which can be used
+	  to pass boot configuration parameters to user space. These
+	  parameters will show up in /proc/bootconfig similar to the kernel
+	  parameters that show up in /proc/cmdline
+
+endmenu
+
 menu "Hashing Support"
 
 config SHA1

lib/Makefile

@@ -68,6 +68,8 @@ obj-$(CONFIG_$(SPL_)LZ4) += lz4_wrapper.o
 
 obj-$(CONFIG_LIBAVB) += libavb/
 
+obj-$(CONFIG_XBC) += libxbc/
+
 obj-$(CONFIG_$(SPL_TPL_)OF_LIBFDT) += libfdt/
 ifneq ($(CONFIG_$(SPL_TPL_)BUILD)$(CONFIG_$(SPL_TPL_)OF_PLATDATA),yy)
 obj-$(CONFIG_$(SPL_TPL_)OF_CONTROL) += fdtdec_common.o

lib/libavb/avb_rsa.c

@@ -13,6 +13,10 @@
 #include "avb_util.h"
 #include "avb_vbmeta_image.h"
 
+#if defined(CONFIG_AVB_HW_ENGINE_ENABLE)
+#include "sec_library.h"
+#endif
+
 typedef struct IAvbKey {
   unsigned int len; /* Length of n[] in number of uint32_t */
   uint32_t n0inv;   /* -1 / n[0] mod 2^32 */
@@ -82,7 +86,19 @@ fail:
 static void iavb_free_parsed_key(IAvbKey* key) {
   avb_free(key);
 }
+#if defined(CONFIG_AVB_HW_ENGINE_ENABLE)
 
+static void hw_crypto_accel_init(void)
+{
+	static bool init = false;
+
+	if (!init) {
+		rambus_crypto_init();
+		init = true;
+	}
+}
+
+#else
 /* a[] -= mod */
 static void subM(const IAvbKey* key, uint32_t* a) {
   int64_t A = 0;
@@ -200,7 +216,7 @@ out:
     avb_free(aaR);
   }
 }
-
+#endif
 /* Verify a RSA PKCS1.5 signature against an expected hash.
  * Returns false on failure, true on success.
  */
@@ -212,6 +228,83 @@ bool avb_rsa_verify(const uint8_t* key,
                     size_t hash_num_bytes,
                     const uint8_t* padding,
                     size_t padding_num_bytes) {
+#if defined(CONFIG_AVB_HW_ENGINE_ENABLE)
+  IAvbKey* parsed_key = NULL;
+  uint8_t *nk = NULL;
+  uint8_t *n = NULL;
+  uint8_t *e = NULL;
+  int i;
+  bool success = false;
+  uint32_t key_bytes = 0;
+  sc_rsa_t  rsa;
+  sc_rsa_context_t rsa_ctx;
+
+  if (key == NULL || sig == NULL || hash == NULL || padding == NULL) {
+    avb_error("Invalid input.\n");
+    goto out;
+  }
+
+  parsed_key = iavb_parse_key_data(key, key_num_bytes);
+  if (parsed_key == NULL) {
+    avb_error("Error parsing key.\n");
+    goto out;
+  }
+  
+  if (padding_num_bytes != sig_num_bytes - hash_num_bytes) {
+    avb_error("Padding length does not match hash and signature lengths.\n");
+    goto out;
+  }
+
+  key_bytes = parsed_key->len * sizeof(uint32_t);
+  /* Currently, we only support RSA key 2048bits and SHA256 */
+  if ((key_bytes * 8 != 2048) || (hash_num_bytes * 8 != 256)) {
+    avb_error("Error unsupported keybits length.\n");
+    goto out;
+  }
+
+  nk = (uint8_t *)parsed_key->n;
+  n = avb_malloc(key_bytes);
+  if (n == NULL) {
+    avb_error("Error malloc n.\n");
+    goto out;
+  }
+  /* Reverse modular little endian */
+  for (i = 0; i < key_bytes; i++) {
+    n[i] = nk[key_bytes - i - 1];
+  }
+
+  e = avb_malloc(key_bytes);
+  if (e == NULL) {
+    avb_error("Error malloc e.\n");
+    goto out;
+  }
+  memset(e, 0, key_bytes);
+  /* public exponentiation. (65537} */
+  e[key_bytes-1] = 0x01; e[key_bytes-2] = 0x00; e[key_bytes-3] = 0x01; e[key_bytes-4] = 0x00;
+
+  hw_crypto_accel_init();
+  sc_rsa_init(&rsa, 0, SC_RSA_KEY_BITS_2048);
+
+  rsa_ctx.padding_type = SC_RSA_PADDING_MODE_PKCS1;
+  rsa_ctx.n = n;
+  rsa_ctx.e = e;
+  rsa_ctx.hash_type = SC_RSA_HASH_TYPE_SHA256;
+  rsa_ctx.is_crt = SC_RSA_CRT_DISABLE;
+  rsa_ctx.is_hash = SC_RSA_HASH_DISABLE;
+
+  success = sc_rsa_verify(&rsa, &rsa_ctx, (void *)hash, hash_num_bytes, (void *)sig, sig_num_bytes, SC_RSA_HASH_TYPE_SHA256);
+  sc_rsa_uninit(&rsa);
+
+out:
+  if (parsed_key != NULL) {
+    iavb_free_parsed_key(parsed_key);
+  }
+  if (e != NULL) {
+    avb_free(e);
+  }
+
+  return success;
+#else
   uint8_t* buf = NULL;
   IAvbKey* parsed_key = NULL;
   bool success = false;
@@ -272,4 +365,5 @@ out:
     avb_free(buf);
   }
   return success;
+#endif
 }

lib/libavb/avb_sha.h

@@ -20,6 +20,9 @@ extern "C" {
 
 #include "avb_crypto.h"
 #include "avb_sysdeps.h"
+#if defined(CONFIG_AVB_HW_ENGINE_ENABLE)
+#include "sec_library.h"
+#endif
 
 /* Block size in bytes of a SHA-256 digest. */
 #define AVB_SHA256_BLOCK_SIZE 64
@@ -30,19 +33,29 @@ extern "C" {
 
 /* Data structure used for SHA-256. */
 typedef struct {
+#if defined(CONFIG_AVB_HW_ENGINE_ENABLE)
+  sc_sha_t sha_t;
+  sc_sha_context_t sha_context;
+#else
   uint32_t h[8];
   uint64_t tot_len;
   size_t len;
   uint8_t block[2 * AVB_SHA256_BLOCK_SIZE];
+#endif
   uint8_t buf[AVB_SHA256_DIGEST_SIZE]; /* Used for storing the final digest. */
 } AvbSHA256Ctx;
 
 /* Data structure used for SHA-512. */
 typedef struct {
+#if defined(CONFIG_AVB_HW_ENGINE_ENABLE)
+  sc_sha_t sha_t;
+  sc_sha_context_t sha_context;
+#else
   uint64_t h[8];
   uint64_t tot_len;
   size_t len;
   uint8_t block[2 * AVB_SHA512_BLOCK_SIZE];
+#endif
   uint8_t buf[AVB_SHA512_DIGEST_SIZE]; /* Used for storing the final digest. */
 } AvbSHA512Ctx;
 

lib/libavb/avb_sha256.c

@@ -10,6 +10,7 @@
 
 #include "avb_sha.h"
 
+#if !defined(CONFIG_AVB_HW_ENGINE_ENABLE)
 #define SHFR(x, n) (x >> n)
 #define ROTR(x, n) ((x >> n) | (x << ((sizeof(x) << 3) - n)))
 #define ROTL(x, n) ((x << n) | (x >> ((sizeof(x) << 3) - n)))
@@ -83,9 +84,19 @@ static const uint32_t sha256_k[64] = {
     0x19a4c116, 0x1e376c08, 0x2748774c, 0x34b0bcb5, 0x391c0cb3, 0x4ed8aa4a,
     0x5b9cca4f, 0x682e6ff3, 0x748f82ee, 0x78a5636f, 0x84c87814, 0x8cc70208,
     0x90befffa, 0xa4506ceb, 0xbef9a3f7, 0xc67178f2};
+#endif
 
 /* SHA-256 implementation */
 void avb_sha256_init(AvbSHA256Ctx* ctx) {
+#if defined(CONFIG_AVB_HW_ENGINE_ENABLE)
+  if (ctx == NULL) {
+    return;
+  }
+
+  sc_sha_init(&ctx->sha_t, 0);
+  sc_sha_start(&ctx->sha_t, &ctx->sha_context, SC_SHA_MODE_256);
+  sc_sha_trans_config(&ctx->sha_t, &ctx->sha_context, 1);
+#else
 #ifndef UNROLL_LOOPS
   int i;
   for (i = 0; i < 8; i++) {
@@ -104,8 +115,10 @@ void avb_sha256_init(AvbSHA256Ctx* ctx) {
 
   ctx->len = 0;
   ctx->tot_len = 0;
+#endif
 }
 
+#if !defined(CONFIG_AVB_HW_ENGINE_ENABLE)
 static void SHA256_transform(AvbSHA256Ctx* ctx,
                              const uint8_t* message,
                              size_t block_nb) {
@@ -304,8 +317,16 @@ static void SHA256_transform(AvbSHA256Ctx* ctx,
 #endif /* !UNROLL_LOOPS */
   }
 }
+#endif
 
 void avb_sha256_update(AvbSHA256Ctx* ctx, const uint8_t* data, size_t len) {
+#if defined(CONFIG_AVB_HW_ENGINE_ENABLE)
+  if (ctx == NULL || data == NULL) {
+    return;
+  }
+
+  sc_sha_update(&ctx->sha_t, &ctx->sha_context, data, len);
+#else
   size_t block_nb;
   size_t new_len, rem_len, tmp_len;
   const uint8_t* shifted_data;
@@ -334,9 +355,25 @@ void avb_sha256_update(AvbSHA256Ctx* ctx, const uint8_t* data, size_t len) {
 
   ctx->len = rem_len;
   ctx->tot_len += (block_nb + 1) << 6;
+#endif
 }
 
 uint8_t* avb_sha256_final(AvbSHA256Ctx* ctx) {
+#if defined(CONFIG_AVB_HW_ENGINE_ENABLE)
+  uint32_t len = 0;
+  uint32_t ret = 0;
+  
+  if (ctx == NULL) {
+    return NULL;
+  }
+
+  ret = sc_sha_finish(&ctx->sha_t, &ctx->sha_context, ctx->buf, &len);
+  if (ret != 0) {
+    return NULL;
+  }
+
+  return ctx->buf;
+#else
   size_t block_nb;
   size_t pm_len;
   uint64_t len_b;
@@ -372,4 +409,5 @@ uint8_t* avb_sha256_final(AvbSHA256Ctx* ctx) {
 #endif /* !UNROLL_LOOPS */
 
   return ctx->buf;
+#endif
 }

lib/libavb/avb_sha512.c

@@ -10,6 +10,7 @@
 
 #include "avb_sha.h"
 
+#if !defined(CONFIG_AVB_HW_ENGINE_ENABLE)
 #define SHFR(x, n) (x >> n)
 #define ROTR(x, n) ((x >> n) | (x << ((sizeof(x) << 3) - n)))
 #define ROTL(x, n) ((x << n) | (x >> ((sizeof(x) << 3) - n)))
@@ -101,10 +102,20 @@ static const uint64_t sha512_k[80] = {
     0x28db77f523047d84ULL, 0x32caab7b40c72493ULL, 0x3c9ebe0a15c9bebcULL,
     0x431d67c49c100d4cULL, 0x4cc5d4becb3e42b6ULL, 0x597f299cfc657e2aULL,
     0x5fcb6fab3ad6faecULL, 0x6c44198c4a475817ULL};
+#endif
 
 /* SHA-512 implementation */
 
 void avb_sha512_init(AvbSHA512Ctx* ctx) {
+#if defined(CONFIG_AVB_HW_ENGINE_ENABLE)
+  if (ctx == NULL) {
+    return;
+  }
+
+  sc_sha_init(&ctx->sha_t, 0);
+  sc_sha_start(&ctx->sha_t, &ctx->sha_context, SC_SHA_MODE_512);
+  sc_sha_trans_config(&ctx->sha_t, &ctx->sha_context, 1);
+#else
 #ifdef UNROLL_LOOPS_SHA512
   ctx->h[0] = sha512_h0[0];
   ctx->h[1] = sha512_h0[1];
@@ -123,8 +134,10 @@ void avb_sha512_init(AvbSHA512Ctx* ctx) {
 
   ctx->len = 0;
   ctx->tot_len = 0;
+#endif
 }
 
+#if !defined(CONFIG_AVB_HW_ENGINE_ENABLE)
 static void SHA512_transform(AvbSHA512Ctx* ctx,
                              const uint8_t* message,
                              size_t block_nb) {
@@ -290,8 +303,16 @@ static void SHA512_transform(AvbSHA512Ctx* ctx,
 #endif /* UNROLL_LOOPS_SHA512 */
   }
 }
+#endif
 
 void avb_sha512_update(AvbSHA512Ctx* ctx, const uint8_t* data, size_t len) {
+#if defined(CONFIG_AVB_HW_ENGINE_ENABLE)
+  if (ctx == NULL || data == NULL) {
+    return;
+  }
+
+  sc_sha_update(&ctx->sha_t, &ctx->sha_context, data, len);
+#else
   size_t block_nb;
   size_t new_len, rem_len, tmp_len;
   const uint8_t* shifted_data;
@@ -320,9 +341,25 @@ void avb_sha512_update(AvbSHA512Ctx* ctx, const uint8_t* data, size_t len) {
 
   ctx->len = rem_len;
   ctx->tot_len += (block_nb + 1) << 7;
+#endif
 }
 
 uint8_t* avb_sha512_final(AvbSHA512Ctx* ctx) {
+#if defined(CONFIG_AVB_HW_ENGINE_ENABLE)
+  uint32_t len = 0;
+  uint32_t ret = 0;
+  
+  if (ctx == NULL) {
+    return NULL;
+  }
+
+  ret = sc_sha_finish(&ctx->sha_t, &ctx->sha_context, ctx->buf, &len);
+  if (ret != 0) {
+    return NULL;
+  }
+
+  return ctx->buf;
+#else
   size_t block_nb;
   size_t pm_len;
   uint64_t len_b;
@@ -358,4 +395,5 @@ uint8_t* avb_sha512_final(AvbSHA512Ctx* ctx) {
 #endif /* UNROLL_LOOPS_SHA512 */
 
   return ctx->buf;
+#endif
 }

lib/libxbc/COPYING

@@ -0,0 +1,170 @@
+
+                                 Apache License
+                           Version 2.0, January 2004
+                        http://www.apache.org/licenses/
+   TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION
+   1. Definitions.
+      "License" shall mean the terms and conditions for use, reproduction,
+      and distribution as defined by Sections 1 through 9 of this document.
+      "Licensor" shall mean the copyright owner or entity authorized by
+      the copyright owner that is granting the License.
+      "Legal Entity" shall mean the union of the acting entity and all
+      other entities that control, are controlled by, or are under common
+      control with that entity. For the purposes of this definition,
+      "control" means (i) the power, direct or indirect, to cause the
+      direction or management of such entity, whether by contract or
+      otherwise, or (ii) ownership of fifty percent (50%) or more of the
+      outstanding shares, or (iii) beneficial ownership of such entity.
+      "You" (or "Your") shall mean an individual or Legal Entity
+      exercising permissions granted by this License.
+      "Source" form shall mean the preferred form for making modifications,
+      including but not limited to software source code, documentation
+      source, and configuration files.
+      "Object" form shall mean any form resulting from mechanical
+      transformation or translation of a Source form, including but
+      not limited to compiled object code, generated documentation,
+      and conversions to other media types.
+      "Work" shall mean the work of authorship, whether in Source or
+      Object form, made available under the License, as indicated by a
+      copyright notice that is included in or attached to the work
+      (an example is provided in the Appendix below).
+      "Derivative Works" shall mean any work, whether in Source or Object
+      form, that is based on (or derived from) the Work and for which the
+      editorial revisions, annotations, elaborations, or other modifications
+      represent, as a whole, an original work of authorship. For the purposes
+      of this License, Derivative Works shall not include works that remain
+      separable from, or merely link (or bind by name) to the interfaces of,
+      the Work and Derivative Works thereof.
+      "Contribution" shall mean any work of authorship, including
+      the original version of the Work and any modifications or additions
+      to that Work or Derivative Works thereof, that is intentionally
+      submitted to Licensor for inclusion in the Work by the copyright owner
+      or by an individual or Legal Entity authorized to submit on behalf of
+      the copyright owner. For the purposes of this definition, "submitted"
+      means any form of electronic, verbal, or written communication sent
+      to the Licensor or its representatives, including but not limited to
+      communication on electronic mailing lists, source code control systems,
+      and issue tracking systems that are managed by, or on behalf of, the
+      Licensor for the purpose of discussing and improving the Work, but
+      excluding communication that is conspicuously marked or otherwise
+      designated in writing by the copyright owner as "Not a Contribution."
+      "Contributor" shall mean Licensor and any individual or Legal Entity
+      on behalf of whom a Contribution has been received by Licensor and
+      subsequently incorporated within the Work.
+   2. Grant of Copyright License. Subject to the terms and conditions of
+      this License, each Contributor hereby grants to You a perpetual,
+      worldwide, non-exclusive, no-charge, royalty-free, irrevocable
+      copyright license to reproduce, prepare Derivative Works of,
+      publicly display, publicly perform, sublicense, and distribute the
+      Work and such Derivative Works in Source or Object form.
+   3. Grant of Patent License. Subject to the terms and conditions of
+      this License, each Contributor hereby grants to You a perpetual,
+      worldwide, non-exclusive, no-charge, royalty-free, irrevocable
+      (except as stated in this section) patent license to make, have made,
+      use, offer to sell, sell, import, and otherwise transfer the Work,
+      where such license applies only to those patent claims licensable
+      by such Contributor that are necessarily infringed by their
+      Contribution(s) alone or by combination of their Contribution(s)
+      with the Work to which such Contribution(s) was submitted. If You
+      institute patent litigation against any entity (including a
+      cross-claim or counterclaim in a lawsuit) alleging that the Work
+      or a Contribution incorporated within the Work constitutes direct
+      or contributory patent infringement, then any patent licenses
+      granted to You under this License for that Work shall terminate
+      as of the date such litigation is filed.
+   4. Redistribution. You may reproduce and distribute copies of the
+      Work or Derivative Works thereof in any medium, with or without
+      modifications, and in Source or Object form, provided that You
+      meet the following conditions:
+      (a) You must give any other recipients of the Work or
+          Derivative Works a copy of this License; and
+      (b) You must cause any modified files to carry prominent notices
+          stating that You changed the files; and
+      (c) You must retain, in the Source form of any Derivative Works
+          that You distribute, all copyright, patent, trademark, and
+          attribution notices from the Source form of the Work,
+          excluding those notices that do not pertain to any part of
+          the Derivative Works; and
+      (d) If the Work includes a "NOTICE" text file as part of its
+          distribution, then any Derivative Works that You distribute must
+          include a readable copy of the attribution notices contained
+          within such NOTICE file, excluding those notices that do not
+          pertain to any part of the Derivative Works, in at least one
+          of the following places: within a NOTICE text file distributed
+          as part of the Derivative Works; within the Source form or
+          documentation, if provided along with the Derivative Works; or,
+          within a display generated by the Derivative Works, if and
+          wherever such third-party notices normally appear. The contents
+          of the NOTICE file are for informational purposes only and
+          do not modify the License. You may add Your own attribution
+          notices within Derivative Works that You distribute, alongside
+          or as an addendum to the NOTICE text from the Work, provided
+          that such additional attribution notices cannot be construed
+          as modifying the License.
+      You may add Your own copyright statement to Your modifications and
+      may provide additional or different license terms and conditions
+      for use, reproduction, or distribution of Your modifications, or
+      for any such Derivative Works as a whole, provided Your use,
+      reproduction, and distribution of the Work otherwise complies with
+      the conditions stated in this License.
+   5. Submission of Contributions. Unless You explicitly state otherwise,
+      any Contribution intentionally submitted for inclusion in the Work
+      by You to the Licensor shall be under the terms and conditions of
+      this License, without any additional terms or conditions.
+      Notwithstanding the above, nothing herein shall supersede or modify
+      the terms of any separate license agreement you may have executed
+      with Licensor regarding such Contributions.
+   6. Trademarks. This License does not grant permission to use the trade
+      names, trademarks, service marks, or product names of the Licensor,
+      except as required for reasonable and customary use in describing the
+      origin of the Work and reproducing the content of the NOTICE file.
+   7. Disclaimer of Warranty. Unless required by applicable law or
+      agreed to in writing, Licensor provides the Work (and each
+      Contributor provides its Contributions) on an "AS IS" BASIS,
+      WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+      implied, including, without limitation, any warranties or conditions
+      of TITLE, NON-INFRINGEMENT, MERCHANTABILITY, or FITNESS FOR A
+      PARTICULAR PURPOSE. You are solely responsible for determining the
+      appropriateness of using or redistributing the Work and assume any
+      risks associated with Your exercise of permissions under this License.
+   8. Limitation of Liability. In no event and under no legal theory,
+      whether in tort (including negligence), contract, or otherwise,
+      unless required by applicable law (such as deliberate and grossly
+      negligent acts) or agreed to in writing, shall any Contributor be
+      liable to You for damages, including any direct, indirect, special,
+      incidental, or consequential damages of any character arising as a
+      result of this License or out of the use or inability to use the
+      Work (including but not limited to damages for loss of goodwill,
+      work stoppage, computer failure or malfunction, or any and all
+      other commercial damages or losses), even if such Contributor
+      has been advised of the possibility of such damages.
+   9. Accepting Warranty or Additional Liability. While redistributing
+      the Work or Derivative Works thereof, You may choose to offer,
+      and charge a fee for, acceptance of support, warranty, indemnity,
+      or other liability obligations and/or rights consistent with this
+      License. However, in accepting such obligations, You may act only
+      on Your own behalf and on Your sole responsibility, not on behalf
+      of any other Contributor, and only if You agree to indemnify,
+      defend, and hold each Contributor harmless for any liability
+      incurred by, or claims asserted against, such Contributor by reason
+      of your accepting any such warranty or additional liability.
+   END OF TERMS AND CONDITIONS
+   APPENDIX: How to apply the Apache License to your work.
+      To apply the Apache License to your work, attach the following
+      boilerplate notice, with the fields enclosed by brackets "[]"
+      replaced with your own identifying information. (Don't include
+      the brackets!)  The text should be enclosed in the appropriate
+      comment syntax for the file format. We also recommend that a
+      file or class name and description of purpose be included on the
+      same "printed page" as the copyright notice for easier
+      identification within third-party archives.
+   Copyright [yyyy] [name of copyright owner]
+   Licensed under the Apache License, Version 2.0 (the "License");
+   you may not use this file except in compliance with the License.
+   You may obtain a copy of the License at
+       http://www.apache.org/licenses/LICENSE-2.0
+   Unless required by applicable law or agreed to in writing, software
+   distributed under the License is distributed on an "AS IS" BASIS,
+   WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+   See the License for the specific language governing permissions and
+   limitations under the License.

lib/libxbc/Makefile

@@ -0,0 +1,14 @@
+ # Copyright (C) 2021 The Android Open Source Project
+ #
+ # Licensed under the Apache License, Version 2.0 (the "License");
+ # you may not use this file except in compliance with the License.
+ # You may obtain a copy of the License at
+ #
+ #      http://www.apache.org/licenses/LICENSE-2.0
+ #
+ # Unless required by applicable law or agreed to in writing, software
+ # distributed under the License is distributed on an "AS IS" BASIS,
+ # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ # See the License for the specific language governing permissions and
+ # limitations under the License.
+obj-$(CONFIG_XBC) += libxbc.o

lib/libxbc/libxbc.c

@@ -0,0 +1,104 @@
+/*
+ * Copyright (C) 2021 The Android Open Source Project
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "libxbc.h"
+#define BOOTCONFIG_MAGIC "#BOOTCONFIG\n"
+#define BOOTCONFIG_MAGIC_SIZE 12
+#define BOOTCONFIG_SIZE_SIZE 4
+#define BOOTCONFIG_CHECKSUM_SIZE 4
+#define BOOTCONFIG_TRAILER_SIZE BOOTCONFIG_MAGIC_SIZE + \
+                                BOOTCONFIG_SIZE_SIZE + \
+                                BOOTCONFIG_CHECKSUM_SIZE
+/*
+ * Simple checksum for a buffer.
+ *
+ * @param addr pointer to the start of the buffer.
+ * @param size size of the buffer in bytes.
+ * @return check sum result.
+ */
+static uint32_t checksum(const unsigned char* const buffer, uint32_t size) {
+    uint32_t sum = 0;
+    for (uint32_t i = 0; i < size; i++) {
+        sum += buffer[i];
+    }
+    return sum;
+}
+/*
+ * Check if the bootconfig trailer is present within the bootconfig section.
+ *
+ * @param bootconfig_end_addr address of the end of the bootconfig section. If
+ *        the trailer is present, it will be directly preceding this address.
+ * @return true if the trailer is present, false if not.
+ */
+static bool isTrailerPresent(uint64_t bootconfig_end_addr) {
+    return !strncmp((char*)(bootconfig_end_addr - BOOTCONFIG_MAGIC_SIZE),
+                    BOOTCONFIG_MAGIC, BOOTCONFIG_MAGIC_SIZE);
+}
+/*
+ * Add a string of boot config parameters to memory appended by the trailer.
+ */
+int32_t addBootConfigParameters(char* params, uint32_t params_size,
+    uint64_t bootconfig_start_addr, uint32_t bootconfig_size) {
+    if (!params || !bootconfig_start_addr) {
+        return -1;
+    }
+    if (params_size == 0) {
+        return 0;
+    }
+    int32_t applied_bytes = 0;
+    int32_t new_size = 0;
+    uint64_t end = bootconfig_start_addr + bootconfig_size;
+    if (isTrailerPresent(end)) {
+      end -= BOOTCONFIG_TRAILER_SIZE;
+      applied_bytes -= BOOTCONFIG_TRAILER_SIZE;
+      memcpy(&new_size, (void *)end, BOOTCONFIG_SIZE_SIZE);
+    } else {
+      new_size = bootconfig_size;
+    }
+    // params
+    memcpy((void*)end, params, params_size);
+    applied_bytes += params_size;
+    applied_bytes += addBootConfigTrailer(bootconfig_start_addr,
+        bootconfig_size + applied_bytes);
+    return applied_bytes;
+}
+/*
+ * Add boot config trailer.
+ */
+int32_t addBootConfigTrailer(uint64_t bootconfig_start_addr,
+                            uint32_t bootconfig_size) {
+    if (!bootconfig_start_addr) {
+        return -1;
+    }
+    if (bootconfig_size == 0) {
+        return 0;
+    }
+    uint64_t end = bootconfig_start_addr + bootconfig_size;
+    if (isTrailerPresent(end)) {
+        // no need to overwrite the current trailers
+        return 0;
+    }
+    // size
+    memcpy((void *)(end), &bootconfig_size, BOOTCONFIG_SIZE_SIZE);
+    // checksum
+    uint32_t sum =
+        checksum((unsigned char*)bootconfig_start_addr, bootconfig_size);
+    memcpy((void *)(end + BOOTCONFIG_SIZE_SIZE), &sum,
+        BOOTCONFIG_CHECKSUM_SIZE);
+    // magic
+    memcpy((void *)(end + BOOTCONFIG_SIZE_SIZE + BOOTCONFIG_CHECKSUM_SIZE),
+           BOOTCONFIG_MAGIC, BOOTCONFIG_MAGIC_SIZE);
+    return BOOTCONFIG_TRAILER_SIZE;
+}

lib/libxbc/libxbc.h

@@ -0,0 +1,54 @@
+/*
+ * Copyright (C) 2021 The Android Open Source Project
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef LIBXBC_H_
+#define LIBXBC_H_
+// memcpy and strncmp
+#include <common.h>
+/*
+ * Add a string of boot config parameters to memory appended by the trailer.
+ * This memory needs to be immediately following the end of the ramdisks.
+ * The new boot config trailer will be written to the end of the entire
+ * parameter section(previous + new). The trailer contains a 4 byte size of the
+ * parameters, followed by a 4 byte checksum of the parameters, followed by a 12
+ * byte magic string.
+ *
+ * @param params pointer to string of boot config parameters
+ * @param params_size size of params string in bytes
+ * @param bootconfig_start_addr address that the boot config section is starting
+ *        at in memory.
+ * @param bootconfig_size size of the current bootconfig section in bytes.
+ * @return number of bytes added to the boot config section. -1 for error.
+ */
+int addBootConfigParameters(char *params, uint32_t params_size,
+                            uint64_t bootconfig_start_addr,
+                            uint32_t bootconfig_size);
+/*
+ * Add the boot config trailer to the end of the boot config parameter section.
+ * This can be used after the vendor bootconfig section has been placed into
+ * memory if there are no additional parameters that need to be added.
+ * The new boot config trailer will be written to the end of the entire
+ * parameter section at (bootconfig_start_addr + bootconfig_size).
+ * The trailer contains a 4 byte size of the parameters, followed by a 4 byte
+ * checksum of the parameters, followed by a 12 byte magic string.
+ *
+ * @param bootconfig_start_addr address that the boot config section is starting
+ *        at in memory.
+ * @param bootconfig_size size of the current bootconfig section in bytes.
+ * @return number of bytes added to the boot config section. -1 for error.
+ */
+int addBootConfigTrailer(uint64_t bootconfig_start_addr,
+                         uint32_t bootconfig_size);
+#endif /* LIBXBC_H_ */

lib/sec_library/include/aes.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2017-2021 Alibaba Group Holding Limited
+ * Copyright (C) 2017-2020 Alibaba Group Holding Limited
  */
 
 /******************************************************************************
@@ -14,23 +14,86 @@
 #define _DRV_AES_H_
 
 #include <stdint.h>
-#include <drv/common.h>
+#include "common.h"
 
 #ifdef __cplusplus
 extern "C" {
 #endif
 
 /*----- Encrypt & Decrypt: Config key length -----*/
+#define AES_KEY_LEN_BYTES_32  (32)
+#define AES_KEY_LEN_BYTES_24  (24)
+#define AES_KEY_LEN_BYTES_16  (16)
+
+#define AES_BLOCK_IV_SIZE     (16)
+#define AES_BLOCK_TAG_SIZE    (16)
+#define AES_BLOCK_CRYPTO_SIZE (16)
+
+#define AES_DIR_ENCRYPT       (1)
+#define AES_DIR_DECRYPT       (0)
+
+#define KEY_128_BITS          (0x08)
+#define KEY_192_BITS          (0x10)
+#define KEY_256_BITS          (0x18)
+
+#define AES_DMA_ENABLE        (1)
+#define AES_DMA_DISABLE       (0)
+
+/**
+\brief AES data transfer mode config
+*/
 typedef enum {
-    AES_KEY_LEN_BITS_128        = 0,       ///< 128 Data bits
-    AES_KEY_LEN_BITS_192,                  ///< 192 Data bits
-    AES_KEY_LEN_BITS_256                   ///< 256 Data bits
+    AES_SLAVE_MODE = 0U,         /*slave mode*/
+    AES_DMA_MODE,                /*dma mode*/
+} csi_aes_trans_mode_t;
+
+/**
+\brief AES Keylen type
+*/
+typedef enum {
+    AES_KEY_LEN_BITS_128        = 0,       /*128 Data bits*/
+    AES_KEY_LEN_BITS_192,                  /*192 Data bits*/
+    AES_KEY_LEN_BITS_256                   /*256 Data bits*/
 } csi_aes_key_bits_t;
 
+/**
+\brief AES mode config
+*/
+typedef enum{
+    AES_MODE_ECB = 0,
+    AES_MODE_CBC = 0x20000020,
+    AES_MODE_CTR = 0x200001c0,
+    AES_MODE_CFB = 0x20000400,
+    AES_MODE_GCM = 0x20030040,
+    AES_MODE_CCM = 0x21D40040,
+    AES_MODE_OFB = 0x24000000,
+} csi_aes_mode_t;
+
+/**
+\brief AES state
+*/
+typedef struct {
+    uint32_t busy             : 1;        /*Calculate busy flag*/
+    uint32_t error            : 1;        /*Calculate error flag*/
+} csi_aes_state_t;
+
+/**
+\brief AES Context
+*/
+typedef struct {
+    uint32_t            key_len_byte;
+    uint8_t             key[32];          /*Data block being processed*/
+    uint32_t            sca;
+    uint32_t            is_kdf;
+    uint32_t            is_dma;
+} csi_aes_context_t;
+
 /**
 \brief AES Ctrl Block
 */
 typedef struct {
+    csi_aes_state_t         state;
+    csi_aes_context_t       context;
     csi_dev_t               dev;
     void                    *priv;
 } csi_aes_t;
@@ -97,7 +160,7 @@ csi_error_t csi_aes_ecb_decrypt(csi_aes_t *aes, void *in, void *out, uint32_t si
   \param[in]   iv      Init vector
   \return      Error code \ref Csi_error_t
 */
-csi_error_t csi_aes_cbc_encrypt(csi_aes_t *aes, void *in, void *out, uint32_t size, void *iv);
+csi_error_t csi_aes_cbc_encrypt(csi_aes_t *aes, void *in, void *out, uint32_t size, void *iv) ;
 
 /**
   \brief       AES cbc decrypt
@@ -161,10 +224,9 @@ csi_error_t csi_aes_cfb8_decrypt(csi_aes_t *aes, void *in, void *out, uint32_t s
   \param[out]  out     Pointer to the result data
   \param[in]   size    The source data size
   \param[in]   iv      Init vector
-  \param[out]  num     The number of the 128-bit block we have used
   \return      Error code \ref csi_error_t
 */
-csi_error_t csi_aes_cfb128_decrypt(csi_aes_t *aes, void *in, void *out, uint32_t size, void *iv, uint32_t *num);
+csi_error_t csi_aes_cfb128_decrypt(csi_aes_t *aes, void *in, void *out, uint32_t size, void *iv);
 
 /**
   \brief       AES cfb128 encrypt
@@ -173,10 +235,9 @@ csi_error_t csi_aes_cfb128_decrypt(csi_aes_t *aes, void *in, void *out, uint32_t
   \param[out]  out     Pointer to the result data
   \param[in]   size    The source data size
   \param[in]   iv      Init vector
-  \param[out]  num     The number of the 128-bit block we have used
   \return      Error code \ref csi_error_t
 */
-csi_error_t csi_aes_cfb128_encrypt(csi_aes_t *aes, void *in, void *out, uint32_t size, void *iv, uint32_t *num);
+csi_error_t csi_aes_cfb128_encrypt(csi_aes_t *aes, void *in, void *out, uint32_t size, void *iv);
 
 /**
   \brief       AES ofb encrypt
@@ -185,22 +246,22 @@ csi_error_t csi_aes_cfb128_encrypt(csi_aes_t *aes, void *in, void *out, uint32_t
   \param[out]  out     Pointer to the result data
   \param[in]   size    The source data size
   \param[in]   iv      Init vector
-  \param[out]  num     The number of the 128-bit block we have used
+  \param[in]  key_len key bits
   \return      Error code \ref csi_error_t
 */
-csi_error_t csi_aes_ofb_encrypt(csi_aes_t *aes, void *in, void *out, uint32_t size, void *iv, uint32_t *num);
+csi_error_t csi_aes_ofb_encrypt(csi_aes_t *aes, void *in, void *out, uint32_t size, void *iv);
 
 /**
-  \brief       AES ofb decrypt
-  \param[in]   aes     Handle to operate
-  \param[in]   in      Pointer to the source data
-  \param[out]  out     Pointer to the result data
-  \param[in]   size    The source data size
-  \param[in]   iv      Init vector
-  \param[out]  num     The number of the 128-bit block we have used
-  \return      Error code \ref csi_error_t
+  \brief       Aes ofb decrypt
+  \param[in]   dev_aes     dev_aes handle to operate
+  \param[in]   in      Pointer to the Source data
+  \param[out]  out     Pointer to the Result data
+  \param[in]   size    the Source data size
+  \param[in]   iv      init vector
+  \param[in]  key_len key bits
+  \return      error code \ref csi_error_t
 */
-csi_error_t csi_aes_ofb_decrypt(csi_aes_t *aes, void *in, void *out, uint32_t size, void *iv, uint32_t *num);
+csi_error_t csi_aes_ofb_decrypt(csi_aes_t *aes, void *in, void *out,uint32_t size, void *iv);
 
 /**
   \brief       AES ctr encrypt
@@ -208,20 +269,10 @@ csi_error_t csi_aes_ofb_decrypt(csi_aes_t *aes, void *in, void *out, uint32_t si
   \param[in]   in               Pointer to the source data
   \param[out]  out              Pointer to the result data
   \param[in]   size             The source data size
-  \param[in]   nonce_counter    Pointer to the 128-bit nonce and counter
-  \param[in]   stream_block     Pointer to the saved stream-block for resuming
   \param[in]   iv               Init vector
-  \param[out]  num              The number of the 128-bit block we have used
   \return      Error code \ref csi_error_t
 */
-csi_error_t csi_aes_ctr_encrypt(csi_aes_t *aes,
-                                void *in,
-                                void *out,
-                                uint32_t size,
-                                uint8_t nonce_counter[16],
-                                uint8_t stream_block[16],
-                                void *iv,
-                                uint32_t *num);
+csi_error_t csi_aes_ctr_encrypt(csi_aes_t *aes,void *in,void *out,uint32_t size,void *iv);
 
 /**
   \brief       AES ctr decrypt
@@ -229,20 +280,56 @@ csi_error_t csi_aes_ctr_encrypt(csi_aes_t *aes,
   \param[in]   in               Pointer to the source data
   \param[out]  out              Pointer to the result data
   \param[in]   size             The source data size
-  \param[in]   nonce_counter    Pointer to the 128-bit nonce and counter
-  \param[in]   stream_block     Pointer to the saved stream-block for resuming
   \param[in]   iv               Init vecotr
-  \param[out]  num              The number of the 128-bit block we have used
   \return      Error code \ref csi_error_t
 */
-csi_error_t csi_aes_ctr_decrypt(csi_aes_t *aes,
-                                void *in,
-                                void *out,
-                                uint32_t size,
-                                uint8_t nonce_counter[16],
-                                uint8_t stream_block[16],
-                                void *iv,
-                                uint32_t *num);
+csi_error_t csi_aes_ctr_decrypt(csi_aes_t *aes,void *in,void *out,uint32_t size,void *iv);
+
+/**
+  \brief       Aes gcm encrypt
+  \param[in]   dev_aes              dev_aes handle to operate
+  \param[in]   in               Pointer to the Source data
+  \param[out]  out              Pointer to the Result data
+  \param[in]   size             the Source data size
+  \param[in]   iv               init vector
+  \return      error code \ref csi_error_t
+*/
+csi_error_t csi_aes_gcm_encrypt(csi_aes_t *aes, void *in, void *out,uint32_t size, uint32_t add_len, void *iv);
+
+/**
+  \brief       Aes gcm decrypt
+  \param[in]   dev_aes              dev_aes handle to operate
+  \param[in]   in               Pointer to the Source data.
+  \param[out]  out              Pointer to the Result data
+  \param[in]   size             the Source data size
+  \param[in]   iv               init vecotr
+  \return      error code \ref csi_error_t
+*/
+csi_error_t csi_aes_gcm_decrypt(csi_aes_t *aes, void *in, void *out,uint32_t size, uint32_t add_len, void *iv);
+
+/**
+  \brief       Aes ccm encrypt
+  \param[in]   dev_aes              dev_aes handle to operate
+  \param[in]   in               Pointer to the Source data
+  \param[out]  out              Pointer to the Result data
+  \param[in]   size             the Source data size
+  \param[in]   iv               init vector
+  \param[in]   tag_out          tag output
+  \return      error code \ref csi_error_t
+*/
+csi_error_t csi_aes_ccm_encrypt(csi_aes_t *aes, void *in, void *out,uint32_t size, uint32_t add_len, void *iv, uint8_t *tag_out);
+
+/**
+  \brief       Aes ccm decrypt
+  \param[in]   dev_aes              dev_aes handle to operate
+  \param[in]   in               Pointer to the Source data
+  \param[out]  out              Pointer to the Result data
+  \param[in]   size             the Source data size
+  \param[in]   iv               init vecotr
+  \param[in]   tag_out          tag output
+  \return      error code \ref csi_error_t
+*/
+csi_error_t csi_aes_ccm_decrypt(csi_aes_t *aes, void *in, void *out,uint32_t size, uint32_t add_len, void *iv, uint8_t *tag_out);
 
 /**
   \brief       Enable AES power manage
@@ -258,6 +345,13 @@ csi_error_t csi_aes_enable_pm(csi_aes_t *aes);
 */
 void csi_aes_disable_pm(csi_aes_t *aes);
 
+/**
+  \brief       Config AES data transfer mode
+  \param[in]   mode    \ref csi_des_trans_mode_t 
+  \return      None
+*/
+csi_error_t csi_aes_trans_config(csi_aes_t *aes, csi_aes_trans_mode_t mode);
+
 #ifdef __cplusplus
 }
 #endif

lib/sec_library/include/common.h

@@ -0,0 +1,146 @@
+/*
+ * Copyright (C) 2017-2020 Alibaba Group Holding Limited
+ */
+
+/******************************************************************************
+ * @file     drv/common.h
+ * @brief    Header File for Common Driver
+ * @version  V1.0
+ * @date     31. March 2020
+ * @model    common
+ ******************************************************************************/
+
+#ifndef _DRV_COMMON_H_
+#define _DRV_COMMON_H_
+
+#include <stdint.h>
+#include <stdio.h>
+#include <string.h>
+#include <stdbool.h>
+#include "list.h"
+#include "dev_tag.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef CONFIG_DEBUG_MODE
+#define CSI_ASSERT(expr)                            \
+    do {                                        \
+        if ((unsigned long)expr == (unsigned long)NULL) {   \
+            printf("PROGRAM ASSERT\n");         \
+            while(1);                           \
+        }                                       \
+    } while(0);
+#else
+#define CSI_ASSERT(expr)        ((void)0U)
+#endif
+
+#ifdef CONFIG_PARAM_NOT_CHECK
+#define CSI_PARAM_CHK(para, err)                    \
+    do {                                            \
+        if ((unsigned long)para == (unsigned long)NULL) {       \
+            return (err);                           \
+        }                                           \
+    } while (0)
+
+#define CSI_PARAM_CHK_NORETVAL(para)                \
+    do {                                            \
+        if ((unsigned long)para == (unsigned long)NULL) {       \
+            return;                                 \
+        }                                           \
+    } while (0)
+#else
+#define CSI_PARAM_CHK(para, err)
+#define CSI_PARAM_CHK_NORETVAL(para)
+#endif
+
+#define CSI_EXAMPLE_RESULT(val)                     \
+    do {                                            \
+        if(val>=0)                                  \
+        {                                           \
+            printf("-*success*-\n");                \
+        }                                           \
+        else                                        \
+        {                                           \
+            printf("-*fail*-\n");                   \
+        }                                           \
+    } while (0);
+
+typedef enum {
+    CSI_OK            =  0,
+    CSI_ERROR         = -1,
+    CSI_BUSY          = -2,
+    CSI_TIMEOUT       = -3,
+    CSI_UNSUPPORTED   = -4,
+    CSI_INVALID_PARAM = -5,
+    CSI_CRYPT_FAIL    = -6,
+} csi_error_t;
+
+typedef struct {
+    uint8_t    readable;
+    uint8_t    writeable;
+    uint8_t    error;
+} csi_state_t;
+
+typedef struct csi_dev csi_dev_t;
+
+#ifdef CONFIG_PM
+typedef enum {
+    PM_DEV_SUSPEND,
+    PM_DEV_RESUME,
+} csi_pm_dev_action_t;
+
+typedef enum {
+    PM_MODE_RUN                  = 0,   ///< Running mode
+    PM_MODE_SLEEP_1,                    ///< Sleep LV1 mode
+    PM_MODE_SLEEP_2,                    ///< Sleep LV2 mode
+    PM_MODE_DEEP_SLEEP_1,               ///< Deep sleep LV1 mode
+    PM_MODE_DEEP_SLEEP_2,               ///< Deep sleep LV2 mode
+    PM_MODE_DEEP_SLEEP_3,               ///< Deep sleep LV3 mode
+} csi_pm_mode_t;
+
+typedef struct {
+    slist_t     next;
+    csi_error_t (*pm_action)(csi_dev_t *dev, csi_pm_dev_action_t action);
+    uint32_t    *reten_mem;
+    uint32_t    size;
+} csi_pm_dev_t;
+#include <drv/pm.h>
+#endif
+
+struct csi_dev {
+    unsigned long reg_base;
+    uint8_t       irq_num;
+    uint8_t       idx;
+    uint16_t      dev_tag;
+    void          (*irq_handler)(void *);
+#ifdef CONFIG_PM
+    csi_pm_dev_t pm_dev;
+#endif
+};
+
+#define HANDLE_REG_BASE(handle)     (handle->dev.reg_base)
+#define HANDLE_IRQ_NUM(handle)      (handle->dev.irq_num)
+#define HANDLE_DEV_IDX(handle)      (handle->dev.idx)
+#define HANDLE_IRQ_HANDLER(handle)  (handle->dev.irq_handler)
+
+typedef struct {
+    unsigned long    reg_base;
+    uint8_t          irq_num;
+    uint8_t          idx;
+    uint16_t         dev_tag;
+} csi_perip_info_t;
+
+csi_error_t target_get(csi_dev_tag_t dev_tag, uint32_t idx, csi_dev_t *dev);
+csi_error_t target_get_optimal_dma_channel(void *dma_list, uint32_t ctrl_num, csi_dev_t *parent_dev, void *ch_info);
+// void mdelay(uint32_t ms);
+// void udelay(uint32_t us);
+void msleep(uint32_t ms);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _DRV_COMMON_H_ */
+

lib/sec_library/include/core/README.txt

@@ -0,0 +1 @@
+Just include csi_core.h!

lib/sec_library/include/core/cmsis/ARMCM0.h

@@ -0,0 +1,126 @@
+/**************************************************************************//**
+ * @file     ARMCM0.h
+ * @brief    CMSIS Core Peripheral Access Layer Header File for
+ *           ARMCM0 Device
+ * @version  V5.3.1
+ * @date     09. July 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef ARMCM0_H
+#define ARMCM0_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/* -------------------------  Interrupt Number Definition  ------------------------ */
+
+typedef enum IRQn
+{
+/* -------------------  Processor Exceptions Numbers  ----------------------------- */
+  NonMaskableInt_IRQn           = -14,     /*  2 Non Maskable Interrupt */
+  HardFault_IRQn                = -13,     /*  3 HardFault Interrupt */
+
+
+
+  SVCall_IRQn                   =  -5,     /* 11 SV Call Interrupt */
+
+  PendSV_IRQn                   =  -2,     /* 14 Pend SV Interrupt */
+  SysTick_IRQn                  =  -1,     /* 15 System Tick Interrupt */
+
+/* -------------------  Processor Interrupt Numbers  ------------------------------ */
+  Interrupt0_IRQn               =   0,
+  Interrupt1_IRQn               =   1,
+  Interrupt2_IRQn               =   2,
+  Interrupt3_IRQn               =   3,
+  Interrupt4_IRQn               =   4,
+  Interrupt5_IRQn               =   5,
+  Interrupt6_IRQn               =   6,
+  Interrupt7_IRQn               =   7,
+  Interrupt8_IRQn               =   8,
+  Interrupt9_IRQn               =   9
+  /* Interrupts 10 .. 31 are left out */
+} IRQn_Type;
+
+
+/* ================================================================================ */
+/* ================      Processor and Core Peripheral Section     ================ */
+/* ================================================================================ */
+
+/* -------  Start of section using anonymous unions and disabling warnings  ------- */
+#if   defined (__CC_ARM)
+  #pragma push
+  #pragma anon_unions
+#elif defined (__ICCARM__)
+  #pragma language=extended
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wc11-extensions"
+  #pragma clang diagnostic ignored "-Wreserved-id-macro"
+#elif defined (__GNUC__)
+  /* anonymous unions are enabled by default */
+#elif defined (__TMS470__)
+  /* anonymous unions are enabled by default */
+#elif defined (__TASKING__)
+  #pragma warning 586
+#elif defined (__CSMC__)
+  /* anonymous unions are enabled by default */
+#else
+  #warning Not supported compiler type
+#endif
+
+
+/* --------  Configuration of Core Peripherals  ----------------------------------- */
+#define __CM0_REV                 0x0000U   /* Core revision r0p0 */
+#define __MPU_PRESENT             0U        /* no MPU present */
+#define __VTOR_PRESENT            0U        /* no VTOR present */
+#define __NVIC_PRIO_BITS          2U        /* Number of Bits used for Priority Levels */
+#define __Vendor_SysTickConfig    0U        /* Set to 1 if different SysTick Config is used */
+
+#include "core_cm0.h"                       /* Processor and core peripherals */
+#include "system_ARMCM0.h"                  /* System Header */
+
+
+/* --------  End of section using anonymous unions and disabling warnings  -------- */
+#if   defined (__CC_ARM)
+  #pragma pop
+#elif defined (__ICCARM__)
+  /* leave anonymous unions enabled */
+#elif (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
+  #pragma clang diagnostic pop
+#elif defined (__GNUC__)
+  /* anonymous unions are enabled by default */
+#elif defined (__TMS470__)
+  /* anonymous unions are enabled by default */
+#elif defined (__TASKING__)
+  #pragma warning restore
+#elif defined (__CSMC__)
+  /* anonymous unions are enabled by default */
+#else
+  #warning Not supported compiler type
+#endif
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* ARMCM0_H */

lib/sec_library/include/core/cmsis/cmsis_compiler.h

@@ -0,0 +1,271 @@
+/**************************************************************************//**
+ * @file     cmsis_compiler.h
+ * @brief    CMSIS compiler generic header file
+ * @version  V5.1.0
+ * @date     09. October 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_COMPILER_H
+#define __CMSIS_COMPILER_H
+
+#include <stdint.h>
+
+/*
+ * Arm Compiler 4/5
+ */
+#if   defined ( __CC_ARM )
+  #include "cmsis_armcc.h"
+
+
+/*
+ * Arm Compiler 6.6 LTM (armclang)
+ */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100)
+  #include "cmsis_armclang_ltm.h"
+
+  /*
+ * Arm Compiler above 6.10.1 (armclang)
+ */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100)
+  #include "cmsis_armclang.h"
+
+
+/*
+ * GNU Compiler
+ */
+#elif defined ( __GNUC__ )
+  #include "cmsis_gcc.h"
+
+
+/*
+ * IAR Compiler
+ */
+#elif defined ( __ICCARM__ )
+  #include <cmsis_iccarm.h>
+
+
+/*
+ * TI Arm Compiler
+ */
+#elif defined ( __TI_ARM__ )
+  #include <cmsis_ccs.h>
+
+  #ifndef   __ASM
+    #define __ASM                                  __asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                               inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE                        static inline
+  #endif
+  #ifndef   __STATIC_FORCEINLINE
+    #define __STATIC_FORCEINLINE                   __STATIC_INLINE
+  #endif
+  #ifndef   __NO_RETURN
+    #define __NO_RETURN                            __attribute__((noreturn))
+  #endif
+  #ifndef   __USED
+    #define __USED                                 __attribute__((used))
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                                 __attribute__((weak))
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                               __attribute__((packed))
+  #endif
+  #ifndef   __PACKED_STRUCT
+    #define __PACKED_STRUCT                        struct __attribute__((packed))
+  #endif
+  #ifndef   __PACKED_UNION
+    #define __PACKED_UNION                         union __attribute__((packed))
+  #endif
+  #ifndef   __UNALIGNED_UINT32        /* deprecated */
+    struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT16_WRITE
+    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT16_READ
+    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT32_WRITE
+    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT32_READ
+    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #define __ALIGNED(x)                           __attribute__((aligned(x)))
+  #endif
+  #ifndef   __RESTRICT
+    #define __RESTRICT                             __restrict
+  #endif
+
+
+/*
+ * TASKING Compiler
+ */
+#elif defined ( __TASKING__ )
+  /*
+   * The CMSIS functions have been implemented as intrinsics in the compiler.
+   * Please use "carm -?i" to get an up to date list of all intrinsics,
+   * Including the CMSIS ones.
+   */
+
+  #ifndef   __ASM
+    #define __ASM                                  __asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                               inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE                        static inline
+  #endif
+  #ifndef   __STATIC_FORCEINLINE
+    #define __STATIC_FORCEINLINE                   __STATIC_INLINE
+  #endif
+  #ifndef   __NO_RETURN
+    #define __NO_RETURN                            __attribute__((noreturn))
+  #endif
+  #ifndef   __USED
+    #define __USED                                 __attribute__((used))
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                                 __attribute__((weak))
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                               __packed__
+  #endif
+  #ifndef   __PACKED_STRUCT
+    #define __PACKED_STRUCT                        struct __packed__
+  #endif
+  #ifndef   __PACKED_UNION
+    #define __PACKED_UNION                         union __packed__
+  #endif
+  #ifndef   __UNALIGNED_UINT32        /* deprecated */
+    struct __packed__ T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT16_WRITE
+    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT16_READ
+    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT32_WRITE
+    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT32_READ
+    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #define __ALIGNED(x)              __align(x)
+  #endif
+  #ifndef   __RESTRICT
+    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+    #define __RESTRICT
+  #endif
+
+
+/*
+ * COSMIC Compiler
+ */
+#elif defined ( __CSMC__ )
+   #include <cmsis_csm.h>
+
+ #ifndef   __ASM
+    #define __ASM                                  _asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                               inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE                        static inline
+  #endif
+  #ifndef   __STATIC_FORCEINLINE
+    #define __STATIC_FORCEINLINE                   __STATIC_INLINE
+  #endif
+  #ifndef   __NO_RETURN
+    // NO RETURN is automatically detected hence no warning here
+    #define __NO_RETURN
+  #endif
+  #ifndef   __USED
+    #warning No compiler specific solution for __USED. __USED is ignored.
+    #define __USED
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                                 __weak
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                               @packed
+  #endif
+  #ifndef   __PACKED_STRUCT
+    #define __PACKED_STRUCT                        @packed struct
+  #endif
+  #ifndef   __PACKED_UNION
+    #define __PACKED_UNION                         @packed union
+  #endif
+  #ifndef   __UNALIGNED_UINT32        /* deprecated */
+    @packed struct T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT16_WRITE
+    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT16_READ
+    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT32_WRITE
+    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT32_READ
+    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
+    #define __ALIGNED(x)
+  #endif
+  #ifndef   __RESTRICT
+    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+    #define __RESTRICT
+  #endif
+
+
+#else
+  #error Unknown compiler.
+#endif
+
+
+#endif /* __CMSIS_COMPILER_H */
+

lib/sec_library/include/core/cmsis/cmsis_version.h

@@ -0,0 +1,39 @@
+/**************************************************************************//**
+ * @file     cmsis_version.h
+ * @brief    CMSIS Core(M) Version definitions
+ * @version  V5.0.2
+ * @date     19. April 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CMSIS_VERSION_H
+#define __CMSIS_VERSION_H
+
+/*  CMSIS Version definitions */
+#define __CM_CMSIS_VERSION_MAIN  ( 5U)                                      /*!< [31:16] CMSIS Core(M) main version */
+#define __CM_CMSIS_VERSION_SUB   ( 1U)                                      /*!< [15:0]  CMSIS Core(M) sub version */
+#define __CM_CMSIS_VERSION       ((__CM_CMSIS_VERSION_MAIN << 16U) | \
+                                   __CM_CMSIS_VERSION_SUB           )       /*!< CMSIS Core(M) version number */
+#endif

lib/sec_library/include/core/cmsis/core_cm0.h

@@ -0,0 +1,949 @@
+/**************************************************************************//**
+ * @file     core_cm0.h
+ * @brief    CMSIS Cortex-M0 Core Peripheral Access Layer Header File
+ * @version  V5.0.6
+ * @date     13. March 2019
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM0_H_GENERIC
+#define __CORE_CM0_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_M0
+  @{
+ */
+
+#include "cmsis_version.h"
+ 
+/*  CMSIS CM0 definitions */
+#define __CM0_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)              /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM0_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)               /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __CM0_CMSIS_VERSION       ((__CM0_CMSIS_VERSION_MAIN << 16U) | \
+                                    __CM0_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M                (0U)                                   /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0U
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_FP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM0_H_DEPENDANT
+#define __CORE_CM0_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM0_REV
+    #define __CM0_REV               0x0000U
+    #warning "__CM0_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          2U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M0 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
+    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:1;               /*!< bit:      0  Reserved */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[1U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[31U];
+  __IOM uint32_t ICER[1U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RESERVED1[31U];
+  __IOM uint32_t ISPR[1U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[31U];
+  __IOM uint32_t ICPR[1U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[31U];
+        uint32_t RESERVED4[64U];
+  __IOM uint32_t IP[8U];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+        uint32_t RESERVED0;
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+        uint32_t RESERVED1;
+  __IOM uint32_t SHP[2U];                /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
+            Therefore they are not covered by the Cortex-M0 header file.
+  @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
+
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+/*#define NVIC_GetActive              __NVIC_GetActive             not available for Cortex-M0 */
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */
+#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */
+#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */
+
+
+/* Interrupt Priorities are WORD accessible only under Armv6-M                  */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
+#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
+#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
+
+#define __NVIC_SetPriorityGrouping(X) (void)(X)
+#define __NVIC_GetPriorityGrouping()  (0U)
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+  else
+  {
+    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           Address 0 must be mapped to SRAM.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+  uint32_t vectors = 0x0U;
+  (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+  uint32_t vectors = 0x0U;
+  return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4));
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+    return 0U;           /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */

lib/sec_library/include/core/cmsis/csi_core.h

@@ -0,0 +1,56 @@
+/*
+ * Copyright (C) 2017-2019 Alibaba Group Holding Limited
+ */
+
+
+/******************************************************************************
+ * @file     csi_core.h
+ * @brief    Header File for csi_core
+ * @version  V1.0
+ * @date     12. june 2019
+ ******************************************************************************/
+#ifndef _CSI_CORE_H_
+#define _CSI_CORE_H_
+
+#include <stddef.h>
+#include <cmsis_gcc.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef __GNUC__
+__STATIC_INLINE size_t csi_irq_save(void)
+{
+    uint32_t result;
+    result = __get_PRIMASK();
+    __disable_irq();
+    return (result);
+}
+
+__STATIC_INLINE void csi_irq_restore(size_t irq_state)
+{
+    __set_PRIMASK(irq_state);
+}
+#else
+static inline __asm size_t csi_irq_save(void)
+{
+    MRS     R0, PRIMASK
+    CPSID   I
+    BX      LR
+
+    return 0;
+}
+
+static inline __asm void csi_irq_restore(size_t irq_state)
+{
+    MSR     PRIMASK, R0
+    BX      LR
+}
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _CSI_CORE_H_ */

lib/sec_library/include/core/cmsis/system_ARMCM0.h

@@ -0,0 +1,55 @@
+/**************************************************************************//**
+ * @file     system_ARMCM0.h
+ * @brief    CMSIS Device System Header File for
+ *           ARMCM0 Device
+ * @version  V5.3.1
+ * @date     09. July 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef SYSTEM_ARMCM0_H
+#define SYSTEM_ARMCM0_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+extern uint32_t SystemCoreClock;     /*!< System Clock Frequency (Core Clock) */
+
+
+/**
+  \brief Setup the microcontroller system.
+
+   Initialize the System and update the SystemCoreClock variable.
+ */
+extern void SystemInit (void);
+
+
+/**
+  \brief  Update SystemCoreClock variable.
+
+   Updates the SystemCoreClock with current core Clock retrieved from cpu registers.
+ */
+extern void SystemCoreClockUpdate (void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SYSTEM_ARMCM0_H */

lib/sec_library/include/core/core_810.h

@@ -0,0 +1,873 @@
+/*
+ * Copyright (C) 2017-2019 Alibaba Group Holding Limited
+ */
+
+
+/******************************************************************************
+ * @file     core_ck810.h
+ * @brief    CSI CK810 Core Peripheral Access Layer Header File
+ * @version  V1.0
+ * @date     26. Jan 2018
+ ******************************************************************************/
+
+#ifndef __CORE_CK810_H_GENERIC
+#define __CORE_CK810_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*******************************************************************************
+ *                 CSI definitions
+ ******************************************************************************/
+/**
+  \ingroup CK810
+  @{
+ */
+
+/*  CSI CK810 definitions */
+#define __CK810_CSI_VERSION_MAIN  (0x04U)                                      /*!< [31:16] CSI HAL main version */
+#define __CK810_CSI_VERSION_SUB   (0x1EU)                                      /*!< [15:0]  CSI HAL sub version */
+#define __CK810_CSI_VERSION       ((__CK810_CSI_VERSION_MAIN << 16U) | \
+                                   __CK810_CSI_VERSION_SUB           )         /*!< CSI HAL version number */
+
+#ifndef __CK810
+#define __CK810                (0x0aU)                                         /*!< CK810 Core */
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not.
+*/
+#define __FPU_USED      1U
+
+#if defined ( __GNUC__ )
+#if defined (__VFP_FP__) && !defined(__SOFTFP__)
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CK810_H_GENERIC */
+
+#ifndef __CSI_GENERIC
+
+#ifndef __CORE_CK810_H_DEPENDANT
+#define __CORE_CK810_H_DEPENDANT
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#ifndef __CK810_REV
+#define __CK810_REV               0x0000U
+#endif
+
+#ifndef __GSR_GCR_PRESENT
+#define __GSR_GCR_PRESENT         0U
+#endif
+
+#ifndef __ICACHE_PRESENT
+#define __ICACHE_PRESENT          1U
+#endif
+
+#ifndef __DCACHE_PRESENT
+#define __DCACHE_PRESENT          1U
+#endif
+
+#include <core/csi_gcc.h>
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CSI_glob_defs CSI Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+#define     __I      volatile             /*!< Defines 'read only' permissions */
+#else
+#define     __I      volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O      volatile             /*!< Defines 'write only' permissions */
+#define     __IO     volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const       /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile             /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile             /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group CK810 */
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+ ******************************************************************************/
+/**
+  \defgroup CSI_core_register Defines and Type Definitions
+  \brief Type definitions and defines for CK810 processor based devices.
+*/
+
+/**
+  \ingroup    CSI_core_register
+  \defgroup   CSI_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Access Processor Status Register(PSR)struct definition.
+ */
+typedef union {
+    struct {
+        uint32_t C: 1;                       /*!< bit:      0  Conditional code/Carry flag */
+        uint32_t AF: 1;                      /*!< bit:      1  Alternate register valid control bit */
+        uint32_t _reserved0: 2;              /*!< bit:  2.. 3  Reserved */
+        uint32_t FE: 1;                      /*!< bit:      4  Fast interrupt enable control bit */
+        uint32_t _reserved1: 1;              /*!< bit:      5  Reserved */
+        uint32_t IE: 1;                      /*!< bit:      6  Interrupt effective control bit */
+        uint32_t IC: 1;                      /*!< bit:      7  Interrupt control bit */
+        uint32_t EE: 1;                      /*!< bit:      8  Abnormally effective control bit */
+        uint32_t MM: 1;                      /*!< bit:      9  Unsymmetrical masking bit */
+        uint32_t _reserved2: 2;              /*!< bit: 10..11  Reserved */
+        uint32_t TE: 1;                      /*!< bit:     12  Trace transmission control bit */
+        uint32_t TP: 1;                      /*!< bit:     13  Pending trace exception set bit */
+        uint32_t TM: 2;                      /*!< bit: 14..15  Tracing mode bit */
+        uint32_t VEC: 8;                     /*!< bit: 16..23  Abnormal event vector value */
+        uint32_t _reserved3: 7;              /*!< bit: 24..30  Reserved */
+        uint32_t S: 1;                       /*!< bit:     31  Superuser mode set bit */
+    } b;                                     /*!< Structure    Access by bit */
+    uint32_t w;                              /*!< Type         Access by whole register */
+} PSR_Type;
+
+/* PSR Register Definitions */
+#define PSR_S_Pos                          31U                                            /*!< PSR: S Position */
+#define PSR_S_Msk                          (0x1UL << PSR_S_Pos)                           /*!< PSR: S Mask */
+
+#define PSR_VEC_Pos                        16U                                            /*!< PSR: VEC Position */
+#define PSR_VEC_Msk                        (0xFFUL << PSR_VEC_Pos)                        /*!< PSR: VEC Mask */
+
+#define PSR_TM_Pos                         14U                                            /*!< PSR: TM Position */
+#define PSR_TM_Msk                         (0x3UL << PSR_TM_Pos)                          /*!< PSR: TM Mask */
+
+#define PSR_TP_Pos                         13U                                            /*!< PSR: TP Position */
+#define PSR_TP_Msk                         (0x1UL << PSR_TM_Pos)                          /*!< PSR: TP Mask */
+
+#define PSR_TE_Pos                         12U                                            /*!< PSR: TE Position */
+#define PSR_TE_Msk                         (0x1UL << PSR_TE_Pos)                          /*!< PSR: TE Mask */
+
+#define PSR_MM_Pos                         9U                                             /*!< PSR: MM Position */
+#define PSR_MM_Msk                         (0x1UL << PSR_MM_Pos)                          /*!< PSR: MM Mask */
+
+#define PSR_EE_Pos                         8U                                             /*!< PSR: EE Position */
+#define PSR_EE_Msk                         (0x1UL << PSR_EE_Pos)                          /*!< PSR: EE Mask */
+
+#define PSR_IC_Pos                         7U                                             /*!< PSR: IC Position */
+#define PSR_IC_Msk                         (0x1UL << PSR_IC_Pos)                          /*!< PSR: IC Mask */
+
+#define PSR_IE_Pos                         6U                                             /*!< PSR: IE Position */
+#define PSR_IE_Msk                         (0x1UL << PSR_IE_Pos)                          /*!< PSR: IE Mask */
+
+#define PSR_FE_Pos                         4U                                             /*!< PSR: FE Position */
+#define PSR_FE_Msk                         (0x1UL << PSR_FE_Pos)                          /*!< PSR: FE Mask */
+
+#define PSR_AF_Pos                         1U                                             /*!< PSR: AF Position */
+#define PSR_AF_Msk                         (0x1UL << PSR_AF_Pos)                          /*!< PSR: AF Mask */
+
+#define PSR_C_Pos                          0U                                             /*!< PSR: C Position */
+#define PSR_C_Msk                          (0x1UL << PSR_C_Pos)                           /*!< PSR: C Mask */
+
+/**
+  \brief Consortium definition for accessing Cache Configuration Registers(CCR, CR<18, 0>).
+ */
+typedef union {
+    struct {
+        uint32_t MP: 2;                      /*!< bit:  0.. 1  memory protection settings */
+        uint32_t IE: 1;                      /*!< bit:      2  Instruction cache enable */
+        uint32_t DE: 1;                      /*!< bit:      3  Data cache enable */
+        uint32_t WB: 1;                      /*!< bit:      4  Cache write back */
+        uint32_t RS: 1;                      /*!< bit:      5  Address return stack settings */
+        uint32_t Z: 1;                       /*!< bit:      6  Allow predictive jump bit */
+        uint32_t BE: 1;                      /*!< bit:      7  Endian mode */
+        uint32_t SCK: 3;                     /*!< bit:  8..10  the clock ratio of the system and the processor */
+        uint32_t _reserved0: 1;              /*!< bit:     11  Reserved */
+        uint32_t WA: 1;                      /*!< bit:     12  Write allocate enable */
+        uint32_t E_V2: 1;                    /*!< bit:     13  V2 Endian mode */
+        uint32_t BSTE: 1;                    /*!< bit:     14  Burst transmit enable */
+        uint32_t IPE: 1;                     /*!< bit:     15  Indirect predict enable */
+        uint32_t _reserved1: 16;             /*!< bit: 16..31  Reserved */
+    } b;                                   /*!< Structure    Access by bit */
+    uint32_t w;                            /*!< Type         Access by whole register */
+} CCR_Type;
+
+/* CCR Register Definitions */
+#define CCR_IPE_Pos                       15u                                            /*!< CCR: IPE Position */
+#define CCR_IPE_Msk                       (0x1UL << CCR_IPE_Pos)                         /*!< CCR: IPE Mask */
+
+#define CCR_BSTE_Pos                      14u                                            /*!< CCR: BSTE Position */
+#define CCR_BSTE_Msk                      (0x1UL << CCR_BSTE_Pos)                        /*!< CCR: BSTE Mask */
+
+#define CCR_E_V2_Pos                      13U                                            /*!< CCR: E_V2 Position */
+#define CCR_E_V2_Msk                      (0x1UL << CCR_E_V2_Pos)                        /*!< CCR: E_V2 Mask */
+
+#define CCR_WA_Pos                        12u                                            /*!< CCR: WA Position */
+#define CCR_WA_Msk                        (0x1UL << CCR_WA_Pos)                          /*!< CCR: WA Mask */
+
+#define CCR_SCK_Pos                       8U                                             /*!< CCR: SCK Position */
+#define CCR_SCK_Msk                       (0x3UL << CCR_SCK_Pos)                         /*!< CCR: SCK Mask */
+
+#define CCR_BE_Pos                        7U                                             /*!< CCR: BE Position */
+#define CCR_BE_Msk                        (0x1UL << CCR_BE_Pos)                          /*!< CCR: BE Mask */
+
+#define CCR_Z_Pos                         6U                                             /*!< CCR: Z Position */
+#define CCR_Z_Msk                         (0x1UL << CCR_BE_Pos)                          /*!< CCR: Z Mask */
+
+#define CCR_RS_Pos                        5U                                             /*!< CCR: RS Position */
+#define CCR_RS_Msk                        (0x1UL << CCR_BE_Pos)                          /*!< CCR: RS Mask */
+
+#define CCR_WB_Pos                        4U                                             /*!< CCR: WB Position */
+#define CCR_WB_Msk                        (0x1UL << CCR_BE_Pos)                          /*!< CCR: WB Mask */
+
+#define CCR_DE_Pos                        3U                                             /*!< CCR: DE Position */
+#define CCR_DE_Msk                        (0x1UL << CCR_BE_Pos)                          /*!< CCR: DE Mask */
+
+#define CCR_IE_Pos                        2U                                             /*!< CCR: IE Position */
+#define CCR_IE_Msk                        (0x1UL << CCR_BE_Pos)                          /*!< CCR: IE Mask */
+
+#define CCR_MP_Pos                        0U                                             /*!< CCR: MP Position */
+#define CCR_MP_Msk                        (0x3UL << CCR_MP_Pos)                          /*!< CCR: MP Mask */
+
+/**
+  \brief  Consortium definition for accessing mmu index register(MIR,CR<0,15>).
+ */
+typedef union {
+    struct {
+        uint32_t Index: 10;                  /*!< bit:   0.. 9   TLB index */
+        uint32_t _reserved: 20;              /*!< bit:  10.. 29  Reserved */
+        uint32_t TF: 1;                      /*!< bit:       30  TLB fatal error */
+        uint32_t P: 1;                       /*!< bit:       31  TLBP instruction */
+    } b;
+    uint32_t w;
+} MIR_Type;
+
+/* MIR Register Definitions */
+#define MIR_P_Pos                          31                                            /*!< PRSR: P(TLBP instruction) Position */
+#define MIR_P_Msk                          (0x1UL << MIR_P_Pos)                          /*!< PRSR: P(TLBP instruction) Mask */
+
+#define MIR_TF_Pos                         30                                            /*!< PRSR: Tfatal Position */
+#define MIR_TF_Msk                         (0x1UL << MIR_TF_Pos)                         /*!< PRSR: Tfatal Mask */
+
+#define MIR_Index_Pos                      0                                             /*!< PRSR: Index Position */
+#define MIR_Index_Msk                      (0x3ffUL << MIR_Index_Pos)                    /*!< PRSR: Index Mask */
+
+
+/**
+  \brief  Consortium definition for accessing mmu entry of high physical address register(MEL, CR<2,15> and CR<3,15>).
+ */
+typedef union {
+    struct {
+        uint32_t G: 1;                        /*!< bit:       0   Global enbale bit */
+        uint32_t V: 1;                        /*!< bit:       1   TLB mapping valid bit */
+        uint32_t D: 1;                        /*!< bit:       2   TLB Page dirty bit */
+        uint32_t C: 1;                        /*!< bit:       3   TLB Page cacheable bit */
+        uint32_t SEC: 1;                      /*!< bit:       4   TLB Page security bit */
+        uint32_t SO: 1;                       /*!< bit:       2   Strong order enable bit */
+        uint32_t B: 1;                        /*!< bit:       2   TLB Page bufferable bit */
+        uint32_t _reserved: 5;                /*!< bit:   7.. 11  Reserved */
+        uint32_t PFN: 20;                     /*!< bit:  12.. 31  Physical frame number */
+    } b;
+    uint32_t w;
+} MEL_Type;
+
+/* MEL Register Definitions */
+#define MEL_PFN_Pos                        12                                            /*!< MEL: PFN Position */
+#define MEL_PFN_Msk                        (0xFFFFFUL << MEL_PFN_Pos)                    /*!< MEL: PFN Mask */
+
+#define MEL_B_Pos                          6                                             /*!< MEL: B Position */
+#define MEL_B_Msk                          (0x1UL << MEL_B_Pos)                          /*!< MEL: B Mask */
+
+#define MEL_SO_Pos                         5                                             /*!< MEL: SO Position */
+#define MEL_SO_Msk                         (0x1UL << MEL_SO_Pos)                         /*!< MEL: SO Mask */
+
+#define MEL_SEC_Pos                        4                                             /*!< MEL: SEC Position */
+#define MEL_SEC_Msk                        (0x1UL << MEL_SEC_Pos)                        /*!< MEL: SEC Mask */
+
+#define MEL_C_Pos                          3                                             /*!< MEL: C Position */
+#define MEL_C_Msk                          (0x1UL << MEL_C_Pos)                          /*!< MEL: C Mask */
+
+#define MEL_D_Pos                          2                                             /*!< MEL: D Position */
+#define MEL_D_Msk                          (0x1UL << MIR_D_Pos)                          /*!< MEL: D Mask */
+
+#define MEL_V_Pos                          1                                             /*!< MEL: V Position */
+#define MEL_V_Msk                          (0x1UL << MIR_V_Pos)                          /*!< MEL: V Mask */
+
+#define MEL_G_Pos                          0                                             /*!< MEL: G Position */
+#define MEL_G_Msk                          (0x1UL << MIR_G_Pos)                          /*!< MEL: G Mask */
+
+
+/**
+  \brief  Consortium definition for accessing mmu entry of high physical address register(MEH, CR<4,15>).
+ */
+typedef union {
+    struct {
+        uint32_t ASID :8;                     /*!< bit:   0.. 7   ASID */
+        uint32_t _reserved :4;                /*!< bit:   7.. 10  Reserved */
+        uint32_t VPN :20;                     /*!< bit:  11.. 31  Virtual page number */
+    } b;
+    uint32_t w;
+} MEH_Type;
+
+/* MEH Register Definitions */
+#define MEH_VPN_Pos                        12                                             /*!< MEH: VPN Position */
+#define MEH_VPN_Msk                        (0xFFFFFUL << MEH_VPN_Pos)                     /*!< MEH: VPN Mask */
+
+#define MEH_ASID_Pos                       0                                              /*!< MEH: ASID Position */
+#define MEH_ASID_Msk                       (0xFFUL << MEH_ASID_Pos)                       /*!< MEH: ASID Mask */
+
+
+/**
+  \brief  Consortium definition for accessing mmu entry of high physical address register(MPR, CR<6,15>).
+ */
+typedef union {
+    struct {
+        uint32_t _reserved0: 13;              /*!< bit:   0.. 12   Reserved */
+        uint32_t page_mask: 12;               /*!< bit:  13.. 24   Page mask */
+        uint32_t _reserved1: 7;               /*!< bit:  25.. 31   Reserved */
+    } b;
+    uint32_t w;
+} MPR_Type;
+
+/* MPR Register Definitions */
+#define MPR_PAGE_MASK_Pos                        13                                             /*!< MPR: PAGE_MASK Position */
+#define MPR_PAGE_MASK_Msk                        (0xFFFUL << MPR_PAGE_MASK_Pos)                 /*!< MPR: PAGE_MASK Mask */
+
+
+/**
+  \brief  Consortium definition for accessing mmu entry of high physical address register(CR<8,15>).
+ */
+typedef union {
+    struct {
+        uint32_t ASID: 8;                     /*!< bit:   0.. 7   ASID */
+        uint32_t _reserved: 17;               /*!< bit:   8.. 24  Reserved */
+        uint32_t TLBINV_INDEX: 1;             /*!< bit:       25  TLBINV_INDEX */
+        uint32_t TLBINV_ALL: 1;               /*!< bit:       26  TLBINV_ALL */
+        uint32_t TLBINV: 1;                   /*!< bit:       27  TLBINV */
+        uint32_t TLBWR: 1;                    /*!< bit:       28  TLBWR */
+        uint32_t TLBWI: 1;                    /*!< bit:       29  TLBWI */
+        uint32_t TLBR: 1;                     /*!< bit:       30  TLBR */
+        uint32_t TLBP: 1;                     /*!< bit:       31  TLBP */
+    } b;
+    uint32_t w;
+} MCIR_Type;
+
+/* MCIR Register Definitions */
+#define MCIR_TLBP_Pos                        31                                               /*!< MCIR: TLBP Position */
+#define MCIR_TLBP_Msk                        (0x1UL << MCIR_TLBP_Pos)                         /*!< MCIR: TLBP Mask */
+
+#define MCIR_TLBR_Pos                        30                                               /*!< MCIR: TLBR Position */
+#define MCIR_TLBR_Msk                        (0x1UL << MCIR_TLBR_Pos)                         /*!< MCIR: TLBR Mask */
+
+#define MCIR_TLBWI_Pos                       29                                               /*!< MCIR: TLBWI Position */
+#define MCIR_TLBWI_Msk                       (0x1UL << MCIR_TLBWI_Pos)                        /*!< MCIR: TLBWI Mask */
+
+#define MCIR_TLBWR_Pos                       28                                               /*!< MCIR: TLBWR Position */
+#define MCIR_TLBWR_Msk                       (0x1UL << MCIR_TLBWR_Pos)                        /*!< MCIR: TLBWR Mask */
+
+#define MCIR_TLBINV_Pos                      27                                               /*!< MCIR: TLBINV Position */
+#define MCIR_TLBINV_Msk                      (0x1UL << MCIR_TLBINV_Pos)                       /*!< MCIR: TLBINV Mask */
+
+#define MCIR_TLBINV_ALL_Pos                  26                                               /*!< MCIR: TLBINV_ALL Position */
+#define MCIR_TLBINV_ALL_Msk                  (0x1UL << MCIR_TLBINV_ALL_Pos)                   /*!< MCIR: TLBINV_ALL Mask */
+
+#define MCIR_TLBINV_INDEX_Pos                25                                               /*!< MCIR: TLBINV_INDEX Position */
+#define MCIR_TLBINV_INDEX_Msk                (0x1UL << MCIR_TLBINV_INDEX_Pos)                 /*!< MCIR: TLBINV_INDEX Mask */
+
+#define MCIR_ASID_Pos                        0                                                /*!< MCIR: ASID Position */
+#define MCIR_ASID_Msk                        (0xFFUL << MCIR_ASID_Pos)                        /*!< MCIR: ASID Mask */
+
+
+/*@} end of group CSI_CORE */
+
+
+/**
+  \ingroup    CSI_core_register
+  \defgroup   CSI_CACHE
+  \brief      Type definitions for the cache Registers
+  @{
+ */
+
+/**
+  \brief  Consortium definition for accessing protection area selection register(CFR,CR<17,0>).
+ */
+typedef union {
+    struct {
+        uint32_t CACHE_SEL: 2;                      /*!< bit:  0..1  Instruction and data cache selection */
+        uint32_t _reserved0: 2;                     /*!< bit:  2..3  Reserved */
+        uint32_t INV: 1;                            /*!< bit:     4  Invalid data in cache */
+        uint32_t CLR: 1;                            /*!< bit:     5  Clear the dirty tlb table */
+        uint32_t OMS: 1;                            /*!< bit:     6  Cache invalid and clear operation mode (one line or all line)*/
+        uint32_t ITS: 1;                            /*!< bit:     7  Cache invalid and clear operation mode (CIR used as virtual index or SET/WAY/LEVE index)*/
+        uint32_t UNLOCK: 1;                         /*!< bit:     8  Unclock data cache line. */
+        uint32_t _reserved1: 7;                     /*!< bit: 9..15  Reserved */
+        uint32_t BHT_INV: 1;                        /*!< bit:    16  Invalid data in branch history table */
+        uint32_t BTB_INV: 1;                        /*!< bit:    17  Invalid data in branch table buffer */
+        uint32_t _reserved2: 13;                    /*!< bit: 18..30 Reserved */
+        uint32_t LICF: 1;                           /*!< bit:     31 Failure of clearing or invalid cache line */
+    } b;                                            /*!< Structure    Access by bit */
+    uint32_t w;                                     /*!< Type         Access by whole register */
+} CFR_Type;
+
+#define CFR_LICF_Pos                     31U                                             /*!< CFR: LICF Position */
+#define CFR_LICF_Msk                     (0x1UL << CFR_LICF_Pos)                         /*!< CFR: LICF Mask */
+
+#define CFR_BTB_INV_Pos                  17U                                             /*!< CFR: BTB Position */
+#define CFR_BTB_INV_Msk                  (0x1UL << CFR_BTB_INV_Pos)                      /*!< CFR: BTB Mask */
+
+#define CFR_BHT_INV_Pos                  16U                                             /*!< CFR: BHT Position */
+#define CFR_BHT_INV_Msk                  (0x1UL << CFR_BHT_INV_Pos)                      /*!< CFR: BHT Mask */
+
+#define CFR_UNLOCK_Pos                   8U                                              /*!< CFR: UNLOCK Position */
+#define CFR_UNLOCK_Msk                   (0x1UL << CFR_UNLOCK_Pos)                       /*!< CFR: UNLOCK Mask */
+
+#define CFR_ITS_Pos                      7U                                              /*!< CFR: ITS Position */
+#define CFR_ITS_Msk                      (0x1UL << CFR_ITS_Pos)                          /*!< CFR: ITS Mask */
+
+#define CFR_OMS_Pos                      6U                                              /*!< CFR: OMS Position */
+#define CFR_OMS_Msk                      (0x1UL << CFR_OMS_Pos)                          /*!< CFR: OMS Mask */
+
+#define CFR_CLR_Pos                      5U                                              /*!< CFR: CLR Position */
+#define CFR_CLR_Msk                      (0x1UL << CFR_CLR_Pos)                          /*!< CFR: CLR Mask */
+
+#define CFR_INV_Pos                      4U                                              /*!< CFR: INV Position */
+#define CFR_INV_Msk                      (0x1UL << CFR_INV_Pos)                          /*!< CFR: INV Mask */
+
+#define CFR_CACHE_SEL_Pos                0                                               /*!< CFR: CACHE_SEL Position */    
+#define CFR_CACHE_SEL_Msk                (0x3UL << CFR_CACHE_SEL_Pos)                    /*!< CFR: CACHE_SEL Masok */
+
+/* CFR Register Definitions */
+/*@} end of group CSI_CACHE */
+
+
+/**
+  \ingroup    CSI_core_register
+  \defgroup   CSI_CACHE
+  \brief      Type definitions for the cache Registers
+  @{
+ */
+#define SSEG0_BASE_ADDR         0x80000000
+#define CACHE_RANGE_MAX_SIZE    0x80000
+
+#define INS_CACHE               (1 << 0)
+#define DATA_CACHE              (1 << 1)
+#define CACHE_INV               (1 << 4)
+#define CACHE_CLR               (1 << 5)
+#define CACHE_OMS               (1 << 6)
+#define CACHE_ITS               (1 << 7)
+#define CACHE_LICF              (1 << 31)
+
+#define    L1_CACHE_SHIFT       4      /* 16 Bytes */
+#define    L1_CACHE_BYTES       (1 << L1_CACHE_SHIFT)
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    ((value << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    ((value & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CSI_core_bitfield */
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core VIC Functions
+  - Core CORET Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
+#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
+
+
+/* ##########################  Cache functions  #################################### */
+/**
+  \ingroup  CSI_Core_FunctionInterface
+  \defgroup CSI_Core_CacheFunctions Cache Functions
+  \brief    Functions that configure Instruction and Data cache.
+  @{
+ */
+
+/**
+  \brief   Enable I-Cache
+  \details Turns on I-Cache
+  */
+__STATIC_INLINE void csi_icache_enable (void)
+{
+   __set_CCR(__get_CCR() | 0x00000004);
+}
+
+
+/**
+  \brief   Disable I-Cache
+  \details Turns off I-Cache
+  */
+__STATIC_INLINE void csi_icache_disable (void)
+{
+   __set_CCR(__get_CCR() & 0xFFFFFFFB);
+}
+
+
+/**
+  \brief   Invalidate I-Cache
+  \details Invalidates I-Cache
+  */
+__STATIC_INLINE void csi_icache_invalid (void)
+{
+    __set_CFR(0x11);
+    __set_CFR(INS_CACHE | CACHE_INV);
+}
+
+
+/**
+  \brief   Enable D-Cache
+  \details Turns on D-Cache
+  \note    I-Cache also turns on.
+  */
+__STATIC_INLINE void csi_dcache_enable (void)
+{
+   __set_CCR(__get_CCR() | 0x00000008);
+}
+
+
+/**
+  \brief   Disable D-Cache
+  \details Turns off D-Cache
+  \note    I-Cache also turns off.
+  */
+__STATIC_INLINE void csi_dcache_disable (void)
+{
+   __set_CCR(__get_CCR() & 0xFFFFFFF7);
+}
+
+
+/**
+  \brief   Invalidate D-Cache
+  \details Invalidates D-Cache
+  \note    I-Cache also invalid
+  */
+__STATIC_INLINE void csi_dcache_invalid (void)
+{
+    __set_CFR(DATA_CACHE | CACHE_INV);
+}
+
+
+/**
+  \brief   Clean D-Cache
+  \details Cleans D-Cache
+  \note    I-Cache also cleans
+  */
+__STATIC_INLINE void csi_dcache_clean (void)
+{
+    __set_CFR(DATA_CACHE | CACHE_CLR);
+}
+
+/**
+  \brief   Clean & Invalidate D-Cache
+  \details Cleans and Invalidates D-Cache
+  \note    I-Cache also flush.
+  */
+__STATIC_INLINE void csi_dcache_clean_invalid (void)
+{
+    __set_CFR(DATA_CACHE | CACHE_CLR | CACHE_INV);
+}
+
+__STATIC_INLINE  void set_cache_range (uint32_t start, uint32_t end, uint32_t value)
+{
+    if (!(start & SSEG0_BASE_ADDR) || (end - start) &~(CACHE_RANGE_MAX_SIZE - 1)) {
+        __set_CFR(value);
+    }
+
+    if (value & INS_CACHE) {
+        csi_icache_disable();
+    }
+    uint32_t i;
+    for (i = start; i < end; i += L1_CACHE_BYTES) {
+        __set_CIR(i);
+        __set_CFR(CACHE_OMS | value);
+    }
+
+    if (end & (L1_CACHE_BYTES-1)) {
+        __set_CIR(end);
+        __set_CFR(CACHE_OMS | value);
+    }
+
+    if (value & INS_CACHE) {
+        csi_icache_enable();
+    }
+
+}
+
+/**
+  \brief   D-Cache Invalidate by address
+  \details Invalidates D-Cache for the given address
+  \param[in]   addr    address (aligned to 16-byte boundary)
+  \param[in]   dsize   size of memory block (aligned to 16-byte boundary)
+*/
+__STATIC_INLINE void csi_dcache_invalid_range (uint32_t *addr, int32_t dsize)
+{
+    set_cache_range((uint32_t)addr, (uint32_t)addr + dsize, (DATA_CACHE | CACHE_INV));
+}
+
+
+/**
+  \brief   D-Cache Clean by address
+  \details Cleans D-Cache for the given address
+  \param[in]   addr    address (aligned to 16-byte boundary)
+  \param[in]   dsize   size of memory block (aligned to 16-byte boundary)
+*/
+__STATIC_INLINE void csi_dcache_clean_range (uint32_t *addr, int32_t dsize)
+{
+    set_cache_range((uint32_t)addr, (uint32_t)addr + dsize, (DATA_CACHE | CACHE_CLR));
+}
+
+
+/**
+  \brief   D-Cache Clean and Invalidate by address
+  \details Cleans and invalidates D_Cache for the given address
+  \param[in]   addr    address (aligned to 16-byte boundary)
+  \param[in]   dsize   size of memory block (aligned to 16-byte boundary)
+*/
+__STATIC_INLINE void csi_dcache_clean_invalid_range (uint32_t *addr, int32_t dsize)
+{
+    set_cache_range((uint32_t)addr, (uint32_t)addr + dsize, (DATA_CACHE | CACHE_CLR | CACHE_INV));
+}
+
+
+/*@} end of CSI_Core_CacheFunctions */
+
+/* ##########################  MMU functions  #################################### */
+/**
+  \ingroup  CSI_Core_FunctionInterface
+  \defgroup CSI_Core_MMUFunctions MMU Functions
+  \brief    Functions that configure MMU.
+  @{
+ */
+
+typedef struct {
+    uint32_t global: 1;         /* tlb page global access. */
+    uint32_t valid: 1;          /* tlb page valid */
+    uint32_t writeable: 1;      /* tlb page writeable */
+    uint32_t cacheable: 1;      /* tlb page cacheable*/
+    uint32_t is_secure: 1;      /* tlb page security access */
+    uint32_t strong_order: 1;   /* the sequence of accessing data on tlb page is corresponding to the program flow? */
+    uint32_t bufferable: 1;     /* tlb page bufferable */
+} page_attr_t;
+
+typedef enum {
+    PAGE_SIZE_4KB   = 0x000,
+    PAGE_SIZE_16KB  = 0x003,
+    PAGE_SIZE_64KB  = 0x00F,
+    PAGE_SIZE_256KB = 0x03F,
+    PAGE_SIZE_1MB   = 0x0FF,
+    PAGE_SIZE_4MB   = 0x3FF,
+    PAGE_SIZE_16MB  = 0xFFF
+} page_size_e;
+
+
+/**
+  \brief  enable mmu
+  \details
+  */
+__STATIC_INLINE void csi_mmu_enable(void)
+{
+    __set_CCR(__get_CCR() | (1u << CCR_MP_Pos));
+}
+
+/**
+  \brief  disable mmu
+  \details
+  */
+__STATIC_INLINE void csi_mmu_disable(void)
+{
+    __set_CCR(__get_CCR() & (~(1u << CCR_MP_Pos)));
+}
+
+/**
+  \brief  create page with feature.
+  \details
+  \param [in]  vaddr     virtual address.
+  \param [in]  paddr     physical address.
+  \param [in]  asid      address sapce id (default: 0).
+  \param [in]  attr      \ref page_attr_t. tlb page attribute.
+  */
+__STATIC_INLINE void csi_mmu_set_tlb(uint32_t vaddr, uint32_t paddr, uint32_t asid, page_attr_t attr)
+{
+     MPR_Type pgmask;
+     MEH_Type meh;
+     MEL_Type mel;
+     uint32_t vaddr_bit;
+     uint32_t page_feature = 0;
+
+     page_feature |= attr.global << MEL_G_Pos | attr.valid << MEL_V_Pos |
+                     attr.writeable << MEL_D_Pos | attr.cacheable << MEL_C_Pos |
+                     attr.is_secure << MEL_SEC_Pos | attr.strong_order << MEL_SO_Pos |
+                     attr.bufferable << MEL_B_Pos;
+
+     pgmask.w = __get_MPR();
+     vaddr_bit = 44 - __FF0(~((uint32_t)pgmask.b.page_mask));
+
+     meh.b.ASID = (uint8_t)asid;
+     meh.b.VPN  = (vaddr & ((~pgmask.w | 0xFE000000) & 0xFFFFE000)) >> MEH_VPN_Pos;
+     __set_MEH(meh.w);
+
+     __set_MCIR(1u << MCIR_TLBP_Pos);
+
+     mel.w = ((paddr & ~(pgmask.b.page_mask << 12)) | page_feature);
+     if (vaddr & (1 << vaddr_bit)) {
+         __set_MEL1(mel.w);
+     }
+     else {
+         __set_MEL0(mel.w);
+     }
+
+     if (__get_MIR() & (1 << MIR_P_Pos)) {
+        __set_MCIR(1u << MCIR_TLBWR_Pos);
+     } else {
+        __set_MCIR(1u << MCIR_TLBWI_Pos);
+     }
+}
+
+
+/**
+  \brief  enble mmu
+  \details
+  \param [in]  size  tlb page size.
+  */
+__STATIC_INLINE void csi_mmu_set_pagesize(page_size_e size)
+{
+    MPR_Type pgmask;
+    pgmask.b.page_mask = size;
+    __set_MPR(pgmask.w);
+}
+
+
+/**
+  \brief  read MEH, MEL0, MEL1 by tlb index.
+  \details
+  \param [in]    index  tlb index(0, 1, 2, ...)
+  \param [out]   meh    pointer to variable for retrieving MEH.
+  \param [out]   mel0   pointer to variable for retrieving MEL0.
+  \param [out]   mel1   pointer to variable for retrieving MEL1.
+  */
+__STATIC_INLINE void csi_mmu_read_by_index(uint32_t index, uint32_t *meh, uint32_t *mel0, uint32_t *mel1)
+{
+    MIR_Type mir;
+
+    if (meh == NULL || mel0 == NULL || mel1 == NULL) {
+        return;
+    }
+
+    mir.b.Index = index;
+    __set_MIR(mir.w);
+    __set_MCIR(1u << MCIR_TLBR_Pos);
+
+    *meh = __get_MEH();
+    *mel0 = __get_MEL0();
+    *mel1 = __get_MEL1();
+}
+
+
+/**
+  \brief  flush all mmu tlb.
+  \details
+  */
+__STATIC_INLINE void csi_mmu_invalid_tlb_all(void)
+{
+    __set_MCIR(1u << MCIR_TLBINV_ALL_Pos);
+}
+
+
+/**
+  \brief  flush mmu tlb by index.
+  \details
+  */
+__STATIC_INLINE void csi_mmu_invalid_tlb_by_index(uint32_t index)
+{
+    MIR_Type mir;
+
+    mir.b.Index = index;
+    __set_MIR(mir.w);
+    __set_MCIR(1u << MCIR_TLBINV_INDEX_Pos);
+}
+
+
+/**
+  \brief  flush mmu tlb by virtual address.
+  \details
+  */
+__STATIC_INLINE void csi_mmu_invalid_tlb_by_vaddr(uint32_t vaddr, uint32_t asid)
+{
+    __set_MEH(vaddr | (asid & MEH_ASID_Msk));
+    __set_MCIR(1u << MCIR_TLBP_Pos);
+
+    if (__get_MIR() & (1 << MIR_P_Pos)) {
+        return;
+    } else {
+        __set_MCIR(1u << MCIR_TLBINV_INDEX_Pos);
+    }
+}
+
+/*@} end of CSI_Core_MMUFunctions */
+
+
+/* ##################################    IRQ Functions  ############################################ */
+
+/**
+  \brief   Save the Irq context
+  \details save the psr result before disable irq.
+  \param [in]      irq_num  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE uint32_t csi_irq_save(void)
+{
+    uint32_t result;
+    result = __get_PSR();
+    __disable_irq();
+    return(result);
+}
+
+/**
+  \brief   Restore the Irq context
+  \details restore saved primask state.
+  \param [in]      irq_state  psr irq state.
+ */
+__STATIC_INLINE void csi_irq_restore(uint32_t irq_state)
+{
+    __set_PSR(irq_state);
+}
+
+/*@} end of IRQ Functions */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CK810_H_DEPENDANT */
+
+#endif /* __CSI_GENERIC */

lib/sec_library/include/core/core_ck610.h

@@ -0,0 +1,973 @@
+/*
+ * Copyright (C) 2017-2019 Alibaba Group Holding Limited
+ */
+
+
+/******************************************************************************
+ * @file     core_ck610.h
+ * @brief    CSI CK610 Core Peripheral Access Layer Header File
+ * @version  V1.0
+ * @date     02. June 2017
+ ******************************************************************************/
+
+#ifndef __CORE_CK610_H_GENERIC
+#define __CORE_CK610_H_GENERIC
+
+#include <stdint.h>
+#include <stdio.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*******************************************************************************
+ *                 CSI definitions
+ ******************************************************************************/
+/**
+  \ingroup Ck610
+  @{
+ */
+
+/*  CSI CK610 definitions */
+#define __CK610_CSI_VERSION_MAIN  (0x01U)                                      /*!< [31:16] CSI HAL main version */
+#define __CK610_CSI_VERSION_SUB   (0x1EU)                                      /*!< [15:0]  CSI HAL sub version */
+#define __CK610_CSI_VERSION       ((__CK610_CSI_VERSION_MAIN << 16U) | \
+                                   __CK610_CSI_VERSION_SUB           )         /*!< CSI HAL version number */
+
+#define __CK610                   (0x01U)                                      /*!< CK610 Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       1U
+
+#if defined ( __GNUC__ )
+#if defined (__VFP_FP__) && !defined(__SOFTFP__)
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CK610_H_GENERIC */
+
+#ifndef __CSI_GENERIC
+
+#ifndef __CORE_CK610_H_DEPENDANT
+#define __CORE_CK610_H_DEPENDANT
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#ifndef __CK610_REV
+#define __CK610_REV               0x0000U
+#endif
+
+#ifndef __GSR_GCR_PRESENT
+#define __GSR_GCR_PRESENT         0U
+#endif
+
+#ifndef __MPU_PRESENT
+#define __MPU_PRESENT             0U
+#endif
+
+#ifndef __ICACHE_PRESENT
+#define __ICACHE_PRESENT          1U
+#endif
+
+#ifndef __DCACHE_PRESENT
+#define __DCACHE_PRESENT          1U
+#endif
+
+#include <csi_gcc.h>
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CSI_glob_defs CSI Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+#define     __I      volatile             /*!< Defines 'read only' permissions */
+#else
+#define     __I      volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O      volatile             /*!< Defines 'write only' permissions */
+#define     __IO     volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const       /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile             /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile             /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group CK610 */
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core MGU Register
+  - Core MMU Register
+ ******************************************************************************/
+/**
+  \defgroup CSI_core_register Defines and Type Definitions
+  \brief Type definitions and defines for CK610 processor based devices.
+*/
+
+/**
+  \brief  Access Processor Status Register(PSR)struct definition.
+ */
+typedef union {
+    struct {
+        uint32_t C: 1;                       /*!< bit:      0  Conditional code/Carry flag */
+        uint32_t AF: 1;                      /*!< bit:      1  Alternate register valid control bit */
+        uint32_t _reserved0: 2;              /*!< bit:  2.. 3  Reserved */
+        uint32_t FE: 1;                      /*!< bit:      4  Fast interrupt enable control bit */
+        uint32_t _reserved1: 1;              /*!< bit:      5  Reserved */
+        uint32_t IE: 1;                      /*!< bit:      6  Interrupt effective control bit */
+        uint32_t IC: 1;                      /*!< bit:      7  Interrupt control bit */
+        uint32_t EE: 1;                      /*!< bit:      8  Abnormally effective control bit */
+        uint32_t MM: 1;                      /*!< bit:      9  Unsymmetrical masking bit */
+        uint32_t _reserved2: 2;              /*!< bit: 10..11  Reserved */
+        uint32_t TE: 1;                      /*!< bit:     12  Trace transmission control bit */
+        uint32_t TP: 1;                      /*!< bit:     13  Pending trace exception set bit */
+        uint32_t TM: 2;                      /*!< bit: 14..15  Tracing mode bit */
+        uint32_t VEC: 8;                     /*!< bit: 16..23  Abnormal event vector value */
+        uint32_t CPID: 4;                    /*!< bit: 24..27  Number of processor currently running */
+        uint32_t _reserved3: 3;              /*!< bit: 28..30  Reserved */
+        uint32_t S: 1;                       /*!< bit:     31  Superuser mode set bit */
+    } b;                                     /*!< Structure    Access by bit */
+    uint32_t w;                              /*!< Type         Access by whole register */
+} PSR_Type;
+
+/* PSR Register Definitions */
+#define PSR_S_Pos                          31U                                            /*!< PSR: S Position */
+#define PSR_S_Msk                          (0x1UL << PSR_S_Pos)                           /*!< PSR: S Mask */
+
+#define PSR_CPID_Pos                       24U                                            /*!< PSR: CPID Position */
+#define PSR_CPID_Msk                       (0xFUL << PSR_CPID_Pos)                        /*!< PSR: CPID Mask */
+
+#define PSR_VEC_Pos                        16U                                            /*!< PSR: VEC Position */
+#define PSR_VEC_Msk                        (0xFFUL << PSR_VEC_Pos)                        /*!< PSR: VEC Mask */
+
+#define PSR_TM_Pos                         14U                                            /*!< PSR: TM Position */
+#define PSR_TM_Msk                         (0x3UL << PSR_TM_Pos)                          /*!< PSR: TM Mask */
+
+#define PSR_TP_Pos                         13U                                            /*!< PSR: TP Position */
+#define PSR_TP_Msk                         (0x1UL << PSR_TM_Pos)                          /*!< PSR: TP Mask */
+
+#define PSR_TE_Pos                         12U                                            /*!< PSR: TE Position */
+#define PSR_TE_Msk                         (0x1UL << PSR_TE_Pos)                          /*!< PSR: TE Mask */
+
+#define PSR_MM_Pos                         9U                                             /*!< PSR: MM Position */
+#define PSR_MM_Msk                         (0x1UL << PSR_MM_Pos)                          /*!< PSR: MM Mask */
+
+#define PSR_EE_Pos                         8U                                             /*!< PSR: EE Position */
+#define PSR_EE_Msk                         (0x1UL << PSR_EE_Pos)                          /*!< PSR: EE Mask */
+
+#define PSR_IC_Pos                         7U                                             /*!< PSR: IC Position */
+#define PSR_IC_Msk                         (0x1UL << PSR_IC_Pos)                          /*!< PSR: IC Mask */
+
+#define PSR_IE_Pos                         6U                                             /*!< PSR: IE Position */
+#define PSR_IE_Msk                         (0x1UL << PSR_IE_Pos)                          /*!< PSR: IE Mask */
+
+#define PSR_FE_Pos                         4U                                             /*!< PSR: FE Position */
+#define PSR_FE_Msk                         (0x1UL << PSR_FE_Pos)                          /*!< PSR: FE Mask */
+
+#define PSR_AF_Pos                         1U                                             /*!< PSR: AF Position */
+#define PSR_AF_Msk                         (0x1UL << PSR_AF_Pos)                          /*!< PSR: AF Mask */
+
+#define PSR_C_Pos                          0U                                             /*!< PSR: C Position */
+#define PSR_C_Msk                          (0x1UL << PSR_C_Pos)                           /*!< PSR: C Mask */
+
+/**
+  \brief Consortium definition for accessing Cache Configuration Registers(CCR, CR<18, 0>).
+ */
+typedef union {
+    struct {
+        uint32_t MP: 2;                      /*!< bit:  0..1   Memory protection settings */
+        uint32_t IE: 1;                      /*!< bit:      2  Endian mode */
+        uint32_t DE: 1;                      /*!< bit:      3  Endian mode */
+        uint32_t WB: 1;                      /*!< bit:      4  Endian mode */
+        uint32_t RS: 1;                      /*!< bit:      5  Endian mode */
+        uint32_t Z:  1;                      /*!< bit:      6  Endian mode */
+        uint32_t BE: 1;                      /*!< bit:      7  Endian mode */
+        uint32_t SCK: 3;                     /*!< bit:  8..10  The clock ratio of the system and the processor */
+        uint32_t _reserved0: 21;             /*!< bit:  11..31 Reserved */
+    } b;                                     /*!< Structure    Access by bit */
+    uint32_t w;                              /*!< Type         Access by whole register */
+} CCR_Type;
+
+/* CCR Register Definitions */
+#define CCR_SCK_Pos                        8U                                               /*!< CCR: SCK Position */
+#define CCR_SCK_Msk                        (0x7UL << CCR_SCK_Pos)                           /*!< CCR: SCK Mask */
+
+#define CCR_BE_Pos                         7U                                               /*!< CCR: BE Position */
+#define CCR_BE_Msk                         (0x1UL << CCR_BE_Pos)                            /*!< CCR: BE Mask */
+
+#define CCR_Z_Pos                          6U                                               /*!< CCR: Z Position */
+#define CCR_Z_Msk                          (0x1UL << CCR_Z_Pos)                             /*!< CCR: Z Mask */
+
+#define CCR_RS_Pos                         5U                                               /*!< CCR: RS Position */
+#define CCR_RS_Msk                         (0x1UL << CCR_RS_Pos)                            /*!< CCR: RS Mask */
+
+#define CCR_WB_Pos                         4U                                               /*!< CCR: WB Position */
+#define CCR_WB_Msk                         (0x1UL << CCR_WB_Pos)                            /*!< CCR: WB Mask */
+
+#define CCR_DE_Pos                         3U                                               /*!< CCR: DE Position */
+#define CCR_DE_Msk                         (0x1UL << CCR_DE_Pos)                            /*!< CCR: DE Mask */
+
+#define CCR_IE_Pos                         2U                                               /*!< CCR: IE Position */
+#define CCR_IE_Msk                         (0x1UL << CCR_IE_Pos)                            /*!< CCR: IE Mask */
+
+#define CCR_MP_Pos                         0U                                               /*!< CCR: MP Position */
+#define CCR_MP_Msk                         (0x3UL << CCR_MP_Pos)                            /*!< CCR: MP Mask */
+
+
+/**
+  \brief  Consortium definition for accessing high ease access permission configutation registers(CAPR, CR<19,0>)
+ */
+typedef union {
+    struct {
+        uint32_t C0: 1;                      /*!< bit:      0  Cacheable setting */
+        uint32_t C1: 1;                      /*!< bit:      1  Cacheable setting */
+        uint32_t C2: 1;                      /*!< bit:      2  Cacheable setting */
+        uint32_t C3: 1;                      /*!< bit:      3  Cacheable setting */
+        uint32_t _reserved0: 4;              /*!< bit:  4.. 7  Reserved */
+        uint32_t AP0: 2;                     /*!< bit:  8.. 9  access permissions settings bit */
+        uint32_t AP1: 2;                     /*!< bit: 10..11  access permissions settings bit */
+        uint32_t AP2: 2;                     /*!< bit: 12..13  access permissions settings bit */
+        uint32_t AP3: 2;                     /*!< bit: 14..15  access permissions settings bit */
+        uint32_t _reserved1: 16;             /*!< bit: 16..31  Reserved */
+    } b;                                   /*!< Structure    Access by bit */
+    uint32_t w;                            /*!< Type         Access by whole register */
+} CAPR_Type;
+
+/* CAPR Register Definitions */
+#define CAPR_AP3_Pos                       14U                                            /*!< CAPR: AP3 Position */
+#define CAPR_AP3_Msk                       (0x3UL << CAPR_AP3_Pos)                        /*!< CAPR: AP3 Mask */
+
+#define CAPR_AP2_Pos                       12U                                            /*!< CAPR: AP2 Position */
+#define CAPR_AP2_Msk                       (0x3UL << CAPR_AP2_Pos)                        /*!< CAPR: AP2 Mask */
+
+#define CAPR_AP1_Pos                       10U                                            /*!< CAPR: AP1 Position */
+#define CAPR_AP1_Msk                       (0x3UL << CAPR_AP1_Pos)                        /*!< CAPR: AP1 Mask */
+
+#define CAPR_AP0_Pos                       8U                                             /*!< CAPR: AP0 Position */
+#define CAPR_AP0_Msk                       (0x3UL << CAPR_AP0_Pos)                        /*!< CAPR: AP0 Mask */
+
+#define CAPR_X3_Pos                        3U                                             /*!< CAPR: X3 Position */
+#define CAPR_X3_Msk                        (0x1UL << CAPR_X3_Pos)                         /*!< CAPR: X3 Mask */
+
+#define CAPR_X2_Pos                        2U                                             /*!< CAPR: X2 Position */
+#define CAPR_X2_Msk                        (0x1UL << CAPR_X2_Pos)                         /*!< CAPR: X2 Mask */
+
+#define CAPR_X1_Pos                        1U                                             /*!< CAPR: X1 Position */
+#define CAPR_X1_Msk                        (0x1UL << CAPR_X1_Pos)                         /*!< CAPR: X1 Mask */
+
+#define CAPR_X0_Pos                        0U                                             /*!< CAPR: X0 Position */
+#define CAPR_X0_Msk                        (0x1UL << CAPR_X0_Pos)                         /*!< CAPR: X0 Mask */
+
+
+/**
+  \brief  Consortium definition for accessing control register(PACR, CR<20,0>).
+ */
+typedef union {
+    struct {
+        uint32_t E: 1;                       /*!< bit:      0  Effective setting of protected area */
+        uint32_t size: 5;                    /*!< bit:  1.. 5  Size of protected area */
+        uint32_t _reserved0: 6;              /*!< bit:  6.. 11 Reserved */
+        uint32_t base_addr: 20;              /*!< bit:  10..31 The high position of the address of a protected area */
+    } b;                                     /*!< Structure    Access by bit */
+    uint32_t w;                              /*!< Type         Access by whole register */
+} PACR_Type;
+
+    /* PACR Register Definitions */
+#define PACR_BASE_ADDR_Pos                 12U                                            /*!< PACR: base_addr Position */
+#define PACR_BASE_ADDR_Msk                 (0xFFFFFUL << PACR_BASE_ADDR_Pos)              /*!< PACR: base_addr Mask */
+
+#define PACR_SIZE_Pos                      1U                                             /*!< PACR: Size Position */
+#define PACR_SIZE_Msk                      (0x1FUL << PACR_SIZE_Pos)                      /*!< PACR: Size Mask */
+
+#define PACR_E_Pos                         0U                                             /*!< PACR: E Position */
+#define PACR_E_Msk                         (0x1UL << PACR_E_Pos)                          /*!< PACR: E Mask */
+
+/**
+  \brief  Consortium definition for accessing protection area selection register(PRSR,CR<21,0>).
+ */
+typedef union {
+    struct {
+        uint32_t RID: 2;                     /*!< bit:  0.. 1  Protected area index value */
+        uint32_t _reserved0: 30;             /*!< bit:  2..31  Reserved */
+    } b;                                     /*!< Structure    Access by bit */
+    uint32_t w;                              /*!< Type         Access by whole register */
+} PRSR_Type;
+
+/* PRSR Register Definitions */
+#define PRSR_RID_Pos                       0U                                            /*!< PRSR: RID Position */
+#define PRSR_RID_Msk                       (0x3UL << PRSR_RID_Pos)                       /*!< PRSR: RID Mask */
+
+/**
+  \brief  Consortium definition for accessing mmu index register(MIR,CP15_CR0).
+ */
+typedef union {
+    struct {
+        uint32_t Index: 10;
+        uint32_t _reserved: 20;
+        uint32_t TF: 1;
+        uint32_t P: 1;
+    } b;
+    uint32_t w;
+} MIR_Type;
+
+/* MIR Register Definitions */
+#define MIR_P_Pos                          31                                            /*!< PRSR: P(TLBP instruction) Position */
+#define MIR_P_Msk                          (0x1UL << MIR_P_Pos)                          /*!< PRSR: P(TLBP instruction) Mask */
+
+#define MIR_TF_Pos                         30                                            /*!< PRSR: Tfatal Position */
+#define MIR_TF_Msk                         (0x1UL << MIR_TF_Pos)                         /*!< PRSR: Tfatal Mask */
+
+#define MIR_Index_Pos                      0                                             /*!< PRSR: Index Position */
+#define MIR_Index_Msk                      (0x3ffUL << MIR_Index_Pos)                    /*!< PRSR: Index Mask */
+
+
+/**
+  \brief  Consortium definition for accessing mmu entry of high physical address register(MEL, CP15_CR2 and CP15_CR3).
+ */
+typedef union {
+    struct {
+        uint32_t G: 1;
+        uint32_t V: 1;
+        uint32_t D: 1;
+        uint32_t C: 3;
+        uint32_t PFN: 20;
+        uint32_t _reserved: 6;
+    } b;
+    uint32_t w;
+} MEL_Type;
+
+/* MEL Register Definitions */
+#define MEL_PFN_Pos                        6                                             /*!< MEL: PFN Position */
+#define MEL_PFN_Msk                        (0xFFFFFUL << MEL_PFN_Pos)                    /*!< MEL: PFN Mask */
+
+#define MEL_C_Pos                          3                                             /*!< MEL: C Position */
+#define MEL_C_Msk                          (0x7UL << MEL_C_Pos)                          /*!< MEL: C Mask */
+
+#define MEL_D_Pos                          2                                             /*!< MEL: D Position */
+#define MEL_D_Msk                          (0x1UL << MIR_D_Pos)                          /*!< MEL: D Mask */
+
+#define MEL_V_Pos                          1                                             /*!< MEL: V Position */
+#define MEL_V_Msk                          (0x1UL << MIR_V_Pos)                          /*!< MEL: V Mask */
+
+#define MEL_G_Pos                          0                                             /*!< MEL: G Position */
+#define MEL_G_Msk                          (0x1UL << MIR_G_Pos)                          /*!< MEL: G Mask */
+
+
+/**
+  \brief  Consortium definition for accessing mmu entry of high physical address register(MEH, CP15_CR4).
+ */
+typedef union {
+    struct {
+        uint32_t ASID :8;
+        uint32_t _reserved :4;
+        uint32_t VPN :20;
+    } b;
+    uint32_t w;
+} MEH_Type;
+
+/* MEH Register Definitions */
+#define MEH_VPN_Pos                        12                                             /*!< MEH: VPN Position */
+#define MEH_VPN_Msk                        (0xFFFFFUL << MEH_VPN_Pos)                     /*!< MEH: VPN Mask */
+
+#define MEH_ASID_Pos                       0                                              /*!< MEH: ASID Position */
+#define MEH_ASID_Msk                       (0xFFUL << MEH_ASID_Pos)                       /*!< MEH: ASID Mask */
+
+
+/**
+  \brief  Consortium definition for accessing mmu entry of high physical address register(MPR, CP15_CR6).
+ */
+typedef union {
+    struct {
+        uint32_t _reserved0: 13;
+        uint32_t page_mask: 12;
+        uint32_t _reserved1: 7;
+    } b;
+    uint32_t w;
+} MPR_Type;
+
+/* MPR Register Definitions */
+#define MPR_PAGE_MASK_Pos                        13                                             /*!< MPR: PAGE_MASK Position */
+#define MPR_PAGE_MASK_Msk                        (0xFFFUL << MPR_PAGE_MASK_Pos)                 /*!< MPR: PAGE_MASK Mask */
+
+
+/**
+  \brief  Consortium definition for accessing mmu entry of high physical address register(MCIR, CP15_CR8).
+ */
+typedef union {
+    struct {
+        uint32_t ASID: 8;
+        uint32_t _reserved: 17;
+        uint32_t TLBINV_INDEX: 1;
+        uint32_t TLBINV_ALL: 1;
+        uint32_t TLBINV: 1;
+        uint32_t TLBWR: 1;
+        uint32_t TLBWI: 1;
+        uint32_t TLBR: 1;
+        uint32_t TLBP: 1;
+    } b;
+    uint32_t w;
+} MCIR_Type;
+
+/* MCIR Register Definitions */
+#define MCIR_TLBP_Pos                        31                                               /*!< MCIR: TLBP Position */
+#define MCIR_TLBP_Msk                        (0x1UL << MCIR_TLBP_Pos)                         /*!< MCIR: TLBP Mask */
+
+#define MCIR_TLBR_Pos                        30                                               /*!< MCIR: TLBR Position */
+#define MCIR_TLBR_Msk                        (0x1UL << MCIR_TLBR_Pos)                         /*!< MCIR: TLBR Mask */
+
+#define MCIR_TLBWI_Pos                       29                                               /*!< MCIR: TLBWI Position */
+#define MCIR_TLBWI_Msk                       (0x1UL << MCIR_TLBWI_Pos)                        /*!< MCIR: TLBWI Mask */
+
+#define MCIR_TLBWR_Pos                       28                                               /*!< MCIR: TLBWR Position */
+#define MCIR_TLBWR_Msk                       (0x1UL << MCIR_TLBWR_Pos)                        /*!< MCIR: TLBWR Mask */
+
+#define MCIR_TLBINV_Pos                      27                                               /*!< MCIR: TLBINV Position */
+#define MCIR_TLBINV_Msk                      (0x1UL << MCIR_TLBINV_Pos)                       /*!< MCIR: TLBINV Mask */
+
+#define MCIR_TLBINV_ALL_Pos                  26                                               /*!< MCIR: TLBINV_ALL Position */
+#define MCIR_TLBINV_ALL_Msk                  (0x1UL << MCIR_TLBINV_ALL_Pos)                   /*!< MCIR: TLBINV_ALL Mask */
+
+#define MCIR_TLBINV_INDEX_Pos                25                                               /*!< MCIR: TLBINV_INDEX Position */
+#define MCIR_TLBINV_INDEX_Msk                (0x1UL << MCIR_TLBINV_INDEX_Pos)                 /*!< MCIR: TLBINV_INDEX Mask */
+
+#define MCIR_ASID_Pos                        0                                                /*!< MCIR: ASID Position */
+#define MCIR_ASID_Msk                        (0xFFUL << MCIR_ASID_Pos)                        /*!< MCIR: ASID Mask */
+
+
+/*@} end of group CSI_CORE */
+
+
+/**
+  \ingroup    CSI_core_register
+  \defgroup   CSI_CACHE
+  \brief      Type definitions for the cache Registers
+  @{
+ */
+
+#define SSEG0_BASE_ADDR         0x80000000
+#define CACHE_RANGE_MAX_SIZE    0x80000
+
+#define INS_CACHE               (1 << 0)
+#define DATA_CACHE              (1 << 1)
+#define CACHE_INV               (1 << 4)
+#define CACHE_CLR               (1 << 5)
+#define CACHE_OMS               (1 << 6)
+#define CACHE_ITS               (1 << 7)
+#define CACHE_LICF              (1 << 31)
+
+#define    L1_CACHE_SHIFT       4      /* 16 Bytes */
+#define    L1_CACHE_BYTES       (1 << L1_CACHE_SHIFT)
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    ((value << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    ((value & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CSI_core_bitfield */
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core VIC Functions
+  - Core CORET Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/* ##########################  Cache functions  #################################### */
+/**
+  \ingroup  CSI_Core_FunctionInterface
+  \defgroup CSI_Core_CacheFunctions Cache Functions
+  \brief    Functions that configure Instruction and Data cache.
+  @{
+ */
+
+/**
+  \brief   Enable I-Cache
+  \details Turns on I-Cache
+  */
+__STATIC_INLINE void csi_icache_enable (void)
+{
+   __set_CCR(__get_CCR() | 0x00000004);
+}
+
+
+/**
+  \brief   Disable I-Cache
+  \details Turns off I-Cache
+  */
+__STATIC_INLINE void csi_icache_disable (void)
+{
+   __set_CCR(__get_CCR() & 0xFFFFFFFB);
+}
+
+
+/**
+  \brief   Invalidate I-Cache
+  \details Invalidates I-Cache
+  */
+__STATIC_INLINE void csi_icache_invalid (void)
+{
+    __set_CFR(0x11);
+    __set_CFR(INS_CACHE | CACHE_INV);
+}
+
+
+/**
+  \brief   Enable D-Cache
+  \details Turns on D-Cache
+  \note    I-Cache also turns on.
+  */
+__STATIC_INLINE void csi_dcache_enable (void)
+{
+   __set_CCR(__get_CCR() | 0x00000008);
+}
+
+
+/**
+  \brief   Disable D-Cache
+  \details Turns off D-Cache
+  \note    I-Cache also turns off.
+  */
+__STATIC_INLINE void csi_dcache_disable (void)
+{
+   __set_CCR(__get_CCR() & 0xFFFFFFF7);
+}
+
+
+/**
+  \brief   Invalidate D-Cache
+  \details Invalidates D-Cache
+  \note    I-Cache also invalid
+  */
+__STATIC_INLINE void csi_dcache_invalid (void)
+{
+    __set_CFR(DATA_CACHE | CACHE_INV);
+}
+
+
+/**
+  \brief   Clean D-Cache
+  \details Cleans D-Cache
+  \note    I-Cache also cleans
+  */
+__STATIC_INLINE void csi_dcache_clean (void)
+{
+    __set_CFR(DATA_CACHE | CACHE_CLR);
+}
+
+
+/**
+  \brief   Clean & Invalidate D-Cache
+  \details Cleans and Invalidates D-Cache
+  \note    I-Cache also flush.
+  */
+__STATIC_INLINE void csi_dcache_clean_invalid (void)
+{
+    __set_CFR(DATA_CACHE | CACHE_CLR | CACHE_INV);
+}
+
+__STATIC_INLINE  void set_cache_range (uint32_t start, uint32_t end, uint32_t value)
+{
+    if (!(start & SSEG0_BASE_ADDR) || (end - start) &~(CACHE_RANGE_MAX_SIZE - 1)) {
+        __set_CFR(value);
+    }
+
+    if (value & INS_CACHE) {
+        csi_icache_disable();
+    }
+    uint32_t i;
+    for (i = start; i < end; i += L1_CACHE_BYTES) {
+        __set_CIR(i);
+        __set_CFR(CACHE_OMS | value);
+    }
+
+    if (end & (L1_CACHE_BYTES-1)) {
+        __set_CIR(end);
+        __set_CFR(CACHE_OMS | value);
+    }
+
+    if (value & INS_CACHE) {
+        csi_icache_enable();
+    }
+
+}
+
+/**
+  \brief   D-Cache Invalidate by address
+  \details Invalidates D-Cache for the given address
+  \param[in]   addr    address (aligned to 16-byte boundary)
+  \param[in]   dsize   size of memory block (in number of bytes)
+*/
+__STATIC_INLINE void csi_dcache_invalid_range (uint32_t *addr, int32_t dsize)
+{
+    set_cache_range((uint32_t)addr, (uint32_t)addr + dsize, (DATA_CACHE | CACHE_INV));
+}
+
+
+/**
+  \brief   D-Cache Clean by address
+  \details Cleans D-Cache for the given address
+  \param[in]   addr    address (aligned to 16-byte boundary)
+  \param[in]   dsize   size of memory block (in number of bytes)
+*/
+__STATIC_INLINE void csi_dcache_clean_range (uint32_t *addr, int32_t dsize)
+{
+    set_cache_range((uint32_t)addr, (uint32_t)addr + dsize, (DATA_CACHE | CACHE_CLR));
+}
+
+
+/**
+  \brief   D-Cache Clean and Invalidate by address
+  \details Cleans and invalidates D_Cache for the given address
+  \param[in]   addr    address (aligned to 16-byte boundary)
+  \param[in]   dsize   size of memory block (in number of bytes)
+*/
+__STATIC_INLINE void csi_dcache_clean_invalid_range (uint32_t *addr, int32_t dsize)
+{
+    set_cache_range((uint32_t)addr, (uint32_t)addr + dsize, (DATA_CACHE | CACHE_CLR | CACHE_INV));
+}
+
+/*@} end of CSI_Core_CacheFunctions */
+
+
+/* ##########################  MMU functions  #################################### */
+/**
+  \ingroup  CSI_Core_FunctionInterface
+  \defgroup CSI_Core_MMUFunctions MMU Functions
+  \brief    Functions that configure MMU.
+  @{
+ */
+
+typedef struct {
+    uint32_t global: 1;         /* tlb page global access. */
+    uint32_t valid: 1;          /* tlb page valid */
+    uint32_t writeable: 1;      /* tlb page writeable */
+    uint32_t cacheable: 1;      /* tlb page cacheable*/
+} page_attr_t;
+
+typedef enum {
+    PAGE_SIZE_4KB   = 0x000,
+    PAGE_SIZE_16KB  = 0x003,
+    PAGE_SIZE_64KB  = 0x00F,
+    PAGE_SIZE_256KB = 0x03F,
+    PAGE_SIZE_1MB   = 0x0FF,
+    PAGE_SIZE_4MB   = 0x3FF,
+    PAGE_SIZE_16MB  = 0xFFF
+} page_size_e;
+
+/**
+  \brief  enable mmu
+  \details
+  */
+__STATIC_INLINE void csi_mmu_enable(void)
+{
+    __set_CCR(__get_CCR() | (1u << CCR_MP_Pos));
+}
+
+/**
+  \brief  disable mmu
+  \details
+  */
+__STATIC_INLINE void csi_mmu_disable(void)
+{
+    __set_CCR(__get_CCR() & (~(1u << CCR_MP_Pos)));
+}
+
+/**
+  \brief  create page with feature.
+  \details
+  \param [in]  vaddr     virtual address.
+  \param [in]  paddr     physical address.
+  \param [in]  asid      address sapce id (default: 0).
+  \param [in]  attr      \ref page_attr_t. tlb page attribute.
+  */
+__STATIC_INLINE void csi_mmu_set_tlb(uint32_t vaddr, uint32_t paddr, uint32_t asid, page_attr_t attr)
+{
+    MPR_Type pgmask;
+    MEL_Type mel;
+    MEH_Type meh;
+    uint32_t vaddr_bit = 0;
+    uint32_t page_feature = 0;
+
+    page_feature |= attr.global << MEL_G_Pos | attr.valid << MEL_V_Pos |
+                    attr.writeable << MEL_D_Pos | (attr.cacheable | 0x2) << MEL_C_Pos;
+
+    pgmask.w = __FF1(__get_MPR());
+    vaddr_bit = (pgmask.w == 32 ? 12 : (31 - pgmask.w));
+
+    meh.b.ASID = asid;
+    meh.b.VPN  = (vaddr & ((~pgmask.w | 0xFE000000) & 0xFFFFE000)) >> MEH_VPN_Pos;
+    __set_MEH(meh.w);
+
+    __set_MCIR(1u << MCIR_TLBP_Pos);
+
+    mel.w = (((paddr >> 6) & ~(pgmask.b.page_mask << 6)) | page_feature);
+
+    if (vaddr & (1 << vaddr_bit)) {
+        __set_MEL1(mel.w);
+    } else {
+        __set_MEL0(mel.w);
+    }
+
+    if (__get_MIR() & (1 << MIR_P_Pos)) {
+       __set_MCIR(1u << MCIR_TLBWR_Pos);
+    } else {
+       __set_MCIR(1u << MCIR_TLBWI_Pos);
+    }
+}
+
+
+/**
+  \brief  enble mmu
+  \details
+  \param [in]  size  tlb page size.
+  */
+__STATIC_INLINE void csi_mmu_set_pagesize(page_size_e size)
+{
+    MPR_Type mpr;
+    mpr.w = __get_MPR();
+    mpr.b.page_mask = size;
+    __set_MPR(mpr.w);
+}
+
+
+/**
+  \brief  read MEH, MEL0, MEL1 by tlb index.
+  \details
+  \param [in]    index  tlb index(0, 1, 2, ...)
+  \param [out]   meh    pointer to variable for retrieving MEH.
+  \param [out]   mel0   pointer to variable for retrieving MEL0.
+  \param [out]   mel1   pointer to variable for retrieving MEL1.
+  */
+__STATIC_INLINE void csi_mmu_read_by_index(uint32_t index, uint32_t *meh, uint32_t *mel0, uint32_t *mel1)
+{
+    MIR_Type mir;
+
+    if (meh == NULL || mel0 == NULL || mel1 == NULL) {
+        return;
+    }
+
+    mir.b.Index = index;
+    __set_MIR(mir.w);
+    __set_MCIR(1u << MCIR_TLBR_Pos);
+
+    *meh = __get_MEH();
+    *mel0 = __get_MEL0();
+    *mel1 = __get_MEL1();
+}
+
+
+/**
+  \brief  flush all mmu tlb.
+  \details
+  */
+__STATIC_INLINE void csi_mmu_invalid_tlb_all(void)
+{
+    __set_MCIR(1u << MCIR_TLBINV_ALL_Pos);
+}
+
+
+/**
+  \brief  flush mmu tlb by index.
+  \details
+  */
+__STATIC_INLINE void csi_mmu_invalid_tlb_by_index(uint32_t index)
+{
+    MIR_Type mir;
+
+    mir.b.Index = index;
+    __set_MIR(mir.w);
+    __set_MCIR(1u << MCIR_TLBINV_INDEX_Pos);
+}
+
+
+/**
+  \brief  flush mmu tlb by virtual address.
+  \details
+  */
+__STATIC_INLINE void csi_mmu_invalid_tlb_by_vaddr(uint32_t vaddr, uint32_t asid)
+{
+    __set_MEH(vaddr | (asid & MEH_ASID_Msk));
+    __set_MCIR(__get_MCIR() | (1 << MCIR_TLBP_Pos));
+
+    if (__get_MIR() & (1 << MIR_P_Pos)) {
+        return;
+    } else {
+        __set_MCIR(__get_MCIR() | (1 << MCIR_TLBINV_INDEX_Pos));
+    }
+}
+
+/*@} end of CSI_Core_MMUFunctions */
+
+/* ##########################  MPU functions  #################################### */
+/**
+  \ingroup  CSI_Core_FunctionInterface
+  \defgroup CSI_Core_MPUFunctions MPU Functions
+  \brief    Functions that configure MPU.
+  @{
+ */
+
+typedef enum {
+    REGION_SIZE_4KB      = 0xB,
+    REGION_SIZE_8KB      = 0xC,
+    REGION_SIZE_16KB     = 0xD,
+    REGION_SIZE_32KB     = 0xE,
+    REGION_SIZE_64KB     = 0xF,
+    REGION_SIZE_128KB    = 0x10,
+    REGION_SIZE_256KB    = 0x11,
+    REGION_SIZE_512KB    = 0x12,
+    REGION_SIZE_1MB      = 0x13,
+    REGION_SIZE_2MB      = 0x14,
+    REGION_SIZE_4MB      = 0x15,
+    REGION_SIZE_8MB      = 0x16,
+    REGION_SIZE_16MB     = 0x17,
+    REGION_SIZE_32MB     = 0x18,
+    REGION_SIZE_64MB     = 0x19,
+    REGION_SIZE_128MB    = 0x1A,
+    REGION_SIZE_256MB    = 0x1B,
+    REGION_SIZE_512MB    = 0x1C,
+    REGION_SIZE_1GB      = 0x1D,
+    REGION_SIZE_2GB      = 0x1E,
+    REGION_SIZE_4GB      = 0x1F
+} region_size_e;
+
+typedef enum {
+    AP_BOTH_INACCESSIBLE = 0,
+    AP_SUPER_RW_USER_INACCESSIBLE,
+    AP_SUPER_RW_USER_RDONLY,
+    AP_BOTH_RW
+} access_permission_e;
+
+typedef struct {
+    access_permission_e ap: 2;    /* super user and normal user access.*/
+    uint32_t c: 1;                /* cacheable */
+} mpu_region_attr_t;
+/**
+  \brief  enable mpu
+  \details
+  */
+__STATIC_INLINE void csi_mpu_enable(void)
+{
+    __set_CCR(__get_CCR() | CCR_MP_Msk);
+}
+
+/**
+  \brief  disable mpu
+  \details
+  */
+__STATIC_INLINE void csi_mpu_disable(void)
+{
+    __set_CCR(__get_CCR() & (~CCR_MP_Msk));
+}
+
+/**
+  \brief  configure memory protected region.
+  \details
+  \param [in]  idx        memory protected region (0, 1, 2, 3.).
+  \param [in]  base_addr  base address must be aligned with page size.
+  \param [in]  size       \ref region_size_e. memory protected region size.
+  \param [in]  attr       \ref region_size_t. memory protected region attribute.
+  \param [in]  enable     enable or disable memory protected region.
+  */
+__STATIC_INLINE void csi_mpu_config_region(uint32_t idx, uint32_t base_addr, region_size_e size,
+                                           mpu_region_attr_t attr, uint32_t enable)
+{
+    if (idx > 3) {
+        return;
+    }
+
+    CAPR_Type capr;
+    PACR_Type pacr;
+    PRSR_Type prsr;
+
+    capr.w = __get_CAPR();
+    pacr.w = __get_PACR();
+    prsr.w = __get_PRSR();
+
+    pacr.b.base_addr = (base_addr >> PACR_BASE_ADDR_Pos) & (0xFFFFF);
+
+    prsr.b.RID = idx;
+    __set_PRSR(prsr.w);
+
+    if (size != REGION_SIZE_4KB) {
+        pacr.w &= ~(((1u << (size -11)) - 1) << 12);
+    }
+
+    pacr.b.size = size;
+
+    capr.w = (0xFFFFFFFE & capr.w) | (attr.c << idx);
+    capr.w = ((~((0x3) << (2*idx + 8))) & capr.w) | (attr.ap << (2*idx + 8));
+    __set_CAPR(capr.w);
+
+    pacr.b.E = enable;
+    __set_PACR(pacr.w);
+}
+
+/**
+  \brief  enable mpu region by idx.
+  \details
+  \param [in]  idx        memory protected region (0, 1, 2, 3.).
+  */
+__STATIC_INLINE void csi_mpu_enable_region(uint32_t idx)
+{
+    if (idx > 3) {
+        return;
+    }
+
+    __set_PRSR((__get_PRSR() & (~PRSR_RID_Msk)) | idx);
+    __set_PACR(__get_PACR() | PACR_E_Msk);
+}
+
+/**
+  \brief  disable mpu region by idx.
+  \details
+  \param [in]  idx        memory protected region (0, 1, 2, 3.).
+  */
+__STATIC_INLINE void csi_mpu_disable_region(uint32_t idx)
+{
+    if (idx > 3) {
+        return;
+    }
+
+    __set_PRSR((__get_PRSR() & (~PRSR_RID_Msk)) | idx);
+    __set_PACR(__get_PACR() & (~PACR_E_Msk));
+}
+
+/*@} end of CSI_Core_MMUFunctions */
+
+/*@} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CK610_H_DEPENDANT */
+
+#endif /* __CSI_GENERIC */

lib/sec_library/include/core/core_ck801.h

@@ -0,0 +1,18 @@
+/*
+ * Copyright (C) 2017-2019 Alibaba Group Holding Limited
+ */
+
+
+/******************************************************************************
+ * @file     core_ck801.h
+ * @brief    CSI CK801 Core Peripheral Access Layer Header File
+ * @version  V1.0
+ * @date     02. June 2017
+ ******************************************************************************/
+
+#ifndef __CORE_CK801_H_GENERIC
+#define __CORE_CK801_H_GENERIC
+
+#include <core_801.h>
+
+#endif /* __CORE_CK801_H_DEPENDANT */

lib/sec_library/include/core/core_ck802.h

@@ -0,0 +1,18 @@
+/*
+ * Copyright (C) 2017-2019 Alibaba Group Holding Limited
+ */
+
+
+/******************************************************************************
+ * @file     core_ck802.h
+ * @brief    CSI CK802 Core Peripheral Access Layer Header File
+ * @version  V1.0
+ * @date     02. June 2017
+ ******************************************************************************/
+
+#ifndef __CORE_CK802_H_GENERIC
+#define __CORE_CK802_H_GENERIC
+
+#include <core_802.h>
+
+#endif /* __CORE_CK802_H_DEPENDANT */

lib/sec_library/include/core/core_ck803.h

@@ -0,0 +1,18 @@
+/*
+ * Copyright (C) 2017-2019 Alibaba Group Holding Limited
+ */
+
+
+/******************************************************************************
+ * @file     core_ck803.h
+ * @brief    CSI CK803 Core Peripheral Access Layer Header File
+ * @version  V1.0
+ * @date     02. June 2017
+ ******************************************************************************/
+
+#ifndef __CORE_CK803_H_GENERIC
+#define __CORE_CK803_H_GENERIC
+
+#include <core_803.h>
+
+#endif /* __CORE_CK803_H_DEPENDANT */

lib/sec_library/include/core/core_ck807.h

@@ -0,0 +1,847 @@
+/*
+ * Copyright (C) 2017-2019 Alibaba Group Holding Limited
+ */
+
+
+/******************************************************************************
+ * @file     core_ck807.h
+ * @brief    CSI CK807 Core Peripheral Access Layer Header File
+ * @version  V1.0
+ * @date     26. Jan 2018
+ ******************************************************************************/
+
+#ifndef __CORE_CK807_H_GENERIC
+#define __CORE_CK807_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*******************************************************************************
+ *                 CSI definitions
+ ******************************************************************************/
+/**
+  \ingroup CK807
+  @{
+ */
+
+/*  CSI CK807 definitions */
+#define __CK807_CSI_VERSION_MAIN  (0x04U)                                      /*!< [31:16] CSI HAL main version */
+#define __CK807_CSI_VERSION_SUB   (0x1EU)                                      /*!< [15:0]  CSI HAL sub version */
+#define __CK807_CSI_VERSION       ((__CK807_CSI_VERSION_MAIN << 16U) | \
+                                   __CK807_CSI_VERSION_SUB           )         /*!< CSI HAL version number */
+
+#ifndef __CK807
+#define __CK807                   (0x07U)                                      /*!< CK807 Core */
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not.
+*/
+#define __FPU_USED       1U
+
+#if defined ( __GNUC__ )
+#if defined (__VFP_FP__) && !defined(__SOFTFP__)
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CK807_H_GENERIC */
+
+#ifndef __CSI_GENERIC
+
+#ifndef __CORE_CK807_H_DEPENDANT
+#define __CORE_CK807_H_DEPENDANT
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#ifndef __CK807_REV
+#define __CK807_REV               0x0000U
+#endif
+
+#ifndef __GSR_GCR_PRESENT
+#define __GSR_GCR_PRESENT         0U
+#endif
+
+#ifndef __ICACHE_PRESENT
+#define __ICACHE_PRESENT          1U
+#endif
+
+#ifndef __DCACHE_PRESENT
+#define __DCACHE_PRESENT          1U
+#endif
+
+#include <csi_gcc.h>
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CSI_glob_defs CSI Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+#define     __I      volatile             /*!< Defines 'read only' permissions */
+#else
+#define     __I      volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O      volatile             /*!< Defines 'write only' permissions */
+#define     __IO     volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const       /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile             /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile             /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group CK807 */
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+ ******************************************************************************/
+/**
+  \defgroup CSI_core_register Defines and Type Definitions
+  \brief Type definitions and defines for CK807 processor based devices.
+*/
+
+/**
+  \ingroup    CSI_core_register
+  \defgroup   CSI_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Access Processor Status Register(PSR)struct definition.
+ */
+typedef union {
+    struct {
+        uint32_t C: 1;                       /*!< bit:      0  Conditional code/Carry flag */
+        uint32_t _reserved0: 5;              /*!< bit:  2.. 5  Reserved */
+        uint32_t IE: 1;                      /*!< bit:      6  Interrupt effective control bit */
+        uint32_t IC: 1;                      /*!< bit:      7  Interrupt control bit */
+        uint32_t EE: 1;                      /*!< bit:      8  Abnormally effective control bit */
+        uint32_t MM: 1;                      /*!< bit:      9  Unsymmetrical masking bit */
+        uint32_t _reserved1: 6;              /*!< bit: 10..15  Reserved */
+        uint32_t VEC: 8;                     /*!< bit: 16..23  Abnormal event vector value */
+        uint32_t _reserved2: 5;              /*!< bit: 24..28  Reserved */
+        uint32_t SP: 1;                      /*!< bit:     29  Secure pedning bit */
+        uint32_t T: 1;                       /*!< bit:     30  TEE mode bit */
+        uint32_t S: 1;                       /*!< bit:     31  Superuser mode set bit */
+    } b;                                   /*!< Structure    Access by bit */
+    uint32_t w;                            /*!< Type         Access by whole register */
+} PSR_Type;
+
+/* PSR Register Definitions */
+#define PSR_S_Pos                          31U                                            /*!< PSR: S Position */
+#define PSR_S_Msk                          (1UL << PSR_S_Pos)                             /*!< PSR: S Mask */
+
+#define PSR_VEC_Pos                        16U                                            /*!< PSR: VEC Position */
+#define PSR_VEC_Msk                        (0x7FUL << PSR_VEC_Pos)                        /*!< PSR: VEC Mask */
+
+#define PSR_MM_Pos                         9U                                             /*!< PSR: MM Position */
+#define PSR_MM_Msk                         (1UL << PSR_MM_Pos)                            /*!< PSR: MM Mask */
+
+#define PSR_EE_Pos                         8U                                             /*!< PSR: EE Position */
+#define PSR_EE_Msk                         (1UL << PSR_EE_Pos)                            /*!< PSR: EE Mask */
+
+#define PSR_IC_Pos                         7U                                             /*!< PSR: IC Position */
+#define PSR_IC_Msk                         (1UL << PSR_IC_Pos)                            /*!< PSR: IC Mask */
+
+#define PSR_IE_Pos                         6U                                             /*!< PSR: IE Position */
+#define PSR_IE_Msk                         (1UL << PSR_IE_Pos)                            /*!< PSR: IE Mask */
+
+#define PSR_C_Pos                          0U                                             /*!< PSR: C Position */
+#define PSR_C_Msk                          (1UL << PSR_C_Pos)                             /*!< PSR: C Mask */
+
+/**
+  \brief Consortium definition for accessing Cache Configuration Registers(CCR, CR<18, 0>).
+ */
+typedef union {
+    struct {
+        uint32_t MP: 2;                      /*!< bit:  0.. 1  memory protection settings */
+        uint32_t IE: 1;                      /*!< bit:      2  Instruction cache enable */
+        uint32_t DE: 1;                      /*!< bit:      3  Data cache enable */
+        uint32_t WB: 1;                      /*!< bit:      4  Cache write back */
+        uint32_t RS: 1;                      /*!< bit:      5  Address return stack settings */
+        uint32_t Z: 1;                       /*!< bit:      6  Allow predictive jump bit */
+        uint32_t BE: 1;                      /*!< bit:      7  Endian mode */
+        uint32_t SCK: 3;                     /*!< bit:  8..10  the clock ratio of the system and the processor */
+        uint32_t _reserved0: 1;              /*!< bit:     11  Reserved */
+        uint32_t WA: 1;                      /*!< bit:     12  Write allocate enable */
+        uint32_t E_V2: 1;                    /*!< bit:     13  V2 Endian mode */
+        uint32_t BSTE: 1;                    /*!< bit:     14  Burst transmit enable */
+        uint32_t IPE: 1;                     /*!< bit:     15  Indirect predict enable */
+        uint32_t _reserved1: 16;             /*!< bit: 16..31  Reserved */
+    } b;                                   /*!< Structure    Access by bit */
+    uint32_t w;                            /*!< Type         Access by whole register */
+} CCR_Type;
+
+/* CCR Register Definitions */
+#define CCR_IPE_Pos                       15u                                            /*!< CCR: IPE Position */
+#define CCR_IPE_Msk                       (0x1UL << CCR_IPE_Pos)                         /*!< CCR: IPE Mask */
+
+#define CCR_BSTE_Pos                      14u                                            /*!< CCR: BSTE Position */
+#define CCR_BSTE_Msk                      (0x1UL << CCR_BSTE_Pos)                        /*!< CCR: BSTE Mask */
+
+#define CCR_E_V2_Pos                      13U                                            /*!< CCR: E_V2 Position */
+#define CCR_E_V2_Msk                      (0x1UL << CCR_E_V2_Pos)                        /*!< CCR: E_V2 Mask */
+
+#define CCR_WA_Pos                        12u                                            /*!< CCR: WA Position */
+#define CCR_WA_Msk                        (0x1UL << CCR_WA_Pos)                          /*!< CCR: WA Mask */
+
+#define CCR_SCK_Pos                       8U                                             /*!< CCR: SCK Position */
+#define CCR_SCK_Msk                       (0x3UL << CCR_SCK_Pos)                         /*!< CCR: SCK Mask */
+
+#define CCR_BE_Pos                        7U                                             /*!< CCR: BE Position */
+#define CCR_BE_Msk                        (0x1UL << CCR_BE_Pos)                          /*!< CCR: BE Mask */
+
+#define CCR_Z_Pos                         6U                                             /*!< CCR: Z Position */
+#define CCR_Z_Msk                         (0x1UL << CCR_BE_Pos)                          /*!< CCR: Z Mask */
+
+#define CCR_RS_Pos                        5U                                             /*!< CCR: RS Position */
+#define CCR_RS_Msk                        (0x1UL << CCR_BE_Pos)                          /*!< CCR: RS Mask */
+
+#define CCR_WB_Pos                        4U                                             /*!< CCR: WB Position */
+#define CCR_WB_Msk                        (0x1UL << CCR_BE_Pos)                          /*!< CCR: WB Mask */
+
+#define CCR_DE_Pos                        3U                                             /*!< CCR: DE Position */
+#define CCR_DE_Msk                        (0x1UL << CCR_BE_Pos)                          /*!< CCR: DE Mask */
+
+#define CCR_IE_Pos                        2U                                             /*!< CCR: IE Position */
+#define CCR_IE_Msk                        (0x1UL << CCR_BE_Pos)                          /*!< CCR: IE Mask */
+
+#define CCR_MP_Pos                        0U                                             /*!< CCR: MP Position */
+#define CCR_MP_Msk                        (0x3UL << CCR_MP_Pos)                          /*!< CCR: MP Mask */
+
+/**
+  \brief  Consortium definition for accessing mmu index register(MIR,CR<0,15>).
+ */
+typedef union {
+    struct {
+        uint32_t Index: 10;                  /*!< bit:   0.. 9   TLB index */
+        uint32_t _reserved: 20;              /*!< bit:  10.. 29  Reserved */
+        uint32_t TF: 1;                      /*!< bit:       30  TLB fatal error */
+        uint32_t P: 1;                       /*!< bit:       31  TLBP instruction */
+    } b;
+    uint32_t w;
+} MIR_Type;
+
+/* MIR Register Definitions */
+#define MIR_P_Pos                          31                                            /*!< PRSR: P(TLBP instruction) Position */
+#define MIR_P_Msk                          (0x1UL << MIR_P_Pos)                          /*!< PRSR: P(TLBP instruction) Mask */
+
+#define MIR_TF_Pos                         30                                            /*!< PRSR: Tfatal Position */
+#define MIR_TF_Msk                         (0x1UL << MIR_TF_Pos)                         /*!< PRSR: Tfatal Mask */
+
+#define MIR_Index_Pos                      0                                             /*!< PRSR: Index Position */
+#define MIR_Index_Msk                      (0x3ffUL << MIR_Index_Pos)                    /*!< PRSR: Index Mask */
+
+
+/**
+  \brief  Consortium definition for accessing mmu entry of high physical address register(MEL, CR<2,15> and CR<3,15>).
+ */
+typedef union {
+    struct {
+        uint32_t G: 1;                        /*!< bit:       0   Global enbale bit */
+        uint32_t V: 1;                        /*!< bit:       1   TLB mapping valid bit */
+        uint32_t D: 1;                        /*!< bit:       2   TLB Page dirty bit */
+        uint32_t C: 1;                        /*!< bit:       3   TLB Page cacheable bit */
+        uint32_t SEC: 1;                      /*!< bit:       4   TLB Page security bit */
+        uint32_t SO: 1;                       /*!< bit:       2   Strong order enable bit */
+        uint32_t B: 1;                        /*!< bit:       2   TLB Page bufferable bit */
+        uint32_t _reserved: 5;                /*!< bit:   7.. 11  Reserved */
+        uint32_t PFN: 20;                     /*!< bit:  12.. 31  Physical frame number */
+    } b;
+    uint32_t w;
+} MEL_Type;
+
+/* MEL Register Definitions */
+#define MEL_PFN_Pos                        12                                            /*!< MEL: PFN Position */
+#define MEL_PFN_Msk                        (0xFFFFFUL << MEL_PFN_Pos)                    /*!< MEL: PFN Mask */
+
+#define MEL_B_Pos                          6                                             /*!< MEL: B Position */
+#define MEL_B_Msk                          (0x1UL << MEL_B_Pos)                          /*!< MEL: B Mask */
+
+#define MEL_SO_Pos                         5                                             /*!< MEL: SO Position */
+#define MEL_SO_Msk                         (0x1UL << MEL_SO_Pos)                         /*!< MEL: SO Mask */
+
+#define MEL_SEC_Pos                        4                                             /*!< MEL: SEC Position */
+#define MEL_SEC_Msk                        (0x1UL << MEL_SEC_Pos)                        /*!< MEL: SEC Mask */
+
+#define MEL_C_Pos                          3                                             /*!< MEL: C Position */
+#define MEL_C_Msk                          (0x1UL << MEL_C_Pos)                          /*!< MEL: C Mask */
+
+#define MEL_D_Pos                          2                                             /*!< MEL: D Position */
+#define MEL_D_Msk                          (0x1UL << MIR_D_Pos)                          /*!< MEL: D Mask */
+
+#define MEL_V_Pos                          1                                             /*!< MEL: V Position */
+#define MEL_V_Msk                          (0x1UL << MIR_V_Pos)                          /*!< MEL: V Mask */
+
+#define MEL_G_Pos                          0                                             /*!< MEL: G Position */
+#define MEL_G_Msk                          (0x1UL << MIR_G_Pos)                          /*!< MEL: G Mask */
+
+
+/**
+  \brief  Consortium definition for accessing mmu entry of high physical address register(MEH, CR<4,15>).
+ */
+typedef union {
+    struct {
+        uint32_t ASID :8;                     /*!< bit:   0.. 7   ASID */
+        uint32_t _reserved :4;                /*!< bit:   7.. 10  Reserved */
+        uint32_t VPN :20;                     /*!< bit:  11.. 31  Virtual page number */
+    } b;
+    uint32_t w;
+} MEH_Type;
+
+/* MEH Register Definitions */
+#define MEH_VPN_Pos                        12                                             /*!< MEH: VPN Position */
+#define MEH_VPN_Msk                        (0xFFFFFUL << MEH_VPN_Pos)                     /*!< MEH: VPN Mask */
+
+#define MEH_ASID_Pos                       0                                              /*!< MEH: ASID Position */
+#define MEH_ASID_Msk                       (0xFFUL << MEH_ASID_Pos)                       /*!< MEH: ASID Mask */
+
+
+/**
+  \brief  Consortium definition for accessing mmu entry of high physical address register(MPR, CR<6,15>). 
+*/
+
+typedef union {
+    struct {
+        uint32_t _reserved0: 13;              /*!< bit:   0.. 12   Reserved */
+        uint32_t page_mask: 12;               /*!< bit:  13.. 24   Page mask */
+        uint32_t _reserved1: 7;               /*!< bit:  25.. 31   Reserved */
+    } b;
+    uint32_t w;
+} MPR_Type;
+
+/* MPR Register Definitions */
+#define MPR_PAGE_MASK_Pos                        13                                             /*!< MPR: PAGE_MASK Position */
+#define MPR_PAGE_MASK_Msk                        (0xFFFUL << MPR_PAGE_MASK_Pos)                 /*!< MPR: PAGE_MASK Mask */
+
+
+/**
+  \brief  Consortium definition for accessing mmu entry of high physical address register(CR<8,15>).
+ */
+typedef union {
+    struct {
+        uint32_t ASID: 8;                     /*!< bit:   0.. 7   ASID */
+        uint32_t _reserved: 17;               /*!< bit:   8.. 24  Reserved */
+        uint32_t TLBINV_INDEX: 1;             /*!< bit:       25  TLBINV_INDEX */
+        uint32_t TLBINV_ALL: 1;               /*!< bit:       26  TLBINV_ALL */
+        uint32_t TLBINV: 1;                   /*!< bit:       27  TLBINV */
+        uint32_t TLBWR: 1;                    /*!< bit:       28  TLBWR */
+        uint32_t TLBWI: 1;                    /*!< bit:       29  TLBWI */
+        uint32_t TLBR: 1;                     /*!< bit:       30  TLBR */
+        uint32_t TLBP: 1;                     /*!< bit:       31  TLBP */
+    } b;
+    uint32_t w;
+} MCIR_Type;
+
+/* MCIR Register Definitions */
+#define MCIR_TLBP_Pos                        31                                               /*!< MCIR: TLBP Position */
+#define MCIR_TLBP_Msk                        (0x1UL << MCIR_TLBP_Pos)                         /*!< MCIR: TLBP Mask */
+
+#define MCIR_TLBR_Pos                        30                                               /*!< MCIR: TLBR Position */
+#define MCIR_TLBR_Msk                        (0x1UL << MCIR_TLBR_Pos)                         /*!< MCIR: TLBR Mask */
+
+#define MCIR_TLBWI_Pos                       29                                               /*!< MCIR: TLBWI Position */
+#define MCIR_TLBWI_Msk                       (0x1UL << MCIR_TLBWI_Pos)                        /*!< MCIR: TLBWI Mask */
+
+#define MCIR_TLBWR_Pos                       28                                               /*!< MCIR: TLBWR Position */
+#define MCIR_TLBWR_Msk                       (0x1UL << MCIR_TLBWR_Pos)                        /*!< MCIR: TLBWR Mask */
+
+#define MCIR_TLBINV_Pos                      27                                               /*!< MCIR: TLBINV Position */
+#define MCIR_TLBINV_Msk                      (0x1UL << MCIR_TLBINV_Pos)                       /*!< MCIR: TLBINV Mask */
+
+#define MCIR_TLBINV_ALL_Pos                  26                                               /*!< MCIR: TLBINV_ALL Position */
+#define MCIR_TLBINV_ALL_Msk                  (0x1UL << MCIR_TLBINV_ALL_Pos)                   /*!< MCIR: TLBINV_ALL Mask */
+
+#define MCIR_TLBINV_INDEX_Pos                25                                               /*!< MCIR: TLBINV_INDEX Position */
+#define MCIR_TLBINV_INDEX_Msk                (0x1UL << MCIR_TLBINV_INDEX_Pos)                 /*!< MCIR: TLBINV_INDEX Mask */
+
+#define MCIR_ASID_Pos                        0                                                /*!< MCIR: ASID Position */
+#define MCIR_ASID_Msk                        (0xFFUL << MCIR_ASID_Pos)                        /*!< MCIR: ASID Mask */
+
+
+/*@} end of group CSI_CORE */
+
+
+/**
+  \ingroup    CSI_core_register
+  \defgroup   CSI_CACHE
+  \brief      Type definitions for the cache Registers
+  @{
+ */
+
+/**
+  \brief  Consortium definition for accessing protection area selection register(CFR,CR<17,0>).
+ */
+typedef union {
+    struct {
+        uint32_t CACHE_SEL: 2;                      /*!< bit:  0..1  Instruction and data cache selection */
+        uint32_t _reserved0: 2;                     /*!< bit:  2..3  Reserved */
+        uint32_t INV: 1;                            /*!< bit:     4  Invalid data in cache */
+        uint32_t CLR: 1;                            /*!< bit:     5  Clear the dirty tlb table */
+        uint32_t OMS: 1;                            /*!< bit:     6  Cache invalid and clear operation mode (one line or all line)*/
+        uint32_t ITS: 1;                            /*!< bit:     7  Cache invalid and clear operation mode (CIR used as virtual index or SET/WAY/LEVE index)*/
+        uint32_t _reserved1: 8;                     /*!< bit: 8..15  Reserved */
+        uint32_t BHT_INV: 1;                        /*!< bit:    16  Invalid data in branch history table */
+        uint32_t _reserved2: 14;                    /*!< bit: 17..30 Reserved */
+        uint32_t LICF: 1;                           /*!< bit:     31 Failure of clearing or invalid cache line */
+    } b;                                            /*!< Structure    Access by bit */
+    uint32_t w;                                     /*!< Type         Access by whole register */
+} CFR_Type;
+
+#define CFR_LICF_Pos                     31U                                             /*!< CFR: LICF Position */
+#define CFR_LICF_Msk                     (0x1UL << CFR_LICF_Pos)                         /*!< CFR: LICF Mask */
+
+#define CFR_BHT_INV_Pos                  16U                                             /*!< CFR: BHT Position */
+#define CFR_BHT_INV_Msk                  (0x1UL << CFR_BHT_INV_Pos)                      /*!< CFR: BHT Mask */
+
+#define CFR_ITS_Pos                      7U                                              /*!< CFR: ITS Position */
+#define CFR_ITS_Msk                      (0x1UL << CFR_ITS_Pos)                          /*!< CFR: ITS Mask */
+
+#define CFR_OMS_Pos                      6U                                              /*!< CFR: OMS Position */
+#define CFR_OMS_Msk                      (0x1UL << CFR_OMS_Pos)                          /*!< CFR: OMS Mask */
+
+#define CFR_CLR_Pos                      5U                                              /*!< CFR: CLR Position */
+#define CFR_CLR_Msk                      (0x1UL << CFR_CLR_Pos)                          /*!< CFR: CLR Mask */
+
+#define CFR_INV_Pos                      4U                                              /*!< CFR: INV Position */
+#define CFR_INV_Msk                      (0x1UL << CFR_INV_Pos)                          /*!< CFR: INV Mask */
+
+#define CFR_CACHE_SEL_Pos                0                                               /*!< CFR: CACHE_SEL Position */    
+#define CFR_CACHE_SEL_Msk                (0x3UL << CFR_CACHE_SEL_Pos)                    /*!< CFR: CACHE_SEL Masok */
+
+/* CFR Register Definitions */
+/*@} end of group CSI_CACHE */
+
+
+/**
+  \ingroup    CSI_core_register
+  \defgroup   CSI_CACHE
+  \brief      Type definitions for the cache Registers
+  @{
+ */
+#define SSEG0_BASE_ADDR         0x80000000
+#define CACHE_RANGE_MAX_SIZE    0x80000
+
+#define INS_CACHE               (1 << 0)
+#define DATA_CACHE              (1 << 1)
+#define CACHE_INV               (1 << 4)
+#define CACHE_CLR               (1 << 5)
+#define CACHE_OMS               (1 << 6)
+#define CACHE_ITS               (1 << 7)
+#define CACHE_LICF              (1 << 31)
+
+#define    L1_CACHE_SHIFT       4      /* 16 Bytes */
+#define    L1_CACHE_BYTES       (1 << L1_CACHE_SHIFT)
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    ((value << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    ((value & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CSI_core_bitfield */
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core VIC Functions
+  - Core CORET Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
+#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
+
+
+/* ##########################  Cache functions  #################################### */
+/**
+  \ingroup  CSI_Core_FunctionInterface
+  \defgroup CSI_Core_CacheFunctions Cache Functions
+  \brief    Functions that configure Instruction and Data cache.
+  @{
+ */
+
+/**
+  \brief   Enable I-Cache
+  \details Turns on I-Cache
+  */
+__STATIC_INLINE void csi_icache_enable (void)
+{
+   __set_CCR(__get_CCR() | 0x00000004);
+}
+
+
+/**
+  \brief   Disable I-Cache
+  \details Turns off I-Cache
+  */
+__STATIC_INLINE void csi_icache_disable (void)
+{
+   __set_CCR(__get_CCR() & 0xFFFFFFFB);
+}
+
+
+/**
+  \brief   Invalidate I-Cache
+  \details Invalidates I-Cache
+  */
+__STATIC_INLINE void csi_icache_invalid (void)
+{
+    __set_CFR(0x11);
+    __set_CFR(INS_CACHE | CACHE_INV);
+}
+
+
+/**
+  \brief   Enable D-Cache
+  \details Turns on D-Cache
+  \note    I-Cache also turns on.
+  */
+__STATIC_INLINE void csi_dcache_enable (void)
+{
+   __set_CCR(__get_CCR() | 0x00000008);
+}
+
+
+/**
+  \brief   Disable D-Cache
+  \details Turns off D-Cache
+  \note    I-Cache also turns off.
+  */
+__STATIC_INLINE void csi_dcache_disable (void)
+{
+   __set_CCR(__get_CCR() & 0xFFFFFFF7);
+}
+
+
+/**
+  \brief   Invalidate D-Cache
+  \details Invalidates D-Cache
+  \note    I-Cache also invalid
+  */
+__STATIC_INLINE void csi_dcache_invalid (void)
+{
+    __set_CFR(DATA_CACHE | CACHE_INV);
+}
+
+
+/**
+  \brief   Clean D-Cache
+  \details Cleans D-Cache
+  \note    I-Cache also cleans
+  */
+__STATIC_INLINE void csi_dcache_clean (void)
+{
+    __set_CFR(DATA_CACHE | CACHE_CLR);
+}
+
+/**
+  \brief   Clean & Invalidate D-Cache
+  \details Cleans and Invalidates D-Cache
+  \note    I-Cache also flush.
+  */
+__STATIC_INLINE void csi_dcache_clean_invalid (void)
+{
+    __set_CFR(DATA_CACHE | CACHE_CLR | CACHE_INV);
+}
+
+__STATIC_INLINE  void set_cache_range (uint32_t start, uint32_t end, uint32_t value)
+{
+    if (!(start & SSEG0_BASE_ADDR) || (end - start) &~(CACHE_RANGE_MAX_SIZE - 1)) {
+        __set_CFR(value);
+    }
+
+    if (value & INS_CACHE) {
+        csi_icache_disable();
+    }
+    uint32_t i;
+    for (i = start; i < end; i += L1_CACHE_BYTES) {
+        __set_CIR(i);
+        __set_CFR(CACHE_OMS | value);
+    }
+
+    if (end & (L1_CACHE_BYTES-1)) {
+        __set_CIR(end);
+        __set_CFR(CACHE_OMS | value);
+    }
+
+    if (value & INS_CACHE) {
+        csi_icache_enable();
+    }
+
+}
+
+/**
+  \brief   D-Cache Invalidate by address
+  \details Invalidates D-Cache for the given address
+  \param[in]   addr    address (aligned to 16-byte boundary)
+  \param[in]   dsize   size of memory block (in number of bytes)
+*/
+__STATIC_INLINE void csi_dcache_invalid_range (uint32_t *addr, int32_t dsize)
+{
+    set_cache_range((uint32_t)addr, (uint32_t)addr + dsize, (DATA_CACHE | CACHE_INV));
+}
+
+
+/**
+  \brief   D-Cache Clean by address
+  \details Cleans D-Cache for the given address
+  \param[in]   addr    address (aligned to 16-byte boundary)
+  \param[in]   dsize   size of memory block (in number of bytes)
+*/
+__STATIC_INLINE void csi_dcache_clean_range (uint32_t *addr, int32_t dsize)
+{
+    set_cache_range((uint32_t)addr, (uint32_t)addr + dsize, (DATA_CACHE | CACHE_CLR));
+}
+
+
+/**
+  \brief   D-Cache Clean and Invalidate by address
+  \details Cleans and invalidates D_Cache for the given address
+  \param[in]   addr    address (aligned to 16-byte boundary)
+  \param[in]   dsize   size of memory block (in number of bytes)
+*/
+__STATIC_INLINE void csi_dcache_clean_invalid_range (uint32_t *addr, int32_t dsize)
+{
+    set_cache_range((uint32_t)addr, (uint32_t)addr + dsize, (DATA_CACHE | CACHE_CLR | CACHE_INV));
+}
+
+
+/*@} end of CSI_Core_CacheFunctions */
+
+
+/* ##########################  MMU functions  #################################### */
+/**
+  \ingroup  CSI_Core_FunctionInterface
+  \defgroup CSI_Core_MMUFunctions MMU Functions
+  \brief    Functions that configure MMU.
+  @{
+ */
+
+typedef struct {
+    uint32_t global: 1;         /* tlb page global access. */
+    uint32_t valid: 1;          /* tlb page valid */
+    uint32_t writeable: 1;      /* tlb page writeable */
+    uint32_t cacheable: 1;      /* tlb page cacheable*/
+    uint32_t is_secure: 1;      /* tlb page security access */
+    uint32_t strong_order: 1;   /* the sequence of accessing data on tlb page is corresponding to the program flow? */
+    uint32_t bufferable: 1;     /* tlb page bufferable */
+} page_attr_t;
+
+typedef enum {
+    PAGE_SIZE_4KB   = 0x000,
+    PAGE_SIZE_16KB  = 0x003,
+    PAGE_SIZE_64KB  = 0x00F,
+    PAGE_SIZE_256KB = 0x03F,
+    PAGE_SIZE_1MB   = 0x0FF,
+    PAGE_SIZE_4MB   = 0x3FF,
+    PAGE_SIZE_16MB  = 0xFFF
+} page_size_e;
+
+
+/**
+  \brief  enable mmu
+  \details
+  */
+__STATIC_INLINE void csi_mmu_enable(void)
+{
+    __set_CCR(__get_CCR() | (1u << CCR_MP_Pos));
+}
+
+/**
+  \brief  disable mmu
+  \details
+  */
+__STATIC_INLINE void csi_mmu_disable(void)
+{
+    __set_CCR(__get_CCR() & (~(1u << CCR_MP_Pos)));
+}
+
+/**
+  \brief  create page with feature.
+  \details
+  \param [in]  vaddr     virtual address.
+  \param [in]  paddr     physical address.
+  \param [in]  asid      address sapce id (default: 0).
+  \param [in]  attr      \ref page_attr_t. tlb page attribute.
+  */
+__STATIC_INLINE void csi_mmu_set_tlb(uint32_t vaddr, uint32_t paddr, uint32_t asid, page_attr_t attr)
+{
+     MPR_Type pgmask;
+     MEH_Type meh;
+     MEL_Type mel;
+     uint32_t vaddr_bit;
+     uint32_t page_feature = 0;
+
+     page_feature |= attr.global << MEL_G_Pos | attr.valid << MEL_V_Pos |
+                     attr.writeable << MEL_D_Pos | attr.cacheable << MEL_C_Pos |
+                     attr.is_secure << MEL_SEC_Pos | attr.strong_order << MEL_SO_Pos |
+                     attr.bufferable << MEL_B_Pos;
+
+     pgmask.w = __get_MPR();
+     vaddr_bit = 44 - __FF0(~((uint32_t)pgmask.b.page_mask));
+
+     meh.b.ASID = (uint8_t)asid;
+     meh.b.VPN  = (vaddr & ((~pgmask.w | 0xFE000000) & 0xFFFFE000)) >> MEH_VPN_Pos;
+     __set_MEH(meh.w);
+
+     __set_MCIR(1u << MCIR_TLBP_Pos);
+
+     mel.w = ((paddr & ~(pgmask.b.page_mask << 12)) | page_feature);
+     if (vaddr & (1 << vaddr_bit)) {
+         __set_MEL1(mel.w);
+     }
+     else {
+         __set_MEL0(mel.w);
+     }
+
+     if (__get_MIR() & (1 << MIR_P_Pos)) {
+        __set_MCIR(1u << MCIR_TLBWR_Pos);
+     } else {
+        __set_MCIR(1u << MCIR_TLBWI_Pos);
+     }
+}
+
+
+/**
+  \brief  enble mmu
+  \details
+  \param [in]  size  tlb page size.
+  */
+__STATIC_INLINE void csi_mmu_set_pagesize(page_size_e size)
+{
+    MPR_Type pgmask;
+    pgmask.b.page_mask = size;
+    __set_MPR(pgmask.w);
+}
+
+
+/**
+  \brief  read MEH, MEL0, MEL1 by tlb index.
+  \details
+  \param [in]    index  tlb index(0, 1, 2, ...)
+  \param [out]   meh    pointer to variable for retrieving MEH.
+  \param [out]   mel0   pointer to variable for retrieving MEL0.
+  \param [out]   mel1   pointer to variable for retrieving MEL1.
+  */
+__STATIC_INLINE void csi_mmu_read_by_index(uint32_t index, uint32_t *meh, uint32_t *mel0, uint32_t *mel1)
+{
+    MIR_Type mir;
+
+    if (meh == NULL || mel0 == NULL || mel1 == NULL) {
+        return;
+    }
+
+    mir.b.Index = index;
+    __set_MIR(mir.w);
+    __set_MCIR(1u << MCIR_TLBR_Pos);
+
+    *meh = __get_MEH();
+    *mel0 = __get_MEL0();
+    *mel1 = __get_MEL1();
+}
+
+
+/**
+  \brief  flush all mmu tlb.
+  \details
+  */
+__STATIC_INLINE void csi_mmu_invalid_tlb_all(void)
+{
+    __set_MCIR(1u << MCIR_TLBINV_ALL_Pos);
+}
+
+/**
+  \brief  flush mmu tlb by index.
+  \details
+  */
+__STATIC_INLINE void csi_mmu_invalid_tlb_by_index(uint32_t index)
+{
+    MIR_Type mir;
+
+    mir.b.Index = index;
+    __set_MIR(mir.w);
+    __set_MCIR(1u << MCIR_TLBINV_INDEX_Pos);
+}
+
+
+/**
+  \brief  flush mmu tlb by virtual address.
+  \details
+  */
+__STATIC_INLINE void csi_mmu_invalid_tlb_by_vaddr(uint32_t vaddr, uint32_t asid)
+{
+    __set_MEH(vaddr | (asid & MEH_ASID_Msk));
+    __set_MCIR(1u << MCIR_TLBP_Pos);
+
+    if (__get_MIR() & (1 << MIR_P_Pos)) {
+        return;
+    } else {
+        __set_MCIR(1u << MCIR_TLBINV_INDEX_Pos);
+    }
+}
+
+/*@} end of CSI_Core_MMUFunctions */
+
+
+/* ##################################    IRQ Functions  ############################################ */
+
+/**
+  \brief   Save the Irq context
+  \details save the psr result before disable irq.
+  \param [in]      irq_num  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE uint32_t csi_irq_save(void)
+{
+    uint32_t result;
+    result = __get_PSR();
+    __disable_irq();
+    return(result);
+}
+
+/**
+  \brief   Restore the Irq context
+  \details restore saved primask state.
+  \param [in]      irq_state  psr irq state.
+ */
+__STATIC_INLINE void csi_irq_restore(uint32_t irq_state)
+{
+    __set_PSR(irq_state);
+}
+
+/*@} end of IRQ Functions */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CK807_H_DEPENDANT */
+
+#endif /* __CSI_GENERIC */

lib/sec_library/include/core/core_ck810.h

@@ -0,0 +1,854 @@
+/*
+ * Copyright (C) 2017-2019 Alibaba Group Holding Limited
+ */
+
+
+/******************************************************************************
+ * @file     core_ck810.h
+ * @brief    CSI CK810 Core Peripheral Access Layer Header File
+ * @version  V1.0
+ * @date     26. Jan 2018
+ ******************************************************************************/
+
+#ifndef __CORE_CK810_H_GENERIC
+#define __CORE_CK810_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*******************************************************************************
+ *                 CSI definitions
+ ******************************************************************************/
+/**
+  \ingroup CK810
+  @{
+ */
+
+/*  CSI CK810 definitions */
+#define __CK810_CSI_VERSION_MAIN  (0x04U)                                      /*!< [31:16] CSI HAL main version */
+#define __CK810_CSI_VERSION_SUB   (0x1EU)                                      /*!< [15:0]  CSI HAL sub version */
+#define __CK810_CSI_VERSION       ((__CK810_CSI_VERSION_MAIN << 16U) | \
+                                   __CK810_CSI_VERSION_SUB           )         /*!< CSI HAL version number */
+
+#ifndef __CK810
+#define __CK810                (0x0aU)                                         /*!< CK810 Core */
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not.
+*/
+#define __FPU_USED      1U
+
+#if defined ( __GNUC__ )
+#if defined (__VFP_FP__) && !defined(__SOFTFP__)
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CK810_H_GENERIC */
+
+#ifndef __CSI_GENERIC
+
+#ifndef __CORE_CK810_H_DEPENDANT
+#define __CORE_CK810_H_DEPENDANT
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#ifndef __CK810_REV
+#define __CK810_REV               0x0000U
+#endif
+
+#ifndef __GSR_GCR_PRESENT
+#define __GSR_GCR_PRESENT         0U
+#endif
+
+#ifndef __ICACHE_PRESENT
+#define __ICACHE_PRESENT          1U
+#endif
+
+#ifndef __DCACHE_PRESENT
+#define __DCACHE_PRESENT          1U
+#endif
+
+#include <csi_gcc.h>
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CSI_glob_defs CSI Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+#define     __I      volatile             /*!< Defines 'read only' permissions */
+#else
+#define     __I      volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O      volatile             /*!< Defines 'write only' permissions */
+#define     __IO     volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const       /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile             /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile             /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group CK810 */
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+ ******************************************************************************/
+/**
+  \defgroup CSI_core_register Defines and Type Definitions
+  \brief Type definitions and defines for CK810 processor based devices.
+*/
+
+/**
+  \ingroup    CSI_core_register
+  \defgroup   CSI_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Access Processor Status Register(PSR)struct definition.
+ */
+typedef union {
+    struct {
+        uint32_t C: 1;                       /*!< bit:      0  Conditional code/Carry flag */
+        uint32_t _reserved0: 5;              /*!< bit:  2.. 5  Reserved */
+        uint32_t IE: 1;                      /*!< bit:      6  Interrupt effective control bit */
+        uint32_t IC: 1;                      /*!< bit:      7  Interrupt control bit */
+        uint32_t EE: 1;                      /*!< bit:      8  Abnormally effective control bit */
+        uint32_t MM: 1;                      /*!< bit:      9  Unsymmetrical masking bit */
+        uint32_t _reserved1: 6;              /*!< bit: 10..15  Reserved */
+        uint32_t VEC: 8;                     /*!< bit: 16..23  Abnormal event vector value */
+        uint32_t _reserved2: 5;              /*!< bit: 24..28  Reserved */
+        uint32_t SP: 1;                      /*!< bit:     29  Secure pedning bit */
+        uint32_t T: 1;                       /*!< bit:     30  TEE mode bit */
+        uint32_t S: 1;                       /*!< bit:     31  Superuser mode set bit */
+    } b;                                   /*!< Structure    Access by bit */
+    uint32_t w;                            /*!< Type         Access by whole register */
+} PSR_Type;
+
+/* PSR Register Definitions */
+#define PSR_S_Pos                          31U                                            /*!< PSR: S Position */
+#define PSR_S_Msk                          (1UL << PSR_S_Pos)                             /*!< PSR: S Mask */
+
+#define PSR_VEC_Pos                        16U                                            /*!< PSR: VEC Position */
+#define PSR_VEC_Msk                        (0x7FUL << PSR_VEC_Pos)                        /*!< PSR: VEC Mask */
+
+#define PSR_MM_Pos                         9U                                             /*!< PSR: MM Position */
+#define PSR_MM_Msk                         (1UL << PSR_MM_Pos)                            /*!< PSR: MM Mask */
+
+#define PSR_EE_Pos                         8U                                             /*!< PSR: EE Position */
+#define PSR_EE_Msk                         (1UL << PSR_EE_Pos)                            /*!< PSR: EE Mask */
+
+#define PSR_IC_Pos                         7U                                             /*!< PSR: IC Position */
+#define PSR_IC_Msk                         (1UL << PSR_IC_Pos)                            /*!< PSR: IC Mask */
+
+#define PSR_IE_Pos                         6U                                             /*!< PSR: IE Position */
+#define PSR_IE_Msk                         (1UL << PSR_IE_Pos)                            /*!< PSR: IE Mask */
+
+#define PSR_C_Pos                          0U                                             /*!< PSR: C Position */
+#define PSR_C_Msk                          (1UL << PSR_C_Pos)                             /*!< PSR: C Mask */
+
+/**
+  \brief Consortium definition for accessing Cache Configuration Registers(CCR, CR<18, 0>).
+ */
+typedef union {
+    struct {
+        uint32_t MP: 2;                      /*!< bit:  0.. 1  memory protection settings */
+        uint32_t IE: 1;                      /*!< bit:      2  Instruction cache enable */
+        uint32_t DE: 1;                      /*!< bit:      3  Data cache enable */
+        uint32_t WB: 1;                      /*!< bit:      4  Cache write back */
+        uint32_t RS: 1;                      /*!< bit:      5  Address return stack settings */
+        uint32_t Z: 1;                       /*!< bit:      6  Allow predictive jump bit */
+        uint32_t BE: 1;                      /*!< bit:      7  Endian mode */
+        uint32_t SCK: 3;                     /*!< bit:  8..10  the clock ratio of the system and the processor */
+        uint32_t _reserved0: 1;              /*!< bit:     11  Reserved */
+        uint32_t WA: 1;                      /*!< bit:     12  Write allocate enable */
+        uint32_t E_V2: 1;                    /*!< bit:     13  V2 Endian mode */
+        uint32_t BSTE: 1;                    /*!< bit:     14  Burst transmit enable */
+        uint32_t IPE: 1;                     /*!< bit:     15  Indirect predict enable */
+        uint32_t _reserved1: 16;             /*!< bit: 16..31  Reserved */
+    } b;                                   /*!< Structure    Access by bit */
+    uint32_t w;                            /*!< Type         Access by whole register */
+} CCR_Type;
+
+/* CCR Register Definitions */
+#define CCR_IPE_Pos                       15u                                            /*!< CCR: IPE Position */
+#define CCR_IPE_Msk                       (0x1UL << CCR_IPE_Pos)                         /*!< CCR: IPE Mask */
+
+#define CCR_BSTE_Pos                      14u                                            /*!< CCR: BSTE Position */
+#define CCR_BSTE_Msk                      (0x1UL << CCR_BSTE_Pos)                        /*!< CCR: BSTE Mask */
+
+#define CCR_E_V2_Pos                      13U                                            /*!< CCR: E_V2 Position */
+#define CCR_E_V2_Msk                      (0x1UL << CCR_E_V2_Pos)                        /*!< CCR: E_V2 Mask */
+
+#define CCR_WA_Pos                        12u                                            /*!< CCR: WA Position */
+#define CCR_WA_Msk                        (0x1UL << CCR_WA_Pos)                          /*!< CCR: WA Mask */
+
+#define CCR_SCK_Pos                       8U                                             /*!< CCR: SCK Position */
+#define CCR_SCK_Msk                       (0x3UL << CCR_SCK_Pos)                         /*!< CCR: SCK Mask */
+
+#define CCR_BE_Pos                        7U                                             /*!< CCR: BE Position */
+#define CCR_BE_Msk                        (0x1UL << CCR_BE_Pos)                          /*!< CCR: BE Mask */
+
+#define CCR_Z_Pos                         6U                                             /*!< CCR: Z Position */
+#define CCR_Z_Msk                         (0x1UL << CCR_BE_Pos)                          /*!< CCR: Z Mask */
+
+#define CCR_RS_Pos                        5U                                             /*!< CCR: RS Position */
+#define CCR_RS_Msk                        (0x1UL << CCR_BE_Pos)                          /*!< CCR: RS Mask */
+
+#define CCR_WB_Pos                        4U                                             /*!< CCR: WB Position */
+#define CCR_WB_Msk                        (0x1UL << CCR_BE_Pos)                          /*!< CCR: WB Mask */
+
+#define CCR_DE_Pos                        3U                                             /*!< CCR: DE Position */
+#define CCR_DE_Msk                        (0x1UL << CCR_BE_Pos)                          /*!< CCR: DE Mask */
+
+#define CCR_IE_Pos                        2U                                             /*!< CCR: IE Position */
+#define CCR_IE_Msk                        (0x1UL << CCR_BE_Pos)                          /*!< CCR: IE Mask */
+
+#define CCR_MP_Pos                        0U                                             /*!< CCR: MP Position */
+#define CCR_MP_Msk                        (0x3UL << CCR_MP_Pos)                          /*!< CCR: MP Mask */
+
+/**
+  \brief  Consortium definition for accessing mmu index register(MIR,CR<0,15>).
+ */
+typedef union {
+    struct {
+        uint32_t Index: 10;                  /*!< bit:   0.. 9   TLB index */
+        uint32_t _reserved: 20;              /*!< bit:  10.. 29  Reserved */
+        uint32_t TF: 1;                      /*!< bit:       30  TLB fatal error */
+        uint32_t P: 1;                       /*!< bit:       31  TLBP instruction */
+    } b;
+    uint32_t w;
+} MIR_Type;
+
+/* MIR Register Definitions */
+#define MIR_P_Pos                          31                                            /*!< PRSR: P(TLBP instruction) Position */
+#define MIR_P_Msk                          (0x1UL << MIR_P_Pos)                          /*!< PRSR: P(TLBP instruction) Mask */
+
+#define MIR_TF_Pos                         30                                            /*!< PRSR: Tfatal Position */
+#define MIR_TF_Msk                         (0x1UL << MIR_TF_Pos)                         /*!< PRSR: Tfatal Mask */
+
+#define MIR_Index_Pos                      0                                             /*!< PRSR: Index Position */
+#define MIR_Index_Msk                      (0x3ffUL << MIR_Index_Pos)                    /*!< PRSR: Index Mask */
+
+
+/**
+  \brief  Consortium definition for accessing mmu entry of high physical address register(MEL, CR<2,15> and CR<3,15>).
+ */
+typedef union {
+    struct {
+        uint32_t G: 1;                        /*!< bit:       0   Global enbale bit */
+        uint32_t V: 1;                        /*!< bit:       1   TLB mapping valid bit */
+        uint32_t D: 1;                        /*!< bit:       2   TLB Page dirty bit */
+        uint32_t C: 1;                        /*!< bit:       3   TLB Page cacheable bit */
+        uint32_t SEC: 1;                      /*!< bit:       4   TLB Page security bit */
+        uint32_t SO: 1;                       /*!< bit:       2   Strong order enable bit */
+        uint32_t B: 1;                        /*!< bit:       2   TLB Page bufferable bit */
+        uint32_t _reserved: 5;                /*!< bit:   7.. 11  Reserved */
+        uint32_t PFN: 20;                     /*!< bit:  12.. 31  Physical frame number */
+    } b;
+    uint32_t w;
+} MEL_Type;
+
+/* MEL Register Definitions */
+#define MEL_PFN_Pos                        12                                            /*!< MEL: PFN Position */
+#define MEL_PFN_Msk                        (0xFFFFFUL << MEL_PFN_Pos)                    /*!< MEL: PFN Mask */
+
+#define MEL_B_Pos                          6                                             /*!< MEL: B Position */
+#define MEL_B_Msk                          (0x1UL << MEL_B_Pos)                          /*!< MEL: B Mask */
+
+#define MEL_SO_Pos                         5                                             /*!< MEL: SO Position */
+#define MEL_SO_Msk                         (0x1UL << MEL_SO_Pos)                         /*!< MEL: SO Mask */
+
+#define MEL_SEC_Pos                        4                                             /*!< MEL: SEC Position */
+#define MEL_SEC_Msk                        (0x1UL << MEL_SEC_Pos)                        /*!< MEL: SEC Mask */
+
+#define MEL_C_Pos                          3                                             /*!< MEL: C Position */
+#define MEL_C_Msk                          (0x1UL << MEL_C_Pos)                          /*!< MEL: C Mask */
+
+#define MEL_D_Pos                          2                                             /*!< MEL: D Position */
+#define MEL_D_Msk                          (0x1UL << MIR_D_Pos)                          /*!< MEL: D Mask */
+
+#define MEL_V_Pos                          1                                             /*!< MEL: V Position */
+#define MEL_V_Msk                          (0x1UL << MIR_V_Pos)                          /*!< MEL: V Mask */
+
+#define MEL_G_Pos                          0                                             /*!< MEL: G Position */
+#define MEL_G_Msk                          (0x1UL << MIR_G_Pos)                          /*!< MEL: G Mask */
+
+
+/**
+  \brief  Consortium definition for accessing mmu entry of high physical address register(MEH, CR<4,15>).
+ */
+typedef union {
+    struct {
+        uint32_t ASID :8;                     /*!< bit:   0.. 7   ASID */
+        uint32_t _reserved :4;                /*!< bit:   7.. 10  Reserved */
+        uint32_t VPN :20;                     /*!< bit:  11.. 31  Virtual page number */
+    } b;
+    uint32_t w;
+} MEH_Type;
+
+/* MEH Register Definitions */
+#define MEH_VPN_Pos                        12                                             /*!< MEH: VPN Position */
+#define MEH_VPN_Msk                        (0xFFFFFUL << MEH_VPN_Pos)                     /*!< MEH: VPN Mask */
+
+#define MEH_ASID_Pos                       0                                              /*!< MEH: ASID Position */
+#define MEH_ASID_Msk                       (0xFFUL << MEH_ASID_Pos)                       /*!< MEH: ASID Mask */
+
+
+/**
+  \brief  Consortium definition for accessing mmu entry of high physical address register(MPR, CR<6,15>).
+ */
+typedef union {
+    struct {
+        uint32_t _reserved0: 13;              /*!< bit:   0.. 12   Reserved */
+        uint32_t page_mask: 12;               /*!< bit:  13.. 24   Page mask */
+        uint32_t _reserved1: 7;               /*!< bit:  25.. 31   Reserved */
+    } b;
+    uint32_t w;
+} MPR_Type;
+
+/* MPR Register Definitions */
+#define MPR_PAGE_MASK_Pos                        13                                             /*!< MPR: PAGE_MASK Position */
+#define MPR_PAGE_MASK_Msk                        (0xFFFUL << MPR_PAGE_MASK_Pos)                 /*!< MPR: PAGE_MASK Mask */
+
+
+/**
+  \brief  Consortium definition for accessing mmu entry of high physical address register(CR<8,15>).
+ */
+typedef union {
+    struct {
+        uint32_t ASID: 8;                     /*!< bit:   0.. 7   ASID */
+        uint32_t _reserved: 17;               /*!< bit:   8.. 24  Reserved */
+        uint32_t TLBINV_INDEX: 1;             /*!< bit:       25  TLBINV_INDEX */
+        uint32_t TLBINV_ALL: 1;               /*!< bit:       26  TLBINV_ALL */
+        uint32_t TLBINV: 1;                   /*!< bit:       27  TLBINV */
+        uint32_t TLBWR: 1;                    /*!< bit:       28  TLBWR */
+        uint32_t TLBWI: 1;                    /*!< bit:       29  TLBWI */
+        uint32_t TLBR: 1;                     /*!< bit:       30  TLBR */
+        uint32_t TLBP: 1;                     /*!< bit:       31  TLBP */
+    } b;
+    uint32_t w;
+} MCIR_Type;
+
+/* MCIR Register Definitions */
+#define MCIR_TLBP_Pos                        31                                               /*!< MCIR: TLBP Position */
+#define MCIR_TLBP_Msk                        (0x1UL << MCIR_TLBP_Pos)                         /*!< MCIR: TLBP Mask */
+
+#define MCIR_TLBR_Pos                        30                                               /*!< MCIR: TLBR Position */
+#define MCIR_TLBR_Msk                        (0x1UL << MCIR_TLBR_Pos)                         /*!< MCIR: TLBR Mask */
+
+#define MCIR_TLBWI_Pos                       29                                               /*!< MCIR: TLBWI Position */
+#define MCIR_TLBWI_Msk                       (0x1UL << MCIR_TLBWI_Pos)                        /*!< MCIR: TLBWI Mask */
+
+#define MCIR_TLBWR_Pos                       28                                               /*!< MCIR: TLBWR Position */
+#define MCIR_TLBWR_Msk                       (0x1UL << MCIR_TLBWR_Pos)                        /*!< MCIR: TLBWR Mask */
+
+#define MCIR_TLBINV_Pos                      27                                               /*!< MCIR: TLBINV Position */
+#define MCIR_TLBINV_Msk                      (0x1UL << MCIR_TLBINV_Pos)                       /*!< MCIR: TLBINV Mask */
+
+#define MCIR_TLBINV_ALL_Pos                  26                                               /*!< MCIR: TLBINV_ALL Position */
+#define MCIR_TLBINV_ALL_Msk                  (0x1UL << MCIR_TLBINV_ALL_Pos)                   /*!< MCIR: TLBINV_ALL Mask */
+
+#define MCIR_TLBINV_INDEX_Pos                25                                               /*!< MCIR: TLBINV_INDEX Position */
+#define MCIR_TLBINV_INDEX_Msk                (0x1UL << MCIR_TLBINV_INDEX_Pos)                 /*!< MCIR: TLBINV_INDEX Mask */
+
+#define MCIR_ASID_Pos                        0                                                /*!< MCIR: ASID Position */
+#define MCIR_ASID_Msk                        (0xFFUL << MCIR_ASID_Pos)                        /*!< MCIR: ASID Mask */
+
+
+/*@} end of group CSI_CORE */
+
+
+/**
+  \ingroup    CSI_core_register
+  \defgroup   CSI_CACHE
+  \brief      Type definitions for the cache Registers
+  @{
+ */
+
+/**
+  \brief  Consortium definition for accessing protection area selection register(CFR,CR<17,0>).
+ */
+typedef union {
+    struct {
+        uint32_t CACHE_SEL: 2;                      /*!< bit:  0..1  Instruction and data cache selection */
+        uint32_t _reserved0: 2;                     /*!< bit:  2..3  Reserved */
+        uint32_t INV: 1;                            /*!< bit:     4  Invalid data in cache */
+        uint32_t CLR: 1;                            /*!< bit:     5  Clear the dirty tlb table */
+        uint32_t OMS: 1;                            /*!< bit:     6  Cache invalid and clear operation mode (one line or all line)*/
+        uint32_t ITS: 1;                            /*!< bit:     7  Cache invalid and clear operation mode (CIR used as virtual index or SET/WAY/LEVE index)*/
+        uint32_t UNLOCK: 1;                         /*!< bit:     8  Unclock data cache line. */
+        uint32_t _reserved1: 7;                     /*!< bit: 9..15  Reserved */
+        uint32_t BHT_INV: 1;                        /*!< bit:    16  Invalid data in branch history table */
+        uint32_t BTB_INV: 1;                        /*!< bit:    17  Invalid data in branch table buffer */
+        uint32_t _reserved2: 13;                    /*!< bit: 18..30 Reserved */
+        uint32_t LICF: 1;                           /*!< bit:     31 Failure of clearing or invalid cache line */
+    } b;                                            /*!< Structure    Access by bit */
+    uint32_t w;                                     /*!< Type         Access by whole register */
+} CFR_Type;
+
+#define CFR_LICF_Pos                     31U                                             /*!< CFR: LICF Position */
+#define CFR_LICF_Msk                     (0x1UL << CFR_LICF_Pos)                         /*!< CFR: LICF Mask */
+
+#define CFR_BTB_INV_Pos                  17U                                             /*!< CFR: BTB Position */
+#define CFR_BTB_INV_Msk                  (0x1UL << CFR_BTB_INV_Pos)                      /*!< CFR: BTB Mask */
+
+#define CFR_BHT_INV_Pos                  16U                                             /*!< CFR: BHT Position */
+#define CFR_BHT_INV_Msk                  (0x1UL << CFR_BHT_INV_Pos)                      /*!< CFR: BHT Mask */
+
+#define CFR_UNLOCK_Pos                   8U                                              /*!< CFR: UNLOCK Position */
+#define CFR_UNLOCK_Msk                   (0x1UL << CFR_UNLOCK_Pos)                       /*!< CFR: UNLOCK Mask */
+
+#define CFR_ITS_Pos                      7U                                              /*!< CFR: ITS Position */
+#define CFR_ITS_Msk                      (0x1UL << CFR_ITS_Pos)                          /*!< CFR: ITS Mask */
+
+#define CFR_OMS_Pos                      6U                                              /*!< CFR: OMS Position */
+#define CFR_OMS_Msk                      (0x1UL << CFR_OMS_Pos)                          /*!< CFR: OMS Mask */
+
+#define CFR_CLR_Pos                      5U                                              /*!< CFR: CLR Position */
+#define CFR_CLR_Msk                      (0x1UL << CFR_CLR_Pos)                          /*!< CFR: CLR Mask */
+
+#define CFR_INV_Pos                      4U                                              /*!< CFR: INV Position */
+#define CFR_INV_Msk                      (0x1UL << CFR_INV_Pos)                          /*!< CFR: INV Mask */
+
+#define CFR_CACHE_SEL_Pos                0                                               /*!< CFR: CACHE_SEL Position */    
+#define CFR_CACHE_SEL_Msk                (0x3UL << CFR_CACHE_SEL_Pos)                    /*!< CFR: CACHE_SEL Masok */
+
+/* CFR Register Definitions */
+/*@} end of group CSI_CACHE */
+
+
+/**
+  \ingroup    CSI_core_register
+  \defgroup   CSI_CACHE
+  \brief      Type definitions for the cache Registers
+  @{
+ */
+#define SSEG0_BASE_ADDR         0x80000000
+#define CACHE_RANGE_MAX_SIZE    0x80000
+
+#define INS_CACHE               (1 << 0)
+#define DATA_CACHE              (1 << 1)
+#define CACHE_INV               (1 << 4)
+#define CACHE_CLR               (1 << 5)
+#define CACHE_OMS               (1 << 6)
+#define CACHE_ITS               (1 << 7)
+#define CACHE_LICF              (1 << 31)
+
+#define    L1_CACHE_SHIFT       4      /* 16 Bytes */
+#define    L1_CACHE_BYTES       (1 << L1_CACHE_SHIFT)
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    ((value << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    ((value & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CSI_core_bitfield */
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core VIC Functions
+  - Core CORET Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
+#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
+
+
+/* ##########################  Cache functions  #################################### */
+/**
+  \ingroup  CSI_Core_FunctionInterface
+  \defgroup CSI_Core_CacheFunctions Cache Functions
+  \brief    Functions that configure Instruction and Data cache.
+  @{
+ */
+
+/**
+  \brief   Enable I-Cache
+  \details Turns on I-Cache
+  */
+__STATIC_INLINE void csi_icache_enable (void)
+{
+   __set_CCR(__get_CCR() | 0x00000004);
+}
+
+
+/**
+  \brief   Disable I-Cache
+  \details Turns off I-Cache
+  */
+__STATIC_INLINE void csi_icache_disable (void)
+{
+   __set_CCR(__get_CCR() & 0xFFFFFFFB);
+}
+
+
+/**
+  \brief   Invalidate I-Cache
+  \details Invalidates I-Cache
+  */
+__STATIC_INLINE void csi_icache_invalid (void)
+{
+    __set_CFR(0x11);
+    __set_CFR(INS_CACHE | CACHE_INV);
+}
+
+
+/**
+  \brief   Enable D-Cache
+  \details Turns on D-Cache
+  \note    I-Cache also turns on.
+  */
+__STATIC_INLINE void csi_dcache_enable (void)
+{
+   __set_CCR(__get_CCR() | 0x00000008);
+}
+
+
+/**
+  \brief   Disable D-Cache
+  \details Turns off D-Cache
+  \note    I-Cache also turns off.
+  */
+__STATIC_INLINE void csi_dcache_disable (void)
+{
+   __set_CCR(__get_CCR() & 0xFFFFFFF7);
+}
+
+
+/**
+  \brief   Invalidate D-Cache
+  \details Invalidates D-Cache
+  \note    I-Cache also invalid
+  */
+__STATIC_INLINE void csi_dcache_invalid (void)
+{
+    __set_CFR(DATA_CACHE | CACHE_INV);
+}
+
+
+/**
+  \brief   Clean D-Cache
+  \details Cleans D-Cache
+  \note    I-Cache also cleans
+  */
+__STATIC_INLINE void csi_dcache_clean (void)
+{
+    __set_CFR(DATA_CACHE | CACHE_CLR);
+}
+
+/**
+  \brief   Clean & Invalidate D-Cache
+  \details Cleans and Invalidates D-Cache
+  \note    I-Cache also flush.
+  */
+__STATIC_INLINE void csi_dcache_clean_invalid (void)
+{
+    __set_CFR(DATA_CACHE | CACHE_CLR | CACHE_INV);
+}
+
+__STATIC_INLINE  void set_cache_range (uint32_t start, uint32_t end, uint32_t value)
+{
+    if (!(start & SSEG0_BASE_ADDR) || (end - start) &~(CACHE_RANGE_MAX_SIZE - 1)) {
+        __set_CFR(value);
+    }
+
+    if (value & INS_CACHE) {
+        csi_icache_disable();
+    }
+    uint32_t i;
+    for (i = start; i < end; i += L1_CACHE_BYTES) {
+        __set_CIR(i);
+        __set_CFR(CACHE_OMS | value);
+    }
+
+    if (end & (L1_CACHE_BYTES-1)) {
+        __set_CIR(end);
+        __set_CFR(CACHE_OMS | value);
+    }
+
+    if (value & INS_CACHE) {
+        csi_icache_enable();
+    }
+
+}
+
+/**
+  \brief   D-Cache Invalidate by address
+  \details Invalidates D-Cache for the given address
+  \param[in]   addr    address (aligned to 16-byte boundary)
+  \param[in]   dsize   size of memory block (in number of bytes)
+*/
+__STATIC_INLINE void csi_dcache_invalid_range (uint32_t *addr, int32_t dsize)
+{
+    set_cache_range((uint32_t)addr, (uint32_t)addr + dsize, (DATA_CACHE | CACHE_INV));
+}
+
+
+/**
+  \brief   D-Cache Clean by address
+  \details Cleans D-Cache for the given address
+  \param[in]   addr    address (aligned to 16-byte boundary)
+  \param[in]   dsize   size of memory block (in number of bytes)
+*/
+__STATIC_INLINE void csi_dcache_clean_range (uint32_t *addr, int32_t dsize)
+{
+    set_cache_range((uint32_t)addr, (uint32_t)addr + dsize, (DATA_CACHE | CACHE_CLR));
+}
+
+
+/**
+  \brief   D-Cache Clean and Invalidate by address
+  \details Cleans and invalidates D_Cache for the given address
+  \param[in]   addr    address (aligned to 16-byte boundary)
+  \param[in]   dsize   size of memory block (in number of bytes)
+*/
+__STATIC_INLINE void csi_dcache_clean_invalid_range (uint32_t *addr, int32_t dsize)
+{
+    set_cache_range((uint32_t)addr, (uint32_t)addr + dsize, (DATA_CACHE | CACHE_CLR | CACHE_INV));
+}
+
+
+/*@} end of CSI_Core_CacheFunctions */
+
+/* ##########################  MMU functions  #################################### */
+/**
+  \ingroup  CSI_Core_FunctionInterface
+  \defgroup CSI_Core_MMUFunctions MMU Functions
+  \brief    Functions that configure MMU.
+  @{
+ */
+
+typedef struct {
+    uint32_t global: 1;         /* tlb page global access. */
+    uint32_t valid: 1;          /* tlb page valid */
+    uint32_t writeable: 1;      /* tlb page writeable */
+    uint32_t cacheable: 1;      /* tlb page cacheable*/
+    uint32_t is_secure: 1;      /* tlb page security access */
+    uint32_t strong_order: 1;   /* the sequence of accessing data on tlb page is corresponding to the program flow? */
+    uint32_t bufferable: 1;     /* tlb page bufferable */
+} page_attr_t;
+
+typedef enum {
+    PAGE_SIZE_4KB   = 0x000,
+    PAGE_SIZE_16KB  = 0x003,
+    PAGE_SIZE_64KB  = 0x00F,
+    PAGE_SIZE_256KB = 0x03F,
+    PAGE_SIZE_1MB   = 0x0FF,
+    PAGE_SIZE_4MB   = 0x3FF,
+    PAGE_SIZE_16MB  = 0xFFF
+} page_size_e;
+
+
+/**
+  \brief  enable mmu
+  \details
+  */
+__STATIC_INLINE void csi_mmu_enable(void)
+{
+    __set_CCR(__get_CCR() | (1u << CCR_MP_Pos));
+}
+
+/**
+  \brief  disable mmu
+  \details
+  */
+__STATIC_INLINE void csi_mmu_disable(void)
+{
+    __set_CCR(__get_CCR() & (~(1u << CCR_MP_Pos)));
+}
+
+/**
+  \brief  create page with feature.
+  \details
+  \param [in]  vaddr     virtual address.
+  \param [in]  paddr     physical address.
+  \param [in]  asid      address sapce id (default: 0).
+  \param [in]  attr      \ref page_attr_t. tlb page attribute.
+  */
+__STATIC_INLINE void csi_mmu_set_tlb(uint32_t vaddr, uint32_t paddr, uint32_t asid, page_attr_t attr)
+{
+     MPR_Type pgmask;
+     MEH_Type meh;
+     MEL_Type mel;
+     uint32_t vaddr_bit;
+     uint32_t page_feature = 0;
+
+     page_feature |= attr.global << MEL_G_Pos | attr.valid << MEL_V_Pos |
+                     attr.writeable << MEL_D_Pos | attr.cacheable << MEL_C_Pos |
+                     attr.is_secure << MEL_SEC_Pos | attr.strong_order << MEL_SO_Pos |
+                     attr.bufferable << MEL_B_Pos;
+
+     pgmask.w = __get_MPR();
+     vaddr_bit = 44 - __FF0(~((uint32_t)pgmask.b.page_mask));
+
+     meh.b.ASID = (uint8_t)asid;
+     meh.b.VPN  = (vaddr & ((~pgmask.w | 0xFE000000) & 0xFFFFE000)) >> MEH_VPN_Pos;
+     __set_MEH(meh.w);
+
+     __set_MCIR(1u << MCIR_TLBP_Pos);
+
+     mel.w = ((paddr & ~(pgmask.b.page_mask << 12)) | page_feature);
+     if (vaddr & (1 << vaddr_bit)) {
+         __set_MEL1(mel.w);
+     }
+     else {
+         __set_MEL0(mel.w);
+     }
+
+     if (__get_MIR() & (1 << MIR_P_Pos)) {
+        __set_MCIR(1u << MCIR_TLBWR_Pos);
+     } else {
+        __set_MCIR(1u << MCIR_TLBWI_Pos);
+     }
+}
+
+
+/**
+  \brief  enble mmu
+  \details
+  \param [in]  size  tlb page size.
+  */
+__STATIC_INLINE void csi_mmu_set_pagesize(page_size_e size)
+{
+    MPR_Type pgmask;
+    pgmask.b.page_mask = size;
+    __set_MPR(pgmask.w);
+}
+
+
+/**
+  \brief  read MEH, MEL0, MEL1 by tlb index.
+  \details
+  \param [in]    index  tlb index(0, 1, 2, ...)
+  \param [out]   meh    pointer to variable for retrieving MEH.
+  \param [out]   mel0   pointer to variable for retrieving MEL0.
+  \param [out]   mel1   pointer to variable for retrieving MEL1.
+  */
+__STATIC_INLINE void csi_mmu_read_by_index(uint32_t index, uint32_t *meh, uint32_t *mel0, uint32_t *mel1)
+{
+    MIR_Type mir;
+
+    if (meh == NULL || mel0 == NULL || mel1 == NULL) {
+        return;
+    }
+
+    mir.b.Index = index;
+    __set_MIR(mir.w);
+    __set_MCIR(1u << MCIR_TLBR_Pos);
+
+    *meh = __get_MEH();
+    *mel0 = __get_MEL0();
+    *mel1 = __get_MEL1();
+}
+
+
+/**
+  \brief  flush all mmu tlb.
+  \details
+  */
+__STATIC_INLINE void csi_mmu_invalid_tlb_all(void)
+{
+    __set_MCIR(1u << MCIR_TLBINV_ALL_Pos);
+}
+
+
+/**
+  \brief  flush mmu tlb by index.
+  \details
+  */
+__STATIC_INLINE void csi_mmu_invalid_tlb_by_index(uint32_t index)
+{
+    MIR_Type mir;
+
+    mir.b.Index = index;
+    __set_MIR(mir.w);
+    __set_MCIR(1u << MCIR_TLBINV_INDEX_Pos);
+}
+
+
+/**
+  \brief  flush mmu tlb by virtual address.
+  \details
+  */
+__STATIC_INLINE void csi_mmu_invalid_tlb_by_vaddr(uint32_t vaddr, uint32_t asid)
+{
+    __set_MEH(vaddr | (asid & MEH_ASID_Msk));
+    __set_MCIR(1u << MCIR_TLBP_Pos);
+
+    if (__get_MIR() & (1 << MIR_P_Pos)) {
+        return;
+    } else {
+        __set_MCIR(1u << MCIR_TLBINV_INDEX_Pos);
+    }
+}
+
+/*@} end of CSI_Core_MMUFunctions */
+
+
+/* ##################################    IRQ Functions  ############################################ */
+
+/**
+  \brief   Save the Irq context
+  \details save the psr result before disable irq.
+  \param [in]      irq_num  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE uint32_t csi_irq_save(void)
+{
+    uint32_t result;
+    result = __get_PSR();
+    __disable_irq();
+    return(result);
+}
+
+/**
+  \brief   Restore the Irq context
+  \details restore saved primask state.
+  \param [in]      irq_state  psr irq state.
+ */
+__STATIC_INLINE void csi_irq_restore(uint32_t irq_state)
+{
+    __set_PSR(irq_state);
+}
+
+/*@} end of IRQ Functions */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CK810_H_DEPENDANT */
+
+#endif /* __CSI_GENERIC */

lib/sec_library/include/csi_core.h

@@ -0,0 +1,62 @@
+/*
+ * Copyright (C) 2017-2019 Alibaba Group Holding Limited
+ */
+
+
+/******************************************************************************
+ * @file     csi_core.h
+ * @brief    CSI Core Layer Header File
+ * @version  V1.0
+ * @date     02. June 2017
+ ******************************************************************************/
+
+#ifndef _CORE_H_
+#define _CORE_H_
+
+#include <stdint.h>
+
+#if defined(__CK801__) || defined(__E801__)
+#include "core/core_801.h"
+#elif defined(__CK802__) || defined(__E802__) || defined(__E802T__) || defined(__S802__) || defined(__S802T__)
+#include "core/core_802.h"
+#elif defined(__CK804__) || defined(__E804D__) || defined(__E804DT__) || defined(__E804F__)  || defined(__E804FT__) || defined (__E804DF__) || defined(__E804DFT__)
+#include "core/core_804.h"
+#elif defined(__CK803__) || defined(__E803__) || defined(__E803T__) || defined(__S803__) || defined(__S803T__)
+#include "core/core_803.h"
+#elif defined(__CK805__) || defined(__I805__) || defined(__I805F__)
+#include "core/core_805.h"
+#elif defined(__CK610__)
+#include "core/core_ck610.h"
+#elif defined(__CK810__) || defined(__C810__) || defined(__C810T__) || defined(__C810V__) || defined(__C810VT__)
+#include "core/core_810.h"
+#elif defined(__CK807__) || defined(__C807__) || defined(__C807F__) || defined(__C807FV__) || defined(__R807__)
+#include "core/core_807.h"
+#elif defined(__riscv) && defined(CONFIG_CSKY_CORETIM)
+#include "core/core_rv32_old.h"
+#elif defined(__riscv) && (__riscv_xlen == 32)
+#include "core/core_rv32.h"
+#elif defined(__riscv) && (__riscv_xlen == 64)
+#include "core/core_rv64.h"
+#endif
+
+#if defined(__riscv) && (__riscv_xlen == 32)
+#include "core/csi_rv32_gcc.h"
+#elif defined(__riscv) && (__riscv_xlen == 64)
+#include "core/csi_rv64_gcc.h"
+#elif defined(__csky__)
+#include "core/csi_gcc.h"
+#endif
+
+#ifdef __arm__
+#include "csi_core_cmsis.h"
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _CORE_H_ */

lib/sec_library/include/csi_efuse_api.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2019-2021 Alibaba Group Holding Limited
+ * Copyright (C) 2019-2020 Alibaba Group Holding Limited
  */
 #ifndef __CSI_EFUSE_API_H__
 #define __CSI_EFUSE_API_H__
@@ -21,9 +21,8 @@ typedef enum {
 	IMAGE_ENCRYPT_EN = ~(IMAGE_ENCRYPT_DIS),
 } img_encrypt_st_t;
 
-int csi_efuse_api_int(void);
-
-int csi_efuse_api_uninit(void);
+int csi_efuse_api_init(void);
+void csi_efuse_api_uninit(void);
 
 int csi_efuse_get_secure_boot_st(sboot_st_t *sboot_st);
 
@@ -49,6 +48,8 @@ int csi_efuse_read_raw(uint32_t addr, void *data, uint32_t cnt);
 
 int csi_efuse_write_raw(uint32_t addr, const void *data, uint32_t cnt);
 
+int csi_efuse_get_lc(int *lc);
+
 #ifdef __cplusplus
 }
 #endif

lib/sec_library/include/csi_sec_img_verify.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2019-2021 Alibaba Group Holding Limited
+ * Copyright (C) 2019-2020 Alibaba Group Holding Limited
  */
 #ifndef __CSI_SEC_IMG_VERIFY_H__
 #define __CSI_SEC_IMG_VERIFY_H__
@@ -24,8 +24,10 @@ int csi_sec_set_boot_stage(boot_stage_t boot_stage);
 
 int csi_sec_get_lib_version(char ** p_version);
 
+int csi_sec_library_init(void);
+
 #ifdef __cplusplus
 }
 #endif
 
-#endif	/* __CSI_SEC_IMG_VERIFY_H__ */
+#endif	/* __CSI_SEC_IMG_VERIFY_H__ */

lib/sec_library/include/curve25519.h

@@ -0,0 +1,86 @@
+/*
+ * Copyright (C) 2017-2022 Alibaba Group Holding Limited
+ */
+
+/******************************************************************************
+ * @file       drv/curve25519.h
+ * @brief      Header File for CURVE25519 Driver
+ * @version    V3.3
+ * @date       10.June 2022
+ * @model      ECC
+ ******************************************************************************/
+
+#ifndef _DRV_CURVE25519_H_
+#define _DRV_CURVE25519_H_
+
+#include <stdint.h>
+#include "common.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef struct {
+    csi_dev_t       dev;
+} csi_curve25519_t;
+
+/**
+  \brief       Initialize CURVE25519.
+  \param[in]   idx  device id
+  \return      Error code \ref csi_error_t
+*/
+csi_error_t csi_curve25519_init(void *ctx, uint32_t idx);
+
+/**
+  \brief       De-initialize CURVE25519 Interface. stops operation and releases the software resources used by the interface
+  \param[in]   curve25519  ecc handle to operate.
+  \return      none
+*/
+void csi_curve25519_uninit(void *ctx);
+
+/**
+  \brief       curve25519 gen public key
+  \param[in]   ctx ctx handle to operate.
+  \param[in]   privkey Pointer to the A(or B) private key.
+  \param[out]  pubkey  Pointer to the A(or B) public key.
+  \return      Error code \ref csi_error_t.
+*/
+csi_error_t csi_curve25519_gen_pubkey(void *ctx, const uint8_t privkey[32], uint8_t pubkey[32]);
+
+/**
+  \brief       curve25519 gen key pair
+  \param[in]   ctx ctx handle to operate.
+  \param[out]  privkey Pointer to the A(or B) private key.
+  \param[out]  pubkey  Pointer to the A(or B) public key.
+  \return      Error code \ref csi_error_t.
+*/
+csi_error_t csi_curve25519_gen_keypair(void *ctx, uint8_t privkey[32], uint8_t pubkey[32]);
+
+/**
+  \brief       curve25519 check key pair
+  \param[in]   ctx ctx handle to operate.
+  \param[in]   privkey Pointer to the B(or A) private key.
+  \param[in]   pubkey  Pointer to the A(or B) public key.
+  \param[out]  sk      Pointer to the share key.
+  \param[out]  sk_len  Pointer to the share key length byte.
+  \return      Error code \ref csi_error_t.
+*/
+csi_error_t csi_curve25519_check_keypair(void *ctx, const uint8_t privkey[32], const uint8_t pubkey[32]);
+
+/**
+  \brief       curve25519 check key pair
+  \param[in]   ctx ctx handle to operate.
+  \param[in]   privkey Pointer to the B(or A) private key.
+  \param[in]   pubkey  Pointer to the A(or B) public key.
+  \param[out]  sk      Pointer to the share key.
+  \param[out]  sk_len  Pointer to the share key length byte.
+  \return      Error code \ref csi_error_t.
+*/
+csi_error_t csi_curve25519_calc_secret(void *ctx, const uint8_t privkey[32], const uint8_t pubkey[32], uint8_t sk[32], uint32_t *sk_len);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

lib/sec_library/include/des.h

@@ -0,0 +1,221 @@
+/*
+ * Copyright (C) 2017-2020 Alibaba Group Holding Limited
+ */
+
+/******************************************************************************
+ * @file       drv/des.h
+ * @brief      Header File for DES Driver
+ * @version    V1.0
+ * @date       24. Oct 2022
+ * @model      des
+ ******************************************************************************/
+
+#ifndef _DRV_DES_H_
+#define _DRV_DES_H_
+
+#include <stdint.h>
+#include "common.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*----- Encrypt & Decrypt: Config key length -----*/
+/**
+\brief DES data transfer mode config
+*/
+typedef enum {
+    DES_SLAVE_MODE = 0U,         /*slave mode*/
+    DES_DMA_MODE,                /*dma mode*/
+} csi_des_trans_mode_t;
+
+/**
+\brief DES key-len-bits type
+*/
+typedef enum {
+    DES_KEY_LEN_BITS_64        = 0,        /*64 Data bits*/
+    DES_KEY_LEN_BITS_128,                  /*128 Data bits*/
+    DES_KEY_LEN_BITS_192,                  /*192 Data bits*/
+} csi_des_key_bits_t;
+
+typedef enum{
+    DES_MODE_ECB    = 0x00000000,
+    DES_MODE_CBC    = 0x20000020,
+    TDES_MODE_ECB   = 0x00000008,
+    TDES_MODE_CBC   = 0x20000028,
+} des_mode_t;
+
+
+#define DES_KEY_LEN_BYTES_32    (32)
+#define DES_KEY_LEN_BYTES_16    (16)
+#define DES_KEY_LEN_BYTES_24    (24)
+#define DES_KEY_LEN_BYTES_8     (8)
+
+#define DES_BLOCK_IV_SIZE       (8)
+#define DES_BLOCK_CRYPTO_SIZE   (8)
+#define TDES_BLOCK_CRYPTO_SIZE  (16)
+
+#define DES_DIR_ENCRYPT         (1)
+#define DES_DIR_DECRYPT         (0)
+
+#define DES_KEY_128_BITS        (0x8)
+#define DES_KEY_192_BITS        (0x10)
+
+/**
+\brief DES State
+*/
+typedef struct {
+    uint32_t busy             : 1;        /*Calculate busy flag*/
+    uint32_t error            : 1;        /*Calculate error flag*/
+} csi_des_state_t;
+
+/**
+\brief DES Context
+*/
+typedef struct {
+    uint32_t            key_len_byte;
+    uint8_t             key[32];          /*Data block being processed*/
+    uint32_t            sca;
+    uint32_t            is_kdf;
+    uint32_t            is_dma;
+} csi_des_context_t;
+
+/**
+\brief DES Ctrl Block
+*/
+typedef struct {
+    csi_des_state_t         state;
+    csi_des_context_t       context;
+    csi_dev_t               dev;
+    void                    *priv;
+} csi_des_t;
+
+/**
+  \brief       Initialize DES interface. Initializes the resources needed for the DES interface
+  \param[in]   des    Handle to operate
+  \param[in]   idx    Device id
+  \return      Error code \ref csi_error_t
+*/
+csi_error_t csi_des_init(csi_des_t *des, uint32_t idx);
+
+/**
+  \brief       De-initialize DES interface. Stops operation and releases the software resources used by the interface
+  \param[in]   des    Dandle to operate
+  \return      None
+*/
+void csi_des_uninit(csi_des_t *des);
+
+/**
+  \brief       Set encrypt key
+  \param[in]   des        Handle to operate
+  \param[in]   key        Pointer to the key buf
+  \param[in]   key_len    Pointer to \ref csi_des_key_bits_t
+  \return      Error code \ref Csi_error_t
+*/
+csi_error_t csi_des_set_encrypt_key(csi_des_t *des, void *key, csi_des_key_bits_t key_len);
+
+/**
+  \brief       Set decrypt key
+  \param[in]   des        Handle to operate
+  \param[in]   key        Pointer to the key buf
+  \param[in]   key_len    Pointer to \ref csi_des_key_bits_t
+  \return      Error code \ref Csi_error_t
+*/
+csi_error_t csi_des_set_decrypt_key(csi_des_t *des, void *key, csi_des_key_bits_t key_len);
+
+/**
+  \brief       DES ecb encrypt
+  \param[in]   des     Handle to operate
+  \param[in]   in      Pointer to the source data
+  \param[out]  out     Pointer to the result data
+  \param[in]   size    The source data size
+  \return      Error code \ref Csi_error_t
+*/
+csi_error_t csi_des_ecb_encrypt(csi_des_t *des, void *in, void *out, uint32_t size);
+
+/**
+  \brief       DES ecb decrypt
+  \param[in]   des     Handle to operate
+  \param[in]   in      Pointer to the source data
+  \param[out]  out     Pointer to the result data
+  \param[in]   size    The source data size
+  \return      Error code \ref Csi_error_t
+*/
+csi_error_t csi_des_ecb_decrypt(csi_des_t *des, void *in, void *out, uint32_t size);
+
+/**
+  \brief       DES cbc encrypt
+  \param[in]   des     Handle to operate
+  \param[in]   in      Pointer to the source data
+  \param[out]  out     Pointer to the result data
+  \param[in]   size    The source data size
+  \param[in]   iv      Init vector
+  \return      Error code \ref Csi_error_t
+*/
+csi_error_t csi_des_cbc_encrypt(csi_des_t *des, void *in, void *out, uint32_t size, void *iv) ;
+
+/**
+  \brief       DES cbc decrypt
+  \param[in]   des     Handle to operate
+  \param[in]   in      Pointer to the source data
+  \param[out]  out     Pointer to the result data
+  \param[in]   size    The source data size
+  \param[in]   iv      Init vector
+  \return      Error code \ref Csi_error_t
+*/
+csi_error_t csi_des_cbc_decrypt(csi_des_t *des, void *in, void *out, uint32_t size, void *iv);
+
+/**
+  \brief       TDES ecb encrypt
+  \param[in]   des     Handle to operate
+  \param[in]   in      Pointer to the source data
+  \param[out]  out     Pointer to the result data
+  \param[in]   size    The source data size
+  \return      Error code \ref Csi_error_t
+*/
+csi_error_t csi_tdes_ecb_encrypt(csi_des_t *des, void *in, void *out, uint32_t size);
+
+/**
+  \brief       TDES ecb decrypt
+  \param[in]   des     Handle to operate
+  \param[in]   in      Pointer to the source data
+  \param[out]  out     Pointer to the result data
+  \param[in]   size    The source data size
+  \return      Error code \ref Csi_error_t
+*/
+csi_error_t csi_tdes_ecb_decrypt(csi_des_t *des, void *in, void *out, uint32_t size);
+
+/**
+  \brief       TDES cbc encrypt
+  \param[in]   des     Handle to operate
+  \param[in]   in      Pointer to the source data
+  \param[out]  out     Pointer to the result data
+  \param[in]   size    The source data size
+  \param[in]   iv      Init vector
+  \return      Error code \ref Csi_error_t
+*/
+csi_error_t csi_tdes_cbc_encrypt(csi_des_t *des, void *in, void *out, uint32_t size, void *iv) ;
+
+/**
+  \brief       TDES cbc decrypt
+  \param[in]   des     Handle to operate
+  \param[in]   in      Pointer to the source data
+  \param[out]  out     Pointer to the result data
+  \param[in]   size    The source data size
+  \param[in]   iv      Init vector
+  \return      Error code \ref Csi_error_t
+*/
+csi_error_t csi_tdes_cbc_decrypt(csi_des_t *des, void *in, void *out, uint32_t size, void *iv);
+
+/**
+  \brief       Config DES mode dma or slave
+  \param[in]   mode    \ref csi_des_trans_mode_t 
+  \return      None
+*/
+csi_error_t csi_des_trans_config(csi_des_t *des, csi_des_trans_mode_t mode);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _DRV_AES_H_ */

lib/sec_library/include/dev_tag.h

@@ -0,0 +1,87 @@
+/*
+ * Copyright (C) 2017-2020 Alibaba Group Holding Limited
+ */
+
+/******************************************************************************
+ * @file     drv/dev_tag.h
+ * @brief    Header File for DEV TAG Driver
+ * @version  V1.0
+ * @date     31. March 2020
+ * @model    common
+ ******************************************************************************/
+
+#ifndef _DRV_DEV_TAG_H_
+#define _DRV_DEV_TAG_H_
+
+#include <stdint.h>
+#include <stdio.h>
+#include <string.h>
+#include <stdbool.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+    DEV_BLANK_TAG = 0U,
+    DEV_DW_UART_TAG,
+    DEV_DW_DMA_TAG,
+    DEV_DW_GPIO_TAG,
+    DEV_DW_IIC_TAG,
+    DEV_DW_QSPI_TAG,
+    DEV_DW_SDMMC_TAG,
+    DEV_DW_SDHCI_TAG,
+    DEV_DW_SPI_TAG,
+    DEV_DW_TIMER_TAG,
+    DEV_DW_WDT_TAG,
+    DEV_WJ_ADC_TAG,
+    DEV_WJ_AES_TAG,
+    DEV_WJ_CODEC_TAG,
+    DEV_WJ_CRC_TAG,
+    DEV_WJ_DMA_TAG,
+    DEV_WJ_EFLASH_TAG,
+    DEV_WJ_EFUSE_TAG,
+    DEV_WJ_ETB_TAG,
+    DEV_WJ_FFT_TAG,
+    DEV_WJ_I2S_TAG,
+    DEV_WJ_MBOX_TAG,
+    DEV_WJ_PADREG_TAG,
+    DEV_WJ_PDM_TAG,
+    DEV_WJ_PINMUX_TAG,
+    DEV_WJ_PMU_TAG,
+    DEV_WJ_PWM_TAG,
+    DEV_WJ_PWMR_TAG,
+    DEV_WJ_RNG_TAG,
+    DEV_WJ_ROM_TAG,
+    DEV_WJ_RSA_TAG,
+    DEV_WJ_RTC_TAG,
+    DEV_WJ_SASC_TAG,
+    DEV_WJ_SHA_TAG,
+    DEV_WJ_SPDIF_TAG,
+    DEV_WJ_SPIDF_TAG,
+    DEV_WJ_TDM_TAG,
+    DEV_WJ_TIPC_TAG,
+    DEV_WJ_USB_TAG,
+    DEV_WJ_USI_TAG,
+    DEV_WJ_VAD_TAG,
+    DEV_CD_QSPI_TAG,
+    DEV_DCD_ISO7816_TAG,
+    DEV_OSR_RNG_TAG,
+    DEV_QX_RTC_TAG,
+    DEV_RCHBAND_CODEC_TAG,
+    DEV_CMSDK_UART_TAG,
+    DEV_RAMBUS_150B_PKA_TAG,
+    DEV_RAMBUS_150B_TRNG_TAG,
+    DEV_RAMBUS_120SI_TAG,
+    DEV_RAMBUS_120SII_TAG,
+    DEV_RAMBUS_120SIII_TAG,
+	DEV_WJ_AVFS_TAG,
+    DEV_WJ_BMU_TAG,
+} csi_dev_tag_t;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _DRV_TAG_H_ */
+

lib/sec_library/include/device_types.h

@@ -0,0 +1,73 @@
+/*
+ * Copyright (C) 2017-2020 Alibaba Group Holding Limited
+ */
+/* device_types.h
+ *
+ * Driver Framework, Device API, Type Definitions
+ *
+ * The document "Driver Framework Porting Guide" contains the detailed
+ * specification of this API. The information contained in this header file
+ * is for reference only.
+ */
+
+
+
+#ifndef INCLUDE_GUARD_DEVICE_TYPES_H
+#define INCLUDE_GUARD_DEVICE_TYPES_H
+
+/*----------------------------------------------------------------------------
+ * Device_Handle_t
+ *
+ * This handle represents a device, typically one hardware block instance.
+ *
+ * The Device API can access the static device resources (registers and RAM
+ * inside the device) using offsets inside the device. This abstracts memory
+ * map knowledge and simplifies device instantiation.
+ *
+ * Each device has its own configuration, including the endianness swapping
+ * need for the words transferred. Endianness swapping can thus be performed
+ * on the fly and transparent to the caller.
+ *
+ * The details of the handle are implementation specific and must not be
+ * relied on, with one exception: NULL is guaranteed to be a non-existing
+ * handle.
+ */
+
+
+
+typedef void * Device_Handle_t;
+
+
+/*----------------------------------------------------------------------------
+ * Device_Reference_t
+ *
+ * This is an implementation-specific reference for the device. It can
+ * be passed from the implementation of the Device API to other modules
+ * for use, for example, with OS services that require such a reference.
+ *
+ * The details of the handle are implementation specific and must not be
+ * relied on, with one exception: NULL is guaranteed to be a non-existing
+ * handle.
+ */
+typedef void * Device_Reference_t;
+
+
+/*----------------------------------------------------------------------------
+ * Device_Data_t
+ *
+ * This is an implementation-specific reference for the device. It can
+ * be passed from the implementation of the Device API to other modules
+ * for use, for example, with OS services that require such a reference.
+ */
+typedef struct
+{
+    // Physical address of the device mapped in memory
+    void * PhysAddr;
+
+} Device_Data_t;
+
+
+#endif /* Include Guard */
+
+
+/* end of file device_types.h */

lib/sec_library/include/dsa.h

@@ -0,0 +1,178 @@
+/*
+ * Copyright (C) 2017-2022 Alibaba Group Holding Limited
+ */
+
+/******************************************************************************
+ * @file       drv/ecc.h
+ * @brief      Header File for ECC Driver
+ * @version    V3.3
+ * @date       30. May 2022
+ * @model      ECC
+ ******************************************************************************/
+
+#ifndef _DRV_DSA_H_
+#define _DRV_DSA_H_
+
+#include <stdint.h>
+#include "common.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+#define CSI_DSA_SHA1_PUBKEY_LEN        (128)
+#define CSI_DSA_SHA1_PRIVKEY_LEN       (20)
+#define CSI_DSA_SHA1_RK_LEN            (20) /*random*/
+#define CSI_DSA_SHA1_SIGNATURE_LEN     (40)
+#define CSI_DSA_SHA1_DIGEST_LEN        (20)
+
+#define CSI_DSA_SHA256_PUBKEY_LEN      (256)
+#define CSI_DSA_SHA256_PRIVKEY_LEN     (32)
+#define CSI_DSA_SHA256_RK_LEN          (32) /*random*/
+#define CSI_DSA_SHA256_SIGNATURE_LEN   (64)
+#define CSI_DSA_SHA256_DIGEST_LEN      (32)
+
+#define CSI_DSA_SHA224_PUBKEY_LEN      (256)
+#define CSI_DSA_SHA224_PRIVKEY_LEN     (28)
+#define CSI_DSA_SHA224_RK_LEN          (28) /*random*/
+#define CSI_DSA_SHA224_SIGNATURE_LEN   (56)
+#define CSI_DSA_SHA224_DIGEST_LEN      (28)
+
+#define CSI_DSA_SHA1_SHIFT_BYTES          (1*4)
+#define CSI_DSA_SHA224_SHIFT_BYTES        (1*4)
+
+#define DSA_SHA1_GROUP_P_G_BYTES          (128)
+#define DSA_SHA1_GROUP_PARAM_WORDS        (76)
+#define DSA_SHA1_GROUP_N_BYTES            (20)
+#define DSA_SHA1_A_LEN_WORDS              (0x20)
+#define DSA_SHA1_B_LEN_WORDS              (0x05)
+
+#define DSA_SHA256_GROUP_P_G_BYTES        (256)
+#define DSA_SHA256_GROUP_PARAM_WORDS      (140)
+#define DSA_SHA256_GROUP_N_BYTES          (32)
+#define DSA_SHA256_A_LEN_WORDS            (0x40)
+#define DSA_SHA256_B_LEN_WORDS            (0x08)
+
+#define DSA_SHA224_GROUP_P_G_BYTES        (256)
+#define DSA_SHA224_GROUP_PARAM_WORDS      (140)
+#define DSA_SHA224_GROUP_N_BYTES          (28)
+#define DSA_SHA224_A_LEN_WORDS            (0x40)
+#define DSA_SHA224_B_LEN_WORDS            (0x07)
+
+
+/**
+\brief DSA sha type
+*/
+typedef enum {
+    DSA_SHA1   = 0,
+    DSA_SHA224,
+    DSA_SHA256,
+    DSA_SHA_TYPE_MAX,
+} dsa_sha_type;
+
+/**
+\brief DSA group param
+*/
+typedef struct {
+    dsa_sha_type  type;
+    uint32_t      *group;
+    uint32_t      words;
+    uint32_t      offset;
+} csi_dsa_group_t;
+
+/**
+\brief DSA g param
+*/
+typedef struct {
+    dsa_sha_type  type;
+    uint8_t       *p;
+    uint8_t       *g;
+    uint8_t       *n;
+} csi_dsa_gpn_t;
+
+typedef enum{
+    CSI_DSA_SHA1_SIGN = 0,
+    CSI_DSA_SHA1_VERIFY,
+    CSI_DSA_SHA224_SIGN,
+    CSI_DSA_SHA224_VERIFY,
+    CSI_DSA_SHA256_SIGN,
+    CSI_DSA_SHA256_VERIFY,
+    CSI_DSA_FUN_MAX,
+}dsa_fun_type;
+
+typedef struct {
+  dsa_fun_type    type;
+  uint32_t        dsa_pka_a_offset;
+  uint32_t        dsa_pka_b_offset;
+  uint32_t        dsa_pka_c_offset;
+  uint32_t        dsa_pka_d_offset;
+  uint32_t        dsa_pka_r_offset;
+  uint32_t        dsa_pka_s_offset;
+  uint32_t        dsa_pka_function;
+  uint32_t        dsa_pka_A_len;
+  uint32_t        dsa_pka_B_len;
+} csi_dsa_pka_offset_t;
+
+/**
+\brief ECC handle
+*/
+typedef struct {
+    csi_dev_t       dev;
+    dsa_sha_type    sha_type;
+} csi_dsa_t;
+
+/**
+  \brief       Initialize ECC.
+  \param[in]   idx  device id
+  \return      Error code \ref csi_error_t
+*/
+csi_error_t csi_dsa_init(csi_dsa_t *dsa, uint32_t idx);
+
+/**
+  \brief       De-initialize ECC Interface. stops operation and releases the software resources used by the interface
+  \param[in]   ecc  ecc handle to operate.
+  \return      none
+*/
+void csi_dsa_uninit(csi_dsa_t *dsa);
+
+/**
+  \brief       config dsa sha type
+  \param[in]   ecc  ECC handle to operate.
+  \param[in]   type  \ref dsa_sha_type.
+*/
+csi_error_t csi_dsa_config(csi_dsa_t *dsa, dsa_sha_type type);
+/**
+  \brief       dsa gen key pairs
+  \param[in]   ecc      dsa handle to operate.
+  \param[out]  privkey  Pointer to the private key
+  \param[out]  pubkey   Pointer to the public key
+  \return      Error code \ref csi_error_t
+*/
+csi_error_t csi_dsa_gen_keypairs(csi_dsa_t *dsa, uint8_t *prikey, uint8_t *pubkey);
+
+/**
+  \brief       dsa sign
+  \param[in]   ecc      dsa handle to operate.
+  \param[in]   d        Pointer to the digest.
+  \param[out]  privkey  Pointer to the private key
+  \param[out]  s        Pointer to the signature
+  \return      Error code \ref csi_error_t
+*/
+csi_error_t csi_dsa_sign(csi_dsa_t *dsa, uint8_t *d, uint8_t *prikey, uint8_t *s);
+
+/**
+  \brief       dsa verify
+  \param[in]   ecc      ecc handle to operate.
+  \param[in]   d        Pointer to the digest.
+  \param[out]  privkey  Pointer to the private key
+  \param[out]  s        Pointer to the signature
+  \return      verify result 
+*/
+bool csi_dsa_verify(csi_dsa_t *dsa, uint8_t *d, uint8_t *pubkey, uint8_t *s);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

lib/sec_library/include/ecc.h

@@ -0,0 +1,306 @@
+/*
+ * Copyright (C) 2017-2022 Alibaba Group Holding Limited
+ */
+
+/******************************************************************************
+ * @file       drv/ecc.h
+ * @brief      Header File for ECC Driver
+ * @version    V3.3
+ * @date       30. May 2022
+ * @model      ECC
+ ******************************************************************************/
+
+#ifndef _DRV_ECC_H_
+#define _DRV_ECC_H_
+
+#include <stdint.h>
+#include "common.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define CSI_ECC_PUBKEY_LEN      (65-1)
+#define CSI_ECC_PRIVKEY_LEN     (32)
+#define CSI_ECC_PUBKEYTMP_LEN   (65)
+#define CSI_ECC_RK_LEN          (32) /*random*/
+#define CSI_ECC_SIGNATURE_LEN   (64)
+#define CSI_ECC_DIGEST_LEN      (32)
+
+#define ECC_PRIME_CURVE_G_BYTES (64)
+#define ECC_PRIME_CURVE_P_BYTES (70)
+
+typedef struct {
+    uint32_t ecc_curve : 1; /*supports 256bits curve*/
+} ecc_capabilities_t;
+
+/**
+\brief ECC ciphertext order
+*/
+typedef enum {
+    ECC_C1C3C2 = 0,
+    ECC_C1C2C3,
+} ecc_cipher_order_e;
+
+/**
+\brief ECC endian mode
+*/
+typedef enum {
+    ECC_ENDIAN_LITTLE = 0, /*Little Endian*/
+    ECC_ENDIAN_BIG         /*Big Endian*/
+} ecc_endian_mode_e;
+
+/**
+\brief ECC prime curve type
+*/
+typedef enum {
+    ECC_PRIME256V1 = 0,
+} ecc_prime_curve_type;
+
+/**
+\brief ECC key exchange role
+*/
+typedef enum { ECC_Role_Sponsor = 0, ECC_Role_Responsor } ecc_exchange_role_e;
+
+/****** ECC Event *****/
+typedef enum {
+    ECC_EVENT_MAKE_KEY_COMPLETE = 0, /*Make key completed*/
+    ECC_EVENT_ENCRYPT_COMPLETE,      /*Encrypt completed*/
+    ECC_EVENT_DECRYPT_COMPLETE,      /*Decrypt completed*/
+    ECC_EVENT_SIGN_COMPLETE,         /*Sign completed*/
+    ECC_EVENT_VERIFY_COMPLETE,       /*Verify completed*/
+    ECC_EVENT_EXCHANGE_KEY_COMPLETE, /*Exchange key completed*/
+} ecc_event_e;
+
+/**
+\brief ECC prime curve param
+*/
+typedef struct {
+    ecc_prime_curve_type type;
+    uint32_t *p;
+} csi_ecc_prime_curve_t;
+
+/**
+\brief ECC curve type g param
+*/
+typedef struct {
+    ecc_prime_curve_type type;
+    uint8_t *G;
+    uint8_t *n;
+} csi_ecc_curve_g_t;
+
+/**
+\brief ECC status
+*/
+typedef struct {
+    uint32_t busy : 1; /*Calculate busy flag*/
+} csi_ecc_state_t;
+
+/**
+\brief ECC handle
+*/
+typedef struct {
+    csi_dev_t       dev;
+    void *          cb;
+    void *          arg;
+    csi_ecc_state_t state;
+    ecc_prime_curve_type  type;
+} csi_ecc_t;
+
+/*Pointer to \ref csi_ecc_callback_t : ECC Event call back.*/
+typedef void (*csi_ecc_callback_t)(ecc_event_e event);
+
+/**
+  \brief       Initialize ECC.
+  \param[in]   idx  device id
+  \return      Error code \ref csi_error_t
+*/
+csi_error_t csi_ecc_init(csi_ecc_t *ecc, uint32_t idx);
+
+/**
+  \brief       De-initialize ECC Interface. stops operation and releases the software resources used by the interface
+  \param[in]   ecc  ecc handle to operate.
+  \return      none
+*/
+void csi_ecc_uninit(csi_ecc_t *ecc);
+
+/**
+  \brief       ecc get capability.
+  \param[in]   ecc  Operate handle.
+  \return      Error code \ref csi_error_t
+*/
+csi_error_t csi_ecc_config(csi_ecc_t *ecc, ecc_cipher_order_e co, ecc_endian_mode_e endian);
+
+/**
+  \brief       Attach the callback handler to ECC
+  \param[in]   ecc  Operate handle.
+  \param[in]   cb    Callback function
+  \param[in]   arg   User can define it by himself as callback's param
+  \return      Error code Error code \ref csi_error_t
+*/
+csi_error_t csi_ecc_attach_callback(csi_ecc_t *ecc, csi_ecc_callback_t cb, void *arg);
+
+/**
+  \brief       Detach the callback handler
+  \param[in]   ecc  Operate handle.
+  \return      Error code Error code \ref csi_error_t
+*/
+csi_error_t csi_ecc_detach_callback(csi_ecc_t *ecc);
+
+/**
+  \brief       ecc get capability.
+  \param[in]   ecc  Operate handle.
+  \param[out]  cap  Pointer of ecc_capabilities_t.
+  \return      Error code Error code \ref csi_error_t
+*/
+csi_error_t csi_ecc_get_capabilities(csi_ecc_t *ecc, ecc_capabilities_t *cap);
+
+/**
+  \brief       check whether the public key and private key are a pair.
+  \param[in]   ecc       ecc handle to operate.
+  \param[in]   private   Pointer to the ecc private key, alloc by caller.
+  \param[in]   public    Pointer to the ecc public key, alloc by caller.
+  \return      Error code \ref csi_error_t
+*/
+csi_error_t csi_ecc_check_keypair(csi_ecc_t *ecc, uint8_t pubkey[65], uint8_t prikey[32]);
+
+/**
+  \brief       generate ecc key.
+  \param[in]   ecc       ecc handle to operate.
+  \param[out]  private   Pointer to the ecc private key, alloc by caller.
+  \param[out]  public    Pointer to the ecc public key, alloc by caller.
+  \return      Error code \ref csi_error_t
+*/
+csi_error_t csi_ecc_gen_key(csi_ecc_t *ecc, uint8_t pubkey[65], uint8_t prikey[32]);
+
+/**
+  \brief       generate ecc public key by private key.
+  \param[in]   ecc       ecc handle to operate.
+  \param[out]  private   Pointer to the ecc private key, alloc by caller.
+  \param[out]  public    Pointer to the ecc public key, alloc by caller.
+  \return      Error code \ref csi_error_t
+*/
+csi_error_t csi_ecc_gen_pubkey(csi_ecc_t *ecc, uint8_t pubkey[65], uint8_t prikey[32]);
+
+/**
+  \brief       ecc sign
+  \param[in]   ecc      ecc handle to operate.
+  \param[in]   d        Pointer to the digest.
+  \param[out]  privkey  Pointer to the private key
+  \param[out]  s        Pointer to the signature
+  \return      Error code \ref csi_error_t
+*/
+csi_error_t csi_ecc_sign(csi_ecc_t *ecc, uint8_t d[32], uint8_t prikey[32], uint8_t s[64]);
+
+/**
+  \brief       ecc sign asybnc
+  \param[in]   ecc      ecc handle to operate.
+  \param[in]   d        Pointer to the digest.
+  \param[out]  privkey  Pointer to the private key
+  \param[out]  s        Pointer to the signature
+  \return      Error code \ref csi_error_t
+*/
+csi_error_t csi_ecc_sign_async(csi_ecc_t *ecc, uint8_t d[32], uint8_t prikey[32], uint8_t s[64]);
+
+/* TODO */
+/**
+  \brief       ecc verify
+  \param[in]   ecc      ecc handle to operate.
+  \param[in]   d        Pointer to the digest.
+  \param[out]  privkey  Pointer to the private key
+  \param[out]  s        Pointer to the signature
+  \return      verify result 
+*/
+bool csi_ecc_verify(csi_ecc_t *ecc, uint8_t d[32], uint8_t pubkey[65], uint8_t s[64]);
+
+/**
+  \brief       ecc verify
+  \param[in]   ecc      ecc handle to operate.
+  \param[in]   d        Pointer to the digest.
+  \param[out]  privkey  Pointer to the private key
+  \param[out]  s        Pointer to the signature
+  \return      verify result
+*/
+bool csi_ecc_verify_async(csi_ecc_t *ecc, uint8_t d[32], uint8_t pubkey[65], uint8_t s[64]);
+
+/**
+  \brief       ecc encrypto
+  \param[in]   ecc              ecc handle to operate.
+  \param[in]   Plain            Pointer to the plaintext.
+  \param[in]   PlainByteLen     plaintext len
+  \param[in]   pubKey           public key.
+  \param[out]  Cipher           Pointer to the chipher
+  \param[out]  CipherByteLen    Pointer to the chipher len.
+  \return      Error code \ref csi_error_t
+*/
+csi_error_t csi_ecc_encrypt(csi_ecc_t *ecc, uint8_t *Plain,
+                            uint32_t PlainByteLen, uint8_t pubKey[65],
+                            uint8_t *Cipher, uint32_t *CipherByteLen);
+
+/**
+  \brief       ecc encrypto
+  \param[in]   ecc              ecc handle to operate.
+  \param[in]   Cipher           Pointer to the chipher
+  \param[in]   CipherByteLen    chipher len.
+  \param[in]   prikey           private key.
+  \param[out]  Plain            Pointer to the plaintext.
+  \param[out]  PlainByteLen     plaintext len
+  \return      Error code \ref csi_error_t
+*/
+csi_error_t csi_ecc_decrypt(csi_ecc_t *ecc, uint8_t *Cipher,
+                            uint32_t CipherByteLen, uint8_t prikey[32],
+                            uint8_t *Plain, uint32_t *PlainByteLen);
+
+/**
+  \brief       ecc key exchange
+  \param[in]   ecc       ecc handle to operate.
+  \return      Error code \ref csi_error_t
+*/
+csi_error_t csi_ecc_exchangekey(csi_ecc_t *ecc, ecc_exchange_role_e role,
+                                uint8_t *dA, uint8_t *PB, uint8_t *rA,
+                                uint8_t *RA, uint8_t *RB, uint8_t *ZA,
+                                uint8_t *ZB, uint32_t kByteLen, uint8_t *KA,
+                                uint8_t *S1, uint8_t *SA);
+
+/**
+  \brief       ecc key exchange get Z.
+  \param[in]   ecc       ecc handle to operate.
+  \return      Error code Error code \ref csi_error_t
+*/
+csi_error_t csi_ecc_getZ(csi_ecc_t *ecc, uint8_t *ID, uint32_t byteLenofID,
+                         uint8_t pubKey[65], uint8_t Z[32]);
+
+/**
+  \brief       ecc key exchange get E
+  \param[in]   ecc       ecc handle to operate.
+  \return      Error code Error code \ref csi_error_t
+*/
+csi_error_t csi_ecc_getE(csi_ecc_t *ecc, uint8_t *M, uint32_t byteLen,
+                         uint8_t Z[32], uint8_t E[32]);
+
+/**
+  \brief       Get ECC state.
+  \param[in]   ecc      ECC handle to operate.
+  \param[out]  state    ECC state \ref csi_ecc_state_t.
+  \return      Error code Error code \ref csi_error_t
+*/
+csi_error_t csi_ecc_get_state(csi_ecc_t *ecc, csi_ecc_state_t *state);
+
+/**
+  \brief       Enable ecc power manage
+  \param[in]   ecc  ECC handle to operate.
+  \return      Error code Error code \ref csi_error_t
+*/
+csi_error_t csi_ecc_enable_pm(csi_ecc_t *ecc);
+
+/**
+  \brief       Disable ecc power manage
+  \param[in]   ecc  ECC handle to operate.
+*/
+void csi_ecc_disable_pm(csi_ecc_t *ecc);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

lib/sec_library/include/ecdh.h

@@ -0,0 +1,43 @@
+/*
+ * Copyright (C) 2017-2022 Alibaba Group Holding Limited
+ */
+
+/******************************************************************************
+ * @file       drv/ecdh.h
+ * @brief      Header File for ECDH Driver
+ * @version    V3.3
+ * @date       10.June 2022
+ * @model      ECC
+ ******************************************************************************/
+
+#ifndef _DRV_ECDH_H_
+#define _DRV_ECDH_H_
+
+#include <stdint.h>
+#include "common.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define CSI_ECDH_PUBKEY_LEN   (65-1)
+#define CSI_ECDH_PRIVKEY_LEN  (32)
+#define CSI_ECDH_SHARE_LEN    (64)
+#define CSI_ECDH_SHAREKEY_LEN (32)
+
+/**
+  \brief       ecdh cacl share secret
+  \param[in]  ecc       ecc handle to operate.
+  \param[in]  pubkey    Pointer to the A public key.
+  \param[in]  prikey    Pointer to the B private key.
+  \param[out] shareKey  Pointer to the share secret.
+  \param[out] len       length of the share secret.
+  \return     Error code \ref csi_error_t
+*/
+csi_error_t csi_ecdh_calc_secret(csi_ecc_t *ecc, uint8_t privkey[32], uint8_t pubkey[65], uint8_t shareKey[32], uint32_t *len);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

lib/sec_library/include/kdf.h

@@ -1,12 +1,19 @@
 /*
- * Copyright (C) 2019-2021 Alibaba Group Holding Limited
+ * Copyright (C) 2019-2020 Alibaba Group Holding Limited
  */
 
 #ifndef __KDF_H__
 #define __KDF_H__
+#ifdef SEC_LIB_VERSION
 #include "drv/aes.h"
 #include "drv/sm4.h"
 #include "drv/common.h"
+#else
+#include "aes.h"
+#include "sm4.h"
+#include "common.h"
+#endif
+
 #include <stdint.h>
 
 typedef enum {
@@ -50,6 +57,9 @@ typedef enum {
         KDF_KEY_TYPE_TDES_192,
         KDF_KEY_TYPE_TDES_128,
         KDF_KEY_TYPE_DES,
+	/* for rpmb, str */
+/* 	KDF_KEY_TYPE_HMAC_SHA256,
+ */
         KDF_KEY_TYPE_MAX,
 } csi_kdf_key_type_t;
 
@@ -113,12 +123,12 @@ csi_error_t csi_kdf_destory_key(csi_kdf_t *kdf, csi_kdf_derived_key_t dkey);
 
 /**
   \brief       Set key to algorithim engine.
-  \param[in]   handle    Handle to cipher.
   \param[in]   kdf    Handle to operate.
+  \param[in]   handle    Handle to cipher.
   \param[in]   dkey derived key type.
   \return      error code
 */
-csi_error_t csi_kdf_set_key(csi_kdf_key_handle_t *handle, csi_kdf_t *kdf,
+csi_error_t csi_kdf_set_key(csi_kdf_t *kdf, csi_kdf_key_handle_t *handle,
                             csi_kdf_derived_key_t dkey);
 
 /**
@@ -139,4 +149,11 @@ csi_error_t csi_kdf_clear_key(csi_kdf_t *kdf, csi_kdf_derived_key_t dkey);
 csi_error_t csi_kdf_get_key_attr(csi_kdf_t *kdf, csi_kdf_derived_key_t dkey,
                                  csi_kdf_key_attr_t *attr);
 
+
+/**
+  \brief       kdf generate hmac key.
+  \param[in]   kdf    Handle to operate
+*/
+csi_error_t csi_kdf_gen_hmac_key(uint8_t* key,uint32_t * length);
+
 #endif